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.TH "ABC" "1" "@VERSION@" "ABC" "User Commands"
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.SH "NAME"
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abc \- sequential logic synthesis and formal verification
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.SH "SYNOPSIS"
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.B abc
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[\fIOPTIONS\fP] \fIFILE\fP
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.SH "DESCRIPTION"
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.PP
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ABC is a growing software system for synthesis and verification of binary
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sequential logic circuits appearing in synchronous hardware designs.  ABC
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combines scalable logic optimization based on And-Inverter Graphs (AIGs),
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optimal-delay DAG-based technology mapping for look-up tables and standard
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cells, and innovative algorithms for sequential synthesis and verification.
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.PP
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ABC provides an experimental implementation of these algorithms and a
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programming environment for building similar applications.  Future development
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will focus on improving the algorithms and making most of the packages
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stand-alone.  This will allow the user to customize ABC for their needs as if
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it were a toolbox rather than a complete tool.
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.SH "OPTIONS"
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.TP
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\fB\-c\fP \fICMD\fP
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Execute commands \fICMD\fP.
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.TP
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\fB\-q\fP \fICMD\fP
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Execute commands \fICMD\fP quietly.
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.TP
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\fB\-C\fP \fICMD\fP
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Execute commands \fICMD\fP, then continue in interactive mode.
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.TP
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\fB\-F\fP \fISCRIPT\fP
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Execute commands from script file \fISCRIPT\fP and echo commands.
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.TP
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\fB\-f\fP \fISCRIPT\fP
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Execute commands from script file \fISCRIPT\fP.
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.TP
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\fB\-h\fP
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Print command usage.
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.TP
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\fB\-o\fP \fIFILE\fP
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Store the result in \fIFILE\fP.
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.TP
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\fB\-s\fP
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Do not read any initialization file.
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.TP
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\fB\-t\fP \fITYPE\fP
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Specify the input type, one of \fIblif_mv\fP, \fIblif_mvs\fP, \fIblif\fP, or
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\fInone\fP.  The default is \fIblif_mv\fP.
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.TP
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\fB\-T\fP \fITYPE\fP
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Specify the output type, one of \fIblif_mv\fP, \fIblif_mvs\fP, \fIblif\fP, or
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\fInone\fP.  The default is \fIblif_mv\fP.
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.TP
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\fB\-x\fP
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Equivalent to \fI-t none -T none\fP.
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.TP
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\fB\-b\fP
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Run in bridge mode.
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.SH "INTRODUCTION"
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.PP
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Data structures and algorithms at the heart of a software system determine its
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capabilities in processing data and its efficiency as a programming
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environment for building new applications.  Extensive experience of developing
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and using SIS, VIS, and MVSIS, makes it clear that these systems do not
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provide a flexible programming environment to implement recent innovations,
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such as integration of technology mapping and retiming.  Specifically, the SIS
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environment is outdated and rather inefficient when handling large circuits.
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VIS, designed as a formal verification tool for multi-valued specifications,
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does not provide enough flexibility for binary synthesis.  MVSIS was developed
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and extensively used by us in the recent years for implementing new synthesis
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algorithms for both multi-valued and binary networks.  Finally, we became
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convinced that (a) the basic data structures and algorithms of MVSIS can be
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made considerably simpler and easier to use by assuming binary networks, and
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(b) a central place in the new system should be given to a new data structure,
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AIGs (multi-level logic networks composed of two-input ANDs and inverters),
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which promises improvements in quality and runtime of synthesis and
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verification.
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.PP
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This understanding motivates us to redevelop the core packages of MVSIS
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resulting in a new programming environment named ABC.  As the name suggests,
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the primary goal is to keep data structures simple and flexible for a wide
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range of applications.  The “philosophy of ABC” has several basic premises.
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One of them is allowing for a variety of functional representations, such as
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BDDs and SOPs, to solve specialized tasks, while defaulting to AIGs for the
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mainstream network manipulation.  Representing logic using AIGs leads to a
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remarkable uniformity in computation and efficient interfacing with CNF-based
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SAT solvers for handing Boolean reasoning problems.  Another fundamental
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premise of ABC is the synergy between synthesis and verification using
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efficient SAT-based Boolean reasoning on the AIG for combinational and
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sequential equivalence checking.
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.PP
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The goal of the ABC project is to provide a public-domain implementation of
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the state-of-the-art combinational and sequential synthesis algorithms and, at
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the same time, create an open-source environment, in which such applications
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can be developed and compared.  The current version of ABC can
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optimize/map/retime industrial gate-level designs with 100K gates and 10K
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sequential elements for optimal delay and heuristically minimized area in
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about one minute of CPU time on a modern computer.  The runtime of the
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combinational synthesis, mapping, and verification is typically faster.