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diff --git a/lib/Target/R600/InstPrinter/AMDGPUInstPrinter.cpp b/lib/Target/R600/InstPrinter/AMDGPUInstPrinter.cpp
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index 99e1377..7105879 100644
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--- a/lib/Target/R600/InstPrinter/AMDGPUInstPrinter.cpp
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+++ b/lib/Target/R600/InstPrinter/AMDGPUInstPrinter.cpp
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@@ -316,6 +316,37 @@ void AMDGPUInstPrinter::printKCache(const MCInst *MI, unsigned OpNo,
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   }
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 }
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+void AMDGPUInstPrinter::printSendMsg(const MCInst *MI, unsigned OpNo,
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+                                     raw_ostream &O) {
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+  unsigned SImm16 = MI->getOperand(OpNo).getImm();
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+  unsigned Msg = SImm16 & 0xF;
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+  if (Msg == 2 || Msg == 3) {
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+    unsigned Op = (SImm16 >> 4) & 0xF;
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+    if (Msg == 3)
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+      O << "Gs_done(";
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+    else
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+      O << "Gs(";
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+    if (Op == 0) {
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+      O << "nop";
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+    } else {
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+      unsigned Stream = (SImm16 >> 8) & 0x3;
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+      if (Op == 1)
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+	O << "cut";
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+      else if (Op == 2)
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+	O << "emit";
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+      else if (Op == 3)
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+	O << "emit-cut";
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+      O << " stream " << Stream;
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+    }
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+    O << "), [m0] ";
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+  } else if (Msg == 1)
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+    O << "interrupt ";
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+  else if (Msg == 15)
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+    O << "system ";
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+  else
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+    O << "unknown(" << Msg << ") ";
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+}
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+
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 void AMDGPUInstPrinter::printWaitFlag(const MCInst *MI, unsigned OpNo,
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                                       raw_ostream &O) {
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   // Note: Mask values are taken from SIInsertWaits.cpp and not from ISA docs
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diff --git a/lib/Target/R600/InstPrinter/AMDGPUInstPrinter.h b/lib/Target/R600/InstPrinter/AMDGPUInstPrinter.h
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index 77af942..2876dd2 100644
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--- a/lib/Target/R600/InstPrinter/AMDGPUInstPrinter.h
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+++ b/lib/Target/R600/InstPrinter/AMDGPUInstPrinter.h
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@@ -53,6 +53,7 @@ private:
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   void printRSel(const MCInst *MI, unsigned OpNo, raw_ostream &O);
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   void printCT(const MCInst *MI, unsigned OpNo, raw_ostream &O);
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   void printKCache(const MCInst *MI, unsigned OpNo, raw_ostream &O);
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+  void printSendMsg(const MCInst *MI, unsigned OpNo, raw_ostream &O);
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   void printWaitFlag(const MCInst *MI, unsigned OpNo, raw_ostream &O);
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 };
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diff --git a/lib/Target/R600/SIInsertWaits.cpp b/lib/Target/R600/SIInsertWaits.cpp
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index 7ef662e..695ec40 100644
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--- a/lib/Target/R600/SIInsertWaits.cpp
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+++ b/lib/Target/R600/SIInsertWaits.cpp
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@@ -314,6 +314,12 @@ Counters SIInsertWaits::handleOperands(MachineInstr &MI) {
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   Counters Result = ZeroCounts;
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+  // S_SENDMSG implicitly waits for all outstanding LGKM transfers to finish,
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+  // but we also want to wait for any other outstanding transfers before
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+  // signalling other hardware blocks
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+  if (MI.getOpcode() == AMDGPU::S_SENDMSG)
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+    return LastIssued;
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+
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   // For each register affected by this
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   // instruction increase the result sequence
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   for (unsigned i = 0, e = MI.getNumOperands(); i != e; ++i) {
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diff --git a/lib/Target/R600/SIInstrInfo.td b/lib/Target/R600/SIInstrInfo.td
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index 4cd0daa..19d2171 100644
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--- a/lib/Target/R600/SIInstrInfo.td
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+++ b/lib/Target/R600/SIInstrInfo.td
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@@ -425,26 +425,48 @@ class MTBUF_Store_Helper <bits<3> op, string asm, RegisterClass regClass> : MTBU
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 multiclass MUBUF_Load_Helper <bits<7> op, string asm, RegisterClass regClass> {
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-  let glc = 0, lds = 0, slc = 0, tfe = 0, soffset = 128 /* ZERO */,
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-                                          mayLoad = 1 in {
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-
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-  let offen = 1, idxen = 0, addr64 = 0, offset = 0 in {
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-    def _OFFEN  : MUBUF 
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-                         (ins SReg_128:$srsrc, VReg_32:$vaddr),
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-                         asm#" $vdata, $srsrc + $vaddr", []>;
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-  }
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-
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-  let offen = 0, idxen = 1, addr64 = 0 in {
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-    def _IDXEN  : MUBUF 
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-                         (ins SReg_128:$srsrc, VReg_32:$vaddr, i16imm:$offset),
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-                         asm#" $vdata, $srsrc[$vaddr] + $offset", []>;
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-  }
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+  let lds = 0, mayLoad = 1 in {
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+
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+    let addr64 = 0 in {
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+
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+      let offen = 0, idxen = 0 in {
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+        def _OFFSET : MUBUF 
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+                             (ins SReg_128:$srsrc, VReg_32:$vaddr,
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+                             i16imm:$offset, SSrc_32:$soffset, i1imm:$glc,
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+                             i1imm:$slc, i1imm:$tfe),
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+                             asm#" $vdata, $srsrc + $offset + $soffset, glc=$glc, slc=$slc, tfe=$tfe", []>;
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+      }
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+
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+      let offen = 1, idxen = 0, offset = 0 in {
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+        def _OFFEN  : MUBUF 
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+                             (ins SReg_128:$srsrc, VReg_32:$vaddr,
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+                             SSrc_32:$soffset, i1imm:$glc, i1imm:$slc,
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+                             i1imm:$tfe),
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+                             asm#" $vdata, $srsrc + $vaddr + $soffset, glc=$glc, slc=$slc, tfe=$tfe", []>;
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+      }
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+
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+      let offen = 0, idxen = 1 in {
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+        def _IDXEN  : MUBUF 
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+                             (ins SReg_128:$srsrc, VReg_32:$vaddr,
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+                             i16imm:$offset, SSrc_32:$soffset, i1imm:$glc,
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+                             i1imm:$slc, i1imm:$tfe),
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+                             asm#" $vdata, $srsrc[$vaddr] + $offset + $soffset, glc=$glc, slc=$slc, tfe=$tfe", []>;
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+      }
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+
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+      let offen = 1, idxen = 1 in {
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+        def _BOTHEN : MUBUF 
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+                             (ins SReg_128:$srsrc, VReg_64:$vaddr,
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+                             SSrc_32:$soffset, i1imm:$glc,
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+                             i1imm:$slc, i1imm:$tfe),
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+                             asm#" $vdata, $srsrc[$vaddr[0]] + $vaddr[1] + $soffset, glc=$glc, slc=$slc, tfe=$tfe", []>;
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+      }
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+    }
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-  let offen = 0, idxen = 0, addr64 = 1 in {
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-    def _ADDR64 : MUBUF 
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-                         (ins SReg_128:$srsrc, VReg_64:$vaddr, i16imm:$offset),
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-                         asm#" $vdata, $srsrc + $vaddr + $offset", []>;
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-  }
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+    let offen = 0, idxen = 0, addr64 = 1, glc = 0, slc = 0, tfe = 0, soffset = 128 /* ZERO */ in {
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+      def _ADDR64 : MUBUF 
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+                           (ins SReg_128:$srsrc, VReg_64:$vaddr, i16imm:$offset),
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+                           asm#" $vdata, $srsrc + $vaddr + $offset", []>;
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+    }
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   }
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 }
3f23b32
 
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diff --git a/lib/Target/R600/SIInstructions.td b/lib/Target/R600/SIInstructions.td
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index 76f05eb..9acb9b6 100644
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--- a/lib/Target/R600/SIInstructions.td
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+++ b/lib/Target/R600/SIInstructions.td
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@@ -22,6 +22,10 @@ def InterpSlot : Operand<i32> {
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   let PrintMethod = "printInterpSlot";
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 }
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+def SendMsgImm : Operand<i32> {
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+  let PrintMethod = "printSendMsg";
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+}
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+
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 def isSI : Predicate<"Subtarget.getGeneration() "
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                       ">= AMDGPUSubtarget::SOUTHERN_ISLANDS">;
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@@ -826,17 +830,25 @@ def S_BARRIER : SOPP <0x0000000a, (ins), "S_BARRIER",
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 def S_WAITCNT : SOPP <0x0000000c, (ins WAIT_FLAG:$simm16), "S_WAITCNT $simm16",
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   []
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 >;
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-} // End hasSideEffects
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 //def S_SETHALT : SOPP_ <0x0000000d, "S_SETHALT", []>;
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 //def S_SLEEP : SOPP_ <0x0000000e, "S_SLEEP", []>;
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 //def S_SETPRIO : SOPP_ <0x0000000f, "S_SETPRIO", []>;
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-//def S_SENDMSG : SOPP_ <0x00000010, "S_SENDMSG", []>;
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+
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+let Uses = [EXEC] in {
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+  def S_SENDMSG : SOPP <0x00000010, (ins SendMsgImm:$simm16, M0Reg:$m0), "S_SENDMSG $simm16",
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+      [(int_SI_sendmsg imm:$simm16, M0Reg:$m0)]
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+  > {
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+    let DisableEncoding = "$m0";
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+  }
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+} // End Uses = [EXEC]
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+
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 //def S_SENDMSGHALT : SOPP_ <0x00000011, "S_SENDMSGHALT", []>;
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 //def S_TRAP : SOPP_ <0x00000012, "S_TRAP", []>;
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 //def S_ICACHE_INV : SOPP_ <0x00000013, "S_ICACHE_INV", []>;
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 //def S_INCPERFLEVEL : SOPP_ <0x00000014, "S_INCPERFLEVEL", []>;
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 //def S_DECPERFLEVEL : SOPP_ <0x00000015, "S_DECPERFLEVEL", []>;
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 //def S_TTRACEDATA : SOPP_ <0x00000016, "S_TTRACEDATA", []>;
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+} // End hasSideEffects
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 def V_CNDMASK_B32_e32 : VOP2 <0x00000000, (outs VReg_32:$dst),
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   (ins VSrc_32:$src0, VReg_32:$src1, VCCReg:$vcc),
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@@ -1305,8 +1317,8 @@ def SI_END_CF : InstSI <
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 def SI_KILL : InstSI <
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   (outs),
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-  (ins VReg_32:$src),
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-  "SI_KIL $src",
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+  (ins VSrc_32:$src),
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+  "SI_KILL $src",
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   [(int_AMDGPU_kill f32:$src)]
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 >;
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@@ -1397,13 +1409,13 @@ def : Pat<
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 def : Pat <
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   (int_AMDGPU_kilp),
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-  (SI_KILL (V_MOV_B32_e32 0xbf800000))
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+  (SI_KILL 0xbf800000)
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 >;
3f23b32
 
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 /* int_SI_vs_load_input */
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 def : Pat<
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   (SIload_input i128:$tlst, IMM12bit:$attr_offset, i32:$buf_idx_vgpr),
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-  (BUFFER_LOAD_FORMAT_XYZW_IDXEN $tlst, $buf_idx_vgpr, imm:$attr_offset)
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+  (BUFFER_LOAD_FORMAT_XYZW_IDXEN $tlst, $buf_idx_vgpr, imm:$attr_offset, 0, 0, 0, 0)
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 >;
3f23b32
 
3f23b32
 /* int_SI_export */
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@@ -1809,7 +1821,7 @@ def : Pat <
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 // 3. Offset in an 32Bit VGPR
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 def : Pat <
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   (SIload_constant i128:$sbase, i32:$voff),
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-  (BUFFER_LOAD_DWORD_OFFEN $sbase, $voff)
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+  (BUFFER_LOAD_DWORD_OFFEN $sbase, $voff, 0, 0, 0, 0)
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 >;
3f23b32
 
3f23b32
 // The multiplication scales from [0,1] to the unsigned integer range
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@@ -1970,6 +1982,50 @@ defm : MUBUFStore_Pattern <BUFFER_STORE_DWORDX2, i64, global_store>;
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 defm : MUBUFStore_Pattern <BUFFER_STORE_DWORDX2, v2i32, global_store>;
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 defm : MUBUFStore_Pattern <BUFFER_STORE_DWORDX4, v4i32, global_store>;
3f23b32
 
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+// BUFFER_LOAD_DWORD*, addr64=0
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+multiclass MUBUF_Load_Dword 
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+                             MUBUF bothen> {
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+
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+  def : Pat <
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+    (vt (int_SI_buffer_load_dword i128:$rsrc, i32:$vaddr, i32:$soffset,
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+                                  imm:$offset, 0, 0, imm:$glc, imm:$slc,
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+                                  imm:$tfe)),
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+    (offset $rsrc, $vaddr, (as_i16imm $offset), $soffset, (as_i1imm $glc),
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+            (as_i1imm $slc), (as_i1imm $tfe))
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+  >;
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+
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+  def : Pat <
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+    (vt (int_SI_buffer_load_dword i128:$rsrc, i32:$vaddr, i32:$soffset,
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+                                  imm, 1, 0, imm:$glc, imm:$slc,
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+                                  imm:$tfe)),
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+    (offen $rsrc, $vaddr, $soffset, (as_i1imm $glc), (as_i1imm $slc),
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+           (as_i1imm $tfe))
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+  >;
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+
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+  def : Pat <
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+    (vt (int_SI_buffer_load_dword i128:$rsrc, i32:$vaddr, i32:$soffset,
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+                                  imm:$offset, 0, 1, imm:$glc, imm:$slc,
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+                                  imm:$tfe)),
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+    (idxen $rsrc, $vaddr, (as_i16imm $offset), $soffset, (as_i1imm $glc),
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+           (as_i1imm $slc), (as_i1imm $tfe))
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+  >;
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+
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+  def : Pat <
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+    (vt (int_SI_buffer_load_dword i128:$rsrc, v2i32:$vaddr, i32:$soffset,
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+                                  imm, 1, 1, imm:$glc, imm:$slc,
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+                                  imm:$tfe)),
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+    (bothen $rsrc, $vaddr, $soffset, (as_i1imm $glc), (as_i1imm $slc),
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+            (as_i1imm $tfe))
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+  >;
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+}
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+
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+defm : MUBUF_Load_Dword 
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+                         BUFFER_LOAD_DWORD_IDXEN, BUFFER_LOAD_DWORD_BOTHEN>;
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+defm : MUBUF_Load_Dword 
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+                         BUFFER_LOAD_DWORDX2_IDXEN, BUFFER_LOAD_DWORDX2_BOTHEN>;
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+defm : MUBUF_Load_Dword 
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+                         BUFFER_LOAD_DWORDX4_IDXEN, BUFFER_LOAD_DWORDX4_BOTHEN>;
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+
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 //===----------------------------------------------------------------------===//
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 // MTBUF Patterns
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 //===----------------------------------------------------------------------===//
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diff --git a/lib/Target/R600/SIIntrinsics.td b/lib/Target/R600/SIIntrinsics.td
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index 7fcc964..00e32c0 100644
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--- a/lib/Target/R600/SIIntrinsics.td
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+++ b/lib/Target/R600/SIIntrinsics.td
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@@ -38,6 +38,22 @@ let TargetPrefix = "SI", isTarget = 1 in {
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      llvm_i32_ty],   // tfe(imm)
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     []>;
3f23b32
 
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+  // Fully-flexible BUFFER_LOAD_DWORD_* except for the ADDR64 bit, which is not exposed
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+  def int_SI_buffer_load_dword : Intrinsic <
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+    [llvm_anyint_ty], // vdata(VGPR), overloaded for types i32, v2i32, v4i32
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+    [llvm_anyint_ty,  // rsrc(SGPR)
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+     llvm_anyint_ty,  // vaddr(VGPR)
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+     llvm_i32_ty,     // soffset(SGPR)
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+     llvm_i32_ty,     // inst_offset(imm)
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+     llvm_i32_ty,     // offen(imm)
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+     llvm_i32_ty,     // idxen(imm)
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+     llvm_i32_ty,     // glc(imm)
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+     llvm_i32_ty,     // slc(imm)
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+     llvm_i32_ty],    // tfe(imm)
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+    [IntrReadArgMem]>;
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+
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+  def int_SI_sendmsg : Intrinsic <[], [llvm_i32_ty, llvm_i32_ty], [IntrNoMem]>;
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+
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   class Sample : Intrinsic <[llvm_v4f32_ty], [llvm_anyvector_ty, llvm_v32i8_ty, llvm_anyint_ty, llvm_i32_ty], [IntrNoMem]>;
3f23b32
 
3f23b32
   def int_SI_sample : Sample;
3f23b32
diff --git a/lib/Target/R600/SILowerControlFlow.cpp b/lib/Target/R600/SILowerControlFlow.cpp
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index 958763d..254f3a6 100644
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--- a/lib/Target/R600/SILowerControlFlow.cpp
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+++ b/lib/Target/R600/SILowerControlFlow.cpp
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@@ -55,6 +55,7 @@
3f23b32
 #include "llvm/CodeGen/MachineFunctionPass.h"
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 #include "llvm/CodeGen/MachineInstrBuilder.h"
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 #include "llvm/CodeGen/MachineRegisterInfo.h"
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+#include "llvm/IR/Constants.h"
3f23b32
 
3f23b32
 using namespace llvm;
3f23b32
 
3f23b32
@@ -145,7 +146,9 @@ void SILowerControlFlowPass::SkipIfDead(MachineInstr &MI) {
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   MachineBasicBlock &MBB = *MI.getParent();
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   DebugLoc DL = MI.getDebugLoc();
3f23b32
 
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-  if (!shouldSkip(&MBB, &MBB.getParent()->back()))
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+  if (MBB.getParent()->getInfo<SIMachineFunctionInfo>()->ShaderType !=
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+      ShaderType::PIXEL ||
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+      !shouldSkip(&MBB, &MBB.getParent()->back()))
3f23b32
     return;
3f23b32
 
3f23b32
   MachineBasicBlock::iterator Insert = &MI;
3f23b32
@@ -295,15 +298,27 @@ void SILowerControlFlowPass::Kill(MachineInstr &MI) {
3f23b32
 
3f23b32
   MachineBasicBlock &MBB = *MI.getParent();
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   DebugLoc DL = MI.getDebugLoc();
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+  const MachineOperand &Op = MI.getOperand(0);
3f23b32
 
3f23b32
-  // Kill is only allowed in pixel shaders
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+  // Kill is only allowed in pixel / geometry shaders
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   assert(MBB.getParent()->getInfo<SIMachineFunctionInfo>()->ShaderType ==
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-         ShaderType::PIXEL);
3f23b32
-
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-  // Clear this pixel from the exec mask if the operand is negative
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-  BuildMI(MBB, &MI, DL, TII->get(AMDGPU::V_CMPX_LE_F32_e32), AMDGPU::VCC)
3f23b32
-          .addImm(0)
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-          .addOperand(MI.getOperand(0));
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+         ShaderType::PIXEL ||
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+         MBB.getParent()->getInfo<SIMachineFunctionInfo>()->ShaderType ==
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+         ShaderType::GEOMETRY);
3f23b32
+
3f23b32
+  // Clear this thread from the exec mask if the operand is negative
3f23b32
+  if ((Op.isImm() || Op.isFPImm())) {
3f23b32
+    // Constant operand: Set exec mask to 0 or do nothing
3f23b32
+    if (Op.isImm() ? (Op.getImm() & 0x80000000) :
3f23b32
+        Op.getFPImm()->isNegative()) {
3f23b32
+      BuildMI(MBB, &MI, DL, TII->get(AMDGPU::S_MOV_B64), AMDGPU::EXEC)
3f23b32
+              .addImm(0);
3f23b32
+    }
3f23b32
+  } else {
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+    BuildMI(MBB, &MI, DL, TII->get(AMDGPU::V_CMPX_LE_F32_e32), AMDGPU::VCC)
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+           .addImm(0)
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+           .addOperand(Op);
3f23b32
+  }
3f23b32
 
3f23b32
   MI.eraseFromParent();
3f23b32
 }
3f23b32
diff --git a/test/CodeGen/R600/llvm.AMDGPU.kill.ll b/test/CodeGen/R600/llvm.AMDGPU.kill.ll
3f23b32
new file mode 100644
3f23b32
index 0000000..4ab6a8a
3f23b32
--- /dev/null
3f23b32
+++ b/test/CodeGen/R600/llvm.AMDGPU.kill.ll
3f23b32
@@ -0,0 +1,22 @@
3f23b32
+; RUN: llc < %s -march=r600 -mcpu=verde -verify-machineinstrs | FileCheck --check-prefix=SI %s
3f23b32
+
3f23b32
+; SI-LABEL: @kill_gs_const
3f23b32
+; SI-NOT: V_CMPX_LE_F32
3f23b32
+; SI: S_MOV_B64 exec, 0
3f23b32
+
3f23b32
+define void @kill_gs_const() #0 {
3f23b32
+main_body:
3f23b32
+  %0 = icmp ule i32 0, 3
3f23b32
+  %1 = select i1 %0, float 1.000000e+00, float -1.000000e+00
3f23b32
+  call void @llvm.AMDGPU.kill(float %1)
3f23b32
+  %2 = icmp ule i32 3, 0
3f23b32
+  %3 = select i1 %2, float 1.000000e+00, float -1.000000e+00
3f23b32
+  call void @llvm.AMDGPU.kill(float %3)
3f23b32
+  ret void
3f23b32
+}
3f23b32
+
3f23b32
+declare void @llvm.AMDGPU.kill(float)
3f23b32
+
3f23b32
+attributes #0 = { "ShaderType"="2" }
3f23b32
+
3f23b32
+!0 = metadata !{metadata !"const", null, i32 1}
3f23b32
diff --git a/test/CodeGen/R600/llvm.SI.load.dword.ll b/test/CodeGen/R600/llvm.SI.load.dword.ll
3f23b32
new file mode 100644
3f23b32
index 0000000..a622775
3f23b32
--- /dev/null
3f23b32
+++ b/test/CodeGen/R600/llvm.SI.load.dword.ll
3f23b32
@@ -0,0 +1,40 @@
3f23b32
+;RUN: llc < %s -march=r600 -mcpu=verde -verify-machineinstrs | FileCheck %s
3f23b32
+
3f23b32
+; Example of a simple geometry shader loading vertex attributes from the
3f23b32
+; ESGS ring buffer
3f23b32
+
3f23b32
+; CHECK-LABEL: @main
3f23b32
+; CHECK: BUFFER_LOAD_DWORD
3f23b32
+; CHECK: BUFFER_LOAD_DWORD
3f23b32
+; CHECK: BUFFER_LOAD_DWORD
3f23b32
+; CHECK: BUFFER_LOAD_DWORD
3f23b32
+
3f23b32
+define void @main([17 x <16 x i8>] addrspace(2)* byval, [32 x <16 x i8>] addrspace(2)* byval, [16 x <32 x i8>] addrspace(2)* byval, [2 x <16 x i8>] addrspace(2)* byval, [17 x <16 x i8>] addrspace(2)* inreg, [17 x <16 x i8>] addrspace(2)* inreg, i32, i32, i32, i32) #0 {
3f23b32
+main_body:
3f23b32
+  %10 = getelementptr [2 x <16 x i8>] addrspace(2)* %3, i64 0, i32 1
3f23b32
+  %11 = load <16 x i8> addrspace(2)* %10, !tbaa !0
3f23b32
+  %12 = shl i32 %6, 2
3f23b32
+  %13 = call i32 @llvm.SI.buffer.load.dword.i32.i32(<16 x i8> %11, i32 0, i32 0, i32 0, i32 0, i32 0, i32 1, i32 1, i32 0)
3f23b32
+  %14 = bitcast i32 %13 to float
3f23b32
+  %15 = call i32 @llvm.SI.buffer.load.dword.i32.i32(<16 x i8> %11, i32 %12, i32 0, i32 0, i32 1, i32 0, i32 1, i32 1, i32 0)
3f23b32
+  %16 = bitcast i32 %15 to float
3f23b32
+  %17 = call i32 @llvm.SI.buffer.load.dword.i32.i32(<16 x i8> %11, i32 %12, i32 0, i32 0, i32 0, i32 1, i32 1, i32 1, i32 0)
3f23b32
+  %18 = bitcast i32 %17 to float
3f23b32
+  %19 = call i32 @llvm.SI.buffer.load.dword.i32.v2i32(<16 x i8> %11, <2 x i32> <i32 0, i32 0>, i32 0, i32 0, i32 1, i32 1, i32 1, i32 1, i32 0)
3f23b32
+  %20 = bitcast i32 %19 to float
3f23b32
+  call void @llvm.SI.export(i32 15, i32 0, i32 1, i32 12, i32 0, float %14, float %16, float %18, float %20)
3f23b32
+  ret void
3f23b32
+}
3f23b32
+
3f23b32
+; Function Attrs: nounwind readonly
3f23b32
+declare i32 @llvm.SI.buffer.load.dword.i32.i32(<16 x i8>, i32, i32, i32, i32, i32, i32, i32, i32) #1
3f23b32
+
3f23b32
+; Function Attrs: nounwind readonly
3f23b32
+declare i32 @llvm.SI.buffer.load.dword.i32.v2i32(<16 x i8>, <2 x i32>, i32, i32, i32, i32, i32, i32, i32) #1
3f23b32
+
3f23b32
+declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)
3f23b32
+
3f23b32
+attributes #0 = { "ShaderType"="1" }
3f23b32
+attributes #1 = { nounwind readonly }
3f23b32
+
3f23b32
+!0 = metadata !{metadata !"const", null, i32 1}
3f23b32
diff --git a/test/CodeGen/R600/llvm.SI.sendmsg.ll b/test/CodeGen/R600/llvm.SI.sendmsg.ll
3f23b32
new file mode 100644
3f23b32
index 0000000..581d422
3f23b32
--- /dev/null
3f23b32
+++ b/test/CodeGen/R600/llvm.SI.sendmsg.ll
3f23b32
@@ -0,0 +1,21 @@
3f23b32
+;RUN: llc < %s -march=r600 -mcpu=verde -verify-machineinstrs | FileCheck %s
3f23b32
+
3f23b32
+; CHECK-LABEL: @main
3f23b32
+; CHECK: S_SENDMSG Gs(emit stream 0)
3f23b32
+; CHECK: S_SENDMSG Gs(cut stream 1)
3f23b32
+; CHECK: S_SENDMSG Gs(emit-cut stream 2)
3f23b32
+; CHECK: S_SENDMSG Gs_done(nop)
3f23b32
+
3f23b32
+define void @main() {
3f23b32
+main_body:
3f23b32
+  call void @llvm.SI.sendmsg(i32 34, i32 0);
3f23b32
+  call void @llvm.SI.sendmsg(i32 274, i32 0);
3f23b32
+  call void @llvm.SI.sendmsg(i32 562, i32 0);
3f23b32
+  call void @llvm.SI.sendmsg(i32 3, i32 0);
3f23b32
+  ret void
3f23b32
+}
3f23b32
+
3f23b32
+; Function Attrs: nounwind
3f23b32
+declare void @llvm.SI.sendmsg(i32, i32) #0
3f23b32
+
3f23b32
+attributes #0 = { nounwind }