From 70dc85b699d0ae67ed9cdb5addfc053515288c1b Mon Sep 17 00:00:00 2001 From: Chitlesh GOORAH Date: Aug 13 2007 21:02:23 +0000 Subject: *** empty log message *** --- diff --git a/.cvsignore b/.cvsignore index e69de29..e2837be 100644 --- a/.cvsignore +++ b/.cvsignore @@ -0,0 +1 @@ +alliance-5.0-20070718.tar.gz diff --git a/alliance-examples.patch b/alliance-examples.patch new file mode 100644 index 0000000..582c2fc --- /dev/null +++ b/alliance-examples.patch @@ -0,0 +1,594 @@ +diff -Naur documentation/alliance-examples/addaccu16/Makefile alliance-examples/addaccu16/Makefile +--- documentation/alliance-examples/addaccu16/Makefile 2004-05-24 00:15:16.000000000 +0200 ++++ alliance-examples/addaccu16/Makefile 2007-07-19 13:13:51.000000000 +0200 +@@ -16,7 +16,9 @@ + # | | + # \------------------------------------------------------------*/ + + ALLIANCE_BIN=$(ALLIANCE_TOP)/bin ++ ++ALLIANCE_EXAMPLES=/usr/share/doc/alliance-doc-5.0/alliance-examples + + VASY = $(ALLIANCE_BIN)/vasy + ASIMUT = $(ALLIANCE_BIN)/asimut +@@ -39,8 +41,8 @@ + TOUCH = touch + + TARGET_LIB = $(ALLIANCE_TOP)/cells/sxlib +-RDS_TECHNO_SYMB = ../etc/techno-symb.rds +-RDS_TECHNO = ../etc/techno-035.rds ++RDS_TECHNO_SYMB = $(ALLIANCE_EXAMPLES)/etc/techno-symb.rds ++RDS_TECHNO = $(ALLIANCE_EXAMPLES)/etc/techno-035.rds + SPI_MODEL = $(ALLIANCE_TOP)/etc/spimodel.cfg + METAL_LEVEL = 2 + +diff -Naur documentation/alliance-examples/addaccu16/README alliance-examples/addaccu16/README +--- documentation/alliance-examples/addaccu16/README 2004-07-28 13:00:06.000000000 +0200 ++++ alliance-examples/addaccu16/README 2007-07-19 13:13:51.000000000 +0200 +@@ -10,11 +10,13 @@ + the associated stimuli file, and also a configuration file for IO + placement (used during the Place and Route step). + +-The Makefile set environement variables properly and run Alliance tools, ++The Makefile set environment variables properly and run Alliance tools, + following each step of the design flow from VHDL up to real layout in a + pseudo 0.35 techno. + +-The environement variable ALLIANCE_TOP has to be set. ++ ++copy the folder "addaccu16" to any writable folder of your choice and type: ++$ make + + The main targets of the makefile are listed below (following the design flow). + +diff -Naur documentation/alliance-examples/adder4/adder4.ioc alliance-examples/adder4/adder4.ioc +--- documentation/alliance-examples/adder4/adder4.ioc 2004-05-23 19:27:03.000000000 +0200 ++++ alliance-examples/adder4/adder4.ioc 2007-07-19 13:13:51.000000000 +0200 +@@ -1,4 +1,4 @@ +-# Copyright (c) 1997 by Cadence. All rights reserved. ++# + ################################################################### + # In each of TOP()/BOTTOM()/LEFT()/RIGHT() section, there are # + # placed IOs. In the IGNORE() section, the IOs are ignored # +diff -Naur documentation/alliance-examples/adder4/Makefile alliance-examples/adder4/Makefile +--- documentation/alliance-examples/adder4/Makefile 2004-05-24 00:15:20.000000000 +0200 ++++ alliance-examples/adder4/Makefile 2007-07-19 13:13:51.000000000 +0200 +@@ -16,7 +16,9 @@ + # | | + # \------------------------------------------------------------*/ + + ALLIANCE_BIN=$(ALLIANCE_TOP)/bin ++ ++ALLIANCE_EXAMPLES=/usr/share/doc/alliance-doc-5.0/alliance-examples + + VASY = $(ALLIANCE_BIN)/vasy + ASIMUT = $(ALLIANCE_BIN)/asimut +@@ -39,8 +41,8 @@ + TOUCH = touch + + TARGET_LIB = $(ALLIANCE_TOP)/cells/sxlib +-RDS_TECHNO_SYMB = ../etc/techno-symb.rds +-RDS_TECHNO = ../etc/techno-035.rds ++RDS_TECHNO_SYMB = $(ALLIANCE_EXAMPLES)/etc/techno-symb.rds ++RDS_TECHNO = $(ALLIANCE_EXAMPLES)/etc/techno-035.rds + SPI_MODEL = $(ALLIANCE_TOP)/etc/spimodel.cfg + METAL_LEVEL = 2 + +diff -Naur documentation/alliance-examples/adder4/README alliance-examples/adder4/README +--- documentation/alliance-examples/adder4/README 2004-07-28 13:00:06.000000000 +0200 ++++ alliance-examples/adder4/README 2007-07-19 13:13:51.000000000 +0200 +@@ -14,7 +14,9 @@ + following each step of the design flow from VHDL up to real layout in a + pseudo 0.35 techno. + +-The environement variable ALLIANCE_TOP has to be set. ++ ++copy the folder "adder4" to any writable folder of your choice and type: ++$ make + + The main targets of the makefile are listed below (following the design flow). + +diff -Naur documentation/alliance-examples/amd2901/amd2901_core.ioc alliance-examples/amd2901/amd2901_core.ioc +--- documentation/alliance-examples/amd2901/amd2901_core.ioc 2004-05-23 20:55:16.000000000 +0200 ++++ alliance-examples/amd2901/amd2901_core.ioc 2007-07-19 13:13:52.000000000 +0200 +@@ -1,4 +1,4 @@ +-# Copyright (c) 1997 by Cadence. All rights reserved. ++# + ################################################################### + # In each of TOP()/BOTTOM()/LEFT()/RIGHT() section, there are # + # placed IOs. In the IGNORE() section, the IOs are ignored # + +diff -Naur documentation/alliance-examples/amd2901/Makefile alliance-examples/amd2901/Makefile +--- documentation/alliance-examples/amd2901/Makefile 2004-05-24 00:15:22.000000000 +0200 ++++ alliance-examples/amd2901/Makefile 2007-07-19 13:13:51.000000000 +0200 +@@ -11,7 +11,9 @@ + STANDART_PATH = PATH=$(STANDART_BIN); export PATH + + # Standart Alliance binary access paths. + ALLIANCE_BIN = $(ALLIANCE_TOP)/bin ++ ++ALLIANCE_EXAMPLES=/usr/share/doc/alliance-doc-5.0/alliance-examples + + # -------------------------------------------------------------------- + # Standarts binaries. +@@ -41,8 +43,8 @@ + CATA_LIB2 = $(ALLIANCE_TOP)/cells/padlib + CATA_LIB = .:$(CATA_LIB0):$(CATA_LIB1):$(CATA_LIB2) + TARGET_LIB = $(ALLIANCE_TOP)/cells/sxlib +- RDS_TECHNO = ../etc/techno-symb.rds +- REAL_RDS_TECHNO = ../etc/techno-035.rds ++RDS_TECHNO_SYMB = $(ALLIANCE_EXAMPLES)/etc/techno-symb.rds ++RDS_TECHNO = $(ALLIANCE_EXAMPLES)/etc/techno-035.rds + GRAAL_TECHNO = $(ALLIANCE_TOP)/etc/cmos.graal + + +diff -Naur documentation/alliance-examples/amd2901-vasy/amd2901.ioc alliance-examples/amd2901-vasy/amd2901.ioc +--- documentation/alliance-examples/amd2901-vasy/amd2901.ioc 2004-05-23 21:00:16.000000000 +0200 ++++ alliance-examples/amd2901-vasy/amd2901.ioc 2007-07-19 13:13:52.000000000 +0200 +@@ -1,4 +1,4 @@ +-# Copyright (c) 1997 by Cadence. All rights reserved. ++# + ################################################################### + # In each of TOP()/BOTTOM()/LEFT()/RIGHT() section, there are # + # placed IOs. In the IGNORE() section, the IOs are ignored # +diff -Naur documentation/alliance-examples/amd2901-vasy/Makefile alliance-examples/amd2901-vasy/Makefile +--- documentation/alliance-examples/amd2901-vasy/Makefile 2004-05-24 00:15:23.000000000 +0200 ++++ alliance-examples/amd2901-vasy/Makefile 2007-07-19 13:13:52.000000000 +0200 +@@ -16,7 +16,9 @@ + # | | + # \------------------------------------------------------------*/ + + ALLIANCE_BIN = $(ALLIANCE_TOP)/bin ++ ++ALLIANCE_EXAMPLES=/usr/share/doc/alliance-doc-5.0/alliance-examples + + VASY = $(ALLIANCE_BIN)/vasy + ASIMUT = $(ALLIANCE_BIN)/asimut +@@ -40,8 +42,8 @@ + TOUCH = touch + + TARGET_LIB = $(ALLIANCE_TOP)/cells/sxlib +-RDS_TECHNO_SYMB = ../etc/techno-symb.rds +-RDS_TECHNO = ../etc/techno-035.rds ++RDS_TECHNO_SYMB = $(ALLIANCE_EXAMPLES)/etc/techno-symb.rds ++RDS_TECHNO = $(ALLIANCE_EXAMPLES)/etc/techno-035.rds + SPI_MODEL = $(ALLIANCE_TOP)/etc/spimodel.cfg + METAL_LEVEL = 4 + +diff -Naur documentation/alliance-examples/digi/Makefile alliance-examples/digi/Makefile +--- documentation/alliance-examples/digi/Makefile 2004-09-09 22:03:49.000000000 +0200 ++++ alliance-examples/digi/Makefile 2007-07-19 13:13:52.000000000 +0200 +@@ -16,7 +16,9 @@ + # | | + # \------------------------------------------------------------*/ + + ALLIANCE_BIN=$(ALLIANCE_TOP)/bin ++ ++ALLIANCE_EXAMPLES=/usr/share/doc/alliance-doc-5.0/alliance-examples + + SYF = $(ALLIANCE_BIN)/syf + ASIMUT = $(ALLIANCE_BIN)/asimut +@@ -40,14 +42,14 @@ + TOUCH = touch + + TARGET_LIB = $(ALLIANCE_TOP)/cells/sxlib +-RDS_TECHNO_SYMB = ../etc/techno-symb.rds +-RDS_TECHNO = ../etc/techno-035.rds ++RDS_TECHNO_SYMB = $(ALLIANCE_EXAMPLES)/etc/techno-symb.rds ++RDS_TECHNO = $(ALLIANCE_EXAMPLES)/etc/techno-035.rds + METAL_LEVEL = 2 + SPI_MODEL = $(ALLIANCE_TOP)/etc/spimodel.cfg + + # /*------------------------------------------------------------\ + # | | +-# | Environement | ++# | Environment | + # | | + # \------------------------------------------------------------*/ + +diff -Naur documentation/alliance-examples/divcas4/divcas4.ioc alliance-examples/divcas4/divcas4.ioc +--- documentation/alliance-examples/divcas4/divcas4.ioc 2004-05-23 19:52:10.000000000 +0200 ++++ alliance-examples/divcas4/divcas4.ioc 2007-07-19 13:13:52.000000000 +0200 +@@ -1,4 +1,4 @@ +-# Copyright (c) 1997 by Cadence. All rights reserved. ++# + ################################################################### + # In each of TOP()/BOTTOM()/LEFT()/RIGHT() section, there are # + # placed IOs. In the IGNORE() section, the IOs are ignored # +diff -Naur documentation/alliance-examples/divcas4/Makefile alliance-examples/divcas4/Makefile +--- documentation/alliance-examples/divcas4/Makefile 2004-05-23 21:11:26.000000000 +0200 ++++ alliance-examples/divcas4/Makefile 2007-07-19 13:13:52.000000000 +0200 +@@ -16,7 +16,9 @@ + # | | + # \------------------------------------------------------------*/ + + ALLIANCE_BIN = $(ALLIANCE_TOP)/bin ++ ++ALLIANCE_EXAMPLES=/usr/share/doc/alliance-doc-5.0/alliance-examples + + VASY = $(ALLIANCE_BIN)/vasy + ASIMUT = $(ALLIANCE_BIN)/asimut +@@ -39,8 +41,8 @@ + TOUCH = touch + + TARGET_LIB = $(ALLIANCE_TOP)/cells/sxlib +-RDS_TECHNO_SYMB = ../etc/techno-symb.rds +-RDS_TECHNO = ../etc/techno-035.rds ++RDS_TECHNO_SYMB = $(ALLIANCE_EXAMPLES)/etc/techno-symb.rds ++RDS_TECHNO = $(ALLIANCE_EXAMPLES)/etc/techno-035.rds + SPI_MODEL = $(ALLIANCE_TOP)/etc/spimodel.cfg + METAL_LEVEL = 2 + +diff -Naur documentation/alliance-examples/divcas4/README alliance-examples/divcas4/README +--- documentation/alliance-examples/divcas4/README 2004-07-28 13:00:06.000000000 +0200 ++++ alliance-examples/divcas4/README 2007-07-19 13:13:52.000000000 +0200 +@@ -14,5 +14,6 @@ + following each step of the design flow from VHDL up to real layout in a + pseudo 0.35 techno. + +-The environement variable ALLIANCE_TOP has to be set. +- ++ ++copy the folder "divcas4" to any writable folder of your choice and type: ++$ make +diff -Naur documentation/alliance-examples/hadamard/Makefile alliance-examples/hadamard/Makefile +--- documentation/alliance-examples/hadamard/Makefile 2004-05-24 00:15:25.000000000 +0200 ++++ alliance-examples/hadamard/Makefile 2007-07-19 16:21:10.000000000 +0200 +@@ -16,7 +16,9 @@ + # | | + # \------------------------------------------------------------*/ + + ALLIANCE_BIN = $(ALLIANCE_TOP)/bin ++ ++ALLIANCE_EXAMPLES=/usr/share/doc/alliance-doc-5.0/alliance-examples + + VASY = $(ALLIANCE_BIN)/vasy + ASIMUT = $(ALLIANCE_BIN)/asimut +@@ -39,14 +41,14 @@ + TOUCH = touch + + TARGET_LIB = $(ALLIANCE_TOP)/cells/sxlib +-RDS_TECHNO_SYMB = ../etc/techno-symb.rds +-RDS_TECHNO = ../etc/techno-035.rds ++RDS_TECHNO_SYMB = $(ALLIANCE_EXAMPLES)/etc/techno-symb.rds ++RDS_TECHNO = $(ALLIANCE_EXAMPLES)/etc/techno-035.rds + SPI_MODEL = $(ALLIANCE_TOP)/etc/spimodel.cfg + METAL_LEVEL = 6 + + # /*------------------------------------------------------------\ + # | | +-# | Environement | ++# | Environment | + # | | + # \------------------------------------------------------------*/ + +@@ -163,11 +165,11 @@ + + res_vasy_1.pat : hadamard.vst calcul.vbe ram.vbe rom.vbe \ + compteur.vbe sequenceur.vbe hadamard_model.vbe +- $(ENV_ASIMUT_VASY); $(ASIMUT) hadamard hadamard_1 res_vasy_1 ++ $(ENV_ASIMUT_VASY); $(ASIMUT) hadamard hadamard_1 res_vasy_1 + + res_synth_1.pat : hadamard.vst calcul.vst ram.vst rom.vst \ + compteur.vst sequenceur.vst hadamard_model.vst +- $(ENV_ASIMUT_SYNTH); $(ASIMUT) -zd hadamard hadamard_1 res_synth_1 ++ $(ENV_ASIMUT_SYNTH); $(ASIMUT) -zd hadamard hadamard_1 res_synth_1 + + + # /*------------------------------------------------------------\ +@@ -299,7 +301,7 @@ + # | | + # \------------------------------------------------------------*/ + +-lvx.done : hadamard.vst hadamard_e.al ++lvx.done : hadamard.vst hadamard_e.al + $(ENV_LVX); $(LVX) vst al hadamard hadamard_e -f + $(TOUCH) lvx.done + +@@ -355,4 +357,4 @@ + $(RM) -f *.vst *.vbe *.boom *.done *.xsc *.al *.ap *.gpl *.gds \ + *.log *.drc *.cif *.fin *.dat *.out hadamard_e.spi res_synth_1.pat \ + res_vasy_1.pat +- ++ +diff -Naur documentation/alliance-examples/mipsR3000/sce/Makefile alliance-examples/mipsR3000/sce/Makefile +--- documentation/alliance-examples/mipsR3000/sce/Makefile 2004-07-30 02:40:09.000000000 +0200 ++++ alliance-examples/mipsR3000/sce/Makefile 2007-07-19 13:13:58.000000000 +0200 +@@ -5,7 +5,9 @@ + STANDART_PATH = PATH=$(STANDART_BIN); export PATH + + # Standart Alliance binary access paths. + ALLIANCE_BIN = $(ALLIANCE_TOP)/bin ++ ++ALLIANCE_EXAMPLES=/usr/share/doc/alliance-doc-5.0/alliance-examples + + # FitPath Alliance binary access paths. + # DEVEL_BIN = /users/soft5/newlabo/alliance-4.5.0/archi/Solaris/bin +diff -Naur documentation/alliance-examples/mipsR3000/sce/mips_core.ioc alliance-examples/mipsR3000/sce/mips_core.ioc +--- documentation/alliance-examples/mipsR3000/sce/mips_core.ioc 2004-05-24 00:23:35.000000000 +0200 ++++ alliance-examples/mipsR3000/sce/mips_core.ioc 2007-07-19 13:13:58.000000000 +0200 +@@ -1,4 +1,4 @@ +-# Copyright (c) 1997 by Cadence. All rights reserved. ++# + ################################################################### + # In each of TOP()/BOTTOM()/LEFT()/RIGHT() section, there are # + # placed IOs. In the IGNORE() section, the IOs are ignored # +diff -Naur documentation/alliance-examples/multi16b-reg/Makefile alliance-examples/multi16b-reg/Makefile +--- documentation/alliance-examples/multi16b-reg/Makefile 2004-05-24 00:15:29.000000000 +0200 ++++ alliance-examples/multi16b-reg/Makefile 2007-07-19 13:13:59.000000000 +0200 +@@ -16,7 +16,9 @@ + # | | + # \------------------------------------------------------------*/ + + ALLIANCE_BIN = $(ALLIANCE_TOP)/bin ++ ++ALLIANCE_EXAMPLES=/usr/share/doc/alliance-doc-5.0/alliance-examples + + VASY = $(ALLIANCE_BIN)/vasy + ASIMUT = $(ALLIANCE_BIN)/asimut +@@ -39,14 +41,14 @@ + TOUCH = touch + + TARGET_LIB = $(ALLIANCE_TOP)/cells/sxlib +-RDS_TECHNO_SYMB = ../etc/techno-symb.rds +-RDS_TECHNO = ../etc/techno-035.rds ++RDS_TECHNO_SYMB = $(ALLIANCE_EXAMPLES)/etc/techno-symb.rds ++RDS_TECHNO = $(ALLIANCE_EXAMPLES)/etc/techno-035.rds + SPI_MODEL = $(ALLIANCE_TOP)/etc/spimodel.cfg + METAL_LEVEL = 6 + + # /*------------------------------------------------------------\ + # | | +-# | Environement | ++# | Environment | + # | | + # \------------------------------------------------------------*/ + +diff -Naur documentation/alliance-examples/multi4b/Makefile alliance-examples/multi4b/Makefile +--- documentation/alliance-examples/multi4b/Makefile 2004-05-24 00:15:29.000000000 +0200 ++++ alliance-examples/multi4b/Makefile 2007-07-19 13:14:00.000000000 +0200 +@@ -16,7 +16,9 @@ + # | | + # \------------------------------------------------------------*/ + + ALLIANCE_BIN=$(ALLIANCE_TOP)/bin ++ ++ALLIANCE_EXAMPLES=/usr/share/doc/alliance-doc-5.0/alliance-examples + + VASY = $(ALLIANCE_BIN)/vasy + ASIMUT = $(ALLIANCE_BIN)/asimut +@@ -39,14 +41,14 @@ + TOUCH = touch + + TARGET_LIB = $(ALLIANCE_TOP)/cells/sxlib +-RDS_TECHNO_SYMB = ../etc/techno-symb.rds +-RDS_TECHNO = ../etc/techno-035.rds ++RDS_TECHNO_SYMB = $(ALLIANCE_EXAMPLES)/etc/techno-symb.rds ++RDS_TECHNO = $(ALLIANCE_EXAMPLES)/etc/techno-035.rds + SPI_MODEL = $(ALLIANCE_TOP)/etc/spimodel.cfg + METAL_LEVEL = 2 + + # /*------------------------------------------------------------\ + # | | +-# | Environement | ++# | Environment | + # | | + # \------------------------------------------------------------*/ + +diff -Naur documentation/alliance-examples/multi4b/README alliance-examples/multi4b/README +--- documentation/alliance-examples/multi4b/README 2004-07-28 13:00:06.000000000 +0200 ++++ alliance-examples/multi4b/README 2007-07-19 13:14:00.000000000 +0200 +@@ -14,7 +14,9 @@ + following each step of the design flow from VHDL up to real layout in a + pseudo 0.35 techno. + +-The environement variable ALLIANCE_TOP has to be set. ++ ++copy the folder "multi4b" to any writable folder of your choice and type: ++$ make + + The main targets of the makefile are listed below (following the design flow). + +diff -Naur documentation/alliance-examples/multi8/Makefile alliance-examples/multi8/Makefile +--- documentation/alliance-examples/multi8/Makefile 2004-05-24 00:15:30.000000000 +0200 ++++ alliance-examples/multi8/Makefile 2007-07-19 13:14:00.000000000 +0200 +@@ -16,7 +16,9 @@ + # | | + # \------------------------------------------------------------*/ + + ALLIANCE_BIN=$(ALLIANCE_TOP)/bin ++ ++ALLIANCE_EXAMPLES=/usr/share/doc/alliance-doc-5.0/alliance-examples + + VASY = $(ALLIANCE_BIN)/vasy + ASIMUT = $(ALLIANCE_BIN)/asimut +@@ -39,8 +41,8 @@ + TOUCH = touch + + TARGET_LIB = $(ALLIANCE_TOP)/cells/sxlib +-RDS_TECHNO_SYMB = ../etc/techno-symb.rds +-RDS_TECHNO = ../etc/techno-035.rds ++RDS_TECHNO_SYMB = $(ALLIANCE_EXAMPLES)/etc/techno-symb.rds ++RDS_TECHNO = $(ALLIANCE_EXAMPLES)/etc/techno-035.rds + SPI_MODEL = $(ALLIANCE_TOP)/etc/spimodel.cfg + METAL_LEVEL = 2 + +diff -Naur documentation/alliance-examples/multi8/README alliance-examples/multi8/README +--- documentation/alliance-examples/multi8/README 2004-07-28 13:00:06.000000000 +0200 ++++ alliance-examples/multi8/README 2007-07-19 13:14:00.000000000 +0200 +@@ -15,4 +15,6 @@ + following each step of the design flow from VHDL up to real layout in a + pseudo 0.35 techno. + +-The environement variable ALLIANCE_TOP has to be set. ++ ++copy the folder "multi8" to any writable folder of your choice and type: ++$ make +diff -Naur documentation/alliance-examples/multi8b/Makefile alliance-examples/multi8b/Makefile +--- documentation/alliance-examples/multi8b/Makefile 2004-05-24 00:15:30.000000000 +0200 ++++ alliance-examples/multi8b/Makefile 2007-07-19 13:14:00.000000000 +0200 +@@ -16,7 +16,9 @@ + # | | + # \------------------------------------------------------------*/ + + ALLIANCE_BIN=$(ALLIANCE_TOP)/bin ++ ++ALLIANCE_EXAMPLES=/usr/share/doc/alliance-doc-5.0/alliance-examples + + VASY = $(ALLIANCE_BIN)/vasy + ASIMUT = $(ALLIANCE_BIN)/asimut +@@ -39,8 +41,8 @@ + TOUCH = touch + + TARGET_LIB = $(ALLIANCE_TOP)/cells/sxlib +-RDS_TECHNO_SYMB = ../etc/techno-symb.rds +-RDS_TECHNO = ../etc/techno-035.rds ++RDS_TECHNO_SYMB = $(ALLIANCE_EXAMPLES)/etc/techno-symb.rds ++RDS_TECHNO = $(ALLIANCE_EXAMPLES)/etc/techno-035.rds + SPI_MODEL = $(ALLIANCE_TOP)/etc/spimodel.cfg + METAL_LEVEL = 4 + +diff -Naur documentation/alliance-examples/multi8b/README alliance-examples/multi8b/README +--- documentation/alliance-examples/multi8b/README 2004-07-28 13:00:06.000000000 +0200 ++++ alliance-examples/multi8b/README 2007-07-19 13:14:00.000000000 +0200 +@@ -14,7 +14,9 @@ + following each step of the design flow from VHDL up to real layout in a + pseudo 0.35 techno. + +-The environement variable ALLIANCE_TOP has to be set. ++ ++copy the folder "multi8b" to any writable folder of your choice and type: ++$ make + + The main targets of the makefile are listed below (following the design flow). + +diff -Naur documentation/alliance-examples/pgcd/Makefile alliance-examples/pgcd/Makefile +--- documentation/alliance-examples/pgcd/Makefile 2004-05-24 00:15:31.000000000 +0200 ++++ alliance-examples/pgcd/Makefile 2007-07-19 13:14:00.000000000 +0200 +@@ -16,7 +16,9 @@ + # | | + # \------------------------------------------------------------*/ + + ALLIANCE_BIN=$(ALLIANCE_TOP)/bin ++ ++ALLIANCE_EXAMPLES=/usr/share/doc/alliance-doc-5.0/alliance-examples + + VASY = $(ALLIANCE_BIN)/vasy + ASIMUT = $(ALLIANCE_BIN)/asimut +@@ -39,8 +41,8 @@ + TOUCH = touch + + TARGET_LIB = $(ALLIANCE_TOP)/cells/sxlib +-RDS_TECHNO_SYMB = ../etc/techno-symb.rds +-RDS_TECHNO = ../etc/techno-035.rds ++RDS_TECHNO_SYMB = $(ALLIANCE_EXAMPLES)/etc/techno-symb.rds ++RDS_TECHNO = $(ALLIANCE_EXAMPLES)/etc/techno-035.rds + SPI_MODEL = $(ALLIANCE_TOP)/etc/spimodel.cfg + METAL_LEVEL = 2 + +diff -Naur documentation/alliance-examples/pgcd/README alliance-examples/pgcd/README +--- documentation/alliance-examples/pgcd/README 2004-07-28 13:00:06.000000000 +0200 ++++ alliance-examples/pgcd/README 2007-07-19 13:14:00.000000000 +0200 +@@ -15,5 +15,7 @@ + following each step of the design flow from VHDL up to real layout in a + pseudo 0.35 techno. + +-The environement variable ALLIANCE_TOP has to be set. ++ ++copy the folder "pgcd" to any writable folder of your choice and type: ++$ make + +diff -Naur documentation/alliance-examples/sqrt32/Makefile alliance-examples/sqrt32/Makefile +--- documentation/alliance-examples/sqrt32/Makefile 2004-05-23 20:49:27.000000000 +0200 ++++ alliance-examples/sqrt32/Makefile 2007-07-19 13:14:00.000000000 +0200 +@@ -16,7 +16,9 @@ + # | | + # \------------------------------------------------------------*/ + + ALLIANCE_BIN=$(ALLIANCE_TOP)/bin ++ ++ALLIANCE_EXAMPLES=/usr/share/doc/alliance-doc-5.0/alliance-examples + + VASY = $(ALLIANCE_BIN)/vasy + ASIMUT = $(ALLIANCE_BIN)/asimut +@@ -39,8 +41,8 @@ + TOUCH = touch + + TARGET_LIB = $(ALLIANCE_TOP)/cells/sxlib +-RDS_TECHNO_SYMB = ../etc/techno-symb.rds +-RDS_TECHNO = ../etc/techno-035.rds ++RDS_TECHNO_SYMB = $(ALLIANCE_EXAMPLES)/etc/techno-symb.rds ++RDS_TECHNO = $(ALLIANCE_EXAMPLES)/etc/techno-035.rds + SPI_MODEL = $(ALLIANCE_TOP)/etc/spimodel.cfg + METAL_LEVEL = 5 + +diff -Naur documentation/alliance-examples/sqrt32/README alliance-examples/sqrt32/README +--- documentation/alliance-examples/sqrt32/README 2004-07-28 13:00:06.000000000 +0200 ++++ alliance-examples/sqrt32/README 2007-07-19 13:14:00.000000000 +0200 +@@ -14,4 +14,6 @@ + following each step of the design flow from VHDL up to real layout in a + pseudo 0.35 techno. + +-The environement variable ALLIANCE_TOP has to be set. ++ ++copy the folder "sqrt32" to any writable folder of your choice and type: ++$ make +diff -Naur documentation/alliance-examples/sqrt8/Makefile alliance-examples/sqrt8/Makefile +--- documentation/alliance-examples/sqrt8/Makefile 2004-05-23 20:51:00.000000000 +0200 ++++ alliance-examples/sqrt8/Makefile 2007-07-19 16:20:40.000000000 +0200 +@@ -16,7 +16,9 @@ + # | | + # \------------------------------------------------------------*/ + + ALLIANCE_BIN=$(ALLIANCE_TOP)/bin ++ ++ALLIANCE_EXAMPLES=/usr/share/doc/alliance-doc-5.0/alliance-examples + + VASY = $(ALLIANCE_BIN)/vasy + ASIMUT = $(ALLIANCE_BIN)/asimut +@@ -39,14 +41,14 @@ + TOUCH = touch + + TARGET_LIB = $(ALLIANCE_TOP)/cells/sxlib +-RDS_TECHNO_SYMB = ../etc/techno-symb.rds +-RDS_TECHNO = ../etc/techno-035.rds ++RDS_TECHNO_SYMB = $(ALLIANCE_EXAMPLES)/etc/techno-symb.rds ++RDS_TECHNO = $(ALLIANCE_EXAMPLES)/etc/techno-035.rds + SPI_MODEL = $(ALLIANCE_TOP)/etc/spimodel.cfg + METAL_LEVEL = 5 + + # /*------------------------------------------------------------\ + # | | +-# | Environement | ++# | Environment | + # | | + # \------------------------------------------------------------*/ + +@@ -161,9 +163,9 @@ + # \------------------------------------------------------------*/ + + res_vasy_1.pat : sqrt8.vst sm.vbe sqrt8_model.vbe +- $(ENV_ASIMUT_VASY); $(ASIMUT) sqrt8 sqrt8 res_vasy_1 ++ $(ENV_ASIMUT_VASY); $(ASIMUT) sqrt8 sqrt8 res_vasy_1 + +-res_synth_1.pat : sqrt8.vst sm.vst sqrt8_model.vst ++res_synth_1.pat : sqrt8.vst sm.vst sqrt8_model.vst + $(ENV_ASIMUT_SYNTH); $(ASIMUT) sqrt8 sqrt8 res_synth_1 + + +@@ -257,7 +259,7 @@ + # | | + # \------------------------------------------------------------*/ + +-lvx.done : sqrt8.vst sqrt8_e.al ++lvx.done : sqrt8.vst sqrt8_e.al + $(ENV_LVX); $(LVX) vst al sqrt8 sqrt8_e -f + $(TOUCH) lvx.done + +@@ -313,4 +315,4 @@ + $(RM) -f *.vst *.vbe *.boom *.done *.xsc *.al *.ap *.gpl *.gds \ + *.log *.drc *.cif *.fin *.dat *.out sqrt8_e.spi res_synth_1.pat \ + res_vasy_1.pat +- ++ + diff --git a/alliance-log3.patch b/alliance-log3.patch new file mode 100644 index 0000000..f320083 --- /dev/null +++ b/alliance-log3.patch @@ -0,0 +1,22 @@ +diff -Naur mbk/man3/Makefile.am man3/Makefile.am +--- mbk/man3/Makefile.am 2003-04-03 16:56:36.000000000 +0200 ++++ man3/Makefile.am 2007-07-25 01:33:26.000000000 +0200 +@@ -87,7 +87,6 @@ + locon.3 \ + lofig.3 \ + lofigchain.3 \ +- log.3 \ + loins.3 \ + losig.3 \ + lotrs.3 \ +diff -Naur mbk/man3/Makefile.in man3/Makefile.in +--- mbk/man3/Makefile.in 2007-07-18 19:04:43.000000000 +0200 ++++ man3/Makefile.in 2007-07-25 01:33:18.000000000 +0200 +@@ -422,7 +422,6 @@ + locon.3 \ + lofig.3 \ + lofigchain.3 \ +- log.3 \ + loins.3 \ + losig.3 \ + lotrs.3 \ diff --git a/alliance-perms.patch b/alliance-perms.patch new file mode 100644 index 0000000..32aa5cc --- /dev/null +++ b/alliance-perms.patch @@ -0,0 +1,14 @@ +--- configure 2006-05-09 12:10:10.000000000 +0200 ++++ configure_mod 2007-07-17 02:24:57.000000000 +0200 +@@ -26054,9 +26054,9 @@ + + + +-INSTALL_DATA='${INSTALL} -m 664' ++INSTALL_DATA='${INSTALL} -m 644' + +-INSTALL_PROGRAM='${INSTALL} -m 775' ++INSTALL_PROGRAM='${INSTALL} -m 755' + + + cat >>confdefs.h <<_ACEOF diff --git a/alliance-run.patch b/alliance-run.patch new file mode 100644 index 0000000..32e2009 --- /dev/null +++ b/alliance-run.patch @@ -0,0 +1,21 @@ +diff -Naur documentation/alliance-run/amd2901_core.ioc alliance-run/amd2901_core.ioc +--- documentation/alliance-run/amd2901_core.ioc 2003-10-09 14:31:00.000000000 +0200 ++++ alliance-run/amd2901_core.ioc 2007-07-13 15:42:11.000000000 +0200 +@@ -1,4 +1,3 @@ +-# Copyright (c) 1997 by Cadence. All rights reserved. + ################################################################### + # In each of TOP()/BOTTOM()/LEFT()/RIGHT() section, there are # + # placed IOs. In the IGNORE() section, the IOs are ignored # +diff -Naur documentation/alliance-run/Makefile alliance-run/Makefile +--- documentation/alliance-run/Makefile 2003-12-01 14:07:11.000000000 +0100 ++++ alliance-run/Makefile 2007-07-13 15:37:37.000000000 +0200 +@@ -12,7 +12,9 @@ + STANDART_PATH = PATH=$(STANDART_BIN); export PATH + + # Standart Alliance binary access paths. + ALLIANCE_BIN = $(ALLIANCE_TOP)/bin ++ ++ALLIANCE_EXAMPLES=/usr/share/doc/alliance-doc-5.0/alliance-examples + + # -------------------------------------------------------------------- + # Standarts binaries. diff --git a/alliance-tutorials.patch b/alliance-tutorials.patch new file mode 100644 index 0000000..4675c27 --- /dev/null +++ b/alliance-tutorials.patch @@ -0,0 +1,690 @@ +diff -Naur documentation/tutorials/place_and_route/tex/place_and_route.tex tutorials/place_and_route/tex/place_and_route.tex +--- documentation/tutorials/place_and_route/tex/place_and_route.tex 2004-10-16 14:51:56.000000000 +0200 ++++ tutorials/place_and_route/tex/place_and_route.tex 2007-08-02 18:37:05.000000000 +0200 +@@ -2,6 +2,7 @@ + % $Id: place_and_route.tex,v 1.5 2004/10/16 12:51:56 fred Exp $ + % $Log: place_and_route.tex,v $ + % Revision 1.5 2004/10/16 12:51:56 fred ++% Modified by Chitlesh GOORAH for Alliance release 5.0 (18/07/2007) + % Erasing the psfig include from the file, changed the font to 10 pt + % instead of 12 (sparing trees and not being payed by the thickness of + % my production) and changing font to charter since I got tired of +@@ -11,14 +12,14 @@ + \documentclass{article} + \usepackage[dvips]{graphics} + \usepackage[english]{babel} +-\usepackage{doublespace} ++\usepackage{setspace} + \usepackage{epsf} + \usepackage{fancybox} + \usepackage{fancyheadings} + \usepackage{float} + \usepackage{graphicx} + \usepackage{here} +-\usepackage{isolatin1} ++\usepackage[latin1]{inputenc} + \usepackage{charter} + \usepackage{picinpar} + \usepackage{rotate} +@@ -92,7 +93,8 @@ + \date{} + \author{ + Frederic AK\hspace{2cm} Kai-shing LAM\\ +-Modified by LJ ++Modified by LJ\\ ++Modified by Chitlesh GOORAH (18/07/2007) + } + + \maketitle +@@ -121,7 +123,7 @@ + + {2.2} inverter Diagram + +-{2.3} Buffer diagram ++{2.3} Buffer diagram + + {2.4} sxlib gauge + +@@ -149,8 +151,8 @@ + + {3.8} pads placement + \\ +-{4} {\bf Annexes} +- ++{4} {\bf Annexes} ++ + \newpage + {\huge + PART 3 : } +@@ -158,9 +160,9 @@ + {\huge + Place and route + } +- ++ + All the files used in this part are located under \\ +-\texttt{/tutorial/place\_and\_route/src} directory.\\ ++\texttt{/usr/share/doc/alliance-doc-5.0/tutorial/place\_and\_route/src} directory.\\ + This directory contents three subdirectories and one Makefile : + + \begin{itemize}\itemsep=-.8ex +@@ -169,7 +171,7 @@ + \item inv + \begin{itemize}\itemsep=-.8ex + \item Makefile +- \item inv.vbe : behavioral description ++ \item inv.vbe : behavioral description + \item inv\_x1.ap : inverter cell design using GRAAL + \end{itemize} + \item buffer +@@ -178,7 +180,7 @@ + \item buffer.vbe : behavioral description + \item buf\_x2.ap : buffer cell design using GRAAL + \end{itemize} +-\item amd2901 ++\item amd2901 + \begin{itemize}\itemsep=-.8ex + \item Makefile + \item amd2901\_ctl.vbe : behavioral description of control +@@ -212,9 +214,9 @@ + The predefined cells concepts, model and + hierarchy will be introduced .\\ + Then this tutorial contain the methodology used in Alliance to produce +-the amd2901 physical layout that you conceived in Alliance Tutorial ++the amd2901 physical layout that you conceived in Alliance Tutorial + PART 2 "Synthesis" (All the documents used will be provided to you). +- ++ + \newpage + %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% + +@@ -225,7 +227,7 @@ + %------------------------ + The library can be enriched by new cells with {\bf GRAAL} editor .\\ + { \bf GRAAL } is an editor of \/{\underline{symbolic }} {\it +-layout} integrating the drawing rules checker {\bf DRUC} and also ++layout} integrating the drawing rules checker {\bf DRUC} and also + a net extractor. + The first part here aims to draw an inverter cell inv\_x1 in the shape + of a predefined cell of sxlib complyiant with provided +@@ -236,7 +238,7 @@ + Some tools of Alliance use a particular technological + environment. It is indicated by the environment variable {\bf + RDS\_TECHNO\_NAME} which must be set to +-{\bf/alliance/etc/cmos.rds} ++{\bf/etc/alliance/cmos.rds} + + \subsubsection{GRAAL} + %-------------------- +@@ -244,7 +246,7 @@ + with the menu { \bf CREATE }: + \begin{itemize}\itemsep=-.4ex + \item The ''instance'' (physical cells importation) +-\item The abutment boxes which define the cell limits ++\item The abutment boxes which define the cell limits + \item Segments: DiffN, DiffP, Poly, Alu1, Alu2... CAluX is used to specify + a possible rectangle area for the connectors. + \item VIAs or contacts: ContDiffN, ContDiffP, ContPoly and +@@ -254,10 +256,10 @@ + \end{itemize} + + {\bf GRAAL} uses the environment variable {\bf +-GRAAL\_TECHNO\_NAME}. It must be set to {\bf/alliance/etc/cmos.graal}. ++GRAAL\_TECHNO\_NAME}. It must be set to {\bf/etc/alliance/cmos.graal}. + + Steps to follow to create a sxlib cell by respecting the sxlib gauge : +-( cf 2.4 Sxlib gauge ) ++( cf 2.4 Sxlib gauge ) + \begin{itemize}\itemsep=-.4ex + \item place the supply Vdd and Vss using the menu CREATE->Segment + \item place the VIAs using the menu CREATE->VIA +@@ -267,7 +269,7 @@ + \item link the transistor P and the transistor N with the Poly segment using the menu CREATE->Segment + \item supply each transistor by linking them with Ndiff and Pdiff segments and VIAs contacts + \item define the cell limit with an abutment box using the menu CREATE->Abutment Box +-\end{itemize} ++\end{itemize} + + \subsubsection{COUGAR} + %-------------------- +@@ -276,7 +278,7 @@ + with the format { \bf ap }. + To extract a netlist at transistor level, use the following command : + \begin{commandline} +- > cougar -t file1 file2 ++ > cougar -t file1 file2 + \end{commandline} + + { \bf COUGAR } uses the environment variables { \bf MBK\_IN\_PH } +@@ -286,14 +288,14 @@ + the following environment variables: \\ + + \begin{commandline} +- > MBK_IN_PH = ap +- > export MBK_IN_PH +- > MBK_OUT_LO = spi ++ > MBK_IN_PH = ap ++ > export MBK_IN_PH ++ > MBK_OUT_LO = spi + > export MBK_OUT_LO + \end{commandline} + + \begin{commandline} +- > cougar -t circuit circuit ++ > cougar -t circuit circuit + \end{commandline} + + The resulting spice netlist can be then simulated using a SPICE simulator and a given +@@ -301,7 +303,7 @@ + + The schematic of the transistor neltlist can also be displayed using {\bf XSCH} : + \begin{commandline} +- > xsch -I spi -l circuit ++ > xsch -I spi -l circuit + \end{commandline} + + \subsection{inverter Diagram} +@@ -341,12 +343,12 @@ + + \begin{itemize}\itemsep=-.4ex + \item The sxlib cells have whole 50 lambdas height and a multiple of 5 lambdas width. +-\item The supply Vdd and Vss are carried out in Calu1; they have 6 lambdas width and are ++\item The supply Vdd and Vss are carried out in Calu1; they have 6 lambdas width and are + horizontally placed in top and bottom of the cell. + \item The transistors P are placed close to the Vdd while transistors N are placed close + to the Vss. + \item Box N must have 24 lambdas height . +-\item The special segments CAluX (CAlu1, Calu2, CAlu3...) form the cell interface (PORT\_MAP) ++\item The special segments CAluX (CAlu1, Calu2, CAlu3...) form the cell interface (PORT\_MAP) + and play the role of ''flat'' connectors. They must be placed on a 5x5 grid and can be anywhere in the cell. + \item The special segments TAlux (TAlu1, TAlu2...) are used to indicate the obstacles for the + router. When you want to protect AluX segment, it is necessary to cover them +@@ -356,7 +358,7 @@ + \item The boxes N and P must be polarized. { \bf It should be respectively connected to Vdd and Vss }. + \end{itemize} + +-You will find a summary of these constraints on the diagram ++You will find a summary of these constraints on the diagram + \ref{Fig:gabarit}: + + \begin{figure}[H]\centering +@@ -443,7 +445,7 @@ + \begin{itemize}\itemsep=-.4ex + \item The data-path contains the regular parts of Amd2901, the registers + and the arithmetic logic unit. +-\item The control part contains irregular logic, ++\item The control part contains irregular logic, + the instructions decoding and the `` flags '' computation. + \end{itemize} + +@@ -463,7 +465,7 @@ + The data-path and the control part will be placed and routed together and not separately. \\ + You will use also {\bf lvx}, the netlists comparator. When the + system is too complex it is difficult to use {\bf proof}, the +-formal comparator (calculations too long). A netlists comparison ++formal comparator (calculations too long). A netlists comparison + then is used. Test the two methods ({\bf proof} and {\bf + lvx}). + +@@ -499,7 +501,7 @@ + %--------------------------------- + + Generally, the file describing a netlist must have the same +-name as the one describing its physical layout ++name as the one describing its physical layout + (but of course the file extention is not the same). + The file amd2901\_dpt.vst (LOFIG) must correspond to the file + amd2901\_dpt.ap (PHFIG). The same applies to the file +@@ -517,7 +519,7 @@ + \noindent GENLIB\_SAVE\_LOFIG()\\ + + This permits to generate a structural description in a { \bf +-VST } file. At the same time, { \bf genlib } will generate ++VST } file. At the same time, { \bf genlib } will generate + physical descriptions of each column in { \bf AP } files. + It is up to you to place these columns explicitly. \\ + Edit again the file amd2901\_dpt.c and include the lines :\\ +@@ -526,7 +528,7 @@ + \noindent /* add here you placement directives !! */ \\ + \noindent GENLIB\_SAVE\_PHFIG()\\ + +-For this placement task, you have the following {\bf GENLIB} functions : ++For this placement task, you have the following {\bf GENLIB} functions : + + \begin{itemize}\itemsep=-.4ex + \item GENLIB\_PLACE() +@@ -540,12 +542,12 @@ + \end{itemize} + + Use {\bf GENLIB} manual. The placement of the data-path columns +-should not be done randomly. The routing feasibility and the quality ++should not be done randomly. The routing feasibility and the quality + of the resulting layout depends on it !\\ + + Use genlib to generate all: + \begin{commandline} +- >genlib amd2901_dpt ++ >genlib amd2901_dpt + \end{commandline} + + The figure \ref{Fig:preplacement} summarizes the followed process: +@@ -568,12 +570,12 @@ + %--------------------------------- + + In the same manner, edit agin the file amd2901\_core.c and insert +- data-path explicitly. You should not place the part controls. ++ data-path explicitly. You should not place the part controls. + This one exists only in the form of a structural description. +-It is the placer { \bf ocp } that will undertake some ++It is the placer { \bf ocp } that will undertake some + (during the placement of the heart { \bf ocp } detects which are the +-cells not placed and supplements the placement). +-Nevertheless you should reserve enough space for the cells placement ++cells not placed and supplements the placement). ++Nevertheless you should reserve enough space for the cells placement + { \bf to the top } of the data-path. + + Include the lines:\\ +@@ -583,28 +585,28 @@ + + Space necessary to the placer to place the cells of the control part + will be determined by successive approximations. You will have to +-adjust dimensions of the heart abutment box ++adjust dimensions of the heart abutment box + (GENLIB\_DEF\_AB()). + Use the command: + + \begin{commandline} +- > genlib amd2901_core ++ > genlib amd2901_core + \end{commandline} + + and + \begin{commandline} +- > ocp -partial amd2901_core -ioc amd2901_core amd2901_core amd2901_core_p ++ > ocp -partial amd2901_core -ioc amd2901_core amd2901_core amd2901_core_p + \end{commandline} + + The option {\bf -- partial} indicates that you give a partial +-placement of the data-path. ++placement of the data-path. + The option { \bf -- ioc } permits to specify a placement for external +-connectors described in a .ioc file. +-This file, amd2901\_core.ioc is provided to you (Modify it according ++connectors described in a .ioc file. ++This file, amd2901\_core.ioc is provided to you (Modify it according + to your predefined placement. + The connectors must be in the north and in the south of your circuit). + +-The third argument is the netlist heart filename, the fourth is the ++The third argument is the netlist heart filename, the fourth is the + name of the { \bf .ap } resulting file. + + The figure \ref{Fig:placement} summarize the followed process: +@@ -620,7 +622,7 @@ + Routing the heart by using { \bf NERO } in the following way: + + \begin{commandline} +- > nero -v -3 -p amd2901_core_p amd2901_core amd2901_core ++ > nero -v -3 -p amd2901_core_p amd2901_core amd2901_core + \end{commandline} + + %The option { \bf -- place } indicates that you transmit a placement, that of the heart. +@@ -639,10 +641,10 @@ + \subsection{pads placement} + %--------------------------------- + +-The core of the AMD2001 is completed. ++The core of the AMD2001 is completed. + We focus now on the chip with pads description, placement and routing. + Those pads allow the connection of the inputs/outputs of the core with +-the external nets of the chip. ++the external nets of the chip. + + The tool {\bf ring} instanciates pads that has been specified + in a {\bf vst} netlist, place them using a file { \bf .rin } +@@ -662,7 +664,7 @@ + Name it `` amd2902\_chip.rin '' and apply the command \\ + + \begin{commandline} +- > ring amd2901_chip amd2901_chip ++ > ring amd2901_chip amd2901_chip + \end{commandline} + + We will validate the work of {\bf ring} with the tools { \bf druc +@@ -682,7 +684,7 @@ + > cougar -f amd2901_chip + \end{commandline} + +-Compare two netlists : ++Compare two netlists : + \begin{commandline} + > lvx vst al amd2901_chip amd2901_chip -f + \end{commandline} +@@ -698,7 +700,7 @@ + the circuit on the level transistor: \\ + + \begin{commandline} +-> cougar -t amd2901_chip amd2901_chip ++> cougar -t amd2901_chip amd2901_chip + \end{commandline} + \\ + +@@ -706,7 +708,7 @@ + \begin{commandline} + > make view_ctl_logic + \end{commandline} +- ++ + If you want to see the data-path physical layout: + \begin{commandline} + > make view_dpt_physic +@@ -723,7 +725,7 @@ + \begin{commandline} + > make view_chip_simulation + \end{commandline} +- ++ + %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% + + %\newpage + +diff -Naur documentation/tutorials/simulation/tex/simulation.tex tutorials/simulation/tex/simulation.tex +--- documentation/tutorials/simulation/tex/simulation.tex 2004-10-16 14:52:05.000000000 +0200 ++++ tutorials/simulation/tex/simulation.tex 2007-07-18 15:47:13.000000000 +0200 +@@ -2,6 +2,7 @@ + % $Id: simulation.tex,v 1.5 2004/10/16 12:52:05 fred Exp $ + % $Log: simulation.tex,v $ + % Revision 1.5 2004/10/16 12:52:05 fred ++% Modified by Chitlesh GOORAH for Alliance release 5.0 (18/07/2007) + % Erasing the psfig include from the file, changed the font to 10 pt + % instead of 12 (sparing trees and not being payed by the thickness of + % my production) and changing font to charter since I got tired of +@@ -13,13 +14,13 @@ + \documentclass{article} + \usepackage[dvips]{graphics} + \usepackage[english]{babel} +-\usepackage{doublespace} ++\usepackage{setspace} + \usepackage{fancybox} + \usepackage{fancyheadings} + \usepackage{float} + \usepackage{graphicx} + \usepackage{here} +-\usepackage{isolatin1} ++\usepackage[latin1]{inputenc} + \usepackage{charter} + \usepackage{picinpar} + \usepackage{rotate} +@@ -96,7 +97,8 @@ + \date{} + + \author{Frederic AK \hspace{2cm} Kai-shing LAM\\ +-Modified by LJ ++Modified by LJ\\ ++Modified by Chitlesh GOORAH (18/07/2007) + } + + \maketitle +@@ -171,7 +173,7 @@ + } + + All the files used in this part are located in the \\ +-\texttt{/tutorial/simulation/src} directory.\\ ++\texttt{/usr/share/doc/alliance-doc-5.0/tutorial/simulation/src} directory.\\ + This directory contains two subdirectories and one Makefile : + \begin{itemize} + \item The Makefile allows you to validate automatically the entire simulation part +@@ -626,13 +628,13 @@ + \bf SXLIB }. For the functionality of the various cells and their + interface, the sxlib man is available. The behavioral + description of each cell is present in \\ +-{\bf /alliance/cells/sxlib }. ++{\bf \$ALLIANCE\_TOP/cells/sxlib }. + + You must set the environment variable { \bf MBK\_CATA\_LIB } + to be able to reach these cells. + + \begin{commandline} +- > MBK_CATA_LIB=/alliance/cells/sxlib ++ > MBK_CATA_LIB=$ALLIANCE_TOP/cells/sxlib + > export MBK_CATA_LIB + \end{commandline} + +diff -Naur documentation/tutorials/start/start.tex tutorials/start/start.tex +--- documentation/tutorials/start/start.tex 2004-10-16 14:52:13.000000000 +0200 ++++ tutorials/start/start.tex 2007-07-18 13:28:50.000000000 +0200 +@@ -4,12 +4,13 @@ + % Original Version 1.0 in text form by Francois Pecheux + % Version for Alliance releases 2.0 and up by Frederic Petrot + % Modified by czo for Alliance release 4.0 (01/2000) +-% TODO : no fully working, needs some adjustements ++% Modified by Chitlesh GOORAH for Alliance release 5.0 (18/07/2007) ++% TODO : no fully working, needs some adjustments + % $Id: start.tex,v 1.5 2004/10/16 12:52:13 fred Exp $ + % + %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% + \documentclass{article} +-\usepackage{charter,doublespace,here,fancybox} ++\usepackage{charter,setspace,here,fancybox} + \textwidth 15cm + \textheight 23cm + \oddsidemargin +0.75cm +@@ -20,7 +21,7 @@ + % Since it is tt, any char is fine + %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% + \newlength{\verbatimbox} +-\settowidth{\verbatimbox}{\scriptsize\tt ++\settowidth{\verbatimbox}{\scriptsize\tt + xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx + } + \newenvironment{framedverbatim} +@@ -33,8 +34,8 @@ + \begin{Sbox}\begin{minipage}{.979\textwidth}\begin{Verbatim}}% + {\end{Verbatim}\end{minipage}\end{Sbox}\setlength{\shadowsize}{2pt}% + \shadowbox{\TheSbox}\normalsize\par\noindent} +- +- ++ ++ + + %%%%%%%%%%%%%%%%%%%%%%%% + % +@@ -56,9 +57,9 @@ + \begin{quote} + \em + These tutorials introduce the design flow to be used in the +-\textbf{Alliance} CAD framework for the design and verification of a ++\textbf{Alliance} CAD framework for the design and verification of a + standard cells circuit, including the pads. +-Each step of the desgin flow is supported by one or more specific ++Each step of the desgin flow is supported by one or more specific + tools, whose use is briefly explained in the tutorials. + + These texts are meant to be simple and comprehensive, and are to be used +@@ -77,7 +78,7 @@ + proceeding, as it describes the main steps of the design conceptually. + + \section{Before starting} +-In those tutorials you will learn the practical use of the following ++In those tutorials you will learn the practical use of the following + \textbf{Alliance} tools : + + In the first tutorial (simulation/ directory) : +@@ -103,30 +104,32 @@ + In the third tutorial (synthesis/ directory) : + \begin{itemize} + \item \textbf{syf} : Finite state machine synthesizer. +-\item \textbf{boom} : Boolean optimization of a logic level behavioral ++\item \textbf{boom} : Boolean optimization of a logic level behavioral + description (VHDL data flow). +-\item \textbf{boog} : Mapping of a behavioral descriptiononto a standard cell ++\item \textbf{boog} : Mapping of a behavioral descriptiononto a standard cell + library. +-\item \textbf{loon} : Fanout optimizer, global optimizer and timing analyser of ++\item \textbf{loon} : Fanout optimizer, global optimizer and timing analyser of + \item \textbf{scapin} : Scan Path insertion + \item \textbf{xsch} : Graphical schematic viewer. + \end{itemize} + +-If you run a \texttt{c-like} shell, like \texttt{csh} or \texttt{tcsh}, ++If you run a \texttt{c-like} shell, like \texttt{csh} or \texttt{tcsh}, + try to run the following command : + + \begin{phraseverbatim} +-~alp/addaccu %-) source /alliance/etc/alc_env.csh ++~alp/addaccu %-) source /etc/profile.d/alc_env.csh + \end{phraseverbatim} + +-Otherwise, if you run a \texttt{sh-like} shell, try to run the following ++Otherwise, if you run a \texttt{sh-like} shell, try to run the following + command : + \begin{phraseverbatim} +-~alp/addaccu %-) source /alliance/alc_env.sh ++~alp/addaccu %-) source /etc/profile.d/alc_env.sh + \end{phraseverbatim} + \\ ++When a user logs in, these environment variables are automatically set from various places. ++\\ + Before we proceed to the tutorial, you must make sure that the +-\textbf{Alliance} tools are readilly available when invoking them at the ++\textbf{Alliance} tools are readilly available when invoking them at the + prompt. + The prompt in represented in the following text by the symbol~: + \begin{phraseverbatim} +@@ -136,7 +139,7 @@ + directory, and \texttt{\%-)} is supposed to give us courage! + + \section{Execution environment set up} +-Later, before you will start examining alliance tools, you will probably want ++Later, before you will start examining alliance tools, you will probably want + to know the environment variables setup. + To see it, please enter the following command : + +@@ -147,18 +150,21 @@ + \begin{figure}[H]\center\leavevmode + \begin{framedverbatim} + ~alp/addaccu %-) env | grep MBK +-MBK_OUT_PH=ap +-MBK_CATAL_NAME=CATAL ++MBK_IN_PH=ap + MBK_SCALE_X=100 ++MBK_CATAL_NAME=CATAL ++MBK_OUT_PH=ap ++MBK_OUT_LO=vst + MBK_VSS=vss +-MBK_CATA_LIB=.:/alliance/cells/sxlib:/alliance/cells/padlib +-MBK_WORK_LIB=. +-MBK_VDD=vdd + MBK_C4_LIB=./cellsC4 ++MBK_VDD=vdd ++MBK_TARGET_LIB=\$ALLIANCE\_TOP/cells/sxlib + MBK_IN_LO=vst +-MBK_IN_PH=ap +-MBK_TARGET_LIB=/alliance/cells/sxlib +-MBK_OUT_LO=vst ++MBK_WORK_LIB=. ++MBK_CATA_LIB=.:/usr/lib/alliance/cells/sxlib:/usr/lib/alliance/cells/dp_sxlib: ++/usr/lib/alliance/cells/rflib:/usr/lib/alliance/cells/ramlib: ++/usr/lib/alliance/cells/romlib:/usr/lib/alliance/cells/pxlib: ++/usr/lib/alliance/cells/padlib + \end{framedverbatim} + \caption{\label{mbk} \texttt{MBK} environment variables.} + \end{figure} +@@ -167,12 +173,12 @@ + variables are documented in each tutorial. + + \section{File Formats} +-One of the interesting features of \textbf{Alliance} is that different ++One of the interesting features of \textbf{Alliance} is that different + file formats can be used for both netlist and layout view. +-However, +-in the design methodology we wish to promote, some formats are ++However, ++in the design methodology we wish to promote, some formats are + recommended. +-The \texttt{vst}, structural \textbf{VHDL}, is dedicated to netlist ++The \texttt{vst}, structural \textbf{VHDL}, is dedicated to netlist + specification. + The \texttt{al} format is dedicated to extracted layout representation. + The \texttt{ap} format is the usual layout format. +diff -Naur documentation/tutorials/synthesis/src/amd2901/Makefile tutorials/synthesis/src/amd2901/Makefile +--- documentation/tutorials/synthesis/src/amd2901/Makefile 2002-07-25 14:50:18.000000000 +0200 ++++ tutorials/synthesis/src/amd2901/Makefile 2007-07-18 19:34:53.000000000 +0200 +@@ -2,17 +2,17 @@ + all: EXAMPLE VAR CATAL02 res.pat + + +-VAR: ++VAR: + MBK_IN_LO=vst;export MBK_IN_LO ;\ +- MBK_CATA_LIB=/asim/alliance/cells/sxlib;export MBK_CATA_LIB ++ MBK_CATA_LIB=$ALLIANCE_TOP/cells/sxlib;export MBK_CATA_LIB + + CATAL01: +- echo amd2901_ctl C >CATAL ++ echo amd2901_ctl C >CATAL + echo amd2901_dpt C >>CATAL + + CATAL02: + echo amd2901_dpt C >CATAL +- ++ + EXAMPLE: + genlib circuit + +@@ -38,7 +38,7 @@ + + res2.pat: amd2901_chip.vst pattern.pat amd2901_core.vst CATAL + asimut amd2901_chip pattern res2 +- touch amd2901_chip.vst ++ touch amd2901_chip.vst + + clean : + rm -f Makefile-* \ +diff -Naur documentation/tutorials/synthesis/tex/synthesis.tex tutorials/synthesis/tex/synthesis.tex +--- documentation/tutorials/synthesis/tex/synthesis.tex 2004-10-16 14:52:17.000000000 +0200 ++++ tutorials/synthesis/tex/synthesis.tex 2007-07-18 15:46:54.000000000 +0200 +@@ -2,6 +2,7 @@ + % $Id: synthesis.tex,v 1.4 2004/10/16 12:52:17 fred Exp $ + % $Log: synthesis.tex,v $ + % Revision 1.4 2004/10/16 12:52:17 fred ++% Modified by Chitlesh GOORAH for Alliance release 5.0 (18/07/2007) + % Erasing the psfig include from the file, changed the font to 10 pt + % instead of 12 (sparing trees and not being payed by the thickness of + % my production) and changing font to charter since I got tired of +@@ -11,13 +12,13 @@ + \documentclass{article} + \usepackage[dvips]{graphics} + \usepackage[english]{babel} +-\usepackage{doublespace} ++\usepackage{setspace} + \usepackage{fancybox} + \usepackage{fancyheadings} + \usepackage{float} + \usepackage{graphicx} + \usepackage{here} +-\usepackage{isolatin1} ++\usepackage[latin1]{inputenc} + \usepackage{charter} + \usepackage{picinpar} + \usepackage{rotate} +@@ -89,7 +90,8 @@ + \date{} + \author{ + Ak Frederic\hspace{2cm} Lam Kai-shing\\ +-Modified by LJ ++Modified by LJ\\ ++Modified by Chitlesh GOORAH (18/07/2007) + } + + \maketitle +@@ -220,7 +222,7 @@ + } + + All the files used in this part are located under \\ +-\texttt{/tutorial/synthesis/src} directory.\\ ++\texttt{/usr/share/doc/alliance-doc-5.0/tutorial/synthesis/src} directory.\\ + This directory contents four subdirectories and one Makefile : + \begin{itemize}\itemsep=-.8ex + diff --git a/alliance.fedora b/alliance.fedora new file mode 100644 index 0000000..add52ad --- /dev/null +++ b/alliance.fedora @@ -0,0 +1,44 @@ + +=== License === +Alliance CAD system is distributed under the GNU license v2. +There is no more or less limitation than the ones defined by the GPL v2. + +You are kindly requested to mention +" Designed with alliance (c) LIP6, Université Pierre et Marie Curie" +so as to spread the word about "alliance CAD system" and its development team. + + +=== Proper Usage === + +It is recommended to source the alc_env.sh or alc_env.csh before using alliance. + +source /etc/profile.d/alc_env.sh +(for example) + +When a user logs in, environment variables on +/etc/profile.d/alc_env.sh +are set will be automatically sourced. + + +=== Overview === + +A general overview of Alliance CAD System can be found here: +/usr/share/doc/alliance-doc-5.0/design-flow/index.html +(available on the alliance-doc rpm) + +=== Tutorials === + +The tutorials can be found at /usr/share/doc/alliance-doc-5.0/tutorials/ +(available on the alliance-doc rpm) + +It is recommended to first read /usr/share/doc/alliance-doc-5.0/overview.pdf + 1. start.pdf + 2. simulation.pdf + 3. synthesis.pdf + 4. place_and_route.pdf + + +========================================================================================= +Chitlesh Goorah (chitlesh AT fedoraproject DOT org) +Alliance development team and other contributors (ASIM/LIP6/UPMC) +alliance-users AT asim DOT lip6 DOT fr diff --git a/alliance.spec b/alliance.spec new file mode 100644 index 0000000..992d486 --- /dev/null +++ b/alliance.spec @@ -0,0 +1,412 @@ +%define prefix %{_libdir}/%{name} +%define snapshot 20070718 + +Name: alliance +Version: 5.0 +Release: 7.%{snapshot}snap%{?dist} +Summary: Alliance VLSI CAD Sytem + +License: GPL +Group: Applications/Engineering + +Source: http://www-asim.lip6.fr/pub/alliance/distribution/5.0/%{name}-%{version}-%{snapshot}.tar.gz +URL: http://www-asim.lip6.fr/recherche/alliance/ + +Patch1: alliance-examples.patch +Patch2: alliance-run.patch +Patch3: alliance-perms.patch +Patch4: alliance-tutorials.patch +Patch5: alliance-log3.patch + +Source1: xsch.desktop +Source2: dreal.desktop +Source3: xpat.desktop +Source4: xfsm.desktop +Source5: xvpn.desktop +Source6: graal.desktop + +Source7: alliance.fedora + +# Chitlesh's donated pictures to alliance +Source8: graal.png +Source9: dreal.png +Source10: xvpn.png +Source11: xfsm.png +Source12: xpat.png +Source13: xsch.png + +BuildRoot: %{_tmppath}/%{name}-%{version}-%{release}-root-%(%{__id_u} -n) +BuildRequires: lesstif-devel libXt-devel byacc desktop-file-utils bison +BuildRequires: libXp-devel libXpm-devel libstdc++-devel flex m4 +BuildRequires: transfig ghostscript tetex-latex + + +%description +Alliance is a complete set of free CAD tools and portable libraries for +VLSI design. It includes a VHDL compiler and simulator, logic synthesis +tools, and automatic place and route tools. + +A complete set of portable CMOS libraries is provided, including a RAM +generator, a ROM generator and a data-path compiler. + +Alliance is the result of more than ten years effort spent at ASIM department +of LIP6 laboratory of the Pierre et Marie Curie University (Paris VI, France). + +Alliance has been used for research projects such as the 875 000 transistors +StaCS superscalar microprocessor and 400 000 transistors IEEE Gigabit HSL +Router. + +You are kindly requested to mention +" Designed with alliance (c) LIP6, Université Pierre et Marie Curie" +so as to spread the word about "alliance CAD system" and its development team. + +Alliance provides CAD tools covering most of all the digital design flow: + + * VHDL Compilation and Simulation + * Model checking and formal proof + * RTL and Logic synthesis + * Data-Path compilation + * Macro-cells generation + * Place and route + * Layout edition + * Netlist extraction and verification + * Design rules checking + + +%package doc +Summary: Alliance VLSI CAD Sytem - Documentations +Group: Applications/Engineering +Requires: %{name} = %{version}-%{release} +Requires: gnuplot + + +%description doc +Documentation and tutorials for the Alliance VLSI CAD Sytem. + + +%prep +%setup -q + +%{__cp} -p %{SOURCE7} . + +# using the formal %%{_sysconfdir} in favor of $${ALLIANCE_TOP}/etc +sed -i "s|sysconfdir='\${prefix}/etc'|sysconfdir=%{_sysconfdir}/%{name}|" configure + +sed -i "s|\${ALLIANCE_TOP}/etc|%{_sysconfdir}/%{name}|" {xfsm,xvpn,xpat,xsch}/src/Makefile* + +sed -i "s|etcdir=\$(prefix)/etc|etcdir=%{_sysconfdir}/%{name}|" \ + {attila,dreal,elp,graal,mbkspice,rds,scapin,sea,xfsm,xvpn,xpat,xsch}/etc/Makefile.am + +sed -i "s|etcdir = \$(prefix)/etc|etcdir = %{_sysconfdir}/%{name}|" \ + {attila,dreal,elp,graal,mbkspice,rds,scapin,sea,xfsm,xvpn,xpat,xsch}/etc/Makefile.in + +sed -i "s|etcdir=\$(prefix)/etc|etcdir=%{_sysconfdir}/profile.d|" distrib/etc/Makefile.am +sed -i "s|etcdir = \$(prefix)/etc|etcdir = %{_sysconfdir}/profile.d|" distrib/etc/Makefile.in + + +%patch1 -p0 -b .examples +%patch2 -p0 -b .run +# fixing permissions +%patch3 -p0 -b .perms + + +## Updating old tutorials +%patch4 -p0 -b .tutorials + +pushd documentation/tutorials + for folder in place_and_route/tex simulation/tex start synthesis/tex; do + pushd $folder + %{__make} + popd + done +popd + +#conflicts with man-pages and is a duplicate of log.1.gz +%patch5 -p0 -b .duplicate + + +# removing useless copyrighted (by Cadence) lines from the examples +# and even in alliance-run +# https://www-asim.lip6.fr/wws/arc/alliance-users/2007-07/msg00006.html +pushd documentation/alliance-examples + for cadence in adder4/adder4.ioc divcas4/divcas4.ioc mipsR3000/sce/mips_core.ioc \ + amd2901/amd2901_core.ioc amd2901-vasy/amd2901.ioc ; do + sed -i "s|# Copyright (c) 1997 by Cadence. All rights reserved.|#|" $cadence + done +popd + +# make sure the man pages are UTF-8... +for nonUTF8 in distrib/doc/alc_origin.1 alcban/man1/alcbanner.1 \ + loon/doc/loon.1 m2e/doc/man1/m2e.1 boog/doc/boog.1 ; do + %{_bindir}/iconv -f ISO-8859-1 -t utf-8 $nonUTF8 > $nonUTF8.conv + %{__mv} -f $nonUTF8.conv $nonUTF8 +done + +#wrong-file-end-of-line-encoding +sed -i 's/\r//' documentation/alliance-examples/mipsR3000/asm/* + + +%build + +export ALLIANCE_TOP=%{prefix} + +%configure --prefix=%{prefix} \ + --enable-alc-shared \ + --disable-static \ + --includedir=%{prefix}/include \ + --libdir=%{prefix}/lib \ + --bindir=%{prefix}/bin + +# disabling rpath +sed -i 's|^hardcode_libdir_flag_spec="\\${wl}--rpath \\${wl}\\$libdir"|hardcode_libdir_flag_spec=""|g' libtool +sed -i 's|^runpath_var=LD_RUN_PATH|runpath_var=DIE_RPATH_DIE|g' libtool + +# clean unused-direct-shlib-dependencies +sed -i -e 's! -shared ! -Wl,--as-needed\0!g' libtool + +# Is not parallel-build-safe +%{__make} + + +%install + +%{__rm} -rf %{buildroot} + +%{__make} INSTALL="install -p" DESTDIR=%{buildroot} install + + +# Set execution rights on the alc_env.* batchs and adjust ALLIANCE_TOP. +pushd %{buildroot}%{_sysconfdir}/profile.d + chmod 0644 alc_env.* + sed -i "s|@DATE@|`date`|" alc_env* + # fixing *** ERROR *** : Variable MBK_SPI_MODEL not found. + echo "MBK_SPI_MODEL=\$ALLIANCE_TOP/etc/spimodel.cfg; export MBK_SPI_MODEL" >> alc_env.sh + echo "setenv MBK_SPI_MODEL \"\${ALLIANCE_TOP}/etc/spimodel.cfg\"" >> alc_env.csh + #don't override $MANPATH + sed -i "s|\$ALLIANCE_TOP/man|\$MANPATH|" alc_env* + sed "s|ALLIANCE_TOP *= *\([^;]*\)|ALLIANCE_TOP=%{prefix}|" alc_env.sh + sed "s|setenv *ALLIANCE_TOP *\([^;]*\)|setenv ALLIANCE_TOP %{prefix}|" alc_env.csh +popd + + +# documentation +%{__cp} -pr %{buildroot}%{prefix}/doc/ . +%{__cp} -pr %{buildroot}%{prefix}/tutorials/ . +%{__cp} -pr %{buildroot}%{prefix}/examples/alliance-examples/ . + +%{__rm} -rf %{buildroot}%{prefix}/doc/ +%{__rm} -rf %{buildroot}%{prefix}/tutorials/ +%{__rm} -rf %{buildroot}%{prefix}/examples/ + +# correcting minor documentation details +sed -i "s|/bin/zsh|/bin/sh|" doc/alliance-run/bench.zsh + + +find %{buildroot} -name '*.la' -exec rm -f {} ';' + + +# Adding icons for the menus +%{__mkdir} -p %{buildroot}%{_datadir}/icons/hicolor/48x48/apps/ +%{__cp} -p %{SOURCE8} %{SOURCE9} %{SOURCE10} %{SOURCE11} %{SOURCE12} %{SOURCE13} \ + %{buildroot}%{_datadir}/icons/hicolor/48x48/apps/ + +# desktop files +for desktopfile in %{SOURCE1} %{SOURCE2} %{SOURCE3} %{SOURCE4} %{SOURCE5} %{SOURCE6}; do +desktop-file-install --vendor fedora \ + --add-category Engineering \ + --dir %{buildroot}%{_datadir}/applications/ \ + $desktopfile +done + + +## Makefiles and tex folder cleanups +pushd tutorials + for folder in place_and_route/tex simulation/tex start synthesis/tex; do + %{__rm} -rf $folder + done +popd + + +# Architecture independent files +%{__mkdir} -p %{buildroot}%{_datadir}/%{name}/ +%{__mv} %{buildroot}%{prefix}/cells %{buildroot}%{_datadir}/%{name}/ + + +# protecting hardcoded links +ln -sf ../../..%{_sysconfdir}/%{name} %{buildroot}%{prefix}/etc +ln -sf ../../..%{_datadir}/%{name}/cells %{buildroot}%{prefix}/cells + + +%{__mkdir} -p %{buildroot}%{_sysconfdir}/ld.so.conf.d/ +cat > %{buildroot}%{_sysconfdir}/ld.so.conf.d/%{name}.conf << EOF +# Alliance VLSI design system +%{prefix}/lib +EOF + + +# removing tools for compiling and installing Alliance tools +# These are for the packager (i.e me) and not for user +%{__rm} -f %{buildroot}%{_sysconfdir}/%{name}/attila.conf +%{__rm} -f %{buildroot}%{prefix}/bin/attila +%{__rm} -f %{buildroot}%{_datadir}/man/man1/attila* +%{__rm} -f doc/html/alliance/*attila.html +%{__rm} -f doc/pdf/attila.pdf + + + + +%post +/sbin/ldconfig +touch --no-create %{_datadir}/icons/hicolor || : +%{_bindir}/gtk-update-icon-cache --quiet %{_datadir}/icons/hicolor || : + + +%postun +/sbin/ldconfig +touch --no-create %{_datadir}/icons/hicolor || : +%{_bindir}/gtk-update-icon-cache --quiet %{_datadir}/icons/hicolor || : + + + +%clean +%{__rm} -rf %{buildroot} + +#These headers are useful for the _usage_ of the binaries +#without these headers some of the binaries will be broken by default + + +%files +%doc CHANGES LICENCE COPYING* FAQ alliance.fedora +%defattr(-,root,root,-) +%{prefix}/ +%{_datadir}/%{name} +%dir %{_sysconfdir}/%{name} +%config(noreplace) %{_sysconfdir}/%{name}/prol.elp +%config(noreplace) %{_sysconfdir}/%{name}/se_defaults.mac +%config(noreplace) %{_sysconfdir}/%{name}/spimodel.cfg +%config(noreplace) %{_sysconfdir}/%{name}/sxlib.scapin +%config %{_sysconfdir}/%{name}/cmos.* +%config %{_sysconfdir}/%{name}/*.par +%config %{_sysconfdir}/ld.so.conf.d/* +%{_datadir}/icons/hicolor/48x48/apps/* +%{_mandir}/man?/* +%{_datadir}/applications/fedora-*.desktop +%{_sysconfdir}/profile.d/alc_env.* + + + +%files doc +%doc doc/html/ +%doc doc/design-flow +%doc doc/pdf/*.pdf +%doc doc/overview/*.ps +%doc doc/overview/*.pdf +%doc tutorials/ +#Makefiles are present in alliance-examples/*. It is normal because +# * it gives the VLSI designer a template on how to create his own +# Makefile for alliance (VLSI designers normally don't know how to do so) +# * it is not part of the build, but part of the working environment of the user +%doc alliance-examples/ +%doc doc/alliance-run/ + + + +%changelog +* Sun Aug 12 2007 Chitlesh Goorah - 5.0-7.20070718snap +- moved Architecture independent files to %%{_datadir}/%%{name} +- Uses verbs in the comments line for desktop files + +* Thu Aug 02 2007 Chitlesh Goorah - 5.0-6.20070718snap +- chose libdir/alliance as prefix +- added new icons to the menus +- removed useless attila +- fixed MANPATH override + +* Sat Jul 28 2007 Chitlesh Goorah - 5.0-5.20070718snap +- fixed unused-direct-shlib-dependency and undefined-non-weak-symbol warnings + +* Tue Jul 24 2007 Chitlesh Goorah - 5.0-4.20070718snap +- removed X-Desktop-File-Install-Version=0.10 from desktop files +- moved the alc_env to /etc/profile.d +- updated to meet reviewer's statements - #248649 + +* Thu Jul 19 2007 Chitlesh Goorah - 5.0-3.20070718snap +- New upstream release which includes bug fixes + +* Wed Jul 18 2007 Chitlesh Goorah - 5.0-2.20060509snap +- minor fixes to the tutorials + added transfig ghostscript tetex-latex as BR +- corrected some hardcoded links in the scripts +- removed %%preun and updated alliance.fedora +- spec file updated to satisfy the review + +* Tue Jul 17 2007 Chitlesh Goorah - 5.0-1 +- prepared spec file for review and spec clean ups +- removed rm and ln from %%post and %%preun +- removed log.3.gz from mandir since it's a duplicate and conflicts with man-pages + +* Sat Jul 14 2007 Chitlesh Goorah - 5.0-0.7 +- since it is not parallel-build-safe, smp mflags are removed : (by wwoods) +- added missing BR : flex : (by wwoods) +- added missing BR : bison: (by rdieter) + +* Fri Jul 13 2007 Chitlesh Goorah - 5.0-0.6 +- removing useless copyrighted lines from .ioc files +- added alliance.fedora among the %%doc + +* Thu Jul 12 2007 Chitlesh Goorah - 5.0-0.5 +- removing copyrighted materials +- patching the remaining examples so that they will still be valid under another folder + +* Wed Jul 04 2007 Chitlesh Goorah - 5.0-0.4 +- removing unwanted debug duplicates + +* Wed May 02 2007 Chitlesh Goorah - 5.0-0.3 +- added desktop files + +* Wed Feb 14 2007 Chitlesh Goorah - 5.0-0.2 +- fixing documentations + +* Wed Dec 13 2006 Chitlesh Goorah - 5.0-0.1 +- Initial package + +* Thu Feb 17 2005 Jean-Paul.Chaput +- Synch with current version: bug & compliance with gcc 3.4.x. + +* Fri Jul 16 2004 Jean-Paul.Chaput +- Added Tutorial sub-package (now managed by autoconf/automake). +- Removed release tag, must be given at compile time using the + --define command line argument of rpmbuild (see mkdistrib). + +* Sat Nov 15 2003 Jean-Paul.Chaput +- assert is now in assert.h, patch mut.h to include it if + GCC_VERSION >= 3003 (gcc >= 3.3.x). + +* Sat Oct 18 2003 Jean-Paul.Chaput +- Synched with 2003/10/18 version. +- Missing depcomp : added "--add-missing --copy" to the individual + packages in autostuff, so the first who needs depcomp will add + it at top level. + +* Sun Oct 13 2002 Jean-Paul.Chaput +- autoconf m4 macros moved back in the Alliance source tree to avoid + re-declaration on our development computers (on which the macros + are in teh source tree). +- Adopt the versioning scheme from czo. +- Try to switch to dynamic libraries. + +* Wed Jul 17 2002 Jean-Paul.Chaput +- Moved autoconf m4 macros to /usr/share/aclocal. +- Synched with the current CVS version of Alliance. + +* Fri May 31 2002 Jean-Paul.Chaput +- GenPat added. +- GenLib docs added. +- seplace/seroute/sea bug fixes. + +* Thu May 16 2002 Jean-Paul.Chaput +- Corrected buggy substitution of ALLIANCE_TOP in alc_env.csh. +- Remove the alc_env.* scripts in "/etc/profile.d" only if this + is the last package to be removed. + +* Mon May 6 2002 Jean-Paul.Chaput +- Initial packaging for release 5.0 (alpha stage). diff --git a/dreal.desktop b/dreal.desktop new file mode 100644 index 0000000..6fc223c --- /dev/null +++ b/dreal.desktop @@ -0,0 +1,10 @@ +[Desktop Entry] +Encoding=UTF-8 +Name=Alliance: Dreal +Exec=dreal +Icon=dreal.png +Type=Application +Terminal=false +GenericName=Alliance +Categories=Education;Science; +Comment=View the Real layout \ No newline at end of file diff --git a/dreal.png b/dreal.png new file mode 100644 index 0000000..50e608a Binary files /dev/null and b/dreal.png differ diff --git a/graal.desktop b/graal.desktop new file mode 100644 index 0000000..5f4b562 --- /dev/null +++ b/graal.desktop @@ -0,0 +1,10 @@ +[Desktop Entry] +Encoding=UTF-8 +Name=Alliance: Graal +Exec=graal +Icon=graal.png +Type=Application +Terminal=false +GenericName=Alliance +Categories=Education;Science; +Comment=Edits physical layouts \ No newline at end of file diff --git a/graal.png b/graal.png new file mode 100644 index 0000000..fdd2a03 Binary files /dev/null and b/graal.png differ diff --git a/sources b/sources index e69de29..5716e50 100644 --- a/sources +++ b/sources @@ -0,0 +1 @@ +917f4493c09f6f5c49d5a606a5e9bbd8 alliance-5.0-20070718.tar.gz diff --git a/xfsm.desktop b/xfsm.desktop new file mode 100644 index 0000000..45bd88f --- /dev/null +++ b/xfsm.desktop @@ -0,0 +1,10 @@ +[Desktop Entry] +Encoding=UTF-8 +Name=Alliance: Xfsm +Exec=xfsm +Icon=xfsm.png +Type=Application +Terminal=false +GenericName=Alliance +Categories=Education;Science; +Comment=View Finite State Machines \ No newline at end of file diff --git a/xfsm.png b/xfsm.png new file mode 100644 index 0000000..414f153 Binary files /dev/null and b/xfsm.png differ diff --git a/xpat.desktop b/xpat.desktop new file mode 100644 index 0000000..f60f580 --- /dev/null +++ b/xpat.desktop @@ -0,0 +1,10 @@ +[Desktop Entry] +Encoding=UTF-8 +Name=Alliance: Xpat +Exec=xpat +Icon=xpat.png +Type=Application +Terminal=false +GenericName=Alliance +Categories=Education;Science; +Comment=View the Patterns \ No newline at end of file diff --git a/xpat.png b/xpat.png new file mode 100644 index 0000000..3957935 Binary files /dev/null and b/xpat.png differ diff --git a/xsch.desktop b/xsch.desktop new file mode 100644 index 0000000..f722f45 --- /dev/null +++ b/xsch.desktop @@ -0,0 +1,10 @@ +[Desktop Entry] +Encoding=UTF-8 +Name=Alliance: Xsch +Exec=xsch +Icon=xsch.png +Type=Application +Terminal=false +GenericName=Alliance +Categories=Education;Science; +Comment=View the Schematic \ No newline at end of file diff --git a/xsch.png b/xsch.png new file mode 100644 index 0000000..fc180e3 Binary files /dev/null and b/xsch.png differ diff --git a/xvpn.desktop b/xvpn.desktop new file mode 100644 index 0000000..e0a651e --- /dev/null +++ b/xvpn.desktop @@ -0,0 +1,10 @@ +[Desktop Entry] +Encoding=UTF-8 +Name=Alliance: Xvpn +Exec=xvpn +Icon=xvpn.png +Type=Application +Terminal=false +GenericName=Alliance +Categories=Education;Science; +Comment=View the Petri Nets \ No newline at end of file diff --git a/xvpn.png b/xvpn.png new file mode 100644 index 0000000..30c25db Binary files /dev/null and b/xvpn.png differ