From 90e4143735e4d594710cda790f0b815eec6d2c59 Mon Sep 17 00:00:00 2001 From: Ralf Corsépius Date: Mar 01 2016 18:34:42 +0000 Subject: Rework spec. - Add upstream changes. - Rework package configuration. - Introduce *-devel. --- diff --git a/0000-alliance-5.1.1-git10a7b7e.patch b/0000-alliance-5.1.1-git10a7b7e.patch new file mode 100644 index 0000000..78be246 --- /dev/null +++ b/0000-alliance-5.1.1-git10a7b7e.patch @@ -0,0 +1,32518 @@ +diff --git a/alliance/src/README b/alliance/src/README +index d769dcd..c4d784c 100644 +--- a/alliance/src/README ++++ b/alliance/src/README +@@ -1,5 +1,5 @@ + # Alliance VLSI CAD System +-# Copyright (C) 1990, 2002 ASIM/LIP6/UPMC ++# Copyright (C) 1990, 2016 UPMC + # + # Home page : http://asim.lip6.fr/recherche/alliance/ + # E-mail : mailto:alliance-users@asim.lip6.fr +@@ -13,6 +13,7 @@ + This file discuss about installation of Alliance on UNIX machines. + + ++ + # Downloading and installing binary distribution : + # =================================================================== + +diff --git a/alliance/src/autostuff b/alliance/src/autostuff +index abbdfd6..53083eb 100755 +--- a/alliance/src/autostuff ++++ b/alliance/src/autostuff +@@ -291,28 +291,28 @@ find $ordered_dirs -name configure.in | while read config; do + echo "" >> configure.in + echo "dnl Infos extracted from $config" >> configure.in + +- for version_line in `grep -h _CUR= $config`; do ++ for version_line in `grep -ah _CUR= $config`; do + echo "$version_line" >> configure.in + version_name=`echo $version_line | sed 's,=.*,,'` + echo "AC_SUBST($version_name)" >> configure.in + done +- for version_line in `grep -h _REV= $config`; do ++ for version_line in `grep -ah _REV= $config`; do + echo "$version_line" >> configure.in + version_name=`echo $version_line | sed 's,=.*,,'` + echo "AC_SUBST($version_name)" >> configure.in + done +- for version_line in `grep -h _REL= $config`; do ++ for version_line in `grep -ah _REL= $config`; do + echo "$version_line" >> configure.in + version_name=`echo $version_line | sed 's,=.*,,'` + echo "AC_SUBST($version_name)" >> configure.in + done + +- for dll_line in `grep -h _DLL_VERSION= $config`; do ++ for dll_line in `grep -ah _DLL_VERSION= $config`; do + echo "$dll_line" >> configure.in + dll_name=`echo $dll_line | sed 's,=.*,,'` + echo "AC_SUBST($dll_name)" >> configure.in + done +- for version_line in `grep -h _VERSION= $config | grep -v DLL`; do ++ for version_line in `grep -ah _VERSION= $config | grep -v DLL`; do + echo "$version_line" >> configure.in + version_name=`echo $version_line | sed 's,=.*,,'` + echo "AC_SUBST($version_name)" >> configure.in +diff --git a/alliance/src/boog/src/bog_lib_reader.c b/alliance/src/boog/src/bog_lib_reader.c +index fca9bd2..da3603b 100644 +--- a/alliance/src/boog/src/bog_lib_reader.c ++++ b/alliance/src/boog/src/bog_lib_reader.c +@@ -149,7 +149,7 @@ static int distribCell(befig_list* befig) + } + + /*patterns aren't equal, new is more precise*/ +- if (!biabl_befig) continue; ++ if (biabl_befig) continue; + + /*patterns are equal -->comparison*/ + if (cell->AREAABL)!=ABL_ATOM(expr)) continue; +- ++ if (ABL_ATOM(expr)&& ++ ((ABL_ATOM_VALUE(expr)==getablatomzero() || ABL_ATOM_VALUE(expr)==getablatomone()) ++ && ABL_ATOM_VALUE(expr)!=ABL_ATOM_VALUE(cell->ABL))) continue; + /*improve speed*/ + if (!ABL_ATOM(expr) && ABL_OPER(expr)!=ABL_NOT/*match all*/) { + if (ABL_ARITY(cell->ABL)!=ABL_ARITY(expr)) continue; +diff --git a/alliance/src/cells/src/Makefile.am b/alliance/src/cells/src/Makefile.am +index 64e6972..b4c0f2a 100644 +--- a/alliance/src/cells/src/Makefile.am ++++ b/alliance/src/cells/src/Makefile.am +@@ -1,4 +1,4 @@ + # $Id: Makefile.am,v 1.5 2005/10/04 15:46:25 jpc Exp $ + +-SUBDIRS = dp_sxlib padlib pxlib rflib rf2lib ramlib romlib sxlib ++SUBDIRS = dp_sxlib padlib pxlib mpxlib rflib rf2lib ramlib romlib sxlib msxlib + +diff --git a/alliance/src/cells/src/dp_sxlib/dp_dff_x4.ap b/alliance/src/cells/src/dp_sxlib/dp_dff_x4.ap +index bb6f720..bd47a67 100644 +--- a/alliance/src/cells/src/dp_sxlib/dp_dff_x4.ap ++++ b/alliance/src/cells/src/dp_sxlib/dp_dff_x4.ap +@@ -1,170 +1,173 @@ + V ALLIANCE : 6 +-H dp_dff_x4,P,26/ 9/2000,100 ++H dp_dff_x4,P, 6/ 8/2015,100 + A 0,0,7000,5000 +-R 3000,2000,ref_ref,nckx +-R 500,4000,ref_ref,i_40 +-R 500,1000,ref_ref,i_10 +-R 500,1500,ref_ref,i_15 +-R 500,2000,ref_ref,i_20 +-R 500,3500,ref_ref,i_35 +-R 500,3000,ref_ref,i_30 +-R 6000,1500,ref_ref,q_15 +-R 6000,1000,ref_ref,q_10 +-R 6000,4000,ref_ref,q_40 +-R 6000,3000,ref_ref,q_30 +-R 6000,2000,ref_ref,q_20 +-R 6000,3500,ref_ref,q_35 +-R 500,2500,ref_ref,i_25 +-R 6000,2500,ref_ref,q_25 +-R 1000,2000,ref_ref,wenx +-R 2000,2000,ref_ref,nwenx + R 4500,2000,ref_ref,ckx +-S 3000,1500,3400,1500,200,*,RIGHT,ALU1 +-S 3000,3000,3900,3000,200,*,RIGHT,ALU1 +-S 3000,1500,3000,3000,100,*,DOWN,ALU1 +-S 3000,2000,3000,2000,200,nckx,LEFT,CALU3 +-S 4400,2500,4400,3500,100,*,DOWN,ALU1 +-S 3700,3500,3700,4000,100,*,DOWN,ALU1 +-S 3700,3500,4400,3500,100,*,RIGHT,ALU1 +-S 300,3300,300,4600,300,*,UP,PDIF +-S 5100,2600,5100,4900,100,*,DOWN,PTRANS +-S 6300,2600,6300,4900,100,*,DOWN,PTRANS +-S 6600,2800,6600,4700,300,*,DOWN,PDIF +-S 0,4000,7000,4000,2600,*,RIGHT,NWELL +-S 2400,3100,2400,4400,100,*,UP,PTRANS +-S 1900,3100,1900,4400,100,*,UP,PTRANS +-S 1100,3100,1100,4400,100,*,UP,PTRANS +-S 5700,2600,5700,4900,100,*,DOWN,PTRANS +-S 6000,2800,6000,4700,300,*,DOWN,PDIF +-S 4700,2600,4700,4900,100,*,DOWN,PTRANS +-S 5300,2800,5300,4700,300,*,DOWN,PDIF +-S 4400,2800,4400,4700,300,*,DOWN,PDIF +-S 3700,3800,3700,4700,300,*,DOWN,PDIF +-S 2700,3300,2700,4700,300,*,UP,PDIF +-S 3000,3600,3000,4900,100,*,DOWN,PTRANS +-S 3400,3600,3400,4900,100,*,DOWN,PTRANS +-S 600,3100,600,4400,100,*,UP,PTRANS +-S 1500,3300,1500,4200,500,*,UP,PDIF +-S 4700,100,4700,1400,100,*,UP,NTRANS +-S 6300,100,6300,1400,100,*,UP,NTRANS +-S 1900,600,1900,1400,100,*,DOWN,NTRANS +-S 2400,600,2400,1400,100,*,DOWN,NTRANS +-S 1100,600,1100,1400,100,*,DOWN,NTRANS +-S 3400,600,3400,1400,100,*,UP,NTRANS +-S 3000,600,3000,1400,100,*,UP,NTRANS +-S 600,600,600,1400,100,*,DOWN,NTRANS +-S 5700,100,5700,1400,100,*,UP,NTRANS +-S 5100,100,5100,1400,100,*,UP,NTRANS +-S 4400,300,4400,1200,300,*,DOWN,NDIF +-S 300,400,300,1200,300,*,DOWN,NDIF +-S 300,300,300,1200,300,*,DOWN,NDIF +-S 5400,300,5400,1200,300,*,DOWN,NDIF +-S 6000,300,6000,1200,300,*,DOWN,NDIF +-S 2700,400,2700,1200,300,*,DOWN,NDIF +-S 6600,300,6600,1200,300,*,DOWN,NDIF +-S 1500,800,1500,1200,500,*,UP,NDIF +-S 3700,800,3700,1200,300,*,DOWN,NDIF +-S 5700,1400,5700,2600,100,*,DOWN,POLY +-S 4700,2500,4700,2600,100,*,DOWN,POLY +-S 5100,1400,5100,2600,100,*,DOWN,POLY +-S 5500,2000,6300,2000,100,*,RIGHT,POLY +-S 6300,1400,6300,2600,100,*,DOWN,POLY +-S 4300,1400,4700,1400,100,*,LEFT,POLY +-S 3900,2500,4700,2500,100,*,LEFT,POLY +-S 3900,2500,3900,3000,100,*,UP,POLY +-S 4300,1400,4300,2000,100,*,DOWN,POLY +-S 3400,2000,4300,2000,100,*,RIGHT,POLY +-S 1500,2000,3000,2000,100,*,RIGHT,POLY +-S 1100,1400,1100,2500,100,*,UP,POLY +-S 1100,2500,1900,2500,100,*,RIGHT,POLY +-S 3400,2000,3400,3600,100,*,DOWN,POLY +-S 3000,900,3000,3600,100,*,DOWN,POLY +-S 1900,2500,1900,3100,100,*,DOWN,POLY +-S 600,1400,600,3100,100,*,DOWN,POLY +-S 2500,1500,2500,3000,100,*,UP,ALU1 +-S 2700,500,2700,1000,200,*,UP,ALU1 +-S 1000,4000,2000,4000,100,*,LEFT,ALU1 +-S 2000,1500,2000,4000,100,*,UP,ALU1 +-S 1500,1000,1500,3500,100,*,UP,ALU1 +-S 6600,500,6600,1000,200,*,DOWN,ALU1 +-S 6600,3000,6600,4500,200,*,DOWN,ALU1 +-S 4400,4000,4900,4000,100,*,RIGHT,ALU1 +-S 3700,1000,3900,1000,200,*,RIGHT,ALU1 +-S 3900,1500,5000,1500,100,*,RIGHT,ALU1 +-S 3900,1000,3900,2500,100,*,DOWN,ALU1 +-S 3900,2500,4400,2500,100,*,RIGHT,ALU1 +-S 4900,2500,4900,4000,100,*,DOWN,ALU1 +-S 1000,3000,1000,4000,100,*,DOWN,ALU1 +-S 2700,3500,2700,4500,200,*,DOWN,ALU1 +-S 5400,3000,5400,4500,200,*,DOWN,ALU1 +-S 4900,2500,5500,2500,100,*,RIGHT,ALU1 +-S 4400,1000,5500,1000,100,*,LEFT,ALU1 +-S 5500,1000,5500,2500,100,*,DOWN,ALU1 +-S 5000,1500,5000,1900,100,*,UP,ALU1 +-S 1000,2000,4500,2000,200,*,RIGHT,TALU2 +-S 0,300,7000,300,600,vss,RIGHT,CALU1 +-S 0,4700,7000,4700,600,vdd,RIGHT,CALU1 +-S 500,1000,500,4000,200,i,UP,CALU1 +-S 6000,1000,6000,4000,200,q,DOWN,CALU1 +-S 2500,2500,6000,2500,200,q,RIGHT,CALU2 +-S 1000,2000,1000,2000,200,wenx,LEFT,CALU3 +-S 2000,2000,2000,2000,200,nwenx,LEFT,CALU3 ++R 2000,2000,ref_ref,nwenx ++R 1000,2000,ref_ref,wenx ++R 6000,2500,ref_ref,q_25 ++R 500,2500,ref_ref,i_25 ++R 6000,3500,ref_ref,q_35 ++R 6000,2000,ref_ref,q_20 ++R 6000,3000,ref_ref,q_30 ++R 6000,4000,ref_ref,q_40 ++R 6000,1000,ref_ref,q_10 ++R 6000,1500,ref_ref,q_15 ++R 500,3000,ref_ref,i_30 ++R 500,3500,ref_ref,i_35 ++R 500,2000,ref_ref,i_20 ++R 500,1500,ref_ref,i_15 ++R 500,1000,ref_ref,i_10 ++R 500,4000,ref_ref,i_40 ++R 3000,2000,ref_ref,nckx ++S 4500,2000,4500,2000,200,ckx,RIGHT,CALU2 ++S 3000,2000,3000,2000,200,nckx,RIGHT,CALU2 ++S 2000,2000,2000,2000,200,nwenx,RIGHT,CALU2 ++S 1000,2000,1000,2000,200,wenx,RIGHT,CALU2 + S 4500,2000,4500,2000,200,ckx,LEFT,CALU3 +-V 3000,2000,CONT_VIA,* +-V 3000,2000,CONT_VIA2,* +-V 5400,4000,CONT_DIF_P,* +-V 5400,4500,CONT_DIF_P,* +-V 6600,4500,CONT_DIF_P,* +-V 6600,3000,CONT_DIF_P,* +-V 5400,3500,CONT_DIF_P,* +-V 900,4700,CONT_BODY_N,* +-V 2100,4700,CONT_BODY_N,* +-V 1500,4700,CONT_BODY_N,* +-V 5400,3000,CONT_DIF_P,* +-V 1500,3500,CONT_DIF_P,* +-V 2700,4500,CONT_DIF_P,* +-V 4400,4000,CONT_DIF_P,* +-V 6600,3500,CONT_DIF_P,* +-V 3700,4000,CONT_DIF_P,* +-V 2700,3500,CONT_DIF_P,* +-V 300,4500,CONT_DIF_P,* +-V 2700,4000,CONT_DIF_P,* +-V 6000,3000,CONT_DIF_P,* +-V 6600,4000,CONT_DIF_P,* +-V 2700,500,CONT_DIF_N,* +-V 4400,1000,CONT_DIF_N,* +-V 6000,1000,CONT_DIF_N,* +-V 5400,500,CONT_DIF_N,* +-V 6600,500,CONT_DIF_N,* +-V 6600,1000,CONT_DIF_N,* ++S 2000,2000,2000,2000,200,nwenx,LEFT,CALU3 ++S 1000,2000,1000,2000,200,wenx,LEFT,CALU3 ++S 2500,2500,6000,2500,200,q,RIGHT,CALU2 ++S 6000,1000,6000,4000,200,q,DOWN,CALU1 ++S 500,1000,500,4000,200,i,UP,CALU1 ++S 0,4700,7000,4700,600,vdd,RIGHT,CALU1 ++S 0,300,7000,300,600,vss,RIGHT,CALU1 ++S 5000,1500,5000,1900,100,*,UP,ALU1 ++S 5500,1000,5500,2500,100,*,DOWN,ALU1 ++S 4400,1000,5500,1000,100,*,LEFT,ALU1 ++S 4900,2500,5500,2500,100,*,RIGHT,ALU1 ++S 5400,3000,5400,4500,200,*,DOWN,ALU1 ++S 2700,3500,2700,4500,200,*,DOWN,ALU1 ++S 1000,3000,1000,4000,100,*,DOWN,ALU1 ++S 4900,2500,4900,4000,100,*,DOWN,ALU1 ++S 3900,2500,4400,2500,100,*,RIGHT,ALU1 ++S 3900,1000,3900,2500,100,*,DOWN,ALU1 ++S 3900,1500,5000,1500,100,*,RIGHT,ALU1 ++S 3700,1000,3900,1000,200,*,RIGHT,ALU1 ++S 4400,4000,4900,4000,100,*,RIGHT,ALU1 ++S 6600,3000,6600,4500,200,*,DOWN,ALU1 ++S 6600,500,6600,1000,200,*,DOWN,ALU1 ++S 1500,1000,1500,3500,100,*,UP,ALU1 ++S 2000,1500,2000,4000,100,*,UP,ALU1 ++S 1000,4000,2000,4000,100,*,LEFT,ALU1 ++S 2700,500,2700,1000,200,*,UP,ALU1 ++S 2500,1500,2500,3000,100,*,UP,ALU1 ++S 600,1400,600,3100,100,*,DOWN,POLY ++S 1900,2500,1900,3100,100,*,DOWN,POLY ++S 3000,900,3000,3600,100,*,DOWN,POLY ++S 3400,2000,3400,3600,100,*,DOWN,POLY ++S 1100,2500,1900,2500,100,*,RIGHT,POLY ++S 1100,1400,1100,2500,100,*,UP,POLY ++S 1500,2000,3000,2000,100,*,RIGHT,POLY ++S 3400,2000,4300,2000,100,*,RIGHT,POLY ++S 4300,1400,4300,2000,100,*,DOWN,POLY ++S 3900,2500,3900,3000,100,*,UP,POLY ++S 3900,2500,4700,2500,100,*,LEFT,POLY ++S 4300,1400,4700,1400,100,*,LEFT,POLY ++S 6300,1400,6300,2600,100,*,DOWN,POLY ++S 5500,2000,6300,2000,100,*,RIGHT,POLY ++S 5100,1400,5100,2600,100,*,DOWN,POLY ++S 4700,2500,4700,2600,100,*,DOWN,POLY ++S 5700,1400,5700,2600,100,*,DOWN,POLY ++S 3700,800,3700,1200,300,*,DOWN,NDIF ++S 1500,800,1500,1200,500,*,UP,NDIF ++S 6600,300,6600,1200,300,*,DOWN,NDIF ++S 2700,400,2700,1200,300,*,DOWN,NDIF ++S 6000,300,6000,1200,300,*,DOWN,NDIF ++S 5400,300,5400,1200,300,*,DOWN,NDIF ++S 300,300,300,1200,300,*,DOWN,NDIF ++S 300,400,300,1200,300,*,DOWN,NDIF ++S 4400,300,4400,1200,300,*,DOWN,NDIF ++S 5100,100,5100,1400,100,*,UP,NTRANS ++S 5700,100,5700,1400,100,*,UP,NTRANS ++S 600,600,600,1400,100,*,DOWN,NTRANS ++S 3000,600,3000,1400,100,*,UP,NTRANS ++S 3400,600,3400,1400,100,*,UP,NTRANS ++S 1100,600,1100,1400,100,*,DOWN,NTRANS ++S 2400,600,2400,1400,100,*,DOWN,NTRANS ++S 1900,600,1900,1400,100,*,DOWN,NTRANS ++S 6300,100,6300,1400,100,*,UP,NTRANS ++S 4700,100,4700,1400,100,*,UP,NTRANS ++S 1500,3300,1500,4200,500,*,UP,PDIF ++S 600,3100,600,4400,100,*,UP,PTRANS ++S 3400,3600,3400,4900,100,*,DOWN,PTRANS ++S 3000,3600,3000,4900,100,*,DOWN,PTRANS ++S 2700,3300,2700,4700,300,*,UP,PDIF ++S 3700,3800,3700,4700,300,*,DOWN,PDIF ++S 4400,2800,4400,4700,300,*,DOWN,PDIF ++S 5300,2800,5300,4700,300,*,DOWN,PDIF ++S 4700,2600,4700,4900,100,*,DOWN,PTRANS ++S 6000,2800,6000,4700,300,*,DOWN,PDIF ++S 5700,2600,5700,4900,100,*,DOWN,PTRANS ++S 1100,3100,1100,4400,100,*,UP,PTRANS ++S 1900,3100,1900,4400,100,*,UP,PTRANS ++S 2400,3100,2400,4400,100,*,UP,PTRANS ++S 0,4000,7000,4000,2600,*,RIGHT,NWELL ++S 6600,2800,6600,4700,300,*,DOWN,PDIF ++S 6300,2600,6300,4900,100,*,DOWN,PTRANS ++S 5100,2600,5100,4900,100,*,DOWN,PTRANS ++S 300,3300,300,4600,300,*,UP,PDIF ++S 3700,3500,4400,3500,100,*,RIGHT,ALU1 ++S 3700,3500,3700,4000,100,*,DOWN,ALU1 ++S 4400,2500,4400,3500,100,*,DOWN,ALU1 ++S 3000,2000,3000,2000,200,nckx,LEFT,CALU3 ++S 3000,1500,3000,3000,100,*,DOWN,ALU1 ++S 3000,3000,3900,3000,200,*,RIGHT,ALU1 ++S 3000,1500,3400,1500,200,*,RIGHT,ALU1 ++V 1000,2000,CONT_VIA2,wenx ++V 4500,2000,CONT_VIA2,* ++V 2000,2000,CONT_VIA2,* ++V 2500,2500,CONT_VIA,* ++V 1000,2000,CONT_VIA,* ++V 2000,2000,CONT_VIA,* ++V 6000,2500,CONT_VIA,* ++V 4500,2000,CONT_VIA,* ++V 4400,2000,CONT_POLY,* ++V 1000,2000,CONT_POLY,* ++V 1000,3000,CONT_POLY,* ++V 2500,3000,CONT_POLY,* ++V 2500,1500,CONT_POLY,* ++V 2000,1500,CONT_POLY,* ++V 5500,2000,CONT_POLY,* ++V 3400,1500,CONT_POLY,* ++V 1500,2000,CONT_POLY,* ++V 5000,2000,CONT_POLY,* ++V 3900,3000,CONT_POLY,* ++V 500,1500,CONT_POLY,* ++V 500,3000,CONT_POLY,* ++V 3700,300,CONT_BODY_P,* ++V 2100,300,CONT_BODY_P,* ++V 900,300,CONT_BODY_P,* ++V 1500,300,CONT_BODY_P,* ++V 1500,1000,CONT_DIF_N,* + V 300,500,CONT_DIF_N,* +-V 2700,1000,CONT_DIF_N,* + V 3700,1000,CONT_DIF_N,* ++V 2700,1000,CONT_DIF_N,* + V 300,500,CONT_DIF_N,* +-V 1500,1000,CONT_DIF_N,* +-V 1500,300,CONT_BODY_P,* +-V 900,300,CONT_BODY_P,* +-V 2100,300,CONT_BODY_P,* +-V 3700,300,CONT_BODY_P,* +-V 500,3000,CONT_POLY,* +-V 500,1500,CONT_POLY,* +-V 3900,3000,CONT_POLY,* +-V 5000,2000,CONT_POLY,* +-V 1500,2000,CONT_POLY,* +-V 3400,1500,CONT_POLY,* +-V 5500,2000,CONT_POLY,* +-V 2000,1500,CONT_POLY,* +-V 2500,1500,CONT_POLY,* +-V 2500,3000,CONT_POLY,* +-V 1000,3000,CONT_POLY,* +-V 1000,2000,CONT_POLY,* +-V 4400,2000,CONT_POLY,* +-V 4500,2000,CONT_VIA,* +-V 6000,2500,CONT_VIA,* +-V 2000,2000,CONT_VIA,* +-V 1000,2000,CONT_VIA,* +-V 2500,2500,CONT_VIA,* +-V 2000,2000,CONT_VIA2,* +-V 1000,2000,CONT_VIA2,* +-V 4500,2000,CONT_VIA2,* ++V 6600,1000,CONT_DIF_N,* ++V 6600,500,CONT_DIF_N,* ++V 5400,500,CONT_DIF_N,* ++V 6000,1000,CONT_DIF_N,* ++V 4400,1000,CONT_DIF_N,* ++V 2700,500,CONT_DIF_N,* ++V 6600,4000,CONT_DIF_P,* ++V 6000,3000,CONT_DIF_P,* ++V 2700,4000,CONT_DIF_P,* ++V 300,4500,CONT_DIF_P,* ++V 2700,3500,CONT_DIF_P,* ++V 3700,4000,CONT_DIF_P,* ++V 6600,3500,CONT_DIF_P,* ++V 4400,4000,CONT_DIF_P,* ++V 2700,4500,CONT_DIF_P,* ++V 1500,3500,CONT_DIF_P,* ++V 5400,3000,CONT_DIF_P,* ++V 1500,4700,CONT_BODY_N,* ++V 2100,4700,CONT_BODY_N,* ++V 900,4700,CONT_BODY_N,* ++V 5400,3500,CONT_DIF_P,* ++V 6600,3000,CONT_DIF_P,* ++V 6600,4500,CONT_DIF_P,* ++V 5400,4500,CONT_DIF_P,* ++V 5400,4000,CONT_DIF_P,* ++V 3000,2000,CONT_VIA2,* ++V 3000,2000,CONT_VIA,* + EOF +diff --git a/alliance/src/cells/src/mpxlib/CATAL b/alliance/src/cells/src/mpxlib/CATAL +new file mode 100644 +index 0000000..6b55fa3 +--- /dev/null ++++ b/alliance/src/cells/src/mpxlib/CATAL +@@ -0,0 +1,13 @@ ++pck_mpx C ++piot_mpx C ++pi_mpx C ++po_mpx C ++pot_mpx C ++pvddeck_mpx C ++pvdde_mpx C ++pvddick_mpx C ++pvddi_mpx C ++pvsseck_mpx C ++pvsse_mpx C ++pvssick_mpx C ++pvssi_mpx C +diff --git a/alliance/src/cells/src/mpxlib/Makefile.am b/alliance/src/cells/src/mpxlib/Makefile.am +new file mode 100644 +index 0000000..9469aab +--- /dev/null ++++ b/alliance/src/cells/src/mpxlib/Makefile.am +@@ -0,0 +1,34 @@ ++ ++mpxlibdir=$(prefix)/cells/mpxlib ++ ++mpxlib_DATA=CATAL \ ++ pck_mpx.ap \ ++ pck_mpx.vbe \ ++ piot_mpx.ap \ ++ piot_mpx.vbe \ ++ pi_mpx.ap \ ++ pi_mpx.vbe \ ++ po_mpx.ap \ ++ po_mpx.vbe \ ++ pot_mpx.ap \ ++ pot_mpx.vbe \ ++ padreal_mpx.ap \ ++ pvddeck_mpx.ap \ ++ pvddeck_mpx.vbe \ ++ pvdde_mpx.ap \ ++ pvdde_mpx.vbe \ ++ pvddick_mpx.ap \ ++ pvddick_mpx.vbe \ ++ pvddi_mpx.ap \ ++ pvddi_mpx.vbe \ ++ pvsseck_mpx.ap \ ++ pvsseck_mpx.vbe \ ++ pvsse_mpx.ap \ ++ pvsse_mpx.vbe \ ++ pvssick_mpx.ap \ ++ pvssick_mpx.vbe \ ++ pvssi_mpx.ap \ ++ pvssi_mpx.vbe ++ ++EXTRA_DIST=$(mpxlib_DATA) ++ +diff --git a/alliance/src/cells/src/mpxlib/padreal_mpx.ap b/alliance/src/cells/src/mpxlib/padreal_mpx.ap +new file mode 100644 +index 0000000..f1edeaf +--- /dev/null ++++ b/alliance/src/cells/src/mpxlib/padreal_mpx.ap +@@ -0,0 +1,5 @@ ++V ALLIANCE : 6 ++H padreal_mpx,P,14/9/2014,100 ++A 0,0,40000,40000 ++S 20000,8100,20000,31900,24400,pad,UP,CALU1 ++EOF +diff --git a/alliance/src/cells/src/mpxlib/pck_mpx.ap b/alliance/src/cells/src/mpxlib/pck_mpx.ap +new file mode 100644 +index 0000000..55cb0c6 +--- /dev/null ++++ b/alliance/src/cells/src/mpxlib/pck_mpx.ap +@@ -0,0 +1,1385 @@ ++V ALLIANCE : 6 ++H pck_mpx,P,14/9/2014,100 ++A 0,0,40000,80000 ++I 0,40000,padreal_mpx,padreal,NOSYM ++S 29000,35100,29000,39700,400,pad,UP,ALU1 ++S 29000,25900,29000,34900,400,pad,UP,ALU1 ++S 28600,33000,29000,33000,600,pad,RIGHT,POLY ++S 28600,31800,29000,31800,600,pad,RIGHT,POLY ++S 28600,30600,29000,30600,600,pad,RIGHT,POLY ++S 28600,25800,29000,25800,600,pad,RIGHT,POLY ++S 20000,48100,20000,71900,24400,pad,UP,CALU1 ++S 700,4000,39300,4000,1000,ck,RIGHT,CALU3 ++S 24000,34200,24400,34200,600,vdde,RIGHT,POLY ++S 16800,29900,16800,38300,400,vdde,UP,ALU2 ++S 16800,34600,17200,34600,200,vdde,RIGHT,POLY ++S 16800,35800,17200,35800,200,vdde,RIGHT,POLY ++S 700,34000,39300,34000,2400,vdde,RIGHT,CALU3 ++S 700,22000,39300,22000,2400,vdde,RIGHT,CALU3 ++S 700,28000,39300,28000,2400,vdde,RIGHT,CALU3 ++S 6800,22200,8400,22200,200,vdde,RIGHT,POLY ++S 3600,22200,5200,22200,200,vdde,RIGHT,POLY ++S 25100,28800,27900,28800,400,vdde,RIGHT,ALU1 ++S 25100,24000,27900,24000,400,vdde,RIGHT,ALU1 ++S 24000,35800,24400,35800,600,vdde,RIGHT,POLY ++S 16800,33400,17200,33400,200,vdde,RIGHT,POLY ++S 16800,32200,17200,32200,200,vdde,RIGHT,POLY ++S 10500,21800,14300,21800,400,vdde,RIGHT,ALU2 ++S 25100,21600,27900,21600,400,vdde,RIGHT,ALU1 ++S 25100,26400,27900,26400,400,vdde,RIGHT,ALU1 ++S 700,16000,39300,16000,2400,vddi,RIGHT,CALU3 ++S 700,10000,39300,10000,2400,vddi,RIGHT,CALU3 ++S 32000,9600,32000,11000,200,vddi,UP,POLY ++S 3100,16000,36900,16000,2400,vddi,RIGHT,ALU1 ++S 17800,22900,17800,31900,400,vsse,UP,ALU2 ++S 700,19000,39300,19000,2400,vsse,RIGHT,CALU3 ++S 700,37000,39300,37000,2400,vsse,RIGHT,CALU3 ++S 700,31000,39300,31000,2400,vsse,RIGHT,CALU3 ++S 700,25000,39300,25000,2400,vsse,RIGHT,CALU3 ++S 7600,22900,7600,37500,400,vsse,UP,ALU1 ++S 4400,22900,4400,37500,400,vsse,UP,ALU1 ++S 30400,36400,30400,36600,200,vsse,UP,POLY ++S 20800,22900,20800,37100,400,vsse,UP,ALU1 ++S 700,13000,39300,13000,2400,vssi,RIGHT,CALU3 ++S 700,7000,39300,7000,2400,vssi,RIGHT,CALU3 ++S 3100,6000,36900,6000,2400,vssi,RIGHT,ALU1 ++S 14800,22500,14800,36700,200,n15d,UP,NTRANS ++S 26600,11100,26600,13100,200,p17c,UP,PTRANS ++S 31700,6000,37100,6000,400,93onymous_,RIGHT,ALU2 ++S 31600,20200,31600,20600,600,92onymous_,UP,POLY ++S 31400,19100,31400,28300,400,91onymous_,UP,ALU2 ++S 2700,20200,15700,20200,400,53onymous_,RIGHT,ALU1 ++S 17900,31600,18700,31600,400,249nymous_,RIGHT,ALU1 ++S 16400,7500,16400,9100,620,210nymous_,UP,NDIF ++S 23100,19200,38100,19200,400,13onymous_,RIGHT,ALU1 ++S 36800,6900,36800,17300,400,126nymous_,UP,ALU2 ++S 23100,37600,27700,37600,400,10onymous_,RIGHT,ALU1 ++S 36800,11100,36800,15900,400,127nymous_,UP,ALU1 ++S 17500,22600,19100,22600,200,n6d,RIGHT,NTRANS ++S 13400,10900,13400,14900,200,p18b,UP,PTRANS ++S 6800,22500,6800,36700,200,n14c,UP,NTRANS ++S 26000,12100,26000,15900,400,52onymous_,UP,ALU1 ++S 17900,30400,18700,30400,400,248nymous_,RIGHT,ALU1 ++S 26000,11300,26000,12900,620,51onymous_,UP,PDIF ++S 16400,11100,16400,14700,620,211nymous_,UP,PDIF ++S 900,19000,9300,19000,2400,169nymous_,RIGHT,ALU2 ++S 23000,19300,23000,37500,400,11onymous_,UP,ALU1 ++S 23000,19080,23000,37920,600,12onymous_,UP,NTIE ++S 27000,24900,27000,36700,400,56onymous_,UP,ALU2 ++S 27200,7500,27200,9100,620,57onymous_,UP,NDIF ++S 27200,8100,27200,8900,400,58onymous_,UP,ALU1 ++S 32000,8100,32000,8500,400,94onymous_,UP,ALU1 ++S 23600,6100,23600,7900,400,16onymous_,UP,ALU1 ++S 31400,20900,31400,34300,200,p14a,UP,PTRANS ++S 16400,12100,16400,15900,400,212nymous_,UP,ALU1 ++S 12200,9600,12200,10600,200,170nymous_,UP,POLY ++S 23080,37600,29920,37600,600,15onymous_,RIGHT,NTIE ++S 22880,19200,38320,19200,600,14onymous_,RIGHT,NTIE ++S 37000,21300,37000,36300,400,130nymous_,UP,ALU1 ++S 36800,10880,36800,16120,600,128nymous_,UP,NTIE ++S 37000,21100,37000,36500,620,129nymous_,UP,PDIF ++S 16500,20200,24300,20200,400,213nymous_,RIGHT,ALU2 ++S 31400,35300,31400,36100,200,p11,UP,PTRANS ++S 23600,7500,23600,9100,620,17onymous_,UP,NDIF ++S 16800,20300,16800,23300,400,214nymous_,UP,ALU1 ++S 12400,20700,12400,36300,400,171nymous_,UP,ALU1 ++S 17900,34000,18700,34000,400,250nymous_,RIGHT,ALU1 ++S 16500,21200,25300,21200,400,215nymous_,RIGHT,ALU2 ++S 12400,22700,12400,36500,620,172nymous_,UP,NDIF ++S 26400,18600,26400,38600,8400,54onymous_,UP,NWELL ++S 12400,18500,12400,22100,2400,173nymous_,UP,ALU2 ++S 26600,9600,26600,10800,200,55onymous_,UP,POLY ++S 14600,10900,14600,14900,200,p18c,UP,PTRANS ++S 14600,7300,14600,9300,200,n18c,UP,NTRANS ++S 12500,4000,17900,4000,400,175nymous_,RIGHT,ALU2 ++S 12800,3700,12800,11300,400,174nymous_,UP,ALU2 ++S 1800,17700,1800,38300,1600,252nymous_,UP,ALU2 ++S 16800,23200,16800,25400,600,217nymous_,UP,POLY ++S 16800,20900,16800,24700,400,216nymous_,UP,ALU2 ++S 23600,12100,23600,15900,400,19onymous_,UP,ALU1 ++S 17900,36400,18700,36400,400,251nymous_,RIGHT,ALU1 ++S 23600,11300,23600,12900,620,18onymous_,UP,PDIF ++S 32000,8500,32000,9100,620,pad2,UP,NDIF ++S 2900,20600,15500,20600,400,pad2,RIGHT,ALU1 ++S 2700,20600,15700,20600,400,pad2,RIGHT,ALU1 ++S 38200,19080,38200,37920,600,133nymous_,UP,NTIE ++S 37000,17700,37000,38300,2400,131nymous_,UP,ALU2 ++S 2800,20500,2800,36300,400,62onymous_,UP,ALU1 ++S 27800,9600,27800,10800,200,61onymous_,UP,POLY ++S 27200,11300,27200,12900,620,60onymous_,UP,PDIF ++S 27200,11100,27200,12500,400,59onymous_,UP,ALU1 ++S 3200,5880,3200,8720,600,97onymous_,UP,PTIE ++S 3200,5700,3200,8300,400,96onymous_,UP,ALU2 ++S 12900,9000,17500,9000,400,177nymous_,RIGHT,ALU1 ++S 32000,11100,32000,15900,400,95onymous_,UP,ALU1 ++S 12800,7500,12800,9100,420,176nymous_,UP,NDIF ++S 18200,9600,18200,10600,200,253nymous_,UP,POLY ++S 38200,19300,38200,37500,400,132nymous_,UP,ALU1 ++S 3600,22500,3600,36700,200,n14a,UP,NTRANS ++S 28400,6100,28400,8900,400,65onymous_,UP,ALU1 ++S 32600,8300,32600,9300,200,n16c,UP,NTRANS ++S 24000,33900,24000,36100,400,21onymous_,UP,ALU2 ++S 16800,24100,16800,29500,400,218nymous_,UP,ALU2 ++S 4400,22700,4400,38300,2400,137nymous_,UP,ALU2 ++S 24000,27100,24000,29100,400,20onymous_,UP,ALU1 ++S 4400,22900,4400,37500,400,136nymous_,UP,ALU1 ++S 4400,22700,4400,36500,620,135nymous_,UP,NDIF ++S 4400,21800,4400,22200,600,134nymous_,UP,POLY ++S 16900,24400,17700,24400,400,219nymous_,RIGHT,ALU1 ++S 16800,25500,16800,28100,400,220nymous_,UP,ALU1 ++S 18500,6000,32300,6000,400,254nymous_,RIGHT,ALU2 ++S 12800,11100,12800,14700,620,178nymous_,UP,PDIF ++S 18800,6100,18800,8900,400,255nymous_,UP,ALU1 ++S 12900,11000,17500,11000,400,179nymous_,RIGHT,ALU1 ++S 3200,6100,3200,9100,400,98onymous_,UP,ALU1 ++S 18800,5700,18800,11300,400,256nymous_,UP,ALU2 ++S 18800,7500,18800,9100,620,257nymous_,UP,NDIF ++S 2900,6000,11900,6000,400,99onymous_,RIGHT,ALU2 ++S 27800,7300,27800,9300,200,n17d,UP,NTRANS ++S 3200,7700,3200,15700,400,100nymous_,UP,ALU2 ++S 13400,9600,13400,10600,200,180nymous_,UP,POLY ++S 3200,11100,3200,15900,400,101nymous_,UP,ALU1 ++S 27800,11100,27800,13100,200,p17d,UP,PTRANS ++S 2800,22700,2800,36500,620,63onymous_,UP,NDIF ++S 2200,13600,37800,13600,6800,64onymous_,RIGHT,NWELL ++S 36200,20900,36200,36700,200,p14d,UP,PTRANS ++S 25100,37000,27900,37000,1600,fbul,RIGHT,ALU1 ++S 25100,25200,27900,25200,400,fbul,RIGHT,ALU1 ++S 13200,22200,14800,22200,200,cn,RIGHT,POLY ++S 10000,22200,11600,22200,200,cn,RIGHT,POLY ++S 4100,21800,7900,21800,400,cn,RIGHT,ALU2 ++S 25100,22800,27900,22800,400,cn,RIGHT,ALU1 ++S 25100,20400,27900,20400,400,cn,RIGHT,ALU1 ++S 25000,20100,25000,23100,400,cn,UP,ALU2 ++S 24900,21600,28100,21600,420,25onymous_,RIGHT,PDIF ++S 24900,20400,28100,20400,620,24onymous_,RIGHT,PDIF ++S 28400,11300,28400,12900,620,67onymous_,UP,PDIF ++S 28400,7500,28400,9100,620,66onymous_,UP,NDIF ++S 18200,7300,18200,9300,200,n18f,UP,NTRANS ++S 6000,20700,6000,36300,400,138nymous_,UP,ALU1 ++S 18200,10900,18200,14900,200,p18f,UP,PTRANS ++S 24000,18900,24000,20500,400,22onymous_,UP,ALU2 ++S 6000,22700,6000,36500,620,139nymous_,UP,NDIF ++S 16800,28200,16800,29800,600,221nymous_,UP,POLY ++S 7600,21800,7600,22200,600,140nymous_,UP,POLY ++S 16900,29200,18700,29200,400,222nymous_,RIGHT,ALU1 ++S 24200,9600,24200,10800,200,23onymous_,UP,POLY ++S 7300,21800,10100,21800,400,141nymous_,RIGHT,ALU2 ++S 18500,10000,35900,10000,2400,258nymous_,RIGHT,ALU2 ++S 3200,10880,3200,16120,600,102nymous_,UP,NTIE ++S 14000,21800,14000,22200,600,181nymous_,UP,POLY ++S 2900,17000,19100,17000,400,103nymous_,RIGHT,ALU2 ++S 14000,22700,14000,36500,620,182nymous_,UP,NDIF ++S 14000,22900,14000,39700,400,183nymous_,UP,ALU1 ++S 11600,22500,11600,36700,200,n15b,UP,NTRANS ++S 32200,21300,32200,39700,400,105nymous_,UP,ALU1 ++S 32200,21100,32200,36500,620,104nymous_,UP,PDIF ++S 19800,32900,19800,35100,400,262nymous_,UP,ALU1 ++S 9200,20700,9200,36300,400,145nymous_,UP,ALU1 ++S 18500,17000,33500,17000,400,261nymous_,RIGHT,ALU2 ++S 18800,11900,18800,15900,400,260nymous_,UP,ALU1 ++S 7600,22700,7600,38300,2400,144nymous_,UP,ALU2 ++S 18800,11100,18800,14700,620,259nymous_,UP,PDIF ++S 17000,9600,17000,10600,200,223nymous_,UP,POLY ++S 7600,22900,7600,37500,400,143nymous_,UP,ALU1 ++S 7600,22700,7600,36500,620,142nymous_,UP,NDIF ++S 14000,6100,14000,7900,400,184nymous_,UP,ALU1 ++S 14000,7500,14000,9100,620,185nymous_,UP,NDIF ++S 14100,10000,24700,10000,400,186nymous_,RIGHT,ALU1 ++S 14000,11100,14000,14700,620,187nymous_,UP,PDIF ++S 33800,8300,33800,9300,200,n16d,UP,NTRANS ++S 17700,22000,18900,22000,620,224nymous_,RIGHT,NDIF ++S 17700,23200,18900,23200,620,225nymous_,RIGHT,NDIF ++S 24900,22800,28100,22800,420,26onymous_,RIGHT,PDIF ++S 17700,24400,18900,24400,620,226nymous_,RIGHT,NDIF ++S 24900,24000,28100,24000,420,27onymous_,RIGHT,PDIF ++S 24900,25200,28100,25200,420,28onymous_,RIGHT,PDIF ++S 18500,31600,25300,31600,400,cpd,RIGHT,ALU2 ++S 18800,21900,18800,36700,400,cpd,UP,ALU2 ++S 25100,32400,27900,32400,400,cpd,RIGHT,ALU1 ++S 25100,30000,27900,30000,400,cpd,RIGHT,ALU1 ++S 25100,27600,27900,27600,400,cpd,RIGHT,ALU1 ++S 25000,27300,25000,32700,400,cpd,UP,ALU2 ++S 19500,36800,26300,36800,400,node_cp,RIGHT,ALU2 ++S 17900,35200,19700,35200,400,node_cp,RIGHT,ALU1 ++S 17900,32800,19700,32800,400,node_cp,RIGHT,ALU1 ++S 34600,20600,36200,20600,200,node_cp,RIGHT,POLY ++S 31400,20600,33000,20600,200,node_cp,RIGHT,POLY ++S 28600,24600,29000,24600,600,node_cp,RIGHT,POLY ++S 27700,24600,29300,24600,400,node_cp,RIGHT,ALU2 ++S 28000,24300,28000,31500,400,node_cp,UP,ALU2 ++S 25100,33600,27900,33600,400,node_cp,RIGHT,ALU1 ++S 25100,31200,27900,31200,400,node_cp,RIGHT,ALU1 ++S 9300,25000,16100,25000,2400,147nymous_,RIGHT,ALU2 ++S 9200,22700,9200,36500,620,146nymous_,UP,NDIF ++S 8400,22500,8400,36700,200,n14d,UP,NTRANS ++S 24200,7300,24200,9300,200,n17a,UP,NTRANS ++S 19500,28200,24300,28200,400,cpb,RIGHT,ALU2 ++S 19800,22700,19800,30900,400,cpb,UP,ALU1 ++S 19400,31000,19800,31000,200,cpb,RIGHT,POLY ++S 19400,27400,19800,27400,200,cpb,RIGHT,POLY ++S 19400,26200,19800,26200,200,cpb,RIGHT,POLY ++S 19400,22600,19800,22600,200,cpb,RIGHT,POLY ++S 24000,29200,24400,29200,600,cpb,RIGHT,POLY ++S 24000,28200,24400,28200,600,cpb,RIGHT,POLY ++S 24000,27000,24400,27000,600,cpb,RIGHT,POLY ++S 9300,31000,16100,31000,2400,148nymous_,RIGHT,ALU2 ++S 19800,34900,19800,37100,400,263nymous_,UP,ALU2 ++S 32800,20200,32800,20600,600,106nymous_,UP,POLY ++S 9800,21500,9800,23100,400,149nymous_,UP,ALU2 ++S 0,6000,40000,6000,12000,264nymous_,RIGHT,TALU6 ++S 33200,8500,33200,9100,420,107nymous_,UP,NDIF ++S 28400,12100,28400,15900,400,68onymous_,UP,ALU1 ++S 14000,12100,14000,15900,400,188nymous_,UP,ALU1 ++S 24900,28800,28100,28800,420,31onymous_,RIGHT,PDIF ++S 1280,37600,21120,37600,600,189nymous_,RIGHT,PTIE ++S 14600,9600,14600,10600,200,190nymous_,UP,POLY ++S 17700,25600,18900,25600,620,227nymous_,RIGHT,NDIF ++S 24900,26400,28100,26400,420,29onymous_,RIGHT,PDIF ++S 24900,27600,28100,27600,420,30onymous_,RIGHT,PDIF ++S 15800,7300,15800,9300,200,n18d,UP,NTRANS ++S 15800,10900,15800,14900,200,p18d,UP,PTRANS ++S 26000,21300,26000,24300,400,45onymous_,UP,ALU2 ++S 24200,11100,24200,13100,200,p17a,UP,PTRANS ++S 24200,10000,28400,10000,600,nnt,RIGHT,POLY ++S 9500,22800,17100,22800,400,150nymous_,RIGHT,ALU2 ++S 9500,37000,17100,37000,2400,151nymous_,RIGHT,ALU2 ++S 33200,9100,33200,9900,400,108nymous_,UP,ALU1 ++S 50,6000,39950,6000,12000,266nymous_,RIGHT,TALU2 ++S 28700,24600,30300,24600,400,69onymous_,RIGHT,ALU2 ++S 24900,30000,28100,30000,420,32onymous_,RIGHT,PDIF ++S 33800,21100,33800,36500,620,109nymous_,UP,PDIF ++S 24900,31200,28100,31200,420,33onymous_,RIGHT,PDIF ++S 33800,21300,33800,36300,400,110nymous_,UP,ALU1 ++S 24900,32400,28100,32400,420,34onymous_,RIGHT,PDIF ++S 15300,37600,20700,37600,400,191nymous_,RIGHT,ALU1 ++S 29400,11100,29400,11700,400,70onymous_,UP,ALU1 ++S 15200,3700,15200,11300,400,192nymous_,UP,ALU2 ++S 15200,7500,15200,9100,420,193nymous_,UP,NDIF ++S 17700,26800,18900,26800,620,228nymous_,RIGHT,NDIF ++S 15200,8100,15200,8900,400,194nymous_,UP,ALU1 ++S 17700,28000,18900,28000,620,229nymous_,RIGHT,NDIF ++S 17700,29200,18900,29200,620,230nymous_,RIGHT,NDIF ++S 30200,8300,30200,9300,200,n16a,UP,NTRANS ++S 25400,9600,25400,10800,200,44onymous_,UP,POLY ++S 26000,30900,26000,37100,400,47onymous_,UP,ALU2 ++S 26000,23700,26000,29100,400,46onymous_,UP,ALU2 ++S 26000,6100,26000,7900,400,48onymous_,UP,ALU1 ++S 33000,20900,33000,36700,200,p14b,UP,PTRANS ++S 10000,22200,11600,22200,200,152nymous_,RIGHT,POLY ++S 24900,33600,28100,33600,420,35onymous_,RIGHT,PDIF ++S 33800,19100,33800,38300,2400,111nymous_,UP,ALU2 ++S 24900,35000,28100,35000,820,36onymous_,RIGHT,PDIF ++S 34000,18200,34000,38200,10400,112nymous_,UP,NWELL ++S 24900,36400,28100,36400,620,37onymous_,RIGHT,PDIF ++S 3280,6000,28520,6000,600,113nymous_,RIGHT,PTIE ++S 34400,8100,34400,8500,400,114nymous_,UP,ALU1 ++S 29400,11800,29400,12000,200,71onymous_,UP,POLY ++S 29300,37000,31900,37000,2400,72onymous_,RIGHT,ALU2 ++S 29480,37600,38520,37600,600,73onymous_,RIGHT,NTIE ++S 15200,11100,15200,13700,400,195nymous_,UP,ALU1 ++S 15200,11100,15200,14700,620,196nymous_,UP,PDIF ++S 15600,20700,15600,36300,400,197nymous_,UP,ALU1 ++S 17700,30400,18900,30400,620,231nymous_,RIGHT,NDIF ++S 17700,31600,18900,31600,620,232nymous_,RIGHT,NDIF ++S 17700,32800,18900,32800,620,233nymous_,RIGHT,NDIF ++S 17700,34000,18900,34000,620,234nymous_,RIGHT,NDIF ++S 16800,29800,17200,29800,200,cnb,RIGHT,POLY ++S 16800,28600,17200,28600,200,cnb,RIGHT,POLY ++S 16800,25000,17200,25000,200,cnb,RIGHT,POLY ++S 16800,23800,17200,23800,200,cnb,RIGHT,POLY ++S 29000,18900,29000,23700,400,cnb,UP,ALU2 ++S 28600,23400,29000,23400,600,cnb,RIGHT,POLY ++S 28600,22200,29000,22200,600,cnb,RIGHT,POLY ++S 28600,21000,29000,21000,600,cnb,RIGHT,POLY ++S 23700,19200,29300,19200,400,cnb,RIGHT,ALU2 ++S 26000,7500,26000,9100,620,49onymous_,UP,NDIF ++S 31400,8300,31400,9300,200,n16b,UP,NTRANS ++S 9700,19000,14900,19000,2400,153nymous_,RIGHT,ALU2 ++S 29000,12300,29000,13100,200,p16,UP,PTRANS ++S 700,25000,8900,25000,2400,154nymous_,RIGHT,ALU2 ++S 700,28000,15100,28000,2400,155nymous_,RIGHT,ALU2 ++S 24800,7500,24800,9100,620,38onymous_,UP,NDIF ++S 24800,8100,24800,12500,400,39onymous_,UP,ALU1 ++S 700,31000,8900,31000,2400,156nymous_,RIGHT,ALU2 ++S 34400,8500,34400,9100,620,115nymous_,UP,NDIF ++S 24900,9000,27100,9000,400,40onymous_,RIGHT,ALU1 ++S 24900,11000,29300,11000,400,41onymous_,RIGHT,ALU1 ++S 29600,8100,29600,8500,400,74onymous_,UP,ALU1 ++S 29700,8000,34300,8000,400,75onymous_,RIGHT,ALU1 ++S 29600,8500,29600,9100,620,76onymous_,UP,NDIF ++S 15600,22700,15600,36500,620,198nymous_,UP,NDIF ++S 29600,12500,29600,12900,620,77onymous_,UP,PDIF ++S 15300,18200,34700,18200,400,199nymous_,RIGHT,ALU2 ++S 15600,17900,15600,20500,400,200nymous_,UP,ALU2 ++S 17700,35200,18900,35200,620,235nymous_,RIGHT,NDIF ++S 17700,36400,18900,36400,620,236nymous_,RIGHT,NDIF ++S 17600,3700,17600,11300,400,237nymous_,UP,ALU2 ++S 17600,7500,17600,9100,420,238nymous_,UP,NDIF ++S 17600,8100,17600,8900,400,239nymous_,UP,ALU1 ++S 25400,7300,25400,9300,200,n17b,UP,NTRANS ++S 30200,9600,33800,9600,200,81onymous_,RIGHT,POLY ++S 15800,9600,15800,10600,200,202nymous_,UP,POLY ++S 25100,35000,29100,35000,400,43onymous_,RIGHT,ALU1 ++S 30100,20200,35900,20200,400,80onymous_,RIGHT,ALU1 ++S 15800,23700,15800,32300,400,201nymous_,UP,ALU2 ++S 30000,19900,30000,24900,400,79onymous_,UP,ALU2 ++S 29700,12800,30300,12800,400,78onymous_,RIGHT,ALU1 ++S 700,15400,33500,15400,1200,159nymous_,RIGHT,ALU2 ++S 35400,21100,35400,36500,620,117nymous_,UP,PDIF ++S 700,10000,11900,10000,2400,158nymous_,RIGHT,ALU2 ++S 24800,11300,24800,12900,620,42onymous_,UP,PDIF ++S 34800,20200,34800,20600,600,116nymous_,UP,POLY ++S 700,34000,16100,34000,2400,157nymous_,RIGHT,ALU2 ++S 12200,10000,18200,10000,600,nt,RIGHT,POLY ++S 29000,12000,29400,12000,200,nt,RIGHT,POLY ++S 26100,10000,33100,10000,400,50onymous_,RIGHT,ALU1 ++S 12200,7300,12200,9300,200,n18a,UP,NTRANS ++S 13200,22500,13200,36700,200,n15c,UP,NTRANS ++S 17600,11100,17600,14700,620,241nymous_,UP,PDIF ++S 25400,11100,25400,13100,200,p17b,UP,PTRANS ++S 17600,11100,17600,13700,400,240nymous_,UP,ALU1 ++S 17500,25000,19100,25000,200,n7c,RIGHT,NTRANS ++S 17500,23800,19100,23800,200,n7d,RIGHT,NTRANS ++S 24700,22200,28300,22200,200,p7b,RIGHT,PTRANS ++S 24700,21000,28300,21000,200,p7c,RIGHT,PTRANS ++S 30400,36400,30400,36600,200,82onymous_,UP,POLY ++S 1700,37600,9500,37600,400,203nymous_,RIGHT,ALU1 ++S 10800,22700,10800,36500,620,162nymous_,UP,NDIF ++S 10800,21800,10800,22200,600,161nymous_,UP,POLY ++S 10700,39600,35500,39600,2400,160nymous_,RIGHT,ALU1 ++S 4100,13000,33500,13000,2400,2nonymous_,RIGHT,ALU2 ++S 32900,12400,37100,12400,1200,1nonymous_,RIGHT,ALU2 ++S 35400,21300,35400,39700,400,118nymous_,UP,ALU1 ++S 20000,200,20000,2000,40000,0nonymous_,UP,TALU3 ++S 10000,22500,10000,36700,200,n15a,UP,NTRANS ++S 17500,29800,19100,29800,200,n7a,RIGHT,NTRANS ++S 17500,28600,19100,28600,200,n7b,RIGHT,NTRANS ++S 17500,27400,19100,27400,200,n6b,RIGHT,NTRANS ++S 24700,27000,28300,27000,200,p6c,RIGHT,PTRANS ++S 5200,22500,5200,36700,200,n14b,UP,NTRANS ++S 12200,10900,12200,14900,200,p18a,UP,PTRANS ++S 12800,8100,12800,13700,400,1.nq,UP,ALU1 ++S 17000,7300,17000,9300,200,n18e,UP,NTRANS ++S 17000,10900,17000,14900,200,p18e,UP,PTRANS ++S 24700,23400,28300,23400,200,p7a,RIGHT,PTRANS ++S 24700,24600,28300,24600,200,p10,RIGHT,PTRANS ++S 24700,25800,28300,25800,200,p13,RIGHT,PTRANS ++S 17500,26200,19100,26200,200,n6c,RIGHT,NTRANS ++S 30400,10100,30400,12700,400,83onymous_,UP,ALU1 ++S 30600,21100,30600,35900,620,84onymous_,UP,PDIF ++S 17900,22000,18700,22000,400,242nymous_,RIGHT,ALU1 ++S 10800,22900,10800,39700,400,163nymous_,UP,ALU1 ++S 20000,40100,20000,59900,4400,5nonymous_,UP,ALU1 ++S 34400,13700,34400,18500,400,4nonymous_,UP,ALU2 ++S 3600,22200,5200,22200,200,121nymous_,RIGHT,POLY ++S 34400,8700,34400,13900,400,3nonymous_,UP,ALU1 ++S 36000,20200,36000,20600,600,120nymous_,UP,POLY ++S 35300,17000,37100,17000,400,119nymous_,RIGHT,ALU2 ++S 17900,24400,18700,24400,400,244nymous_,RIGHT,ALU1 ++S 50,17000,39950,17000,10000,blockagenet,RIGHT,TALU2 ++S 17500,34600,19100,34600,200,n8b,RIGHT,NTRANS ++S 17500,33400,19100,33400,200,n8c,RIGHT,NTRANS ++S 17500,32200,19100,32200,200,n8d,RIGHT,NTRANS ++S 17500,31000,19100,31000,200,n6a,RIGHT,NTRANS ++S 24700,30600,28300,30600,200,p8c,RIGHT,PTRANS ++S 24700,29400,28300,29400,200,p6a,RIGHT,PTRANS ++S 24700,28200,28300,28200,200,p6b,RIGHT,PTRANS ++S 30680,6000,37120,6000,600,88onymous_,RIGHT,PTIE ++S 17900,25600,18700,25600,400,245nymous_,RIGHT,ALU1 ++S 30600,36400,31400,36400,200,87onymous_,RIGHT,POLY ++S 1700,19200,20700,19200,400,204nymous_,RIGHT,ALU1 ++S 11600,6100,11600,8900,400,164nymous_,UP,ALU1 ++S 1480,19200,20920,19200,600,205nymous_,RIGHT,PTIE ++S 1600,19300,1600,37500,400,206nymous_,UP,ALU1 ++S 11600,7500,11600,9100,620,165nymous_,UP,NDIF ++S 30600,21300,30600,35500,400,85onymous_,UP,ALU1 ++S 17900,23200,18700,23200,400,243nymous_,RIGHT,ALU1 ++S 1600,19080,1600,37720,600,207nymous_,UP,PTIE ++S 30600,26700,30600,35300,2400,86onymous_,UP,ALU2 ++S 20800,19300,20800,37500,400,7nonymous_,UP,ALU1 ++S 36700,37600,38100,37600,400,123nymous_,RIGHT,ALU1 ++S 19700,7600,37100,7600,1200,6nonymous_,RIGHT,ALU2 ++S 3480,16000,36920,16000,600,122nymous_,RIGHT,NTIE ++S 34600,20900,34600,36700,200,p14c,UP,PTRANS ++S 17500,35800,19100,35800,200,n8a,RIGHT,NTRANS ++S 24700,35800,28300,35800,200,p12,RIGHT,PTRANS ++S 24700,34200,28300,34200,200,p9,RIGHT,PTRANS ++S 24700,33000,28300,33000,200,p8a,RIGHT,PTRANS ++S 24700,31800,28300,31800,200,p8b,RIGHT,PTRANS ++S 26600,7300,26600,9300,200,n17c,UP,NTRANS ++S 900,37000,8900,37000,2400,168nymous_,RIGHT,ALU2 ++S 16400,6100,16400,7900,400,209nymous_,UP,ALU1 ++S 11600,11900,11600,15900,400,167nymous_,UP,ALU1 ++S 16400,29900,16400,32300,400,208nymous_,UP,ALU2 ++S 17900,26800,18700,26800,400,246nymous_,RIGHT,ALU1 ++S 30800,8500,30800,9100,420,89onymous_,UP,NDIF ++S 17900,28000,18700,28000,400,247nymous_,RIGHT,ALU1 ++S 30800,9100,30800,9900,400,90onymous_,UP,ALU1 ++S 13400,7300,13400,9300,200,n18b,UP,NTRANS ++S 36800,5880,36800,8720,600,124nymous_,UP,PTIE ++S 20800,19080,20800,37720,600,8nonymous_,UP,PTIE ++S 36800,6100,36800,9100,400,125nymous_,UP,ALU1 ++S 22000,23700,22000,28500,400,9nonymous_,UP,ALU2 ++S 11600,11100,11600,14700,620,166nymous_,UP,PDIF ++B 23000,28400,300,300,CONT_BODY_N,320nymous_ ++B 23000,27400,300,300,CONT_BODY_N,319nymous_ ++B 23000,29400,300,300,CONT_BODY_N,321nymous_ ++B 23000,26400,300,300,CONT_BODY_N,318nymous_ ++B 20800,23400,300,300,CONT_BODY_P,285nymous_ ++B 20800,24400,300,300,CONT_BODY_P,286nymous_ ++B 20800,25400,300,300,CONT_BODY_P,287nymous_ ++B 20800,26400,300,300,CONT_BODY_P,288nymous_ ++B 20800,27400,300,300,CONT_BODY_P,289nymous_ ++B 20800,28400,300,300,CONT_BODY_P,290nymous_ ++B 23000,30400,300,300,CONT_BODY_N,322nymous_ ++B 23000,31400,300,300,CONT_BODY_N,323nymous_ ++B 23000,32400,300,300,CONT_BODY_N,324nymous_ ++B 23000,33400,300,300,CONT_BODY_N,325nymous_ ++B 23000,37600,300,300,CONT_BODY_N,329nymous_ ++B 23000,36400,300,300,CONT_BODY_N,328nymous_ ++B 23000,35400,300,300,CONT_BODY_N,327nymous_ ++B 23000,34400,300,300,CONT_BODY_N,326nymous_ ++B 20800,32400,300,300,CONT_BODY_P,294nymous_ ++B 20800,31400,300,300,CONT_BODY_P,293nymous_ ++B 20800,30400,300,300,CONT_BODY_P,292nymous_ ++B 20800,29400,300,300,CONT_BODY_P,291nymous_ ++B 23600,6000,300,300,CONT_BODY_P,333nymous_ ++B 23400,17000,300,300,CONT_VIA2,332nymous_ ++B 23400,17000,300,300,CONT_VIA,331nymous_ ++B 23000,19200,300,300,CONT_BODY_N,330nymous_ ++B 20800,33400,300,300,CONT_BODY_P,295nymous_ ++B 20800,36400,300,300,CONT_BODY_P,298nymous_ ++B 20800,35400,300,300,CONT_BODY_P,297nymous_ ++B 23600,6000,300,300,CONT_VIA2,335nymous_ ++B 23600,7200,300,300,CONT_DIF_N,336nymous_ ++B 23600,8000,300,300,CONT_DIF_N,337nymous_ ++B 20800,34400,300,300,CONT_BODY_P,296nymous_ ++B 23600,6000,300,300,CONT_VIA,334nymous_ ++B 20800,37600,300,300,CONT_BODY_P,299nymous_ ++B 23600,16000,300,300,CONT_BODY_N,340nymous_ ++B 23600,12800,300,300,CONT_DIF_P,339nymous_ ++B 23600,12000,300,300,CONT_DIF_P,338nymous_ ++B 20800,19200,300,300,CONT_BODY_P,300nymous_ ++B 21200,6000,300,300,CONT_BODY_P,301nymous_ ++B 21200,6000,300,300,CONT_VIA2,302nymous_ ++B 21200,16000,300,300,CONT_BODY_N,303nymous_ ++B 24000,29200,300,300,CONT_POLY,344nymous_ ++B 24000,28200,300,300,CONT_VIA,343nymous_ ++B 24000,28200,300,300,CONT_POLY,342nymous_ ++B 24000,27000,300,300,CONT_POLY,341nymous_ ++B 21200,17000,300,300,CONT_VIA2,304nymous_ ++B 22000,24000,300,300,CONT_VIA2,305nymous_ ++B 22000,26000,300,300,CONT_VIA2,306nymous_ ++B 22400,6000,300,300,CONT_BODY_P,307nymous_ ++B 24000,34200,300,300,CONT_VIA,346nymous_ ++B 24000,34200,300,300,CONT_POLY,345nymous_ ++B 22400,6000,300,300,CONT_VIA2,308nymous_ ++B 22400,16000,300,300,CONT_BODY_N,309nymous_ ++B 22400,17000,300,300,CONT_VIA,310nymous_ ++B 22400,17000,300,300,CONT_VIA2,311nymous_ ++B 24000,35800,300,300,CONT_VIA,349nymous_ ++B 24000,35800,300,300,CONT_POLY,348nymous_ ++B 24000,34200,300,300,CONT_VIA2,347nymous_ ++B 23000,20400,300,300,CONT_BODY_N,312nymous_ ++B 23000,21400,300,300,CONT_BODY_N,313nymous_ ++B 29400,11000,200,200,CONT_TURN1,269nymous_ ++B 34400,14000,300,300,CONT_VIA,268nymous_ ++B 29600,8000,200,200,CONT_TURN1,270nymous_ ++B 24000,19200,300,300,CONT_BODY_N,351nymous_ ++B 24000,37600,300,300,CONT_BODY_N,350nymous_ ++B 23000,22400,300,300,CONT_BODY_N,314nymous_ ++B 23000,23400,300,300,CONT_BODY_N,315nymous_ ++B 30400,12800,200,200,CONT_TURN1,271nymous_ ++B 33200,10000,200,200,CONT_TURN1,272nymous_ ++B 34400,8000,200,200,CONT_TURN1,273nymous_ ++B 5000,19000,8300,2300,CONT_VIA2,274nymous_ ++B 24800,6000,300,300,CONT_VIA,353nymous_ ++B 24800,6000,300,300,CONT_BODY_P,352nymous_ ++B 19800,32800,200,200,CONT_TURN1,277nymous_ ++B 17800,22000,200,200,CONT_TURN1,276nymous_ ++B 17600,11000,200,200,CONT_TURN1,275nymous_ ++B 20000,6000,300,300,CONT_VIA2,279nymous_ ++B 20000,6000,300,300,CONT_BODY_P,278nymous_ ++B 20000,17000,300,300,CONT_VIA2,281nymous_ ++B 20000,16000,300,300,CONT_BODY_N,280nymous_ ++B 23000,25400,300,300,CONT_BODY_N,317nymous_ ++B 23000,24400,300,300,CONT_BODY_N,316nymous_ ++B 20800,20400,300,300,CONT_BODY_P,282nymous_ ++B 20800,21400,300,300,CONT_BODY_P,283nymous_ ++B 20800,22400,300,300,CONT_BODY_P,284nymous_ ++B 4400,35000,300,300,CONT_DIF_N,840nymous_ ++B 38000,33000,300,300,CONT_VIA2,786nymous_ ++B 36800,10000,300,300,CONT_VIA2,732nymous_ ++B 34400,8600,300,300,CONT_DIF_N,678nymous_ ++B 17600,16000,300,300,CONT_BODY_N,1163ymous_ ++B 1600,25400,300,300,CONT_BODY_P,1109ymous_ ++B 33200,6000,300,300,CONT_VIA2,624nymous_ ++B 32000,6000,300,300,CONT_BODY_P,570nymous_ ++B 28000,32400,300,300,CONT_DIF_P,463nymous_ ++B 29600,17000,300,300,CONT_VIA,517nymous_ ++B 14000,34000,300,300,CONT_DIF_N,1055ymous_ ++B 11600,6000,300,300,CONT_VIA,1001ymous_ ++B 26000,6000,300,300,CONT_VIA2,409nymous_ ++B 18800,13800,300,300,CONT_DIF_P,1215ymous_ ++B 8600,26000,300,300,CONT_VIA2,947nymous_ ++B 6800,37600,300,300,CONT_VIA,893nymous_ ++B 4400,34000,300,300,CONT_VIA,839nymous_ ++B 38000,29000,300,300,CONT_VIA2,785nymous_ ++B 34400,6000,300,300,CONT_VIA2,677nymous_ ++B 29600,16000,300,300,CONT_BODY_N,516nymous_ ++B 17600,13800,300,300,CONT_DIF_P,1162ymous_ ++B 1600,24400,300,300,CONT_BODY_P,1108ymous_ ++B 33200,6000,300,300,CONT_VIA,623nymous_ ++B 31600,35000,300,300,CONT_VIA2,569nymous_ ++B 26000,6000,300,300,CONT_VIA,408nymous_ ++B 28000,31200,300,300,CONT_VIA,462nymous_ ++B 14000,33000,300,300,CONT_DIF_N,1054ymous_ ++B 11600,6000,300,300,CONT_BODY_P,1000ymous_ ++B 18800,12800,300,300,CONT_DIF_P,1214ymous_ ++B 30600,31000,300,300,CONT_DIF_P,540nymous_ ++B 17600,17000,300,300,CONT_VIA2,1165ymous_ ++B 1600,27400,300,300,CONT_BODY_P,1111ymous_ ++B 14000,36000,300,300,CONT_DIF_N,1057ymous_ ++B 32000,6000,300,300,CONT_VIA2,572nymous_ ++B 26000,8000,300,300,CONT_DIF_N,411nymous_ ++B 18800,16000,300,300,CONT_BODY_N,1217ymous_ ++B 11600,8000,300,300,CONT_DIF_N,1003ymous_ ++B 8600,31000,300,300,CONT_VIA2,949nymous_ ++B 24800,11600,300,300,CONT_DIF_P,357nymous_ ++B 6800,6000,300,300,CONT_BODY_P,895nymous_ ++B 4400,35000,300,300,CONT_VIA,841nymous_ ++B 38000,34000,300,300,CONT_VIA2,787nymous_ ++B 36800,11000,300,300,CONT_VIA2,733nymous_ ++B 17600,17000,300,300,CONT_VIA,1164ymous_ ++B 34400,16000,300,300,CONT_BODY_N,679nymous_ ++B 33200,9000,300,300,CONT_DIF_N,625nymous_ ++B 28000,33600,300,300,CONT_DIF_P,464nymous_ ++B 29600,17000,300,300,CONT_VIA2,518nymous_ ++B 1600,26400,300,300,CONT_BODY_P,1110ymous_ ++B 14000,35000,300,300,CONT_DIF_N,1056ymous_ ++B 32000,6000,300,300,CONT_VIA,571nymous_ ++B 24800,9000,300,300,CONT_DIF_N,356nymous_ ++B 26000,7200,300,300,CONT_DIF_N,410nymous_ ++B 18800,14800,300,300,CONT_DIF_P,1216ymous_ ++B 11600,6000,300,300,CONT_VIA2,1002ymous_ ++B 8600,30000,300,300,CONT_VIA2,948nymous_ ++B 6800,37600,300,300,CONT_VIA2,894nymous_ ++B 11600,11800,300,300,CONT_DIF_P,1005ymous_ ++B 24800,16000,300,300,CONT_BODY_N,359nymous_ ++B 18800,17000,300,300,CONT_VIA2,1219ymous_ ++B 8600,36000,300,300,CONT_VIA2,951nymous_ ++B 6800,16000,300,300,CONT_BODY_N,897nymous_ ++B 4400,36000,300,300,CONT_VIA,843nymous_ ++B 38200,20400,300,300,CONT_BODY_N,789nymous_ ++B 36800,13000,300,300,CONT_BODY_N,735nymous_ ++B 34800,22000,300,300,CONT_VIA2,681nymous_ ++B 30000,19200,300,300,CONT_BODY_N,520nymous_ ++B 17600,19200,300,300,CONT_BODY_P,1166ymous_ ++B 1600,28400,300,300,CONT_BODY_P,1112ymous_ ++B 33200,17000,300,300,CONT_VIA,627nymous_ ++B 32000,8600,300,300,CONT_DIF_N,573nymous_ ++B 26000,10000,300,300,CONT_POLY,412nymous_ ++B 28000,19200,300,300,CONT_BODY_N,466nymous_ ++B 14000,4000,300,300,CONT_VIA2,1058ymous_ ++B 11600,9000,300,300,CONT_DIF_N,1004ymous_ ++B 24800,12600,300,300,CONT_DIF_P,358nymous_ ++B 18800,17000,300,300,CONT_VIA,1218ymous_ ++B 8600,32000,300,300,CONT_VIA2,950nymous_ ++B 6800,6000,300,300,CONT_VIA2,896nymous_ ++B 4400,36000,300,300,CONT_DIF_N,842nymous_ ++B 38000,35000,300,300,CONT_VIA2,788nymous_ ++B 36800,12000,300,300,CONT_BODY_N,734nymous_ ++B 34800,20200,300,300,CONT_POLY,680nymous_ ++B 33200,16000,300,300,CONT_BODY_N,626nymous_ ++B 30000,20200,300,300,CONT_VIA,519nymous_ ++B 28000,35000,300,300,CONT_DIF_P,465nymous_ ++B 4400,6000,300,300,CONT_BODY_P,845nymous_ ++B 38200,22400,300,300,CONT_BODY_N,791nymous_ ++B 36800,15000,300,300,CONT_BODY_N,737nymous_ ++B 17800,23200,300,300,CONT_VIA,1168ymous_ ++B 34800,27000,300,300,CONT_VIA2,683nymous_ ++B 33800,22000,300,300,CONT_DIF_P,629nymous_ ++B 2800,24000,300,300,CONT_DIF_N,468nymous_ ++B 30400,36600,300,300,CONT_VIA,522nymous_ ++B 1600,30400,300,300,CONT_BODY_P,1114ymous_ ++B 14000,7200,300,300,CONT_DIF_N,1060ymous_ ++B 32000,16000,300,300,CONT_BODY_N,575nymous_ ++B 24800,17000,300,300,CONT_VIA2,360nymous_ ++B 26000,12800,300,300,CONT_DIF_P,414nymous_ ++B 19600,19200,300,300,CONT_BODY_P,1220ymous_ ++B 11600,12800,300,300,CONT_DIF_P,1006ymous_ ++B 8600,19200,300,300,CONT_BODY_P,952nymous_ ++B 6800,17000,300,300,CONT_VIA,898nymous_ ++B 4400,36000,300,300,CONT_VIA2,844nymous_ ++B 38200,21400,300,300,CONT_BODY_N,790nymous_ ++B 36800,14000,300,300,CONT_BODY_N,736nymous_ ++B 34800,23000,300,300,CONT_VIA2,682nymous_ ++B 17800,23200,300,300,CONT_DIF_N,1167ymous_ ++B 1600,29400,300,300,CONT_BODY_P,1113ymous_ ++B 33200,17000,300,300,CONT_VIA2,628nymous_ ++B 32000,11000,300,300,CONT_POLY,574nymous_ ++B 2800,23000,300,300,CONT_DIF_N,467nymous_ ++B 30400,36600,300,300,CONT_POLY,521nymous_ ++B 14000,6000,300,300,CONT_BODY_P,1059ymous_ ++B 26000,12000,300,300,CONT_DIF_P,413nymous_ ++B 30600,22000,300,300,CONT_DIF_P,524nymous_ ++B 17800,24400,300,300,CONT_VIA2,1170ymous_ ++B 1600,32400,300,300,CONT_BODY_P,1116ymous_ ++B 32000,17000,300,300,CONT_VIA2,577nymous_ ++B 26000,17000,300,300,CONT_VIA,416nymous_ ++B 14000,10000,300,300,CONT_POLY,1062ymous_ ++B 11600,14800,300,300,CONT_DIF_P,1008ymous_ ++B 25000,20400,300,300,CONT_VIA,362nymous_ ++B 19800,26200,300,300,CONT_POLY,1222ymous_ ++B 8800,37600,300,300,CONT_VIA,954nymous_ ++B 7600,21800,300,300,CONT_POLY,900nymous_ ++B 4400,6000,300,300,CONT_VIA2,846nymous_ ++B 38200,23400,300,300,CONT_BODY_N,792nymous_ ++B 36800,15000,300,300,CONT_VIA2,738nymous_ ++B 17800,24400,300,300,CONT_DIF_N,1169ymous_ ++B 34800,28000,300,300,CONT_VIA2,684nymous_ ++B 33800,22000,300,300,CONT_VIA,630nymous_ ++B 30400,36600,300,300,CONT_VIA2,523nymous_ ++B 1600,31400,300,300,CONT_BODY_P,1115ymous_ ++B 14000,8000,300,300,CONT_DIF_N,1061ymous_ ++B 32000,17000,300,300,CONT_VIA,576nymous_ ++B 26000,16000,300,300,CONT_BODY_N,415nymous_ ++B 2800,25000,300,300,CONT_DIF_N,469nymous_ ++B 19800,22600,300,300,CONT_POLY,1221ymous_ ++B 11600,13800,300,300,CONT_DIF_P,1007ymous_ ++B 8800,37600,300,300,CONT_BODY_P,953nymous_ ++B 25000,20400,300,300,CONT_DIF_P,361nymous_ ++B 6800,17000,300,300,CONT_VIA2,899nymous_ ++B 25000,22800,300,300,CONT_DIF_P,364nymous_ ++B 19800,28200,300,300,CONT_VIA,1224ymous_ ++B 11600,17000,300,300,CONT_VIA,1010ymous_ ++B 9200,23000,300,300,CONT_DIF_N,956nymous_ ++B 7600,23000,300,300,CONT_DIF_N,902nymous_ ++B 4400,17000,300,300,CONT_VIA,848nymous_ ++B 38200,25400,300,300,CONT_BODY_N,794nymous_ ++B 36800,16000,300,300,CONT_VIA2,740nymous_ ++B 34800,33000,300,300,CONT_VIA2,686nymous_ ++B 17800,25600,300,300,CONT_DIF_N,1171ymous_ ++B 1600,33400,300,300,CONT_BODY_P,1117ymous_ ++B 33800,23000,300,300,CONT_DIF_P,632nymous_ ++B 32000,19200,300,300,CONT_BODY_N,578nymous_ ++B 2800,27000,300,300,CONT_DIF_N,471nymous_ ++B 30600,23000,300,300,CONT_DIF_P,525nymous_ ++B 14000,12000,300,300,CONT_DIF_P,1063ymous_ ++B 11600,16000,300,300,CONT_BODY_N,1009ymous_ ++B 25000,21600,300,300,CONT_DIF_P,363nymous_ ++B 26000,17000,300,300,CONT_VIA2,417nymous_ ++B 19800,27400,300,300,CONT_POLY,1223ymous_ ++B 8800,37600,300,300,CONT_VIA2,955nymous_ ++B 7600,21800,300,300,CONT_VIA,901nymous_ ++B 4400,16000,300,300,CONT_BODY_N,847nymous_ ++B 38200,24400,300,300,CONT_BODY_N,793nymous_ ++B 36800,16000,300,300,CONT_BODY_N,739nymous_ ++B 34800,29000,300,300,CONT_VIA2,685nymous_ ++B 33800,22000,300,300,CONT_VIA2,631nymous_ ++B 2800,26000,300,300,CONT_DIF_N,470nymous_ ++B 7600,24000,300,300,CONT_DIF_N,904nymous_ ++B 4600,37600,300,300,CONT_BODY_P,850nymous_ ++B 38200,27400,300,300,CONT_BODY_N,796nymous_ ++B 36800,17000,300,300,CONT_VIA2,742nymous_ ++B 17800,25600,300,300,CONT_VIA2,1173ymous_ ++B 34800,35000,300,300,CONT_VIA2,688nymous_ ++B 33800,23000,300,300,CONT_VIA2,634nymous_ ++B 30600,25000,300,300,CONT_DIF_P,527nymous_ ++B 1600,35400,300,300,CONT_BODY_P,1119ymous_ ++B 14000,13800,300,300,CONT_DIF_P,1065ymous_ ++B 3200,6000,300,300,CONT_VIA,580nymous_ ++B 2600,37600,300,300,CONT_BODY_P,419nymous_ ++B 2800,29000,300,300,CONT_DIF_N,473nymous_ ++B 19800,31000,300,300,CONT_POLY,1225ymous_ ++B 11600,17000,300,300,CONT_VIA2,1011ymous_ ++B 9200,24000,300,300,CONT_DIF_N,957nymous_ ++B 25000,22800,300,300,CONT_VIA,365nymous_ ++B 7600,23000,300,300,CONT_VIA,903nymous_ ++B 4400,17000,300,300,CONT_VIA2,849nymous_ ++B 38200,26400,300,300,CONT_BODY_N,795nymous_ ++B 36800,17000,300,300,CONT_VIA,741nymous_ ++B 17800,25600,300,300,CONT_VIA,1172ymous_ ++B 34800,34000,300,300,CONT_VIA2,687nymous_ ++B 33800,23000,300,300,CONT_VIA,633nymous_ ++B 2800,28000,300,300,CONT_DIF_N,472nymous_ ++B 30600,24000,300,300,CONT_DIF_P,526nymous_ ++B 1600,34400,300,300,CONT_BODY_P,1118ymous_ ++B 14000,12800,300,300,CONT_DIF_P,1064ymous_ ++B 3200,6000,300,300,CONT_BODY_P,579nymous_ ++B 26000,19200,300,300,CONT_BODY_N,418nymous_ ++B 2800,30000,300,300,CONT_DIF_N,474nymous_ ++B 14000,14800,300,300,CONT_DIF_P,1066ymous_ ++B 11600,19200,300,300,CONT_BODY_P,1012ymous_ ++B 25000,24000,300,300,CONT_DIF_P,366nymous_ ++B 19800,35200,300,300,CONT_VIA,1226ymous_ ++B 9200,25000,300,300,CONT_DIF_N,958nymous_ ++B 2600,19200,300,300,CONT_BODY_P,420nymous_ ++B 3200,6000,300,300,CONT_VIA2,581nymous_ ++B 33800,24000,300,300,CONT_DIF_P,635nymous_ ++B 1600,36400,300,300,CONT_BODY_P,1120ymous_ ++B 17800,26800,300,300,CONT_DIF_N,1174ymous_ ++B 30600,26000,300,300,CONT_DIF_P,528nymous_ ++B 35000,19200,300,300,CONT_BODY_N,689nymous_ ++B 37000,22000,300,300,CONT_DIF_P,743nymous_ ++B 38200,28400,300,300,CONT_BODY_N,797nymous_ ++B 4600,37600,300,300,CONT_VIA,851nymous_ ++B 7600,24000,300,300,CONT_VIA,905nymous_ ++B 9200,26000,300,300,CONT_DIF_N,959nymous_ ++B 19800,37600,300,300,CONT_BODY_P,1227ymous_ ++B 27000,20400,300,300,CONT_DIF_P,421nymous_ ++B 25000,25200,300,300,CONT_DIF_P,367nymous_ ++B 12400,23000,300,300,CONT_DIF_N,1013ymous_ ++B 14000,16000,300,300,CONT_BODY_N,1067ymous_ ++B 30600,27000,300,300,CONT_DIF_P,529nymous_ ++B 2800,31000,300,300,CONT_DIF_N,475nymous_ ++B 3200,7000,300,300,CONT_BODY_P,582nymous_ ++B 33800,24000,300,300,CONT_VIA,636nymous_ ++B 1600,37600,300,300,CONT_BODY_P,1121ymous_ ++B 35400,22000,300,300,CONT_DIF_P,690nymous_ ++B 37000,22000,300,300,CONT_VIA,744nymous_ ++B 38200,29400,300,300,CONT_BODY_N,798nymous_ ++B 4600,37600,300,300,CONT_VIA2,852nymous_ ++B 7600,24000,300,300,CONT_VIA2,906nymous_ ++B 9200,27000,300,300,CONT_DIF_N,960nymous_ ++B 12400,24000,300,300,CONT_DIF_N,1014ymous_ ++B 27000,21600,300,300,CONT_DIF_P,422nymous_ ++B 25000,26400,300,300,CONT_DIF_P,368nymous_ ++B 3200,7000,300,300,CONT_VIA2,583nymous_ ++B 14000,17000,300,300,CONT_VIA,1068ymous_ ++B 1600,19200,300,300,CONT_BODY_P,1122ymous_ ++B 30600,27000,300,300,CONT_VIA,530nymous_ ++B 2800,32000,300,300,CONT_DIF_N,476nymous_ ++B 33800,25000,300,300,CONT_DIF_P,637nymous_ ++B 35400,23000,300,300,CONT_DIF_P,691nymous_ ++B 17800,28000,300,300,CONT_VIA,1176ymous_ ++B 37000,22000,300,300,CONT_VIA2,745nymous_ ++B 38200,30400,300,300,CONT_BODY_N,799nymous_ ++B 4600,19200,300,300,CONT_BODY_P,853nymous_ ++B 7600,25000,300,300,CONT_DIF_N,907nymous_ ++B 25000,27600,300,300,CONT_DIF_P,369nymous_ ++B 9200,28000,300,300,CONT_DIF_N,961nymous_ ++B 12400,25000,300,300,CONT_DIF_N,1015ymous_ ++B 27000,22800,300,300,CONT_DIF_P,423nymous_ ++B 14000,17000,300,300,CONT_VIA2,1069ymous_ ++B 2800,33000,300,300,CONT_DIF_N,477nymous_ ++B 3200,8000,300,300,CONT_BODY_P,584nymous_ ++B 16400,4000,300,300,CONT_VIA2,1123ymous_ ++B 30600,27000,300,300,CONT_VIA2,531nymous_ ++B 33800,25000,300,300,CONT_VIA,638nymous_ ++B 35400,24000,300,300,CONT_DIF_P,692nymous_ ++B 17800,29200,300,300,CONT_DIF_N,1177ymous_ ++B 37000,23000,300,300,CONT_DIF_P,746nymous_ ++B 38200,31400,300,300,CONT_BODY_N,800nymous_ ++B 5400,24000,300,300,CONT_VIA2,854nymous_ ++B 7600,25000,300,300,CONT_VIA,908nymous_ ++B 9200,29000,300,300,CONT_DIF_N,962nymous_ ++B 25000,27600,300,300,CONT_VIA,370nymous_ ++B 12400,26000,300,300,CONT_DIF_N,1016ymous_ ++B 14600,19200,300,300,CONT_BODY_P,1070ymous_ ++B 2800,34000,300,300,CONT_DIF_N,478nymous_ ++B 27000,24000,300,300,CONT_DIF_P,424nymous_ ++B 3200,8000,300,300,CONT_VIA2,585nymous_ ++B 33800,26000,300,300,CONT_DIF_P,639nymous_ ++B 16400,6000,300,300,CONT_BODY_P,1124ymous_ ++B 17800,30400,300,300,CONT_DIF_N,1178ymous_ ++B 30600,28000,300,300,CONT_DIF_P,532nymous_ ++B 35400,25000,300,300,CONT_DIF_P,693nymous_ ++B 37000,23000,300,300,CONT_VIA,747nymous_ ++B 38200,32400,300,300,CONT_BODY_N,801nymous_ ++B 5400,25000,300,300,CONT_VIA2,855nymous_ ++B 7600,25000,300,300,CONT_VIA2,909nymous_ ++B 9200,30000,300,300,CONT_DIF_N,963nymous_ ++B 12400,27000,300,300,CONT_DIF_N,1017ymous_ ++B 27000,25200,300,300,CONT_DIF_P,425nymous_ ++B 25000,28800,300,300,CONT_DIF_P,371nymous_ ++B 15200,4000,300,300,CONT_VIA2,1071ymous_ ++B 30600,28000,300,300,CONT_VIA,533nymous_ ++B 2800,35000,300,300,CONT_DIF_N,479nymous_ ++B 3200,9000,300,300,CONT_BODY_P,586nymous_ ++B 33800,26000,300,300,CONT_VIA,640nymous_ ++B 16400,7200,300,300,CONT_DIF_N,1125ymous_ ++B 17800,30400,300,300,CONT_VIA,1179ymous_ ++B 35400,26000,300,300,CONT_DIF_P,694nymous_ ++B 37000,23000,300,300,CONT_VIA2,748nymous_ ++B 38200,33400,300,300,CONT_BODY_N,802nymous_ ++B 5400,26000,300,300,CONT_VIA2,856nymous_ ++B 7600,26000,300,300,CONT_DIF_N,910nymous_ ++B 9200,31000,300,300,CONT_DIF_N,964nymous_ ++B 12400,28000,300,300,CONT_DIF_N,1018ymous_ ++B 27000,25200,300,300,CONT_VIA,426nymous_ ++B 25000,30000,300,300,CONT_DIF_P,372nymous_ ++B 3200,12000,300,300,CONT_BODY_N,587nymous_ ++B 15200,6000,300,300,CONT_BODY_P,1072ymous_ ++B 16400,8000,300,300,CONT_DIF_N,1126ymous_ ++B 30600,28000,300,300,CONT_VIA2,534nymous_ ++B 2800,36000,300,300,CONT_DIF_N,480nymous_ ++B 33800,27000,300,300,CONT_DIF_P,641nymous_ ++B 35400,27000,300,300,CONT_DIF_P,695nymous_ ++B 37000,24000,300,300,CONT_DIF_P,749nymous_ ++B 38200,34400,300,300,CONT_BODY_N,803nymous_ ++B 5400,30000,300,300,CONT_VIA2,857nymous_ ++B 7600,26000,300,300,CONT_VIA,911nymous_ ++B 25000,30000,300,300,CONT_VIA,373nymous_ ++B 9200,32000,300,300,CONT_DIF_N,965nymous_ ++B 12400,29000,300,300,CONT_DIF_N,1019ymous_ ++B 28400,6000,300,300,CONT_BODY_P,481nymous_ ++B 27000,26400,300,300,CONT_DIF_P,427nymous_ ++B 3200,12000,300,300,CONT_VIA2,588nymous_ ++B 15200,8000,300,300,CONT_DIF_N,1073ymous_ ++B 16400,10000,300,300,CONT_POLY,1127ymous_ ++B 30600,29000,300,300,CONT_DIF_P,535nymous_ ++B 33800,27000,300,300,CONT_VIA,642nymous_ ++B 35400,28000,300,300,CONT_DIF_P,696nymous_ ++B 37000,24000,300,300,CONT_VIA,750nymous_ ++B 38200,35400,300,300,CONT_BODY_N,804nymous_ ++B 5400,31000,300,300,CONT_VIA2,858nymous_ ++B 7600,26000,300,300,CONT_VIA2,912nymous_ ++B 9200,33000,300,300,CONT_DIF_N,966nymous_ ++B 25000,31200,300,300,CONT_DIF_P,374nymous_ ++B 12400,30000,300,300,CONT_DIF_N,1020ymous_ ++B 15200,9000,300,300,CONT_DIF_N,1074ymous_ ++B 27000,27600,300,300,CONT_DIF_P,428nymous_ ++B 3200,13000,300,300,CONT_BODY_N,589nymous_ ++B 16400,12000,300,300,CONT_DIF_P,1128ymous_ ++B 30600,29000,300,300,CONT_VIA,536nymous_ ++B 28400,6000,300,300,CONT_VIA,482nymous_ ++B 33800,27000,300,300,CONT_VIA2,643nymous_ ++B 17800,31600,300,300,CONT_VIA2,1182ymous_ ++B 35400,29000,300,300,CONT_DIF_P,697nymous_ ++B 37000,25000,300,300,CONT_DIF_P,751nymous_ ++B 38200,36400,300,300,CONT_BODY_N,805nymous_ ++B 5400,32000,300,300,CONT_VIA2,859nymous_ ++B 7600,27000,300,300,CONT_DIF_N,913nymous_ ++B 9200,34000,300,300,CONT_DIF_N,967nymous_ ++B 27000,28800,300,300,CONT_DIF_P,429nymous_ ++B 25000,32400,300,300,CONT_DIF_P,375nymous_ ++B 12400,31000,300,300,CONT_DIF_N,1021ymous_ ++B 15200,9000,300,300,CONT_VIA,1075ymous_ ++B 30600,29000,300,300,CONT_VIA2,537nymous_ ++B 28400,6000,300,300,CONT_VIA2,483nymous_ ++B 3200,13000,300,300,CONT_VIA2,590nymous_ ++B 33800,28000,300,300,CONT_DIF_P,644nymous_ ++B 16400,12800,300,300,CONT_DIF_P,1129ymous_ ++B 35400,30000,300,300,CONT_DIF_P,698nymous_ ++B 37000,25000,300,300,CONT_VIA,752nymous_ ++B 38200,37600,300,300,CONT_BODY_N,806nymous_ ++B 5400,36000,300,300,CONT_VIA2,860nymous_ ++B 7600,27000,300,300,CONT_VIA,914nymous_ ++B 9200,35000,300,300,CONT_DIF_N,968nymous_ ++B 12400,32000,300,300,CONT_DIF_N,1022ymous_ ++B 25000,32400,300,300,CONT_VIA,376nymous_ ++B 17800,32800,300,300,CONT_DIF_N,1183ymous_ ++B 27000,30000,300,300,CONT_DIF_P,430nymous_ ++B 3200,14000,300,300,CONT_BODY_N,591nymous_ ++B 15200,10000,300,300,CONT_POLY,1076ymous_ ++B 16400,13800,300,300,CONT_DIF_P,1130ymous_ ++B 30600,30000,300,300,CONT_DIF_P,538nymous_ ++B 28400,8000,300,300,CONT_DIF_N,484nymous_ ++B 33800,28000,300,300,CONT_VIA,645nymous_ ++B 35400,31000,300,300,CONT_DIF_P,699nymous_ ++B 17800,34000,300,300,CONT_DIF_N,1184ymous_ ++B 37000,26000,300,300,CONT_DIF_P,753nymous_ ++B 38200,19200,300,300,CONT_BODY_N,807nymous_ ++B 5600,37600,300,300,CONT_BODY_P,861nymous_ ++B 7600,28000,300,300,CONT_DIF_N,915nymous_ ++B 25000,33600,300,300,CONT_DIF_P,377nymous_ ++B 9200,36000,300,300,CONT_DIF_N,969nymous_ ++B 12400,33000,300,300,CONT_DIF_N,1023ymous_ ++B 28400,9000,300,300,CONT_DIF_N,485nymous_ ++B 27000,31200,300,300,CONT_DIF_P,431nymous_ ++B 3200,14000,300,300,CONT_VIA2,592nymous_ ++B 15200,11000,300,300,CONT_VIA,1077ymous_ ++B 16400,14800,300,300,CONT_DIF_P,1131ymous_ ++B 30600,30000,300,300,CONT_VIA,539nymous_ ++B 33800,28000,300,300,CONT_VIA2,646nymous_ ++B 35400,32000,300,300,CONT_DIF_P,700nymous_ ++B 37000,26000,300,300,CONT_VIA,754nymous_ ++B 4400,21800,300,300,CONT_POLY,808nymous_ ++B 5600,37600,300,300,CONT_VIA,862nymous_ ++B 7600,28000,300,300,CONT_VIA,916nymous_ ++B 17800,30400,300,300,CONT_VIA2,1180ymous_ ++B 17800,31600,300,300,CONT_DIF_N,1181ymous_ ++B 17800,35200,300,300,CONT_DIF_N,1185ymous_ ++B 9200,6000,300,300,CONT_BODY_P,970nymous_ ++B 25000,35000,300,300,CONT_DIF_P,378nymous_ ++B 12400,34000,300,300,CONT_DIF_N,1024ymous_ ++B 15200,11800,300,300,CONT_DIF_P,1078ymous_ ++B 28400,10000,300,300,CONT_POLY,486nymous_ ++B 27000,32400,300,300,CONT_DIF_P,432nymous_ ++B 3200,15000,300,300,CONT_BODY_N,593nymous_ ++B 33800,29000,300,300,CONT_DIF_P,647nymous_ ++B 16400,16000,300,300,CONT_BODY_N,1132ymous_ ++B 35400,33000,300,300,CONT_DIF_P,701nymous_ ++B 37000,27000,300,300,CONT_DIF_P,755nymous_ ++B 4400,21800,300,300,CONT_VIA,809nymous_ ++B 5600,37600,300,300,CONT_VIA2,863nymous_ ++B 7600,29000,300,300,CONT_DIF_N,917nymous_ ++B 9200,6000,300,300,CONT_VIA2,971nymous_ ++B 27000,33600,300,300,CONT_DIF_P,433nymous_ ++B 25000,36400,300,300,CONT_DIF_P,379nymous_ ++B 12400,35000,300,300,CONT_DIF_N,1025ymous_ ++B 15200,12800,300,300,CONT_DIF_P,1079ymous_ ++B 28400,12000,300,300,CONT_DIF_P,487nymous_ ++B 3200,16000,300,300,CONT_BODY_N,594nymous_ ++B 33800,29000,300,300,CONT_VIA,648nymous_ ++B 16400,17000,300,300,CONT_VIA,1133ymous_ ++B 17800,36400,300,300,CONT_DIF_N,1186ymous_ ++B 17800,37600,300,300,CONT_BODY_P,1187ymous_ ++B 35400,34000,300,300,CONT_DIF_P,702nymous_ ++B 37000,27000,300,300,CONT_VIA,756nymous_ ++B 4400,23000,300,300,CONT_DIF_N,810nymous_ ++B 5600,6000,300,300,CONT_BODY_P,864nymous_ ++B 7600,29000,300,300,CONT_VIA,918nymous_ ++B 9200,16000,300,300,CONT_BODY_N,972nymous_ ++B 12400,36000,300,300,CONT_DIF_N,1026ymous_ ++B 27000,35000,300,300,CONT_DIF_P,434nymous_ ++B 25000,37600,300,300,CONT_BODY_N,380nymous_ ++B 3200,17000,300,300,CONT_VIA,595nymous_ ++B 15200,13800,300,300,CONT_DIF_P,1080ymous_ ++B 16400,17000,300,300,CONT_VIA2,1134ymous_ ++B 28400,12800,300,300,CONT_DIF_P,488nymous_ ++B 33800,29000,300,300,CONT_VIA2,649nymous_ ++B 35400,35000,300,300,CONT_DIF_P,703nymous_ ++B 37000,27000,300,300,CONT_VIA2,757nymous_ ++B 4400,23000,300,300,CONT_VIA,811nymous_ ++B 5600,6000,300,300,CONT_VIA2,865nymous_ ++B 7600,30000,300,300,CONT_DIF_N,919nymous_ ++B 25000,19200,300,300,CONT_BODY_N,381nymous_ ++B 9200,17000,300,300,CONT_VIA,973nymous_ ++B 12600,19200,300,300,CONT_BODY_P,1027ymous_ ++B 27000,36400,300,300,CONT_DIF_P,435nymous_ ++B 15200,16000,300,300,CONT_BODY_N,1081ymous_ ++B 30600,32000,300,300,CONT_DIF_P,542nymous_ ++B 18600,19200,300,300,CONT_BODY_P,1188ymous_ ++B 28400,16000,300,300,CONT_BODY_N,489nymous_ ++B 3200,17000,300,300,CONT_VIA2,596nymous_ ++B 16600,19200,300,300,CONT_BODY_P,1135ymous_ ++B 30600,32000,300,300,CONT_VIA,543nymous_ ++B 33800,30000,300,300,CONT_DIF_P,650nymous_ ++B 35400,36000,300,300,CONT_DIF_P,704nymous_ ++B 18800,22000,300,300,CONT_DIF_N,1189ymous_ ++B 37000,28000,300,300,CONT_DIF_P,758nymous_ ++B 4400,24000,300,300,CONT_DIF_N,812nymous_ ++B 5600,16000,300,300,CONT_BODY_N,866nymous_ ++B 7600,30000,300,300,CONT_VIA,920nymous_ ++B 9200,17000,300,300,CONT_VIA2,974nymous_ ++B 26000,20400,300,300,CONT_DIF_P,382nymous_ ++B 12800,4000,300,300,CONT_VIA2,1028ymous_ ++B 15200,17000,300,300,CONT_VIA,1082ymous_ ++B 28400,17000,300,300,CONT_VIA,490nymous_ ++B 27000,36400,300,300,CONT_VIA,436nymous_ ++B 32200,22000,300,300,CONT_DIF_P,597nymous_ ++B 33800,30000,300,300,CONT_VIA,651nymous_ ++B 16800,20200,300,300,CONT_VIA,1136ymous_ ++B 35600,6000,300,300,CONT_BODY_P,705nymous_ ++B 37000,28000,300,300,CONT_VIA,759nymous_ ++B 4400,24000,300,300,CONT_VIA,813nymous_ ++B 5600,17000,300,300,CONT_VIA,867nymous_ ++B 7600,30000,300,300,CONT_VIA2,921nymous_ ++B 9600,37600,300,300,CONT_BODY_P,975nymous_ ++B 12800,6000,300,300,CONT_BODY_P,1029ymous_ ++B 18800,22200,300,300,CONT_VIA,1190ymous_ ++B 30600,33000,300,300,CONT_DIF_P,544nymous_ ++B 27000,37600,300,300,CONT_BODY_N,437nymous_ ++B 26000,21600,300,300,CONT_DIF_P,383nymous_ ++B 15200,17000,300,300,CONT_VIA2,1083ymous_ ++B 30600,33000,300,300,CONT_VIA,545nymous_ ++B 28400,17000,300,300,CONT_VIA2,491nymous_ ++B 32200,23000,300,300,CONT_DIF_P,598nymous_ ++B 33800,31000,300,300,CONT_DIF_P,652nymous_ ++B 16800,23400,300,300,CONT_POLY,1137ymous_ ++B 35600,6000,300,300,CONT_VIA,706nymous_ ++B 37000,28000,300,300,CONT_VIA2,760nymous_ ++B 4400,24000,300,300,CONT_VIA2,814nymous_ ++B 5600,17000,300,300,CONT_VIA2,868nymous_ ++B 7600,31000,300,300,CONT_DIF_N,922nymous_ ++B 9600,19200,300,300,CONT_BODY_P,976nymous_ ++B 12800,8000,300,300,CONT_DIF_N,1030ymous_ ++B 27000,19200,300,300,CONT_BODY_N,438nymous_ ++B 26000,21600,300,300,CONT_VIA,384nymous_ ++B 32200,24000,300,300,CONT_DIF_P,599nymous_ ++B 15600,20200,300,300,CONT_VIA,1084ymous_ ++B 16800,24400,300,300,CONT_VIA,1138ymous_ ++B 29000,21000,300,300,CONT_POLY,492nymous_ ++B 33800,31000,300,300,CONT_VIA,653nymous_ ++B 35600,6000,300,300,CONT_VIA2,707nymous_ ++B 37000,29000,300,300,CONT_DIF_P,761nymous_ ++B 18800,23200,300,300,CONT_DIF_N,1191ymous_ ++B 30600,33000,300,300,CONT_VIA2,546nymous_ ++B 18800,24400,300,300,CONT_DIF_N,1192ymous_ ++B 4400,25000,300,300,CONT_DIF_N,815nymous_ ++B 5600,19200,300,300,CONT_BODY_P,869nymous_ ++B 7600,31000,300,300,CONT_VIA,923nymous_ ++B 26000,21600,300,300,CONT_VIA2,385nymous_ ++B 10400,6000,300,300,CONT_BODY_P,977nymous_ ++B 12800,9000,300,300,CONT_DIF_N,1031ymous_ ++B 29000,21000,300,300,CONT_VIA,493nymous_ ++B 27200,6000,300,300,CONT_BODY_P,439nymous_ ++B 32200,25000,300,300,CONT_DIF_P,600nymous_ ++B 15600,23000,300,300,CONT_DIF_N,1085ymous_ ++B 16800,25400,300,300,CONT_POLY,1139ymous_ ++B 30600,34000,300,300,CONT_DIF_P,547nymous_ ++B 33800,32000,300,300,CONT_DIF_P,654nymous_ ++B 35600,16000,300,300,CONT_BODY_N,708nymous_ ++B 37000,29000,300,300,CONT_VIA,762nymous_ ++B 4400,25000,300,300,CONT_VIA,816nymous_ ++B 6000,23000,300,300,CONT_DIF_N,870nymous_ ++B 7600,31000,300,300,CONT_VIA2,924nymous_ ++B 10400,6000,300,300,CONT_VIA2,978nymous_ ++B 26000,22800,300,300,CONT_DIF_P,386nymous_ ++B 12800,9000,300,300,CONT_VIA,1032ymous_ ++B 15600,24000,300,300,CONT_DIF_N,1086ymous_ ++B 27200,6000,300,300,CONT_VIA,440nymous_ ++B 12800,11800,300,300,CONT_DIF_P,1034ymous_ ++B 10400,17000,300,300,CONT_VIA,980nymous_ ++B 7600,32000,300,300,CONT_VIA,926nymous_ ++B 6000,25000,300,300,CONT_DIF_N,872nymous_ ++B 4400,26000,300,300,CONT_DIF_N,818nymous_ ++B 37000,30000,300,300,CONT_DIF_P,764nymous_ ++B 35600,17000,300,300,CONT_VIA2,710nymous_ ++B 16800,29200,300,300,CONT_VIA,1141ymous_ ++B 33800,33000,300,300,CONT_DIF_P,656nymous_ ++B 32200,27000,300,300,CONT_DIF_P,602nymous_ ++B 29000,22200,300,300,CONT_POLY,495nymous_ ++B 15600,25000,300,300,CONT_DIF_N,1087ymous_ ++B 18800,25600,300,300,CONT_DIF_N,1193ymous_ ++B 29000,21000,300,300,CONT_VIA2,494nymous_ ++B 32200,26000,300,300,CONT_DIF_P,601nymous_ ++B 33800,32000,300,300,CONT_VIA,655nymous_ ++B 16800,28200,300,300,CONT_POLY,1140ymous_ ++B 18800,26800,300,300,CONT_DIF_N,1194ymous_ ++B 30600,34000,300,300,CONT_VIA,548nymous_ ++B 35600,17000,300,300,CONT_VIA,709nymous_ ++B 37000,29000,300,300,CONT_VIA2,763nymous_ ++B 4400,25000,300,300,CONT_VIA2,817nymous_ ++B 6000,24000,300,300,CONT_DIF_N,871nymous_ ++B 7600,32000,300,300,CONT_DIF_N,925nymous_ ++B 10400,16000,300,300,CONT_BODY_N,979nymous_ ++B 27200,6000,300,300,CONT_VIA2,441nymous_ ++B 26000,22800,300,300,CONT_VIA2,387nymous_ ++B 12800,11000,300,300,CONT_VIA,1033ymous_ ++B 4400,26000,300,300,CONT_VIA,819nymous_ ++B 36000,20200,300,300,CONT_POLY,711nymous_ ++B 33800,33000,300,300,CONT_VIA,657nymous_ ++B 29000,22200,300,300,CONT_VIA,496nymous_ ++B 30600,35000,300,300,CONT_DIF_P,550nymous_ ++B 16800,32200,300,300,CONT_POLY,1142ymous_ ++B 15600,26000,300,300,CONT_DIF_N,1088ymous_ ++B 32200,28000,300,300,CONT_DIF_P,603nymous_ ++B 26000,24000,300,300,CONT_DIF_P,388nymous_ ++B 27200,8000,300,300,CONT_DIF_N,442nymous_ ++B 18800,26800,300,300,CONT_VIA,1195ymous_ ++B 30600,34000,300,300,CONT_VIA2,549nymous_ ++B 4400,26000,300,300,CONT_VIA2,820nymous_ ++B 37000,31000,300,300,CONT_DIF_P,766nymous_ ++B 36000,22000,300,300,CONT_VIA2,712nymous_ ++B 33800,33000,300,300,CONT_VIA2,658nymous_ ++B 16800,32200,300,300,CONT_VIA,1143ymous_ ++B 15600,27000,300,300,CONT_DIF_N,1089ymous_ ++B 32200,29000,300,300,CONT_DIF_P,604nymous_ ++B 27200,9000,300,300,CONT_DIF_N,443nymous_ ++B 29000,22200,300,300,CONT_VIA2,497nymous_ ++B 12800,12800,300,300,CONT_DIF_P,1035ymous_ ++B 10400,17000,300,300,CONT_VIA2,981nymous_ ++B 26000,24000,300,300,CONT_VIA,389nymous_ ++B 7600,32000,300,300,CONT_VIA2,927nymous_ ++B 6000,26000,300,300,CONT_DIF_N,873nymous_ ++B 37000,30000,300,300,CONT_VIA,765nymous_ ++B 18800,28000,300,300,CONT_DIF_N,1196ymous_ ++B 16800,33400,300,300,CONT_VIA,1145ymous_ ++B 29000,23400,300,300,CONT_VIA,499nymous_ ++B 15600,29000,300,300,CONT_DIF_N,1091ymous_ ++B 12800,16000,300,300,CONT_BODY_N,1037ymous_ ++B 26000,26400,300,300,CONT_DIF_P,391nymous_ ++B 10800,21800,300,300,CONT_POLY,983nymous_ ++B 7600,33000,300,300,CONT_VIA,929nymous_ ++B 6000,28000,300,300,CONT_DIF_N,875nymous_ ++B 4400,27000,300,300,CONT_DIF_N,821nymous_ ++B 37000,31000,300,300,CONT_VIA,767nymous_ ++B 36000,23000,300,300,CONT_VIA2,713nymous_ ++B 30600,35000,300,300,CONT_VIA2,552nymous_ ++B 16800,33400,300,300,CONT_POLY,1144ymous_ ++B 33800,34000,300,300,CONT_DIF_P,659nymous_ ++B 32200,30000,300,300,CONT_DIF_P,605nymous_ ++B 27200,10000,300,300,CONT_POLY,444nymous_ ++B 29000,23400,300,300,CONT_POLY,498nymous_ ++B 15600,28000,300,300,CONT_DIF_N,1090ymous_ ++B 12800,13800,300,300,CONT_DIF_P,1036ymous_ ++B 26000,25200,300,300,CONT_DIF_P,390nymous_ ++B 10600,19200,300,300,CONT_BODY_P,982nymous_ ++B 7600,33000,300,300,CONT_DIF_N,928nymous_ ++B 6000,27000,300,300,CONT_DIF_N,874nymous_ ++B 18800,29200,300,300,CONT_DIF_N,1197ymous_ ++B 30600,35000,300,300,CONT_VIA,551nymous_ ++B 15600,31000,300,300,CONT_DIF_N,1093ymous_ ++B 12800,17000,300,300,CONT_VIA2,1039ymous_ ++B 10800,21800,300,300,CONT_VIA2,985nymous_ ++B 7600,34000,300,300,CONT_VIA,931nymous_ ++B 6000,30000,300,300,CONT_DIF_N,877nymous_ ++B 4400,28000,300,300,CONT_DIF_N,823nymous_ ++B 37000,32000,300,300,CONT_VIA,769nymous_ ++B 36000,28000,300,300,CONT_VIA2,715nymous_ ++B 33800,34000,300,300,CONT_VIA2,661nymous_ ++B 29000,24600,300,300,CONT_POLY,500nymous_ ++B 16800,33400,300,300,CONT_VIA2,1146ymous_ ++B 15600,30000,300,300,CONT_DIF_N,1092ymous_ ++B 32200,32000,300,300,CONT_DIF_P,607nymous_ ++B 26000,26400,300,300,CONT_VIA,392nymous_ ++B 27200,12600,300,300,CONT_DIF_P,446nymous_ ++B 12800,17000,300,300,CONT_VIA,1038ymous_ ++B 10800,21800,300,300,CONT_VIA,984nymous_ ++B 7600,34000,300,300,CONT_DIF_N,930nymous_ ++B 6000,29000,300,300,CONT_DIF_N,876nymous_ ++B 4400,27000,300,300,CONT_VIA,822nymous_ ++B 37000,32000,300,300,CONT_DIF_P,768nymous_ ++B 36000,27000,300,300,CONT_VIA2,714nymous_ ++B 18800,31600,300,300,CONT_DIF_N,1199ymous_ ++B 33800,34000,300,300,CONT_VIA,660nymous_ ++B 32200,31000,300,300,CONT_DIF_P,606nymous_ ++B 30800,6000,300,300,CONT_BODY_P,553nymous_ ++B 27200,11600,300,300,CONT_DIF_P,445nymous_ ++B 18800,30400,300,300,CONT_DIF_N,1198ymous_ ++B 6000,32000,300,300,CONT_DIF_N,879nymous_ ++B 4400,29000,300,300,CONT_DIF_N,825nymous_ ++B 37000,33000,300,300,CONT_VIA,771nymous_ ++B 36000,33000,300,300,CONT_VIA2,717nymous_ ++B 16800,34600,300,300,CONT_VIA,1148ymous_ ++B 33800,35000,300,300,CONT_VIA,663nymous_ ++B 32200,34000,300,300,CONT_DIF_P,609nymous_ ++B 27200,17000,300,300,CONT_VIA,448nymous_ ++B 29000,25800,300,300,CONT_POLY,502nymous_ ++B 15600,32000,300,300,CONT_DIF_N,1094ymous_ ++B 13600,19200,300,300,CONT_BODY_P,1040ymous_ ++B 26000,27600,300,300,CONT_VIA2,394nymous_ ++B 10800,23000,300,300,CONT_DIF_N,986nymous_ ++B 7600,35000,300,300,CONT_DIF_N,932nymous_ ++B 6000,31000,300,300,CONT_DIF_N,878nymous_ ++B 4400,28000,300,300,CONT_VIA,824nymous_ ++B 37000,33000,300,300,CONT_DIF_P,770nymous_ ++B 36000,29000,300,300,CONT_VIA2,716nymous_ ++B 33800,35000,300,300,CONT_DIF_P,662nymous_ ++B 30800,6000,300,300,CONT_VIA2,555nymous_ ++B 16800,34600,300,300,CONT_POLY,1147ymous_ ++B 32200,33000,300,300,CONT_DIF_P,608nymous_ ++B 27200,16000,300,300,CONT_BODY_N,447nymous_ ++B 29000,24600,300,300,CONT_VIA,501nymous_ ++B 26000,27600,300,300,CONT_DIF_P,393nymous_ ++B 18800,31600,300,300,CONT_VIA,1200ymous_ ++B 30800,6000,300,300,CONT_VIA,554nymous_ ++B 18800,34000,300,300,CONT_DIF_N,1202ymous_ ++B 29000,31800,300,300,CONT_POLY,504nymous_ ++B 16800,35800,300,300,CONT_POLY,1150ymous_ ++B 15600,34000,300,300,CONT_DIF_N,1096ymous_ ++B 26000,28800,300,300,CONT_VIA,396nymous_ ++B 27800,36400,300,300,CONT_DIF_P,450nymous_ ++B 14000,21800,300,300,CONT_VIA,1042ymous_ ++B 10800,25000,300,300,CONT_DIF_N,988nymous_ ++B 7600,36000,300,300,CONT_DIF_N,934nymous_ ++B 6000,33000,300,300,CONT_DIF_N,880nymous_ ++B 4400,29000,300,300,CONT_VIA,826nymous_ ++B 37000,33000,300,300,CONT_VIA2,772nymous_ ++B 36000,34000,300,300,CONT_VIA2,718nymous_ ++B 16800,34600,300,300,CONT_VIA2,1149ymous_ ++B 33800,35000,300,300,CONT_VIA2,664nymous_ ++B 32200,35000,300,300,CONT_DIF_P,610nymous_ ++B 29000,30600,300,300,CONT_POLY,503nymous_ ++B 30800,16000,300,300,CONT_BODY_N,557nymous_ ++B 15600,33000,300,300,CONT_DIF_N,1095ymous_ ++B 14000,21800,300,300,CONT_POLY,1041ymous_ ++B 26000,28800,300,300,CONT_DIF_P,395nymous_ ++B 27200,17000,300,300,CONT_VIA2,449nymous_ ++B 10800,24000,300,300,CONT_DIF_N,987nymous_ ++B 7600,35000,300,300,CONT_VIA,933nymous_ ++B 30800,9000,300,300,CONT_DIF_N,556nymous_ ++B 18800,32800,300,300,CONT_DIF_N,1201ymous_ ++B 18800,34000,300,300,CONT_VIA,1203ymous_ ++B 15600,36000,300,300,CONT_DIF_N,1098ymous_ ++B 14000,23000,300,300,CONT_DIF_N,1044ymous_ ++B 18800,35200,300,300,CONT_DIF_N,1204ymous_ ++B 10800,27000,300,300,CONT_DIF_N,990nymous_ ++B 7600,36000,300,300,CONT_VIA2,936nymous_ ++B 6000,35000,300,300,CONT_DIF_N,882nymous_ ++B 4400,30000,300,300,CONT_VIA,828nymous_ ++B 37000,34000,300,300,CONT_VIA,774nymous_ ++B 36000,19200,300,300,CONT_BODY_N,720nymous_ ++B 33800,36000,300,300,CONT_VIA,666nymous_ ++B 16800,35800,300,300,CONT_VIA,1151ymous_ ++B 15600,35000,300,300,CONT_DIF_N,1097ymous_ ++B 32800,20200,300,300,CONT_POLY,612nymous_ ++B 27800,37600,300,300,CONT_BODY_N,451nymous_ ++B 29000,33000,300,300,CONT_POLY,505nymous_ ++B 14000,21800,300,300,CONT_VIA2,1043ymous_ ++B 10800,26000,300,300,CONT_DIF_N,989nymous_ ++B 26000,28800,300,300,CONT_VIA2,397nymous_ ++B 7600,36000,300,300,CONT_VIA,935nymous_ ++B 6000,34000,300,300,CONT_DIF_N,881nymous_ ++B 4400,30000,300,300,CONT_DIF_N,827nymous_ ++B 37000,34000,300,300,CONT_DIF_P,773nymous_ ++B 36000,35000,300,300,CONT_VIA2,719nymous_ ++B 33800,36000,300,300,CONT_DIF_P,665nymous_ ++B 30800,17000,300,300,CONT_VIA,558nymous_ ++B 32200,36000,300,300,CONT_DIF_P,611nymous_ ++B 7800,37600,300,300,CONT_BODY_P,938nymous_ ++B 6600,24000,300,300,CONT_VIA2,884nymous_ ++B 4400,31000,300,300,CONT_DIF_N,830nymous_ ++B 37000,35000,300,300,CONT_DIF_P,776nymous_ ++B 3600,37600,300,300,CONT_VIA,722nymous_ ++B 17600,4000,300,300,CONT_VIA2,1153ymous_ ++B 3400,24000,300,300,CONT_VIA2,668nymous_ ++B 32800,23000,300,300,CONT_VIA2,614nymous_ ++B 29400,11800,300,300,CONT_POLY,507nymous_ ++B 15600,19200,300,300,CONT_BODY_P,1099ymous_ ++B 14000,24000,300,300,CONT_DIF_N,1045ymous_ ++B 26000,31200,300,300,CONT_DIF_P,399nymous_ ++B 28000,21600,300,300,CONT_DIF_P,453nymous_ ++B 18800,36400,300,300,CONT_DIF_N,1205ymous_ ++B 10800,28000,300,300,CONT_DIF_N,991nymous_ ++B 7600,19200,300,300,CONT_BODY_P,937nymous_ ++B 6000,36000,300,300,CONT_DIF_N,883nymous_ ++B 4400,30000,300,300,CONT_VIA2,829nymous_ ++B 37000,34000,300,300,CONT_VIA2,775nymous_ ++B 3600,37600,300,300,CONT_BODY_P,721nymous_ ++B 31000,19200,300,300,CONT_BODY_N,560nymous_ ++B 16800,37600,300,300,CONT_BODY_P,1152ymous_ ++B 34000,19200,300,300,CONT_BODY_N,667nymous_ ++B 32800,22000,300,300,CONT_VIA2,613nymous_ ++B 28000,20400,300,300,CONT_DIF_P,452nymous_ ++B 29000,19200,300,300,CONT_BODY_N,506nymous_ ++B 26000,30000,300,300,CONT_DIF_P,398nymous_ ++B 30800,17000,300,300,CONT_VIA2,559nymous_ ++B 17600,8000,300,300,CONT_DIF_N,1155ymous_ ++B 15800,28000,300,300,CONT_VIA2,1101ymous_ ++B 32800,28000,300,300,CONT_VIA2,616nymous_ ++B 28000,24000,300,300,CONT_DIF_P,455nymous_ ++B 14000,26000,300,300,CONT_DIF_N,1047ymous_ ++B 10800,30000,300,300,CONT_DIF_N,993nymous_ ++B 26000,32400,300,300,CONT_DIF_P,401nymous_ ++B 18800,37600,300,300,CONT_BODY_P,1207ymous_ ++B 7800,37600,300,300,CONT_VIA,939nymous_ ++B 6600,25000,300,300,CONT_VIA2,885nymous_ ++B 4400,31000,300,300,CONT_VIA,831nymous_ ++B 37000,35000,300,300,CONT_VIA,777nymous_ ++B 3600,37600,300,300,CONT_VIA2,723nymous_ ++B 3400,25000,300,300,CONT_VIA2,669nymous_ ++B 29600,33000,300,300,CONT_VIA2,508nymous_ ++B 17600,6000,300,300,CONT_BODY_P,1154ymous_ ++B 15800,27000,300,300,CONT_VIA2,1100ymous_ ++B 32800,27000,300,300,CONT_VIA2,615nymous_ ++B 26000,31200,300,300,CONT_VIA,400nymous_ ++B 28000,22800,300,300,CONT_DIF_P,454nymous_ ++B 14000,25000,300,300,CONT_DIF_N,1046ymous_ ++B 10800,29000,300,300,CONT_DIF_N,992nymous_ ++B 18800,36400,300,300,CONT_VIA,1206ymous_ ++B 31600,20200,300,300,CONT_POLY,561nymous_ ++B 31600,22000,300,300,CONT_VIA2,562nymous_ ++B 36800,9000,300,300,CONT_VIA2,731nymous_ ++B 14000,28000,300,300,CONT_DIF_N,1049ymous_ ++B 18800,6000,300,300,CONT_VIA,1209ymous_ ++B 10800,32000,300,300,CONT_DIF_N,995nymous_ ++B 8000,6000,300,300,CONT_VIA2,941nymous_ ++B 6600,30000,300,300,CONT_VIA2,887nymous_ ++B 4400,32000,300,300,CONT_DIF_N,833nymous_ ++B 37000,36000,300,300,CONT_DIF_P,779nymous_ ++B 36800,6000,300,300,CONT_BODY_P,725nymous_ ++B 17600,9000,300,300,CONT_DIF_N,1156ymous_ ++B 3400,30000,300,300,CONT_VIA2,671nymous_ ++B 32800,29000,300,300,CONT_VIA2,617nymous_ ++B 28000,25200,300,300,CONT_DIF_P,456nymous_ ++B 29600,35000,300,300,CONT_VIA2,510nymous_ ++B 15800,29000,300,300,CONT_VIA2,1102ymous_ ++B 14000,27000,300,300,CONT_DIF_N,1048ymous_ ++B 26000,33600,300,300,CONT_DIF_P,402nymous_ ++B 18800,6000,300,300,CONT_BODY_P,1208ymous_ ++B 10800,31000,300,300,CONT_DIF_N,994nymous_ ++B 7800,37600,300,300,CONT_VIA2,940nymous_ ++B 6600,26000,300,300,CONT_VIA2,886nymous_ ++B 4400,31000,300,300,CONT_VIA2,832nymous_ ++B 37000,35000,300,300,CONT_VIA2,778nymous_ ++B 3600,19200,300,300,CONT_BODY_P,724nymous_ ++B 3400,26000,300,300,CONT_VIA2,670nymous_ ++B 29600,34000,300,300,CONT_VIA2,509nymous_ ++B 17800,28000,300,300,CONT_DIF_N,1175ymous_ ++B 31600,23000,300,300,CONT_VIA2,563nymous_ ++B 4400,32000,300,300,CONT_VIA2,835nymous_ ++B 37000,19200,300,300,CONT_BODY_N,781nymous_ ++B 36800,6000,300,300,CONT_VIA2,727nymous_ ++B 3400,32000,300,300,CONT_VIA2,673nymous_ ++B 29600,6000,300,300,CONT_VIA,512nymous_ ++B 17600,10000,300,300,CONT_POLY,1158ymous_ ++B 1600,20400,300,300,CONT_BODY_P,1104ymous_ ++B 32800,34000,300,300,CONT_VIA2,619nymous_ ++B 31600,28000,300,300,CONT_VIA2,565nymous_ ++B 26000,35000,300,300,CONT_DIF_P,404nymous_ ++B 28000,27600,300,300,CONT_DIF_P,458nymous_ ++B 14000,29000,300,300,CONT_DIF_N,1050ymous_ ++B 10800,33000,300,300,CONT_DIF_N,996nymous_ ++B 18800,6000,300,300,CONT_VIA2,1210ymous_ ++B 8000,16000,300,300,CONT_BODY_N,942nymous_ ++B 6600,31000,300,300,CONT_VIA2,888nymous_ ++B 4400,32000,300,300,CONT_VIA,834nymous_ ++B 37000,36000,300,300,CONT_VIA,780nymous_ ++B 36800,6000,300,300,CONT_VIA,726nymous_ ++B 17600,9000,300,300,CONT_VIA,1157ymous_ ++B 3400,31000,300,300,CONT_VIA2,672nymous_ ++B 32800,33000,300,300,CONT_VIA2,618nymous_ ++B 29600,6000,300,300,CONT_BODY_P,511nymous_ ++B 15800,37600,300,300,CONT_BODY_P,1103ymous_ ++B 31600,27000,300,300,CONT_VIA2,564nymous_ ++B 26000,33600,300,300,CONT_VIA,403nymous_ ++B 28000,26400,300,300,CONT_DIF_P,457nymous_ ++B 24800,6000,300,300,CONT_VIA2,354nymous_ ++B 24800,8000,300,300,CONT_DIF_N,355nymous_ ++B 30600,31000,300,300,CONT_VIA,541nymous_ ++B 17600,11800,300,300,CONT_DIF_P,1160ymous_ ++B 33000,19200,300,300,CONT_BODY_N,621nymous_ ++B 28000,30000,300,300,CONT_DIF_P,460nymous_ ++B 29600,8600,300,300,CONT_DIF_N,514nymous_ ++B 1600,22400,300,300,CONT_BODY_P,1106ymous_ ++B 28000,28800,300,300,CONT_DIF_P,459nymous_ ++B 29600,6000,300,300,CONT_VIA2,513nymous_ ++B 14000,30000,300,300,CONT_DIF_N,1051ymous_ ++B 10800,34000,300,300,CONT_DIF_N,997nymous_ ++B 26000,36400,300,300,CONT_DIF_P,405nymous_ ++B 18800,8000,300,300,CONT_DIF_N,1211ymous_ ++B 8000,17000,300,300,CONT_VIA,943nymous_ ++B 6600,32000,300,300,CONT_VIA2,889nymous_ ++B 31600,29000,300,300,CONT_VIA2,566nymous_ ++B 32800,35000,300,300,CONT_VIA2,620nymous_ ++B 1600,21400,300,300,CONT_BODY_P,1105ymous_ ++B 17600,11000,300,300,CONT_VIA,1159ymous_ ++B 3400,36000,300,300,CONT_VIA2,674nymous_ ++B 36800,7000,300,300,CONT_BODY_P,728nymous_ ++B 37200,37600,300,300,CONT_BODY_N,782nymous_ ++B 4400,33000,300,300,CONT_DIF_N,836nymous_ ++B 6600,36000,300,300,CONT_VIA2,890nymous_ ++B 8000,17000,300,300,CONT_VIA2,944nymous_ ++B 10800,35000,300,300,CONT_DIF_N,998nymous_ ++B 18800,9000,300,300,CONT_DIF_N,1212ymous_ ++B 26000,37600,300,300,CONT_BODY_N,406nymous_ ++B 31600,33000,300,300,CONT_VIA2,567nymous_ ++B 14000,31000,300,300,CONT_DIF_N,1052ymous_ ++B 8600,25000,300,300,CONT_VIA2,946nymous_ ++B 6800,37600,300,300,CONT_BODY_P,892nymous_ ++B 4400,34000,300,300,CONT_DIF_N,838nymous_ ++B 38000,28000,300,300,CONT_VIA2,784nymous_ ++B 36800,9000,300,300,CONT_BODY_P,730nymous_ ++B 17600,12800,300,300,CONT_DIF_P,1161ymous_ ++B 34400,6000,300,300,CONT_VIA,676nymous_ ++B 33200,6000,300,300,CONT_BODY_P,622nymous_ ++B 29600,12800,300,300,CONT_DIF_P,515nymous_ ++B 1600,23400,300,300,CONT_BODY_P,1107ymous_ ++B 14000,32000,300,300,CONT_DIF_N,1053ymous_ ++B 31600,34000,300,300,CONT_VIA2,568nymous_ ++B 26000,6000,300,300,CONT_BODY_P,407nymous_ ++B 28000,31200,300,300,CONT_DIF_P,461nymous_ ++B 18800,11800,300,300,CONT_DIF_P,1213ymous_ ++B 10800,36000,300,300,CONT_DIF_N,999nymous_ ++B 8600,24000,300,300,CONT_VIA2,945nymous_ ++B 6600,19200,300,300,CONT_BODY_P,891nymous_ ++B 4400,33000,300,300,CONT_VIA,837nymous_ ++B 38000,27000,300,300,CONT_VIA2,783nymous_ ++B 36800,8000,300,300,CONT_BODY_P,729nymous_ ++B 34400,6000,300,300,CONT_BODY_P,675nymous_ ++EOF +diff --git a/alliance/src/cells/src/mpxlib/pck_mpx.vbe b/alliance/src/cells/src/mpxlib/pck_mpx.vbe +new file mode 100644 +index 0000000..59f6ddd +--- /dev/null ++++ b/alliance/src/cells/src/mpxlib/pck_mpx.vbe +@@ -0,0 +1,29 @@ ++ENTITY pck_mpx IS ++ GENERIC ( ++ CONSTANT area : NATURAL := 80000; ++ CONSTANT cin_pad : NATURAL := 1326; ++ CONSTANT tpll_pad : NATURAL := 1443; ++ CONSTANT rdown_pad : NATURAL := 58; ++ CONSTANT tphh_pad : NATURAL := 228; ++ CONSTANT rup_pad : NATURAL := 68 ++ ); ++ PORT ( ++ pad : in BIT; ++ ck : out BIT; ++ vdde : in BIT; ++ vddi : in BIT; ++ vsse : in BIT; ++ vssi : in BIT ++ ); ++END pck_mpx; ++ ++ ++ARCHITECTURE behaviour_data_flow OF pck_mpx IS ++ ++BEGIN ++ ck <= pad; ++ ++ ASSERT ((((vddi and vdde) and not (vssi)) and not (vsse)) = '1') ++ REPORT "power supply is missing on pck_mpx" ++ SEVERITY WARNING; ++END; +diff --git a/alliance/src/cells/src/mpxlib/pi_mpx.ap b/alliance/src/cells/src/mpxlib/pi_mpx.ap +new file mode 100644 +index 0000000..6650743 +--- /dev/null ++++ b/alliance/src/cells/src/mpxlib/pi_mpx.ap +@@ -0,0 +1,1547 @@ ++V ALLIANCE : 6 ++H pi_mpx,P,14/9/2014,100 ++A 0,0,40000,80000 ++I 0,40000,padreal_mpx,padreal,NOSYM ++S 29000,35100,29000,39700,400,pad,UP,ALU1 ++S 29000,25900,29000,34900,400,pad,UP,ALU1 ++S 28600,33000,29000,33000,600,pad,RIGHT,POLY ++S 28600,31800,29000,31800,600,pad,RIGHT,POLY ++S 28600,30600,29000,30600,600,pad,RIGHT,POLY ++S 28600,25800,29000,25800,600,pad,RIGHT,POLY ++S 20000,48100,20000,71900,24400,pad,UP,CALU1 ++S 8000,0,8000,0,400,t,RIGHT,CALU5 ++S 8000,0,8000,0,400,t,RIGHT,CALU4 ++S 700,4000,39300,4000,1000,ck,RIGHT,CALU3 ++S 16800,33400,17200,33400,200,vdde,RIGHT,POLY ++S 700,28000,39300,28000,2400,vdde,RIGHT,CALU3 ++S 700,22000,39300,22000,2400,vdde,RIGHT,CALU3 ++S 3600,22200,5200,22200,200,vdde,RIGHT,POLY ++S 25100,28800,27900,28800,400,vdde,RIGHT,ALU1 ++S 25100,26400,27900,26400,400,vdde,RIGHT,ALU1 ++S 700,34000,39300,34000,2400,vdde,RIGHT,CALU3 ++S 6800,22200,8400,22200,200,vdde,RIGHT,POLY ++S 25100,21600,27900,21600,400,vdde,RIGHT,ALU1 ++S 24000,35800,24400,35800,600,vdde,RIGHT,POLY ++S 24000,34200,24400,34200,600,vdde,RIGHT,POLY ++S 16800,32200,17200,32200,200,vdde,RIGHT,POLY ++S 16800,35800,17200,35800,200,vdde,RIGHT,POLY ++S 16800,34600,17200,34600,200,vdde,RIGHT,POLY ++S 16800,29900,16800,38300,400,vdde,UP,ALU2 ++S 10500,21800,14300,21800,400,vdde,RIGHT,ALU2 ++S 25100,24000,27900,24000,400,vdde,RIGHT,ALU1 ++S 700,16000,39300,16000,2400,vddi,RIGHT,CALU3 ++S 700,10000,39300,10000,2400,vddi,RIGHT,CALU3 ++S 3100,16000,36900,16000,2400,vddi,RIGHT,ALU1 ++S 20000,9600,20000,11000,200,vddi,UP,POLY ++S 17800,22900,17800,31900,400,vsse,UP,ALU2 ++S 700,19000,39300,19000,2400,vsse,RIGHT,CALU3 ++S 700,37000,39300,37000,2400,vsse,RIGHT,CALU3 ++S 700,31000,39300,31000,2400,vsse,RIGHT,CALU3 ++S 700,25000,39300,25000,2400,vsse,RIGHT,CALU3 ++S 7600,22900,7600,37500,400,vsse,UP,ALU1 ++S 4400,22900,4400,37500,400,vsse,UP,ALU1 ++S 30400,36400,30400,36600,200,vsse,UP,POLY ++S 20800,22900,20800,37100,400,vsse,UP,ALU1 ++S 700,13000,39300,13000,2400,vssi,RIGHT,CALU3 ++S 700,7000,39300,7000,2400,vssi,RIGHT,CALU3 ++S 3100,6000,36900,6000,2400,vssi,RIGHT,ALU1 ++S 28800,9000,29000,9000,200,i,RIGHT,POLY ++S 27800,11800,28200,11800,200,i,RIGHT,POLY ++S 17500,22600,19100,22600,200,n6d,RIGHT,NTRANS ++S 28300,9000,28700,9000,400,91onymous_,RIGHT,ALU1 ++S 24900,31200,28100,31200,420,53onymous_,RIGHT,PDIF ++S 28300,10600,29500,10600,400,92onymous_,RIGHT,ALU1 ++S 20000,11100,20000,15900,400,12onymous_,UP,ALU1 ++S 28400,7500,28400,8100,620,93onymous_,UP,NDIF ++S 20000,12700,20000,17300,400,13onymous_,UP,ALU2 ++S 6200,10900,6200,14900,200,p18b,UP,PTRANS ++S 14600,11100,14600,13100,200,p17c,UP,PTRANS ++S 30800,10600,33800,10600,200,cnbb,RIGHT,POLY ++S 30800,8100,30800,12900,400,cnbb,UP,ALU1 ++S 6800,22500,6800,36700,200,n14c,UP,NTRANS ++S 14800,22500,14800,36700,200,n15d,UP,NTRANS ++S 35000,7300,35000,8300,200,n5b,UP,NTRANS ++S 35000,12700,35000,14700,200,p5b,UP,PTRANS ++S 27800,12500,27800,14500,200,p1,UP,PTRANS ++S 17700,29200,18900,29200,620,318nymous_,RIGHT,NDIF ++S 17700,30400,18900,30400,620,319nymous_,RIGHT,NDIF ++S 17700,31600,18900,31600,620,320nymous_,RIGHT,NDIF ++S 15600,22700,15600,36500,620,285nymous_,UP,NDIF ++S 24900,30000,28100,30000,420,52onymous_,RIGHT,PDIF ++S 20000,8100,20000,8500,400,11onymous_,UP,ALU1 ++S 10800,21800,10800,22200,600,249nymous_,UP,POLY ++S 10700,39600,35500,39600,2400,248nymous_,RIGHT,ALU1 ++S 7600,21800,7600,22200,600,211nymous_,UP,POLY ++S 31800,12000,31800,12200,200,127nymous_,UP,POLY ++S 20000,40100,20000,59900,4400,10onymous_,UP,ALU1 ++S 24900,28800,28100,28800,420,51onymous_,RIGHT,PDIF ++S 31600,20200,31600,20600,600,126nymous_,UP,POLY ++S 15300,18200,21300,18200,400,286nymous_,RIGHT,ALU2 ++S 17700,32800,18900,32800,620,321nymous_,RIGHT,NDIF ++S 7400,9600,7400,10600,200,210nymous_,UP,POLY ++S 35600,12900,35600,14500,620,169nymous_,UP,PDIF ++S 7300,21800,10100,21800,400,212nymous_,RIGHT,ALU2 ++S 31700,6000,37100,6000,400,128nymous_,RIGHT,ALU2 ++S 36000,20200,36000,20600,600,172nymous_,UP,POLY ++S 15800,23700,15800,32300,400,288nymous_,UP,ALU2 ++S 17700,35200,18900,35200,620,323nymous_,RIGHT,NDIF ++S 35300,17000,37100,17000,400,171nymous_,RIGHT,ALU2 ++S 15600,17900,15600,20500,400,287nymous_,UP,ALU2 ++S 17700,34000,18900,34000,620,322nymous_,RIGHT,NDIF ++S 35600,13100,35600,15900,400,170nymous_,UP,ALU1 ++S 31400,35300,31400,36100,200,p11,UP,PTRANS ++S 31400,20900,31400,34300,200,p14a,UP,PTRANS ++S 24900,35000,28100,35000,820,56onymous_,RIGHT,PDIF ++S 7600,22700,7600,38300,2400,215nymous_,UP,ALU2 ++S 1700,37600,9500,37600,400,290nymous_,RIGHT,ALU1 ++S 24900,33600,28100,33600,420,55onymous_,RIGHT,PDIF ++S 7600,22900,7600,37500,400,214nymous_,UP,ALU1 ++S 31700,7600,37100,7600,1200,130nymous_,RIGHT,ALU2 ++S 17700,36400,18900,36400,620,324nymous_,RIGHT,NDIF ++S 32000,7500,32000,8100,620,129nymous_,UP,NDIF ++S 15800,9600,15800,10800,200,289nymous_,UP,POLY ++S 7600,22700,7600,36500,620,213nymous_,UP,NDIF ++S 17700,8000,22300,8000,400,325nymous_,RIGHT,ALU1 ++S 3600,22200,5200,22200,200,173nymous_,RIGHT,POLY ++S 10800,22700,10800,36500,620,250nymous_,UP,NDIF ++S 24900,32400,28100,32400,420,54onymous_,RIGHT,PDIF ++S 28500,8000,30700,8000,400,94onymous_,RIGHT,ALU1 ++S 24900,36400,28100,36400,620,57onymous_,RIGHT,PDIF ++S 20800,19300,20800,37500,400,14onymous_,UP,ALU1 ++S 24800,7500,24800,8100,620,58onymous_,UP,NDIF ++S 20800,19080,20800,37720,600,15onymous_,UP,PTIE ++S 21000,13100,21000,13900,400,16onymous_,UP,ALU1 ++S 21100,13000,22300,13000,400,17onymous_,RIGHT,ALU1 ++S 24800,13100,24800,14500,620,60onymous_,UP,PDIF ++S 8000,7500,8000,9100,420,217nymous_,UP,NDIF ++S 11600,6100,11600,8900,400,253nymous_,UP,ALU1 ++S 28700,24600,30300,24600,400,97onymous_,RIGHT,ALU2 ++S 1600,19080,1600,37720,600,294nymous_,UP,PTIE ++S 36800,6100,36800,9100,400,177nymous_,UP,ALU1 ++S 24800,8100,24800,13900,400,59onymous_,UP,ALU1 ++S 28400,14100,28400,15900,400,96onymous_,UP,ALU1 ++S 1600,19300,1600,37500,400,293nymous_,UP,ALU1 ++S 36800,5880,36800,8720,600,176nymous_,UP,PTIE ++S 28400,12700,28400,14300,620,95onymous_,UP,PDIF ++S 1480,19200,20920,19200,600,292nymous_,RIGHT,PTIE ++S 17700,12800,18300,12800,400,329nymous_,RIGHT,ALU1 ++S 36700,37600,38100,37600,400,175nymous_,RIGHT,ALU1 ++S 3200,5880,3200,8720,600,133nymous_,UP,PTIE ++S 11000,9600,11000,10600,200,252nymous_,UP,POLY ++S 8000,-100,8000,11300,400,216nymous_,UP,ALU2 ++S 1700,19200,20700,19200,400,291nymous_,RIGHT,ALU1 ++S 2900,20600,15500,20600,400,pad2,RIGHT,ALU1 ++S 2700,20600,15700,20600,400,pad2,RIGHT,ALU1 ++S 21000,12700,21000,18500,400,pad2,UP,ALU2 ++S 20000,8500,20000,9100,620,pad2,UP,NDIF ++S 17600,8100,17600,8500,400,326nymous_,UP,ALU1 ++S 3480,16000,36920,16000,600,174nymous_,RIGHT,NTIE ++S 10800,22900,10800,39700,400,251nymous_,UP,ALU1 ++S 32000,8100,32000,12900,400,131nymous_,UP,ALU1 ++S 7400,10900,7400,14900,200,p18c,UP,PTRANS ++S 7400,7300,7400,9300,200,n18c,UP,NTRANS ++S 25400,8600,25400,12400,200,62onymous_,UP,POLY ++S 25100,35000,29100,35000,400,61onymous_,RIGHT,ALU1 ++S 21200,9100,21200,9900,400,19onymous_,UP,ALU1 ++S 21200,8500,21200,9100,420,18onymous_,UP,NDIF ++S 17600,12500,17600,12900,620,328nymous_,UP,PDIF ++S 32000,12900,32000,14500,620,132nymous_,UP,PDIF ++S 17600,8500,17600,9100,620,327nymous_,UP,NDIF ++S 26000,30900,26000,37100,400,65onymous_,UP,ALU2 ++S 26000,23700,26000,29100,400,64onymous_,UP,ALU2 ++S 26000,21300,26000,24300,400,63onymous_,UP,ALU2 ++S 2900,10000,6300,10000,2400,137nymous_,RIGHT,ALU2 ++S 11600,7500,11600,9100,420,254nymous_,UP,NDIF ++S 8000,8100,8000,8900,400,218nymous_,UP,ALU1 ++S 17900,24400,18700,24400,400,332nymous_,RIGHT,ALU1 ++S 16400,29900,16400,32300,400,295nymous_,UP,ALU2 ++S 36800,6900,36800,17300,400,178nymous_,UP,ALU2 ++S 2900,6000,7100,6000,400,136nymous_,RIGHT,ALU2 ++S 17900,23200,18700,23200,400,331nymous_,RIGHT,ALU1 ++S 3200,5700,3200,16100,400,135nymous_,UP,ALU2 ++S 17900,22000,18700,22000,400,330nymous_,RIGHT,ALU1 ++S 3200,6100,3200,9100,400,134nymous_,UP,ALU1 ++S 20600,8300,20600,9300,200,n16c,UP,NTRANS ++S 3600,22500,3600,36700,200,n14a,UP,NTRANS ++S 15800,7300,15800,9300,200,n17d,UP,NTRANS ++S 15800,11100,15800,13100,200,p17d,UP,PTRANS ++S 36800,11100,36800,15900,400,179nymous_,UP,ALU1 ++S 8000,11100,8000,13700,400,219nymous_,UP,ALU1 ++S 17900,25600,18700,25600,400,333nymous_,RIGHT,ALU1 ++S 11600,11100,11600,14700,620,255nymous_,UP,PDIF ++S 36800,10880,36800,16120,600,180nymous_,UP,NTIE ++S 8000,11100,8000,14700,620,220nymous_,UP,PDIF ++S 11600,11900,11600,15900,400,256nymous_,UP,ALU1 ++S 900,37000,8900,37000,2400,257nymous_,RIGHT,ALU2 ++S 29000,8600,29000,9000,200,98onymous_,UP,POLY ++S 22000,21900,22000,28500,400,20onymous_,UP,ALU2 ++S 29000,11400,29000,12200,200,99onymous_,UP,POLY ++S 22000,17900,22000,19500,400,21onymous_,UP,ALU2 ++S 29000,11400,32600,11400,200,100nymous_,RIGHT,POLY ++S 28700,18200,34700,18200,400,101nymous_,RIGHT,ALU2 ++S 11000,7300,11000,9300,200,n18f,UP,NTRANS ++S 36200,20900,36200,36700,200,p14d,UP,PTRANS ++S 16400,6100,16400,8900,400,296nymous_,UP,ALU1 ++S 3200,11100,3200,15900,400,138nymous_,UP,ALU1 ++S 25100,37000,27900,37000,1600,fbul,RIGHT,ALU1 ++S 25100,25200,27900,25200,400,fbul,RIGHT,ALU1 ++S 16400,7500,16400,9100,620,297nymous_,UP,NDIF ++S 17900,26800,18700,26800,400,334nymous_,RIGHT,ALU1 ++S 3200,10880,3200,16120,600,139nymous_,UP,NTIE ++S 37000,21100,37000,36500,620,181nymous_,UP,PDIF ++S 16400,11300,16400,12900,620,298nymous_,UP,PDIF ++S 17900,28000,18700,28000,400,335nymous_,RIGHT,ALU1 ++S 2900,15400,19300,15400,1200,140nymous_,RIGHT,ALU2 ++S 37000,21300,37000,36300,400,182nymous_,UP,ALU1 ++S 16400,12100,16400,15900,400,299nymous_,UP,ALU1 ++S 17900,30400,18700,30400,400,336nymous_,RIGHT,ALU1 ++S 900,19000,9300,19000,2400,258nymous_,RIGHT,ALU2 ++S 2900,17000,19100,17000,400,141nymous_,RIGHT,ALU2 ++S 37000,17700,37000,38300,2400,183nymous_,UP,ALU2 ++S 8600,9600,8600,10600,200,221nymous_,UP,POLY ++S 17900,31600,18700,31600,400,337nymous_,RIGHT,ALU1 ++S 21700,18200,25100,18200,400,22onymous_,RIGHT,ALU2 ++S 9200,20700,9200,36300,400,222nymous_,UP,ALU1 ++S 22000,19300,22000,22100,400,23onymous_,UP,ALU1 ++S 29000,18300,29000,19500,400,102nymous_,UP,ALU2 ++S 22400,8100,22400,8500,400,24onymous_,UP,ALU1 ++S 11000,10900,11000,14900,200,p18f,UP,PTRANS ++S 11600,22500,11600,36700,200,n15b,UP,NTRANS ++S 13200,22200,14800,22200,200,cn,RIGHT,POLY ++S 10000,22200,11600,22200,200,cn,RIGHT,POLY ++S 4100,21800,7900,21800,400,cn,RIGHT,ALU2 ++S 25100,22800,27900,22800,400,cn,RIGHT,ALU1 ++S 25100,20400,27900,20400,400,cn,RIGHT,ALU1 ++S 25000,20100,25000,23100,400,cn,UP,ALU2 ++S 29300,37000,31900,37000,2400,103nymous_,RIGHT,ALU2 ++S 22400,8500,22400,9100,620,25onymous_,UP,NDIF ++S 26000,6100,26000,7900,400,66onymous_,UP,ALU1 ++S 26000,7500,26000,8100,620,67onymous_,UP,NDIF ++S 12400,22700,12400,36500,620,261nymous_,UP,NDIF ++S 9200,6100,9200,7900,400,225nymous_,UP,ALU1 ++S 32600,11400,32600,12400,200,145nymous_,UP,POLY ++S 12400,20700,12400,36300,400,260nymous_,UP,ALU1 ++S 8900,6000,26300,6000,400,224nymous_,RIGHT,ALU2 ++S 1800,17700,1800,38300,1600,340nymous_,UP,ALU2 ++S 4400,21800,4400,22200,600,187nymous_,UP,POLY ++S 32600,8600,32600,9800,200,144nymous_,UP,POLY ++S 9200,22700,9200,36500,620,223nymous_,UP,NDIF ++S 16800,20900,16800,24700,400,303nymous_,UP,ALU2 ++S 3900,7600,7300,7600,1200,186nymous_,RIGHT,ALU2 ++S 17900,36400,18700,36400,400,339nymous_,RIGHT,ALU1 ++S 16500,21200,25300,21200,400,302nymous_,RIGHT,ALU2 ++S 38200,19080,38200,37920,600,185nymous_,UP,NTIE ++S 32200,21300,32200,39700,400,143nymous_,UP,ALU1 ++S 12200,9600,12200,10800,200,259nymous_,UP,POLY ++S 17900,34000,18700,34000,400,338nymous_,RIGHT,ALU1 ++S 16800,20300,16800,23300,400,301nymous_,UP,ALU1 ++S 38200,19300,38200,37500,400,184nymous_,UP,ALU1 ++S 32200,21100,32200,36500,620,142nymous_,UP,PDIF ++S 19500,36800,26300,36800,400,node_cp,RIGHT,ALU2 ++S 17900,35200,19700,35200,400,node_cp,RIGHT,ALU1 ++S 17900,32800,19700,32800,400,node_cp,RIGHT,ALU1 ++S 34600,20600,36200,20600,200,node_cp,RIGHT,POLY ++S 31400,20600,33000,20600,200,node_cp,RIGHT,POLY ++S 28600,24600,29000,24600,600,node_cp,RIGHT,POLY ++S 27700,24600,29300,24600,400,node_cp,RIGHT,ALU2 ++S 28000,24300,28000,31500,400,node_cp,UP,ALU2 ++S 25100,33600,27900,33600,400,node_cp,RIGHT,ALU1 ++S 25100,31200,27900,31200,400,node_cp,RIGHT,ALU1 ++S 16500,20200,24300,20200,400,300nymous_,RIGHT,ALU2 ++S 21800,8300,21800,9300,200,n16d,UP,NTRANS ++S 18500,31600,25300,31600,400,cpd,RIGHT,ALU2 ++S 18800,21900,18800,36700,400,cpd,UP,ALU2 ++S 25100,32400,27900,32400,400,cpd,RIGHT,ALU1 ++S 25100,30000,27900,30000,400,cpd,RIGHT,ALU1 ++S 25100,27600,27900,27600,400,cpd,RIGHT,ALU1 ++S 25000,27300,25000,32700,400,cpd,UP,ALU2 ++S 29000,7300,29000,8300,200,n1,UP,NTRANS ++S 9200,5700,9200,11300,400,226nymous_,UP,ALU2 ++S 12400,18500,12400,22100,2400,262nymous_,UP,ALU2 ++S 29480,37600,38520,37600,600,104nymous_,RIGHT,NTIE ++S 22400,8700,22400,12900,400,26onymous_,UP,ALU1 ++S 29600,7100,29600,8100,620,105nymous_,UP,NDIF ++S 22100,17000,23700,17000,400,27onymous_,RIGHT,ALU2 ++S 23100,37600,27700,37600,400,28onymous_,RIGHT,ALU1 ++S 16800,24100,16800,29500,400,305nymous_,UP,ALU2 ++S 4400,22700,4400,36500,620,188nymous_,UP,NDIF ++S 19500,28200,24300,28200,400,cpb,RIGHT,ALU2 ++S 19400,27400,19800,27400,200,cpb,RIGHT,POLY ++S 19400,26200,19800,26200,200,cpb,RIGHT,POLY ++S 24000,29200,24400,29200,600,cpb,RIGHT,POLY ++S 24000,28200,24400,28200,600,cpb,RIGHT,POLY ++S 19800,22700,19800,30900,400,cpb,UP,ALU1 ++S 19400,31000,19800,31000,200,cpb,RIGHT,POLY ++S 19400,22600,19800,22600,200,cpb,RIGHT,POLY ++S 24800,12700,24800,18500,400,cpb,UP,ALU2 ++S 24000,27000,24400,27000,600,cpb,RIGHT,POLY ++S 16800,23200,16800,25400,600,304nymous_,UP,POLY ++S 25400,7300,25400,8300,200,n4b,UP,NTRANS ++S 29000,12500,29000,14500,200,p2,UP,PTRANS ++S 8600,10900,8600,14900,200,p18d,UP,PTRANS ++S 12200,7300,12200,9300,200,n17a,UP,NTRANS ++S 8600,7300,8600,9300,200,n18d,UP,NTRANS ++S 8400,22500,8400,36700,200,n14d,UP,NTRANS ++S 18200,9600,21800,9600,200,341nymous_,RIGHT,POLY ++S 4400,22900,4400,37500,400,189nymous_,UP,ALU1 ++S 16900,24400,17700,24400,400,306nymous_,RIGHT,ALU1 ++S 32800,20200,32800,20600,600,146nymous_,UP,POLY ++S 18400,10100,18400,12700,400,342nymous_,UP,ALU1 ++S 16800,25500,16800,28100,400,307nymous_,UP,ALU1 ++S 9200,7500,9200,9100,620,227nymous_,UP,NDIF ++S 12800,7500,12800,9100,620,263nymous_,UP,NDIF ++S 4400,22700,4400,38300,2400,190nymous_,UP,ALU2 ++S 18800,8500,18800,9100,420,343nymous_,UP,NDIF ++S 12800,8100,12800,12500,400,264nymous_,UP,ALU1 ++S 33200,6100,33200,7900,400,147nymous_,UP,ALU1 ++S 29600,9800,29600,11400,200,106nymous_,UP,POLY ++S 12900,9000,15100,9000,400,265nymous_,RIGHT,ALU1 ++S 33200,7500,33200,8100,620,148nymous_,UP,NDIF ++S 18800,9100,18800,9900,400,344nymous_,UP,ALU1 ++S 29600,12700,29600,14300,620,107nymous_,UP,PDIF ++S 23000,11700,23000,17300,2000,29onymous_,UP,ALU2 ++S 33200,12900,33200,14500,620,149nymous_,UP,PDIF ++S 23000,19300,23000,37500,400,30onymous_,UP,ALU1 ++S 23000,19080,23000,37920,600,31onymous_,UP,NTIE ++S 26000,8700,26000,14300,400,68onymous_,UP,ALU2 ++S 24900,21600,28100,21600,420,45onymous_,RIGHT,PDIF ++S 24900,20400,28100,20400,620,44onymous_,RIGHT,PDIF ++S 17400,11100,17400,11700,400,310nymous_,UP,ALU1 ++S 17400,11800,17400,12000,200,311nymous_,UP,POLY ++S 18200,8300,18200,9300,200,n16a,UP,NTRANS ++S 12200,11100,12200,13100,200,p17a,UP,PTRANS ++S 32600,7300,32600,8300,200,n0,UP,NTRANS ++S 12200,10000,16400,10000,600,nnt,RIGHT,POLY ++S 27200,8100,27200,12900,400,cpbb,UP,ALU1 ++S 25400,10600,27200,10600,200,cpbb,RIGHT,POLY ++S 25400,12700,25400,14700,200,p4b,UP,PTRANS ++S 8900,10000,26300,10000,2400,228nymous_,RIGHT,ALU2 ++S 4400,6100,4400,8900,400,191nymous_,UP,ALU1 ++S 16800,28200,16800,29800,600,308nymous_,UP,POLY ++S 9200,11100,9200,14700,620,229nymous_,UP,PDIF ++S 16900,29200,18700,29200,400,309nymous_,RIGHT,ALU1 ++S 4400,7500,4400,9100,620,192nymous_,UP,NDIF ++S 9200,12100,9200,15900,400,230nymous_,UP,ALU1 ++S 12900,11000,17300,11000,400,266nymous_,RIGHT,ALU1 ++S 4400,11100,4400,14700,620,193nymous_,UP,PDIF ++S 18500,17000,20300,17000,400,345nymous_,RIGHT,ALU2 ++S 29600,13100,29600,13900,400,108nymous_,UP,ALU1 ++S 4400,11900,4400,15900,400,194nymous_,UP,ALU1 ++S 33200,13100,33200,15900,400,150nymous_,UP,ALU1 ++S 30000,19900,30000,24900,400,109nymous_,UP,ALU2 ++S 33400,11700,33400,17300,400,151nymous_,UP,ALU2 ++S 30100,20200,35900,20200,400,110nymous_,RIGHT,ALU1 ++S 23100,19200,38100,19200,400,32onymous_,RIGHT,ALU1 ++S 19800,32900,19800,35100,400,346nymous_,UP,ALU1 ++S 26000,12900,26000,14500,620,69onymous_,UP,PDIF ++S 22880,19200,38320,19200,600,33onymous_,RIGHT,NTIE ++S 26000,13100,26000,15900,400,70onymous_,UP,ALU1 ++S 23080,37600,29920,37600,600,34onymous_,RIGHT,NTIE ++S 24900,25200,28100,25200,420,48onymous_,RIGHT,PDIF ++S 24900,24000,28100,24000,420,47onymous_,RIGHT,PDIF ++S 24900,22800,28100,22800,420,46onymous_,RIGHT,PDIF ++S 17700,23200,18900,23200,620,313nymous_,RIGHT,NDIF ++S 17700,22000,18900,22000,620,312nymous_,RIGHT,NDIF ++S 32600,12700,32600,14700,200,p0,UP,PTRANS ++S 33000,20900,33000,36700,200,p14b,UP,PTRANS ++S 9300,25000,16100,25000,2400,231nymous_,RIGHT,ALU2 ++S 12800,11300,12800,12900,620,267nymous_,UP,PDIF ++S 9300,31000,16100,31000,2400,232nymous_,RIGHT,ALU2 ++S 4100,13000,20300,13000,2400,195nymous_,RIGHT,ALU2 ++S 9800,21500,9800,23100,400,233nymous_,UP,ALU2 ++S 33800,21100,33800,36500,620,152nymous_,UP,PDIF ++S 5000,9600,5000,10600,200,196nymous_,UP,POLY ++S 9500,22800,17100,22800,400,234nymous_,RIGHT,ALU2 ++S 13400,9600,13400,10800,200,268nymous_,UP,POLY ++S 30200,8600,30200,9000,200,111nymous_,UP,POLY ++S 19800,34900,19800,37100,400,347nymous_,UP,ALU2 ++S 26000,13700,26000,16100,400,71onymous_,UP,ALU2 ++S 23600,6100,23600,7900,400,35onymous_,UP,ALU1 ++S 14000,21800,14000,22200,600,269nymous_,UP,POLY ++S 30200,12000,30200,12200,200,112nymous_,UP,POLY ++S 25700,15400,32500,15400,1200,72onymous_,RIGHT,ALU2 ++S 23600,7500,23600,8100,620,36onymous_,UP,NDIF ++S 14000,22700,14000,36500,620,270nymous_,UP,NDIF ++S 25700,17000,33500,17000,400,73onymous_,RIGHT,ALU2 ++S 23600,12900,23600,14500,620,37onymous_,UP,PDIF ++S 5600,7500,5600,9100,420,197nymous_,UP,NDIF ++S 30400,36400,30400,36600,200,113nymous_,UP,POLY ++S 30600,21100,30600,35900,620,114nymous_,UP,PDIF ++S 24000,18900,24000,20500,400,41onymous_,UP,ALU2 ++S 27000,6900,27000,14300,400,77onymous_,UP,ALU2 ++S 5700,11000,10300,11000,400,200nymous_,RIGHT,ALU1 ++S 30600,21300,30600,35500,400,115nymous_,UP,ALU1 ++S 9700,19000,14900,19000,2400,238nymous_,RIGHT,ALU2 ++S 24900,26400,28100,26400,420,49onymous_,RIGHT,PDIF ++S 17700,25600,18900,25600,620,315nymous_,RIGHT,NDIF ++S 17700,24400,18900,24400,620,314nymous_,RIGHT,NDIF ++S 24200,7300,24200,8300,200,n4a,UP,NTRANS ++S 16800,29800,17200,29800,200,cnb,RIGHT,POLY ++S 16800,28600,17200,28600,200,cnb,RIGHT,POLY ++S 16800,25000,17200,25000,200,cnb,RIGHT,POLY ++S 16800,23800,17200,23800,200,cnb,RIGHT,POLY ++S 34400,12700,34400,18500,400,cnb,UP,ALU2 ++S 29000,17900,29000,23700,400,cnb,UP,ALU2 ++S 28600,23400,29000,23400,600,cnb,RIGHT,POLY ++S 28600,22200,29000,22200,600,cnb,RIGHT,POLY ++S 28600,21000,29000,21000,600,cnb,RIGHT,POLY ++S 23700,19200,29300,19200,400,cnb,RIGHT,ALU2 ++S 17000,12300,17000,13100,200,p16,UP,PTRANS ++S 19400,8300,19400,9300,200,n16b,UP,NTRANS ++S 33800,21300,33800,36300,400,153nymous_,UP,ALU1 ++S 9500,37000,17100,37000,2400,235nymous_,RIGHT,ALU2 ++S 33800,8600,33800,12400,200,154nymous_,UP,POLY ++S 9800,9600,9800,10600,200,236nymous_,UP,POLY ++S 33800,8600,35000,8600,200,155nymous_,RIGHT,POLY ++S 14000,22900,14000,39700,400,271nymous_,UP,ALU1 ++S 2700,20200,15700,20200,400,74onymous_,RIGHT,ALU1 ++S 23600,13100,23600,15900,400,38onymous_,UP,ALU1 ++S 33800,12400,35000,12400,200,156nymous_,RIGHT,POLY ++S 14000,6100,14000,7900,400,272nymous_,UP,ALU1 ++S 10000,22200,11600,22200,200,237nymous_,RIGHT,POLY ++S 26400,18600,26400,38600,8400,75onymous_,UP,NWELL ++S 24000,27100,24000,29100,400,39onymous_,UP,ALU1 ++S 5700,9000,10300,9000,400,198nymous_,RIGHT,ALU1 ++S 14000,7500,14000,9100,620,273nymous_,UP,NDIF ++S 24000,33900,24000,36100,400,40onymous_,UP,ALU2 ++S 5600,11100,5600,14700,620,199nymous_,UP,PDIF ++S 27000,24900,27000,36700,400,76onymous_,UP,ALU2 ++S 6000,22700,6000,36500,620,202nymous_,UP,NDIF ++S 30600,36400,31400,36400,200,117nymous_,RIGHT,POLY ++S 26700,13000,33700,13000,2400,78onymous_,RIGHT,ALU2 ++S 6000,20700,6000,36300,400,201nymous_,UP,ALU1 ++S 30600,26700,30600,35300,2400,116nymous_,UP,ALU2 ++S 700,25000,8900,25000,2400,239nymous_,RIGHT,ALU2 ++S 3280,6000,28520,6000,600,159nymous_,RIGHT,PTIE ++S 34000,18200,34000,38200,10400,158nymous_,UP,NWELL ++S 14100,10000,21100,10000,400,274nymous_,RIGHT,ALU1 ++S 33800,19100,33800,38300,2400,157nymous_,UP,ALU2 ++S 24700,22200,28300,22200,200,p7b,RIGHT,PTRANS ++S 24700,21000,28300,21000,200,p7c,RIGHT,PTRANS ++S 24200,12400,25400,12400,200,43onymous_,RIGHT,POLY ++S 24200,12700,24200,14700,200,p4a,UP,PTRANS ++S 17500,25000,19100,25000,200,n7c,RIGHT,NTRANS ++S 33800,7300,33800,8300,200,n5a,UP,NTRANS ++S 13400,11100,13400,13100,200,p17b,UP,PTRANS ++S 17000,12000,17400,12000,200,nt,RIGHT,POLY ++S 5000,10000,11000,10000,600,nt,RIGHT,POLY ++S 17500,23800,19100,23800,200,n7d,RIGHT,NTRANS ++S 30200,7300,30200,8300,200,n3,UP,NTRANS ++S 5000,7300,5000,9300,200,n18a,UP,NTRANS ++S 13400,7300,13400,9300,200,n17b,UP,NTRANS ++S 13200,22500,13200,36700,200,n15c,UP,NTRANS ++S 27200,7500,27200,8100,620,79onymous_,UP,NDIF ++S 700,28000,15100,28000,2400,240nymous_,RIGHT,ALU2 ++S 27200,12700,27200,14300,620,80onymous_,UP,PDIF ++S 24200,8600,25400,8600,200,42onymous_,RIGHT,POLY ++S 700,31000,8900,31000,2400,241nymous_,RIGHT,ALU2 ++S 27200,13100,27200,13900,400,81onymous_,UP,ALU1 ++S 24900,27600,28100,27600,420,50onymous_,RIGHT,PDIF ++S 14000,12100,14000,15900,400,276nymous_,UP,ALU1 ++S 34400,7500,34400,8100,620,160nymous_,UP,NDIF ++S 24700,27000,28300,27000,200,p6c,RIGHT,PTRANS ++S 14000,11300,14000,12900,620,275nymous_,UP,PDIF ++S 24700,25800,28300,25800,200,p13,RIGHT,PTRANS ++S 24700,24600,28300,24600,200,p10,RIGHT,PTRANS ++S 24700,23400,28300,23400,200,p7a,RIGHT,PTRANS ++S 17500,29800,19100,29800,200,n7a,RIGHT,NTRANS ++S 5600,8100,5600,13700,400,1.nq,UP,ALU1 ++S 10000,22500,10000,36700,200,n15a,UP,NTRANS ++S 17500,28600,19100,28600,200,n7b,RIGHT,NTRANS ++S 33800,12700,33800,14700,200,p5a,UP,PTRANS ++S 30200,12500,30200,14500,200,p3,UP,PTRANS ++S 9800,10900,9800,14900,200,p18e,UP,PTRANS ++S 17500,27400,19100,27400,200,n6b,RIGHT,NTRANS ++S 5200,22500,5200,36700,200,n14b,UP,NTRANS ++S 17500,26200,19100,26200,200,n6c,RIGHT,NTRANS ++S 9800,7300,9800,9300,200,n18e,UP,NTRANS ++S 5000,10900,5000,14900,200,p18a,UP,PTRANS ++S 30200,12000,31800,12000,200,eb,RIGHT,POLY ++S 30200,9000,31800,9000,200,eb,RIGHT,POLY ++S 34400,8100,34400,13900,400,161nymous_,UP,ALU1 ++S 1280,37600,21120,37600,600,277nymous_,RIGHT,PTIE ++S 30680,6000,37120,6000,600,118nymous_,RIGHT,PTIE ++S 34400,13100,34400,14500,620,162nymous_,UP,PDIF ++S 6200,9600,6200,10600,200,203nymous_,UP,POLY ++S 9200,6000,39950,6000,12000,0nonymous_,RIGHT,TALU2 ++S 27300,13000,29500,13000,400,82onymous_,RIGHT,ALU1 ++S 700,34000,16100,34000,2400,242nymous_,RIGHT,ALU2 ++S 50,6000,6800,6000,12000,1nonymous_,RIGHT,TALU2 ++S 27800,8600,27800,9800,200,83onymous_,UP,POLY ++S 9200,6000,39950,6000,12000,2nonymous_,RIGHT,TALU4 ++S 27800,9800,32600,9800,200,84onymous_,RIGHT,POLY ++S 24700,28200,28300,28200,200,p6b,RIGHT,PTRANS ++S 17500,34600,19100,34600,200,n8b,RIGHT,NTRANS ++S 50,17000,39950,17000,10000,blockagenet,RIGHT,TALU2 ++S 17500,33400,19100,33400,200,n8c,RIGHT,NTRANS ++S 17500,32200,19100,32200,200,n8d,RIGHT,NTRANS ++S 17500,31000,19100,31000,200,n6a,RIGHT,NTRANS ++S 24700,29400,28300,29400,200,p6a,RIGHT,PTRANS ++S 24700,30600,28300,30600,200,p8c,RIGHT,PTRANS ++S 14600,9600,14600,10800,200,278nymous_,UP,POLY ++S 30800,7500,30800,8100,620,119nymous_,UP,NDIF ++S 34800,20200,34800,20600,600,163nymous_,UP,POLY ++S 30800,12700,30800,14300,620,120nymous_,UP,PDIF ++S 6800,6100,6800,7900,400,204nymous_,UP,ALU1 ++S 10400,7500,10400,9100,420,243nymous_,UP,NDIF ++S 15300,37600,20700,37600,400,279nymous_,RIGHT,ALU1 ++S 30800,13100,30800,13900,400,121nymous_,UP,ALU1 ++S 6800,7500,6800,9100,620,205nymous_,UP,NDIF ++S 15200,7500,15200,9100,620,280nymous_,UP,NDIF ++S 50,6000,6800,6000,12000,3nonymous_,RIGHT,TALU4 ++S 35400,21100,35400,36500,620,164nymous_,UP,PDIF ++S 6900,10000,12700,10000,400,206nymous_,RIGHT,ALU1 ++S 15200,8100,15200,8900,400,281nymous_,UP,ALU1 ++S 27800,11800,27800,12400,200,85onymous_,UP,POLY ++S 0,6000,40000,6000,12000,4nonymous_,RIGHT,TALU6 ++S 35400,21300,35400,39700,400,165nymous_,UP,ALU1 ++S 6800,11100,6800,14700,620,207nymous_,UP,PDIF ++S 24600,200,24600,2000,31000,5nonymous_,UP,TALU3 ++S 10100,7600,27300,7600,1200,244nymous_,RIGHT,ALU2 ++S 2800,20500,2800,36300,400,86onymous_,UP,ALU1 ++S 10400,8100,10400,8900,400,245nymous_,UP,ALU1 ++S 2800,22700,2800,36500,620,87onymous_,UP,NDIF ++S 2200,13600,37800,13600,6800,88onymous_,RIGHT,NWELL ++S 28200,9100,28200,11700,400,90onymous_,UP,ALU1 ++S 17500,35800,19100,35800,200,n8a,RIGHT,NTRANS ++S 6200,7300,6200,9300,200,n18b,UP,NTRANS ++S 14600,7300,14600,9300,200,n17c,UP,NTRANS ++S 34600,20900,34600,36700,200,p14c,UP,PTRANS ++S 24700,31800,28300,31800,200,p8b,RIGHT,PTRANS ++S 24700,33000,28300,33000,200,p8a,RIGHT,PTRANS ++S 27800,7300,27800,8300,200,n2,UP,NTRANS ++S 24700,34200,28300,34200,200,p9,RIGHT,PTRANS ++S 24700,35800,28300,35800,200,p12,RIGHT,PTRANS ++S 31000,5700,31000,11300,400,122nymous_,UP,ALU2 ++S 17700,26800,18900,26800,620,316nymous_,RIGHT,NDIF ++S 30700,6000,32300,6000,400,123nymous_,RIGHT,ALU2 ++S 15200,11100,15200,12500,400,282nymous_,UP,ALU1 ++S 17700,28000,18900,28000,620,317nymous_,RIGHT,NDIF ++S 30700,10000,36100,10000,2400,124nymous_,RIGHT,ALU2 ++S 35100,13000,37100,13000,2400,166nymous_,RIGHT,ALU2 ++S 15200,11300,15200,12900,620,283nymous_,UP,PDIF ++S 6800,12100,6800,15900,400,208nymous_,UP,ALU1 ++S 3400,200,3400,2000,7000,6nonymous_,UP,TALU3 ++S 35600,6100,35600,7900,400,167nymous_,UP,ALU1 ++S 15600,20700,15600,36300,400,284nymous_,UP,ALU1 ++S 7000,6900,7000,14300,400,209nymous_,UP,ALU2 ++S 24600,200,24600,12000,31000,7nonymous_,UP,TALU5 ++S 35600,7500,35600,8100,620,168nymous_,UP,NDIF ++S 3400,200,3400,12000,7000,8nonymous_,UP,TALU5 ++S 31400,19100,31400,28300,400,125nymous_,UP,ALU2 ++S 10400,11100,10400,13700,400,246nymous_,UP,ALU1 ++S 20000,40100,20000,59900,4400,9nonymous_,UP,ALU1 ++S 10400,11100,10400,14700,620,247nymous_,UP,PDIF ++S 28200,6300,28200,10900,400,89onymous_,UP,ALU2 ++B 22400,8000,200,200,CONT_TURN1,349nymous_ ++B 21200,10000,200,200,CONT_TURN1,348nymous_ ++B 28200,9000,200,200,CONT_TURN1,351nymous_ ++B 22400,13000,200,200,CONT_TURN1,350nymous_ ++B 5000,19000,8300,2300,CONT_VIA2,352nymous_ ++B 10400,11000,200,200,CONT_TURN1,353nymous_ ++B 16400,9000,300,300,CONT_DIF_N,1268ymous_ ++B 15200,6000,300,300,CONT_BODY_P,1214ymous_ ++B 6800,37600,300,300,CONT_BODY_P,1000ymous_ ++B 7600,36000,300,300,CONT_VIA,1054ymous_ ++B 17800,36400,300,300,CONT_DIF_N,1322ymous_ ++B 23000,28400,300,300,CONT_BODY_N,408nymous_ ++B 28200,6600,300,300,CONT_VIA,569nymous_ ++B 9200,12800,300,300,CONT_DIF_P,1108ymous_ ++B 12400,26000,300,300,CONT_DIF_N,1162ymous_ ++B 27000,27600,300,300,CONT_DIF_P,516nymous_ ++B 25000,32400,300,300,CONT_DIF_P,462nymous_ ++B 30600,31000,300,300,CONT_DIF_P,623nymous_ ++B 3200,14000,300,300,CONT_BODY_N,677nymous_ ++B 35400,25000,300,300,CONT_DIF_P,785nymous_ ++B 37000,22000,300,300,CONT_VIA,839nymous_ ++B 38200,29400,300,300,CONT_BODY_N,893nymous_ ++B 4400,13800,300,300,CONT_DIF_P,947nymous_ ++B 16400,10000,300,300,CONT_POLY,1269ymous_ ++B 15200,6000,300,300,CONT_VIA,1215ymous_ ++B 6800,37600,300,300,CONT_VIA,1001ymous_ ++B 7600,36000,300,300,CONT_VIA2,1055ymous_ ++B 17800,37600,300,300,CONT_BODY_P,1323ymous_ ++B 23000,29400,300,300,CONT_BODY_N,409nymous_ ++B 28200,10600,300,300,CONT_VIA,570nymous_ ++B 9200,13800,300,300,CONT_DIF_P,1109ymous_ ++B 12400,27000,300,300,CONT_DIF_N,1163ymous_ ++B 27000,28800,300,300,CONT_DIF_P,517nymous_ ++B 25000,32400,300,300,CONT_VIA,463nymous_ ++B 30600,31000,300,300,CONT_VIA,624nymous_ ++B 3200,14000,300,300,CONT_VIA2,678nymous_ ++B 35400,26000,300,300,CONT_DIF_P,786nymous_ ++B 33800,28000,300,300,CONT_DIF_P,732nymous_ ++B 37000,22000,300,300,CONT_VIA2,840nymous_ ++B 28000,20400,300,300,CONT_DIF_P,540nymous_ ++B 38200,30400,300,300,CONT_BODY_N,894nymous_ ++B 4400,14800,300,300,CONT_DIF_P,948nymous_ ++B 6800,37600,300,300,CONT_VIA2,1002ymous_ ++B 16400,12000,300,300,CONT_DIF_P,1270ymous_ ++B 15200,6000,300,300,CONT_VIA2,1216ymous_ ++B 17800,22000,200,200,CONT_TURN1,356nymous_ ++B 7600,19200,300,300,CONT_BODY_P,1056ymous_ ++B 9200,14800,300,300,CONT_DIF_P,1110ymous_ ++B 18600,19200,300,300,CONT_BODY_P,1324ymous_ ++B 25000,33600,300,300,CONT_DIF_P,464nymous_ ++B 23000,30400,300,300,CONT_BODY_N,410nymous_ ++B 28200,11800,300,300,CONT_POLY,571nymous_ ++B 30600,32000,300,300,CONT_DIF_P,625nymous_ ++B 12400,28000,300,300,CONT_DIF_N,1164ymous_ ++B 27000,30000,300,300,CONT_DIF_P,518nymous_ ++B 3200,15000,300,300,CONT_BODY_N,679nymous_ ++B 33800,28000,300,300,CONT_VIA,733nymous_ ++B 35400,27000,300,300,CONT_DIF_P,787nymous_ ++B 37000,23000,300,300,CONT_DIF_P,841nymous_ ++B 38200,31400,300,300,CONT_BODY_N,895nymous_ ++B 15200,8000,300,300,CONT_DIF_N,1217ymous_ ++B 4400,16000,300,300,CONT_BODY_N,949nymous_ ++B 6800,6000,300,300,CONT_BODY_P,1003ymous_ ++B 18800,22000,300,300,CONT_DIF_N,1325ymous_ ++B 16400,12800,300,300,CONT_DIF_P,1271ymous_ ++B 18400,12800,200,200,CONT_TURN1,357nymous_ ++B 7800,37600,300,300,CONT_BODY_P,1057ymous_ ++B 9200,16000,300,300,CONT_BODY_N,1111ymous_ ++B 23000,31400,300,300,CONT_BODY_N,411nymous_ ++B 28400,6000,300,300,CONT_BODY_P,572nymous_ ++B 12400,29000,300,300,CONT_DIF_N,1165ymous_ ++B 25000,35000,300,300,CONT_DIF_P,465nymous_ ++B 30600,32000,300,300,CONT_VIA,626nymous_ ++B 27000,31200,300,300,CONT_DIF_P,519nymous_ ++B 3200,16000,300,300,CONT_BODY_N,680nymous_ ++B 33800,28000,300,300,CONT_VIA2,734nymous_ ++B 35400,28000,300,300,CONT_DIF_P,788nymous_ ++B 37000,23000,300,300,CONT_VIA,842nymous_ ++B 38200,32400,300,300,CONT_BODY_N,896nymous_ ++B 4400,17000,300,300,CONT_VIA,950nymous_ ++B 15200,9000,300,300,CONT_DIF_N,1218ymous_ ++B 6800,6000,300,300,CONT_VIA,1004ymous_ ++B 7800,37600,300,300,CONT_VIA,1058ymous_ ++B 18800,22200,300,300,CONT_VIA,1326ymous_ ++B 16400,16000,300,300,CONT_BODY_N,1272ymous_ ++B 23000,32400,300,300,CONT_BODY_N,412nymous_ ++B 19800,32800,200,200,CONT_TURN1,358nymous_ ++B 28400,8000,300,300,CONT_DIF_N,573nymous_ ++B 9200,17000,300,300,CONT_VIA,1112ymous_ ++B 12400,30000,300,300,CONT_DIF_N,1166ymous_ ++B 27000,32400,300,300,CONT_DIF_P,520nymous_ ++B 25000,36400,300,300,CONT_DIF_P,466nymous_ ++B 30600,33000,300,300,CONT_DIF_P,627nymous_ ++B 3200,17000,300,300,CONT_VIA,681nymous_ ++B 33800,29000,300,300,CONT_DIF_P,735nymous_ ++B 35400,29000,300,300,CONT_DIF_P,789nymous_ ++B 37000,23000,300,300,CONT_VIA2,843nymous_ ++B 38200,33400,300,300,CONT_BODY_N,897nymous_ ++B 4400,17000,300,300,CONT_VIA2,951nymous_ ++B 16400,17000,300,300,CONT_VIA,1273ymous_ ++B 15200,10000,300,300,CONT_POLY,1219ymous_ ++B 6800,6000,300,300,CONT_VIA2,1005ymous_ ++B 20000,6000,300,300,CONT_BODY_P,359nymous_ ++B 7800,37600,300,300,CONT_VIA2,1059ymous_ ++B 18800,23200,300,300,CONT_DIF_N,1327ymous_ ++B 23000,33400,300,300,CONT_BODY_N,413nymous_ ++B 28400,14000,300,300,CONT_DIF_P,574nymous_ ++B 9200,17000,300,300,CONT_VIA2,1113ymous_ ++B 12400,31000,300,300,CONT_DIF_N,1167ymous_ ++B 27000,33600,300,300,CONT_DIF_P,521nymous_ ++B 25000,37600,300,300,CONT_BODY_N,467nymous_ ++B 30600,33000,300,300,CONT_VIA,628nymous_ ++B 3200,17000,300,300,CONT_VIA2,682nymous_ ++B 35400,30000,300,300,CONT_DIF_P,790nymous_ ++B 33800,29000,300,300,CONT_VIA,736nymous_ ++B 37000,24000,300,300,CONT_DIF_P,844nymous_ ++B 38200,34400,300,300,CONT_BODY_N,898nymous_ ++B 4600,37600,300,300,CONT_BODY_P,952nymous_ ++B 6800,7200,300,300,CONT_DIF_N,1006ymous_ ++B 16400,17000,300,300,CONT_VIA2,1274ymous_ ++B 15200,11600,300,300,CONT_DIF_P,1220ymous_ ++B 20000,6000,300,300,CONT_VIA,360nymous_ ++B 8000,0,300,300,CONT_VIA2,1060ymous_ ++B 9600,37600,300,300,CONT_BODY_P,1114ymous_ ++B 18800,24400,300,300,CONT_DIF_N,1328ymous_ ++B 25000,19200,300,300,CONT_BODY_N,468nymous_ ++B 23000,34400,300,300,CONT_BODY_N,414nymous_ ++B 28400,16000,300,300,CONT_BODY_N,575nymous_ ++B 30600,33000,300,300,CONT_VIA2,629nymous_ ++B 12400,32000,300,300,CONT_DIF_N,1168ymous_ ++B 27000,35000,300,300,CONT_DIF_P,522nymous_ ++B 32200,22000,300,300,CONT_DIF_P,683nymous_ ++B 33800,29000,300,300,CONT_VIA2,737nymous_ ++B 35400,31000,300,300,CONT_DIF_P,791nymous_ ++B 37000,24000,300,300,CONT_VIA,845nymous_ ++B 15200,12600,300,300,CONT_DIF_P,1221ymous_ ++B 4600,37600,300,300,CONT_VIA,953nymous_ ++B 6800,8000,300,300,CONT_DIF_N,1007ymous_ ++B 18800,25600,300,300,CONT_DIF_N,1329ymous_ ++B 16600,19200,300,300,CONT_BODY_P,1275ymous_ ++B 20000,6000,300,300,CONT_VIA2,361nymous_ ++B 8000,0,300,300,CONT_VIA3,1061ymous_ ++B 9600,19200,300,300,CONT_BODY_P,1115ymous_ ++B 26000,20400,300,300,CONT_DIF_P,469nymous_ ++B 23000,35400,300,300,CONT_BODY_N,415nymous_ ++B 28400,17000,300,300,CONT_VIA,576nymous_ ++B 30600,34000,300,300,CONT_DIF_P,630nymous_ ++B 33800,30000,300,300,CONT_DIF_P,738nymous_ ++B 12400,33000,300,300,CONT_DIF_N,1169ymous_ ++B 27000,36400,300,300,CONT_DIF_P,523nymous_ ++B 32200,23000,300,300,CONT_DIF_P,684nymous_ ++B 35400,32000,300,300,CONT_DIF_P,792nymous_ ++B 37000,25000,300,300,CONT_DIF_P,846nymous_ ++B 38200,36400,300,300,CONT_BODY_N,900nymous_ ++B 4600,37600,300,300,CONT_VIA2,954nymous_ ++B 15200,16000,300,300,CONT_BODY_N,1222ymous_ ++B 6800,10000,300,300,CONT_POLY,1008ymous_ ++B 8000,0,300,300,CONT_VIA4,1062ymous_ ++B 18800,26800,300,300,CONT_DIF_N,1330ymous_ ++B 16800,20200,300,300,CONT_VIA,1276ymous_ ++B 23000,36400,300,300,CONT_BODY_N,416nymous_ ++B 20000,8600,300,300,CONT_DIF_N,362nymous_ ++B 28400,17000,300,300,CONT_VIA2,577nymous_ ++B 10400,6000,300,300,CONT_BODY_P,1116ymous_ ++B 12400,34000,300,300,CONT_DIF_N,1170ymous_ ++B 27000,36400,300,300,CONT_VIA,524nymous_ ++B 38200,35400,300,300,CONT_BODY_N,899nymous_ ++B 4600,19200,300,300,CONT_BODY_P,955nymous_ ++B 16800,23400,300,300,CONT_POLY,1277ymous_ ++B 15200,17000,300,300,CONT_VIA,1223ymous_ ++B 6800,12000,300,300,CONT_DIF_P,1009ymous_ ++B 8000,8000,300,300,CONT_DIF_N,1063ymous_ ++B 18800,26800,300,300,CONT_VIA,1331ymous_ ++B 23000,37600,300,300,CONT_BODY_N,417nymous_ ++B 20000,11000,300,300,CONT_POLY,363nymous_ ++B 28800,9000,300,300,CONT_POLY,578nymous_ ++B 10400,6000,300,300,CONT_VIA,1117ymous_ ++B 12400,35000,300,300,CONT_DIF_N,1171ymous_ ++B 27000,37600,300,300,CONT_BODY_N,525nymous_ ++B 26000,21600,300,300,CONT_VIA,471nymous_ ++B 30600,34000,300,300,CONT_VIA2,632nymous_ ++B 32200,25000,300,300,CONT_DIF_P,686nymous_ ++B 33800,31000,300,300,CONT_DIF_P,740nymous_ ++B 35400,34000,300,300,CONT_DIF_P,794nymous_ ++B 37000,26000,300,300,CONT_DIF_P,848nymous_ ++B 38200,19200,300,300,CONT_BODY_N,902nymous_ ++B 5400,24000,300,300,CONT_VIA2,956nymous_ ++B 6800,12800,300,300,CONT_DIF_P,1010ymous_ ++B 16800,24400,300,300,CONT_VIA,1278ymous_ ++B 15200,17000,300,300,CONT_VIA2,1224ymous_ ++B 20000,16000,300,300,CONT_BODY_N,364nymous_ ++B 18800,28000,300,300,CONT_DIF_N,1332ymous_ ++B 38200,37600,300,300,CONT_BODY_N,901nymous_ ++B 37000,25000,300,300,CONT_VIA,847nymous_ ++B 35400,33000,300,300,CONT_DIF_P,793nymous_ ++B 33800,30000,300,300,CONT_VIA,739nymous_ ++B 32200,24000,300,300,CONT_DIF_P,685nymous_ ++B 30600,34000,300,300,CONT_VIA,631nymous_ ++B 26000,21600,300,300,CONT_DIF_P,470nymous_ ++B 4400,21800,300,300,CONT_VIA,904nymous_ ++B 37000,27000,300,300,CONT_DIF_P,850nymous_ ++B 35400,36000,300,300,CONT_DIF_P,796nymous_ ++B 32200,27000,300,300,CONT_DIF_P,688nymous_ ++B 27000,10000,300,300,CONT_VIA2,527nymous_ ++B 12600,19200,300,300,CONT_BODY_P,1173ymous_ ++B 33800,32000,300,300,CONT_DIF_P,742nymous_ ++B 30600,35000,300,300,CONT_VIA,634nymous_ ++B 29000,21000,300,300,CONT_VIA,580nymous_ ++B 23400,17000,300,300,CONT_VIA,419nymous_ ++B 26000,22800,300,300,CONT_DIF_P,473nymous_ ++B 10400,8000,300,300,CONT_DIF_N,1119ymous_ ++B 8000,9000,300,300,CONT_VIA,1065ymous_ ++B 20800,20400,300,300,CONT_BODY_P,365nymous_ ++B 16800,25400,300,300,CONT_POLY,1279ymous_ ++B 18800,29200,300,300,CONT_DIF_N,1333ymous_ ++B 6800,13800,300,300,CONT_DIF_P,1011ymous_ ++B 5400,25000,300,300,CONT_VIA2,957nymous_ ++B 15600,20200,300,300,CONT_VIA,1225ymous_ ++B 4400,21800,300,300,CONT_POLY,903nymous_ ++B 37000,26000,300,300,CONT_VIA,849nymous_ ++B 35400,35000,300,300,CONT_DIF_P,795nymous_ ++B 33800,31000,300,300,CONT_VIA,741nymous_ ++B 32200,26000,300,300,CONT_DIF_P,687nymous_ ++B 27000,9000,300,300,CONT_VIA2,526nymous_ ++B 12400,36000,300,300,CONT_DIF_N,1172ymous_ ++B 30600,35000,300,300,CONT_DIF_P,633nymous_ ++B 29000,21000,300,300,CONT_POLY,579nymous_ ++B 23000,19200,300,300,CONT_BODY_N,418nymous_ ++B 26000,21600,300,300,CONT_VIA2,472nymous_ ++B 10400,6000,300,300,CONT_VIA2,1118ymous_ ++B 8000,9000,300,300,CONT_DIF_N,1064ymous_ ++B 30800,6000,300,300,CONT_BODY_P,636nymous_ ++B 26000,24000,300,300,CONT_DIF_P,475nymous_ ++B 27000,19200,300,300,CONT_BODY_N,529nymous_ ++B 10400,10000,300,300,CONT_POLY,1121ymous_ ++B 29000,22200,300,300,CONT_VIA,582nymous_ ++B 20800,22400,300,300,CONT_BODY_P,367nymous_ ++B 23600,6000,300,300,CONT_BODY_P,421nymous_ ++B 18800,31600,300,300,CONT_DIF_N,1335ymous_ ++B 8000,11000,300,300,CONT_VIA,1067ymous_ ++B 6800,16000,300,300,CONT_BODY_N,1013ymous_ ++B 15600,24000,300,300,CONT_DIF_N,1227ymous_ ++B 16800,29200,300,300,CONT_VIA,1281ymous_ ++B 5400,30000,300,300,CONT_VIA2,959nymous_ ++B 4400,23000,300,300,CONT_DIF_N,905nymous_ ++B 37000,27000,300,300,CONT_VIA,851nymous_ ++B 35600,6000,300,300,CONT_BODY_P,797nymous_ ++B 33800,32000,300,300,CONT_VIA,743nymous_ ++B 32200,28000,300,300,CONT_DIF_P,689nymous_ ++B 30600,35000,300,300,CONT_VIA2,635nymous_ ++B 26000,22800,300,300,CONT_VIA2,474nymous_ ++B 27000,11000,300,300,CONT_VIA2,528nymous_ ++B 12800,6000,300,300,CONT_BODY_P,1174ymous_ ++B 10400,9000,300,300,CONT_DIF_N,1120ymous_ ++B 29000,22200,300,300,CONT_POLY,581nymous_ ++B 20800,21400,300,300,CONT_BODY_P,366nymous_ ++B 23400,17000,300,300,CONT_VIA2,420nymous_ ++B 16800,28200,300,300,CONT_POLY,1280ymous_ ++B 18800,30400,300,300,CONT_DIF_N,1334ymous_ ++B 8000,10000,300,300,CONT_POLY,1066ymous_ ++B 6800,14800,300,300,CONT_DIF_P,1012ymous_ ++B 15600,23000,300,300,CONT_DIF_N,1226ymous_ ++B 5400,26000,300,300,CONT_VIA2,958nymous_ ++B 23600,6000,300,300,CONT_VIA2,423nymous_ ++B 8000,12800,300,300,CONT_DIF_P,1069ymous_ ++B 20800,24400,300,300,CONT_BODY_P,369nymous_ ++B 16800,32200,300,300,CONT_VIA,1283ymous_ ++B 18800,32800,300,300,CONT_DIF_N,1337ymous_ ++B 6800,17000,300,300,CONT_VIA2,1015ymous_ ++B 5400,32000,300,300,CONT_VIA2,961nymous_ ++B 15600,26000,300,300,CONT_DIF_N,1229ymous_ ++B 4400,24000,300,300,CONT_DIF_N,907nymous_ ++B 37000,28000,300,300,CONT_DIF_P,853nymous_ ++B 35600,6000,300,300,CONT_VIA2,799nymous_ ++B 33800,33000,300,300,CONT_VIA,745nymous_ ++B 32200,30000,300,300,CONT_DIF_P,691nymous_ ++B 27200,6000,300,300,CONT_BODY_P,530nymous_ ++B 12800,6000,300,300,CONT_VIA2,1176ymous_ ++B 30800,8000,300,300,CONT_DIF_N,637nymous_ ++B 29000,23400,300,300,CONT_POLY,583nymous_ ++B 23600,6000,300,300,CONT_VIA,422nymous_ ++B 26000,24000,300,300,CONT_VIA,476nymous_ ++B 18800,31600,300,300,CONT_VIA,1336ymous_ ++B 10400,11800,300,300,CONT_DIF_P,1122ymous_ ++B 8000,11800,300,300,CONT_DIF_P,1068ymous_ ++B 20800,23400,300,300,CONT_BODY_P,368nymous_ ++B 15600,25000,300,300,CONT_DIF_N,1228ymous_ ++B 16800,32200,300,300,CONT_POLY,1282ymous_ ++B 6800,17000,300,300,CONT_VIA,1014ymous_ ++B 5400,31000,300,300,CONT_VIA2,960nymous_ ++B 4400,23000,300,300,CONT_VIA,906nymous_ ++B 37000,27000,300,300,CONT_VIA2,852nymous_ ++B 35600,6000,300,300,CONT_VIA,798nymous_ ++B 33800,33000,300,300,CONT_DIF_P,744nymous_ ++B 32200,29000,300,300,CONT_DIF_P,690nymous_ ++B 5600,37600,300,300,CONT_BODY_P,963nymous_ ++B 4400,24000,300,300,CONT_VIA2,909nymous_ ++B 37000,28000,300,300,CONT_VIA2,855nymous_ ++B 35600,13000,300,300,CONT_DIF_P,801nymous_ ++B 33800,34000,300,300,CONT_DIF_P,747nymous_ ++B 32200,32000,300,300,CONT_DIF_P,693nymous_ ++B 30800,13000,300,300,CONT_DIF_P,639nymous_ ++B 26000,26400,300,300,CONT_DIF_P,478nymous_ ++B 27200,10600,300,300,CONT_POLY,532nymous_ ++B 12800,9000,300,300,CONT_DIF_N,1178ymous_ ++B 10400,13800,300,300,CONT_DIF_P,1124ymous_ ++B 29000,24600,300,300,CONT_POLY,585nymous_ ++B 20800,25400,300,300,CONT_BODY_P,370nymous_ ++B 23600,8000,300,300,CONT_DIF_N,424nymous_ ++B 16800,33400,300,300,CONT_POLY,1284ymous_ ++B 18800,34000,300,300,CONT_DIF_N,1338ymous_ ++B 8000,13800,300,300,CONT_DIF_P,1070ymous_ ++B 7000,9000,300,300,CONT_VIA2,1016ymous_ ++B 15600,27000,300,300,CONT_DIF_N,1230ymous_ ++B 5400,36000,300,300,CONT_VIA2,962nymous_ ++B 4400,24000,300,300,CONT_VIA,908nymous_ ++B 37000,28000,300,300,CONT_VIA,854nymous_ ++B 35600,8000,300,300,CONT_DIF_N,800nymous_ ++B 32200,31000,300,300,CONT_DIF_P,692nymous_ ++B 27200,8000,300,300,CONT_DIF_N,531nymous_ ++B 12800,8000,300,300,CONT_DIF_N,1177ymous_ ++B 33800,33000,300,300,CONT_VIA2,746nymous_ ++B 30800,10600,300,300,CONT_POLY,638nymous_ ++B 29000,23400,300,300,CONT_VIA,584nymous_ ++B 26000,25200,300,300,CONT_DIF_P,477nymous_ ++B 10400,12800,300,300,CONT_DIF_P,1123ymous_ ++B 7000,10000,300,300,CONT_VIA2,1017ymous_ ++B 16800,33400,300,300,CONT_VIA,1285ymous_ ++B 15600,28000,300,300,CONT_DIF_N,1231ymous_ ++B 8000,16000,300,300,CONT_BODY_N,1071ymous_ ++B 18800,34000,300,300,CONT_VIA,1339ymous_ ++B 23600,13000,300,300,CONT_DIF_P,425nymous_ ++B 20800,26400,300,300,CONT_BODY_P,371nymous_ ++B 29000,24600,300,300,CONT_VIA,586nymous_ ++B 10400,16000,300,300,CONT_BODY_N,1125ymous_ ++B 12800,11600,300,300,CONT_DIF_P,1179ymous_ ++B 27200,13000,300,300,CONT_DIF_P,533nymous_ ++B 26000,26400,300,300,CONT_VIA,479nymous_ ++B 30800,14000,300,300,CONT_DIF_P,640nymous_ ++B 32200,33000,300,300,CONT_DIF_P,694nymous_ ++B 33800,34000,300,300,CONT_VIA,748nymous_ ++B 35600,14000,300,300,CONT_DIF_P,802nymous_ ++B 37000,29000,300,300,CONT_DIF_P,856nymous_ ++B 4400,25000,300,300,CONT_DIF_N,910nymous_ ++B 5600,37600,300,300,CONT_VIA,964nymous_ ++B 7000,11000,300,300,CONT_VIA2,1018ymous_ ++B 16800,33400,300,300,CONT_VIA2,1286ymous_ ++B 15600,29000,300,300,CONT_DIF_N,1232ymous_ ++B 20800,27400,300,300,CONT_BODY_P,372nymous_ ++B 8000,17000,300,300,CONT_VIA,1072ymous_ ++B 10400,17000,300,300,CONT_VIA,1126ymous_ ++B 18800,35200,300,300,CONT_DIF_N,1340ymous_ ++B 26000,27600,300,300,CONT_DIF_P,480nymous_ ++B 23600,14000,300,300,CONT_DIF_P,426nymous_ ++B 29000,25800,300,300,CONT_POLY,587nymous_ ++B 30800,16000,300,300,CONT_BODY_N,641nymous_ ++B 27200,14000,300,300,CONT_DIF_P,534nymous_ ++B 32200,34000,300,300,CONT_DIF_P,695nymous_ ++B 33800,34000,300,300,CONT_VIA2,749nymous_ ++B 35600,16000,300,300,CONT_BODY_N,803nymous_ ++B 37000,29000,300,300,CONT_VIA,857nymous_ ++B 4400,25000,300,300,CONT_VIA,911nymous_ ++B 15600,30000,300,300,CONT_DIF_N,1233ymous_ ++B 5600,37600,300,300,CONT_VIA2,965nymous_ ++B 7600,21800,300,300,CONT_POLY,1019ymous_ ++B 18800,36400,300,300,CONT_DIF_N,1341ymous_ ++B 16800,34600,300,300,CONT_POLY,1287ymous_ ++B 20800,28400,300,300,CONT_BODY_P,373nymous_ ++B 8000,17000,300,300,CONT_VIA2,1073ymous_ ++B 10400,17000,300,300,CONT_VIA2,1127ymous_ ++B 26000,27600,300,300,CONT_VIA2,481nymous_ ++B 23600,16000,300,300,CONT_BODY_N,427nymous_ ++B 29000,30600,300,300,CONT_POLY,588nymous_ ++B 30800,17000,300,300,CONT_VIA,642nymous_ ++B 33800,35000,300,300,CONT_DIF_P,750nymous_ ++B 27200,16000,300,300,CONT_BODY_N,535nymous_ ++B 32200,35000,300,300,CONT_DIF_P,696nymous_ ++B 35600,17000,300,300,CONT_VIA,804nymous_ ++B 37000,29000,300,300,CONT_VIA2,858nymous_ ++B 4400,25000,300,300,CONT_VIA2,912nymous_ ++B 5600,6000,300,300,CONT_BODY_P,966nymous_ ++B 15600,31000,300,300,CONT_DIF_N,1234ymous_ ++B 7600,21800,300,300,CONT_VIA,1020ymous_ ++B 8600,24000,300,300,CONT_VIA2,1074ymous_ ++B 18800,36400,300,300,CONT_VIA,1342ymous_ ++B 16800,34600,300,300,CONT_VIA,1288ymous_ ++B 24000,27000,300,300,CONT_POLY,428nymous_ ++B 20800,29400,300,300,CONT_BODY_P,374nymous_ ++B 29000,31800,300,300,CONT_POLY,589nymous_ ++B 10600,19200,300,300,CONT_BODY_P,1128ymous_ ++B 27200,17000,300,300,CONT_VIA,536nymous_ ++B 26000,28800,300,300,CONT_DIF_P,482nymous_ ++B 30800,17000,300,300,CONT_VIA2,643nymous_ ++B 32200,36000,300,300,CONT_DIF_P,697nymous_ ++B 33800,35000,300,300,CONT_VIA,751nymous_ ++B 35600,17000,300,300,CONT_VIA2,805nymous_ ++B 37000,30000,300,300,CONT_DIF_P,859nymous_ ++B 4400,26000,300,300,CONT_DIF_N,913nymous_ ++B 5600,6000,300,300,CONT_VIA,967nymous_ ++B 16800,34600,300,300,CONT_VIA2,1289ymous_ ++B 15600,32000,300,300,CONT_DIF_N,1235ymous_ ++B 7600,23000,300,300,CONT_DIF_N,1021ymous_ ++B 8600,25000,300,300,CONT_VIA2,1075ymous_ ++B 18800,37600,300,300,CONT_BODY_P,1343ymous_ ++B 24000,28200,300,300,CONT_POLY,429nymous_ ++B 20800,30400,300,300,CONT_BODY_P,375nymous_ ++B 29000,33000,300,300,CONT_POLY,590nymous_ ++B 10800,21800,300,300,CONT_POLY,1129ymous_ ++B 27200,17000,300,300,CONT_VIA2,537nymous_ ++B 26000,28800,300,300,CONT_VIA,483nymous_ ++B 31000,19200,300,300,CONT_BODY_N,644nymous_ ++B 32800,20200,300,300,CONT_POLY,698nymous_ ++B 33800,35000,300,300,CONT_VIA2,752nymous_ ++B 36000,20200,300,300,CONT_POLY,806nymous_ ++B 37000,30000,300,300,CONT_VIA,860nymous_ ++B 4400,26000,300,300,CONT_VIA,914nymous_ ++B 5600,6000,300,300,CONT_VIA2,968nymous_ ++B 7600,23000,300,300,CONT_VIA,1022ymous_ ++B 16800,35800,300,300,CONT_POLY,1290ymous_ ++B 15600,33000,300,300,CONT_DIF_N,1236ymous_ ++B 20800,31400,300,300,CONT_BODY_P,376nymous_ ++B 18800,6000,300,300,CONT_BODY_P,1344ymous_ ++B 12800,17000,300,300,CONT_VIA,1182ymous_ ++B 8600,26000,300,300,CONT_VIA2,1076ymous_ ++B 10800,21800,300,300,CONT_VIA,1130ymous_ ++B 26000,28800,300,300,CONT_VIA2,484nymous_ ++B 24000,28200,300,300,CONT_VIA,430nymous_ ++B 29000,19200,300,300,CONT_BODY_N,591nymous_ ++B 31600,20200,300,300,CONT_POLY,645nymous_ ++B 27800,36400,300,300,CONT_DIF_P,538nymous_ ++B 32800,22000,300,300,CONT_VIA2,699nymous_ ++B 33800,36000,300,300,CONT_DIF_P,753nymous_ ++B 36000,22000,300,300,CONT_VIA2,807nymous_ ++B 37000,31000,300,300,CONT_DIF_P,861nymous_ ++B 4400,26000,300,300,CONT_VIA2,915nymous_ ++B 15600,34000,300,300,CONT_DIF_N,1237ymous_ ++B 5600,8000,300,300,CONT_DIF_N,969nymous_ ++B 7600,24000,300,300,CONT_DIF_N,1023ymous_ ++B 18800,6000,300,300,CONT_VIA,1345ymous_ ++B 16800,35800,300,300,CONT_VIA,1291ymous_ ++B 20800,32400,300,300,CONT_BODY_P,377nymous_ ++B 8600,30000,300,300,CONT_VIA2,1077ymous_ ++B 10800,21800,300,300,CONT_VIA2,1131ymous_ ++B 26000,30000,300,300,CONT_DIF_P,485nymous_ ++B 24000,29200,300,300,CONT_POLY,431nymous_ ++B 29600,33000,300,300,CONT_VIA2,592nymous_ ++B 31600,22000,300,300,CONT_VIA2,646nymous_ ++B 33800,36000,300,300,CONT_VIA,754nymous_ ++B 27800,37600,300,300,CONT_BODY_N,539nymous_ ++B 32800,23000,300,300,CONT_VIA2,700nymous_ ++B 36000,23000,300,300,CONT_VIA2,808nymous_ ++B 37000,31000,300,300,CONT_VIA,862nymous_ ++B 4400,27000,300,300,CONT_DIF_N,916nymous_ ++B 13600,19200,300,300,CONT_BODY_P,1184ymous_ ++B 12800,17000,300,300,CONT_VIA2,1183ymous_ ++B 12800,12600,300,300,CONT_DIF_P,1180ymous_ ++B 5600,9000,300,300,CONT_DIF_N,970nymous_ ++B 15600,35000,300,300,CONT_DIF_N,1238ymous_ ++B 7600,24000,300,300,CONT_VIA,1024ymous_ ++B 8600,31000,300,300,CONT_VIA2,1078ymous_ ++B 18800,6000,300,300,CONT_VIA2,1346ymous_ ++B 16800,37600,300,300,CONT_BODY_P,1292ymous_ ++B 24000,34200,300,300,CONT_POLY,432nymous_ ++B 20800,33400,300,300,CONT_BODY_P,378nymous_ ++B 29600,34000,300,300,CONT_VIA2,593nymous_ ++B 10800,23000,300,300,CONT_DIF_N,1132ymous_ ++B 26000,31200,300,300,CONT_DIF_P,486nymous_ ++B 31600,23000,300,300,CONT_VIA2,647nymous_ ++B 32800,27000,300,300,CONT_VIA2,701nymous_ ++B 34000,19200,300,300,CONT_BODY_N,755nymous_ ++B 36000,27000,300,300,CONT_VIA2,809nymous_ ++B 37000,32000,300,300,CONT_DIF_P,863nymous_ ++B 14000,21800,300,300,CONT_POLY,1185ymous_ ++B 4400,27000,300,300,CONT_VIA,917nymous_ ++B 5600,11800,300,300,CONT_DIF_P,971nymous_ ++B 17400,11800,300,300,CONT_POLY,1293ymous_ ++B 15600,36000,300,300,CONT_DIF_N,1239ymous_ ++B 7600,24000,300,300,CONT_VIA2,1025ymous_ ++B 8600,32000,300,300,CONT_VIA2,1079ymous_ ++B 18800,9000,300,300,CONT_DIF_N,1347ymous_ ++B 24000,34200,300,300,CONT_VIA,433nymous_ ++B 20800,34400,300,300,CONT_BODY_P,379nymous_ ++B 29600,35000,300,300,CONT_VIA2,594nymous_ ++B 10800,24000,300,300,CONT_DIF_N,1133ymous_ ++B 12800,16000,300,300,CONT_BODY_N,1181ymous_ ++B 26000,31200,300,300,CONT_VIA,487nymous_ ++B 31600,27000,300,300,CONT_VIA2,648nymous_ ++B 32800,28000,300,300,CONT_VIA2,702nymous_ ++B 3400,24000,300,300,CONT_VIA2,756nymous_ ++B 36000,28000,300,300,CONT_VIA2,810nymous_ ++B 37000,32000,300,300,CONT_VIA,864nymous_ ++B 4400,28000,300,300,CONT_DIF_N,918nymous_ ++B 14000,21800,300,300,CONT_VIA,1186ymous_ ++B 5600,12800,300,300,CONT_DIF_P,972nymous_ ++B 7600,25000,300,300,CONT_DIF_N,1026ymous_ ++B 17600,6000,300,300,CONT_BODY_P,1294ymous_ ++B 15600,19200,300,300,CONT_BODY_P,1240ymous_ ++B 20800,35400,300,300,CONT_BODY_P,380nymous_ ++B 8600,36000,300,300,CONT_VIA2,1080ymous_ ++B 10800,25000,300,300,CONT_DIF_N,1134ymous_ ++B 18800,16000,300,300,CONT_BODY_N,1348ymous_ ++B 26000,32400,300,300,CONT_DIF_P,488nymous_ ++B 24000,34200,300,300,CONT_VIA2,434nymous_ ++B 29600,7000,300,300,CONT_DIF_N,595nymous_ ++B 31600,28000,300,300,CONT_VIA2,649nymous_ ++B 32800,29000,300,300,CONT_VIA2,703nymous_ ++B 3400,25000,300,300,CONT_VIA2,757nymous_ ++B 36000,29000,300,300,CONT_VIA2,811nymous_ ++B 37000,33000,300,300,CONT_DIF_P,865nymous_ ++B 4400,28000,300,300,CONT_VIA,919nymous_ ++B 15800,27000,300,300,CONT_VIA2,1241ymous_ ++B 14000,21800,300,300,CONT_VIA2,1187ymous_ ++B 5600,13800,300,300,CONT_DIF_P,973nymous_ ++B 7600,25000,300,300,CONT_VIA,1027ymous_ ++B 18800,17000,300,300,CONT_VIA,1349ymous_ ++B 17600,6000,300,300,CONT_VIA,1295ymous_ ++B 20800,36400,300,300,CONT_BODY_P,381nymous_ ++B 8600,19200,300,300,CONT_BODY_P,1081ymous_ ++B 24000,35800,300,300,CONT_POLY,435nymous_ ++B 10800,26000,300,300,CONT_DIF_N,1135ymous_ ++B 26000,33600,300,300,CONT_DIF_P,489nymous_ ++B 29600,10600,300,300,CONT_POLY,596nymous_ ++B 31600,29000,300,300,CONT_VIA2,650nymous_ ++B 3400,26000,300,300,CONT_VIA2,758nymous_ ++B 32800,33000,300,300,CONT_VIA2,704nymous_ ++B 36000,33000,300,300,CONT_VIA2,812nymous_ ++B 37000,33000,300,300,CONT_VIA,866nymous_ ++B 4400,29000,300,300,CONT_DIF_N,920nymous_ ++B 5600,16000,300,300,CONT_BODY_N,974nymous_ ++B 15800,28000,300,300,CONT_VIA2,1242ymous_ ++B 14000,23000,300,300,CONT_DIF_N,1188ymous_ ++B 7600,25000,300,300,CONT_VIA2,1028ymous_ ++B 8800,37600,300,300,CONT_BODY_P,1082ymous_ ++B 18800,17000,300,300,CONT_VIA2,1350ymous_ ++B 17600,6000,300,300,CONT_VIA2,1296ymous_ ++B 24000,35800,300,300,CONT_VIA,436nymous_ ++B 20800,37600,300,300,CONT_BODY_P,382nymous_ ++B 28000,24000,300,300,CONT_DIF_P,543nymous_ ++B 29600,13000,300,300,CONT_DIF_P,597nymous_ ++B 10800,27000,300,300,CONT_DIF_N,1136ymous_ ++B 26000,33600,300,300,CONT_VIA,490nymous_ ++B 31600,33000,300,300,CONT_VIA2,651nymous_ ++B 32800,34000,300,300,CONT_VIA2,705nymous_ ++B 3400,30000,300,300,CONT_VIA2,759nymous_ ++B 36000,34000,300,300,CONT_VIA2,813nymous_ ++B 37000,33000,300,300,CONT_VIA2,867nymous_ ++B 14000,24000,300,300,CONT_DIF_N,1189ymous_ ++B 4400,29000,300,300,CONT_VIA,921nymous_ ++B 5600,17000,300,300,CONT_VIA,975nymous_ ++B 7600,26000,300,300,CONT_DIF_N,1029ymous_ ++B 28000,22800,300,300,CONT_DIF_P,542nymous_ ++B 17600,8600,300,300,CONT_DIF_N,1297ymous_ ++B 15800,29000,300,300,CONT_VIA2,1243ymous_ ++B 8800,37600,300,300,CONT_VIA,1083ymous_ ++B 19600,19200,300,300,CONT_BODY_P,1351ymous_ ++B 24000,37600,300,300,CONT_BODY_N,437nymous_ ++B 20800,19200,300,300,CONT_BODY_P,383nymous_ ++B 28000,25200,300,300,CONT_DIF_P,544nymous_ ++B 29600,14000,300,300,CONT_DIF_P,598nymous_ ++B 10800,28000,300,300,CONT_DIF_N,1137ymous_ ++B 26000,35000,300,300,CONT_DIF_P,491nymous_ ++B 31600,34000,300,300,CONT_VIA2,652nymous_ ++B 32800,35000,300,300,CONT_VIA2,706nymous_ ++B 3400,31000,300,300,CONT_VIA2,760nymous_ ++B 36000,35000,300,300,CONT_VIA2,814nymous_ ++B 37000,34000,300,300,CONT_DIF_P,868nymous_ ++B 4400,30000,300,300,CONT_DIF_N,922nymous_ ++B 14000,25000,300,300,CONT_DIF_N,1190ymous_ ++B 5600,17000,300,300,CONT_VIA2,976nymous_ ++B 7600,26000,300,300,CONT_VIA,1030ymous_ ++B 17600,12800,300,300,CONT_DIF_P,1298ymous_ ++B 15800,37600,300,300,CONT_BODY_P,1244ymous_ ++B 21000,13000,300,300,CONT_VIA,384nymous_ ++B 28000,26400,300,300,CONT_DIF_P,545nymous_ ++B 8800,37600,300,300,CONT_VIA2,1084ymous_ ++B 10800,29000,300,300,CONT_DIF_N,1138ymous_ ++B 19800,22600,300,300,CONT_POLY,1352ymous_ ++B 26000,36400,300,300,CONT_DIF_P,492nymous_ ++B 24000,19200,300,300,CONT_BODY_N,438nymous_ ++B 29600,16000,300,300,CONT_BODY_N,599nymous_ ++B 31600,35000,300,300,CONT_VIA2,653nymous_ ++B 33000,19200,300,300,CONT_BODY_N,707nymous_ ++B 3400,32000,300,300,CONT_VIA2,761nymous_ ++B 36000,19200,300,300,CONT_BODY_N,815nymous_ ++B 37000,34000,300,300,CONT_VIA,869nymous_ ++B 4400,30000,300,300,CONT_VIA,923nymous_ ++B 1600,20400,300,300,CONT_BODY_P,1245ymous_ ++B 14000,26000,300,300,CONT_DIF_N,1191ymous_ ++B 5600,19200,300,300,CONT_BODY_P,977nymous_ ++B 7600,26000,300,300,CONT_VIA2,1031ymous_ ++B 19800,26200,300,300,CONT_POLY,1353ymous_ ++B 17600,16000,300,300,CONT_BODY_N,1299ymous_ ++B 21000,14000,300,300,CONT_VIA,385nymous_ ++B 28000,27600,300,300,CONT_DIF_P,546nymous_ ++B 9200,23000,300,300,CONT_DIF_N,1085ymous_ ++B 10800,30000,300,300,CONT_DIF_N,1139ymous_ ++B 26000,37600,300,300,CONT_BODY_N,493nymous_ ++B 24800,6000,300,300,CONT_BODY_P,439nymous_ ++B 29600,17000,300,300,CONT_VIA,600nymous_ ++B 31800,9000,300,300,CONT_POLY,654nymous_ ++B 3400,36000,300,300,CONT_VIA2,762nymous_ ++B 33200,6000,300,300,CONT_BODY_P,708nymous_ ++B 3600,37600,300,300,CONT_BODY_P,816nymous_ ++B 37000,34000,300,300,CONT_VIA2,870nymous_ ++B 4400,30000,300,300,CONT_VIA2,924nymous_ ++B 6000,23000,300,300,CONT_DIF_N,978nymous_ ++B 1600,21400,300,300,CONT_BODY_P,1246ymous_ ++B 14000,27000,300,300,CONT_DIF_N,1192ymous_ ++B 7600,27000,300,300,CONT_DIF_N,1032ymous_ ++B 9200,24000,300,300,CONT_DIF_N,1086ymous_ ++B 19800,27400,300,300,CONT_POLY,1354ymous_ ++B 17600,17000,300,300,CONT_VIA,1300ymous_ ++B 24800,6000,300,300,CONT_VIA,440nymous_ ++B 21200,6000,300,300,CONT_BODY_P,386nymous_ ++B 28000,28800,300,300,CONT_DIF_P,547nymous_ ++B 29600,17000,300,300,CONT_VIA2,601nymous_ ++B 10800,31000,300,300,CONT_DIF_N,1140ymous_ ++B 26000,6000,300,300,CONT_BODY_P,494nymous_ ++B 31800,12200,300,300,CONT_POLY,655nymous_ ++B 33200,6000,300,300,CONT_VIA,709nymous_ ++B 34400,6000,300,300,CONT_BODY_P,763nymous_ ++B 3600,37600,300,300,CONT_VIA,817nymous_ ++B 37000,35000,300,300,CONT_DIF_P,871nymous_ ++B 14000,28000,300,300,CONT_DIF_N,1193ymous_ ++B 4400,31000,300,300,CONT_DIF_N,925nymous_ ++B 6000,24000,300,300,CONT_DIF_N,979nymous_ ++B 17600,17000,300,300,CONT_VIA2,1301ymous_ ++B 1600,22400,300,300,CONT_BODY_P,1247ymous_ ++B 7600,27000,300,300,CONT_VIA,1033ymous_ ++B 9200,25000,300,300,CONT_DIF_N,1087ymous_ ++B 19800,28200,300,300,CONT_VIA,1355ymous_ ++B 24800,6000,300,300,CONT_VIA2,441nymous_ ++B 21200,6000,300,300,CONT_VIA,387nymous_ ++B 28000,30000,300,300,CONT_DIF_P,548nymous_ ++B 30000,20200,300,300,CONT_VIA,602nymous_ ++B 10800,32000,300,300,CONT_DIF_N,1141ymous_ ++B 26000,6000,300,300,CONT_VIA,495nymous_ ++B 32000,6000,300,300,CONT_BODY_P,656nymous_ ++B 33200,6000,300,300,CONT_VIA2,710nymous_ ++B 34400,6000,300,300,CONT_VIA,764nymous_ ++B 3600,37600,300,300,CONT_VIA2,818nymous_ ++B 37000,35000,300,300,CONT_VIA,872nymous_ ++B 4400,31000,300,300,CONT_VIA,926nymous_ ++B 14000,29000,300,300,CONT_DIF_N,1194ymous_ ++B 6000,25000,300,300,CONT_DIF_N,980nymous_ ++B 7600,28000,300,300,CONT_DIF_N,1034ymous_ ++B 1600,23400,300,300,CONT_BODY_P,1248ymous_ ++B 17600,19200,300,300,CONT_BODY_P,1302ymous_ ++B 21200,6000,300,300,CONT_VIA2,388nymous_ ++B 28000,31200,300,300,CONT_DIF_P,549nymous_ ++B 9200,26000,300,300,CONT_DIF_N,1088ymous_ ++B 10800,33000,300,300,CONT_DIF_N,1142ymous_ ++B 19800,31000,300,300,CONT_POLY,1356ymous_ ++B 26000,6000,300,300,CONT_VIA2,496nymous_ ++B 24800,8000,300,300,CONT_DIF_N,442nymous_ ++B 30000,19200,300,300,CONT_BODY_N,603nymous_ ++B 32000,6000,300,300,CONT_VIA,657nymous_ ++B 33200,8000,300,300,CONT_DIF_N,711nymous_ ++B 34400,6000,300,300,CONT_VIA2,765nymous_ ++B 3600,19200,300,300,CONT_BODY_P,819nymous_ ++B 37000,35000,300,300,CONT_VIA2,873nymous_ ++B 4400,31000,300,300,CONT_VIA2,927nymous_ ++B 1600,24400,300,300,CONT_BODY_P,1249ymous_ ++B 14000,30000,300,300,CONT_DIF_N,1195ymous_ ++B 6000,26000,300,300,CONT_DIF_N,981nymous_ ++B 7600,28000,300,300,CONT_VIA,1035ymous_ ++B 19800,35200,300,300,CONT_VIA,1357ymous_ ++B 17800,23200,300,300,CONT_DIF_N,1303ymous_ ++B 21200,9000,300,300,CONT_DIF_N,389nymous_ ++B 28000,31200,300,300,CONT_VIA,550nymous_ ++B 9200,27000,300,300,CONT_DIF_N,1089ymous_ ++B 10800,34000,300,300,CONT_DIF_N,1143ymous_ ++B 26000,8000,300,300,CONT_DIF_N,497nymous_ ++B 24800,13000,300,300,CONT_DIF_P,443nymous_ ++B 30400,36600,300,300,CONT_POLY,604nymous_ ++B 32000,6000,300,300,CONT_VIA2,658nymous_ ++B 34400,8000,300,300,CONT_DIF_N,766nymous_ ++B 33200,13000,300,300,CONT_DIF_P,712nymous_ ++B 36800,6000,300,300,CONT_BODY_P,820nymous_ ++B 37000,36000,300,300,CONT_DIF_P,874nymous_ ++B 4400,32000,300,300,CONT_DIF_N,928nymous_ ++B 6000,27000,300,300,CONT_DIF_N,982nymous_ ++B 1600,25400,300,300,CONT_BODY_P,1250ymous_ ++B 14000,31000,300,300,CONT_DIF_N,1196ymous_ ++B 7600,29000,300,300,CONT_DIF_N,1036ymous_ ++B 9200,28000,300,300,CONT_DIF_N,1090ymous_ ++B 19800,37600,300,300,CONT_BODY_P,1358ymous_ ++B 17800,23200,300,300,CONT_VIA,1304ymous_ ++B 24800,13000,300,300,CONT_VIA,444nymous_ ++B 21200,16000,300,300,CONT_BODY_N,390nymous_ ++B 28000,32400,300,300,CONT_DIF_P,551nymous_ ++B 30400,36600,300,300,CONT_VIA,605nymous_ ++B 10800,35000,300,300,CONT_DIF_N,1144ymous_ ++B 26000,12000,300,300,CONT_VIA2,498nymous_ ++B 32000,8000,300,300,CONT_DIF_N,659nymous_ ++B 33200,14000,300,300,CONT_DIF_P,713nymous_ ++B 34400,13000,300,300,CONT_DIF_P,767nymous_ ++B 36800,6000,300,300,CONT_VIA,821nymous_ ++B 37000,36000,300,300,CONT_VIA,875nymous_ ++B 14000,32000,300,300,CONT_DIF_N,1197ymous_ ++B 4400,32000,300,300,CONT_VIA,929nymous_ ++B 6000,28000,300,300,CONT_DIF_N,983nymous_ ++B 17800,24400,300,300,CONT_DIF_N,1305ymous_ ++B 1600,26400,300,300,CONT_BODY_P,1251ymous_ ++B 7600,29000,300,300,CONT_VIA,1037ymous_ ++B 9200,29000,300,300,CONT_DIF_N,1091ymous_ ++B 22000,22200,300,300,CONT_VIA,391nymous_ ++B 28000,33600,300,300,CONT_DIF_P,552nymous_ ++B 10800,36000,300,300,CONT_DIF_N,1145ymous_ ++B 26000,13000,300,300,CONT_DIF_P,499nymous_ ++B 24800,14000,300,300,CONT_DIF_P,445nymous_ ++B 30400,36600,300,300,CONT_VIA2,606nymous_ ++B 32000,13000,300,300,CONT_DIF_P,660nymous_ ++B 33200,16000,300,300,CONT_BODY_N,714nymous_ ++B 34400,13000,300,300,CONT_VIA,768nymous_ ++B 36800,6000,300,300,CONT_VIA2,822nymous_ ++B 37000,19200,300,300,CONT_BODY_N,876nymous_ ++B 4400,32000,300,300,CONT_VIA2,930nymous_ ++B 14000,33000,300,300,CONT_DIF_N,1198ymous_ ++B 6000,29000,300,300,CONT_DIF_N,984nymous_ ++B 7600,30000,300,300,CONT_DIF_N,1038ymous_ ++B 17800,24400,300,300,CONT_VIA2,1306ymous_ ++B 1600,27400,300,300,CONT_BODY_P,1252ymous_ ++B 22000,19200,300,300,CONT_VIA,392nymous_ ++B 28000,35000,300,300,CONT_DIF_P,553nymous_ ++B 9200,30000,300,300,CONT_DIF_N,1092ymous_ ++B 11600,6000,300,300,CONT_BODY_P,1146ymous_ ++B 26000,13000,300,300,CONT_VIA2,500nymous_ ++B 24800,14000,300,300,CONT_VIA,446nymous_ ++B 30600,22000,300,300,CONT_DIF_P,607nymous_ ++B 32000,16000,300,300,CONT_BODY_N,661nymous_ ++B 33200,17000,300,300,CONT_VIA,715nymous_ ++B 34400,14000,300,300,CONT_DIF_P,769nymous_ ++B 36800,7000,300,300,CONT_BODY_P,823nymous_ ++B 37200,37600,300,300,CONT_BODY_N,877nymous_ ++B 4400,33000,300,300,CONT_DIF_N,931nymous_ ++B 1600,28400,300,300,CONT_BODY_P,1253ymous_ ++B 14000,34000,300,300,CONT_DIF_N,1199ymous_ ++B 6000,30000,300,300,CONT_DIF_N,985nymous_ ++B 7600,30000,300,300,CONT_VIA,1039ymous_ ++B 9200,31000,300,300,CONT_DIF_N,1093ymous_ ++B 17800,25600,300,300,CONT_DIF_N,1307ymous_ ++B 22400,6000,300,300,CONT_BODY_P,393nymous_ ++B 28000,19200,300,300,CONT_BODY_N,554nymous_ ++B 11600,6000,300,300,CONT_VIA,1147ymous_ ++B 26000,14000,300,300,CONT_DIF_P,501nymous_ ++B 24800,16000,300,300,CONT_BODY_N,447nymous_ ++B 30600,23000,300,300,CONT_DIF_P,608nymous_ ++B 32000,17000,300,300,CONT_VIA,662nymous_ ++B 34400,14000,300,300,CONT_VIA,770nymous_ ++B 33200,17000,300,300,CONT_VIA2,716nymous_ ++B 36800,8000,300,300,CONT_BODY_P,824nymous_ ++B 38000,27000,300,300,CONT_VIA2,878nymous_ ++B 4400,33000,300,300,CONT_VIA,932nymous_ ++B 6000,31000,300,300,CONT_DIF_N,986nymous_ ++B 1600,29400,300,300,CONT_BODY_P,1254ymous_ ++B 14000,35000,300,300,CONT_DIF_N,1200ymous_ ++B 7600,30000,300,300,CONT_VIA2,1040ymous_ ++B 9200,32000,300,300,CONT_DIF_N,1094ymous_ ++B 17800,25600,300,300,CONT_VIA,1308ymous_ ++B 25000,20400,300,300,CONT_DIF_P,448nymous_ ++B 22400,6000,300,300,CONT_VIA,394nymous_ ++B 2800,23000,300,300,CONT_DIF_N,555nymous_ ++B 30600,24000,300,300,CONT_DIF_P,609nymous_ ++B 11600,6000,300,300,CONT_VIA2,1148ymous_ ++B 26000,14000,300,300,CONT_VIA2,502nymous_ ++B 32000,17000,300,300,CONT_VIA2,663nymous_ ++B 33800,22000,300,300,CONT_DIF_P,717nymous_ ++B 34400,16000,300,300,CONT_BODY_N,771nymous_ ++B 36800,9000,300,300,CONT_BODY_P,825nymous_ ++B 38000,28000,300,300,CONT_VIA2,879nymous_ ++B 14000,36000,300,300,CONT_DIF_N,1201ymous_ ++B 4400,34000,300,300,CONT_DIF_N,933nymous_ ++B 6000,32000,300,300,CONT_DIF_N,987nymous_ ++B 17800,25600,300,300,CONT_VIA2,1309ymous_ ++B 1600,30400,300,300,CONT_BODY_P,1255ymous_ ++B 7600,31000,300,300,CONT_DIF_N,1041ymous_ ++B 9200,33000,300,300,CONT_DIF_N,1095ymous_ ++B 25000,20400,300,300,CONT_VIA,449nymous_ ++B 22400,6000,300,300,CONT_VIA2,395nymous_ ++B 2800,24000,300,300,CONT_DIF_N,556nymous_ ++B 30600,25000,300,300,CONT_DIF_P,610nymous_ ++B 11600,8000,300,300,CONT_DIF_N,1149ymous_ ++B 26000,16000,300,300,CONT_BODY_N,503nymous_ ++B 32000,19200,300,300,CONT_BODY_N,664nymous_ ++B 33800,22000,300,300,CONT_VIA,718nymous_ ++B 34800,20200,300,300,CONT_POLY,772nymous_ ++B 36800,9000,300,300,CONT_VIA2,826nymous_ ++B 38000,29000,300,300,CONT_VIA2,880nymous_ ++B 4400,34000,300,300,CONT_VIA,934nymous_ ++B 14000,6000,300,300,CONT_BODY_P,1202ymous_ ++B 6000,33000,300,300,CONT_DIF_N,988nymous_ ++B 7600,31000,300,300,CONT_VIA,1042ymous_ ++B 17800,26800,300,300,CONT_DIF_N,1310ymous_ ++B 1600,31400,300,300,CONT_BODY_P,1256ymous_ ++B 22400,8600,300,300,CONT_DIF_N,396nymous_ ++B 2800,25000,300,300,CONT_DIF_N,557nymous_ ++B 9200,34000,300,300,CONT_DIF_N,1096ymous_ ++B 11600,9000,300,300,CONT_DIF_N,1150ymous_ ++B 26000,17000,300,300,CONT_VIA,504nymous_ ++B 25000,21600,300,300,CONT_DIF_P,450nymous_ ++B 30600,26000,300,300,CONT_DIF_P,611nymous_ ++B 3200,6000,300,300,CONT_BODY_P,665nymous_ ++B 33800,22000,300,300,CONT_VIA2,719nymous_ ++B 34800,22000,300,300,CONT_VIA2,773nymous_ ++B 36800,10000,300,300,CONT_VIA2,827nymous_ ++B 38000,33000,300,300,CONT_VIA2,881nymous_ ++B 4400,35000,300,300,CONT_DIF_N,935nymous_ ++B 1600,32400,300,300,CONT_BODY_P,1257ymous_ ++B 14000,6000,300,300,CONT_VIA,1203ymous_ ++B 6000,34000,300,300,CONT_DIF_N,989nymous_ ++B 7600,31000,300,300,CONT_VIA2,1043ymous_ ++B 17800,28000,300,300,CONT_DIF_N,1311ymous_ ++B 22400,16000,300,300,CONT_BODY_N,397nymous_ ++B 2800,26000,300,300,CONT_DIF_N,558nymous_ ++B 9200,35000,300,300,CONT_DIF_N,1097ymous_ ++B 11600,11800,300,300,CONT_DIF_P,1151ymous_ ++B 26000,17000,300,300,CONT_VIA2,505nymous_ ++B 25000,22800,300,300,CONT_DIF_P,451nymous_ ++B 30600,27000,300,300,CONT_DIF_P,612nymous_ ++B 3200,6000,300,300,CONT_VIA,666nymous_ ++B 34800,23000,300,300,CONT_VIA2,774nymous_ ++B 33800,23000,300,300,CONT_DIF_P,720nymous_ ++B 36800,11000,300,300,CONT_VIA2,828nymous_ ++B 38000,34000,300,300,CONT_VIA2,882nymous_ ++B 4400,35000,300,300,CONT_VIA,936nymous_ ++B 6000,35000,300,300,CONT_DIF_N,990nymous_ ++B 1600,33400,300,300,CONT_BODY_P,1258ymous_ ++B 14000,6000,300,300,CONT_VIA2,1204ymous_ ++B 7600,32000,300,300,CONT_DIF_N,1044ymous_ ++B 9200,36000,300,300,CONT_DIF_N,1098ymous_ ++B 17800,28000,300,300,CONT_VIA,1312ymous_ ++B 4400,36000,300,300,CONT_VIA,938nymous_ ++B 38200,20400,300,300,CONT_BODY_N,884nymous_ ++B 36800,13000,300,300,CONT_BODY_N,830nymous_ ++B 34800,28000,300,300,CONT_VIA2,776nymous_ ++B 33800,23000,300,300,CONT_VIA2,722nymous_ ++B 3200,7000,300,300,CONT_BODY_P,668nymous_ ++B 2600,37600,300,300,CONT_BODY_P,507nymous_ ++B 11600,13800,300,300,CONT_DIF_P,1153ymous_ ++B 30600,27000,300,300,CONT_VIA2,614nymous_ ++B 2800,28000,300,300,CONT_DIF_N,560nymous_ ++B 22400,17000,300,300,CONT_VIA2,399nymous_ ++B 25000,24000,300,300,CONT_DIF_P,453nymous_ ++B 9200,6000,300,300,CONT_BODY_P,1099ymous_ ++B 7600,32000,300,300,CONT_VIA,1045ymous_ ++B 1600,34400,300,300,CONT_BODY_P,1259ymous_ ++B 17800,29200,300,300,CONT_DIF_N,1313ymous_ ++B 6000,36000,300,300,CONT_DIF_N,991nymous_ ++B 4400,36000,300,300,CONT_DIF_N,937nymous_ ++B 14000,7200,300,300,CONT_DIF_N,1205ymous_ ++B 38000,35000,300,300,CONT_VIA2,883nymous_ ++B 36800,12000,300,300,CONT_BODY_N,829nymous_ ++B 34800,27000,300,300,CONT_VIA2,775nymous_ ++B 33800,23000,300,300,CONT_VIA,721nymous_ ++B 3200,6000,300,300,CONT_VIA2,667nymous_ ++B 26000,19200,300,300,CONT_BODY_N,506nymous_ ++B 11600,12800,300,300,CONT_DIF_P,1152ymous_ ++B 30600,27000,300,300,CONT_VIA,613nymous_ ++B 2800,27000,300,300,CONT_DIF_N,559nymous_ ++B 22400,17000,300,300,CONT_VIA,398nymous_ ++B 25000,22800,300,300,CONT_VIA,452nymous_ ++B 30600,28000,300,300,CONT_VIA,616nymous_ ++B 25000,26400,300,300,CONT_DIF_P,455nymous_ ++B 11600,16000,300,300,CONT_BODY_N,1155ymous_ ++B 9200,6000,300,300,CONT_VIA2,1101ymous_ ++B 2800,30000,300,300,CONT_DIF_N,562nymous_ ++B 23000,21400,300,300,CONT_BODY_N,401nymous_ ++B 17800,30400,300,300,CONT_VIA,1315ymous_ ++B 7600,33000,300,300,CONT_DIF_N,1047ymous_ ++B 6600,25000,300,300,CONT_VIA2,993nymous_ ++B 14000,10000,300,300,CONT_POLY,1207ymous_ ++B 1600,36400,300,300,CONT_BODY_P,1261ymous_ ++B 4400,36000,300,300,CONT_VIA2,939nymous_ ++B 38200,21400,300,300,CONT_BODY_N,885nymous_ ++B 36800,14000,300,300,CONT_BODY_N,831nymous_ ++B 34800,29000,300,300,CONT_VIA2,777nymous_ ++B 33800,24000,300,300,CONT_DIF_P,723nymous_ ++B 3200,7000,300,300,CONT_VIA2,669nymous_ ++B 30600,28000,300,300,CONT_DIF_P,615nymous_ ++B 25000,25200,300,300,CONT_DIF_P,454nymous_ ++B 2600,19200,300,300,CONT_BODY_P,508nymous_ ++B 11600,14800,300,300,CONT_DIF_P,1154ymous_ ++B 9200,6000,300,300,CONT_VIA,1100ymous_ ++B 2800,29000,300,300,CONT_DIF_N,561nymous_ ++B 23000,20400,300,300,CONT_BODY_N,400nymous_ ++B 1600,35400,300,300,CONT_BODY_P,1260ymous_ ++B 17800,30400,300,300,CONT_DIF_N,1314ymous_ ++B 7600,32000,300,300,CONT_VIA2,1046ymous_ ++B 6600,24000,300,300,CONT_VIA2,992nymous_ ++B 14000,8000,300,300,CONT_DIF_N,1206ymous_ ++B 33800,27000,300,300,CONT_VIA2,731nymous_ ++B 7600,34000,300,300,CONT_DIF_N,1049ymous_ ++B 1600,19200,300,300,CONT_BODY_P,1263ymous_ ++B 17800,31600,300,300,CONT_DIF_N,1317ymous_ ++B 6600,30000,300,300,CONT_VIA2,995nymous_ ++B 4400,6000,300,300,CONT_VIA,941nymous_ ++B 14000,12800,300,300,CONT_DIF_P,1209ymous_ ++B 38200,23400,300,300,CONT_BODY_N,887nymous_ ++B 36800,15000,300,300,CONT_VIA2,833nymous_ ++B 34800,34000,300,300,CONT_VIA2,779nymous_ ++B 33800,25000,300,300,CONT_DIF_P,725nymous_ ++B 3200,8000,300,300,CONT_VIA2,671nymous_ ++B 27000,21600,300,300,CONT_DIF_P,510nymous_ ++B 11600,17000,300,300,CONT_VIA,1156ymous_ ++B 30600,28000,300,300,CONT_VIA2,617nymous_ ++B 2800,31000,300,300,CONT_DIF_N,563nymous_ ++B 23000,22400,300,300,CONT_BODY_N,402nymous_ ++B 25000,27600,300,300,CONT_DIF_P,456nymous_ ++B 17800,30400,300,300,CONT_VIA2,1316ymous_ ++B 9200,7000,300,300,CONT_VIA2,1102ymous_ ++B 7600,33000,300,300,CONT_VIA,1048ymous_ ++B 14000,12000,300,300,CONT_DIF_P,1208ymous_ ++B 1600,37600,300,300,CONT_BODY_P,1262ymous_ ++B 6600,26000,300,300,CONT_VIA2,994nymous_ ++B 4400,6000,300,300,CONT_BODY_P,940nymous_ ++B 38200,22400,300,300,CONT_BODY_N,886nymous_ ++B 36800,15000,300,300,CONT_BODY_N,832nymous_ ++B 33800,24000,300,300,CONT_VIA,724nymous_ ++B 34800,33000,300,300,CONT_VIA2,778nymous_ ++B 3200,8000,300,300,CONT_BODY_P,670nymous_ ++B 27000,20400,300,300,CONT_DIF_P,509nymous_ ++B 12800,6000,300,300,CONT_VIA,1175ymous_ ++B 36800,16000,300,300,CONT_VIA2,835nymous_ ++B 35000,19200,300,300,CONT_BODY_N,781nymous_ ++B 33800,26000,300,300,CONT_DIF_P,727nymous_ ++B 3200,12000,300,300,CONT_BODY_N,673nymous_ ++B 30600,29000,300,300,CONT_VIA,619nymous_ ++B 25000,28800,300,300,CONT_DIF_P,458nymous_ ++B 27000,24000,300,300,CONT_DIF_P,512nymous_ ++B 11600,19200,300,300,CONT_BODY_P,1158ymous_ ++B 9200,8000,300,300,CONT_DIF_N,1104ymous_ ++B 2800,33000,300,300,CONT_DIF_N,565nymous_ ++B 23000,24400,300,300,CONT_BODY_N,404nymous_ ++B 16400,6000,300,300,CONT_BODY_P,1264ymous_ ++B 17800,31600,300,300,CONT_VIA2,1318ymous_ ++B 7600,34000,300,300,CONT_VIA,1050ymous_ ++B 6600,31000,300,300,CONT_VIA2,996nymous_ ++B 14000,16000,300,300,CONT_BODY_N,1210ymous_ ++B 4400,6000,300,300,CONT_VIA2,942nymous_ ++B 38200,24400,300,300,CONT_BODY_N,888nymous_ ++B 36800,16000,300,300,CONT_BODY_N,834nymous_ ++B 34800,35000,300,300,CONT_VIA2,780nymous_ ++B 33800,25000,300,300,CONT_VIA,726nymous_ ++B 3200,9000,300,300,CONT_BODY_P,672nymous_ ++B 27000,22800,300,300,CONT_DIF_P,511nymous_ ++B 11600,17000,300,300,CONT_VIA2,1157ymous_ ++B 30600,29000,300,300,CONT_DIF_P,618nymous_ ++B 2800,32000,300,300,CONT_DIF_N,564nymous_ ++B 23000,23400,300,300,CONT_BODY_N,403nymous_ ++B 25000,27600,300,300,CONT_VIA,457nymous_ ++B 9200,7200,300,300,CONT_DIF_N,1103ymous_ ++B 28000,21600,300,300,CONT_DIF_P,541nymous_ ++B 17400,11000,200,200,CONT_TURN1,354nymous_ ++B 17600,8000,200,200,CONT_TURN1,355nymous_ ++B 12400,23000,300,300,CONT_DIF_N,1159ymous_ ++B 9200,8000,300,300,CONT_VIA2,1105ymous_ ++B 2800,34000,300,300,CONT_DIF_N,566nymous_ ++B 23000,25400,300,300,CONT_BODY_N,405nymous_ ++B 17800,32800,300,300,CONT_DIF_N,1319ymous_ ++B 7600,35000,300,300,CONT_DIF_N,1051ymous_ ++B 6600,32000,300,300,CONT_VIA2,997nymous_ ++B 14000,17000,300,300,CONT_VIA,1211ymous_ ++B 16400,6000,300,300,CONT_VIA,1265ymous_ ++B 4400,8000,300,300,CONT_DIF_N,943nymous_ ++B 38200,25400,300,300,CONT_BODY_N,889nymous_ ++B 27000,25200,300,300,CONT_DIF_P,513nymous_ ++B 25000,30000,300,300,CONT_DIF_P,459nymous_ ++B 30600,29000,300,300,CONT_VIA2,620nymous_ ++B 3200,12000,300,300,CONT_VIA2,674nymous_ ++B 35400,22000,300,300,CONT_DIF_P,782nymous_ ++B 33800,26000,300,300,CONT_VIA,728nymous_ ++B 36800,17000,300,300,CONT_VIA,836nymous_ ++B 38200,26400,300,300,CONT_BODY_N,890nymous_ ++B 4400,9000,300,300,CONT_DIF_N,944nymous_ ++B 6600,36000,300,300,CONT_VIA2,998nymous_ ++B 16400,6000,300,300,CONT_VIA2,1266ymous_ ++B 14000,17000,300,300,CONT_VIA2,1212ymous_ ++B 7600,35000,300,300,CONT_VIA,1052ymous_ ++B 9200,10000,300,300,CONT_POLY,1106ymous_ ++B 17800,34000,300,300,CONT_DIF_N,1320ymous_ ++B 25000,30000,300,300,CONT_VIA,460nymous_ ++B 23000,26400,300,300,CONT_BODY_N,406nymous_ ++B 2800,35000,300,300,CONT_DIF_N,567nymous_ ++B 30600,30000,300,300,CONT_DIF_P,621nymous_ ++B 12400,24000,300,300,CONT_DIF_N,1160ymous_ ++B 27000,25200,300,300,CONT_VIA,514nymous_ ++B 3200,13000,300,300,CONT_BODY_N,675nymous_ ++B 33800,27000,300,300,CONT_DIF_P,729nymous_ ++B 35400,23000,300,300,CONT_DIF_P,783nymous_ ++B 36800,17000,300,300,CONT_VIA2,837nymous_ ++B 38200,27400,300,300,CONT_BODY_N,891nymous_ ++B 14600,19200,300,300,CONT_BODY_P,1213ymous_ ++B 4400,11800,300,300,CONT_DIF_P,945nymous_ ++B 6600,19200,300,300,CONT_BODY_P,999nymous_ ++B 17800,35200,300,300,CONT_DIF_N,1321ymous_ ++B 16400,8000,300,300,CONT_DIF_N,1267ymous_ ++B 7600,36000,300,300,CONT_DIF_N,1053ymous_ ++B 9200,12000,300,300,CONT_DIF_P,1107ymous_ ++B 25000,31200,300,300,CONT_DIF_P,461nymous_ ++B 23000,27400,300,300,CONT_BODY_N,407nymous_ ++B 2800,36000,300,300,CONT_DIF_N,568nymous_ ++B 30600,30000,300,300,CONT_VIA,622nymous_ ++B 12400,25000,300,300,CONT_DIF_N,1161ymous_ ++B 27000,26400,300,300,CONT_DIF_P,515nymous_ ++B 3200,13000,300,300,CONT_VIA2,676nymous_ ++B 33800,27000,300,300,CONT_VIA,730nymous_ ++B 35400,24000,300,300,CONT_DIF_P,784nymous_ ++B 37000,22000,300,300,CONT_DIF_P,838nymous_ ++B 38200,28400,300,300,CONT_BODY_N,892nymous_ ++B 4400,12800,300,300,CONT_DIF_P,946nymous_ ++EOF +diff --git a/alliance/src/cells/src/mpxlib/pi_mpx.vbe b/alliance/src/cells/src/mpxlib/pi_mpx.vbe +new file mode 100644 +index 0000000..4e2b19e +--- /dev/null ++++ b/alliance/src/cells/src/mpxlib/pi_mpx.vbe +@@ -0,0 +1,30 @@ ++ENTITY pi_mpx IS ++ GENERIC ( ++ CONSTANT area : NATURAL := 80000; ++ CONSTANT cin_pad : NATURAL := 654; ++ CONSTANT tpll_pad : NATURAL := 1487; ++ CONSTANT rdown_pad : NATURAL := 234; ++ CONSTANT tphh_pad : NATURAL := 233; ++ CONSTANT rup_pad : NATURAL := 273 ++ ); ++ PORT ( ++ pad : in BIT; ++ t : out BIT; ++ ck : in BIT; ++ vdde : in BIT; ++ vddi : in BIT; ++ vsse : in BIT; ++ vssi : in BIT ++ ); ++END pi_mpx; ++ ++ ++ARCHITECTURE behaviour_data_flow OF pi_mpx IS ++ ++BEGIN ++ t <= pad; ++ ++ ASSERT ((((vddi and vdde) and not (vssi)) and not (vsse)) = '1') ++ REPORT "power supply is missing on pi_mpx" ++ SEVERITY WARNING; ++END; +diff --git a/alliance/src/cells/src/mpxlib/piot_mpx.ap b/alliance/src/cells/src/mpxlib/piot_mpx.ap +new file mode 100644 +index 0000000..080fb5d +--- /dev/null ++++ b/alliance/src/cells/src/mpxlib/piot_mpx.ap +@@ -0,0 +1,1563 @@ ++V ALLIANCE : 6 ++H piot_mpx,P,14/9/2014,100 ++A 0,0,40000,80000 ++I 0,40000,padreal_mpx,padreal,NOSYM ++S 28800,9000,29000,9000,200,i,RIGHT,POLY ++S 28000,-300,28000,10900,400,i,UP,ALU2 ++S 28000,0,28000,0,400,i,RIGHT,CALU5 ++S 28000,0,28000,0,400,i,RIGHT,CALU4 ++S 27800,11800,28200,11800,200,i,RIGHT,POLY ++S 30000,-100,30000,10900,400,b,UP,ALU2 ++S 30000,0,30000,0,400,b,RIGHT,CALU5 ++S 30000,0,30000,0,400,b,RIGHT,CALU4 ++S 29600,9800,29600,11400,200,b,UP,POLY ++S 8000,0,8000,0,400,t,RIGHT,CALU5 ++S 8000,0,8000,0,400,t,RIGHT,CALU4 ++S 29000,35100,29000,39700,400,pad,UP,ALU1 ++S 29000,25900,29000,34900,400,pad,UP,ALU1 ++S 28600,33000,29000,33000,600,pad,RIGHT,POLY ++S 28600,31800,29000,31800,600,pad,RIGHT,POLY ++S 28600,30600,29000,30600,600,pad,RIGHT,POLY ++S 28600,25800,29000,25800,600,pad,RIGHT,POLY ++S 20000,48100,20000,71900,24400,pad,UP,CALU1 ++S 700,4000,39300,4000,1000,ck,RIGHT,CALU3 ++S 16800,35800,17200,35800,200,vdde,RIGHT,POLY ++S 700,34000,39300,34000,2400,vdde,RIGHT,CALU3 ++S 700,28000,39300,28000,2400,vdde,RIGHT,CALU3 ++S 3600,22200,5200,22200,200,vdde,RIGHT,POLY ++S 25100,28800,27900,28800,400,vdde,RIGHT,ALU1 ++S 25100,26400,27900,26400,400,vdde,RIGHT,ALU1 ++S 700,22000,39300,22000,2400,vdde,RIGHT,CALU3 ++S 6800,22200,8400,22200,200,vdde,RIGHT,POLY ++S 25100,21600,27900,21600,400,vdde,RIGHT,ALU1 ++S 10500,21800,14300,21800,400,vdde,RIGHT,ALU2 ++S 16800,29900,16800,38300,400,vdde,UP,ALU2 ++S 16800,34600,17200,34600,200,vdde,RIGHT,POLY ++S 16800,33400,17200,33400,200,vdde,RIGHT,POLY ++S 16800,32200,17200,32200,200,vdde,RIGHT,POLY ++S 24000,34200,24400,34200,600,vdde,RIGHT,POLY ++S 24000,35800,24400,35800,600,vdde,RIGHT,POLY ++S 25100,24000,27900,24000,400,vdde,RIGHT,ALU1 ++S 700,16000,39300,16000,2400,vddi,RIGHT,CALU3 ++S 700,10000,39300,10000,2400,vddi,RIGHT,CALU3 ++S 3100,16000,36900,16000,2400,vddi,RIGHT,ALU1 ++S 20000,9600,20000,11000,200,vddi,UP,POLY ++S 17800,22900,17800,31900,400,vsse,UP,ALU2 ++S 700,19000,39300,19000,2400,vsse,RIGHT,CALU3 ++S 700,37000,39300,37000,2400,vsse,RIGHT,CALU3 ++S 700,31000,39300,31000,2400,vsse,RIGHT,CALU3 ++S 700,25000,39300,25000,2400,vsse,RIGHT,CALU3 ++S 7600,22900,7600,37500,400,vsse,UP,ALU1 ++S 4400,22900,4400,37500,400,vsse,UP,ALU1 ++S 30400,36400,30400,36600,200,vsse,UP,POLY ++S 20800,22900,20800,37100,400,vsse,UP,ALU1 ++S 700,13000,39300,13000,2400,vssi,RIGHT,CALU3 ++S 700,7000,39300,7000,2400,vssi,RIGHT,CALU3 ++S 3100,6000,36900,6000,2400,vssi,RIGHT,ALU1 ++S 27800,11800,27800,12400,200,92onymous_,UP,POLY ++S 17500,22600,19100,22600,200,n6d,RIGHT,NTRANS ++S 6800,22500,6800,36700,200,n14c,UP,NTRANS ++S 700,34000,16100,34000,2400,248nymous_,RIGHT,ALU2 ++S 14600,11100,14600,13100,200,p17c,UP,PTRANS ++S 34800,20200,34800,20600,600,169nymous_,UP,POLY ++S 30800,10600,33800,10600,200,cnbb,RIGHT,POLY ++S 30800,8100,30800,12900,400,cnbb,UP,ALU1 ++S 29000,200,29000,2000,0,10onymous_,UP,TALU3 ++S 17700,22000,18900,22000,620,318nymous_,RIGHT,NDIF ++S 24900,20400,28100,20400,620,51onymous_,RIGHT,PDIF ++S 6200,10900,6200,14900,200,p18b,UP,PTRANS ++S 27800,9800,32600,9800,200,91onymous_,RIGHT,POLY ++S 30800,12700,30800,14300,620,126nymous_,UP,PDIF ++S 17700,23200,18900,23200,620,319nymous_,RIGHT,NDIF ++S 14800,22500,14800,36700,200,n15d,UP,NTRANS ++S 24900,21600,28100,21600,420,52onymous_,RIGHT,PDIF ++S 35600,200,35600,2000,9000,11onymous_,UP,TALU3 ++S 35000,7300,35000,8300,200,n5b,UP,NTRANS ++S 6800,6100,6800,7900,400,210nymous_,UP,ALU1 ++S 27800,12500,27800,14500,200,p1,UP,PTRANS ++S 17700,25600,18900,25600,620,321nymous_,RIGHT,NDIF ++S 15200,7500,15200,9100,620,286nymous_,UP,NDIF ++S 6800,7500,6800,9100,620,211nymous_,UP,NDIF ++S 18000,200,18000,12000,18000,13onymous_,UP,TALU5 ++S 10400,7500,10400,9100,420,249nymous_,UP,NDIF ++S 35000,12700,35000,14700,200,p5b,UP,PTRANS ++S 30800,13100,30800,13900,400,127nymous_,UP,ALU1 ++S 24900,22800,28100,22800,420,53onymous_,RIGHT,PDIF ++S 15300,37600,20700,37600,400,285nymous_,RIGHT,ALU1 ++S 17700,24400,18900,24400,620,320nymous_,RIGHT,NDIF ++S 3400,200,3400,12000,7000,12onymous_,UP,TALU5 ++S 24900,24000,28100,24000,420,54onymous_,RIGHT,PDIF ++S 31000,5700,31000,11300,400,128nymous_,UP,ALU2 ++S 35400,21100,35400,36500,620,170nymous_,UP,PDIF ++S 29000,200,29000,12000,0,14onymous_,UP,TALU5 ++S 6900,10000,12700,10000,400,212nymous_,RIGHT,ALU1 ++S 17700,26800,18900,26800,620,322nymous_,RIGHT,NDIF ++S 15200,8100,15200,8900,400,287nymous_,UP,ALU1 ++S 24900,25200,28100,25200,420,55onymous_,RIGHT,PDIF ++S 30700,6000,32300,6000,400,129nymous_,RIGHT,ALU2 ++S 35400,21300,35400,39700,400,171nymous_,UP,ALU1 ++S 35600,200,35600,12000,9000,15onymous_,UP,TALU5 ++S 6800,11100,6800,14700,620,213nymous_,UP,PDIF ++S 17700,28000,18900,28000,620,323nymous_,RIGHT,NDIF ++S 15200,11100,15200,12500,400,288nymous_,UP,ALU1 ++S 24900,26400,28100,26400,420,56onymous_,RIGHT,PDIF ++S 30700,10000,36100,10000,2400,130nymous_,RIGHT,ALU2 ++S 35100,13000,37100,13000,2400,172nymous_,RIGHT,ALU2 ++S 17700,29200,18900,29200,620,324nymous_,RIGHT,NDIF ++S 0,6000,40000,6000,12000,16onymous_,RIGHT,TALU6 ++S 6800,12100,6800,15900,400,214nymous_,UP,ALU1 ++S 15200,11300,15200,12900,620,289nymous_,UP,PDIF ++S 24900,27600,28100,27600,420,57onymous_,RIGHT,PDIF ++S 31400,20900,31400,34300,200,p14a,UP,PTRANS ++S 35600,6100,35600,7900,400,173nymous_,UP,ALU1 ++S 17700,30400,18900,30400,620,325nymous_,RIGHT,NDIF ++S 15600,20700,15600,36300,400,290nymous_,UP,ALU1 ++S 2800,20500,2800,36300,400,94onymous_,UP,ALU1 ++S 20000,40100,20000,59900,4400,17onymous_,UP,ALU1 ++S 7000,6900,7000,14300,400,215nymous_,UP,ALU2 ++S 10100,7600,27300,7600,1200,250nymous_,RIGHT,ALU2 ++S 24900,28800,28100,28800,420,58onymous_,RIGHT,PDIF ++S 31400,35300,31400,36100,200,p11,UP,PTRANS ++S 24900,30000,28100,30000,420,59onymous_,RIGHT,PDIF ++S 10400,8100,10400,8900,400,251nymous_,UP,ALU1 ++S 15600,22700,15600,36500,620,291nymous_,UP,NDIF ++S 17700,31600,18900,31600,620,326nymous_,RIGHT,NDIF ++S 7400,7300,7400,9300,200,n18c,UP,NTRANS ++S 20000,8100,20000,8500,400,18onymous_,UP,ALU1 ++S 2800,22700,2800,36500,620,95onymous_,UP,NDIF ++S 35600,7500,35600,8100,620,174nymous_,UP,NDIF ++S 31400,19100,31400,28300,400,131nymous_,UP,ALU2 ++S 35600,12900,35600,14500,620,175nymous_,UP,PDIF ++S 7400,9600,7400,10600,200,216nymous_,UP,POLY ++S 17700,32800,18900,32800,620,327nymous_,RIGHT,NDIF ++S 15300,18200,21300,18200,400,292nymous_,RIGHT,ALU2 ++S 24900,31200,28100,31200,420,60onymous_,RIGHT,PDIF ++S 10400,11100,10400,13700,400,252nymous_,UP,ALU1 ++S 2200,13600,37800,13600,6800,96onymous_,RIGHT,NWELL ++S 31600,20200,31600,20600,600,132nymous_,UP,POLY ++S 35600,13100,35600,15900,400,176nymous_,UP,ALU1 ++S 2900,20600,15500,20600,400,pad2,RIGHT,ALU1 ++S 2700,20600,15700,20600,400,pad2,RIGHT,ALU1 ++S 21000,12700,21000,18500,400,pad2,UP,ALU2 ++S 20000,8500,20000,9100,620,pad2,UP,NDIF ++S 7400,10900,7400,14900,200,p18c,UP,PTRANS ++S 17700,34000,18900,34000,620,328nymous_,RIGHT,NDIF ++S 15600,17900,15600,20500,400,293nymous_,UP,ALU2 ++S 24900,32400,28100,32400,420,61onymous_,RIGHT,PDIF ++S 10400,11100,10400,14700,620,253nymous_,UP,PDIF ++S 24900,33600,28100,33600,420,62onymous_,RIGHT,PDIF ++S 15800,23700,15800,32300,400,294nymous_,UP,ALU2 ++S 17700,35200,18900,35200,620,329nymous_,RIGHT,NDIF ++S 7600,21800,7600,22200,600,217nymous_,UP,POLY ++S 35300,17000,37100,17000,400,177nymous_,RIGHT,ALU2 ++S 31800,12000,31800,12200,200,133nymous_,UP,POLY ++S 20000,11100,20000,15900,400,19onymous_,UP,ALU1 ++S 28200,9100,28200,11700,400,97onymous_,UP,ALU1 ++S 10700,39600,35500,39600,2400,254nymous_,RIGHT,ALU1 ++S 28300,9000,28700,9000,400,98onymous_,RIGHT,ALU1 ++S 31700,6000,37100,6000,400,134nymous_,RIGHT,ALU2 ++S 36000,20200,36000,20600,600,178nymous_,UP,POLY ++S 20000,12700,20000,17300,400,20onymous_,UP,ALU2 ++S 7300,21800,10100,21800,400,218nymous_,RIGHT,ALU2 ++S 17700,36400,18900,36400,620,330nymous_,RIGHT,NDIF ++S 15800,7300,15800,9300,200,n17d,UP,NTRANS ++S 24900,35000,28100,35000,820,63onymous_,RIGHT,PDIF ++S 10800,21800,10800,22200,600,255nymous_,UP,POLY ++S 28400,7500,28400,8100,620,99onymous_,UP,NDIF ++S 32000,7500,32000,8100,620,135nymous_,UP,NDIF ++S 3600,22500,3600,36700,200,n14a,UP,NTRANS ++S 15800,9600,15800,10800,200,295nymous_,UP,POLY ++S 20600,8300,20600,9300,200,n16c,UP,NTRANS ++S 7600,22700,7600,36500,620,219nymous_,UP,NDIF ++S 17700,8000,22300,8000,400,331nymous_,RIGHT,ALU1 ++S 10800,22700,10800,36500,620,256nymous_,UP,NDIF ++S 28500,8000,30700,8000,400,100nymous_,RIGHT,ALU1 ++S 24900,36400,28100,36400,620,64onymous_,RIGHT,PDIF ++S 3600,22200,5200,22200,200,179nymous_,RIGHT,POLY ++S 31700,7600,37100,7600,1200,136nymous_,RIGHT,ALU2 ++S 20800,19300,20800,37500,400,21onymous_,UP,ALU1 ++S 7600,22900,7600,37500,400,220nymous_,UP,ALU1 ++S 17600,8100,17600,8500,400,332nymous_,UP,ALU1 ++S 15800,11100,15800,13100,200,p17d,UP,PTRANS ++S 28400,12700,28400,14300,620,101nymous_,UP,PDIF ++S 24800,7500,24800,8100,620,65onymous_,UP,NDIF ++S 3480,16000,36920,16000,600,180nymous_,RIGHT,NTIE ++S 10800,22900,10800,39700,400,257nymous_,UP,ALU1 ++S 32000,8100,32000,12900,400,137nymous_,UP,ALU1 ++S 17600,8500,17600,9100,620,333nymous_,UP,NDIF ++S 1700,37600,9500,37600,400,296nymous_,RIGHT,ALU1 ++S 28400,14100,28400,15900,400,102nymous_,UP,ALU1 ++S 24800,8100,24800,13900,400,66onymous_,UP,ALU1 ++S 20800,19080,20800,37720,600,22onymous_,UP,PTIE ++S 7600,22700,7600,38300,2400,221nymous_,UP,ALU2 ++S 11000,7300,11000,9300,200,n18f,UP,NTRANS ++S 32000,12900,32000,14500,620,138nymous_,UP,PDIF ++S 36200,20900,36200,36700,200,p14d,UP,PTRANS ++S 17600,12500,17600,12900,620,334nymous_,UP,PDIF ++S 1700,19200,20700,19200,400,297nymous_,RIGHT,ALU1 ++S 28700,24600,30300,24600,400,103nymous_,RIGHT,ALU2 ++S 24800,13100,24800,14500,620,67onymous_,UP,PDIF ++S 21000,13100,21000,13900,400,23onymous_,UP,ALU1 ++S 8000,-100,8000,11300,400,222nymous_,UP,ALU2 ++S 11000,9600,11000,10600,200,258nymous_,UP,POLY ++S 3200,5880,3200,8720,600,139nymous_,UP,PTIE ++S 36700,37600,38100,37600,400,181nymous_,RIGHT,ALU1 ++S 17700,12800,18300,12800,400,335nymous_,RIGHT,ALU1 ++S 1480,19200,20920,19200,600,298nymous_,RIGHT,PTIE ++S 13200,22200,14800,22200,200,cn,RIGHT,POLY ++S 10000,22200,11600,22200,200,cn,RIGHT,POLY ++S 4100,21800,7900,21800,400,cn,RIGHT,ALU2 ++S 25100,22800,27900,22800,400,cn,RIGHT,ALU1 ++S 25100,20400,27900,20400,400,cn,RIGHT,ALU1 ++S 25000,20100,25000,23100,400,cn,UP,ALU2 ++S 21100,13000,22300,13000,400,24onymous_,RIGHT,ALU1 ++S 3200,6100,3200,9100,400,140nymous_,UP,ALU1 ++S 11000,10900,11000,14900,200,p18f,UP,PTRANS ++S 36800,5880,36800,8720,600,182nymous_,UP,PTIE ++S 17900,22000,18700,22000,400,336nymous_,RIGHT,ALU1 ++S 1600,19300,1600,37500,400,299nymous_,UP,ALU1 ++S 25100,37000,27900,37000,1600,fbul,RIGHT,ALU1 ++S 25100,25200,27900,25200,400,fbul,RIGHT,ALU1 ++S 11600,22500,11600,36700,200,n15b,UP,NTRANS ++S 21200,8500,21200,9100,420,25onymous_,UP,NDIF ++S 3200,5700,3200,16100,400,141nymous_,UP,ALU2 ++S 36800,6100,36800,9100,400,183nymous_,UP,ALU1 ++S 17900,23200,18700,23200,400,337nymous_,RIGHT,ALU1 ++S 1600,19080,1600,37720,600,300nymous_,UP,PTIE ++S 8000,7500,8000,9100,420,223nymous_,UP,NDIF ++S 11600,6100,11600,8900,400,259nymous_,UP,ALU1 ++S 21200,9100,21200,9900,400,26onymous_,UP,ALU1 ++S 2900,6000,7100,6000,400,142nymous_,RIGHT,ALU2 ++S 36800,6900,36800,17300,400,184nymous_,UP,ALU2 ++S 29000,7300,29000,8300,200,n1,UP,NTRANS ++S 16400,29900,16400,32300,400,301nymous_,UP,ALU2 ++S 17900,24400,18700,24400,400,338nymous_,RIGHT,ALU1 ++S 8000,8100,8000,8900,400,224nymous_,UP,ALU1 ++S 11600,7500,11600,9100,420,260nymous_,UP,NDIF ++S 18500,31600,25300,31600,400,cpd,RIGHT,ALU2 ++S 18800,21900,18800,36700,400,cpd,UP,ALU2 ++S 25100,32400,27900,32400,400,cpd,RIGHT,ALU1 ++S 25100,30000,27900,30000,400,cpd,RIGHT,ALU1 ++S 25100,27600,27900,27600,400,cpd,RIGHT,ALU1 ++S 25000,27300,25000,32700,400,cpd,UP,ALU2 ++S 21800,8300,21800,9300,200,n16d,UP,NTRANS ++S 2900,10000,6300,10000,2400,143nymous_,RIGHT,ALU2 ++S 36800,11100,36800,15900,400,185nymous_,UP,ALU1 ++S 16400,6100,16400,8900,400,302nymous_,UP,ALU1 ++S 17900,25600,18700,25600,400,339nymous_,RIGHT,ALU1 ++S 22000,21900,22000,28500,400,27onymous_,UP,ALU2 ++S 8000,11100,8000,13700,400,225nymous_,UP,ALU1 ++S 11600,11100,11600,14700,620,261nymous_,UP,PDIF ++S 29000,8600,29000,9000,200,104nymous_,UP,POLY ++S 3200,11100,3200,15900,400,144nymous_,UP,ALU1 ++S 19500,36800,26300,36800,400,node_cp,RIGHT,ALU2 ++S 17900,35200,19700,35200,400,node_cp,RIGHT,ALU1 ++S 17900,32800,19700,32800,400,node_cp,RIGHT,ALU1 ++S 34600,20600,36200,20600,200,node_cp,RIGHT,POLY ++S 31400,20600,33000,20600,200,node_cp,RIGHT,POLY ++S 28600,24600,29000,24600,600,node_cp,RIGHT,POLY ++S 27700,24600,29300,24600,400,node_cp,RIGHT,ALU2 ++S 28000,24300,28000,31500,400,node_cp,UP,ALU2 ++S 25100,33600,27900,33600,400,node_cp,RIGHT,ALU1 ++S 25100,31200,27900,31200,400,node_cp,RIGHT,ALU1 ++S 36800,10880,36800,16120,600,186nymous_,UP,NTIE ++S 16400,7500,16400,9100,620,303nymous_,UP,NDIF ++S 17900,26800,18700,26800,400,340nymous_,RIGHT,ALU1 ++S 8000,11100,8000,14700,620,226nymous_,UP,PDIF ++S 11600,11900,11600,15900,400,262nymous_,UP,ALU1 ++S 29000,11400,29000,12200,200,105nymous_,UP,POLY ++S 22000,17900,22000,19500,400,28onymous_,UP,ALU2 ++S 3200,10880,3200,16120,600,145nymous_,UP,NTIE ++S 37000,21100,37000,36500,620,187nymous_,UP,PDIF ++S 16400,11300,16400,12900,620,304nymous_,UP,PDIF ++S 8400,22500,8400,36700,200,n14d,UP,NTRANS ++S 17900,28000,18700,28000,400,341nymous_,RIGHT,ALU1 ++S 900,37000,8900,37000,2400,263nymous_,RIGHT,ALU2 ++S 29000,11400,32600,11400,200,106nymous_,RIGHT,POLY ++S 25100,35000,29100,35000,400,68onymous_,RIGHT,ALU1 ++S 21700,18200,25100,18200,400,29onymous_,RIGHT,ALU2 ++S 2900,15400,19300,15400,1200,146nymous_,RIGHT,ALU2 ++S 37000,21300,37000,36300,400,188nymous_,UP,ALU1 ++S 16400,12100,16400,15900,400,305nymous_,UP,ALU1 ++S 8600,7300,8600,9300,200,n18d,UP,NTRANS ++S 17900,30400,18700,30400,400,342nymous_,RIGHT,ALU1 ++S 900,19000,9300,19000,2400,264nymous_,RIGHT,ALU2 ++S 29000,12500,29000,14500,200,p2,UP,PTRANS ++S 22000,19300,22000,22100,400,30onymous_,UP,ALU1 ++S 2900,17000,19100,17000,400,147nymous_,RIGHT,ALU2 ++S 37000,17700,37000,38300,2400,189nymous_,UP,ALU2 ++S 16500,20200,24300,20200,400,306nymous_,RIGHT,ALU2 ++S 8600,9600,8600,10600,200,227nymous_,UP,POLY ++S 17900,31600,18700,31600,400,343nymous_,RIGHT,ALU1 ++S 12200,7300,12200,9300,200,n17a,UP,NTRANS ++S 28700,18200,34700,18200,400,107nymous_,RIGHT,ALU2 ++S 25400,7300,25400,8300,200,n4b,UP,NTRANS ++S 32200,21100,32200,36500,620,148nymous_,UP,PDIF ++S 24000,28200,24400,28200,600,cpb,RIGHT,POLY ++S 19800,22700,19800,30900,400,cpb,UP,ALU1 ++S 19400,31000,19800,31000,200,cpb,RIGHT,POLY ++S 19400,27400,19800,27400,200,cpb,RIGHT,POLY ++S 24000,27000,24400,27000,600,cpb,RIGHT,POLY ++S 19500,28200,24300,28200,400,cpb,RIGHT,ALU2 ++S 19400,26200,19800,26200,200,cpb,RIGHT,POLY ++S 19400,22600,19800,22600,200,cpb,RIGHT,POLY ++S 24800,12700,24800,18500,400,cpb,UP,ALU2 ++S 24000,29200,24400,29200,600,cpb,RIGHT,POLY ++S 38200,19300,38200,37500,400,190nymous_,UP,ALU1 ++S 16800,20300,16800,23300,400,307nymous_,UP,ALU1 ++S 17900,34000,18700,34000,400,344nymous_,RIGHT,ALU1 ++S 8600,10900,8600,14900,200,p18d,UP,PTRANS ++S 12200,9600,12200,10800,200,265nymous_,UP,POLY ++S 22400,8100,22400,8500,400,31onymous_,UP,ALU1 ++S 32200,21300,32200,39700,400,149nymous_,UP,ALU1 ++S 25400,8600,25400,12400,200,69onymous_,UP,POLY ++S 38200,19080,38200,37920,600,191nymous_,UP,NTIE ++S 29000,18300,29000,19500,400,108nymous_,UP,ALU2 ++S 16500,21200,25300,21200,400,308nymous_,RIGHT,ALU2 ++S 9200,20700,9200,36300,400,228nymous_,UP,ALU1 ++S 12200,10000,16400,10000,600,nnt,RIGHT,POLY ++S 22400,8500,22400,9100,620,32onymous_,UP,NDIF ++S 32600,7300,32600,8300,200,n0,UP,NTRANS ++S 17900,36400,18700,36400,400,345nymous_,RIGHT,ALU1 ++S 27200,8100,27200,12900,400,cpbb,UP,ALU1 ++S 25400,10600,27200,10600,200,cpbb,RIGHT,POLY ++S 3900,7600,7300,7600,1200,192nymous_,RIGHT,ALU2 ++S 29300,37000,31900,37000,2400,109nymous_,RIGHT,ALU2 ++S 16800,20900,16800,24700,400,309nymous_,UP,ALU2 ++S 9200,22700,9200,36500,620,229nymous_,UP,NDIF ++S 12200,11100,12200,13100,200,p17a,UP,PTRANS ++S 23600,12900,23600,14500,620,44onymous_,UP,PDIF ++S 32600,8600,32600,9800,200,150nymous_,UP,POLY ++S 25400,12700,25400,14700,200,p4b,UP,PTRANS ++S 22400,8700,22400,12900,400,33onymous_,UP,ALU1 ++S 4400,21800,4400,22200,600,193nymous_,UP,POLY ++S 1800,17700,1800,38300,1600,346nymous_,UP,ALU2 ++S 16800,23200,16800,25400,600,310nymous_,UP,POLY ++S 29480,37600,38520,37600,600,110nymous_,RIGHT,NTIE ++S 8900,6000,26300,6000,400,230nymous_,RIGHT,ALU2 ++S 12400,20700,12400,36300,400,266nymous_,UP,ALU1 ++S 23600,13100,23600,15900,400,45onymous_,UP,ALU1 ++S 26000,21300,26000,24300,400,70onymous_,UP,ALU2 ++S 22100,17000,23700,17000,400,34onymous_,RIGHT,ALU2 ++S 32600,11400,32600,12400,200,151nymous_,UP,POLY ++S 4400,22700,4400,36500,620,194nymous_,UP,NDIF ++S 18200,8300,18200,9300,200,n16a,UP,NTRANS ++S 16800,24100,16800,29500,400,311nymous_,UP,ALU2 ++S 29600,7100,29600,8100,620,111nymous_,UP,NDIF ++S 9200,6100,9200,7900,400,231nymous_,UP,ALU1 ++S 12400,22700,12400,36500,620,267nymous_,UP,NDIF ++S 24000,27100,24000,29100,400,46onymous_,UP,ALU1 ++S 26000,23700,26000,29100,400,71onymous_,UP,ALU2 ++S 23100,37600,27700,37600,400,35onymous_,RIGHT,ALU1 ++S 32600,12700,32600,14700,200,p0,UP,PTRANS ++S 18200,9600,21800,9600,200,347nymous_,RIGHT,POLY ++S 29300,10600,30300,10600,400,112nymous_,RIGHT,ALU2 ++S 4400,22900,4400,37500,400,195nymous_,UP,ALU1 ++S 24000,33900,24000,36100,400,47onymous_,UP,ALU2 ++S 9200,5700,9200,11300,400,232nymous_,UP,ALU2 ++S 16900,24400,17700,24400,400,312nymous_,RIGHT,ALU1 ++S 12400,18500,12400,22100,2400,268nymous_,UP,ALU2 ++S 32800,20200,32800,20600,600,152nymous_,UP,POLY ++S 26000,30900,26000,37100,400,72onymous_,UP,ALU2 ++S 23000,11700,23000,17300,2000,36onymous_,UP,ALU2 ++S 18400,10100,18400,12700,400,348nymous_,UP,ALU1 ++S 16800,25500,16800,28100,400,313nymous_,UP,ALU1 ++S 29600,12700,29600,14300,620,113nymous_,UP,PDIF ++S 4400,22700,4400,38300,2400,196nymous_,UP,ALU2 ++S 9200,7500,9200,9100,620,233nymous_,UP,NDIF ++S 12800,7500,12800,9100,620,269nymous_,UP,NDIF ++S 33000,20900,33000,36700,200,p14b,UP,PTRANS ++S 26000,6100,26000,7900,400,73onymous_,UP,ALU1 ++S 23000,19300,23000,37500,400,37onymous_,UP,ALU1 ++S 18800,8500,18800,9100,420,349nymous_,UP,NDIF ++S 29600,13100,29600,13900,400,114nymous_,UP,ALU1 ++S 24000,18900,24000,20500,400,48onymous_,UP,ALU2 ++S 4400,6100,4400,8900,400,197nymous_,UP,ALU1 ++S 8900,10000,26300,10000,2400,234nymous_,RIGHT,ALU2 ++S 12800,8100,12800,12500,400,270nymous_,UP,ALU1 ++S 9300,25000,16100,25000,2400,237nymous_,RIGHT,ALU2 ++S 17000,12300,17000,13100,200,p16,UP,PTRANS ++S 24200,7300,24200,8300,200,n4a,UP,NTRANS ++S 26000,12900,26000,14500,620,76onymous_,UP,PDIF ++S 33200,12900,33200,14500,620,155nymous_,UP,PDIF ++S 22880,19200,38320,19200,600,40onymous_,RIGHT,NTIE ++S 12900,11000,17300,11000,400,272nymous_,RIGHT,ALU1 ++S 18500,17000,20300,17000,400,351nymous_,RIGHT,ALU2 ++S 9300,31000,16100,31000,2400,238nymous_,RIGHT,ALU2 ++S 24200,8600,25400,8600,200,49onymous_,RIGHT,POLY ++S 26000,13100,26000,15900,400,77onymous_,UP,ALU1 ++S 33200,13100,33200,15900,400,156nymous_,UP,ALU1 ++S 23080,37600,29920,37600,600,41onymous_,RIGHT,NTIE ++S 12800,11300,12800,12900,620,273nymous_,UP,PDIF ++S 19400,8300,19400,9300,200,n16b,UP,NTRANS ++S 4400,11900,4400,15900,400,200nymous_,UP,ALU1 ++S 23000,19080,23000,37920,600,38onymous_,UP,NTIE ++S 33200,6100,33200,7900,400,153nymous_,UP,ALU1 ++S 16800,28200,16800,29800,600,314nymous_,UP,POLY ++S 26000,7500,26000,8100,620,74onymous_,UP,NDIF ++S 30000,19900,30000,24900,400,115nymous_,UP,ALU2 ++S 4400,7500,4400,9100,620,198nymous_,UP,NDIF ++S 9200,11100,9200,14700,620,235nymous_,UP,PDIF ++S 18800,9100,18800,9900,400,350nymous_,UP,ALU1 ++S 12900,9000,15100,9000,400,271nymous_,RIGHT,ALU1 ++S 23100,19200,38100,19200,400,39onymous_,RIGHT,ALU1 ++S 33200,7500,33200,8100,620,154nymous_,UP,NDIF ++S 16900,29200,18700,29200,400,315nymous_,RIGHT,ALU1 ++S 26000,8700,26000,14300,400,75onymous_,UP,ALU2 ++S 16800,29800,17200,29800,200,cnb,RIGHT,POLY ++S 16800,28600,17200,28600,200,cnb,RIGHT,POLY ++S 16800,25000,17200,25000,200,cnb,RIGHT,POLY ++S 16800,23800,17200,23800,200,cnb,RIGHT,POLY ++S 34400,12700,34400,18500,400,cnb,UP,ALU2 ++S 29000,17900,29000,23700,400,cnb,UP,ALU2 ++S 28600,23400,29000,23400,600,cnb,RIGHT,POLY ++S 28600,22200,29000,22200,600,cnb,RIGHT,POLY ++S 28600,21000,29000,21000,600,cnb,RIGHT,POLY ++S 23700,19200,29300,19200,400,cnb,RIGHT,ALU2 ++S 4400,11100,4400,14700,620,199nymous_,UP,PDIF ++S 9200,12100,9200,15900,400,236nymous_,UP,ALU1 ++S 13200,22500,13200,36700,200,n15c,UP,NTRANS ++S 4100,13000,20300,13000,2400,201nymous_,RIGHT,ALU2 ++S 30100,20200,35900,20200,400,116nymous_,RIGHT,ALU1 ++S 26000,13700,26000,16100,400,78onymous_,UP,ALU2 ++S 23600,6100,23600,7900,400,42onymous_,UP,ALU1 ++S 33400,11700,33400,17300,400,157nymous_,UP,ALU2 ++S 24200,12700,24200,14700,200,p4a,UP,PTRANS ++S 13400,7300,13400,9300,200,n17b,UP,NTRANS ++S 23600,7500,23600,8100,620,43onymous_,UP,NDIF ++S 9800,21500,9800,23100,400,239nymous_,UP,ALU2 ++S 33800,21100,33800,36500,620,158nymous_,UP,PDIF ++S 5000,7300,5000,9300,200,n18a,UP,NTRANS ++S 19800,32900,19800,35100,400,352nymous_,UP,ALU1 ++S 30200,7300,30200,8300,200,n3,UP,NTRANS ++S 25700,15400,32500,15400,1200,79onymous_,RIGHT,ALU2 ++S 24200,12400,25400,12400,200,50onymous_,RIGHT,POLY ++S 5000,9600,5000,10600,200,202nymous_,UP,POLY ++S 9500,22800,17100,22800,400,240nymous_,RIGHT,ALU2 ++S 33800,21300,33800,36300,400,159nymous_,UP,ALU1 ++S 13400,9600,13400,10800,200,274nymous_,UP,POLY ++S 25700,17000,33500,17000,400,80onymous_,RIGHT,ALU2 ++S 17500,23800,19100,23800,200,n7d,RIGHT,NTRANS ++S 24700,21000,28300,21000,200,p7c,RIGHT,PTRANS ++S 30200,8600,30200,9000,200,117nymous_,UP,POLY ++S 17000,12000,17400,12000,200,nt,RIGHT,POLY ++S 5000,10000,11000,10000,600,nt,RIGHT,POLY ++S 9500,37000,17100,37000,2400,241nymous_,RIGHT,ALU2 ++S 19800,34900,19800,37100,400,353nymous_,UP,ALU2 ++S 33800,7300,33800,8300,200,n5a,UP,NTRANS ++S 17500,25000,19100,25000,200,n7c,RIGHT,NTRANS ++S 13400,11100,13400,13100,200,p17b,UP,PTRANS ++S 2700,20200,15700,20200,400,81onymous_,RIGHT,ALU1 ++S 24700,22200,28300,22200,200,p7b,RIGHT,PTRANS ++S 30200,12000,31800,12000,200,eb,RIGHT,POLY ++S 30200,9000,31800,9000,200,eb,RIGHT,POLY ++S 33800,8600,33800,12400,200,160nymous_,UP,POLY ++S 5000,10900,5000,14900,200,p18a,UP,PTRANS ++S 9800,7300,9800,9300,200,n18e,UP,NTRANS ++S 17500,26200,19100,26200,200,n6c,RIGHT,NTRANS ++S 14000,21800,14000,22200,600,275nymous_,UP,POLY ++S 26400,18600,26400,38600,8400,82onymous_,UP,NWELL ++S 24700,23400,28300,23400,200,p7a,RIGHT,PTRANS ++S 30200,12000,30200,12200,200,118nymous_,UP,POLY ++S 50,6000,6800,6000,12000,0nonymous_,RIGHT,TALU2 ++S 5200,22500,5200,36700,200,n14b,UP,NTRANS ++S 9800,9600,9800,10600,200,242nymous_,UP,POLY ++S 24700,24600,28300,24600,200,p10,RIGHT,PTRANS ++S 33800,8600,35000,8600,200,161nymous_,RIGHT,POLY ++S 17500,27400,19100,27400,200,n6b,RIGHT,NTRANS ++S 14000,22700,14000,36500,620,276nymous_,UP,NDIF ++S 27000,24900,27000,36700,400,83onymous_,UP,ALU2 ++S 5600,7500,5600,9100,420,203nymous_,UP,NDIF ++S 9800,10900,9800,14900,200,p18e,UP,PTRANS ++S 9200,6000,26800,6000,12000,1nonymous_,RIGHT,TALU2 ++S 24700,25800,28300,25800,200,p13,RIGHT,PTRANS ++S 30200,12500,30200,14500,200,p3,UP,PTRANS ++S 33800,12700,33800,14700,200,p5a,UP,PTRANS ++S 17500,28600,19100,28600,200,n7b,RIGHT,NTRANS ++S 14000,22900,14000,39700,400,277nymous_,UP,ALU1 ++S 27000,6900,27000,14300,400,84onymous_,UP,ALU2 ++S 5600,8100,5600,13700,400,1.nq,UP,ALU1 ++S 10000,22500,10000,36700,200,n15a,UP,NTRANS ++S 33800,12400,35000,12400,200,162nymous_,RIGHT,POLY ++S 17500,29800,19100,29800,200,n7a,RIGHT,NTRANS ++S 31200,6000,39950,6000,12000,2nonymous_,RIGHT,TALU2 ++S 24700,27000,28300,27000,200,p6c,RIGHT,PTRANS ++S 14000,6100,14000,7900,400,278nymous_,UP,ALU1 ++S 30400,36400,30400,36600,200,119nymous_,UP,POLY ++S 26700,13000,33700,13000,2400,85onymous_,RIGHT,ALU2 ++S 10000,22200,11600,22200,200,243nymous_,RIGHT,POLY ++S 5700,9000,10300,9000,400,204nymous_,RIGHT,ALU1 ++S 33800,19100,33800,38300,2400,163nymous_,UP,ALU2 ++S 17500,31000,19100,31000,200,n6a,RIGHT,NTRANS ++S 24700,28200,28300,28200,200,p6b,RIGHT,PTRANS ++S 14000,7500,14000,9100,620,279nymous_,UP,NDIF ++S 27200,7500,27200,8100,620,86onymous_,UP,NDIF ++S 30600,21100,30600,35900,620,120nymous_,UP,PDIF ++S 5600,11100,5600,14700,620,205nymous_,UP,PDIF ++S 24700,29400,28300,29400,200,p6a,RIGHT,PTRANS ++S 34000,18200,34000,38200,10400,164nymous_,UP,NWELL ++S 9700,19000,14900,19000,2400,244nymous_,RIGHT,ALU2 ++S 17500,32200,19100,32200,200,n8d,RIGHT,NTRANS ++S 14100,10000,21100,10000,400,280nymous_,RIGHT,ALU1 ++S 50,6000,6800,6000,12000,4nonymous_,RIGHT,TALU4 ++S 27200,12700,27200,14300,620,87onymous_,UP,PDIF ++S 5700,11000,10300,11000,400,206nymous_,RIGHT,ALU1 ++S 9200,6000,26800,6000,12000,5nonymous_,RIGHT,TALU4 ++S 24700,30600,28300,30600,200,p8c,RIGHT,PTRANS ++S 3280,6000,28520,6000,600,165nymous_,RIGHT,PTIE ++S 700,25000,8900,25000,2400,245nymous_,RIGHT,ALU2 ++S 17500,33400,19100,33400,200,n8c,RIGHT,NTRANS ++S 14000,11300,14000,12900,620,281nymous_,UP,PDIF ++S 30600,21300,30600,35500,400,121nymous_,UP,ALU1 ++S 27200,13100,27200,13900,400,88onymous_,UP,ALU1 ++S 6000,20700,6000,36300,400,207nymous_,UP,ALU1 ++S 50,17000,39950,17000,10000,blockagenet,RIGHT,TALU2 ++S 17500,34600,19100,34600,200,n8b,RIGHT,NTRANS ++S 31200,6000,39950,6000,12000,6nonymous_,RIGHT,TALU4 ++S 24700,31800,28300,31800,200,p8b,RIGHT,PTRANS ++S 30600,26700,30600,35300,2400,122nymous_,UP,ALU2 ++S 34400,7500,34400,8100,620,166nymous_,UP,NDIF ++S 14000,12100,14000,15900,400,282nymous_,UP,ALU1 ++S 27300,13000,29500,13000,400,89onymous_,RIGHT,ALU1 ++S 6000,22700,6000,36500,620,208nymous_,UP,NDIF ++S 17500,35800,19100,35800,200,n8a,RIGHT,NTRANS ++S 24700,33000,28300,33000,200,p8a,RIGHT,PTRANS ++S 30600,36400,31400,36400,200,123nymous_,RIGHT,POLY ++S 34400,8100,34400,13900,400,167nymous_,UP,ALU1 ++S 1280,37600,21120,37600,600,283nymous_,RIGHT,PTIE ++S 700,28000,15100,28000,2400,246nymous_,RIGHT,ALU2 ++S 27800,7300,27800,8300,200,n2,UP,NTRANS ++S 24700,34200,28300,34200,200,p9,RIGHT,PTRANS ++S 6200,7300,6200,9300,200,n18b,UP,NTRANS ++S 17400,11100,17400,11700,400,316nymous_,UP,ALU1 ++S 3400,200,3400,2000,7000,8nonymous_,UP,TALU3 ++S 30680,6000,37120,6000,600,124nymous_,RIGHT,PTIE ++S 34400,13100,34400,14500,620,168nymous_,UP,PDIF ++S 14600,7300,14600,9300,200,n17c,UP,NTRANS ++S 27800,8600,27800,9800,200,90onymous_,UP,POLY ++S 6200,9600,6200,10600,200,209nymous_,UP,POLY ++S 24700,35800,28300,35800,200,p12,RIGHT,PTRANS ++S 34600,20900,34600,36700,200,p14c,UP,PTRANS ++S 700,31000,8900,31000,2400,247nymous_,RIGHT,ALU2 ++S 17400,11800,17400,12000,200,317nymous_,UP,POLY ++S 14600,9600,14600,10800,200,284nymous_,UP,POLY ++S 18000,200,18000,2000,18000,9nonymous_,UP,TALU3 ++S 30800,7500,30800,8100,620,125nymous_,UP,NDIF ++B 1600,31400,300,300,CONT_BODY_P,1268ymous_ ++B 14000,6000,300,300,CONT_BODY_P,1214ymous_ ++B 6000,33000,300,300,CONT_DIF_N,1000ymous_ ++B 7600,31000,300,300,CONT_VIA,1054ymous_ ++B 17800,26800,300,300,CONT_DIF_N,1322ymous_ ++B 23000,22400,300,300,CONT_BODY_N,408nymous_ ++B 2800,28000,300,300,CONT_DIF_N,569nymous_ ++B 9200,34000,300,300,CONT_DIF_N,1108ymous_ ++B 11600,9000,300,300,CONT_DIF_N,1162ymous_ ++B 27000,21600,300,300,CONT_DIF_P,516nymous_ ++B 25000,27600,300,300,CONT_DIF_P,462nymous_ ++B 30600,26000,300,300,CONT_DIF_P,623nymous_ ++B 3200,6000,300,300,CONT_BODY_P,677nymous_ ++B 34800,22000,300,300,CONT_VIA2,785nymous_ ++B 36800,10000,300,300,CONT_VIA2,839nymous_ ++B 38000,33000,300,300,CONT_VIA2,893nymous_ ++B 4400,35000,300,300,CONT_DIF_N,947nymous_ ++B 6000,34000,300,300,CONT_DIF_N,1001ymous_ ++B 1600,32400,300,300,CONT_BODY_P,1269ymous_ ++B 14000,6000,300,300,CONT_VIA,1215ymous_ ++B 7600,31000,300,300,CONT_VIA2,1055ymous_ ++B 9200,35000,300,300,CONT_DIF_N,1109ymous_ ++B 17800,28000,300,300,CONT_DIF_N,1323ymous_ ++B 25000,27600,300,300,CONT_VIA,463nymous_ ++B 23000,23400,300,300,CONT_BODY_N,409nymous_ ++B 2800,29000,300,300,CONT_DIF_N,570nymous_ ++B 30600,27000,300,300,CONT_DIF_P,624nymous_ ++B 11600,11800,300,300,CONT_DIF_P,1163ymous_ ++B 27000,22800,300,300,CONT_DIF_P,517nymous_ ++B 3200,6000,300,300,CONT_VIA,678nymous_ ++B 33800,23000,300,300,CONT_DIF_P,732nymous_ ++B 34800,23000,300,300,CONT_VIA2,786nymous_ ++B 36800,11000,300,300,CONT_VIA2,840nymous_ ++B 38000,34000,300,300,CONT_VIA2,894nymous_ ++B 14000,6000,300,300,CONT_VIA2,1216ymous_ ++B 4400,35000,300,300,CONT_VIA,948nymous_ ++B 6000,35000,300,300,CONT_DIF_N,1002ymous_ ++B 17800,28000,300,300,CONT_VIA,1324ymous_ ++B 1600,33400,300,300,CONT_BODY_P,1270ymous_ ++B 22400,13000,200,200,CONT_TURN1,356nymous_ ++B 7600,32000,300,300,CONT_DIF_N,1056ymous_ ++B 9200,36000,300,300,CONT_DIF_N,1110ymous_ ++B 25000,28800,300,300,CONT_DIF_P,464nymous_ ++B 23000,24400,300,300,CONT_BODY_N,410nymous_ ++B 27200,14000,300,300,CONT_DIF_P,540nymous_ ++B 2800,30000,300,300,CONT_DIF_N,571nymous_ ++B 30600,27000,300,300,CONT_VIA,625nymous_ ++B 33800,23000,300,300,CONT_VIA,733nymous_ ++B 11600,12800,300,300,CONT_DIF_P,1164ymous_ ++B 27000,24000,300,300,CONT_DIF_P,518nymous_ ++B 3200,6000,300,300,CONT_VIA2,679nymous_ ++B 34800,27000,300,300,CONT_VIA2,787nymous_ ++B 36800,12000,300,300,CONT_BODY_N,841nymous_ ++B 38000,35000,300,300,CONT_VIA2,895nymous_ ++B 4400,36000,300,300,CONT_DIF_N,949nymous_ ++B 14000,7200,300,300,CONT_DIF_N,1217ymous_ ++B 6000,36000,300,300,CONT_DIF_N,1003ymous_ ++B 7600,32000,300,300,CONT_VIA,1057ymous_ ++B 17800,29200,300,300,CONT_DIF_N,1325ymous_ ++B 1600,34400,300,300,CONT_BODY_P,1271ymous_ ++B 23000,25400,300,300,CONT_BODY_N,411nymous_ ++B 28200,9000,200,200,CONT_TURN1,357nymous_ ++B 2800,31000,300,300,CONT_DIF_N,572nymous_ ++B 9200,6000,300,300,CONT_BODY_P,1111ymous_ ++B 11600,13800,300,300,CONT_DIF_P,1165ymous_ ++B 27000,25200,300,300,CONT_DIF_P,519nymous_ ++B 25000,30000,300,300,CONT_DIF_P,465nymous_ ++B 30600,27000,300,300,CONT_VIA2,626nymous_ ++B 3200,7000,300,300,CONT_BODY_P,680nymous_ ++B 33800,23000,300,300,CONT_VIA2,734nymous_ ++B 34800,28000,300,300,CONT_VIA2,788nymous_ ++B 36800,13000,300,300,CONT_BODY_N,842nymous_ ++B 38200,20400,300,300,CONT_BODY_N,896nymous_ ++B 4400,36000,300,300,CONT_VIA,950nymous_ ++B 1600,35400,300,300,CONT_BODY_P,1272ymous_ ++B 14000,8000,300,300,CONT_DIF_N,1218ymous_ ++B 6600,24000,300,300,CONT_VIA2,1004ymous_ ++B 7600,32000,300,300,CONT_VIA2,1058ymous_ ++B 17800,30400,300,300,CONT_DIF_N,1326ymous_ ++B 23000,26400,300,300,CONT_BODY_N,412nymous_ ++B 5000,19000,8300,2300,CONT_VIA2,358nymous_ ++B 2800,32000,300,300,CONT_DIF_N,573nymous_ ++B 9200,6000,300,300,CONT_VIA,1112ymous_ ++B 11600,14800,300,300,CONT_DIF_P,1166ymous_ ++B 27000,25200,300,300,CONT_VIA,520nymous_ ++B 25000,30000,300,300,CONT_VIA,466nymous_ ++B 30600,28000,300,300,CONT_DIF_P,627nymous_ ++B 3200,7000,300,300,CONT_VIA2,681nymous_ ++B 33800,24000,300,300,CONT_DIF_P,735nymous_ ++B 34800,29000,300,300,CONT_VIA2,789nymous_ ++B 36800,14000,300,300,CONT_BODY_N,843nymous_ ++B 38200,21400,300,300,CONT_BODY_N,897nymous_ ++B 4400,36000,300,300,CONT_VIA2,951nymous_ ++B 6600,25000,300,300,CONT_VIA2,1005ymous_ ++B 1600,36400,300,300,CONT_BODY_P,1273ymous_ ++B 14000,10000,300,300,CONT_POLY,1219ymous_ ++B 10400,11000,200,200,CONT_TURN1,359nymous_ ++B 7600,33000,300,300,CONT_DIF_N,1059ymous_ ++B 9200,6000,300,300,CONT_VIA2,1113ymous_ ++B 17800,30400,300,300,CONT_VIA,1327ymous_ ++B 25000,31200,300,300,CONT_DIF_P,467nymous_ ++B 23000,27400,300,300,CONT_BODY_N,413nymous_ ++B 2800,33000,300,300,CONT_DIF_N,574nymous_ ++B 30600,28000,300,300,CONT_VIA,628nymous_ ++B 11600,16000,300,300,CONT_BODY_N,1167ymous_ ++B 27000,26400,300,300,CONT_DIF_P,521nymous_ ++B 3200,8000,300,300,CONT_BODY_P,682nymous_ ++B 33800,24000,300,300,CONT_VIA,736nymous_ ++B 34800,33000,300,300,CONT_VIA2,790nymous_ ++B 36800,15000,300,300,CONT_BODY_N,844nymous_ ++B 38200,22400,300,300,CONT_BODY_N,898nymous_ ++B 14000,12000,300,300,CONT_DIF_P,1220ymous_ ++B 4400,6000,300,300,CONT_BODY_P,952nymous_ ++B 6600,26000,300,300,CONT_VIA2,1006ymous_ ++B 17800,30400,300,300,CONT_VIA2,1328ymous_ ++B 1600,37600,300,300,CONT_BODY_P,1274ymous_ ++B 17400,11000,200,200,CONT_TURN1,360nymous_ ++B 7600,33000,300,300,CONT_VIA,1060ymous_ ++B 9200,7000,300,300,CONT_VIA2,1114ymous_ ++B 25000,32400,300,300,CONT_DIF_P,468nymous_ ++B 23000,28400,300,300,CONT_BODY_N,414nymous_ ++B 2800,34000,300,300,CONT_DIF_N,575nymous_ ++B 30600,28000,300,300,CONT_VIA2,629nymous_ ++B 33800,25000,300,300,CONT_DIF_P,737nymous_ ++B 11600,17000,300,300,CONT_VIA,1168ymous_ ++B 27000,27600,300,300,CONT_DIF_P,522nymous_ ++B 3200,8000,300,300,CONT_VIA2,683nymous_ ++B 34800,34000,300,300,CONT_VIA2,791nymous_ ++B 36800,15000,300,300,CONT_VIA2,845nymous_ ++B 38200,23400,300,300,CONT_BODY_N,899nymous_ ++B 4400,6000,300,300,CONT_VIA,953nymous_ ++B 14000,12800,300,300,CONT_DIF_P,1221ymous_ ++B 6600,30000,300,300,CONT_VIA2,1007ymous_ ++B 7600,34000,300,300,CONT_DIF_N,1061ymous_ ++B 17800,31600,300,300,CONT_DIF_N,1329ymous_ ++B 1600,19200,300,300,CONT_BODY_P,1275ymous_ ++B 23000,29400,300,300,CONT_BODY_N,415nymous_ ++B 17600,8000,200,200,CONT_TURN1,361nymous_ ++B 2800,35000,300,300,CONT_DIF_N,576nymous_ ++B 9200,7200,300,300,CONT_DIF_N,1115ymous_ ++B 11600,17000,300,300,CONT_VIA2,1169ymous_ ++B 27000,28800,300,300,CONT_DIF_P,523nymous_ ++B 25000,32400,300,300,CONT_VIA,469nymous_ ++B 30600,29000,300,300,CONT_DIF_P,630nymous_ ++B 3200,9000,300,300,CONT_BODY_P,684nymous_ ++B 33800,25000,300,300,CONT_VIA,738nymous_ ++B 34800,35000,300,300,CONT_VIA2,792nymous_ ++B 36800,16000,300,300,CONT_BODY_N,846nymous_ ++B 38200,24400,300,300,CONT_BODY_N,900nymous_ ++B 4400,6000,300,300,CONT_VIA2,954nymous_ ++B 16400,6000,300,300,CONT_BODY_P,1276ymous_ ++B 14000,16000,300,300,CONT_BODY_N,1222ymous_ ++B 6600,31000,300,300,CONT_VIA2,1008ymous_ ++B 7600,34000,300,300,CONT_VIA,1062ymous_ ++B 17800,31600,300,300,CONT_VIA2,1330ymous_ ++B 23000,30400,300,300,CONT_BODY_N,416nymous_ ++B 17800,22000,200,200,CONT_TURN1,362nymous_ ++B 2800,36000,300,300,CONT_DIF_N,577nymous_ ++B 9200,8000,300,300,CONT_DIF_N,1116ymous_ ++B 11600,19200,300,300,CONT_BODY_P,1170ymous_ ++B 27000,30000,300,300,CONT_DIF_P,524nymous_ ++B 25000,33600,300,300,CONT_DIF_P,470nymous_ ++B 30600,29000,300,300,CONT_VIA,631nymous_ ++B 3200,12000,300,300,CONT_BODY_N,685nymous_ ++B 33800,26000,300,300,CONT_DIF_P,739nymous_ ++B 35000,19200,300,300,CONT_BODY_N,793nymous_ ++B 36800,16000,300,300,CONT_VIA2,847nymous_ ++B 38200,25400,300,300,CONT_BODY_N,901nymous_ ++B 4400,8000,300,300,CONT_DIF_N,955nymous_ ++B 6600,32000,300,300,CONT_VIA2,1009ymous_ ++B 16400,6000,300,300,CONT_VIA,1277ymous_ ++B 14000,17000,300,300,CONT_VIA,1223ymous_ ++B 18400,12800,200,200,CONT_TURN1,363nymous_ ++B 7600,35000,300,300,CONT_DIF_N,1063ymous_ ++B 9200,8000,300,300,CONT_VIA2,1117ymous_ ++B 17800,32800,300,300,CONT_DIF_N,1331ymous_ ++B 25000,35000,300,300,CONT_DIF_P,471nymous_ ++B 23000,31400,300,300,CONT_BODY_N,417nymous_ ++B 28200,10600,300,300,CONT_VIA,578nymous_ ++B 30600,29000,300,300,CONT_VIA2,632nymous_ ++B 12400,23000,300,300,CONT_DIF_N,1171ymous_ ++B 27000,31200,300,300,CONT_DIF_P,525nymous_ ++B 3200,12000,300,300,CONT_VIA2,686nymous_ ++B 33800,26000,300,300,CONT_VIA,740nymous_ ++B 35400,22000,300,300,CONT_DIF_P,794nymous_ ++B 36800,17000,300,300,CONT_VIA,848nymous_ ++B 38200,26400,300,300,CONT_BODY_N,902nymous_ ++B 14000,17000,300,300,CONT_VIA2,1224ymous_ ++B 4400,9000,300,300,CONT_DIF_N,956nymous_ ++B 6600,36000,300,300,CONT_VIA2,1010ymous_ ++B 17800,34000,300,300,CONT_DIF_N,1332ymous_ ++B 16400,6000,300,300,CONT_VIA2,1278ymous_ ++B 19800,32800,200,200,CONT_TURN1,364nymous_ ++B 7600,35000,300,300,CONT_VIA,1064ymous_ ++B 9200,10000,300,300,CONT_POLY,1118ymous_ ++B 25000,36400,300,300,CONT_DIF_P,472nymous_ ++B 23000,32400,300,300,CONT_BODY_N,418nymous_ ++B 28200,11800,300,300,CONT_POLY,579nymous_ ++B 30600,30000,300,300,CONT_DIF_P,633nymous_ ++B 33800,27000,300,300,CONT_DIF_P,741nymous_ ++B 12400,24000,300,300,CONT_DIF_N,1172ymous_ ++B 27000,32400,300,300,CONT_DIF_P,526nymous_ ++B 3200,13000,300,300,CONT_BODY_N,687nymous_ ++B 35400,23000,300,300,CONT_DIF_P,795nymous_ ++B 36800,17000,300,300,CONT_VIA2,849nymous_ ++B 38200,27400,300,300,CONT_BODY_N,903nymous_ ++B 4400,11800,300,300,CONT_DIF_P,957nymous_ ++B 14600,19200,300,300,CONT_BODY_P,1225ymous_ ++B 6600,19200,300,300,CONT_BODY_P,1011ymous_ ++B 7600,36000,300,300,CONT_DIF_N,1065ymous_ ++B 17800,35200,300,300,CONT_DIF_N,1333ymous_ ++B 16400,8000,300,300,CONT_DIF_N,1279ymous_ ++B 23000,33400,300,300,CONT_BODY_N,419nymous_ ++B 20000,6000,300,300,CONT_BODY_P,365nymous_ ++B 28400,6000,300,300,CONT_BODY_P,580nymous_ ++B 9200,12000,300,300,CONT_DIF_P,1119ymous_ ++B 12400,25000,300,300,CONT_DIF_N,1173ymous_ ++B 27000,33600,300,300,CONT_DIF_P,527nymous_ ++B 25000,37600,300,300,CONT_BODY_N,473nymous_ ++B 30600,30000,300,300,CONT_VIA,634nymous_ ++B 3200,13000,300,300,CONT_VIA2,688nymous_ ++B 33800,27000,300,300,CONT_VIA,742nymous_ ++B 35400,24000,300,300,CONT_DIF_P,796nymous_ ++B 37000,22000,300,300,CONT_DIF_P,850nymous_ ++B 38200,28400,300,300,CONT_BODY_N,904nymous_ ++B 4400,12800,300,300,CONT_DIF_P,958nymous_ ++B 16400,9000,300,300,CONT_DIF_N,1280ymous_ ++B 15200,6000,300,300,CONT_BODY_P,1226ymous_ ++B 6800,37600,300,300,CONT_BODY_P,1012ymous_ ++B 7600,36000,300,300,CONT_VIA,1066ymous_ ++B 17800,36400,300,300,CONT_DIF_N,1334ymous_ ++B 23000,34400,300,300,CONT_BODY_N,420nymous_ ++B 20000,6000,300,300,CONT_VIA,366nymous_ ++B 28400,8000,300,300,CONT_DIF_N,581nymous_ ++B 9200,12800,300,300,CONT_DIF_P,1120ymous_ ++B 12400,26000,300,300,CONT_DIF_N,1174ymous_ ++B 27000,35000,300,300,CONT_DIF_P,528nymous_ ++B 25000,19200,300,300,CONT_BODY_N,474nymous_ ++B 30600,31000,300,300,CONT_DIF_P,635nymous_ ++B 3200,14000,300,300,CONT_BODY_N,689nymous_ ++B 33800,27000,300,300,CONT_VIA2,743nymous_ ++B 35400,25000,300,300,CONT_DIF_P,797nymous_ ++B 37000,22000,300,300,CONT_VIA,851nymous_ ++B 38200,29400,300,300,CONT_BODY_N,905nymous_ ++B 4400,13800,300,300,CONT_DIF_P,959nymous_ ++B 6800,37600,300,300,CONT_VIA,1013ymous_ ++B 16400,10000,300,300,CONT_POLY,1281ymous_ ++B 15200,6000,300,300,CONT_VIA,1227ymous_ ++B 20000,6000,300,300,CONT_VIA2,367nymous_ ++B 7600,36000,300,300,CONT_VIA2,1067ymous_ ++B 9200,13800,300,300,CONT_DIF_P,1121ymous_ ++B 17800,37600,300,300,CONT_BODY_P,1335ymous_ ++B 26000,20400,300,300,CONT_DIF_P,475nymous_ ++B 23000,35400,300,300,CONT_BODY_N,421nymous_ ++B 28400,14000,300,300,CONT_DIF_P,582nymous_ ++B 30600,31000,300,300,CONT_VIA,636nymous_ ++B 27000,36400,300,300,CONT_DIF_P,529nymous_ ++B 3200,14000,300,300,CONT_VIA2,690nymous_ ++B 33800,28000,300,300,CONT_DIF_P,744nymous_ ++B 35400,26000,300,300,CONT_DIF_P,798nymous_ ++B 37000,22000,300,300,CONT_VIA2,852nymous_ ++B 38200,30400,300,300,CONT_BODY_N,906nymous_ ++B 15200,6000,300,300,CONT_VIA2,1228ymous_ ++B 4400,14800,300,300,CONT_DIF_P,960nymous_ ++B 6800,37600,300,300,CONT_VIA2,1014ymous_ ++B 18600,19200,300,300,CONT_BODY_P,1336ymous_ ++B 16400,12000,300,300,CONT_DIF_P,1282ymous_ ++B 20000,8600,300,300,CONT_DIF_N,368nymous_ ++B 7600,19200,300,300,CONT_BODY_P,1068ymous_ ++B 9200,14800,300,300,CONT_DIF_P,1122ymous_ ++B 12400,28000,300,300,CONT_DIF_N,1176ymous_ ++B 26000,21600,300,300,CONT_DIF_P,476nymous_ ++B 23000,36400,300,300,CONT_BODY_N,422nymous_ ++B 28400,16000,300,300,CONT_BODY_N,583nymous_ ++B 30600,32000,300,300,CONT_DIF_P,637nymous_ ++B 33800,28000,300,300,CONT_VIA,745nymous_ ++B 27000,36400,300,300,CONT_VIA,530nymous_ ++B 3200,15000,300,300,CONT_BODY_N,691nymous_ ++B 35400,27000,300,300,CONT_DIF_P,799nymous_ ++B 37000,23000,300,300,CONT_DIF_P,853nymous_ ++B 38200,31400,300,300,CONT_BODY_N,907nymous_ ++B 4400,16000,300,300,CONT_BODY_N,961nymous_ ++B 15200,8000,300,300,CONT_DIF_N,1229ymous_ ++B 6800,6000,300,300,CONT_BODY_P,1015ymous_ ++B 7800,37600,300,300,CONT_BODY_P,1069ymous_ ++B 18800,22000,300,300,CONT_DIF_N,1337ymous_ ++B 16400,12800,300,300,CONT_DIF_P,1283ymous_ ++B 23000,37600,300,300,CONT_BODY_N,423nymous_ ++B 20000,11000,300,300,CONT_POLY,369nymous_ ++B 28400,17000,300,300,CONT_VIA,584nymous_ ++B 9200,16000,300,300,CONT_BODY_N,1123ymous_ ++B 12400,29000,300,300,CONT_DIF_N,1177ymous_ ++B 27000,37600,300,300,CONT_BODY_N,531nymous_ ++B 26000,21600,300,300,CONT_VIA,477nymous_ ++B 30600,32000,300,300,CONT_VIA,638nymous_ ++B 3200,16000,300,300,CONT_BODY_N,692nymous_ ++B 33800,28000,300,300,CONT_VIA2,746nymous_ ++B 35400,28000,300,300,CONT_DIF_P,800nymous_ ++B 37000,23000,300,300,CONT_VIA,854nymous_ ++B 38200,32400,300,300,CONT_BODY_N,908nymous_ ++B 4400,17000,300,300,CONT_VIA,962nymous_ ++B 16400,16000,300,300,CONT_BODY_N,1284ymous_ ++B 15200,9000,300,300,CONT_DIF_N,1230ymous_ ++B 6800,6000,300,300,CONT_VIA,1016ymous_ ++B 7800,37600,300,300,CONT_VIA,1070ymous_ ++B 18800,22200,300,300,CONT_VIA,1338ymous_ ++B 23000,19200,300,300,CONT_BODY_N,424nymous_ ++B 20000,16000,300,300,CONT_BODY_N,370nymous_ ++B 28400,17000,300,300,CONT_VIA2,585nymous_ ++B 9200,17000,300,300,CONT_VIA,1124ymous_ ++B 12400,30000,300,300,CONT_DIF_N,1178ymous_ ++B 27000,9000,300,300,CONT_VIA2,532nymous_ ++B 26000,21600,300,300,CONT_VIA2,478nymous_ ++B 30600,33000,300,300,CONT_DIF_P,639nymous_ ++B 3200,17000,300,300,CONT_VIA,693nymous_ ++B 33800,29000,300,300,CONT_DIF_P,747nymous_ ++B 35400,29000,300,300,CONT_DIF_P,801nymous_ ++B 37000,23000,300,300,CONT_VIA2,855nymous_ ++B 38200,33400,300,300,CONT_BODY_N,909nymous_ ++B 4400,17000,300,300,CONT_VIA2,963nymous_ ++B 6800,6000,300,300,CONT_VIA2,1017ymous_ ++B 16400,17000,300,300,CONT_VIA,1285ymous_ ++B 15200,10000,300,300,CONT_POLY,1231ymous_ ++B 20800,20400,300,300,CONT_BODY_P,371nymous_ ++B 7800,37600,300,300,CONT_VIA2,1071ymous_ ++B 9200,17000,300,300,CONT_VIA2,1125ymous_ ++B 18800,23200,300,300,CONT_DIF_N,1339ymous_ ++B 26000,22800,300,300,CONT_DIF_P,479nymous_ ++B 23400,17000,300,300,CONT_VIA,425nymous_ ++B 28800,9000,300,300,CONT_POLY,586nymous_ ++B 30600,33000,300,300,CONT_VIA,640nymous_ ++B 12400,31000,300,300,CONT_DIF_N,1179ymous_ ++B 27000,10000,300,300,CONT_VIA2,533nymous_ ++B 3200,17000,300,300,CONT_VIA2,694nymous_ ++B 33800,29000,300,300,CONT_VIA,748nymous_ ++B 35400,30000,300,300,CONT_DIF_P,802nymous_ ++B 37000,24000,300,300,CONT_DIF_P,856nymous_ ++B 38200,34400,300,300,CONT_BODY_N,910nymous_ ++B 15200,11600,300,300,CONT_DIF_P,1232ymous_ ++B 4600,37600,300,300,CONT_BODY_P,964nymous_ ++B 6800,7200,300,300,CONT_DIF_N,1018ymous_ ++B 18800,24400,300,300,CONT_DIF_N,1340ymous_ ++B 16400,17000,300,300,CONT_VIA2,1286ymous_ ++B 20800,21400,300,300,CONT_BODY_P,372nymous_ ++B 8000,0,300,300,CONT_VIA2,1072ymous_ ++B 9600,37600,300,300,CONT_BODY_P,1126ymous_ ++B 26000,22800,300,300,CONT_VIA2,480nymous_ ++B 23400,17000,300,300,CONT_VIA2,426nymous_ ++B 29000,21000,300,300,CONT_POLY,587nymous_ ++B 30600,33000,300,300,CONT_VIA2,641nymous_ ++B 33800,29000,300,300,CONT_VIA2,749nymous_ ++B 27000,11000,300,300,CONT_VIA2,534nymous_ ++B 32200,22000,300,300,CONT_DIF_P,695nymous_ ++B 35400,31000,300,300,CONT_DIF_P,803nymous_ ++B 37000,24000,300,300,CONT_VIA,857nymous_ ++B 38200,35400,300,300,CONT_BODY_N,911nymous_ ++B 4600,37600,300,300,CONT_VIA,965nymous_ ++B 15200,12600,300,300,CONT_DIF_P,1233ymous_ ++B 6800,8000,300,300,CONT_DIF_N,1019ymous_ ++B 8000,0,300,300,CONT_VIA3,1073ymous_ ++B 18800,25600,300,300,CONT_DIF_N,1341ymous_ ++B 16600,19200,300,300,CONT_BODY_P,1287ymous_ ++B 23600,6000,300,300,CONT_BODY_P,427nymous_ ++B 20800,22400,300,300,CONT_BODY_P,373nymous_ ++B 29000,21000,300,300,CONT_VIA,588nymous_ ++B 9600,19200,300,300,CONT_BODY_P,1127ymous_ ++B 27000,19200,300,300,CONT_BODY_N,535nymous_ ++B 26000,24000,300,300,CONT_DIF_P,481nymous_ ++B 30600,34000,300,300,CONT_DIF_P,642nymous_ ++B 32200,23000,300,300,CONT_DIF_P,696nymous_ ++B 33800,30000,300,300,CONT_DIF_P,750nymous_ ++B 35400,32000,300,300,CONT_DIF_P,804nymous_ ++B 37000,25000,300,300,CONT_DIF_P,858nymous_ ++B 38200,36400,300,300,CONT_BODY_N,912nymous_ ++B 4600,37600,300,300,CONT_VIA2,966nymous_ ++B 16800,20200,300,300,CONT_VIA,1288ymous_ ++B 15200,16000,300,300,CONT_BODY_N,1234ymous_ ++B 6800,10000,300,300,CONT_POLY,1020ymous_ ++B 8000,0,300,300,CONT_VIA4,1074ymous_ ++B 18800,26800,300,300,CONT_DIF_N,1342ymous_ ++B 23600,6000,300,300,CONT_VIA,428nymous_ ++B 20800,23400,300,300,CONT_BODY_P,374nymous_ ++B 29000,22200,300,300,CONT_POLY,589nymous_ ++B 10400,6000,300,300,CONT_BODY_P,1128ymous_ ++B 27200,6000,300,300,CONT_BODY_P,536nymous_ ++B 26000,24000,300,300,CONT_VIA,482nymous_ ++B 30600,34000,300,300,CONT_VIA,643nymous_ ++B 32200,24000,300,300,CONT_DIF_P,697nymous_ ++B 33800,30000,300,300,CONT_VIA,751nymous_ ++B 35400,33000,300,300,CONT_DIF_P,805nymous_ ++B 37000,25000,300,300,CONT_VIA,859nymous_ ++B 38200,37600,300,300,CONT_BODY_N,913nymous_ ++B 4600,19200,300,300,CONT_BODY_P,967nymous_ ++B 6800,12000,300,300,CONT_DIF_P,1021ymous_ ++B 16800,23400,300,300,CONT_POLY,1289ymous_ ++B 15200,17000,300,300,CONT_VIA,1235ymous_ ++B 20800,24400,300,300,CONT_BODY_P,375nymous_ ++B 8000,8000,300,300,CONT_DIF_N,1075ymous_ ++B 10400,6000,300,300,CONT_VIA,1129ymous_ ++B 18800,26800,300,300,CONT_VIA,1343ymous_ ++B 26000,25200,300,300,CONT_DIF_P,483nymous_ ++B 23600,6000,300,300,CONT_VIA2,429nymous_ ++B 29000,22200,300,300,CONT_VIA,590nymous_ ++B 30600,34000,300,300,CONT_VIA2,644nymous_ ++B 27200,8000,300,300,CONT_DIF_N,537nymous_ ++B 32200,25000,300,300,CONT_DIF_P,698nymous_ ++B 33800,31000,300,300,CONT_DIF_P,752nymous_ ++B 35400,34000,300,300,CONT_DIF_P,806nymous_ ++B 37000,26000,300,300,CONT_DIF_P,860nymous_ ++B 38200,19200,300,300,CONT_BODY_N,914nymous_ ++B 15200,17000,300,300,CONT_VIA2,1236ymous_ ++B 12400,34000,300,300,CONT_DIF_N,1182ymous_ ++B 5400,24000,300,300,CONT_VIA2,968nymous_ ++B 6800,12800,300,300,CONT_DIF_P,1022ymous_ ++B 18800,28000,300,300,CONT_DIF_N,1344ymous_ ++B 16800,24400,300,300,CONT_VIA,1290ymous_ ++B 20800,25400,300,300,CONT_BODY_P,376nymous_ ++B 8000,9000,300,300,CONT_DIF_N,1076ymous_ ++B 10400,6000,300,300,CONT_VIA2,1130ymous_ ++B 26000,26400,300,300,CONT_DIF_P,484nymous_ ++B 23600,8000,300,300,CONT_DIF_N,430nymous_ ++B 29000,23400,300,300,CONT_POLY,591nymous_ ++B 30600,35000,300,300,CONT_DIF_P,645nymous_ ++B 33800,31000,300,300,CONT_VIA,753nymous_ ++B 27200,10600,300,300,CONT_POLY,538nymous_ ++B 32200,26000,300,300,CONT_DIF_P,699nymous_ ++B 35400,35000,300,300,CONT_DIF_P,807nymous_ ++B 37000,26000,300,300,CONT_VIA,861nymous_ ++B 4400,21800,300,300,CONT_POLY,915nymous_ ++B 5400,25000,300,300,CONT_VIA2,969nymous_ ++B 15600,20200,300,300,CONT_VIA,1237ymous_ ++B 12400,35000,300,300,CONT_DIF_N,1183ymous_ ++B 6800,13800,300,300,CONT_DIF_P,1023ymous_ ++B 8000,9000,300,300,CONT_VIA,1077ymous_ ++B 18800,29200,300,300,CONT_DIF_N,1345ymous_ ++B 16800,25400,300,300,CONT_POLY,1291ymous_ ++B 23600,13000,300,300,CONT_DIF_P,431nymous_ ++B 20800,26400,300,300,CONT_BODY_P,377nymous_ ++B 29000,23400,300,300,CONT_VIA,592nymous_ ++B 10400,8000,300,300,CONT_DIF_N,1131ymous_ ++B 27200,13000,300,300,CONT_DIF_P,539nymous_ ++B 26000,26400,300,300,CONT_VIA,485nymous_ ++B 30600,35000,300,300,CONT_VIA,646nymous_ ++B 32200,27000,300,300,CONT_DIF_P,700nymous_ ++B 33800,32000,300,300,CONT_DIF_P,754nymous_ ++B 35400,36000,300,300,CONT_DIF_P,808nymous_ ++B 37000,27000,300,300,CONT_DIF_P,862nymous_ ++B 12400,36000,300,300,CONT_DIF_N,1184ymous_ ++B 4400,21800,300,300,CONT_VIA,916nymous_ ++B 5400,26000,300,300,CONT_VIA2,970nymous_ ++B 16800,28200,300,300,CONT_POLY,1292ymous_ ++B 15600,23000,300,300,CONT_DIF_N,1238ymous_ ++B 6800,14800,300,300,CONT_DIF_P,1024ymous_ ++B 8000,10000,300,300,CONT_POLY,1078ymous_ ++B 18800,30400,300,300,CONT_DIF_N,1346ymous_ ++B 23600,14000,300,300,CONT_DIF_P,432nymous_ ++B 20800,27400,300,300,CONT_BODY_P,378nymous_ ++B 29000,24600,300,300,CONT_POLY,593nymous_ ++B 10400,9000,300,300,CONT_DIF_N,1132ymous_ ++B 12400,32000,300,300,CONT_DIF_N,1180ymous_ ++B 26000,27600,300,300,CONT_DIF_P,486nymous_ ++B 30600,35000,300,300,CONT_VIA2,647nymous_ ++B 32200,28000,300,300,CONT_DIF_P,701nymous_ ++B 33800,32000,300,300,CONT_VIA,755nymous_ ++B 35600,6000,300,300,CONT_BODY_P,809nymous_ ++B 37000,27000,300,300,CONT_VIA,863nymous_ ++B 4400,23000,300,300,CONT_DIF_N,917nymous_ ++B 12600,19200,300,300,CONT_BODY_P,1185ymous_ ++B 5400,30000,300,300,CONT_VIA2,971nymous_ ++B 6800,16000,300,300,CONT_BODY_N,1025ymous_ ++B 16800,29200,300,300,CONT_VIA,1293ymous_ ++B 15600,24000,300,300,CONT_DIF_N,1239ymous_ ++B 20800,28400,300,300,CONT_BODY_P,379nymous_ ++B 8000,11000,300,300,CONT_VIA,1079ymous_ ++B 10400,10000,300,300,CONT_POLY,1133ymous_ ++B 18800,31600,300,300,CONT_DIF_N,1347ymous_ ++B 26000,27600,300,300,CONT_VIA2,487nymous_ ++B 23600,16000,300,300,CONT_BODY_N,433nymous_ ++B 29000,24600,300,300,CONT_VIA,594nymous_ ++B 30800,6000,300,300,CONT_BODY_P,648nymous_ ++B 12400,33000,300,300,CONT_DIF_N,1181ymous_ ++B 32200,29000,300,300,CONT_DIF_P,702nymous_ ++B 33800,33000,300,300,CONT_DIF_P,756nymous_ ++B 35600,6000,300,300,CONT_VIA,810nymous_ ++B 37000,27000,300,300,CONT_VIA2,864nymous_ ++B 4400,23000,300,300,CONT_VIA,918nymous_ ++B 15600,25000,300,300,CONT_DIF_N,1240ymous_ ++B 12800,6000,300,300,CONT_BODY_P,1186ymous_ ++B 5400,31000,300,300,CONT_VIA2,972nymous_ ++B 6800,17000,300,300,CONT_VIA,1026ymous_ ++B 18800,31600,300,300,CONT_VIA,1348ymous_ ++B 16800,32200,300,300,CONT_POLY,1294ymous_ ++B 20800,29400,300,300,CONT_BODY_P,380nymous_ ++B 8000,11800,300,300,CONT_DIF_P,1080ymous_ ++B 10400,11800,300,300,CONT_DIF_P,1134ymous_ ++B 26000,28800,300,300,CONT_DIF_P,488nymous_ ++B 24000,27000,300,300,CONT_POLY,434nymous_ ++B 29000,25800,300,300,CONT_POLY,595nymous_ ++B 30800,8000,300,300,CONT_DIF_N,649nymous_ ++B 33800,33000,300,300,CONT_VIA,757nymous_ ++B 32200,30000,300,300,CONT_DIF_P,703nymous_ ++B 35600,6000,300,300,CONT_VIA2,811nymous_ ++B 37000,28000,300,300,CONT_DIF_P,865nymous_ ++B 4400,24000,300,300,CONT_DIF_N,919nymous_ ++B 5400,32000,300,300,CONT_VIA2,973nymous_ ++B 15600,26000,300,300,CONT_DIF_N,1241ymous_ ++B 12800,6000,300,300,CONT_VIA,1187ymous_ ++B 6800,17000,300,300,CONT_VIA2,1027ymous_ ++B 8000,12800,300,300,CONT_DIF_P,1081ymous_ ++B 18800,32800,300,300,CONT_DIF_N,1349ymous_ ++B 16800,32200,300,300,CONT_VIA,1295ymous_ ++B 24000,28200,300,300,CONT_POLY,435nymous_ ++B 20800,30400,300,300,CONT_BODY_P,381nymous_ ++B 27200,17000,300,300,CONT_VIA,542nymous_ ++B 29000,30600,300,300,CONT_POLY,596nymous_ ++B 10400,12800,300,300,CONT_DIF_P,1135ymous_ ++B 26000,28800,300,300,CONT_VIA,489nymous_ ++B 30800,10600,300,300,CONT_POLY,650nymous_ ++B 32200,31000,300,300,CONT_DIF_P,704nymous_ ++B 33800,33000,300,300,CONT_VIA2,758nymous_ ++B 35600,8000,300,300,CONT_DIF_N,812nymous_ ++B 37000,28000,300,300,CONT_VIA,866nymous_ ++B 12800,6000,300,300,CONT_VIA2,1188ymous_ ++B 4400,24000,300,300,CONT_VIA,920nymous_ ++B 5400,36000,300,300,CONT_VIA2,974nymous_ ++B 16800,33400,300,300,CONT_POLY,1296ymous_ ++B 15600,27000,300,300,CONT_DIF_N,1242ymous_ ++B 7000,9000,300,300,CONT_VIA2,1028ymous_ ++B 8000,13800,300,300,CONT_DIF_P,1082ymous_ ++B 18800,34000,300,300,CONT_DIF_N,1350ymous_ ++B 24000,28200,300,300,CONT_VIA,436nymous_ ++B 20800,31400,300,300,CONT_BODY_P,382nymous_ ++B 27200,17000,300,300,CONT_VIA2,543nymous_ ++B 29000,31800,300,300,CONT_POLY,597nymous_ ++B 10400,13800,300,300,CONT_DIF_P,1136ymous_ ++B 26000,28800,300,300,CONT_VIA2,490nymous_ ++B 30800,13000,300,300,CONT_DIF_P,651nymous_ ++B 32200,32000,300,300,CONT_DIF_P,705nymous_ ++B 33800,34000,300,300,CONT_DIF_P,759nymous_ ++B 35600,13000,300,300,CONT_DIF_P,813nymous_ ++B 37000,28000,300,300,CONT_VIA2,867nymous_ ++B 4400,24000,300,300,CONT_VIA2,921nymous_ ++B 12800,8000,300,300,CONT_DIF_N,1189ymous_ ++B 5600,37600,300,300,CONT_BODY_P,975nymous_ ++B 7000,10000,300,300,CONT_VIA2,1029ymous_ ++B 16800,33400,300,300,CONT_VIA,1297ymous_ ++B 15600,28000,300,300,CONT_DIF_N,1243ymous_ ++B 20800,32400,300,300,CONT_BODY_P,383nymous_ ++B 27800,36400,300,300,CONT_DIF_P,544nymous_ ++B 8000,16000,300,300,CONT_BODY_N,1083ymous_ ++B 10400,16000,300,300,CONT_BODY_N,1137ymous_ ++B 18800,34000,300,300,CONT_VIA,1351ymous_ ++B 26000,30000,300,300,CONT_DIF_P,491nymous_ ++B 24000,29200,300,300,CONT_POLY,437nymous_ ++B 29000,33000,300,300,CONT_POLY,598nymous_ ++B 30800,14000,300,300,CONT_DIF_P,652nymous_ ++B 32200,33000,300,300,CONT_DIF_P,706nymous_ ++B 33800,34000,300,300,CONT_VIA,760nymous_ ++B 35600,14000,300,300,CONT_DIF_P,814nymous_ ++B 37000,29000,300,300,CONT_DIF_P,868nymous_ ++B 4400,25000,300,300,CONT_DIF_N,922nymous_ ++B 15600,29000,300,300,CONT_DIF_N,1244ymous_ ++B 12800,9000,300,300,CONT_DIF_N,1190ymous_ ++B 5600,37600,300,300,CONT_VIA,976nymous_ ++B 7000,11000,300,300,CONT_VIA2,1030ymous_ ++B 18800,35200,300,300,CONT_DIF_N,1352ymous_ ++B 16800,33400,300,300,CONT_VIA2,1298ymous_ ++B 20800,33400,300,300,CONT_BODY_P,384nymous_ ++B 27800,37600,300,300,CONT_BODY_N,545nymous_ ++B 8000,17000,300,300,CONT_VIA,1084ymous_ ++B 10400,17000,300,300,CONT_VIA,1138ymous_ ++B 26000,31200,300,300,CONT_DIF_P,492nymous_ ++B 24000,34200,300,300,CONT_POLY,438nymous_ ++B 29000,19200,300,300,CONT_BODY_N,599nymous_ ++B 30800,16000,300,300,CONT_BODY_N,653nymous_ ++B 33800,34000,300,300,CONT_VIA2,761nymous_ ++B 32200,34000,300,300,CONT_DIF_P,707nymous_ ++B 35600,16000,300,300,CONT_BODY_N,815nymous_ ++B 37000,29000,300,300,CONT_VIA,869nymous_ ++B 4400,25000,300,300,CONT_VIA,923nymous_ ++B 5600,37600,300,300,CONT_VIA2,977nymous_ ++B 15600,30000,300,300,CONT_DIF_N,1245ymous_ ++B 12800,11600,300,300,CONT_DIF_P,1191ymous_ ++B 7600,21800,300,300,CONT_POLY,1031ymous_ ++B 8000,17000,300,300,CONT_VIA2,1085ymous_ ++B 18800,36400,300,300,CONT_DIF_N,1353ymous_ ++B 16800,34600,300,300,CONT_POLY,1299ymous_ ++B 24000,34200,300,300,CONT_VIA,439nymous_ ++B 20800,34400,300,300,CONT_BODY_P,385nymous_ ++B 28000,0,300,300,CONT_VIA2,546nymous_ ++B 29600,33000,300,300,CONT_VIA2,600nymous_ ++B 10400,17000,300,300,CONT_VIA2,1139ymous_ ++B 26000,31200,300,300,CONT_VIA,493nymous_ ++B 30800,17000,300,300,CONT_VIA,654nymous_ ++B 32200,35000,300,300,CONT_DIF_P,708nymous_ ++B 33800,35000,300,300,CONT_DIF_P,762nymous_ ++B 35600,17000,300,300,CONT_VIA,816nymous_ ++B 37000,29000,300,300,CONT_VIA2,870nymous_ ++B 12800,12600,300,300,CONT_DIF_P,1192ymous_ ++B 4400,25000,300,300,CONT_VIA2,924nymous_ ++B 5600,6000,300,300,CONT_BODY_P,978nymous_ ++B 16800,34600,300,300,CONT_VIA,1300ymous_ ++B 15600,31000,300,300,CONT_DIF_N,1246ymous_ ++B 7600,21800,300,300,CONT_VIA,1032ymous_ ++B 8600,24000,300,300,CONT_VIA2,1086ymous_ ++B 18800,36400,300,300,CONT_VIA,1354ymous_ ++B 24000,34200,300,300,CONT_VIA2,440nymous_ ++B 20800,35400,300,300,CONT_BODY_P,386nymous_ ++B 28000,0,300,300,CONT_VIA3,547nymous_ ++B 29600,34000,300,300,CONT_VIA2,601nymous_ ++B 10600,19200,300,300,CONT_BODY_P,1140ymous_ ++B 26000,32400,300,300,CONT_DIF_P,494nymous_ ++B 30800,17000,300,300,CONT_VIA2,655nymous_ ++B 32200,36000,300,300,CONT_DIF_P,709nymous_ ++B 33800,35000,300,300,CONT_VIA,763nymous_ ++B 35600,17000,300,300,CONT_VIA2,817nymous_ ++B 37000,30000,300,300,CONT_DIF_P,871nymous_ ++B 4400,26000,300,300,CONT_DIF_N,925nymous_ ++B 12800,16000,300,300,CONT_BODY_N,1193ymous_ ++B 5600,6000,300,300,CONT_VIA,979nymous_ ++B 7600,23000,300,300,CONT_DIF_N,1033ymous_ ++B 16800,34600,300,300,CONT_VIA2,1301ymous_ ++B 15600,32000,300,300,CONT_DIF_N,1247ymous_ ++B 20800,36400,300,300,CONT_BODY_P,387nymous_ ++B 28000,0,300,300,CONT_VIA4,548nymous_ ++B 8600,25000,300,300,CONT_VIA2,1087ymous_ ++B 10800,21800,300,300,CONT_POLY,1141ymous_ ++B 18800,37600,300,300,CONT_BODY_P,1355ymous_ ++B 26000,33600,300,300,CONT_DIF_P,495nymous_ ++B 24000,35800,300,300,CONT_POLY,441nymous_ ++B 29600,35000,300,300,CONT_VIA2,602nymous_ ++B 31000,19200,300,300,CONT_BODY_N,656nymous_ ++B 32800,20200,300,300,CONT_POLY,710nymous_ ++B 33800,35000,300,300,CONT_VIA2,764nymous_ ++B 36000,20200,300,300,CONT_POLY,818nymous_ ++B 37000,30000,300,300,CONT_VIA,872nymous_ ++B 4400,26000,300,300,CONT_VIA,926nymous_ ++B 15600,33000,300,300,CONT_DIF_N,1248ymous_ ++B 12800,17000,300,300,CONT_VIA,1194ymous_ ++B 5600,6000,300,300,CONT_VIA2,980nymous_ ++B 7600,23000,300,300,CONT_VIA,1034ymous_ ++B 18800,6000,300,300,CONT_BODY_P,1356ymous_ ++B 16800,35800,300,300,CONT_POLY,1302ymous_ ++B 20800,37600,300,300,CONT_BODY_P,388nymous_ ++B 28000,20400,300,300,CONT_DIF_P,549nymous_ ++B 8600,26000,300,300,CONT_VIA2,1088ymous_ ++B 10800,21800,300,300,CONT_VIA,1142ymous_ ++B 26000,33600,300,300,CONT_VIA,496nymous_ ++B 24000,35800,300,300,CONT_VIA,442nymous_ ++B 29600,7000,300,300,CONT_DIF_N,603nymous_ ++B 31600,20200,300,300,CONT_POLY,657nymous_ ++B 33800,36000,300,300,CONT_DIF_P,765nymous_ ++B 32800,22000,300,300,CONT_VIA2,711nymous_ ++B 36000,22000,300,300,CONT_VIA2,819nymous_ ++B 37000,31000,300,300,CONT_DIF_P,873nymous_ ++B 4400,26000,300,300,CONT_VIA2,927nymous_ ++B 5600,8000,300,300,CONT_DIF_N,981nymous_ ++B 15600,34000,300,300,CONT_DIF_N,1249ymous_ ++B 12800,17000,300,300,CONT_VIA2,1195ymous_ ++B 7600,24000,300,300,CONT_DIF_N,1035ymous_ ++B 8600,30000,300,300,CONT_VIA2,1089ymous_ ++B 18800,6000,300,300,CONT_VIA,1357ymous_ ++B 16800,35800,300,300,CONT_VIA,1303ymous_ ++B 24000,37600,300,300,CONT_BODY_N,443nymous_ ++B 20800,19200,300,300,CONT_BODY_P,389nymous_ ++B 28000,21600,300,300,CONT_DIF_P,550nymous_ ++B 29600,10600,300,300,CONT_POLY,604nymous_ ++B 10800,21800,300,300,CONT_VIA2,1143ymous_ ++B 26000,35000,300,300,CONT_DIF_P,497nymous_ ++B 31600,22000,300,300,CONT_VIA2,658nymous_ ++B 32800,23000,300,300,CONT_VIA2,712nymous_ ++B 33800,36000,300,300,CONT_VIA,766nymous_ ++B 36000,23000,300,300,CONT_VIA2,820nymous_ ++B 37000,31000,300,300,CONT_VIA,874nymous_ ++B 13600,19200,300,300,CONT_BODY_P,1196ymous_ ++B 4400,27000,300,300,CONT_DIF_N,928nymous_ ++B 5600,9000,300,300,CONT_DIF_N,982nymous_ ++B 16800,37600,300,300,CONT_BODY_P,1304ymous_ ++B 15600,35000,300,300,CONT_DIF_N,1250ymous_ ++B 7600,24000,300,300,CONT_VIA,1036ymous_ ++B 8600,31000,300,300,CONT_VIA2,1090ymous_ ++B 18800,6000,300,300,CONT_VIA2,1358ymous_ ++B 24000,19200,300,300,CONT_BODY_N,444nymous_ ++B 21000,13000,300,300,CONT_VIA,390nymous_ ++B 28000,22800,300,300,CONT_DIF_P,551nymous_ ++B 29600,10600,300,300,CONT_VIA,605nymous_ ++B 10800,23000,300,300,CONT_DIF_N,1144ymous_ ++B 26000,36400,300,300,CONT_DIF_P,498nymous_ ++B 31600,23000,300,300,CONT_VIA2,659nymous_ ++B 32800,27000,300,300,CONT_VIA2,713nymous_ ++B 34000,19200,300,300,CONT_BODY_N,767nymous_ ++B 36000,27000,300,300,CONT_VIA2,821nymous_ ++B 37000,32000,300,300,CONT_DIF_P,875nymous_ ++B 4400,27000,300,300,CONT_VIA,929nymous_ ++B 14000,21800,300,300,CONT_POLY,1197ymous_ ++B 5600,11800,300,300,CONT_DIF_P,983nymous_ ++B 7600,24000,300,300,CONT_VIA2,1037ymous_ ++B 17400,11800,300,300,CONT_POLY,1305ymous_ ++B 15600,36000,300,300,CONT_DIF_N,1251ymous_ ++B 21000,14000,300,300,CONT_VIA,391nymous_ ++B 28000,24000,300,300,CONT_DIF_P,552nymous_ ++B 8600,32000,300,300,CONT_VIA2,1091ymous_ ++B 10800,24000,300,300,CONT_DIF_N,1145ymous_ ++B 18800,9000,300,300,CONT_DIF_N,1359ymous_ ++B 26000,37600,300,300,CONT_BODY_N,499nymous_ ++B 24800,6000,300,300,CONT_BODY_P,445nymous_ ++B 29600,13000,300,300,CONT_DIF_P,606nymous_ ++B 31600,27000,300,300,CONT_VIA2,660nymous_ ++B 32800,28000,300,300,CONT_VIA2,714nymous_ ++B 3400,24000,300,300,CONT_VIA2,768nymous_ ++B 36000,28000,300,300,CONT_VIA2,822nymous_ ++B 37000,32000,300,300,CONT_VIA,876nymous_ ++B 4400,28000,300,300,CONT_DIF_N,930nymous_ ++B 15600,19200,300,300,CONT_BODY_P,1252ymous_ ++B 14000,21800,300,300,CONT_VIA,1198ymous_ ++B 5600,12800,300,300,CONT_DIF_P,984nymous_ ++B 7600,25000,300,300,CONT_DIF_N,1038ymous_ ++B 18800,16000,300,300,CONT_BODY_N,1360ymous_ ++B 17600,6000,300,300,CONT_BODY_P,1306ymous_ ++B 21200,6000,300,300,CONT_BODY_P,392nymous_ ++B 28000,25200,300,300,CONT_DIF_P,553nymous_ ++B 8600,36000,300,300,CONT_VIA2,1092ymous_ ++B 10800,25000,300,300,CONT_DIF_N,1146ymous_ ++B 26000,6000,300,300,CONT_BODY_P,500nymous_ ++B 24800,6000,300,300,CONT_VIA,446nymous_ ++B 29600,14000,300,300,CONT_DIF_P,607nymous_ ++B 31600,28000,300,300,CONT_VIA2,661nymous_ ++B 3400,25000,300,300,CONT_VIA2,769nymous_ ++B 32800,29000,300,300,CONT_VIA2,715nymous_ ++B 36000,29000,300,300,CONT_VIA2,823nymous_ ++B 37000,33000,300,300,CONT_DIF_P,877nymous_ ++B 4400,28000,300,300,CONT_VIA,931nymous_ ++B 5600,13800,300,300,CONT_DIF_P,985nymous_ ++B 15800,27000,300,300,CONT_VIA2,1253ymous_ ++B 14000,21800,300,300,CONT_VIA2,1199ymous_ ++B 7600,25000,300,300,CONT_VIA,1039ymous_ ++B 8600,19200,300,300,CONT_BODY_P,1093ymous_ ++B 18800,17000,300,300,CONT_VIA,1361ymous_ ++B 17600,6000,300,300,CONT_VIA,1307ymous_ ++B 24800,6000,300,300,CONT_VIA2,447nymous_ ++B 21200,6000,300,300,CONT_VIA,393nymous_ ++B 28000,26400,300,300,CONT_DIF_P,554nymous_ ++B 29600,16000,300,300,CONT_BODY_N,608nymous_ ++B 10800,26000,300,300,CONT_DIF_N,1147ymous_ ++B 26000,6000,300,300,CONT_VIA,501nymous_ ++B 31600,29000,300,300,CONT_VIA2,662nymous_ ++B 32800,33000,300,300,CONT_VIA2,716nymous_ ++B 3400,26000,300,300,CONT_VIA2,770nymous_ ++B 36000,33000,300,300,CONT_VIA2,824nymous_ ++B 37000,33000,300,300,CONT_VIA,878nymous_ ++B 14000,23000,300,300,CONT_DIF_N,1200ymous_ ++B 4400,29000,300,300,CONT_DIF_N,932nymous_ ++B 5600,16000,300,300,CONT_BODY_N,986nymous_ ++B 17600,6000,300,300,CONT_VIA2,1308ymous_ ++B 15800,28000,300,300,CONT_VIA2,1254ymous_ ++B 7600,25000,300,300,CONT_VIA2,1040ymous_ ++B 8800,37600,300,300,CONT_BODY_P,1094ymous_ ++B 18800,17000,300,300,CONT_VIA2,1362ymous_ ++B 24800,8000,300,300,CONT_DIF_N,448nymous_ ++B 21200,6000,300,300,CONT_VIA2,394nymous_ ++B 28000,27600,300,300,CONT_DIF_P,555nymous_ ++B 29600,17000,300,300,CONT_VIA,609nymous_ ++B 10800,27000,300,300,CONT_DIF_N,1148ymous_ ++B 26000,6000,300,300,CONT_VIA2,502nymous_ ++B 31600,33000,300,300,CONT_VIA2,663nymous_ ++B 32800,34000,300,300,CONT_VIA2,717nymous_ ++B 3400,30000,300,300,CONT_VIA2,771nymous_ ++B 36000,34000,300,300,CONT_VIA2,825nymous_ ++B 37000,33000,300,300,CONT_VIA2,879nymous_ ++B 4400,29000,300,300,CONT_VIA,933nymous_ ++B 14000,24000,300,300,CONT_DIF_N,1201ymous_ ++B 5600,17000,300,300,CONT_VIA,987nymous_ ++B 7600,26000,300,300,CONT_DIF_N,1041ymous_ ++B 17600,8600,300,300,CONT_DIF_N,1309ymous_ ++B 15800,29000,300,300,CONT_VIA2,1255ymous_ ++B 21200,9000,300,300,CONT_DIF_N,395nymous_ ++B 28000,28800,300,300,CONT_DIF_P,556nymous_ ++B 8800,37600,300,300,CONT_VIA,1095ymous_ ++B 10800,28000,300,300,CONT_DIF_N,1149ymous_ ++B 19600,19200,300,300,CONT_BODY_P,1363ymous_ ++B 26000,8000,300,300,CONT_DIF_N,503nymous_ ++B 24800,13000,300,300,CONT_DIF_P,449nymous_ ++B 29600,17000,300,300,CONT_VIA2,610nymous_ ++B 31600,34000,300,300,CONT_VIA2,664nymous_ ++B 32800,35000,300,300,CONT_VIA2,718nymous_ ++B 3400,31000,300,300,CONT_VIA2,772nymous_ ++B 36000,35000,300,300,CONT_VIA2,826nymous_ ++B 37000,34000,300,300,CONT_DIF_P,880nymous_ ++B 4400,30000,300,300,CONT_DIF_N,934nymous_ ++B 15800,37600,300,300,CONT_BODY_P,1256ymous_ ++B 14000,25000,300,300,CONT_DIF_N,1202ymous_ ++B 5600,17000,300,300,CONT_VIA2,988nymous_ ++B 7600,26000,300,300,CONT_VIA,1042ymous_ ++B 19800,22600,300,300,CONT_POLY,1364ymous_ ++B 17600,12800,300,300,CONT_DIF_P,1310ymous_ ++B 21200,16000,300,300,CONT_BODY_N,396nymous_ ++B 28000,30000,300,300,CONT_DIF_P,557nymous_ ++B 8800,37600,300,300,CONT_VIA2,1096ymous_ ++B 10800,29000,300,300,CONT_DIF_N,1150ymous_ ++B 26000,12000,300,300,CONT_VIA2,504nymous_ ++B 24800,13000,300,300,CONT_VIA,450nymous_ ++B 3600,37600,300,300,CONT_BODY_P,828nymous_ ++B 3400,36000,300,300,CONT_VIA2,774nymous_ ++B 33200,6000,300,300,CONT_BODY_P,720nymous_ ++B 31800,9000,300,300,CONT_POLY,666nymous_ ++B 26000,13000,300,300,CONT_DIF_P,505nymous_ ++B 10800,30000,300,300,CONT_DIF_N,1151ymous_ ++B 30000,0,300,300,CONT_VIA3,612nymous_ ++B 28000,31200,300,300,CONT_DIF_P,558nymous_ ++B 9200,24000,300,300,CONT_DIF_N,1098ymous_ ++B 7600,27000,300,300,CONT_DIF_N,1044ymous_ ++B 1600,21400,300,300,CONT_BODY_P,1258ymous_ ++B 17600,17000,300,300,CONT_VIA,1312ymous_ ++B 6000,23000,300,300,CONT_DIF_N,990nymous_ ++B 4400,30000,300,300,CONT_VIA2,936nymous_ ++B 14000,27000,300,300,CONT_DIF_N,1204ymous_ ++B 37000,34000,300,300,CONT_VIA2,882nymous_ ++B 30000,0,300,300,CONT_VIA2,611nymous_ ++B 31600,35000,300,300,CONT_VIA2,665nymous_ ++B 3400,32000,300,300,CONT_VIA2,773nymous_ ++B 33000,19200,300,300,CONT_BODY_N,719nymous_ ++B 36000,19200,300,300,CONT_BODY_N,827nymous_ ++B 37000,34000,300,300,CONT_VIA,881nymous_ ++B 4400,30000,300,300,CONT_VIA,935nymous_ ++B 5600,19200,300,300,CONT_BODY_P,989nymous_ ++B 1600,20400,300,300,CONT_BODY_P,1257ymous_ ++B 14000,26000,300,300,CONT_DIF_N,1203ymous_ ++B 7600,26000,300,300,CONT_VIA2,1043ymous_ ++B 9200,23000,300,300,CONT_DIF_N,1097ymous_ ++B 19800,26200,300,300,CONT_POLY,1365ymous_ ++B 17600,16000,300,300,CONT_BODY_N,1311ymous_ ++B 24800,14000,300,300,CONT_DIF_P,451nymous_ ++B 22000,22200,300,300,CONT_VIA,397nymous_ ++B 19800,27400,300,300,CONT_POLY,1366ymous_ ++B 24800,14000,300,300,CONT_VIA,452nymous_ ++B 22000,19200,300,300,CONT_VIA,398nymous_ ++B 28000,31200,300,300,CONT_VIA,559nymous_ ++B 30000,0,300,300,CONT_VIA4,613nymous_ ++B 10800,31000,300,300,CONT_DIF_N,1152ymous_ ++B 26000,13000,300,300,CONT_VIA2,506nymous_ ++B 31800,12200,300,300,CONT_POLY,667nymous_ ++B 33200,6000,300,300,CONT_VIA,721nymous_ ++B 34400,6000,300,300,CONT_BODY_P,775nymous_ ++B 3600,37600,300,300,CONT_VIA,829nymous_ ++B 37000,35000,300,300,CONT_DIF_P,883nymous_ ++B 4400,31000,300,300,CONT_DIF_N,937nymous_ ++B 14000,28000,300,300,CONT_DIF_N,1205ymous_ ++B 6000,24000,300,300,CONT_DIF_N,991nymous_ ++B 7600,27000,300,300,CONT_VIA,1045ymous_ ++B 17600,17000,300,300,CONT_VIA2,1313ymous_ ++B 1600,22400,300,300,CONT_BODY_P,1259ymous_ ++B 22400,6000,300,300,CONT_BODY_P,399nymous_ ++B 28000,32400,300,300,CONT_DIF_P,560nymous_ ++B 9200,25000,300,300,CONT_DIF_N,1099ymous_ ++B 10800,32000,300,300,CONT_DIF_N,1153ymous_ ++B 19800,28200,300,300,CONT_VIA,1367ymous_ ++B 26000,14000,300,300,CONT_DIF_P,507nymous_ ++B 24800,16000,300,300,CONT_BODY_N,453nymous_ ++B 30000,20200,300,300,CONT_VIA,614nymous_ ++B 32000,6000,300,300,CONT_BODY_P,668nymous_ ++B 33200,6000,300,300,CONT_VIA2,722nymous_ ++B 34400,6000,300,300,CONT_VIA,776nymous_ ++B 3600,37600,300,300,CONT_VIA2,830nymous_ ++B 37000,35000,300,300,CONT_VIA,884nymous_ ++B 4400,31000,300,300,CONT_VIA,938nymous_ ++B 1600,23400,300,300,CONT_BODY_P,1260ymous_ ++B 14000,29000,300,300,CONT_DIF_N,1206ymous_ ++B 6000,25000,300,300,CONT_DIF_N,992nymous_ ++B 7600,28000,300,300,CONT_DIF_N,1046ymous_ ++B 19800,31000,300,300,CONT_POLY,1368ymous_ ++B 17600,19200,300,300,CONT_BODY_P,1314ymous_ ++B 22400,6000,300,300,CONT_VIA,400nymous_ ++B 28000,33600,300,300,CONT_DIF_P,561nymous_ ++B 9200,26000,300,300,CONT_DIF_N,1100ymous_ ++B 10800,33000,300,300,CONT_DIF_N,1154ymous_ ++B 26000,14000,300,300,CONT_VIA2,508nymous_ ++B 25000,20400,300,300,CONT_DIF_P,454nymous_ ++B 30000,19200,300,300,CONT_BODY_N,615nymous_ ++B 32000,6000,300,300,CONT_VIA,669nymous_ ++B 34400,6000,300,300,CONT_VIA2,777nymous_ ++B 33200,8000,300,300,CONT_DIF_N,723nymous_ ++B 3600,19200,300,300,CONT_BODY_P,831nymous_ ++B 37000,35000,300,300,CONT_VIA2,885nymous_ ++B 4400,31000,300,300,CONT_VIA2,939nymous_ ++B 6000,26000,300,300,CONT_DIF_N,993nymous_ ++B 1600,24400,300,300,CONT_BODY_P,1261ymous_ ++B 14000,30000,300,300,CONT_DIF_N,1207ymous_ ++B 33800,22000,300,300,CONT_VIA2,731nymous_ ++B 7600,28000,300,300,CONT_VIA,1047ymous_ ++B 9200,27000,300,300,CONT_DIF_N,1101ymous_ ++B 19800,35200,300,300,CONT_VIA,1369ymous_ ++B 17800,23200,300,300,CONT_DIF_N,1315ymous_ ++B 25000,20400,300,300,CONT_VIA,455nymous_ ++B 22400,6000,300,300,CONT_VIA2,401nymous_ ++B 28000,35000,300,300,CONT_DIF_P,562nymous_ ++B 30400,36600,300,300,CONT_POLY,616nymous_ ++B 10800,34000,300,300,CONT_DIF_N,1155ymous_ ++B 26000,16000,300,300,CONT_BODY_N,509nymous_ ++B 32000,6000,300,300,CONT_VIA2,670nymous_ ++B 33200,13000,300,300,CONT_DIF_P,724nymous_ ++B 34400,8000,300,300,CONT_DIF_N,778nymous_ ++B 36800,6000,300,300,CONT_BODY_P,832nymous_ ++B 37000,36000,300,300,CONT_DIF_P,886nymous_ ++B 14000,31000,300,300,CONT_DIF_N,1208ymous_ ++B 4400,32000,300,300,CONT_DIF_N,940nymous_ ++B 6000,27000,300,300,CONT_DIF_N,994nymous_ ++B 17800,23200,300,300,CONT_VIA,1316ymous_ ++B 1600,25400,300,300,CONT_BODY_P,1262ymous_ ++B 7600,29000,300,300,CONT_DIF_N,1048ymous_ ++B 9200,28000,300,300,CONT_DIF_N,1102ymous_ ++B 19800,37600,300,300,CONT_BODY_P,1370ymous_ ++B 25000,21600,300,300,CONT_DIF_P,456nymous_ ++B 22400,8600,300,300,CONT_DIF_N,402nymous_ ++B 28000,19200,300,300,CONT_BODY_N,563nymous_ ++B 30400,36600,300,300,CONT_VIA,617nymous_ ++B 10800,35000,300,300,CONT_DIF_N,1156ymous_ ++B 26000,17000,300,300,CONT_VIA,510nymous_ ++B 32000,8000,300,300,CONT_DIF_N,671nymous_ ++B 33200,14000,300,300,CONT_DIF_P,725nymous_ ++B 34400,13000,300,300,CONT_DIF_P,779nymous_ ++B 36800,6000,300,300,CONT_VIA,833nymous_ ++B 37000,36000,300,300,CONT_VIA,887nymous_ ++B 4400,32000,300,300,CONT_VIA,941nymous_ ++B 12400,27000,300,300,CONT_DIF_N,1175ymous_ ++B 14000,32000,300,300,CONT_DIF_N,1209ymous_ ++B 6000,28000,300,300,CONT_DIF_N,995nymous_ ++B 7600,29000,300,300,CONT_VIA,1049ymous_ ++B 17800,24400,300,300,CONT_DIF_N,1317ymous_ ++B 1600,26400,300,300,CONT_BODY_P,1263ymous_ ++B 22400,16000,300,300,CONT_BODY_N,403nymous_ ++B 2800,23000,300,300,CONT_DIF_N,564nymous_ ++B 9200,29000,300,300,CONT_DIF_N,1103ymous_ ++B 10800,36000,300,300,CONT_DIF_N,1157ymous_ ++B 26000,17000,300,300,CONT_VIA2,511nymous_ ++B 25000,22800,300,300,CONT_DIF_P,457nymous_ ++B 22400,8000,200,200,CONT_TURN1,355nymous_ ++B 21200,10000,200,200,CONT_TURN1,354nymous_ ++B 30400,36600,300,300,CONT_VIA2,618nymous_ ++B 32000,13000,300,300,CONT_DIF_P,672nymous_ ++B 33200,16000,300,300,CONT_BODY_N,726nymous_ ++B 34400,13000,300,300,CONT_VIA,780nymous_ ++B 36800,6000,300,300,CONT_VIA2,834nymous_ ++B 37000,19200,300,300,CONT_BODY_N,888nymous_ ++B 4400,32000,300,300,CONT_VIA2,942nymous_ ++B 1600,27400,300,300,CONT_BODY_P,1264ymous_ ++B 14000,33000,300,300,CONT_DIF_N,1210ymous_ ++B 6000,29000,300,300,CONT_DIF_N,996nymous_ ++B 7600,30000,300,300,CONT_DIF_N,1050ymous_ ++B 17800,24400,300,300,CONT_VIA2,1318ymous_ ++B 22400,17000,300,300,CONT_VIA,404nymous_ ++B 2800,24000,300,300,CONT_DIF_N,565nymous_ ++B 9200,30000,300,300,CONT_DIF_N,1104ymous_ ++B 11600,6000,300,300,CONT_BODY_P,1158ymous_ ++B 26000,19200,300,300,CONT_BODY_N,512nymous_ ++B 25000,22800,300,300,CONT_VIA,458nymous_ ++B 27200,16000,300,300,CONT_BODY_N,541nymous_ ++B 30600,22000,300,300,CONT_DIF_P,619nymous_ ++B 32000,16000,300,300,CONT_BODY_N,673nymous_ ++B 34400,14000,300,300,CONT_DIF_P,781nymous_ ++B 33200,17000,300,300,CONT_VIA,727nymous_ ++B 36800,7000,300,300,CONT_BODY_P,835nymous_ ++B 37200,37600,300,300,CONT_BODY_N,889nymous_ ++B 4400,33000,300,300,CONT_DIF_N,943nymous_ ++B 6000,30000,300,300,CONT_DIF_N,997nymous_ ++B 1600,28400,300,300,CONT_BODY_P,1265ymous_ ++B 14000,34000,300,300,CONT_DIF_N,1211ymous_ ++B 7600,30000,300,300,CONT_VIA,1051ymous_ ++B 9200,31000,300,300,CONT_DIF_N,1105ymous_ ++B 17800,25600,300,300,CONT_DIF_N,1319ymous_ ++B 25000,24000,300,300,CONT_DIF_P,459nymous_ ++B 22400,17000,300,300,CONT_VIA2,405nymous_ ++B 2800,25000,300,300,CONT_DIF_N,566nymous_ ++B 30600,23000,300,300,CONT_DIF_P,620nymous_ ++B 11600,6000,300,300,CONT_VIA,1159ymous_ ++B 2600,37600,300,300,CONT_BODY_P,513nymous_ ++B 32000,17000,300,300,CONT_VIA,674nymous_ ++B 33200,17000,300,300,CONT_VIA2,728nymous_ ++B 34400,14000,300,300,CONT_VIA,782nymous_ ++B 36800,8000,300,300,CONT_BODY_P,836nymous_ ++B 38000,27000,300,300,CONT_VIA2,890nymous_ ++B 14000,35000,300,300,CONT_DIF_N,1212ymous_ ++B 4400,33000,300,300,CONT_VIA,944nymous_ ++B 6000,31000,300,300,CONT_DIF_N,998nymous_ ++B 17800,25600,300,300,CONT_VIA,1320ymous_ ++B 1600,29400,300,300,CONT_BODY_P,1266ymous_ ++B 7600,30000,300,300,CONT_VIA2,1052ymous_ ++B 9200,32000,300,300,CONT_DIF_N,1106ymous_ ++B 25000,25200,300,300,CONT_DIF_P,460nymous_ ++B 23000,20400,300,300,CONT_BODY_N,406nymous_ ++B 2800,26000,300,300,CONT_DIF_N,567nymous_ ++B 30600,24000,300,300,CONT_DIF_P,621nymous_ ++B 11600,6000,300,300,CONT_VIA2,1160ymous_ ++B 2600,19200,300,300,CONT_BODY_P,514nymous_ ++B 32000,17000,300,300,CONT_VIA2,675nymous_ ++B 33800,22000,300,300,CONT_DIF_P,729nymous_ ++B 34400,16000,300,300,CONT_BODY_N,783nymous_ ++B 36800,9000,300,300,CONT_BODY_P,837nymous_ ++B 38000,28000,300,300,CONT_VIA2,891nymous_ ++B 4400,34000,300,300,CONT_DIF_N,945nymous_ ++B 14000,36000,300,300,CONT_DIF_N,1213ymous_ ++B 6000,32000,300,300,CONT_DIF_N,999nymous_ ++B 7600,31000,300,300,CONT_DIF_N,1053ymous_ ++B 17800,25600,300,300,CONT_VIA2,1321ymous_ ++B 1600,30400,300,300,CONT_BODY_P,1267ymous_ ++B 23000,21400,300,300,CONT_BODY_N,407nymous_ ++B 2800,27000,300,300,CONT_DIF_N,568nymous_ ++B 9200,33000,300,300,CONT_DIF_N,1107ymous_ ++B 11600,8000,300,300,CONT_DIF_N,1161ymous_ ++B 27000,20400,300,300,CONT_DIF_P,515nymous_ ++B 25000,26400,300,300,CONT_DIF_P,461nymous_ ++B 30600,25000,300,300,CONT_DIF_P,622nymous_ ++B 32000,19200,300,300,CONT_BODY_N,676nymous_ ++B 33800,22000,300,300,CONT_VIA,730nymous_ ++B 34800,20200,300,300,CONT_POLY,784nymous_ ++B 36800,9000,300,300,CONT_VIA2,838nymous_ ++B 38000,29000,300,300,CONT_VIA2,892nymous_ ++B 4400,34000,300,300,CONT_VIA,946nymous_ ++EOF +diff --git a/alliance/src/cells/src/mpxlib/piot_mpx.vbe b/alliance/src/cells/src/mpxlib/piot_mpx.vbe +new file mode 100644 +index 0000000..2723794 +--- /dev/null ++++ b/alliance/src/cells/src/mpxlib/piot_mpx.vbe +@@ -0,0 +1,44 @@ ++ENTITY piot_mpx IS ++ GENERIC ( ++ CONSTANT area : NATURAL := 80000; ++ CONSTANT rup : NATURAL := 402; ++ CONSTANT rdown : NATURAL := 0 ++ ); ++ PORT ( ++ i : in BIT; ++ b : in BIT; ++ t : out BIT; ++ pad : inout MUX_BIT BUS; ++ ck : in BIT; ++ vdde : in BIT; ++ vddi : in BIT; ++ vsse : in BIT; ++ vssi : in BIT ++ ); ++END piot_mpx; ++ ++ARCHITECTURE behaviour_data_flow OF piot_mpx IS ++ SIGNAL b1 : BIT; ++ SIGNAL b2 : BIT; ++ SIGNAL b3 : BIT; ++ SIGNAL b4 : BIT; ++ SIGNAL b5 : BIT; ++ SIGNAL b6 : BIT; ++ ++BEGIN ++ b6 <= b5; ++ b5 <= b4; ++ b4 <= b3; ++ b3 <= b2; ++ b2 <= b1; ++ b1 <= b; ++ label0 : BLOCK (b6 = '1') ++ BEGIN ++ pad <= GUARDED i; ++ END BLOCK label0; ++ t <= pad; ++ ++ ASSERT ((((vddi and vdde) and not (vssi)) and not (vsse)) = '1') ++ REPORT "power supply is missing on piot_mpx" ++ SEVERITY WARNING; ++END; +diff --git a/alliance/src/cells/src/mpxlib/po_mpx.ap b/alliance/src/cells/src/mpxlib/po_mpx.ap +new file mode 100644 +index 0000000..ffb3150 +--- /dev/null ++++ b/alliance/src/cells/src/mpxlib/po_mpx.ap +@@ -0,0 +1,1536 @@ ++V ALLIANCE : 6 ++H po_mpx,P,14/9/2014,100 ++A 0,0,40000,80000 ++I 0,40000,padreal_mpx,padreal,NOSYM ++S 27800,11800,28200,11800,200,i,RIGHT,POLY ++S 28000,0,28000,0,400,i,RIGHT,CALU4 ++S 28000,0,28000,0,400,i,RIGHT,CALU5 ++S 28000,-300,28000,10900,400,i,UP,ALU2 ++S 28800,9000,29000,9000,200,i,RIGHT,POLY ++S 20000,48100,20000,71900,24400,pad,UP,CALU1 ++S 28600,25800,29000,25800,600,pad,RIGHT,POLY ++S 28600,30600,29000,30600,600,pad,RIGHT,POLY ++S 28600,31800,29000,31800,600,pad,RIGHT,POLY ++S 28600,33000,29000,33000,600,pad,RIGHT,POLY ++S 29000,25900,29000,34900,400,pad,UP,ALU1 ++S 29000,35100,29000,39700,400,pad,UP,ALU1 ++S 700,4000,39300,4000,1000,ck,RIGHT,CALU3 ++S 25100,26400,27900,26400,400,vdde,RIGHT,ALU1 ++S 25100,21600,27900,21600,400,vdde,RIGHT,ALU1 ++S 6800,22200,8400,22200,200,vdde,RIGHT,POLY ++S 700,28000,39300,28000,2400,vdde,RIGHT,CALU3 ++S 700,34000,39300,34000,2400,vdde,RIGHT,CALU3 ++S 16800,33400,17200,33400,200,vdde,RIGHT,POLY ++S 3600,22200,5200,22200,200,vdde,RIGHT,POLY ++S 700,22000,39300,22000,2400,vdde,RIGHT,CALU3 ++S 10500,21800,14300,21800,400,vdde,RIGHT,ALU2 ++S 16800,29900,16800,38300,400,vdde,UP,ALU2 ++S 16800,32200,17200,32200,200,vdde,RIGHT,POLY ++S 16800,35800,17200,35800,200,vdde,RIGHT,POLY ++S 24000,34200,24400,34200,600,vdde,RIGHT,POLY ++S 24000,35800,24400,35800,600,vdde,RIGHT,POLY ++S 25100,24000,27900,24000,400,vdde,RIGHT,ALU1 ++S 25100,28800,27900,28800,400,vdde,RIGHT,ALU1 ++S 16800,34600,17200,34600,200,vdde,RIGHT,POLY ++S 20000,9600,20000,11000,200,vddi,UP,POLY ++S 3100,16000,36900,16000,2400,vddi,RIGHT,ALU1 ++S 700,10000,39300,10000,2400,vddi,RIGHT,CALU3 ++S 700,16000,39300,16000,2400,vddi,RIGHT,CALU3 ++S 20800,22900,20800,37100,400,vsse,UP,ALU1 ++S 30400,36400,30400,36600,200,vsse,UP,POLY ++S 4400,22900,4400,37500,400,vsse,UP,ALU1 ++S 7600,22900,7600,37500,400,vsse,UP,ALU1 ++S 700,25000,39300,25000,2400,vsse,RIGHT,CALU3 ++S 700,31000,39300,31000,2400,vsse,RIGHT,CALU3 ++S 700,37000,39300,37000,2400,vsse,RIGHT,CALU3 ++S 700,19000,39300,19000,2400,vsse,RIGHT,CALU3 ++S 17800,22900,17800,31900,400,vsse,UP,ALU2 ++S 3100,6000,36900,6000,2400,vssi,RIGHT,ALU1 ++S 700,7000,39300,7000,2400,vssi,RIGHT,CALU3 ++S 700,13000,39300,13000,2400,vssi,RIGHT,CALU3 ++S 29600,9800,29600,11400,200,248nymous_,UP,POLY ++S 14600,11100,14600,13100,200,p17c,UP,PTRANS ++S 14800,22500,14800,36700,200,n15d,UP,NTRANS ++S 6200,10900,6200,14900,200,p18b,UP,PTRANS ++S 30800,8100,30800,12900,400,cnbb,UP,ALU1 ++S 30800,10600,33800,10600,200,cnbb,RIGHT,POLY ++S 6800,22500,6800,36700,200,n14c,UP,NTRANS ++S 35000,7300,35000,8300,200,n5b,UP,NTRANS ++S 35000,12700,35000,14700,200,p5b,UP,PTRANS ++S 27800,12500,27800,14500,200,p1,UP,PTRANS ++S 18800,8500,18800,9100,420,13onymous_,UP,NDIF ++S 18800,9100,18800,9900,400,12onymous_,UP,ALU1 ++S 16800,23200,16800,25400,600,52onymous_,UP,POLY ++S 16800,24100,16800,29500,400,51onymous_,UP,ALU2 ++S 16800,20900,16800,24700,400,53onymous_,UP,ALU2 ++S 18500,17000,20300,17000,400,11onymous_,RIGHT,ALU2 ++S 17500,22600,19100,22600,200,n6d,RIGHT,NTRANS ++S 26000,6100,26000,7900,400,285nymous_,UP,ALU1 ++S 26000,30900,26000,37100,400,286nymous_,UP,ALU2 ++S 12400,22700,12400,36500,620,93onymous_,UP,NDIF ++S 19800,32900,19800,35100,400,10onymous_,UP,ALU1 ++S 38200,19300,38200,37500,400,169nymous_,UP,ALU1 ++S 32200,21100,32200,36500,620,211nymous_,UP,PDIF ++S 32200,21300,32200,39700,400,210nymous_,UP,ALU1 ++S 23000,19300,23000,37500,400,321nymous_,UP,ALU1 ++S 12400,18500,12400,22100,2400,92onymous_,UP,ALU2 ++S 23000,19080,23000,37920,600,320nymous_,UP,NTIE ++S 9200,7500,9200,9100,620,127nymous_,UP,NDIF ++S 12800,7500,12800,9100,620,91onymous_,UP,NDIF ++S 23100,19200,38100,19200,400,319nymous_,RIGHT,ALU1 ++S 8900,10000,26300,10000,2400,126nymous_,RIGHT,ALU2 ++S 22880,19200,38320,19200,600,318nymous_,RIGHT,NTIE ++S 29600,7100,29600,8100,620,249nymous_,UP,NDIF ++S 12400,20700,12400,36300,400,94onymous_,UP,ALU1 ++S 8900,6000,26300,6000,400,130nymous_,RIGHT,ALU2 ++S 9200,6100,9200,7900,400,129nymous_,UP,ALU1 ++S 23000,11700,23000,17300,2000,322nymous_,UP,ALU2 ++S 25100,35000,29100,35000,400,290nymous_,RIGHT,ALU1 ++S 9200,5700,9200,11300,400,128nymous_,UP,ALU2 ++S 25400,8600,25400,12400,200,289nymous_,UP,POLY ++S 29480,37600,38520,37600,600,250nymous_,RIGHT,NTIE ++S 26000,21300,26000,24300,400,288nymous_,UP,ALU2 ++S 26000,23700,26000,29100,400,287nymous_,UP,ALU2 ++S 31400,35300,31400,36100,200,p11,UP,PTRANS ++S 17900,36400,18700,36400,400,17onymous_,RIGHT,ALU1 ++S 1800,17700,1800,38300,1600,16onymous_,UP,ALU2 ++S 16800,20300,16800,23300,400,55onymous_,UP,ALU1 ++S 3200,11100,3200,15900,400,215nymous_,UP,ALU1 ++S 36800,10880,36800,16120,600,173nymous_,UP,NTIE ++S 16500,21200,25300,21200,400,54onymous_,RIGHT,ALU2 ++S 3200,10880,3200,16120,600,214nymous_,UP,NTIE ++S 37000,21100,37000,36500,620,172nymous_,UP,PDIF ++S 22400,8500,22400,9100,620,325nymous_,UP,NDIF ++S 2900,15400,19300,15400,1200,213nymous_,RIGHT,ALU2 ++S 37000,17700,37000,38300,2400,170nymous_,UP,ALU2 ++S 23100,37600,27700,37600,400,323nymous_,RIGHT,ALU1 ++S 2900,17000,19100,17000,400,212nymous_,RIGHT,ALU2 ++S 22100,17000,23700,17000,400,324nymous_,RIGHT,ALU2 ++S 37000,21300,37000,36300,400,171nymous_,UP,ALU1 ++S 16500,20200,24300,20200,400,56onymous_,RIGHT,ALU2 ++S 16400,12100,16400,15900,400,57onymous_,UP,ALU1 ++S 16400,11300,16400,12900,620,58onymous_,UP,PDIF ++S 18400,10100,18400,12700,400,14onymous_,UP,ALU1 ++S 18200,9600,21800,9600,200,15onymous_,RIGHT,POLY ++S 31400,20900,31400,34300,200,p14a,UP,PTRANS ++S 16400,7500,16400,9100,620,59onymous_,UP,NDIF ++S 36800,5880,36800,8720,600,177nymous_,UP,PTIE ++S 24900,36400,28100,36400,620,294nymous_,RIGHT,PDIF ++S 36800,6100,36800,9100,400,176nymous_,UP,ALU1 ++S 22000,17900,22000,19500,400,329nymous_,UP,ALU2 ++S 24800,7500,24800,8100,620,293nymous_,UP,NDIF ++S 2900,6000,7100,6000,400,217nymous_,RIGHT,ALU2 ++S 900,37000,8900,37000,2400,97onymous_,RIGHT,ALU2 ++S 36800,6900,36800,17300,400,175nymous_,UP,ALU2 ++S 21700,18200,25100,18200,400,328nymous_,RIGHT,ALU2 ++S 24800,8100,24800,13900,400,292nymous_,UP,ALU1 ++S 2900,10000,6300,10000,2400,216nymous_,RIGHT,ALU2 ++S 36800,11100,36800,15900,400,174nymous_,UP,ALU1 ++S 9200,22700,9200,36500,620,131nymous_,UP,NDIF ++S 9200,20700,9200,36300,400,132nymous_,UP,ALU1 ++S 12200,9600,12200,10800,200,95onymous_,UP,POLY ++S 22400,8100,22400,8500,400,326nymous_,UP,ALU1 ++S 8600,9600,8600,10600,200,133nymous_,UP,POLY ++S 22000,19300,22000,22100,400,327nymous_,UP,ALU1 ++S 900,19000,9300,19000,2400,96onymous_,RIGHT,ALU2 ++S 16400,6100,16400,8900,400,60onymous_,UP,ALU1 ++S 16400,29900,16400,32300,400,61onymous_,UP,ALU2 ++S 24800,13100,24800,14500,620,291nymous_,UP,PDIF ++S 28700,18200,34700,18200,400,253nymous_,RIGHT,ALU2 ++S 29000,18300,29000,19500,400,252nymous_,UP,ALU2 ++S 29300,37000,31900,37000,2400,251nymous_,RIGHT,ALU2 ++S 7400,7300,7400,9300,200,n18c,UP,NTRANS ++S 7400,10900,7400,14900,200,p18c,UP,PTRANS ++S 20000,8500,20000,9100,620,pad2,UP,NDIF ++S 2700,20600,15700,20600,400,pad2,RIGHT,ALU1 ++S 2900,20600,15500,20600,400,pad2,RIGHT,ALU1 ++S 17900,31600,18700,31600,400,19onymous_,RIGHT,ALU1 ++S 17900,34000,18700,34000,400,18onymous_,RIGHT,ALU1 ++S 1600,19080,1600,37720,600,62onymous_,UP,PTIE ++S 21200,9100,21200,9900,400,331nymous_,UP,ALU1 ++S 3200,5880,3200,8720,600,220nymous_,UP,PTIE ++S 8000,8100,8000,8900,400,136nymous_,UP,ALU1 ++S 36700,37600,38100,37600,400,178nymous_,RIGHT,ALU1 ++S 11600,7500,11600,9100,420,100nymous_,UP,NDIF ++S 24900,35000,28100,35000,820,295nymous_,RIGHT,PDIF ++S 3200,6100,3200,9100,400,219nymous_,UP,ALU1 ++S 8000,11100,8000,13700,400,135nymous_,UP,ALU1 ++S 11600,11100,11600,14700,620,99onymous_,UP,PDIF ++S 22000,21900,22000,28500,400,330nymous_,UP,ALU2 ++S 3200,5700,3200,16100,400,218nymous_,UP,ALU2 ++S 8000,11100,8000,14700,620,134nymous_,UP,PDIF ++S 11600,11900,11600,15900,400,98onymous_,UP,ALU1 ++S 29000,8600,29000,9000,200,256nymous_,UP,POLY ++S 29000,11400,29000,12200,200,255nymous_,UP,POLY ++S 28700,24600,30300,24600,400,257nymous_,RIGHT,ALU2 ++S 11600,6100,11600,8900,400,101nymous_,UP,ALU1 ++S 8000,7500,8000,9100,420,137nymous_,UP,NDIF ++S 21200,8500,21200,9100,420,332nymous_,UP,NDIF ++S 3480,16000,36920,16000,600,179nymous_,RIGHT,NTIE ++S 20800,19080,20800,37720,600,333nymous_,UP,PTIE ++S 3600,22200,5200,22200,200,180nymous_,RIGHT,POLY ++S 1600,19300,1600,37500,400,63onymous_,UP,ALU1 ++S 3600,22500,3600,36700,200,n14a,UP,NTRANS ++S 20600,8300,20600,9300,200,n16c,UP,NTRANS ++S 1480,19200,20920,19200,600,64onymous_,RIGHT,PTIE ++S 1700,19200,20700,19200,400,65onymous_,RIGHT,ALU1 ++S 17900,30400,18700,30400,400,20onymous_,RIGHT,ALU1 ++S 15800,11100,15800,13100,200,p17d,UP,PTRANS ++S 17900,28000,18700,28000,400,21onymous_,RIGHT,ALU1 ++S 15800,7300,15800,9300,200,n17d,UP,NTRANS ++S 29000,11400,32600,11400,200,254nymous_,RIGHT,POLY ++S 32000,12900,32000,14500,620,221nymous_,UP,PDIF ++S 24900,32400,28100,32400,420,297nymous_,RIGHT,PDIF ++S 11600,22500,11600,36700,200,n15b,UP,NTRANS ++S 32000,8100,32000,12900,400,222nymous_,UP,ALU1 ++S 7600,22700,7600,38300,2400,138nymous_,UP,ALU2 ++S 24900,31200,28100,31200,420,298nymous_,RIGHT,PDIF ++S 11000,10900,11000,14900,200,p18f,UP,PTRANS ++S 7600,22900,7600,37500,400,139nymous_,UP,ALU1 ++S 24900,30000,28100,30000,420,299nymous_,RIGHT,PDIF ++S 20800,19300,20800,37500,400,334nymous_,UP,ALU1 ++S 11000,9600,11000,10600,200,102nymous_,UP,POLY ++S 7600,22700,7600,36500,620,140nymous_,UP,NDIF ++S 11000,7300,11000,9300,200,n18f,UP,NTRANS ++S 36000,20200,36000,20600,600,181nymous_,UP,POLY ++S 7300,21800,10100,21800,400,141nymous_,RIGHT,ALU2 ++S 20000,12700,20000,17300,400,335nymous_,UP,ALU2 ++S 10800,22900,10800,39700,400,103nymous_,UP,ALU1 ++S 35300,17000,37100,17000,400,182nymous_,RIGHT,ALU2 ++S 20000,11100,20000,15900,400,336nymous_,UP,ALU1 ++S 1700,37600,9500,37600,400,66onymous_,RIGHT,ALU1 ++S 35600,13100,35600,15900,400,183nymous_,UP,ALU1 ++S 20000,6300,20000,8500,400,337nymous_,UP,ALU1 ++S 15800,9600,15800,10800,200,67onymous_,UP,POLY ++S 17900,26800,18700,26800,400,22onymous_,RIGHT,ALU1 ++S 25000,20100,25000,23100,400,cn,UP,ALU2 ++S 25100,20400,27900,20400,400,cn,RIGHT,ALU1 ++S 25100,22800,27900,22800,400,cn,RIGHT,ALU1 ++S 4100,21800,7900,21800,400,cn,RIGHT,ALU2 ++S 10000,22200,11600,22200,200,cn,RIGHT,POLY ++S 13200,22200,14800,22200,200,cn,RIGHT,POLY ++S 25100,25200,27900,25200,400,fbul,RIGHT,ALU1 ++S 25100,37000,27900,37000,1600,fbul,RIGHT,ALU1 ++S 36200,20900,36200,36700,200,p14d,UP,PTRANS ++S 28400,14100,28400,15900,400,258nymous_,UP,ALU1 ++S 24900,33600,28100,33600,420,296nymous_,RIGHT,PDIF ++S 17900,25600,18700,25600,400,23onymous_,RIGHT,ALU1 ++S 17900,24400,18700,24400,400,24onymous_,RIGHT,ALU1 ++S 17900,23200,18700,23200,400,25onymous_,RIGHT,ALU1 ++S 25100,31200,27900,31200,400,node_cp,RIGHT,ALU1 ++S 25100,33600,27900,33600,400,node_cp,RIGHT,ALU1 ++S 28000,24300,28000,31500,400,node_cp,UP,ALU2 ++S 27700,24600,29300,24600,400,node_cp,RIGHT,ALU2 ++S 28600,24600,29000,24600,600,node_cp,RIGHT,POLY ++S 31400,20600,33000,20600,200,node_cp,RIGHT,POLY ++S 34600,20600,36200,20600,200,node_cp,RIGHT,POLY ++S 17900,32800,19700,32800,400,node_cp,RIGHT,ALU1 ++S 17900,35200,19700,35200,400,node_cp,RIGHT,ALU1 ++S 19500,36800,26300,36800,400,node_cp,RIGHT,ALU2 ++S 20000,40100,20000,59900,4400,338nymous_,UP,ALU1 ++S 35600,7500,35600,8100,620,185nymous_,UP,NDIF ++S 7400,9600,7400,10600,200,143nymous_,UP,POLY ++S 35600,12900,35600,14500,620,184nymous_,UP,PDIF ++S 10800,21800,10800,22200,600,105nymous_,UP,POLY ++S 24900,25200,28100,25200,420,303nymous_,RIGHT,PDIF ++S 10800,22700,10800,36500,620,104nymous_,UP,NDIF ++S 7600,21800,7600,22200,600,142nymous_,UP,POLY ++S 24900,26400,28100,26400,420,302nymous_,RIGHT,PDIF ++S 31800,12000,31800,12200,200,226nymous_,UP,POLY ++S 24900,27600,28100,27600,420,301nymous_,RIGHT,PDIF ++S 31700,6000,37100,6000,400,225nymous_,RIGHT,ALU2 ++S 24900,28800,28100,28800,420,300nymous_,RIGHT,PDIF ++S 32000,7500,32000,8100,620,224nymous_,UP,NDIF ++S 28300,9000,28700,9000,400,262nymous_,RIGHT,ALU1 ++S 31700,7600,37100,7600,1200,223nymous_,RIGHT,ALU2 ++S 28400,7500,28400,8100,620,261nymous_,UP,NDIF ++S 28500,8000,30700,8000,400,260nymous_,RIGHT,ALU1 ++S 29000,7300,29000,8300,200,n1,UP,NTRANS ++S 25000,27300,25000,32700,400,cpd,UP,ALU2 ++S 25100,27600,27900,27600,400,cpd,RIGHT,ALU1 ++S 25100,30000,27900,30000,400,cpd,RIGHT,ALU1 ++S 25100,32400,27900,32400,400,cpd,RIGHT,ALU1 ++S 18800,21900,18800,36700,400,cpd,UP,ALU2 ++S 18500,31600,25300,31600,400,cpd,RIGHT,ALU2 ++S 21800,8300,21800,9300,200,n16d,UP,NTRANS ++S 28400,12700,28400,14300,620,259nymous_,UP,PDIF ++S 7000,6900,7000,14300,400,144nymous_,UP,ALU2 ++S 35600,6100,35600,7900,400,186nymous_,UP,ALU1 ++S 25700,15400,28900,15400,1200,339nymous_,RIGHT,ALU2 ++S 35100,13000,37100,13000,2400,187nymous_,RIGHT,ALU2 ++S 6800,12100,6800,15900,400,145nymous_,UP,ALU1 ++S 26700,13000,33700,13000,2400,340nymous_,RIGHT,ALU2 ++S 17900,22000,18700,22000,400,26onymous_,RIGHT,ALU1 ++S 17700,12800,18300,12800,400,27onymous_,RIGHT,ALU1 ++S 17600,12500,17600,12900,620,28onymous_,UP,PDIF ++S 29000,12500,29000,14500,200,p2,UP,PTRANS ++S 25400,7300,25400,8300,200,n4b,UP,NTRANS ++S 24900,22800,28100,22800,420,305nymous_,RIGHT,PDIF ++S 10700,39600,35500,39600,2400,106nymous_,RIGHT,ALU1 ++S 24900,24000,28100,24000,420,304nymous_,RIGHT,PDIF ++S 31600,20200,31600,20600,600,227nymous_,UP,POLY ++S 2800,22700,2800,36500,620,265nymous_,UP,NDIF ++S 2200,13600,37800,13600,6800,264nymous_,RIGHT,NWELL ++S 28200,9100,28200,11700,400,263nymous_,UP,ALU1 ++S 12200,7300,12200,9300,200,n17a,UP,NTRANS ++S 8600,10900,8600,14900,200,p18d,UP,PTRANS ++S 24000,27000,24400,27000,600,cpb,RIGHT,POLY ++S 24000,28200,24400,28200,600,cpb,RIGHT,POLY ++S 24800,12700,24800,18500,400,cpb,UP,ALU2 ++S 19400,22600,19800,22600,200,cpb,RIGHT,POLY ++S 19400,26200,19800,26200,200,cpb,RIGHT,POLY ++S 24000,29200,24400,29200,600,cpb,RIGHT,POLY ++S 19400,27400,19800,27400,200,cpb,RIGHT,POLY ++S 19400,31000,19800,31000,200,cpb,RIGHT,POLY ++S 19800,22700,19800,30900,400,cpb,UP,ALU1 ++S 19500,28200,24300,28200,400,cpb,RIGHT,ALU2 ++S 8600,7300,8600,9300,200,n18d,UP,NTRANS ++S 8400,22500,8400,36700,200,n14d,UP,NTRANS ++S 10400,11100,10400,14700,620,107nymous_,UP,PDIF ++S 24900,21600,28100,21600,420,306nymous_,RIGHT,PDIF ++S 15800,23700,15800,32300,400,68onymous_,UP,ALU2 ++S 24900,20400,28100,20400,620,307nymous_,RIGHT,PDIF ++S 35400,21300,35400,39700,400,188nymous_,UP,ALU1 ++S 6800,11100,6800,14700,620,146nymous_,UP,PDIF ++S 35400,21100,35400,36500,620,189nymous_,UP,PDIF ++S 6900,10000,12700,10000,400,147nymous_,RIGHT,ALU1 ++S 6800,7500,6800,9100,620,148nymous_,UP,NDIF ++S 6800,6100,6800,7900,400,149nymous_,UP,ALU1 ++S 34800,20200,34800,20600,600,190nymous_,UP,POLY ++S 17600,8500,17600,9100,620,29onymous_,UP,NDIF ++S 17600,8100,17600,8500,400,30onymous_,UP,ALU1 ++S 17700,8000,22300,8000,400,31onymous_,RIGHT,ALU1 ++S 32600,7300,32600,8300,200,n0,UP,NTRANS ++S 25400,12700,25400,14700,200,p4b,UP,PTRANS ++S 2800,20500,2800,36300,400,266nymous_,UP,ALU1 ++S 31400,19100,31400,28300,400,228nymous_,UP,ALU2 ++S 18200,8300,18200,9300,200,n16a,UP,NTRANS ++S 12200,11100,12200,13100,200,p17a,UP,PTRANS ++S 12200,10000,16400,10000,600,nnt,RIGHT,POLY ++S 10400,11100,10400,13700,400,108nymous_,UP,ALU1 ++S 30700,10000,36100,10000,2400,229nymous_,RIGHT,ALU2 ++S 15600,22700,15600,36500,620,69onymous_,UP,NDIF ++S 10400,8100,10400,8900,400,109nymous_,UP,ALU1 ++S 30700,6000,32300,6000,400,230nymous_,RIGHT,ALU2 ++S 15600,20700,15600,36300,400,70onymous_,UP,ALU1 ++S 10100,7600,27300,7600,1200,110nymous_,RIGHT,ALU2 ++S 34400,13100,34400,14500,620,191nymous_,UP,PDIF ++S 6200,9600,6200,10600,200,150nymous_,UP,POLY ++S 17700,36400,18900,36400,620,32onymous_,RIGHT,NDIF ++S 34400,8100,34400,13900,400,192nymous_,UP,ALU1 ++S 17700,22000,18900,22000,620,44onymous_,RIGHT,NDIF ++S 17700,35200,18900,35200,620,33onymous_,RIGHT,NDIF ++S 6000,22700,6000,36500,620,151nymous_,UP,NDIF ++S 34400,7500,34400,8100,620,193nymous_,UP,NDIF ++S 17400,11800,17400,12000,200,45onymous_,UP,POLY ++S 17700,34000,18900,34000,620,34onymous_,RIGHT,NDIF ++S 3280,6000,28520,6000,600,194nymous_,RIGHT,PTIE ++S 25400,10600,27200,10600,200,cpbb,RIGHT,POLY ++S 27200,8100,27200,12900,400,cpbb,UP,ALU1 ++S 24200,12400,25400,12400,200,308nymous_,RIGHT,POLY ++S 24200,8600,25400,8600,200,309nymous_,RIGHT,POLY ++S 24000,18900,24000,20500,400,310nymous_,UP,ALU2 ++S 24000,33900,24000,36100,400,311nymous_,UP,ALU2 ++S 16800,28200,16800,29800,600,48onymous_,UP,POLY ++S 16900,29200,18700,29200,400,47onymous_,RIGHT,ALU1 ++S 32600,12700,32600,14700,200,p0,UP,PTRANS ++S 33000,20900,33000,36700,200,p14b,UP,PTRANS ++S 23600,13100,23600,15900,400,313nymous_,UP,ALU1 ++S 24000,27100,24000,29100,400,312nymous_,UP,ALU1 ++S 31000,5700,31000,11300,400,231nymous_,UP,ALU2 ++S 15200,11300,15200,12900,620,71onymous_,UP,PDIF ++S 10400,7500,10400,9100,420,111nymous_,UP,NDIF ++S 30800,13100,30800,13900,400,232nymous_,UP,ALU1 ++S 27800,11800,27800,12400,200,268nymous_,UP,POLY ++S 15200,11100,15200,12500,400,72onymous_,UP,ALU1 ++S 700,34000,16100,34000,2400,112nymous_,RIGHT,ALU2 ++S 30800,12700,30800,14300,620,233nymous_,UP,PDIF ++S 15200,8100,15200,8900,400,73onymous_,UP,ALU1 ++S 27800,9800,32600,9800,200,269nymous_,RIGHT,POLY ++S 27800,8600,27800,9800,200,270nymous_,UP,POLY ++S 30800,7500,30800,8100,620,234nymous_,UP,NDIF ++S 700,31000,8900,31000,2400,113nymous_,RIGHT,ALU2 ++S 6000,20700,6000,36300,400,152nymous_,UP,ALU1 ++S 700,28000,15100,28000,2400,114nymous_,RIGHT,ALU2 ++S 17400,11100,17400,11700,400,46onymous_,UP,ALU1 ++S 17700,32800,18900,32800,620,35onymous_,RIGHT,NDIF ++S 34000,18200,34000,38200,10400,195nymous_,UP,NWELL ++S 17700,31600,18900,31600,620,36onymous_,RIGHT,NDIF ++S 33800,19100,33800,38300,2400,196nymous_,UP,ALU2 ++S 17700,30400,18900,30400,620,37onymous_,RIGHT,NDIF ++S 33800,12400,35000,12400,200,197nymous_,RIGHT,POLY ++S 17700,25600,18900,25600,620,41onymous_,RIGHT,NDIF ++S 24200,7300,24200,8300,200,n4a,UP,NTRANS ++S 33800,8600,33800,12400,200,199nymous_,UP,POLY ++S 17700,26800,18900,26800,620,40onymous_,RIGHT,NDIF ++S 16800,25500,16800,28100,400,49onymous_,UP,ALU1 ++S 23700,19200,29300,19200,400,cnb,RIGHT,ALU2 ++S 28600,21000,29000,21000,600,cnb,RIGHT,POLY ++S 28600,22200,29000,22200,600,cnb,RIGHT,POLY ++S 28600,23400,29000,23400,600,cnb,RIGHT,POLY ++S 29000,17900,29000,23700,400,cnb,UP,ALU2 ++S 34400,12700,34400,18500,400,cnb,UP,ALU2 ++S 16800,23800,17200,23800,200,cnb,RIGHT,POLY ++S 16800,25000,17200,25000,200,cnb,RIGHT,POLY ++S 16800,28600,17200,28600,200,cnb,RIGHT,POLY ++S 16800,29800,17200,29800,200,cnb,RIGHT,POLY ++S 23600,7500,23600,8100,620,315nymous_,UP,NDIF ++S 17000,12300,17000,13100,200,p16,UP,PTRANS ++S 23600,12900,23600,14500,620,314nymous_,UP,PDIF ++S 33800,21300,33800,36300,400,200nymous_,UP,ALU1 ++S 19400,8300,19400,9300,200,n16b,UP,NTRANS ++S 15200,7500,15200,9100,620,74onymous_,UP,NDIF ++S 15300,37600,20700,37600,400,75onymous_,RIGHT,ALU1 ++S 30680,6000,37120,6000,600,235nymous_,RIGHT,PTIE ++S 27300,13000,29500,13000,400,271nymous_,RIGHT,ALU1 ++S 30600,36400,31400,36400,200,236nymous_,RIGHT,POLY ++S 27200,13100,27200,13900,400,272nymous_,UP,ALU1 ++S 14600,9600,14600,10800,200,76onymous_,UP,POLY ++S 30600,26700,30600,35300,2400,237nymous_,UP,ALU2 ++S 27200,12700,27200,14300,620,273nymous_,UP,PDIF ++S 30600,21300,30600,35500,400,238nymous_,UP,ALU1 ++S 1280,37600,21120,37600,600,77onymous_,RIGHT,PTIE ++S 5700,11000,10300,11000,400,153nymous_,RIGHT,ALU1 ++S 700,25000,8900,25000,2400,115nymous_,RIGHT,ALU2 ++S 5600,11100,5600,14700,620,154nymous_,UP,PDIF ++S 5700,9000,10300,9000,400,155nymous_,RIGHT,ALU1 ++S 17700,29200,18900,29200,620,38onymous_,RIGHT,NDIF ++S 17700,28000,18900,28000,620,39onymous_,RIGHT,NDIF ++S 5600,7500,5600,9100,420,156nymous_,UP,NDIF ++S 33800,8600,35000,8600,200,198nymous_,RIGHT,POLY ++S 5000,9600,5000,10600,200,157nymous_,UP,POLY ++S 17700,24400,18900,24400,620,42onymous_,RIGHT,NDIF ++S 33800,7300,33800,8300,200,n5a,UP,NTRANS ++S 30200,12000,30200,12200,200,241nymous_,UP,POLY ++S 10000,22200,11600,22200,200,117nymous_,RIGHT,POLY ++S 14000,7500,14000,9100,620,81onymous_,UP,NDIF ++S 24200,12700,24200,14700,200,p4a,UP,PTRANS ++S 14100,10000,21100,10000,400,80onymous_,RIGHT,ALU1 ++S 9700,19000,14900,19000,2400,116nymous_,RIGHT,ALU2 ++S 14000,11300,14000,12900,620,79onymous_,UP,PDIF ++S 24700,21000,28300,21000,200,p7c,RIGHT,PTRANS ++S 14000,12100,14000,15900,400,78onymous_,UP,ALU1 ++S 30400,36400,30400,36600,200,240nymous_,UP,POLY ++S 24700,22200,28300,22200,200,p7b,RIGHT,PTRANS ++S 30600,21100,30600,35900,620,239nymous_,UP,PDIF ++S 27200,7500,27200,8100,620,274nymous_,UP,NDIF ++S 17700,23200,18900,23200,620,43onymous_,RIGHT,NDIF ++S 30200,7300,30200,8300,200,n3,UP,NTRANS ++S 33800,21100,33800,36500,620,201nymous_,UP,PDIF ++S 5000,7300,5000,9300,200,n18a,UP,NTRANS ++S 13400,11100,13400,13100,200,p17b,UP,PTRANS ++S 17500,25000,19100,25000,200,n7c,RIGHT,NTRANS ++S 4100,13000,20300,13000,2400,158nymous_,RIGHT,ALU2 ++S 33400,11700,33400,17300,400,202nymous_,UP,ALU2 ++S 17500,23800,19100,23800,200,n7d,RIGHT,NTRANS ++S 4400,11900,4400,15900,400,159nymous_,UP,ALU1 ++S 13400,7300,13400,9300,200,n17b,UP,NTRANS ++S 5000,10000,11000,10000,600,nt,RIGHT,POLY ++S 17000,12000,17400,12000,200,nt,RIGHT,POLY ++S 13200,22500,13200,36700,200,n15c,UP,NTRANS ++S 16900,24400,17700,24400,400,50onymous_,RIGHT,ALU1 ++S 17500,28600,19100,28600,200,n7b,RIGHT,NTRANS ++S 14000,22900,14000,39700,400,83onymous_,UP,ALU1 ++S 5000,10900,5000,14900,200,p18a,UP,PTRANS ++S 30200,8600,30200,9000,200,242nymous_,UP,POLY ++S 10000,22500,10000,36700,200,n15a,UP,NTRANS ++S 17500,29800,19100,29800,200,n7a,RIGHT,NTRANS ++S 5200,22500,5200,36700,200,n14b,UP,NTRANS ++S 14000,6100,14000,7900,400,82onymous_,UP,ALU1 ++S 30200,9000,31800,9000,200,eb,RIGHT,POLY ++S 30200,12000,31800,12000,200,eb,RIGHT,POLY ++S 33800,12700,33800,14700,200,p5a,UP,PTRANS ++S 26400,18600,26400,38600,8400,277nymous_,UP,NWELL ++S 5600,8100,5600,13700,400,1.nq,UP,ALU1 ++S 30200,12500,30200,14500,200,p3,UP,PTRANS ++S 27000,24900,27000,36700,400,276nymous_,UP,ALU2 ++S 27000,6900,27000,14300,400,275nymous_,UP,ALU2 ++S 24700,23400,28300,23400,200,p7a,RIGHT,PTRANS ++S 24700,24600,28300,24600,200,p10,RIGHT,PTRANS ++S 24700,25800,28300,25800,200,p13,RIGHT,PTRANS ++S 24700,27000,28300,27000,200,p6c,RIGHT,PTRANS ++S 14000,22700,14000,36500,620,84onymous_,UP,NDIF ++S 17500,27400,19100,27400,200,n6b,RIGHT,NTRANS ++S 9800,10900,9800,14900,200,p18e,UP,PTRANS ++S 17500,26200,19100,26200,200,n6c,RIGHT,NTRANS ++S 9800,9600,9800,10600,200,118nymous_,UP,POLY ++S 34600,200,34600,2000,11000,0nonymous_,UP,TALU3 ++S 9800,7300,9800,9300,200,n18e,UP,NTRANS ++S 33200,13100,33200,15900,400,203nymous_,UP,ALU1 ++S 13400,200,13400,2000,27000,1nonymous_,UP,TALU3 ++S 4400,11100,4400,14700,620,160nymous_,UP,PDIF ++S 34600,200,34600,12000,11000,2nonymous_,UP,TALU5 ++S 4400,7500,4400,9100,620,161nymous_,UP,NDIF ++S 4400,6100,4400,8900,400,162nymous_,UP,ALU1 ++S 26000,13700,26000,16100,400,280nymous_,UP,ALU2 ++S 25700,17000,33500,17000,400,279nymous_,RIGHT,ALU2 ++S 17500,31000,19100,31000,200,n6a,RIGHT,NTRANS ++S 2700,20200,15700,20200,400,278nymous_,RIGHT,ALU1 ++S 17500,32200,19100,32200,200,n8d,RIGHT,NTRANS ++S 17500,33400,19100,33400,200,n8c,RIGHT,NTRANS ++S 17500,34600,19100,34600,200,n8b,RIGHT,NTRANS ++S 50,17000,39950,17000,10000,blockagenet,RIGHT,TALU2 ++S 24700,28200,28300,28200,200,p6b,RIGHT,PTRANS ++S 24700,29400,28300,29400,200,p6a,RIGHT,PTRANS ++S 24700,30600,28300,30600,200,p8c,RIGHT,PTRANS ++S 26000,13100,26000,15900,400,281nymous_,UP,ALU1 ++S 30100,20200,35900,20200,400,243nymous_,RIGHT,ALU1 ++S 14000,21800,14000,22200,600,85onymous_,UP,POLY ++S 30000,19900,30000,24900,400,244nymous_,UP,ALU2 ++S 13400,9600,13400,10800,200,86onymous_,UP,POLY ++S 9500,37000,17100,37000,2400,119nymous_,RIGHT,ALU2 ++S 29600,13100,29600,13900,400,245nymous_,UP,ALU1 ++S 33200,12900,33200,14500,620,204nymous_,UP,PDIF ++S 9500,22800,17100,22800,400,120nymous_,RIGHT,ALU2 ++S 33200,7500,33200,8100,620,205nymous_,UP,NDIF ++S 9800,21500,9800,23100,400,121nymous_,UP,ALU2 ++S 13400,200,13400,12000,27000,3nonymous_,UP,TALU5 ++S 33200,6100,33200,7900,400,206nymous_,UP,ALU1 ++S 50,6000,26800,6000,12000,4nonymous_,RIGHT,TALU2 ++S 12800,11300,12800,12900,620,87onymous_,UP,PDIF ++S 4400,22700,4400,38300,2400,163nymous_,UP,ALU2 ++S 29200,6000,39950,6000,12000,5nonymous_,RIGHT,TALU2 ++S 32800,20200,32800,20600,600,207nymous_,UP,POLY ++S 12900,11000,17300,11000,400,88onymous_,RIGHT,ALU1 ++S 4400,22900,4400,37500,400,164nymous_,UP,ALU1 ++S 4400,22700,4400,36500,620,165nymous_,UP,NDIF ++S 17500,35800,19100,35800,200,n8a,RIGHT,NTRANS ++S 14600,7300,14600,9300,200,n17c,UP,NTRANS ++S 6200,7300,6200,9300,200,n18b,UP,NTRANS ++S 27800,7300,27800,8300,200,n2,UP,NTRANS ++S 34600,20900,34600,36700,200,p14c,UP,PTRANS ++S 24700,31800,28300,31800,200,p8b,RIGHT,PTRANS ++S 24700,33000,28300,33000,200,p8a,RIGHT,PTRANS ++S 24700,34200,28300,34200,200,p9,RIGHT,PTRANS ++S 24700,35800,28300,35800,200,p12,RIGHT,PTRANS ++S 26000,12900,26000,14500,620,282nymous_,UP,PDIF ++S 26000,8700,26000,14300,400,283nymous_,UP,ALU2 ++S 26000,7500,26000,8100,620,284nymous_,UP,NDIF ++S 29600,12700,29600,14300,620,246nymous_,UP,PDIF ++S 29600,10300,29600,16300,400,247nymous_,UP,ALU2 ++S 9300,31000,16100,31000,2400,122nymous_,RIGHT,ALU2 ++S 9300,25000,16100,25000,2400,123nymous_,RIGHT,ALU2 ++S 23600,6100,23600,7900,400,316nymous_,UP,ALU1 ++S 9200,12100,9200,15900,400,124nymous_,UP,ALU1 ++S 23080,37600,29920,37600,600,317nymous_,RIGHT,NTIE ++S 50,6000,26800,6000,12000,6nonymous_,RIGHT,TALU4 ++S 12900,9000,15100,9000,400,89onymous_,RIGHT,ALU1 ++S 9200,11100,9200,14700,620,125nymous_,UP,PDIF ++S 29200,6000,39950,6000,12000,7nonymous_,RIGHT,TALU4 ++S 12800,8100,12800,12500,400,90onymous_,UP,ALU1 ++S 32600,11400,32600,12400,200,208nymous_,UP,POLY ++S 0,6000,40000,6000,12000,8nonymous_,RIGHT,TALU6 ++S 4400,21800,4400,22200,600,166nymous_,UP,POLY ++S 32600,8600,32600,9800,200,209nymous_,UP,POLY ++S 3900,7600,7300,7600,1200,167nymous_,RIGHT,ALU2 ++S 19800,34900,19800,37100,400,9nonymous_,UP,ALU2 ++S 38200,19080,38200,37920,600,168nymous_,UP,NTIE ++B 19800,35200,300,300,CONT_VIA,342nymous_ ++B 19800,37600,300,300,CONT_BODY_P,341nymous_ ++B 19800,31000,300,300,CONT_POLY,343nymous_ ++B 19800,28200,300,300,CONT_VIA,344nymous_ ++B 19800,27400,300,300,CONT_POLY,345nymous_ ++B 19800,26200,300,300,CONT_POLY,346nymous_ ++B 19800,22600,300,300,CONT_POLY,347nymous_ ++B 19600,19200,300,300,CONT_BODY_P,348nymous_ ++B 18800,17000,300,300,CONT_VIA2,349nymous_ ++B 18800,16000,300,300,CONT_BODY_N,351nymous_ ++B 18800,17000,300,300,CONT_VIA,350nymous_ ++B 18800,9000,300,300,CONT_DIF_N,352nymous_ ++B 18800,6000,300,300,CONT_VIA2,353nymous_ ++B 24000,29200,300,300,CONT_POLY,1268ymous_ ++B 26000,30000,300,300,CONT_DIF_P,1214ymous_ ++B 32200,34000,300,300,CONT_DIF_P,1000ymous_ ++B 30800,16000,300,300,CONT_BODY_N,1054ymous_ ++B 20800,30400,300,300,CONT_BODY_P,1322ymous_ ++B 16800,35800,300,300,CONT_VIA,408nymous_ ++B 10800,21800,300,300,CONT_POLY,569nymous_ ++B 29000,31800,300,300,CONT_POLY,1108ymous_ ++B 27200,17000,300,300,CONT_VIA2,1162ymous_ ++B 12800,17000,300,300,CONT_VIA,516nymous_ ++B 15600,34000,300,300,CONT_DIF_N,462nymous_ ++B 8600,25000,300,300,CONT_VIA2,623nymous_ ++B 7000,11000,300,300,CONT_VIA2,677nymous_ ++B 4400,25000,300,300,CONT_DIF_N,785nymous_ ++B 37000,29000,300,300,CONT_DIF_P,839nymous_ ++B 35600,14000,300,300,CONT_DIF_P,893nymous_ ++B 33800,34000,300,300,CONT_VIA,947nymous_ ++B 24000,28200,300,300,CONT_VIA,1269ymous_ ++B 26000,28800,300,300,CONT_VIA2,1215ymous_ ++B 32200,33000,300,300,CONT_DIF_P,1001ymous_ ++B 30800,14000,300,300,CONT_DIF_P,1055ymous_ ++B 20800,29400,300,300,CONT_BODY_P,1323ymous_ ++B 15600,33000,300,300,CONT_DIF_N,463nymous_ ++B 16800,35800,300,300,CONT_POLY,409nymous_ ++B 10600,19200,300,300,CONT_BODY_P,570nymous_ ++B 8600,24000,300,300,CONT_VIA2,624nymous_ ++B 29000,30600,300,300,CONT_POLY,1109ymous_ ++B 27200,17000,300,300,CONT_VIA,1163ymous_ ++B 12800,16000,300,300,CONT_BODY_N,517nymous_ ++B 7000,10000,300,300,CONT_VIA2,678nymous_ ++B 5600,37600,300,300,CONT_BODY_P,732nymous_ ++B 4400,24000,300,300,CONT_VIA2,786nymous_ ++B 37000,28000,300,300,CONT_VIA2,840nymous_ ++B 11600,19200,300,300,CONT_BODY_P,540nymous_ ++B 35600,13000,300,300,CONT_DIF_P,894nymous_ ++B 26000,28800,300,300,CONT_VIA,1216ymous_ ++B 33800,34000,300,300,CONT_DIF_P,948nymous_ ++B 32200,32000,300,300,CONT_DIF_P,1002ymous_ ++B 20800,28400,300,300,CONT_BODY_P,1324ymous_ ++B 24000,28200,300,300,CONT_POLY,1270ymous_ ++B 18800,37600,300,300,CONT_BODY_P,356nymous_ ++B 30800,13000,300,300,CONT_DIF_P,1056ymous_ ++B 29000,25800,300,300,CONT_POLY,1110ymous_ ++B 15600,32000,300,300,CONT_DIF_N,464nymous_ ++B 16800,34600,300,300,CONT_VIA2,410nymous_ ++B 10400,17000,300,300,CONT_VIA2,571nymous_ ++B 8000,17000,300,300,CONT_VIA2,625nymous_ ++B 27200,16000,300,300,CONT_BODY_N,1164ymous_ ++B 12800,12600,300,300,CONT_DIF_P,518nymous_ ++B 7000,9000,300,300,CONT_VIA2,679nymous_ ++B 5400,36000,300,300,CONT_VIA2,733nymous_ ++B 4400,24000,300,300,CONT_VIA,787nymous_ ++B 37000,28000,300,300,CONT_VIA,841nymous_ ++B 35600,8000,300,300,CONT_DIF_N,895nymous_ ++B 26000,28800,300,300,CONT_DIF_P,1217ymous_ ++B 33800,33000,300,300,CONT_VIA2,949nymous_ ++B 32200,31000,300,300,CONT_DIF_P,1003ymous_ ++B 20800,27400,300,300,CONT_BODY_P,1325ymous_ ++B 24000,27000,300,300,CONT_POLY,1271ymous_ ++B 16800,34600,300,300,CONT_VIA,411nymous_ ++B 18800,36400,300,300,CONT_VIA,357nymous_ ++B 10400,17000,300,300,CONT_VIA,572nymous_ ++B 30800,10600,300,300,CONT_POLY,1057ymous_ ++B 29000,24600,300,300,CONT_VIA,1111ymous_ ++B 27200,14000,300,300,CONT_DIF_P,1165ymous_ ++B 12800,11600,300,300,CONT_DIF_P,519nymous_ ++B 15600,31000,300,300,CONT_DIF_N,465nymous_ ++B 8000,17000,300,300,CONT_VIA,626nymous_ ++B 6800,17000,300,300,CONT_VIA2,680nymous_ ++B 5400,32000,300,300,CONT_VIA2,734nymous_ ++B 4400,24000,300,300,CONT_DIF_N,788nymous_ ++B 37000,28000,300,300,CONT_DIF_P,842nymous_ ++B 35600,6000,300,300,CONT_VIA2,896nymous_ ++B 33800,33000,300,300,CONT_VIA,950nymous_ ++B 23600,16000,300,300,CONT_BODY_N,1272ymous_ ++B 26000,27600,300,300,CONT_VIA2,1218ymous_ ++B 32200,30000,300,300,CONT_DIF_P,1004ymous_ ++B 30800,8000,300,300,CONT_DIF_N,1058ymous_ ++B 20800,26400,300,300,CONT_BODY_P,1326ymous_ ++B 16800,34600,300,300,CONT_POLY,412nymous_ ++B 18800,36400,300,300,CONT_DIF_N,358nymous_ ++B 10400,16000,300,300,CONT_BODY_N,573nymous_ ++B 29000,24600,300,300,CONT_POLY,1112ymous_ ++B 27200,13000,300,300,CONT_DIF_P,1166ymous_ ++B 12800,9000,300,300,CONT_DIF_N,520nymous_ ++B 15600,30000,300,300,CONT_DIF_N,466nymous_ ++B 8000,16000,300,300,CONT_BODY_N,627nymous_ ++B 6800,17000,300,300,CONT_VIA,681nymous_ ++B 5400,31000,300,300,CONT_VIA2,735nymous_ ++B 4400,23000,300,300,CONT_VIA,789nymous_ ++B 37000,27000,300,300,CONT_VIA2,843nymous_ ++B 35600,6000,300,300,CONT_VIA,897nymous_ ++B 33800,33000,300,300,CONT_DIF_P,951nymous_ ++B 23600,14000,300,300,CONT_DIF_P,1273ymous_ ++B 26000,27600,300,300,CONT_DIF_P,1219ymous_ ++B 18800,35200,300,300,CONT_DIF_N,359nymous_ ++B 32200,29000,300,300,CONT_DIF_P,1005ymous_ ++B 30800,6000,300,300,CONT_BODY_P,1059ymous_ ++B 20800,25400,300,300,CONT_BODY_P,1327ymous_ ++B 15600,29000,300,300,CONT_DIF_N,467nymous_ ++B 16800,33400,300,300,CONT_VIA2,413nymous_ ++B 10400,13800,300,300,CONT_DIF_P,574nymous_ ++B 8000,13800,300,300,CONT_DIF_P,628nymous_ ++B 29000,23400,300,300,CONT_VIA,1113ymous_ ++B 27200,10600,300,300,CONT_POLY,1167ymous_ ++B 12800,8000,300,300,CONT_DIF_N,521nymous_ ++B 6800,16000,300,300,CONT_BODY_N,682nymous_ ++B 5400,30000,300,300,CONT_VIA2,736nymous_ ++B 4400,23000,300,300,CONT_DIF_N,790nymous_ ++B 37000,27000,300,300,CONT_VIA,844nymous_ ++B 35600,6000,300,300,CONT_BODY_P,898nymous_ ++B 26000,26400,300,300,CONT_VIA,1220ymous_ ++B 33800,32000,300,300,CONT_VIA,952nymous_ ++B 32200,28000,300,300,CONT_DIF_P,1006ymous_ ++B 20800,24400,300,300,CONT_BODY_P,1328ymous_ ++B 23600,13000,300,300,CONT_DIF_P,1274ymous_ ++B 18800,34000,300,300,CONT_VIA,360nymous_ ++B 30600,35000,300,300,CONT_VIA2,1060ymous_ ++B 29000,23400,300,300,CONT_POLY,1114ymous_ ++B 15600,28000,300,300,CONT_DIF_N,468nymous_ ++B 16800,33400,300,300,CONT_VIA,414nymous_ ++B 10400,12800,300,300,CONT_DIF_P,575nymous_ ++B 8000,12800,300,300,CONT_DIF_P,629nymous_ ++B 27200,8000,300,300,CONT_DIF_N,1168ymous_ ++B 12800,6000,300,300,CONT_VIA2,522nymous_ ++B 6800,14800,300,300,CONT_DIF_P,683nymous_ ++B 5400,26000,300,300,CONT_VIA2,737nymous_ ++B 4400,21800,300,300,CONT_VIA,791nymous_ ++B 37000,27000,300,300,CONT_DIF_P,845nymous_ ++B 5400,25000,300,300,CONT_VIA2,738nymous_ ++B 35400,35000,300,300,CONT_DIF_P,900nymous_ ++B 33800,31000,300,300,CONT_VIA,954nymous_ ++B 23600,6000,300,300,CONT_VIA2,1276ymous_ ++B 26000,25200,300,300,CONT_DIF_P,1222ymous_ ++B 32200,26000,300,300,CONT_DIF_P,1008ymous_ ++B 30600,35000,300,300,CONT_DIF_P,1062ymous_ ++B 20800,22400,300,300,CONT_BODY_P,1330ymous_ ++B 16800,32200,300,300,CONT_VIA,416nymous_ ++B 18800,32800,300,300,CONT_DIF_N,362nymous_ ++B 10400,10000,300,300,CONT_POLY,577nymous_ ++B 29000,22200,300,300,CONT_POLY,1116ymous_ ++B 27000,19200,300,300,CONT_BODY_N,1170ymous_ ++B 12800,6000,300,300,CONT_BODY_P,524nymous_ ++B 35400,36000,300,300,CONT_DIF_P,899nymous_ ++B 26000,26400,300,300,CONT_DIF_P,1221ymous_ ++B 33800,32000,300,300,CONT_DIF_P,953nymous_ ++B 32200,27000,300,300,CONT_DIF_P,1007ymous_ ++B 20800,23400,300,300,CONT_BODY_P,1329ymous_ ++B 23600,8000,300,300,CONT_DIF_N,1275ymous_ ++B 16800,33400,300,300,CONT_POLY,415nymous_ ++B 18800,34000,300,300,CONT_DIF_N,361nymous_ ++B 10400,11800,300,300,CONT_DIF_P,576nymous_ ++B 30600,35000,300,300,CONT_VIA,1061ymous_ ++B 29000,22200,300,300,CONT_VIA,1115ymous_ ++B 12800,6000,300,300,CONT_VIA,523nymous_ ++B 15600,27000,300,300,CONT_DIF_N,469nymous_ ++B 8000,11800,300,300,CONT_DIF_P,630nymous_ ++B 6800,13800,300,300,CONT_DIF_P,684nymous_ ++B 27200,6000,300,300,CONT_BODY_P,1169ymous_ ++B 4400,21800,300,300,CONT_POLY,792nymous_ ++B 37000,26000,300,300,CONT_VIA,846nymous_ ++B 35400,34000,300,300,CONT_DIF_P,901nymous_ ++B 33800,31000,300,300,CONT_DIF_P,955nymous_ ++B 23600,6000,300,300,CONT_VIA,1277ymous_ ++B 26000,24000,300,300,CONT_VIA,1223ymous_ ++B 18800,31600,300,300,CONT_VIA,363nymous_ ++B 32200,25000,300,300,CONT_DIF_P,1009ymous_ ++B 30600,34000,300,300,CONT_VIA2,1063ymous_ ++B 20800,21400,300,300,CONT_BODY_P,1331ymous_ ++B 15600,25000,300,300,CONT_DIF_N,471nymous_ ++B 16800,32200,300,300,CONT_POLY,417nymous_ ++B 10400,9000,300,300,CONT_DIF_N,578nymous_ ++B 8000,10000,300,300,CONT_POLY,632nymous_ ++B 29000,21000,300,300,CONT_VIA,1117ymous_ ++B 27000,11000,300,300,CONT_VIA2,1171ymous_ ++B 12600,19200,300,300,CONT_BODY_P,525nymous_ ++B 6800,12000,300,300,CONT_DIF_P,686nymous_ ++B 4600,19200,300,300,CONT_BODY_P,740nymous_ ++B 38200,37600,300,300,CONT_BODY_N,794nymous_ ++B 37000,25000,300,300,CONT_VIA,848nymous_ ++B 35400,33000,300,300,CONT_DIF_P,902nymous_ ++B 26000,24000,300,300,CONT_DIF_P,1224ymous_ ++B 33800,30000,300,300,CONT_VIA,956nymous_ ++B 32200,24000,300,300,CONT_DIF_P,1010ymous_ ++B 20800,20400,300,300,CONT_BODY_P,1332ymous_ ++B 23600,6000,300,300,CONT_BODY_P,1278ymous_ ++B 18800,31600,300,300,CONT_DIF_N,364nymous_ ++B 37000,26000,300,300,CONT_DIF_P,847nymous_ ++B 38200,19200,300,300,CONT_BODY_N,793nymous_ ++B 5400,24000,300,300,CONT_VIA2,739nymous_ ++B 6800,12800,300,300,CONT_DIF_P,685nymous_ ++B 8000,11000,300,300,CONT_VIA,631nymous_ ++B 15600,26000,300,300,CONT_DIF_N,470nymous_ ++B 35400,31000,300,300,CONT_DIF_P,904nymous_ ++B 37000,24000,300,300,CONT_VIA,850nymous_ ++B 38200,35400,300,300,CONT_BODY_N,796nymous_ ++B 27000,9000,300,300,CONT_VIA2,1173ymous_ ++B 4600,37600,300,300,CONT_VIA,742nymous_ ++B 6800,8000,300,300,CONT_DIF_N,688nymous_ ++B 8000,9000,300,300,CONT_DIF_N,634nymous_ ++B 15600,23000,300,300,CONT_DIF_N,473nymous_ ++B 12400,35000,300,300,CONT_DIF_N,527nymous_ ++B 28800,9000,300,300,CONT_POLY,1119ymous_ ++B 30600,34000,300,300,CONT_DIF_P,1065ymous_ ++B 10400,6000,300,300,CONT_VIA2,580nymous_ ++B 18800,30400,300,300,CONT_DIF_N,365nymous_ ++B 16800,28200,300,300,CONT_POLY,419nymous_ ++B 23400,17000,300,300,CONT_VIA2,1279ymous_ ++B 20000,16000,300,300,CONT_BODY_N,1333ymous_ ++B 32200,23000,300,300,CONT_DIF_P,1011ymous_ ++B 33800,30000,300,300,CONT_DIF_P,957nymous_ ++B 26000,22800,300,300,CONT_VIA2,1225ymous_ ++B 35400,32000,300,300,CONT_DIF_P,903nymous_ ++B 37000,25000,300,300,CONT_DIF_P,849nymous_ ++B 38200,36400,300,300,CONT_BODY_N,795nymous_ ++B 4600,37600,300,300,CONT_VIA2,741nymous_ ++B 6800,10000,300,300,CONT_POLY,687nymous_ ++B 12400,36000,300,300,CONT_DIF_N,526nymous_ ++B 27000,10000,300,300,CONT_VIA2,1172ymous_ ++B 8000,9000,300,300,CONT_VIA,633nymous_ ++B 10400,8000,300,300,CONT_DIF_N,579nymous_ ++B 16800,29200,300,300,CONT_VIA,418nymous_ ++B 15600,24000,300,300,CONT_DIF_N,472nymous_ ++B 29000,21000,300,300,CONT_POLY,1118ymous_ ++B 30600,34000,300,300,CONT_VIA,1064ymous_ ++B 12400,33000,300,300,CONT_DIF_N,529nymous_ ++B 28400,17000,300,300,CONT_VIA,1121ymous_ ++B 7800,37600,300,300,CONT_VIA2,636nymous_ ++B 10400,6000,300,300,CONT_BODY_P,582nymous_ ++B 16800,24400,300,300,CONT_VIA,421nymous_ ++B 15200,17000,300,300,CONT_VIA,475nymous_ ++B 20000,8600,300,300,CONT_DIF_N,1335ymous_ ++B 30600,33000,300,300,CONT_VIA,1067ymous_ ++B 3200,17000,300,300,CONT_VIA2,1013ymous_ ++B 18800,28000,300,300,CONT_DIF_N,367nymous_ ++B 26000,21600,300,300,CONT_VIA2,1227ymous_ ++B 23000,19200,300,300,CONT_BODY_N,1281ymous_ ++B 33800,29000,300,300,CONT_VIA,959nymous_ ++B 35400,30000,300,300,CONT_DIF_P,905nymous_ ++B 37000,24000,300,300,CONT_DIF_P,851nymous_ ++B 38200,34400,300,300,CONT_BODY_N,797nymous_ ++B 4600,37600,300,300,CONT_BODY_P,743nymous_ ++B 6800,7200,300,300,CONT_DIF_N,689nymous_ ++B 8000,8000,300,300,CONT_DIF_N,635nymous_ ++B 15200,17000,300,300,CONT_VIA2,474nymous_ ++B 12400,34000,300,300,CONT_DIF_N,528nymous_ ++B 27000,37600,300,300,CONT_BODY_N,1174ymous_ ++B 28400,17000,300,300,CONT_VIA2,1120ymous_ ++B 10400,6000,300,300,CONT_VIA,581nymous_ ++B 18800,29200,300,300,CONT_DIF_N,366nymous_ ++B 16800,25400,300,300,CONT_POLY,420nymous_ ++B 20000,11000,300,300,CONT_POLY,1334ymous_ ++B 30600,33000,300,300,CONT_VIA2,1066ymous_ ++B 32200,22000,300,300,CONT_DIF_P,1012ymous_ ++B 26000,22800,300,300,CONT_DIF_P,1226ymous_ ++B 23400,17000,300,300,CONT_VIA,1280ymous_ ++B 33800,29000,300,300,CONT_VIA2,958nymous_ ++B 30600,32000,300,300,CONT_VIA,1069ymous_ ++B 18800,26800,300,300,CONT_DIF_N,369nymous_ ++B 16800,20200,300,300,CONT_VIA,423nymous_ ++B 23000,36400,300,300,CONT_BODY_N,1283ymous_ ++B 20000,6000,300,300,CONT_VIA,1337ymous_ ++B 3200,16000,300,300,CONT_BODY_N,1015ymous_ ++B 33800,28000,300,300,CONT_VIA2,961nymous_ ++B 26000,21600,300,300,CONT_DIF_P,1229ymous_ ++B 35400,28000,300,300,CONT_DIF_P,907nymous_ ++B 37000,23000,300,300,CONT_VIA,853nymous_ ++B 38200,32400,300,300,CONT_BODY_N,799nymous_ ++B 4400,17000,300,300,CONT_VIA,745nymous_ ++B 6800,6000,300,300,CONT_VIA,691nymous_ ++B 12400,32000,300,300,CONT_DIF_N,530nymous_ ++B 27000,36400,300,300,CONT_DIF_P,1176ymous_ ++B 7800,37600,300,300,CONT_VIA,637nymous_ ++B 9600,19200,300,300,CONT_BODY_P,583nymous_ ++B 16800,23400,300,300,CONT_POLY,422nymous_ ++B 15200,16000,300,300,CONT_BODY_N,476nymous_ ++B 28400,16000,300,300,CONT_BODY_N,1122ymous_ ++B 30600,33000,300,300,CONT_DIF_P,1068ymous_ ++B 18800,26800,300,300,CONT_VIA,368nymous_ ++B 23000,37600,300,300,CONT_BODY_N,1282ymous_ ++B 20000,6000,300,300,CONT_VIA2,1336ymous_ ++B 3200,17000,300,300,CONT_VIA,1014ymous_ ++B 33800,29000,300,300,CONT_DIF_P,960nymous_ ++B 26000,21600,300,300,CONT_VIA,1228ymous_ ++B 35400,29000,300,300,CONT_DIF_P,906nymous_ ++B 37000,23000,300,300,CONT_VIA2,852nymous_ ++B 38200,33400,300,300,CONT_BODY_N,798nymous_ ++B 4400,17000,300,300,CONT_VIA2,744nymous_ ++B 6800,6000,300,300,CONT_VIA2,690nymous_ ++B 3200,14000,300,300,CONT_VIA2,1017ymous_ ++B 33800,28000,300,300,CONT_DIF_P,963nymous_ ++B 35400,26000,300,300,CONT_DIF_P,909nymous_ ++B 37000,22000,300,300,CONT_VIA2,855nymous_ ++B 38200,30400,300,300,CONT_BODY_N,801nymous_ ++B 4400,14800,300,300,CONT_DIF_P,747nymous_ ++B 6800,37600,300,300,CONT_VIA2,693nymous_ ++B 7600,19200,300,300,CONT_BODY_P,639nymous_ ++B 15200,11600,300,300,CONT_DIF_P,478nymous_ ++B 12400,30000,300,300,CONT_DIF_N,532nymous_ ++B 27000,33600,300,300,CONT_DIF_P,1178ymous_ ++B 28400,8000,300,300,CONT_DIF_N,1124ymous_ ++B 9200,17000,300,300,CONT_VIA2,585nymous_ ++B 18800,25600,300,300,CONT_DIF_N,370nymous_ ++B 16600,19200,300,300,CONT_BODY_P,424nymous_ ++B 20000,6000,300,300,CONT_BODY_P,1338ymous_ ++B 30600,32000,300,300,CONT_DIF_P,1070ymous_ ++B 3200,15000,300,300,CONT_BODY_N,1016ymous_ ++B 26000,20400,300,300,CONT_DIF_P,1230ymous_ ++B 23000,35400,300,300,CONT_BODY_N,1284ymous_ ++B 33800,28000,300,300,CONT_VIA,962nymous_ ++B 35400,27000,300,300,CONT_DIF_P,908nymous_ ++B 37000,23000,300,300,CONT_DIF_P,854nymous_ ++B 38200,31400,300,300,CONT_BODY_N,800nymous_ ++B 27000,35000,300,300,CONT_DIF_P,1177ymous_ ++B 4400,16000,300,300,CONT_BODY_N,746nymous_ ++B 6800,6000,300,300,CONT_BODY_P,692nymous_ ++B 7800,37600,300,300,CONT_BODY_P,638nymous_ ++B 15200,12600,300,300,CONT_DIF_P,477nymous_ ++B 12400,31000,300,300,CONT_DIF_N,531nymous_ ++B 28400,14000,300,300,CONT_DIF_P,1123ymous_ ++B 9600,37600,300,300,CONT_BODY_P,584nymous_ ++B 15200,9000,300,300,CONT_DIF_N,480nymous_ ++B 18400,12800,200,200,CONT_TURN1,1340ymous_ ++B 28200,11800,300,300,CONT_POLY,1126ymous_ ++B 30600,31000,300,300,CONT_DIF_P,1072ymous_ ++B 18800,23200,300,300,CONT_DIF_N,372nymous_ ++B 23000,33400,300,300,CONT_BODY_N,1286ymous_ ++B 3200,14000,300,300,CONT_BODY_N,1018ymous_ ++B 33800,27000,300,300,CONT_VIA2,964nymous_ ++B 25000,37600,300,300,CONT_BODY_N,1232ymous_ ++B 35400,25000,300,300,CONT_DIF_P,910nymous_ ++B 37000,22000,300,300,CONT_VIA,856nymous_ ++B 38200,29400,300,300,CONT_BODY_N,802nymous_ ++B 4400,13800,300,300,CONT_DIF_P,748nymous_ ++B 6800,37600,300,300,CONT_VIA,694nymous_ ++B 12400,29000,300,300,CONT_DIF_N,533nymous_ ++B 27000,32400,300,300,CONT_DIF_P,1179ymous_ ++B 28400,6000,300,300,CONT_BODY_P,1125ymous_ ++B 7600,36000,300,300,CONT_VIA2,640nymous_ ++B 9200,17000,300,300,CONT_VIA,586nymous_ ++B 16400,17000,300,300,CONT_VIA2,425nymous_ ++B 15200,10000,300,300,CONT_POLY,479nymous_ ++B 19800,32800,200,200,CONT_TURN1,1339ymous_ ++B 30600,31000,300,300,CONT_VIA,1071ymous_ ++B 18800,24400,300,300,CONT_DIF_N,371nymous_ ++B 25000,19200,300,300,CONT_BODY_N,1231ymous_ ++B 23000,34400,300,300,CONT_BODY_N,1285ymous_ ++B 16400,17000,300,300,CONT_VIA,426nymous_ ++B 9200,16000,300,300,CONT_BODY_N,587nymous_ ++B 7600,36000,300,300,CONT_VIA,641nymous_ ++B 12400,28000,300,300,CONT_DIF_N,534nymous_ ++B 6800,37600,300,300,CONT_BODY_P,695nymous_ ++B 4400,12800,300,300,CONT_DIF_P,749nymous_ ++B 38200,28400,300,300,CONT_BODY_N,803nymous_ ++B 37000,22000,300,300,CONT_DIF_P,857nymous_ ++B 35400,24000,300,300,CONT_DIF_P,911nymous_ ++B 25000,36400,300,300,CONT_DIF_P,1233ymous_ ++B 33800,27000,300,300,CONT_VIA,965nymous_ ++B 3200,13000,300,300,CONT_VIA2,1019ymous_ ++B 23000,32400,300,300,CONT_BODY_N,1287ymous_ ++B 16400,16000,300,300,CONT_BODY_N,427nymous_ ++B 18800,22200,300,300,CONT_VIA,373nymous_ ++B 9200,14800,300,300,CONT_DIF_P,588nymous_ ++B 30600,30000,300,300,CONT_VIA,1073ymous_ ++B 28200,10600,300,300,CONT_VIA,1127ymous_ ++B 17800,22000,200,200,CONT_TURN1,1341ymous_ ++B 12400,27000,300,300,CONT_DIF_N,535nymous_ ++B 15200,8000,300,300,CONT_DIF_N,481nymous_ ++B 7600,36000,300,300,CONT_DIF_N,642nymous_ ++B 6600,19200,300,300,CONT_BODY_P,696nymous_ ++B 4400,11800,300,300,CONT_DIF_P,750nymous_ ++B 38200,27400,300,300,CONT_BODY_N,804nymous_ ++B 36800,17000,300,300,CONT_VIA2,858nymous_ ++B 35400,23000,300,300,CONT_DIF_P,912nymous_ ++B 33800,27000,300,300,CONT_DIF_P,966nymous_ ++B 23000,31400,300,300,CONT_BODY_N,1288ymous_ ++B 25000,35000,300,300,CONT_DIF_P,1234ymous_ ++B 3200,13000,300,300,CONT_BODY_N,1020ymous_ ++B 30600,30000,300,300,CONT_DIF_P,1074ymous_ ++B 16400,12800,300,300,CONT_DIF_P,428nymous_ ++B 18800,22000,300,300,CONT_DIF_N,374nymous_ ++B 9200,13800,300,300,CONT_DIF_P,589nymous_ ++B 2800,36000,300,300,CONT_DIF_N,1128ymous_ ++B 17600,8000,200,200,CONT_TURN1,1342ymous_ ++B 12400,26000,300,300,CONT_DIF_N,536nymous_ ++B 15200,6000,300,300,CONT_VIA2,482nymous_ ++B 7600,35000,300,300,CONT_VIA,643nymous_ ++B 6600,36000,300,300,CONT_VIA2,697nymous_ ++B 4400,9000,300,300,CONT_DIF_N,751nymous_ ++B 38200,26400,300,300,CONT_BODY_N,805nymous_ ++B 36800,17000,300,300,CONT_VIA,859nymous_ ++B 35400,22000,300,300,CONT_DIF_P,913nymous_ ++B 33800,26000,300,300,CONT_VIA,967nymous_ ++B 23000,30400,300,300,CONT_BODY_N,1289ymous_ ++B 25000,33600,300,300,CONT_DIF_P,1235ymous_ ++B 18600,19200,300,300,CONT_BODY_P,375nymous_ ++B 3200,12000,300,300,CONT_VIA2,1021ymous_ ++B 30600,29000,300,300,CONT_VIA2,1075ymous_ ++B 17400,11000,200,200,CONT_TURN1,1343ymous_ ++B 15200,6000,300,300,CONT_VIA,483nymous_ ++B 16400,12000,300,300,CONT_DIF_P,429nymous_ ++B 9200,12800,300,300,CONT_DIF_P,590nymous_ ++B 7600,35000,300,300,CONT_DIF_N,644nymous_ ++B 2800,35000,300,300,CONT_DIF_N,1129ymous_ ++B 12400,25000,300,300,CONT_DIF_N,537nymous_ ++B 6600,32000,300,300,CONT_VIA2,698nymous_ ++B 4400,8000,300,300,CONT_DIF_N,752nymous_ ++B 38200,25400,300,300,CONT_BODY_N,806nymous_ ++B 36800,16000,300,300,CONT_VIA2,860nymous_ ++B 35000,19200,300,300,CONT_BODY_N,914nymous_ ++B 25000,32400,300,300,CONT_VIA,1236ymous_ ++B 33800,26000,300,300,CONT_DIF_P,968nymous_ ++B 3200,12000,300,300,CONT_BODY_N,1022ymous_ ++B 23000,29400,300,300,CONT_BODY_N,1290ymous_ ++B 17800,37600,300,300,CONT_BODY_P,376nymous_ ++B 10400,11000,200,200,CONT_TURN1,1344ymous_ ++B 27000,28800,300,300,CONT_DIF_P,1182ymous_ ++B 30600,29000,300,300,CONT_VIA,1076ymous_ ++B 2800,34000,300,300,CONT_DIF_N,1130ymous_ ++B 15200,6000,300,300,CONT_BODY_P,484nymous_ ++B 16400,10000,300,300,CONT_POLY,430nymous_ ++B 9200,12000,300,300,CONT_DIF_P,591nymous_ ++B 7600,34000,300,300,CONT_VIA,645nymous_ ++B 12400,24000,300,300,CONT_DIF_N,538nymous_ ++B 6600,31000,300,300,CONT_VIA2,699nymous_ ++B 4400,6000,300,300,CONT_VIA2,753nymous_ ++B 38200,24400,300,300,CONT_BODY_N,807nymous_ ++B 36800,16000,300,300,CONT_BODY_N,861nymous_ ++B 34800,35000,300,300,CONT_VIA2,915nymous_ ++B 25000,32400,300,300,CONT_DIF_P,1237ymous_ ++B 33800,25000,300,300,CONT_VIA,969nymous_ ++B 3200,9000,300,300,CONT_BODY_P,1023ymous_ ++B 23000,28400,300,300,CONT_BODY_N,1291ymous_ ++B 16400,9000,300,300,CONT_DIF_N,431nymous_ ++B 17800,36400,300,300,CONT_DIF_N,377nymous_ ++B 9200,10000,300,300,CONT_POLY,592nymous_ ++B 30600,29000,300,300,CONT_DIF_P,1077ymous_ ++B 2800,33000,300,300,CONT_DIF_N,1131ymous_ ++B 5000,19000,8300,2300,CONT_VIA2,1345ymous_ ++B 12400,23000,300,300,CONT_DIF_N,539nymous_ ++B 14600,19200,300,300,CONT_BODY_P,485nymous_ ++B 7600,34000,300,300,CONT_DIF_N,646nymous_ ++B 6600,30000,300,300,CONT_VIA2,700nymous_ ++B 4400,6000,300,300,CONT_VIA,754nymous_ ++B 38200,23400,300,300,CONT_BODY_N,808nymous_ ++B 36800,15000,300,300,CONT_VIA2,862nymous_ ++B 34800,34000,300,300,CONT_VIA2,916nymous_ ++B 27000,27600,300,300,CONT_DIF_P,1183ymous_ ++B 27000,26400,300,300,CONT_DIF_P,1184ymous_ ++B 27000,31200,300,300,CONT_DIF_P,1180ymous_ ++B 27000,30000,300,300,CONT_DIF_P,1181ymous_ ++B 33800,25000,300,300,CONT_DIF_P,970nymous_ ++B 23000,27400,300,300,CONT_BODY_N,1292ymous_ ++B 25000,31200,300,300,CONT_DIF_P,1238ymous_ ++B 3200,8000,300,300,CONT_VIA2,1024ymous_ ++B 30600,28000,300,300,CONT_VIA2,1078ymous_ ++B 16400,8000,300,300,CONT_DIF_N,432nymous_ ++B 17800,35200,300,300,CONT_DIF_N,378nymous_ ++B 9200,8000,300,300,CONT_VIA2,593nymous_ ++B 2800,32000,300,300,CONT_DIF_N,1132ymous_ ++B 28200,9000,200,200,CONT_TURN1,1346ymous_ ++B 14000,17000,300,300,CONT_VIA2,486nymous_ ++B 7600,33000,300,300,CONT_VIA,647nymous_ ++B 6600,26000,300,300,CONT_VIA2,701nymous_ ++B 4400,6000,300,300,CONT_BODY_P,755nymous_ ++B 38200,22400,300,300,CONT_BODY_N,809nymous_ ++B 36800,15000,300,300,CONT_BODY_N,863nymous_ ++B 27000,25200,300,300,CONT_VIA,1185ymous_ ++B 34800,33000,300,300,CONT_VIA2,917nymous_ ++B 33800,24000,300,300,CONT_VIA,971nymous_ ++B 23000,26400,300,300,CONT_BODY_N,1293ymous_ ++B 25000,30000,300,300,CONT_VIA,1239ymous_ ++B 17800,34000,300,300,CONT_DIF_N,379nymous_ ++B 3200,8000,300,300,CONT_BODY_P,1025ymous_ ++B 30600,28000,300,300,CONT_VIA,1079ymous_ ++B 22400,8000,200,200,CONT_TURN1,1347ymous_ ++B 14000,17000,300,300,CONT_VIA,487nymous_ ++B 16400,6000,300,300,CONT_VIA2,433nymous_ ++B 9200,8000,300,300,CONT_DIF_N,594nymous_ ++B 7600,33000,300,300,CONT_DIF_N,648nymous_ ++B 2800,31000,300,300,CONT_DIF_N,1133ymous_ ++B 6600,25000,300,300,CONT_VIA2,702nymous_ ++B 4400,36000,300,300,CONT_VIA2,756nymous_ ++B 38200,21400,300,300,CONT_BODY_N,810nymous_ ++B 36800,14000,300,300,CONT_BODY_N,864nymous_ ++B 34800,29000,300,300,CONT_VIA2,918nymous_ ++B 25000,30000,300,300,CONT_DIF_P,1240ymous_ ++B 27000,25200,300,300,CONT_DIF_P,1186ymous_ ++B 33800,24000,300,300,CONT_DIF_P,972nymous_ ++B 3200,7000,300,300,CONT_VIA2,1026ymous_ ++B 23000,25400,300,300,CONT_BODY_N,1294ymous_ ++B 17800,32800,300,300,CONT_DIF_N,380nymous_ ++B 30600,28000,300,300,CONT_DIF_P,1080ymous_ ++B 2800,30000,300,300,CONT_DIF_N,1134ymous_ ++B 21200,10000,200,200,CONT_TURN1,1348ymous_ ++B 14000,16000,300,300,CONT_BODY_N,488nymous_ ++B 16400,6000,300,300,CONT_VIA,434nymous_ ++B 9200,7200,300,300,CONT_DIF_N,595nymous_ ++B 7600,32000,300,300,CONT_VIA2,649nymous_ ++B 6600,24000,300,300,CONT_VIA2,703nymous_ ++B 4400,36000,300,300,CONT_VIA,757nymous_ ++B 38200,20400,300,300,CONT_BODY_N,811nymous_ ++B 36800,13000,300,300,CONT_BODY_N,865nymous_ ++B 34800,28000,300,300,CONT_VIA2,919nymous_ ++B 25000,28800,300,300,CONT_DIF_P,1241ymous_ ++B 27000,24000,300,300,CONT_DIF_P,1187ymous_ ++B 33800,23000,300,300,CONT_VIA2,973nymous_ ++B 3200,7000,300,300,CONT_BODY_P,1027ymous_ ++B 23000,24400,300,300,CONT_BODY_N,1295ymous_ ++B 16400,6000,300,300,CONT_BODY_P,435nymous_ ++B 17800,31600,300,300,CONT_VIA2,381nymous_ ++B 30600,27000,300,300,CONT_VIA2,1081ymous_ ++B 11600,17000,300,300,CONT_VIA,542nymous_ ++B 9200,7000,300,300,CONT_VIA2,596nymous_ ++B 2800,29000,300,300,CONT_DIF_N,1135ymous_ ++B 14000,12800,300,300,CONT_DIF_P,489nymous_ ++B 7600,32000,300,300,CONT_VIA,650nymous_ ++B 6000,36000,300,300,CONT_DIF_N,704nymous_ ++B 4400,36000,300,300,CONT_DIF_N,758nymous_ ++B 38000,35000,300,300,CONT_VIA2,812nymous_ ++B 36800,12000,300,300,CONT_BODY_N,866nymous_ ++B 27000,22800,300,300,CONT_DIF_P,1188ymous_ ++B 34800,27000,300,300,CONT_VIA2,920nymous_ ++B 33800,23000,300,300,CONT_VIA,974nymous_ ++B 23000,23400,300,300,CONT_BODY_N,1296ymous_ ++B 25000,27600,300,300,CONT_VIA,1242ymous_ ++B 3200,6000,300,300,CONT_VIA2,1028ymous_ ++B 30600,27000,300,300,CONT_VIA,1082ymous_ ++B 1600,19200,300,300,CONT_BODY_P,436nymous_ ++B 17800,31600,300,300,CONT_DIF_N,382nymous_ ++B 9200,6000,300,300,CONT_VIA2,597nymous_ ++B 2800,28000,300,300,CONT_DIF_N,1136ymous_ ++B 14000,12000,300,300,CONT_DIF_P,490nymous_ ++B 7600,32000,300,300,CONT_DIF_N,651nymous_ ++B 6000,35000,300,300,CONT_DIF_N,705nymous_ ++B 4400,35000,300,300,CONT_VIA,759nymous_ ++B 38000,34000,300,300,CONT_VIA2,813nymous_ ++B 36800,11000,300,300,CONT_VIA2,867nymous_ ++B 27000,21600,300,300,CONT_DIF_P,1189ymous_ ++B 34800,23000,300,300,CONT_VIA2,921nymous_ ++B 33800,23000,300,300,CONT_DIF_P,975nymous_ ++B 3200,6000,300,300,CONT_VIA,1029ymous_ ++B 11600,16000,300,300,CONT_BODY_N,543nymous_ ++B 23000,22400,300,300,CONT_BODY_N,1297ymous_ ++B 25000,27600,300,300,CONT_DIF_P,1243ymous_ ++B 17800,30400,300,300,CONT_VIA2,383nymous_ ++B 11600,14800,300,300,CONT_DIF_P,544nymous_ ++B 30600,27000,300,300,CONT_DIF_P,1083ymous_ ++B 14000,10000,300,300,CONT_POLY,491nymous_ ++B 1600,37600,300,300,CONT_BODY_P,437nymous_ ++B 9200,6000,300,300,CONT_VIA,598nymous_ ++B 7600,31000,300,300,CONT_VIA2,652nymous_ ++B 2800,27000,300,300,CONT_DIF_N,1137ymous_ ++B 6000,34000,300,300,CONT_DIF_N,706nymous_ ++B 4400,35000,300,300,CONT_DIF_N,760nymous_ ++B 38000,33000,300,300,CONT_VIA2,814nymous_ ++B 36800,10000,300,300,CONT_VIA2,868nymous_ ++B 34800,22000,300,300,CONT_VIA2,922nymous_ ++B 25000,26400,300,300,CONT_DIF_P,1244ymous_ ++B 27000,20400,300,300,CONT_DIF_P,1190ymous_ ++B 33800,22000,300,300,CONT_VIA2,976nymous_ ++B 3200,6000,300,300,CONT_BODY_P,1030ymous_ ++B 23000,21400,300,300,CONT_BODY_N,1298ymous_ ++B 17800,30400,300,300,CONT_VIA,384nymous_ ++B 11600,13800,300,300,CONT_DIF_P,545nymous_ ++B 30600,26000,300,300,CONT_DIF_P,1084ymous_ ++B 2800,26000,300,300,CONT_DIF_N,1138ymous_ ++B 14000,8000,300,300,CONT_DIF_N,492nymous_ ++B 1600,36400,300,300,CONT_BODY_P,438nymous_ ++B 9200,6000,300,300,CONT_BODY_P,599nymous_ ++B 7600,31000,300,300,CONT_VIA,653nymous_ ++B 6000,33000,300,300,CONT_DIF_N,707nymous_ ++B 4400,34000,300,300,CONT_VIA,761nymous_ ++B 38000,29000,300,300,CONT_VIA2,815nymous_ ++B 36800,9000,300,300,CONT_VIA2,869nymous_ ++B 34800,20200,300,300,CONT_POLY,923nymous_ ++B 25000,25200,300,300,CONT_DIF_P,1245ymous_ ++B 2600,19200,300,300,CONT_BODY_P,1191ymous_ ++B 33800,22000,300,300,CONT_VIA,977nymous_ ++B 32000,19200,300,300,CONT_BODY_N,1031ymous_ ++B 23000,20400,300,300,CONT_BODY_N,1299ymous_ ++B 1600,35400,300,300,CONT_BODY_P,439nymous_ ++B 17800,30400,300,300,CONT_DIF_N,385nymous_ ++B 11600,12800,300,300,CONT_DIF_P,546nymous_ ++B 9200,36000,300,300,CONT_DIF_N,600nymous_ ++B 30600,25000,300,300,CONT_DIF_P,1085ymous_ ++B 2800,25000,300,300,CONT_DIF_N,1139ymous_ ++B 14000,7200,300,300,CONT_DIF_N,493nymous_ ++B 7600,31000,300,300,CONT_DIF_N,654nymous_ ++B 6000,32000,300,300,CONT_DIF_N,708nymous_ ++B 4400,34000,300,300,CONT_DIF_N,762nymous_ ++B 38000,28000,300,300,CONT_VIA2,816nymous_ ++B 36800,9000,300,300,CONT_BODY_P,870nymous_ ++B 2600,37600,300,300,CONT_BODY_P,1192ymous_ ++B 34400,16000,300,300,CONT_BODY_N,924nymous_ ++B 33800,22000,300,300,CONT_DIF_P,978nymous_ ++B 22400,17000,300,300,CONT_VIA2,1300ymous_ ++B 25000,24000,300,300,CONT_DIF_P,1246ymous_ ++B 32000,17000,300,300,CONT_VIA2,1032ymous_ ++B 30600,24000,300,300,CONT_DIF_P,1086ymous_ ++B 1600,34400,300,300,CONT_BODY_P,440nymous_ ++B 17800,29200,300,300,CONT_DIF_N,386nymous_ ++B 11600,11800,300,300,CONT_DIF_P,547nymous_ ++B 9200,35000,300,300,CONT_DIF_N,601nymous_ ++B 2800,24000,300,300,CONT_DIF_N,1140ymous_ ++B 14000,6000,300,300,CONT_VIA2,494nymous_ ++B 7600,30000,300,300,CONT_VIA2,655nymous_ ++B 6000,31000,300,300,CONT_DIF_N,709nymous_ ++B 4400,33000,300,300,CONT_VIA,763nymous_ ++B 38000,27000,300,300,CONT_VIA2,817nymous_ ++B 36800,8000,300,300,CONT_BODY_P,871nymous_ ++B 26000,19200,300,300,CONT_BODY_N,1193ymous_ ++B 34400,14000,300,300,CONT_VIA,925nymous_ ++B 33200,17000,300,300,CONT_VIA2,979nymous_ ++B 22400,17000,300,300,CONT_VIA,1301ymous_ ++B 25000,22800,300,300,CONT_VIA,1247ymous_ ++B 17800,28000,300,300,CONT_VIA,387nymous_ ++B 11600,9000,300,300,CONT_DIF_N,548nymous_ ++B 32000,17000,300,300,CONT_VIA,1033ymous_ ++B 30600,23000,300,300,CONT_DIF_P,1087ymous_ ++B 14000,6000,300,300,CONT_VIA,495nymous_ ++B 1600,33400,300,300,CONT_BODY_P,441nymous_ ++B 9200,34000,300,300,CONT_DIF_N,602nymous_ ++B 7600,30000,300,300,CONT_VIA,656nymous_ ++B 2800,23000,300,300,CONT_DIF_N,1141ymous_ ++B 6000,30000,300,300,CONT_DIF_N,710nymous_ ++B 4400,33000,300,300,CONT_DIF_N,764nymous_ ++B 37200,37600,300,300,CONT_BODY_N,818nymous_ ++B 36800,7000,300,300,CONT_BODY_P,872nymous_ ++B 34400,14000,300,300,CONT_DIF_P,926nymous_ ++B 25000,22800,300,300,CONT_DIF_P,1248ymous_ ++B 26000,17000,300,300,CONT_VIA2,1194ymous_ ++B 33200,17000,300,300,CONT_VIA,980nymous_ ++B 32000,16000,300,300,CONT_BODY_N,1034ymous_ ++B 22400,16000,300,300,CONT_BODY_N,1302ymous_ ++B 17800,28000,300,300,CONT_DIF_N,388nymous_ ++B 11600,8000,300,300,CONT_DIF_N,549nymous_ ++B 30600,22000,300,300,CONT_DIF_P,1088ymous_ ++B 28000,19200,300,300,CONT_BODY_N,1142ymous_ ++B 14000,6000,300,300,CONT_BODY_P,496nymous_ ++B 1600,32400,300,300,CONT_BODY_P,442nymous_ ++B 9200,33000,300,300,CONT_DIF_N,603nymous_ ++B 7600,30000,300,300,CONT_DIF_N,657nymous_ ++B 6000,29000,300,300,CONT_DIF_N,711nymous_ ++B 4400,32000,300,300,CONT_VIA2,765nymous_ ++B 37000,19200,300,300,CONT_BODY_N,819nymous_ ++B 36800,6000,300,300,CONT_VIA2,873nymous_ ++B 34400,13000,300,300,CONT_VIA,927nymous_ ++B 25000,21600,300,300,CONT_DIF_P,1249ymous_ ++B 26000,17000,300,300,CONT_VIA,1195ymous_ ++B 33200,16000,300,300,CONT_BODY_N,981nymous_ ++B 32000,13000,300,300,CONT_DIF_P,1035ymous_ ++B 22400,8600,300,300,CONT_DIF_N,1303ymous_ ++B 1600,31400,300,300,CONT_BODY_P,443nymous_ ++B 17800,26800,300,300,CONT_DIF_N,389nymous_ ++B 11600,6000,300,300,CONT_VIA2,550nymous_ ++B 9200,32000,300,300,CONT_DIF_N,604nymous_ ++B 30400,36600,300,300,CONT_VIA2,1089ymous_ ++B 28000,35000,300,300,CONT_DIF_P,1143ymous_ ++B 14000,36000,300,300,CONT_DIF_N,497nymous_ ++B 7600,29000,300,300,CONT_VIA,658nymous_ ++B 6000,28000,300,300,CONT_DIF_N,712nymous_ ++B 4400,32000,300,300,CONT_VIA,766nymous_ ++B 37000,36000,300,300,CONT_VIA,820nymous_ ++B 36800,6000,300,300,CONT_VIA,874nymous_ ++B 26000,16000,300,300,CONT_BODY_N,1196ymous_ ++B 34400,13000,300,300,CONT_DIF_P,928nymous_ ++B 33200,14000,300,300,CONT_DIF_P,982nymous_ ++B 22400,6000,300,300,CONT_VIA2,1304ymous_ ++B 25000,20400,300,300,CONT_VIA,1250ymous_ ++B 32000,8000,300,300,CONT_DIF_N,1036ymous_ ++B 30400,36600,300,300,CONT_VIA,1090ymous_ ++B 1600,30400,300,300,CONT_BODY_P,444nymous_ ++B 17800,25600,300,300,CONT_VIA2,390nymous_ ++B 11600,6000,300,300,CONT_VIA,551nymous_ ++B 9200,31000,300,300,CONT_DIF_N,605nymous_ ++B 28000,33600,300,300,CONT_DIF_P,1144ymous_ ++B 14000,35000,300,300,CONT_DIF_N,498nymous_ ++B 7600,29000,300,300,CONT_DIF_N,659nymous_ ++B 6000,27000,300,300,CONT_DIF_N,713nymous_ ++B 4400,32000,300,300,CONT_DIF_N,767nymous_ ++B 37000,36000,300,300,CONT_DIF_P,821nymous_ ++B 36800,6000,300,300,CONT_BODY_P,875nymous_ ++B 26000,14000,300,300,CONT_VIA2,1197ymous_ ++B 34400,8000,300,300,CONT_DIF_N,929nymous_ ++B 33200,13000,300,300,CONT_DIF_P,983nymous_ ++B 22400,6000,300,300,CONT_VIA,1305ymous_ ++B 25000,20400,300,300,CONT_DIF_P,1251ymous_ ++B 17800,25600,300,300,CONT_VIA,391nymous_ ++B 11600,6000,300,300,CONT_BODY_P,552nymous_ ++B 32000,6000,300,300,CONT_VIA2,1037ymous_ ++B 30400,36600,300,300,CONT_POLY,1091ymous_ ++B 14000,34000,300,300,CONT_DIF_N,499nymous_ ++B 28000,32400,300,300,CONT_DIF_P,1145ymous_ ++B 1600,29400,300,300,CONT_BODY_P,445nymous_ ++B 9200,30000,300,300,CONT_DIF_N,606nymous_ ++B 7600,28000,300,300,CONT_VIA,660nymous_ ++B 6000,26000,300,300,CONT_DIF_N,714nymous_ ++B 4400,31000,300,300,CONT_VIA2,768nymous_ ++B 37000,35000,300,300,CONT_VIA2,822nymous_ ++B 3600,19200,300,300,CONT_BODY_P,876nymous_ ++B 34400,6000,300,300,CONT_VIA2,930nymous_ ++B 24800,16000,300,300,CONT_BODY_N,1252ymous_ ++B 26000,14000,300,300,CONT_DIF_P,1198ymous_ ++B 33200,8000,300,300,CONT_DIF_N,984nymous_ ++B 32000,6000,300,300,CONT_VIA,1038ymous_ ++B 22400,6000,300,300,CONT_BODY_P,1306ymous_ ++B 17800,25600,300,300,CONT_DIF_N,392nymous_ ++B 10800,36000,300,300,CONT_DIF_N,553nymous_ ++B 30000,19200,300,300,CONT_BODY_N,1092ymous_ ++B 28000,31200,300,300,CONT_VIA,1146ymous_ ++B 14000,33000,300,300,CONT_DIF_N,500nymous_ ++B 1600,28400,300,300,CONT_BODY_P,446nymous_ ++B 9200,29000,300,300,CONT_DIF_N,607nymous_ ++B 7600,28000,300,300,CONT_DIF_N,661nymous_ ++B 6000,25000,300,300,CONT_DIF_N,715nymous_ ++B 4400,31000,300,300,CONT_VIA,769nymous_ ++B 37000,35000,300,300,CONT_VIA,823nymous_ ++B 3600,37600,300,300,CONT_VIA2,877nymous_ ++B 34400,6000,300,300,CONT_VIA,931nymous_ ++B 24800,14000,300,300,CONT_VIA,1253ymous_ ++B 26000,13000,300,300,CONT_VIA2,1199ymous_ ++B 33200,6000,300,300,CONT_VIA2,985nymous_ ++B 32000,6000,300,300,CONT_BODY_P,1039ymous_ ++B 30000,20200,300,300,CONT_VIA,1093ymous_ ++B 22000,19200,300,300,CONT_VIA,1307ymous_ ++B 1600,27400,300,300,CONT_BODY_P,447nymous_ ++B 17800,24400,300,300,CONT_VIA2,393nymous_ ++B 10800,35000,300,300,CONT_DIF_N,554nymous_ ++B 9200,28000,300,300,CONT_DIF_N,608nymous_ ++B 28000,31200,300,300,CONT_DIF_P,1147ymous_ ++B 14000,32000,300,300,CONT_DIF_N,501nymous_ ++B 7600,27000,300,300,CONT_VIA,662nymous_ ++B 6000,24000,300,300,CONT_DIF_N,716nymous_ ++B 4400,31000,300,300,CONT_DIF_N,770nymous_ ++B 37000,35000,300,300,CONT_DIF_P,824nymous_ ++B 3600,37600,300,300,CONT_VIA,878nymous_ ++B 26000,13000,300,300,CONT_DIF_P,1200ymous_ ++B 34400,6000,300,300,CONT_BODY_P,932nymous_ ++B 33200,6000,300,300,CONT_VIA,986nymous_ ++B 22000,22200,300,300,CONT_VIA,1308ymous_ ++B 24800,14000,300,300,CONT_DIF_P,1254ymous_ ++B 31800,12200,300,300,CONT_POLY,1040ymous_ ++B 29600,17000,300,300,CONT_VIA2,1094ymous_ ++B 1600,26400,300,300,CONT_BODY_P,448nymous_ ++B 17800,24400,300,300,CONT_DIF_N,394nymous_ ++B 10800,34000,300,300,CONT_DIF_N,555nymous_ ++B 9200,27000,300,300,CONT_DIF_N,609nymous_ ++B 28000,30000,300,300,CONT_DIF_P,1148ymous_ ++B 14000,31000,300,300,CONT_DIF_N,502nymous_ ++B 7600,27000,300,300,CONT_DIF_N,663nymous_ ++B 6000,23000,300,300,CONT_DIF_N,717nymous_ ++B 4400,30000,300,300,CONT_VIA2,771nymous_ ++B 37000,34000,300,300,CONT_VIA2,825nymous_ ++B 3600,37600,300,300,CONT_BODY_P,879nymous_ ++B 26000,12000,300,300,CONT_VIA2,1201ymous_ ++B 3400,36000,300,300,CONT_VIA2,933nymous_ ++B 33200,6000,300,300,CONT_BODY_P,987nymous_ ++B 21200,16000,300,300,CONT_BODY_N,1309ymous_ ++B 24800,13000,300,300,CONT_VIA,1255ymous_ ++B 17800,23200,300,300,CONT_VIA,395nymous_ ++B 10800,33000,300,300,CONT_DIF_N,556nymous_ ++B 31800,9000,300,300,CONT_POLY,1041ymous_ ++B 29600,17000,300,300,CONT_VIA,1095ymous_ ++B 14000,30000,300,300,CONT_DIF_N,503nymous_ ++B 1600,25400,300,300,CONT_BODY_P,449nymous_ ++B 9200,26000,300,300,CONT_DIF_N,610nymous_ ++B 7600,26000,300,300,CONT_VIA2,664nymous_ ++B 28000,28800,300,300,CONT_DIF_P,1149ymous_ ++B 5600,19200,300,300,CONT_BODY_P,718nymous_ ++B 4400,30000,300,300,CONT_VIA,772nymous_ ++B 37000,34000,300,300,CONT_VIA,826nymous_ ++B 36000,19200,300,300,CONT_BODY_N,880nymous_ ++B 3400,32000,300,300,CONT_VIA2,934nymous_ ++B 24800,13000,300,300,CONT_DIF_P,1256ymous_ ++B 26000,8000,300,300,CONT_DIF_N,1202ymous_ ++B 33000,19200,300,300,CONT_BODY_N,988nymous_ ++B 31600,35000,300,300,CONT_VIA2,1042ymous_ ++B 21200,9000,300,300,CONT_DIF_N,1310ymous_ ++B 17800,23200,300,300,CONT_DIF_N,396nymous_ ++B 10800,32000,300,300,CONT_DIF_N,557nymous_ ++B 29600,16000,300,300,CONT_VIA,1096ymous_ ++B 28000,27600,300,300,CONT_DIF_P,1150ymous_ ++B 14000,29000,300,300,CONT_DIF_N,504nymous_ ++B 1600,24400,300,300,CONT_BODY_P,450nymous_ ++B 9200,25000,300,300,CONT_DIF_N,611nymous_ ++B 7600,26000,300,300,CONT_VIA,665nymous_ ++B 5600,17000,300,300,CONT_VIA2,719nymous_ ++B 4400,30000,300,300,CONT_DIF_N,773nymous_ ++B 37000,34000,300,300,CONT_DIF_P,827nymous_ ++B 36000,35000,300,300,CONT_VIA2,881nymous_ ++B 3400,31000,300,300,CONT_VIA2,935nymous_ ++B 24800,8000,300,300,CONT_DIF_N,1257ymous_ ++B 26000,6000,300,300,CONT_VIA2,1203ymous_ ++B 32800,35000,300,300,CONT_VIA2,989nymous_ ++B 31600,34000,300,300,CONT_VIA2,1043ymous_ ++B 21200,6000,300,300,CONT_VIA2,1311ymous_ ++B 1600,23400,300,300,CONT_BODY_P,451nymous_ ++B 17600,19200,300,300,CONT_BODY_P,397nymous_ ++B 10800,31000,300,300,CONT_DIF_N,558nymous_ ++B 9200,24000,300,300,CONT_DIF_N,612nymous_ ++B 29600,16000,300,300,CONT_BODY_N,1097ymous_ ++B 28000,26400,300,300,CONT_DIF_P,1151ymous_ ++B 14000,28000,300,300,CONT_DIF_N,505nymous_ ++B 7600,26000,300,300,CONT_DIF_N,666nymous_ ++B 5600,17000,300,300,CONT_VIA,720nymous_ ++B 4400,29000,300,300,CONT_VIA,774nymous_ ++B 37000,33000,300,300,CONT_VIA2,828nymous_ ++B 36000,34000,300,300,CONT_VIA2,882nymous_ ++B 26000,6000,300,300,CONT_VIA,1204ymous_ ++B 3400,30000,300,300,CONT_VIA2,936nymous_ ++B 32800,34000,300,300,CONT_VIA2,990nymous_ ++B 21200,6000,300,300,CONT_VIA,1312ymous_ ++B 24800,6000,300,300,CONT_VIA2,1258ymous_ ++B 31600,33000,300,300,CONT_VIA2,1044ymous_ ++B 29600,14000,300,300,CONT_DIF_P,1098ymous_ ++B 3400,25000,300,300,CONT_VIA2,938nymous_ ++B 36000,29000,300,300,CONT_VIA2,884nymous_ ++B 37000,33000,300,300,CONT_DIF_P,830nymous_ ++B 4400,28000,300,300,CONT_VIA,776nymous_ ++B 5600,13800,300,300,CONT_DIF_P,722nymous_ ++B 28000,24000,300,300,CONT_DIF_P,1153ymous_ ++B 7600,25000,300,300,CONT_VIA,668nymous_ ++B 8800,37600,300,300,CONT_VIA2,614nymous_ ++B 1600,21400,300,300,CONT_BODY_P,453nymous_ ++B 14000,26000,300,300,CONT_DIF_N,507nymous_ ++B 29600,13000,300,300,CONT_DIF_P,1099ymous_ ++B 31600,29000,300,300,CONT_VIA2,1045ymous_ ++B 10800,29000,300,300,CONT_DIF_N,560nymous_ ++B 17600,17000,300,300,CONT_VIA,399nymous_ ++B 24800,6000,300,300,CONT_VIA,1259ymous_ ++B 21200,6000,300,300,CONT_BODY_P,1313ymous_ ++B 32800,33000,300,300,CONT_VIA2,991nymous_ ++B 3400,26000,300,300,CONT_VIA2,937nymous_ ++B 26000,6000,300,300,CONT_BODY_P,1205ymous_ ++B 1600,22400,300,300,CONT_BODY_P,452nymous_ ++B 17600,17000,300,300,CONT_VIA2,398nymous_ ++B 10800,30000,300,300,CONT_DIF_N,559nymous_ ++B 9200,23000,300,300,CONT_DIF_N,613nymous_ ++B 28000,25200,300,300,CONT_DIF_P,1152ymous_ ++B 14000,27000,300,300,CONT_DIF_N,506nymous_ ++B 7600,25000,300,300,CONT_VIA2,667nymous_ ++B 5600,16000,300,300,CONT_BODY_N,721nymous_ ++B 4400,29000,300,300,CONT_DIF_N,775nymous_ ++B 37000,33000,300,300,CONT_VIA,829nymous_ ++B 36000,33000,300,300,CONT_VIA2,883nymous_ ++B 28000,21600,300,300,CONT_DIF_P,1155ymous_ ++B 29600,10600,300,300,CONT_POLY,1101ymous_ ++B 8800,37600,300,300,CONT_BODY_P,616nymous_ ++B 10800,27000,300,300,CONT_DIF_N,562nymous_ ++B 17600,12800,300,300,CONT_DIF_P,401nymous_ ++B 15800,37600,300,300,CONT_BODY_P,455nymous_ ++B 20800,37600,300,300,CONT_BODY_P,1315ymous_ ++B 31600,27000,300,300,CONT_VIA2,1047ymous_ ++B 32800,28000,300,300,CONT_VIA2,993nymous_ ++B 26000,36400,300,300,CONT_DIF_P,1207ymous_ ++B 24000,19200,300,300,CONT_BODY_N,1261ymous_ ++B 3400,24000,300,300,CONT_VIA2,939nymous_ ++B 36000,28000,300,300,CONT_VIA2,885nymous_ ++B 37000,32000,300,300,CONT_VIA,831nymous_ ++B 4400,28000,300,300,CONT_DIF_N,777nymous_ ++B 5600,12800,300,300,CONT_DIF_P,723nymous_ ++B 7600,25000,300,300,CONT_DIF_N,669nymous_ ++B 8800,37600,300,300,CONT_VIA,615nymous_ ++B 1600,20400,300,300,CONT_BODY_P,454nymous_ ++B 14000,25000,300,300,CONT_DIF_N,508nymous_ ++B 28000,22800,300,300,CONT_DIF_P,1154ymous_ ++B 29600,10600,300,300,CONT_VIA,1100ymous_ ++B 10800,28000,300,300,CONT_DIF_N,561nymous_ ++B 17600,16000,300,300,CONT_BODY_N,400nymous_ ++B 20800,19200,300,300,CONT_BODY_P,1314ymous_ ++B 31600,28000,300,300,CONT_VIA2,1046ymous_ ++B 32800,29000,300,300,CONT_VIA2,992nymous_ ++B 26000,37600,300,300,CONT_BODY_N,1206ymous_ ++B 24800,6000,300,300,CONT_BODY_P,1260ymous_ ++B 5600,37600,300,300,CONT_VIA,731nymous_ ++B 31600,22000,300,300,CONT_VIA2,1049ymous_ ++B 24000,35800,300,300,CONT_VIA,1263ymous_ ++B 20800,35400,300,300,CONT_BODY_P,1317ymous_ ++B 32800,23000,300,300,CONT_VIA2,995nymous_ ++B 33800,36000,300,300,CONT_VIA,941nymous_ ++B 26000,33600,300,300,CONT_VIA,1209ymous_ ++B 36000,23000,300,300,CONT_VIA2,887nymous_ ++B 37000,31000,300,300,CONT_VIA,833nymous_ ++B 4400,27000,300,300,CONT_DIF_N,779nymous_ ++B 5600,9000,300,300,CONT_DIF_N,725nymous_ ++B 7600,24000,300,300,CONT_VIA,671nymous_ ++B 14000,23000,300,300,CONT_DIF_N,510nymous_ ++B 28000,20400,300,300,CONT_DIF_P,1156ymous_ ++B 8600,19200,300,300,CONT_BODY_P,617nymous_ ++B 10800,26000,300,300,CONT_DIF_N,563nymous_ ++B 17600,8600,300,300,CONT_DIF_N,402nymous_ ++B 15800,29000,300,300,CONT_VIA2,456nymous_ ++B 29600,7000,300,300,CONT_DIF_N,1102ymous_ ++B 31600,23000,300,300,CONT_VIA2,1048ymous_ ++B 24000,37600,300,300,CONT_BODY_N,1262ymous_ ++B 20800,36400,300,300,CONT_BODY_P,1316ymous_ ++B 32800,27000,300,300,CONT_VIA2,994nymous_ ++B 34000,19200,300,300,CONT_BODY_N,940nymous_ ++B 26000,35000,300,300,CONT_DIF_P,1208ymous_ ++B 36000,27000,300,300,CONT_VIA2,886nymous_ ++B 37000,32000,300,300,CONT_DIF_P,832nymous_ ++B 4400,27000,300,300,CONT_VIA,778nymous_ ++B 5600,11800,300,300,CONT_DIF_P,724nymous_ ++B 7600,24000,300,300,CONT_VIA2,670nymous_ ++B 14000,24000,300,300,CONT_DIF_N,509nymous_ ++B 27000,36400,300,300,CONT_VIA,1175ymous_ ++B 37000,30000,300,300,CONT_VIA,835nymous_ ++B 4400,26000,300,300,CONT_VIA,781nymous_ ++B 5600,6000,300,300,CONT_VIA2,727nymous_ ++B 7600,23000,300,300,CONT_VIA,673nymous_ ++B 8600,32000,300,300,CONT_VIA2,619nymous_ ++B 15800,27000,300,300,CONT_VIA2,458nymous_ ++B 14000,21800,300,300,CONT_VIA,512nymous_ ++B 28000,0,300,300,CONT_VIA3,1158ymous_ ++B 29600,34000,300,300,CONT_VIA2,1104ymous_ ++B 10800,24000,300,300,CONT_DIF_N,565nymous_ ++B 17600,6000,300,300,CONT_VIA,404nymous_ ++B 20800,34400,300,300,CONT_BODY_P,1318ymous_ ++B 31600,20200,300,300,CONT_POLY,1050ymous_ ++B 32800,22000,300,300,CONT_VIA2,996nymous_ ++B 26000,33600,300,300,CONT_DIF_P,1210ymous_ ++B 24000,35800,300,300,CONT_POLY,1264ymous_ ++B 33800,36000,300,300,CONT_DIF_P,942nymous_ ++B 36000,22000,300,300,CONT_VIA2,888nymous_ ++B 37000,31000,300,300,CONT_DIF_P,834nymous_ ++B 4400,26000,300,300,CONT_VIA2,780nymous_ ++B 5600,8000,300,300,CONT_DIF_N,726nymous_ ++B 28000,0,300,300,CONT_VIA4,1157ymous_ ++B 7600,24000,300,300,CONT_DIF_N,672nymous_ ++B 8600,36000,300,300,CONT_VIA2,618nymous_ ++B 15800,28000,300,300,CONT_VIA2,457nymous_ ++B 14000,21800,300,300,CONT_VIA2,511nymous_ ++B 29600,35000,300,300,CONT_VIA2,1103ymous_ ++B 10800,25000,300,300,CONT_DIF_N,564nymous_ ++B 17600,6000,300,300,CONT_VIA2,403nymous_ ++B 11600,17000,300,300,CONT_VIA2,541nymous_ ++B 18800,6000,300,300,CONT_VIA,354nymous_ ++B 18800,6000,300,300,CONT_BODY_P,355nymous_ ++B 13600,19200,300,300,CONT_BODY_P,514nymous_ ++B 27800,37600,300,300,CONT_BODY_N,1160ymous_ ++B 8600,30000,300,300,CONT_VIA2,621nymous_ ++B 10800,21800,300,300,CONT_VIA2,567nymous_ ++B 17400,11800,300,300,CONT_POLY,406nymous_ ++B 15600,36000,300,300,CONT_DIF_N,460nymous_ ++B 29000,19200,300,300,CONT_BODY_N,1106ymous_ ++B 30800,17000,300,300,CONT_VIA2,1052ymous_ ++B 24000,34200,300,300,CONT_VIA,1266ymous_ ++B 20800,32400,300,300,CONT_BODY_P,1320ymous_ ++B 32200,36000,300,300,CONT_DIF_P,998nymous_ ++B 33800,35000,300,300,CONT_VIA,944nymous_ ++B 26000,31200,300,300,CONT_VIA,1212ymous_ ++B 35600,17000,300,300,CONT_VIA2,890nymous_ ++B 37000,30000,300,300,CONT_DIF_P,836nymous_ ++B 4400,26000,300,300,CONT_DIF_N,782nymous_ ++B 5600,6000,300,300,CONT_VIA,728nymous_ ++B 7600,23000,300,300,CONT_DIF_N,674nymous_ ++B 14000,21800,300,300,CONT_POLY,513nymous_ ++B 28000,0,300,300,CONT_VIA2,1159ymous_ ++B 29600,33000,300,300,CONT_VIA2,1105ymous_ ++B 8600,31000,300,300,CONT_VIA2,620nymous_ ++B 10800,23000,300,300,CONT_DIF_N,566nymous_ ++B 17600,6000,300,300,CONT_BODY_P,405nymous_ ++B 15600,19200,300,300,CONT_BODY_P,459nymous_ ++B 20800,33400,300,300,CONT_BODY_P,1319ymous_ ++B 31000,19200,300,300,CONT_BODY_N,1051ymous_ ++B 32800,20200,300,300,CONT_POLY,997nymous_ ++B 26000,32400,300,300,CONT_DIF_P,1211ymous_ ++B 24000,34200,300,300,CONT_VIA2,1265ymous_ ++B 33800,35000,300,300,CONT_VIA2,943nymous_ ++B 36000,20200,300,300,CONT_POLY,889nymous_ ++B 33800,35000,300,300,CONT_DIF_P,945nymous_ ++B 26000,31200,300,300,CONT_DIF_P,1213ymous_ ++B 35600,17000,300,300,CONT_VIA,891nymous_ ++B 37000,29000,300,300,CONT_VIA2,837nymous_ ++B 4400,25000,300,300,CONT_VIA2,783nymous_ ++B 5600,6000,300,300,CONT_BODY_P,729nymous_ ++B 7600,21800,300,300,CONT_VIA,675nymous_ ++B 32200,35000,300,300,CONT_DIF_P,999nymous_ ++B 20800,31400,300,300,CONT_BODY_P,1321ymous_ ++B 24000,34200,300,300,CONT_POLY,1267ymous_ ++B 16800,37600,300,300,CONT_BODY_P,407nymous_ ++B 10800,21800,300,300,CONT_VIA,568nymous_ ++B 30800,17000,300,300,CONT_VIA,1053ymous_ ++B 29000,33000,300,300,CONT_POLY,1107ymous_ ++B 12800,17000,300,300,CONT_VIA2,515nymous_ ++B 15600,35000,300,300,CONT_DIF_N,461nymous_ ++B 8600,26000,300,300,CONT_VIA2,622nymous_ ++B 7600,21800,300,300,CONT_POLY,676nymous_ ++B 27800,36400,300,300,CONT_DIF_P,1161ymous_ ++B 5600,37600,300,300,CONT_VIA2,730nymous_ ++B 4400,25000,300,300,CONT_VIA,784nymous_ ++B 37000,29000,300,300,CONT_VIA,838nymous_ ++B 35600,16000,300,300,CONT_BODY_N,892nymous_ ++B 33800,34000,300,300,CONT_VIA2,946nymous_ ++EOF +diff --git a/alliance/src/cells/src/mpxlib/po_mpx.vbe b/alliance/src/cells/src/mpxlib/po_mpx.vbe +new file mode 100644 +index 0000000..91d5df8 +--- /dev/null ++++ b/alliance/src/cells/src/mpxlib/po_mpx.vbe +@@ -0,0 +1,29 @@ ++ENTITY po_mpx IS ++ GENERIC ( ++ CONSTANT area : NATURAL := 80000; ++ CONSTANT cin_i : NATURAL := 191; ++ CONSTANT tpll_i : NATURAL := 2176; ++ CONSTANT rdown_i : NATURAL := 15; ++ CONSTANT tphh_i : NATURAL := 2032; ++ CONSTANT rup_i : NATURAL := 16 ++ ); ++ PORT ( ++ i : in BIT; ++ pad : out BIT; ++ ck : in BIT; ++ vdde : in BIT; ++ vddi : in BIT; ++ vsse : in BIT; ++ vssi : in BIT ++ ); ++END po_mpx; ++ ++ARCHITECTURE behaviour_data_flow OF po_mpx IS ++ ++BEGIN ++ pad <= i; ++ ++ ASSERT ((((vddi and vdde) and not (vssi)) and not (vsse)) = '1') ++ REPORT "power supply is missing on po_mpx" ++ SEVERITY WARNING; ++END; +diff --git a/alliance/src/cells/src/mpxlib/pot_mpx.ap b/alliance/src/cells/src/mpxlib/pot_mpx.ap +new file mode 100644 +index 0000000..161daf8 +--- /dev/null ++++ b/alliance/src/cells/src/mpxlib/pot_mpx.ap +@@ -0,0 +1,1543 @@ ++V ALLIANCE : 6 ++H pot_mpx,P,14/9/2014,100 ++A 0,0,40000,80000 ++I 0,40000,padreal_mpx,padreal,NOSYM ++S 28800,9000,29000,9000,200,i,RIGHT,POLY ++S 28000,-300,28000,10900,400,i,UP,ALU2 ++S 28000,0,28000,0,400,i,RIGHT,CALU5 ++S 28000,0,28000,0,400,i,RIGHT,CALU4 ++S 27800,11800,28200,11800,200,i,RIGHT,POLY ++S 30000,-100,30000,10900,400,b,UP,ALU2 ++S 30000,0,30000,0,400,b,RIGHT,CALU5 ++S 30000,0,30000,0,400,b,RIGHT,CALU4 ++S 29600,9800,29600,11400,200,b,UP,POLY ++S 29000,35100,29000,39700,400,pad,UP,ALU1 ++S 29000,25900,29000,34900,400,pad,UP,ALU1 ++S 28600,33000,29000,33000,600,pad,RIGHT,POLY ++S 28600,31800,29000,31800,600,pad,RIGHT,POLY ++S 28600,30600,29000,30600,600,pad,RIGHT,POLY ++S 28600,25800,29000,25800,600,pad,RIGHT,POLY ++S 20000,48100,20000,71900,24400,pad,UP,CALU1 ++S 700,4000,39300,4000,1000,ck,RIGHT,CALU3 ++S 16800,33400,17200,33400,200,vdde,RIGHT,POLY ++S 700,28000,39300,28000,2400,vdde,RIGHT,CALU3 ++S 700,22000,39300,22000,2400,vdde,RIGHT,CALU3 ++S 3600,22200,5200,22200,200,vdde,RIGHT,POLY ++S 25100,28800,27900,28800,400,vdde,RIGHT,ALU1 ++S 25100,26400,27900,26400,400,vdde,RIGHT,ALU1 ++S 700,34000,39300,34000,2400,vdde,RIGHT,CALU3 ++S 6800,22200,8400,22200,200,vdde,RIGHT,POLY ++S 25100,21600,27900,21600,400,vdde,RIGHT,ALU1 ++S 24000,35800,24400,35800,600,vdde,RIGHT,POLY ++S 24000,34200,24400,34200,600,vdde,RIGHT,POLY ++S 16800,32200,17200,32200,200,vdde,RIGHT,POLY ++S 16800,35800,17200,35800,200,vdde,RIGHT,POLY ++S 16800,34600,17200,34600,200,vdde,RIGHT,POLY ++S 16800,29900,16800,38300,400,vdde,UP,ALU2 ++S 10500,21800,14300,21800,400,vdde,RIGHT,ALU2 ++S 25100,24000,27900,24000,400,vdde,RIGHT,ALU1 ++S 700,16000,39300,16000,2400,vddi,RIGHT,CALU3 ++S 700,10000,39300,10000,2400,vddi,RIGHT,CALU3 ++S 3100,16000,36900,16000,2400,vddi,RIGHT,ALU1 ++S 20000,9600,20000,11000,200,vddi,UP,POLY ++S 17800,22900,17800,31900,400,vsse,UP,ALU2 ++S 700,19000,39300,19000,2400,vsse,RIGHT,CALU3 ++S 700,37000,39300,37000,2400,vsse,RIGHT,CALU3 ++S 700,31000,39300,31000,2400,vsse,RIGHT,CALU3 ++S 700,25000,39300,25000,2400,vsse,RIGHT,CALU3 ++S 7600,22900,7600,37500,400,vsse,UP,ALU1 ++S 4400,22900,4400,37500,400,vsse,UP,ALU1 ++S 30400,36400,30400,36600,200,vsse,UP,POLY ++S 20800,22900,20800,37100,400,vsse,UP,ALU1 ++S 700,13000,39300,13000,2400,vssi,RIGHT,CALU3 ++S 700,7000,39300,7000,2400,vssi,RIGHT,CALU3 ++S 3100,6000,36900,6000,2400,vssi,RIGHT,ALU1 ++S 17500,22600,19100,22600,200,n6d,RIGHT,NTRANS ++S 28500,8000,30700,8000,400,93onymous_,RIGHT,ALU1 ++S 28400,7500,28400,8100,620,92onymous_,UP,NDIF ++S 7300,21800,10100,21800,400,211nymous_,RIGHT,ALU2 ++S 31700,6000,37100,6000,400,127nymous_,RIGHT,ALU2 ++S 28300,9000,28700,9000,400,91onymous_,RIGHT,ALU1 ++S 10800,22900,10800,39700,400,249nymous_,UP,ALU1 ++S 35600,200,35600,12000,9000,11onymous_,UP,TALU5 ++S 17700,8000,22300,8000,400,321nymous_,RIGHT,ALU1 ++S 15800,9600,15800,10800,200,285nymous_,UP,POLY ++S 24900,30000,28100,30000,420,52onymous_,RIGHT,PDIF ++S 24900,31200,28100,31200,420,53onymous_,RIGHT,PDIF ++S 0,6000,40000,6000,12000,12onymous_,RIGHT,TALU6 ++S 35600,13100,35600,15900,400,169nymous_,UP,ALU1 ++S 10800,22700,10800,36500,620,248nymous_,UP,NDIF ++S 1700,37600,9500,37600,400,286nymous_,RIGHT,ALU1 ++S 20000,40100,20000,59900,4400,13onymous_,UP,ALU1 ++S 31800,12000,31800,12200,200,126nymous_,UP,POLY ++S 7600,21800,7600,22200,600,210nymous_,UP,POLY ++S 17700,36400,18900,36400,620,320nymous_,RIGHT,NDIF ++S 24900,28800,28100,28800,420,51onymous_,RIGHT,PDIF ++S 29000,200,29000,12000,0,10onymous_,UP,TALU5 ++S 17700,35200,18900,35200,620,319nymous_,RIGHT,NDIF ++S 17700,34000,18900,34000,620,318nymous_,RIGHT,NDIF ++S 35000,12700,35000,14700,200,p5b,UP,PTRANS ++S 27800,12500,27800,14500,200,p1,UP,PTRANS ++S 35000,7300,35000,8300,200,n5b,UP,NTRANS ++S 6800,22500,6800,36700,200,n14c,UP,NTRANS ++S 30800,10600,33800,10600,200,cnbb,RIGHT,POLY ++S 30800,8100,30800,12900,400,cnbb,UP,ALU1 ++S 6200,10900,6200,14900,200,p18b,UP,PTRANS ++S 14800,22500,14800,36700,200,n15d,UP,NTRANS ++S 14600,11100,14600,13100,200,p17c,UP,PTRANS ++S 31400,35300,31400,36100,200,p11,UP,PTRANS ++S 31400,20900,31400,34300,200,p14a,UP,PTRANS ++S 20800,19300,20800,37500,400,17onymous_,UP,ALU1 ++S 8000,7500,8000,9100,420,215nymous_,UP,NDIF ++S 20000,6300,20000,8500,400,14onymous_,UP,ALU1 ++S 24900,33600,28100,33600,420,55onymous_,RIGHT,PDIF ++S 1700,19200,20700,19200,400,287nymous_,RIGHT,ALU1 ++S 17600,12500,17600,12900,620,324nymous_,UP,PDIF ++S 35300,17000,37100,17000,400,170nymous_,RIGHT,ALU2 ++S 24900,32400,28100,32400,420,54onymous_,RIGHT,PDIF ++S 17600,8500,17600,9100,620,323nymous_,UP,NDIF ++S 17600,8100,17600,8500,400,322nymous_,UP,ALU1 ++S 36000,20200,36000,20600,600,171nymous_,UP,POLY ++S 17700,12800,18300,12800,400,325nymous_,RIGHT,ALU1 ++S 1480,19200,20920,19200,600,288nymous_,RIGHT,PTIE ++S 24900,35000,28100,35000,820,56onymous_,RIGHT,PDIF ++S 32000,7500,32000,8100,620,128nymous_,UP,NDIF ++S 1600,19300,1600,37500,400,289nymous_,UP,ALU1 ++S 7600,22700,7600,36500,620,212nymous_,UP,NDIF ++S 24900,36400,28100,36400,620,57onymous_,RIGHT,PDIF ++S 11000,9600,11000,10600,200,250nymous_,UP,POLY ++S 3600,22200,5200,22200,200,172nymous_,RIGHT,POLY ++S 31700,7600,37100,7600,1200,129nymous_,RIGHT,ALU2 ++S 20000,11100,20000,15900,400,15onymous_,UP,ALU1 ++S 7600,22900,7600,37500,400,213nymous_,UP,ALU1 ++S 1600,19080,1600,37720,600,290nymous_,UP,PTIE ++S 28400,12700,28400,14300,620,94onymous_,UP,PDIF ++S 24800,7500,24800,8100,620,58onymous_,UP,NDIF ++S 3480,16000,36920,16000,600,173nymous_,RIGHT,NTIE ++S 32000,8100,32000,12900,400,130nymous_,UP,ALU1 ++S 20000,12700,20000,17300,400,16onymous_,UP,ALU2 ++S 7600,22700,7600,38300,2400,214nymous_,UP,ALU2 ++S 25400,8600,25400,12400,200,62onymous_,UP,POLY ++S 17900,25600,18700,25600,400,329nymous_,RIGHT,ALU1 ++S 16400,6100,16400,8900,400,292nymous_,UP,ALU1 ++S 32000,12900,32000,14500,620,131nymous_,UP,PDIF ++S 24800,8100,24800,13900,400,59onymous_,UP,ALU1 ++S 28400,14100,28400,15900,400,95onymous_,UP,ALU1 ++S 17900,24400,18700,24400,400,328nymous_,RIGHT,ALU1 ++S 16400,29900,16400,32300,400,291nymous_,UP,ALU2 ++S 17900,23200,18700,23200,400,327nymous_,RIGHT,ALU1 ++S 2900,20600,15500,20600,400,pad2,RIGHT,ALU1 ++S 2700,20600,15700,20600,400,pad2,RIGHT,ALU1 ++S 20000,8500,20000,9100,620,pad2,UP,NDIF ++S 17900,22000,18700,22000,400,326nymous_,RIGHT,ALU1 ++S 7400,7300,7400,9300,200,n18c,UP,NTRANS ++S 7400,10900,7400,14900,200,p18c,UP,PTRANS ++S 11600,6100,11600,8900,400,251nymous_,UP,ALU1 ++S 28700,24600,30300,24600,400,96onymous_,RIGHT,ALU2 ++S 24800,13100,24800,14500,620,60onymous_,UP,PDIF ++S 3200,5880,3200,8720,600,132nymous_,UP,PTIE ++S 36700,37600,38100,37600,400,174nymous_,RIGHT,ALU1 ++S 16400,7500,16400,9100,620,293nymous_,UP,NDIF ++S 8000,8100,8000,8900,400,216nymous_,UP,ALU1 ++S 11600,7500,11600,9100,420,252nymous_,UP,NDIF ++S 3200,6100,3200,9100,400,133nymous_,UP,ALU1 ++S 36800,5880,36800,8720,600,175nymous_,UP,PTIE ++S 25100,35000,29100,35000,400,61onymous_,RIGHT,ALU1 ++S 29000,8600,29000,9000,200,97onymous_,UP,POLY ++S 36800,6900,36800,17300,400,177nymous_,UP,ALU2 ++S 21200,8500,21200,9100,420,19onymous_,UP,NDIF ++S 36800,6100,36800,9100,400,176nymous_,UP,ALU1 ++S 20800,19080,20800,37720,600,18onymous_,UP,PTIE ++S 11600,11100,11600,14700,620,253nymous_,UP,PDIF ++S 8000,11100,8000,13700,400,217nymous_,UP,ALU1 ++S 16400,11300,16400,12900,620,294nymous_,UP,PDIF ++S 26000,30900,26000,37100,400,65onymous_,UP,ALU2 ++S 26000,23700,26000,29100,400,64onymous_,UP,ALU2 ++S 26000,21300,26000,24300,400,63onymous_,UP,ALU2 ++S 29000,18300,29000,19500,400,101nymous_,UP,ALU2 ++S 3600,22500,3600,36700,200,n14a,UP,NTRANS ++S 15800,11100,15800,13100,200,p17d,UP,PTRANS ++S 20600,8300,20600,9300,200,n16c,UP,NTRANS ++S 17900,26800,18700,26800,400,330nymous_,RIGHT,ALU1 ++S 17900,28000,18700,28000,400,331nymous_,RIGHT,ALU1 ++S 3200,5700,3200,16100,400,134nymous_,UP,ALU2 ++S 16400,12100,16400,15900,400,295nymous_,UP,ALU1 ++S 8000,11100,8000,14700,620,218nymous_,UP,PDIF ++S 17900,30400,18700,30400,400,332nymous_,RIGHT,ALU1 ++S 11600,11900,11600,15900,400,254nymous_,UP,ALU1 ++S 2900,6000,7100,6000,400,135nymous_,RIGHT,ALU2 ++S 17900,31600,18700,31600,400,333nymous_,RIGHT,ALU1 ++S 900,37000,8900,37000,2400,255nymous_,RIGHT,ALU2 ++S 21200,9100,21200,9900,400,20onymous_,UP,ALU1 ++S 2900,10000,6300,10000,2400,136nymous_,RIGHT,ALU2 ++S 36800,11100,36800,15900,400,178nymous_,UP,ALU1 ++S 900,19000,9300,19000,2400,256nymous_,RIGHT,ALU2 ++S 3200,11100,3200,15900,400,137nymous_,UP,ALU1 ++S 36800,10880,36800,16120,600,179nymous_,UP,NTIE ++S 8600,9600,8600,10600,200,219nymous_,UP,POLY ++S 22000,21900,22000,28500,400,21onymous_,UP,ALU2 ++S 29000,11400,29000,12200,200,98onymous_,UP,POLY ++S 37000,21100,37000,36500,620,180nymous_,UP,PDIF ++S 12200,9600,12200,10800,200,257nymous_,UP,POLY ++S 29000,11400,32600,11400,200,99onymous_,RIGHT,POLY ++S 9200,20700,9200,36300,400,220nymous_,UP,ALU1 ++S 28700,18200,34700,18200,400,100nymous_,RIGHT,ALU2 ++S 15800,7300,15800,9300,200,n17d,UP,NTRANS ++S 38200,19300,38200,37500,400,183nymous_,UP,ALU1 ++S 18200,9600,21800,9600,200,337nymous_,RIGHT,POLY ++S 36200,20900,36200,36700,200,p14d,UP,PTRANS ++S 11600,22500,11600,36700,200,n15b,UP,NTRANS ++S 11000,10900,11000,14900,200,p18f,UP,PTRANS ++S 13200,22200,14800,22200,200,cn,RIGHT,POLY ++S 10000,22200,11600,22200,200,cn,RIGHT,POLY ++S 4100,21800,7900,21800,400,cn,RIGHT,ALU2 ++S 25100,22800,27900,22800,400,cn,RIGHT,ALU1 ++S 25100,20400,27900,20400,400,cn,RIGHT,ALU1 ++S 25000,20100,25000,23100,400,cn,UP,ALU2 ++S 25100,37000,27900,37000,1600,fbul,RIGHT,ALU1 ++S 25100,25200,27900,25200,400,fbul,RIGHT,ALU1 ++S 16500,20200,24300,20200,400,296nymous_,RIGHT,ALU2 ++S 16800,20300,16800,23300,400,297nymous_,UP,ALU1 ++S 17900,34000,18700,34000,400,334nymous_,RIGHT,ALU1 ++S 16500,21200,25300,21200,400,298nymous_,RIGHT,ALU2 ++S 17900,36400,18700,36400,400,335nymous_,RIGHT,ALU1 ++S 3200,10880,3200,16120,600,138nymous_,UP,NTIE ++S 16800,20900,16800,24700,400,299nymous_,UP,ALU2 ++S 22000,17900,22000,19500,400,22onymous_,UP,ALU2 ++S 2900,15400,19300,15400,1200,139nymous_,RIGHT,ALU2 ++S 37000,21300,37000,36300,400,181nymous_,UP,ALU1 ++S 1800,17700,1800,38300,1600,336nymous_,UP,ALU2 ++S 21700,18200,25100,18200,400,23onymous_,RIGHT,ALU2 ++S 2900,17000,19100,17000,400,140nymous_,RIGHT,ALU2 ++S 37000,17700,37000,38300,2400,182nymous_,UP,ALU2 ++S 9200,22700,9200,36500,620,221nymous_,UP,NDIF ++S 22000,19300,22000,22100,400,24onymous_,UP,ALU1 ++S 32200,21100,32200,36500,620,141nymous_,UP,PDIF ++S 11000,7300,11000,9300,200,n18f,UP,NTRANS ++S 8900,6000,26300,6000,400,222nymous_,RIGHT,ALU2 ++S 12400,20700,12400,36300,400,258nymous_,UP,ALU1 ++S 22400,8100,22400,8500,400,25onymous_,UP,ALU1 ++S 29300,37000,31900,37000,2400,102nymous_,RIGHT,ALU2 ++S 29480,37600,38520,37600,600,103nymous_,RIGHT,NTIE ++S 26000,6100,26000,7900,400,66onymous_,UP,ALU1 ++S 26000,7500,26000,8100,620,67onymous_,UP,NDIF ++S 16800,24100,16800,29500,400,301nymous_,UP,ALU2 ++S 16800,23200,16800,25400,600,300nymous_,UP,POLY ++S 19500,36800,26300,36800,400,node_cp,RIGHT,ALU2 ++S 17900,35200,19700,35200,400,node_cp,RIGHT,ALU1 ++S 17900,32800,19700,32800,400,node_cp,RIGHT,ALU1 ++S 34600,20600,36200,20600,200,node_cp,RIGHT,POLY ++S 31400,20600,33000,20600,200,node_cp,RIGHT,POLY ++S 28600,24600,29000,24600,600,node_cp,RIGHT,POLY ++S 27700,24600,29300,24600,400,node_cp,RIGHT,ALU2 ++S 28000,24300,28000,31500,400,node_cp,UP,ALU2 ++S 25100,33600,27900,33600,400,node_cp,RIGHT,ALU1 ++S 25100,31200,27900,31200,400,node_cp,RIGHT,ALU1 ++S 21800,8300,21800,9300,200,n16d,UP,NTRANS ++S 18500,31600,25300,31600,400,cpd,RIGHT,ALU2 ++S 18800,21900,18800,36700,400,cpd,UP,ALU2 ++S 25100,32400,27900,32400,400,cpd,RIGHT,ALU1 ++S 25100,30000,27900,30000,400,cpd,RIGHT,ALU1 ++S 25100,27600,27900,27600,400,cpd,RIGHT,ALU1 ++S 25000,27300,25000,32700,400,cpd,UP,ALU2 ++S 29000,7300,29000,8300,200,n1,UP,NTRANS ++S 16900,24400,17700,24400,400,302nymous_,RIGHT,ALU1 ++S 32200,21300,32200,39700,400,142nymous_,UP,ALU1 ++S 38200,19080,38200,37920,600,184nymous_,UP,NTIE ++S 18400,10100,18400,12700,400,338nymous_,UP,ALU1 ++S 16800,25500,16800,28100,400,303nymous_,UP,ALU1 ++S 9200,6100,9200,7900,400,223nymous_,UP,ALU1 ++S 12400,22700,12400,36500,620,259nymous_,UP,NDIF ++S 3900,7600,7300,7600,1200,185nymous_,RIGHT,ALU2 ++S 18800,8500,18800,9100,420,339nymous_,UP,NDIF ++S 9200,5700,9200,11300,400,224nymous_,UP,ALU2 ++S 12400,18500,12400,22100,2400,260nymous_,UP,ALU2 ++S 32600,8600,32600,9800,200,143nymous_,UP,POLY ++S 22400,8500,22400,9100,620,26onymous_,UP,NDIF ++S 4400,21800,4400,22200,600,186nymous_,UP,POLY ++S 9200,7500,9200,9100,620,225nymous_,UP,NDIF ++S 18800,9100,18800,9900,400,340nymous_,UP,ALU1 ++S 12800,7500,12800,9100,620,261nymous_,UP,NDIF ++S 22100,17000,23700,17000,400,27onymous_,RIGHT,ALU2 ++S 32600,11400,32600,12400,200,144nymous_,UP,POLY ++S 4400,22700,4400,36500,620,187nymous_,UP,NDIF ++S 29600,7100,29600,8100,620,104nymous_,UP,NDIF ++S 8900,10000,26300,10000,2400,226nymous_,RIGHT,ALU2 ++S 12800,8100,12800,12500,400,262nymous_,UP,ALU1 ++S 23100,37600,27700,37600,400,28onymous_,RIGHT,ALU1 ++S 29300,10600,30300,10600,400,105nymous_,RIGHT,ALU2 ++S 32800,20200,32800,20600,600,145nymous_,UP,POLY ++S 17400,11800,17400,12000,200,307nymous_,UP,POLY ++S 17400,11100,17400,11700,400,306nymous_,UP,ALU1 ++S 25400,7300,25400,8300,200,n4b,UP,NTRANS ++S 29000,12500,29000,14500,200,p2,UP,PTRANS ++S 8600,10900,8600,14900,200,p18d,UP,PTRANS ++S 12200,7300,12200,9300,200,n17a,UP,NTRANS ++S 8600,7300,8600,9300,200,n18d,UP,NTRANS ++S 8400,22500,8400,36700,200,n14d,UP,NTRANS ++S 19500,28200,24300,28200,400,cpb,RIGHT,ALU2 ++S 19400,26200,19800,26200,200,cpb,RIGHT,POLY ++S 19400,22600,19800,22600,200,cpb,RIGHT,POLY ++S 24000,29200,24400,29200,600,cpb,RIGHT,POLY ++S 24000,28200,24400,28200,600,cpb,RIGHT,POLY ++S 19800,22700,19800,30900,400,cpb,UP,ALU1 ++S 19400,31000,19800,31000,200,cpb,RIGHT,POLY ++S 19400,27400,19800,27400,200,cpb,RIGHT,POLY ++S 24800,12700,24800,18500,400,cpb,UP,ALU2 ++S 24000,27000,24400,27000,600,cpb,RIGHT,POLY ++S 16800,28200,16800,29800,600,304nymous_,UP,POLY ++S 16900,29200,18700,29200,400,305nymous_,RIGHT,ALU1 ++S 18500,17000,20300,17000,400,341nymous_,RIGHT,ALU2 ++S 4400,22900,4400,37500,400,188nymous_,UP,ALU1 ++S 9200,11100,9200,14700,620,227nymous_,UP,PDIF ++S 12900,9000,15100,9000,400,263nymous_,RIGHT,ALU1 ++S 23000,11700,23000,17300,2000,29onymous_,UP,ALU2 ++S 12900,11000,17300,11000,400,264nymous_,RIGHT,ALU1 ++S 29600,12700,29600,14300,620,106nymous_,UP,PDIF ++S 4400,22700,4400,38300,2400,189nymous_,UP,ALU2 ++S 23000,19300,23000,37500,400,30onymous_,UP,ALU1 ++S 12800,11300,12800,12900,620,265nymous_,UP,PDIF ++S 29600,13100,29600,13900,400,107nymous_,UP,ALU1 ++S 4400,6100,4400,8900,400,190nymous_,UP,ALU1 ++S 19800,32900,19800,35100,400,342nymous_,UP,ALU1 ++S 33200,6100,33200,7900,400,146nymous_,UP,ALU1 ++S 23000,19080,23000,37920,600,31onymous_,UP,NTIE ++S 33200,7500,33200,8100,620,147nymous_,UP,NDIF ++S 26000,8700,26000,14300,400,68onymous_,UP,ALU2 ++S 19800,34900,19800,37100,400,343nymous_,UP,ALU2 ++S 33200,12900,33200,14500,620,148nymous_,UP,PDIF ++S 33200,13100,33200,15900,400,149nymous_,UP,ALU1 ++S 24900,21600,28100,21600,420,45onymous_,RIGHT,PDIF ++S 24900,20400,28100,20400,620,44onymous_,RIGHT,PDIF ++S 17700,25600,18900,25600,620,311nymous_,RIGHT,NDIF ++S 17700,24400,18900,24400,620,310nymous_,RIGHT,NDIF ++S 17700,23200,18900,23200,620,309nymous_,RIGHT,NDIF ++S 12200,11100,12200,13100,200,p17a,UP,PTRANS ++S 18200,8300,18200,9300,200,n16a,UP,NTRANS ++S 12200,10000,16400,10000,600,nnt,RIGHT,POLY ++S 17700,22000,18900,22000,620,308nymous_,RIGHT,NDIF ++S 32600,7300,32600,8300,200,n0,UP,NTRANS ++S 27200,8100,27200,12900,400,cpbb,UP,ALU1 ++S 25400,10600,27200,10600,200,cpbb,RIGHT,POLY ++S 25400,12700,25400,14700,200,p4b,UP,PTRANS ++S 9200,12100,9200,15900,400,228nymous_,UP,ALU1 ++S 9300,25000,16100,25000,2400,229nymous_,RIGHT,ALU2 ++S 30000,19900,30000,24900,400,108nymous_,UP,ALU2 ++S 9300,31000,16100,31000,2400,230nymous_,RIGHT,ALU2 ++S 4400,7500,4400,9100,620,191nymous_,UP,NDIF ++S 23100,19200,38100,19200,400,32onymous_,RIGHT,ALU1 ++S 4400,11100,4400,14700,620,192nymous_,UP,PDIF ++S 26000,12900,26000,14500,620,69onymous_,UP,PDIF ++S 22880,19200,38320,19200,600,33onymous_,RIGHT,NTIE ++S 4400,11900,4400,15900,400,193nymous_,UP,ALU1 ++S 13400,9600,13400,10800,200,266nymous_,UP,POLY ++S 23080,37600,29920,37600,600,34onymous_,RIGHT,NTIE ++S 26000,13100,26000,15900,400,70onymous_,UP,ALU1 ++S 4100,13000,20300,13000,2400,194nymous_,RIGHT,ALU2 ++S 30100,20200,35900,20200,400,109nymous_,RIGHT,ALU1 ++S 33400,11700,33400,17300,400,150nymous_,UP,ALU2 ++S 33800,21100,33800,36500,620,151nymous_,UP,PDIF ++S 30200,8600,30200,9000,200,110nymous_,UP,POLY ++S 24900,25200,28100,25200,420,48onymous_,RIGHT,PDIF ++S 24900,24000,28100,24000,420,47onymous_,RIGHT,PDIF ++S 24900,22800,28100,22800,420,46onymous_,RIGHT,PDIF ++S 17700,28000,18900,28000,620,313nymous_,RIGHT,NDIF ++S 17700,26800,18900,26800,620,312nymous_,RIGHT,NDIF ++S 30600,21300,30600,35500,400,114nymous_,UP,ALU1 ++S 30600,21100,30600,35900,620,113nymous_,UP,PDIF ++S 5700,9000,10300,9000,400,197nymous_,RIGHT,ALU1 ++S 32600,12700,32600,14700,200,p0,UP,PTRANS ++S 33000,20900,33000,36700,200,p14b,UP,PTRANS ++S 9800,21500,9800,23100,400,231nymous_,UP,ALU2 ++S 9500,22800,17100,22800,400,232nymous_,RIGHT,ALU2 ++S 9500,37000,17100,37000,2400,233nymous_,RIGHT,ALU2 ++S 26000,13700,26000,16100,400,71onymous_,UP,ALU2 ++S 23600,6100,23600,7900,400,35onymous_,UP,ALU1 ++S 14000,21800,14000,22200,600,267nymous_,UP,POLY ++S 25700,15400,32500,15400,1200,72onymous_,RIGHT,ALU2 ++S 23600,7500,23600,8100,620,36onymous_,UP,NDIF ++S 9800,9600,9800,10600,200,234nymous_,UP,POLY ++S 5000,9600,5000,10600,200,195nymous_,UP,POLY ++S 33800,21300,33800,36300,400,152nymous_,UP,ALU1 ++S 14000,22700,14000,36500,620,268nymous_,UP,NDIF ++S 25700,17000,33500,17000,400,73onymous_,RIGHT,ALU2 ++S 23600,12900,23600,14500,620,37onymous_,UP,PDIF ++S 14000,22900,14000,39700,400,269nymous_,UP,ALU1 ++S 14000,6100,14000,7900,400,270nymous_,UP,ALU1 ++S 30200,12000,30200,12200,200,111nymous_,UP,POLY ++S 5600,7500,5600,9100,420,196nymous_,UP,NDIF ++S 30400,36400,30400,36600,200,112nymous_,UP,POLY ++S 700,25000,8900,25000,2400,237nymous_,RIGHT,ALU2 ++S 33800,12400,35000,12400,200,155nymous_,RIGHT,POLY ++S 27000,6900,27000,14300,400,77onymous_,UP,ALU2 ++S 14100,10000,21100,10000,400,272nymous_,RIGHT,ALU1 ++S 9700,19000,14900,19000,2400,236nymous_,RIGHT,ALU2 ++S 27000,24900,27000,36700,400,76onymous_,UP,ALU2 ++S 33800,8600,35000,8600,200,154nymous_,RIGHT,POLY ++S 24900,26400,28100,26400,420,49onymous_,RIGHT,PDIF ++S 17700,30400,18900,30400,620,315nymous_,RIGHT,NDIF ++S 17700,29200,18900,29200,620,314nymous_,RIGHT,NDIF ++S 6000,20700,6000,36300,400,200nymous_,UP,ALU1 ++S 30600,26700,30600,35300,2400,115nymous_,UP,ALU2 ++S 5700,11000,10300,11000,400,199nymous_,RIGHT,ALU1 ++S 700,28000,15100,28000,2400,238nymous_,RIGHT,ALU2 ++S 5600,11100,5600,14700,620,198nymous_,UP,PDIF ++S 16800,29800,17200,29800,200,cnb,RIGHT,POLY ++S 16800,28600,17200,28600,200,cnb,RIGHT,POLY ++S 16800,25000,17200,25000,200,cnb,RIGHT,POLY ++S 16800,23800,17200,23800,200,cnb,RIGHT,POLY ++S 34400,12700,34400,18500,400,cnb,UP,ALU2 ++S 29000,17900,29000,23700,400,cnb,UP,ALU2 ++S 28600,23400,29000,23400,600,cnb,RIGHT,POLY ++S 28600,22200,29000,22200,600,cnb,RIGHT,POLY ++S 28600,21000,29000,21000,600,cnb,RIGHT,POLY ++S 23700,19200,29300,19200,400,cnb,RIGHT,ALU2 ++S 33800,19100,33800,38300,2400,156nymous_,UP,ALU2 ++S 24000,18900,24000,20500,400,41onymous_,UP,ALU2 ++S 14000,11300,14000,12900,620,273nymous_,UP,PDIF ++S 17000,12300,17000,13100,200,p16,UP,PTRANS ++S 19400,8300,19400,9300,200,n16b,UP,NTRANS ++S 24200,7300,24200,8300,200,n4a,UP,NTRANS ++S 2700,20200,15700,20200,400,74onymous_,RIGHT,ALU1 ++S 23600,13100,23600,15900,400,38onymous_,UP,ALU1 ++S 33800,8600,33800,12400,200,153nymous_,UP,POLY ++S 26400,18600,26400,38600,8400,75onymous_,UP,NWELL ++S 24000,27100,24000,29100,400,39onymous_,UP,ALU1 ++S 10000,22200,11600,22200,200,235nymous_,RIGHT,POLY ++S 14000,7500,14000,9100,620,271nymous_,UP,NDIF ++S 24000,33900,24000,36100,400,40onymous_,UP,ALU2 ++S 24700,22200,28300,22200,200,p7b,RIGHT,PTRANS ++S 33800,7300,33800,8300,200,n5a,UP,NTRANS ++S 17000,12000,17400,12000,200,nt,RIGHT,POLY ++S 5000,10000,11000,10000,600,nt,RIGHT,POLY ++S 24700,21000,28300,21000,200,p7c,RIGHT,PTRANS ++S 24200,12400,25400,12400,200,43onymous_,RIGHT,POLY ++S 30200,7300,30200,8300,200,n3,UP,NTRANS ++S 5000,7300,5000,9300,200,n18a,UP,NTRANS ++S 24200,12700,24200,14700,200,p4a,UP,PTRANS ++S 13400,11100,13400,13100,200,p17b,UP,PTRANS ++S 24200,8600,25400,8600,200,42onymous_,RIGHT,POLY ++S 17500,25000,19100,25000,200,n7c,RIGHT,NTRANS ++S 13400,7300,13400,9300,200,n17b,UP,NTRANS ++S 17500,23800,19100,23800,200,n7d,RIGHT,NTRANS ++S 13200,22500,13200,36700,200,n15c,UP,NTRANS ++S 26700,13000,33700,13000,2400,78onymous_,RIGHT,ALU2 ++S 14000,12100,14000,15900,400,274nymous_,UP,ALU1 ++S 27200,7500,27200,8100,620,79onymous_,UP,NDIF ++S 34000,18200,34000,38200,10400,157nymous_,UP,NWELL ++S 27200,12700,27200,14300,620,80onymous_,UP,PDIF ++S 3280,6000,28520,6000,600,158nymous_,RIGHT,PTIE ++S 27200,13100,27200,13900,400,81onymous_,UP,ALU1 ++S 700,31000,8900,31000,2400,239nymous_,RIGHT,ALU2 ++S 34400,7500,34400,8100,620,159nymous_,UP,NDIF ++S 30600,36400,31400,36400,200,116nymous_,RIGHT,POLY ++S 6000,22700,6000,36500,620,201nymous_,UP,NDIF ++S 700,34000,16100,34000,2400,240nymous_,RIGHT,ALU2 ++S 30680,6000,37120,6000,600,117nymous_,RIGHT,PTIE ++S 6200,9600,6200,10600,200,202nymous_,UP,POLY ++S 10400,7500,10400,9100,420,241nymous_,UP,NDIF ++S 24900,27600,28100,27600,420,50onymous_,RIGHT,PDIF ++S 5600,8100,5600,13700,400,1.nq,UP,ALU1 ++S 33800,12700,33800,14700,200,p5a,UP,PTRANS ++S 24700,25800,28300,25800,200,p13,RIGHT,PTRANS ++S 30200,12500,30200,14500,200,p3,UP,PTRANS ++S 24700,24600,28300,24600,200,p10,RIGHT,PTRANS ++S 5200,22500,5200,36700,200,n14b,UP,NTRANS ++S 24700,23400,28300,23400,200,p7a,RIGHT,PTRANS ++S 5000,10900,5000,14900,200,p18a,UP,PTRANS ++S 30200,12000,31800,12000,200,eb,RIGHT,POLY ++S 30200,9000,31800,9000,200,eb,RIGHT,POLY ++S 10000,22500,10000,36700,200,n15a,UP,NTRANS ++S 9800,10900,9800,14900,200,p18e,UP,PTRANS ++S 17500,29800,19100,29800,200,n7a,RIGHT,NTRANS ++S 17500,28600,19100,28600,200,n7b,RIGHT,NTRANS ++S 9800,7300,9800,9300,200,n18e,UP,NTRANS ++S 17500,27400,19100,27400,200,n6b,RIGHT,NTRANS ++S 17500,26200,19100,26200,200,n6c,RIGHT,NTRANS ++S 24700,27000,28300,27000,200,p6c,RIGHT,PTRANS ++S 1280,37600,21120,37600,600,275nymous_,RIGHT,PTIE ++S 14600,9600,14600,10800,200,276nymous_,UP,POLY ++S 27300,13000,29500,13000,400,82onymous_,RIGHT,ALU1 ++S 50,6000,26800,6000,12000,0nonymous_,RIGHT,TALU2 ++S 34400,8100,34400,13900,400,160nymous_,UP,ALU1 ++S 34400,13100,34400,14500,620,161nymous_,UP,PDIF ++S 30800,7500,30800,8100,620,118nymous_,UP,NDIF ++S 27800,8600,27800,9800,200,83onymous_,UP,POLY ++S 15300,37600,20700,37600,400,277nymous_,RIGHT,ALU1 ++S 31200,6000,39950,6000,12000,2nonymous_,RIGHT,TALU2 ++S 27800,9800,32600,9800,200,84onymous_,RIGHT,POLY ++S 34800,20200,34800,20600,600,162nymous_,UP,POLY ++S 6800,6100,6800,7900,400,203nymous_,UP,ALU1 ++S 10100,7600,27300,7600,1200,242nymous_,RIGHT,ALU2 ++S 17500,34600,19100,34600,200,n8b,RIGHT,NTRANS ++S 50,17000,39950,17000,10000,blockagenet,RIGHT,TALU2 ++S 17500,33400,19100,33400,200,n8c,RIGHT,NTRANS ++S 17500,32200,19100,32200,200,n8d,RIGHT,NTRANS ++S 17500,31000,19100,31000,200,n6a,RIGHT,NTRANS ++S 2800,22700,2800,36500,620,88onymous_,UP,NDIF ++S 24700,28200,28300,28200,200,p6b,RIGHT,PTRANS ++S 24700,29400,28300,29400,200,p6a,RIGHT,PTRANS ++S 24700,30600,28300,30600,200,p8c,RIGHT,PTRANS ++S 15200,7500,15200,9100,620,278nymous_,UP,NDIF ++S 50,6000,26800,6000,12000,3nonymous_,RIGHT,TALU4 ++S 27800,11800,27800,12400,200,85onymous_,UP,POLY ++S 30800,12700,30800,14300,620,119nymous_,UP,PDIF ++S 15200,8100,15200,8900,400,279nymous_,UP,ALU1 ++S 15200,11100,15200,12500,400,280nymous_,UP,ALU1 ++S 31200,6000,39950,6000,12000,5nonymous_,RIGHT,TALU4 ++S 30800,13100,30800,13900,400,120nymous_,UP,ALU1 ++S 15200,11300,15200,12900,620,281nymous_,UP,PDIF ++S 6800,7500,6800,9100,620,204nymous_,UP,NDIF ++S 31000,5700,31000,11300,400,121nymous_,UP,ALU2 ++S 35400,21100,35400,36500,620,163nymous_,UP,PDIF ++S 6900,10000,12700,10000,400,205nymous_,RIGHT,ALU1 ++S 35400,21300,35400,39700,400,164nymous_,UP,ALU1 ++S 10400,8100,10400,8900,400,243nymous_,UP,ALU1 ++S 6800,11100,6800,14700,620,206nymous_,UP,PDIF ++S 35100,13000,37100,13000,2400,165nymous_,RIGHT,ALU2 ++S 10400,11100,10400,13700,400,244nymous_,UP,ALU1 ++S 6800,12100,6800,15900,400,207nymous_,UP,ALU1 ++S 10400,11100,10400,14700,620,245nymous_,UP,PDIF ++S 2800,20500,2800,36300,400,87onymous_,UP,ALU1 ++S 17500,35800,19100,35800,200,n8a,RIGHT,NTRANS ++S 7400,9600,7400,10600,200,209nymous_,UP,POLY ++S 35600,12900,35600,14500,620,168nymous_,UP,PDIF ++S 31400,19100,31400,28300,400,124nymous_,UP,ALU2 ++S 10700,39600,35500,39600,2400,246nymous_,RIGHT,ALU1 ++S 10800,21800,10800,22200,600,247nymous_,UP,POLY ++S 2200,13600,37800,13600,6800,89onymous_,RIGHT,NWELL ++S 31600,20200,31600,20600,600,125nymous_,UP,POLY ++S 28200,9100,28200,11700,400,90onymous_,UP,ALU1 ++S 14600,7300,14600,9300,200,n17c,UP,NTRANS ++S 24700,31800,28300,31800,200,p8b,RIGHT,PTRANS ++S 24700,33000,28300,33000,200,p8a,RIGHT,PTRANS ++S 27800,7300,27800,8300,200,n2,UP,NTRANS ++S 24700,34200,28300,34200,200,p9,RIGHT,PTRANS ++S 6200,7300,6200,9300,200,n18b,UP,NTRANS ++S 24700,35800,28300,35800,200,p12,RIGHT,PTRANS ++S 34600,20900,34600,36700,200,p14c,UP,PTRANS ++S 17700,31600,18900,31600,620,316nymous_,RIGHT,NDIF ++S 13400,200,13400,2000,27000,6nonymous_,UP,TALU3 ++S 17700,32800,18900,32800,620,317nymous_,RIGHT,NDIF ++S 15600,20700,15600,36300,400,282nymous_,UP,ALU1 ++S 29000,200,29000,2000,0,7nonymous_,UP,TALU3 ++S 30700,6000,32300,6000,400,122nymous_,RIGHT,ALU2 ++S 15600,22700,15600,36500,620,283nymous_,UP,NDIF ++S 35600,200,35600,2000,9000,8nonymous_,UP,TALU3 ++S 30700,10000,36100,10000,2400,123nymous_,RIGHT,ALU2 ++S 15800,23700,15800,32300,400,284nymous_,UP,ALU2 ++S 13400,200,13400,12000,27000,9nonymous_,UP,TALU5 ++S 35600,6100,35600,7900,400,166nymous_,UP,ALU1 ++S 7000,6900,7000,14300,400,208nymous_,UP,ALU2 ++S 35600,7500,35600,8100,620,167nymous_,UP,NDIF ++B 21200,10000,200,200,CONT_TURN1,344nymous_ ++B 22400,8000,200,200,CONT_TURN1,345nymous_ ++B 28200,9000,200,200,CONT_TURN1,346nymous_ ++B 17400,11000,200,200,CONT_TURN1,349nymous_ ++B 5000,19000,8300,2300,CONT_VIA2,347nymous_ ++B 10400,11000,200,200,CONT_TURN1,348nymous_ ++B 17800,22000,200,200,CONT_TURN1,351nymous_ ++B 17600,8000,200,200,CONT_TURN1,350nymous_ ++B 18400,12800,200,200,CONT_TURN1,352nymous_ ++B 19800,32800,200,200,CONT_TURN1,353nymous_ ++B 16400,17000,300,300,CONT_VIA,1268ymous_ ++B 15200,9000,300,300,CONT_DIF_N,1214ymous_ ++B 6800,37600,300,300,CONT_VIA,1000ymous_ ++B 18800,23200,300,300,CONT_DIF_N,1322ymous_ ++B 7600,36000,300,300,CONT_VIA2,1054ymous_ ++B 9200,17000,300,300,CONT_VIA,1108ymous_ ++B 26000,20400,300,300,CONT_DIF_P,462nymous_ ++B 23000,35400,300,300,CONT_BODY_N,408nymous_ ++B 28400,14000,300,300,CONT_DIF_P,569nymous_ ++B 30600,31000,300,300,CONT_VIA,623nymous_ ++B 12400,30000,300,300,CONT_DIF_N,1162ymous_ ++B 27000,36400,300,300,CONT_DIF_P,516nymous_ ++B 3200,14000,300,300,CONT_VIA2,677nymous_ ++B 35400,26000,300,300,CONT_DIF_P,785nymous_ ++B 37000,22000,300,300,CONT_VIA2,839nymous_ ++B 38200,30400,300,300,CONT_BODY_N,893nymous_ ++B 15200,10000,300,300,CONT_POLY,1215ymous_ ++B 4400,14800,300,300,CONT_DIF_P,947nymous_ ++B 6800,37600,300,300,CONT_VIA2,1001ymous_ ++B 18800,24400,300,300,CONT_DIF_N,1323ymous_ ++B 16400,17000,300,300,CONT_VIA2,1269ymous_ ++B 23000,36400,300,300,CONT_BODY_N,409nymous_ ++B 28400,16000,300,300,CONT_BODY_N,570nymous_ ++B 7600,19200,300,300,CONT_BODY_P,1055ymous_ ++B 9200,17000,300,300,CONT_VIA2,1109ymous_ ++B 27000,36400,300,300,CONT_VIA,517nymous_ ++B 26000,21600,300,300,CONT_DIF_P,463nymous_ ++B 30600,32000,300,300,CONT_DIF_P,624nymous_ ++B 3200,15000,300,300,CONT_BODY_N,678nymous_ ++B 12400,31000,300,300,CONT_DIF_N,1163ymous_ ++B 33800,28000,300,300,CONT_VIA,732nymous_ ++B 35400,27000,300,300,CONT_DIF_P,786nymous_ ++B 37000,23000,300,300,CONT_DIF_P,840nymous_ ++B 28000,25200,300,300,CONT_DIF_P,540nymous_ ++B 38200,31400,300,300,CONT_BODY_N,894nymous_ ++B 4400,16000,300,300,CONT_BODY_N,948nymous_ ++B 16600,19200,300,300,CONT_BODY_P,1270ymous_ ++B 15200,11600,300,300,CONT_DIF_P,1216ymous_ ++B 6800,6000,300,300,CONT_BODY_P,1002ymous_ ++B 7800,37600,300,300,CONT_BODY_P,1056ymous_ ++B 18800,25600,300,300,CONT_DIF_N,1324ymous_ ++B 23000,37600,300,300,CONT_BODY_N,410nymous_ ++B 20000,6000,300,300,CONT_VIA2,356nymous_ ++B 28400,17000,300,300,CONT_VIA,571nymous_ ++B 9600,37600,300,300,CONT_BODY_P,1110ymous_ ++B 12400,32000,300,300,CONT_DIF_N,1164ymous_ ++B 27000,37600,300,300,CONT_BODY_N,518nymous_ ++B 26000,21600,300,300,CONT_VIA,464nymous_ ++B 30600,32000,300,300,CONT_VIA,625nymous_ ++B 3200,16000,300,300,CONT_BODY_N,679nymous_ ++B 33800,28000,300,300,CONT_VIA2,733nymous_ ++B 35400,28000,300,300,CONT_DIF_P,787nymous_ ++B 37000,23000,300,300,CONT_VIA,841nymous_ ++B 38200,32400,300,300,CONT_BODY_N,895nymous_ ++B 4400,17000,300,300,CONT_VIA,949nymous_ ++B 16800,20200,300,300,CONT_VIA,1271ymous_ ++B 15200,12600,300,300,CONT_DIF_P,1217ymous_ ++B 20000,8600,300,300,CONT_DIF_N,357nymous_ ++B 6800,6000,300,300,CONT_VIA,1003ymous_ ++B 7800,37600,300,300,CONT_VIA,1057ymous_ ++B 18800,26800,300,300,CONT_DIF_N,1325ymous_ ++B 23000,19200,300,300,CONT_BODY_N,411nymous_ ++B 28400,17000,300,300,CONT_VIA2,572nymous_ ++B 9600,19200,300,300,CONT_BODY_P,1111ymous_ ++B 12400,33000,300,300,CONT_DIF_N,1165ymous_ ++B 37000,23000,300,300,CONT_VIA2,842nymous_ ++B 38200,33400,300,300,CONT_BODY_N,896nymous_ ++B 15200,16000,300,300,CONT_BODY_N,1218ymous_ ++B 4400,17000,300,300,CONT_VIA2,950nymous_ ++B 6800,6000,300,300,CONT_VIA2,1004ymous_ ++B 18800,26800,300,300,CONT_VIA,1326ymous_ ++B 16800,23400,300,300,CONT_POLY,1272ymous_ ++B 20000,11000,300,300,CONT_POLY,358nymous_ ++B 7800,37600,300,300,CONT_VIA2,1058ymous_ ++B 10400,6000,300,300,CONT_BODY_P,1112ymous_ ++B 26000,22800,300,300,CONT_DIF_P,466nymous_ ++B 23400,17000,300,300,CONT_VIA,412nymous_ ++B 28800,9000,300,300,CONT_POLY,573nymous_ ++B 30600,33000,300,300,CONT_VIA,627nymous_ ++B 12400,34000,300,300,CONT_DIF_N,1166ymous_ ++B 27000,10000,300,300,CONT_VIA2,520nymous_ ++B 3200,17000,300,300,CONT_VIA2,681nymous_ ++B 33800,29000,300,300,CONT_VIA,735nymous_ ++B 35400,30000,300,300,CONT_DIF_P,789nymous_ ++B 37000,24000,300,300,CONT_DIF_P,843nymous_ ++B 38200,34400,300,300,CONT_BODY_N,897nymous_ ++B 15200,17000,300,300,CONT_VIA,1219ymous_ ++B 4600,37600,300,300,CONT_BODY_P,951nymous_ ++B 6800,7200,300,300,CONT_DIF_N,1005ymous_ ++B 16800,24400,300,300,CONT_VIA,1273ymous_ ++B 20000,16000,300,300,CONT_BODY_N,359nymous_ ++B 26000,21600,300,300,CONT_VIA2,465nymous_ ++B 30600,33000,300,300,CONT_DIF_P,626nymous_ ++B 27000,9000,300,300,CONT_VIA2,519nymous_ ++B 3200,17000,300,300,CONT_VIA,680nymous_ ++B 33800,29000,300,300,CONT_DIF_P,734nymous_ ++B 35400,29000,300,300,CONT_DIF_P,788nymous_ ++B 18800,28000,300,300,CONT_DIF_N,1327ymous_ ++B 23400,17000,300,300,CONT_VIA2,413nymous_ ++B 29000,21000,300,300,CONT_POLY,574nymous_ ++B 8000,8000,300,300,CONT_DIF_N,1059ymous_ ++B 10400,6000,300,300,CONT_VIA,1113ymous_ ++B 27000,11000,300,300,CONT_VIA2,521nymous_ ++B 26000,22800,300,300,CONT_VIA2,467nymous_ ++B 30600,33000,300,300,CONT_VIA2,628nymous_ ++B 32200,22000,300,300,CONT_DIF_P,682nymous_ ++B 33800,29000,300,300,CONT_VIA2,736nymous_ ++B 12400,35000,300,300,CONT_DIF_N,1167ymous_ ++B 35400,31000,300,300,CONT_DIF_P,790nymous_ ++B 37000,24000,300,300,CONT_VIA,844nymous_ ++B 38200,35400,300,300,CONT_BODY_N,898nymous_ ++B 4600,37600,300,300,CONT_VIA,952nymous_ ++B 16800,25400,300,300,CONT_POLY,1274ymous_ ++B 15200,17000,300,300,CONT_VIA2,1220ymous_ ++B 6800,8000,300,300,CONT_DIF_N,1006ymous_ ++B 8000,9000,300,300,CONT_DIF_N,1060ymous_ ++B 18800,29200,300,300,CONT_DIF_N,1328ymous_ ++B 23600,6000,300,300,CONT_BODY_P,414nymous_ ++B 20800,20400,300,300,CONT_BODY_P,360nymous_ ++B 29000,21000,300,300,CONT_VIA,575nymous_ ++B 10400,6000,300,300,CONT_VIA2,1114ymous_ ++B 12400,36000,300,300,CONT_DIF_N,1168ymous_ ++B 27000,19200,300,300,CONT_BODY_N,522nymous_ ++B 26000,24000,300,300,CONT_DIF_P,468nymous_ ++B 30600,34000,300,300,CONT_DIF_P,629nymous_ ++B 32200,23000,300,300,CONT_DIF_P,683nymous_ ++B 33800,30000,300,300,CONT_DIF_P,737nymous_ ++B 35400,32000,300,300,CONT_DIF_P,791nymous_ ++B 37000,25000,300,300,CONT_DIF_P,845nymous_ ++B 38200,36400,300,300,CONT_BODY_N,899nymous_ ++B 4600,37600,300,300,CONT_VIA2,953nymous_ ++B 16800,28200,300,300,CONT_POLY,1275ymous_ ++B 15600,23000,300,300,CONT_DIF_N,1221ymous_ ++B 20800,21400,300,300,CONT_BODY_P,361nymous_ ++B 6800,10000,300,300,CONT_POLY,1007ymous_ ++B 8000,9000,300,300,CONT_VIA,1061ymous_ ++B 18800,30400,300,300,CONT_DIF_N,1329ymous_ ++B 26000,24000,300,300,CONT_VIA,469nymous_ ++B 23600,6000,300,300,CONT_VIA,415nymous_ ++B 29000,22200,300,300,CONT_POLY,576nymous_ ++B 30600,34000,300,300,CONT_VIA,630nymous_ ++B 10400,8000,300,300,CONT_DIF_N,1115ymous_ ++B 12600,19200,300,300,CONT_BODY_P,1169ymous_ ++B 27200,6000,300,300,CONT_BODY_P,523nymous_ ++B 32200,24000,300,300,CONT_DIF_P,684nymous_ ++B 33800,30000,300,300,CONT_VIA,738nymous_ ++B 35400,33000,300,300,CONT_DIF_P,792nymous_ ++B 37000,25000,300,300,CONT_VIA,846nymous_ ++B 38200,37600,300,300,CONT_BODY_N,900nymous_ ++B 15600,24000,300,300,CONT_DIF_N,1222ymous_ ++B 4600,19200,300,300,CONT_BODY_P,954nymous_ ++B 6800,12000,300,300,CONT_DIF_P,1008ymous_ ++B 18800,31600,300,300,CONT_DIF_N,1330ymous_ ++B 16800,29200,300,300,CONT_VIA,1276ymous_ ++B 20800,22400,300,300,CONT_BODY_P,362nymous_ ++B 8000,10000,300,300,CONT_POLY,1062ymous_ ++B 10400,9000,300,300,CONT_DIF_N,1116ymous_ ++B 23600,6000,300,300,CONT_VIA2,416nymous_ ++B 29000,22200,300,300,CONT_VIA,577nymous_ ++B 12800,6000,300,300,CONT_BODY_P,1170ymous_ ++B 27200,8000,300,300,CONT_DIF_N,524nymous_ ++B 15600,25000,300,300,CONT_DIF_N,1223ymous_ ++B 5400,24000,300,300,CONT_VIA2,955nymous_ ++B 6800,12800,300,300,CONT_DIF_P,1009ymous_ ++B 18800,31600,300,300,CONT_VIA,1331ymous_ ++B 16800,32200,300,300,CONT_POLY,1277ymous_ ++B 23600,8000,300,300,CONT_DIF_N,417nymous_ ++B 20800,23400,300,300,CONT_BODY_P,363nymous_ ++B 29000,23400,300,300,CONT_POLY,578nymous_ ++B 8000,11000,300,300,CONT_VIA,1063ymous_ ++B 10400,10000,300,300,CONT_POLY,1117ymous_ ++B 27200,10600,300,300,CONT_POLY,525nymous_ ++B 26000,26400,300,300,CONT_DIF_P,471nymous_ ++B 30600,35000,300,300,CONT_DIF_P,632nymous_ ++B 32200,26000,300,300,CONT_DIF_P,686nymous_ ++B 33800,31000,300,300,CONT_VIA,740nymous_ ++B 12800,6000,300,300,CONT_VIA,1171ymous_ ++B 35400,35000,300,300,CONT_DIF_P,794nymous_ ++B 37000,26000,300,300,CONT_VIA,848nymous_ ++B 4400,21800,300,300,CONT_POLY,902nymous_ ++B 5400,25000,300,300,CONT_VIA2,956nymous_ ++B 16800,32200,300,300,CONT_VIA,1278ymous_ ++B 15600,26000,300,300,CONT_DIF_N,1224ymous_ ++B 6800,13800,300,300,CONT_DIF_P,1010ymous_ ++B 18800,32800,300,300,CONT_DIF_N,1332ymous_ ++B 20800,24400,300,300,CONT_BODY_P,364nymous_ ++B 38200,19200,300,300,CONT_BODY_N,901nymous_ ++B 37000,26000,300,300,CONT_DIF_P,847nymous_ ++B 35400,34000,300,300,CONT_DIF_P,793nymous_ ++B 33800,31000,300,300,CONT_DIF_P,739nymous_ ++B 32200,25000,300,300,CONT_DIF_P,685nymous_ ++B 30600,34000,300,300,CONT_VIA2,631nymous_ ++B 26000,25200,300,300,CONT_DIF_P,470nymous_ ++B 4400,23000,300,300,CONT_DIF_N,904nymous_ ++B 37000,27000,300,300,CONT_VIA,850nymous_ ++B 35600,6000,300,300,CONT_BODY_P,796nymous_ ++B 33800,32000,300,300,CONT_VIA,742nymous_ ++B 32200,28000,300,300,CONT_DIF_P,688nymous_ ++B 27200,14000,300,300,CONT_DIF_P,527nymous_ ++B 12800,8000,300,300,CONT_DIF_N,1173ymous_ ++B 10400,12800,300,300,CONT_DIF_P,1119ymous_ ++B 30600,35000,300,300,CONT_VIA2,634nymous_ ++B 29000,24600,300,300,CONT_POLY,580nymous_ ++B 23600,14000,300,300,CONT_DIF_P,419nymous_ ++B 26000,27600,300,300,CONT_DIF_P,473nymous_ ++B 18800,34000,300,300,CONT_DIF_N,1333ymous_ ++B 8000,12800,300,300,CONT_DIF_P,1065ymous_ ++B 6800,14800,300,300,CONT_DIF_P,1011ymous_ ++B 20800,25400,300,300,CONT_BODY_P,365nymous_ ++B 15600,27000,300,300,CONT_DIF_N,1225ymous_ ++B 16800,33400,300,300,CONT_POLY,1279ymous_ ++B 5400,26000,300,300,CONT_VIA2,957nymous_ ++B 4400,21800,300,300,CONT_VIA,903nymous_ ++B 37000,27000,300,300,CONT_DIF_P,849nymous_ ++B 35400,36000,300,300,CONT_DIF_P,795nymous_ ++B 33800,32000,300,300,CONT_DIF_P,741nymous_ ++B 32200,27000,300,300,CONT_DIF_P,687nymous_ ++B 30600,35000,300,300,CONT_VIA,633nymous_ ++B 26000,26400,300,300,CONT_VIA,472nymous_ ++B 27200,13000,300,300,CONT_DIF_P,526nymous_ ++B 12800,6000,300,300,CONT_VIA2,1172ymous_ ++B 10400,11800,300,300,CONT_DIF_P,1118ymous_ ++B 29000,23400,300,300,CONT_VIA,579nymous_ ++B 23600,13000,300,300,CONT_DIF_P,418nymous_ ++B 8000,11800,300,300,CONT_DIF_P,1064ymous_ ++B 30800,8000,300,300,CONT_DIF_N,636nymous_ ++B 26000,28800,300,300,CONT_DIF_P,475nymous_ ++B 27200,17000,300,300,CONT_VIA,529nymous_ ++B 10400,16000,300,300,CONT_BODY_N,1121ymous_ ++B 8000,16000,300,300,CONT_BODY_N,1067ymous_ ++B 29000,25800,300,300,CONT_POLY,582nymous_ ++B 20800,27400,300,300,CONT_BODY_P,367nymous_ ++B 24000,27000,300,300,CONT_POLY,421nymous_ ++B 16800,33400,300,300,CONT_VIA2,1281ymous_ ++B 18800,35200,300,300,CONT_DIF_N,1335ymous_ ++B 6800,17000,300,300,CONT_VIA,1013ymous_ ++B 5400,31000,300,300,CONT_VIA2,959nymous_ ++B 15600,29000,300,300,CONT_DIF_N,1227ymous_ ++B 4400,23000,300,300,CONT_VIA,905nymous_ ++B 37000,27000,300,300,CONT_VIA2,851nymous_ ++B 35600,6000,300,300,CONT_VIA,797nymous_ ++B 33800,33000,300,300,CONT_DIF_P,743nymous_ ++B 32200,29000,300,300,CONT_DIF_P,689nymous_ ++B 27200,16000,300,300,CONT_BODY_N,528nymous_ ++B 12800,9000,300,300,CONT_DIF_N,1174ymous_ ++B 30800,6000,300,300,CONT_BODY_P,635nymous_ ++B 29000,24600,300,300,CONT_VIA,581nymous_ ++B 23600,16000,300,300,CONT_BODY_N,420nymous_ ++B 26000,27600,300,300,CONT_VIA2,474nymous_ ++B 10400,13800,300,300,CONT_DIF_P,1120ymous_ ++B 8000,13800,300,300,CONT_DIF_P,1066ymous_ ++B 20800,26400,300,300,CONT_BODY_P,366nymous_ ++B 16800,33400,300,300,CONT_VIA,1280ymous_ ++B 18800,34000,300,300,CONT_VIA,1334ymous_ ++B 6800,16000,300,300,CONT_BODY_N,1012ymous_ ++B 5400,30000,300,300,CONT_VIA2,958nymous_ ++B 15600,28000,300,300,CONT_DIF_N,1226ymous_ ++B 15600,30000,300,300,CONT_DIF_N,1228ymous_ ++B 16800,34600,300,300,CONT_POLY,1282ymous_ ++B 5400,32000,300,300,CONT_VIA2,960nymous_ ++B 4400,24000,300,300,CONT_DIF_N,906nymous_ ++B 37000,28000,300,300,CONT_DIF_P,852nymous_ ++B 35600,6000,300,300,CONT_VIA2,798nymous_ ++B 33800,33000,300,300,CONT_VIA,744nymous_ ++B 32200,30000,300,300,CONT_DIF_P,690nymous_ ++B 6800,17000,300,300,CONT_VIA2,1014ymous_ ++B 8000,17000,300,300,CONT_VIA,1068ymous_ ++B 18800,36400,300,300,CONT_DIF_N,1336ymous_ ++B 24000,28200,300,300,CONT_POLY,422nymous_ ++B 20800,28400,300,300,CONT_BODY_P,368nymous_ ++B 29000,30600,300,300,CONT_POLY,583nymous_ ++B 10400,17000,300,300,CONT_VIA,1122ymous_ ++B 12800,12600,300,300,CONT_DIF_P,1176ymous_ ++B 27200,17000,300,300,CONT_VIA2,530nymous_ ++B 26000,28800,300,300,CONT_VIA,476nymous_ ++B 30800,10600,300,300,CONT_POLY,637nymous_ ++B 32200,31000,300,300,CONT_DIF_P,691nymous_ ++B 33800,33000,300,300,CONT_VIA2,745nymous_ ++B 35600,8000,300,300,CONT_DIF_N,799nymous_ ++B 37000,28000,300,300,CONT_VIA,853nymous_ ++B 4400,24000,300,300,CONT_VIA,907nymous_ ++B 5400,36000,300,300,CONT_VIA2,961nymous_ ++B 16800,34600,300,300,CONT_VIA,1283ymous_ ++B 15600,31000,300,300,CONT_DIF_N,1229ymous_ ++B 20800,29400,300,300,CONT_BODY_P,369nymous_ ++B 7000,9000,300,300,CONT_VIA2,1015ymous_ ++B 8000,17000,300,300,CONT_VIA2,1069ymous_ ++B 18800,36400,300,300,CONT_VIA,1337ymous_ ++B 24000,28200,300,300,CONT_VIA,423nymous_ ++B 26000,28800,300,300,CONT_VIA2,477nymous_ ++B 29000,31800,300,300,CONT_POLY,584nymous_ ++B 30800,13000,300,300,CONT_DIF_P,638nymous_ ++B 10400,17000,300,300,CONT_VIA2,1123ymous_ ++B 12800,16000,300,300,CONT_BODY_N,1177ymous_ ++B 27800,36400,300,300,CONT_DIF_P,531nymous_ ++B 32200,32000,300,300,CONT_DIF_P,692nymous_ ++B 33800,34000,300,300,CONT_DIF_P,746nymous_ ++B 35600,13000,300,300,CONT_DIF_P,800nymous_ ++B 37000,28000,300,300,CONT_VIA2,854nymous_ ++B 4400,24000,300,300,CONT_VIA2,908nymous_ ++B 15600,32000,300,300,CONT_DIF_N,1230ymous_ ++B 5600,37600,300,300,CONT_BODY_P,962nymous_ ++B 7000,10000,300,300,CONT_VIA2,1016ymous_ ++B 18800,37600,300,300,CONT_BODY_P,1338ymous_ ++B 16800,34600,300,300,CONT_VIA2,1284ymous_ ++B 20800,30400,300,300,CONT_BODY_P,370nymous_ ++B 8600,24000,300,300,CONT_VIA2,1070ymous_ ++B 10600,19200,300,300,CONT_BODY_P,1124ymous_ ++B 26000,30000,300,300,CONT_DIF_P,478nymous_ ++B 24000,29200,300,300,CONT_POLY,424nymous_ ++B 29000,33000,300,300,CONT_POLY,585nymous_ ++B 30800,14000,300,300,CONT_DIF_P,639nymous_ ++B 12800,17000,300,300,CONT_VIA,1178ymous_ ++B 27800,37600,300,300,CONT_BODY_N,532nymous_ ++B 32200,33000,300,300,CONT_DIF_P,693nymous_ ++B 33800,34000,300,300,CONT_VIA,747nymous_ ++B 35600,14000,300,300,CONT_DIF_P,801nymous_ ++B 37000,29000,300,300,CONT_DIF_P,855nymous_ ++B 4400,25000,300,300,CONT_DIF_N,909nymous_ ++B 5600,37600,300,300,CONT_VIA,963nymous_ ++B 7000,11000,300,300,CONT_VIA2,1017ymous_ ++B 12800,17000,300,300,CONT_VIA2,1179ymous_ ++B 15600,33000,300,300,CONT_DIF_N,1231ymous_ ++B 18800,6000,300,300,CONT_BODY_P,1339ymous_ ++B 16800,35800,300,300,CONT_POLY,1285ymous_ ++B 24000,34200,300,300,CONT_POLY,425nymous_ ++B 20800,31400,300,300,CONT_BODY_P,371nymous_ ++B 29000,19200,300,300,CONT_BODY_N,586nymous_ ++B 8600,25000,300,300,CONT_VIA2,1071ymous_ ++B 10800,21800,300,300,CONT_POLY,1125ymous_ ++B 28000,0,300,300,CONT_VIA2,533nymous_ ++B 26000,31200,300,300,CONT_DIF_P,479nymous_ ++B 30800,16000,300,300,CONT_BODY_N,640nymous_ ++B 32200,34000,300,300,CONT_DIF_P,694nymous_ ++B 33800,34000,300,300,CONT_VIA2,748nymous_ ++B 35600,16000,300,300,CONT_BODY_N,802nymous_ ++B 37000,29000,300,300,CONT_VIA,856nymous_ ++B 4400,25000,300,300,CONT_VIA,910nymous_ ++B 5600,37600,300,300,CONT_VIA2,964nymous_ ++B 16800,35800,300,300,CONT_VIA,1286ymous_ ++B 15600,34000,300,300,CONT_DIF_N,1232ymous_ ++B 7600,21800,300,300,CONT_POLY,1018ymous_ ++B 8600,26000,300,300,CONT_VIA2,1072ymous_ ++B 18800,6000,300,300,CONT_VIA,1340ymous_ ++B 24000,34200,300,300,CONT_VIA,426nymous_ ++B 20800,32400,300,300,CONT_BODY_P,372nymous_ ++B 29600,33000,300,300,CONT_VIA2,587nymous_ ++B 10800,21800,300,300,CONT_VIA,1126ymous_ ++B 28000,0,300,300,CONT_VIA3,534nymous_ ++B 26000,31200,300,300,CONT_VIA,480nymous_ ++B 30800,17000,300,300,CONT_VIA,641nymous_ ++B 32200,35000,300,300,CONT_DIF_P,695nymous_ ++B 33800,35000,300,300,CONT_DIF_P,749nymous_ ++B 35600,17000,300,300,CONT_VIA,803nymous_ ++B 37000,29000,300,300,CONT_VIA2,857nymous_ ++B 4400,25000,300,300,CONT_VIA2,911nymous_ ++B 5600,6000,300,300,CONT_BODY_P,965nymous_ ++B 16800,37600,300,300,CONT_BODY_P,1287ymous_ ++B 15600,35000,300,300,CONT_DIF_N,1233ymous_ ++B 20800,33400,300,300,CONT_BODY_P,373nymous_ ++B 7600,21800,300,300,CONT_VIA,1019ymous_ ++B 8600,30000,300,300,CONT_VIA2,1073ymous_ ++B 18800,6000,300,300,CONT_VIA2,1341ymous_ ++B 26000,32400,300,300,CONT_DIF_P,481nymous_ ++B 24000,34200,300,300,CONT_VIA2,427nymous_ ++B 29600,34000,300,300,CONT_VIA2,588nymous_ ++B 30800,17000,300,300,CONT_VIA2,642nymous_ ++B 10800,21800,300,300,CONT_VIA2,1127ymous_ ++B 28000,0,300,300,CONT_VIA4,535nymous_ ++B 32200,36000,300,300,CONT_DIF_P,696nymous_ ++B 33800,35000,300,300,CONT_VIA,750nymous_ ++B 35600,17000,300,300,CONT_VIA2,804nymous_ ++B 37000,30000,300,300,CONT_DIF_P,858nymous_ ++B 4400,26000,300,300,CONT_DIF_N,912nymous_ ++B 15600,36000,300,300,CONT_DIF_N,1234ymous_ ++B 5600,6000,300,300,CONT_VIA,966nymous_ ++B 7600,23000,300,300,CONT_DIF_N,1020ymous_ ++B 18800,9000,300,300,CONT_DIF_N,1342ymous_ ++B 17400,11800,300,300,CONT_POLY,1288ymous_ ++B 20800,34400,300,300,CONT_BODY_P,374nymous_ ++B 8600,31000,300,300,CONT_VIA2,1074ymous_ ++B 10800,23000,300,300,CONT_DIF_N,1128ymous_ ++B 24000,35800,300,300,CONT_POLY,428nymous_ ++B 29600,35000,300,300,CONT_VIA2,589nymous_ ++B 28000,20400,300,300,CONT_DIF_P,536nymous_ ++B 26000,33600,300,300,CONT_DIF_P,482nymous_ ++B 31000,19200,300,300,CONT_BODY_N,643nymous_ ++B 32800,20200,300,300,CONT_POLY,697nymous_ ++B 33800,35000,300,300,CONT_VIA2,751nymous_ ++B 36000,20200,300,300,CONT_POLY,805nymous_ ++B 37000,30000,300,300,CONT_VIA,859nymous_ ++B 4400,26000,300,300,CONT_VIA,913nymous_ ++B 15600,19200,300,300,CONT_BODY_P,1235ymous_ ++B 5600,6000,300,300,CONT_VIA2,967nymous_ ++B 7600,23000,300,300,CONT_VIA,1021ymous_ ++B 18800,16000,300,300,CONT_BODY_N,1343ymous_ ++B 17600,6000,300,300,CONT_BODY_P,1289ymous_ ++B 24000,35800,300,300,CONT_VIA,429nymous_ ++B 20800,35400,300,300,CONT_BODY_P,375nymous_ ++B 29600,7000,300,300,CONT_DIF_N,590nymous_ ++B 8600,32000,300,300,CONT_VIA2,1075ymous_ ++B 10800,24000,300,300,CONT_DIF_N,1129ymous_ ++B 28000,21600,300,300,CONT_DIF_P,537nymous_ ++B 26000,33600,300,300,CONT_VIA,483nymous_ ++B 31600,20200,300,300,CONT_POLY,644nymous_ ++B 32800,22000,300,300,CONT_VIA2,698nymous_ ++B 33800,36000,300,300,CONT_DIF_P,752nymous_ ++B 36000,22000,300,300,CONT_VIA2,806nymous_ ++B 37000,31000,300,300,CONT_DIF_P,860nymous_ ++B 4400,26000,300,300,CONT_VIA2,914nymous_ ++B 5600,8000,300,300,CONT_DIF_N,968nymous_ ++B 17600,6000,300,300,CONT_VIA,1290ymous_ ++B 15800,27000,300,300,CONT_VIA2,1236ymous_ ++B 7600,24000,300,300,CONT_DIF_N,1022ymous_ ++B 18800,17000,300,300,CONT_VIA,1344ymous_ ++B 20800,36400,300,300,CONT_BODY_P,376nymous_ ++B 14000,21800,300,300,CONT_VIA,1182ymous_ ++B 8600,36000,300,300,CONT_VIA2,1076ymous_ ++B 24000,37600,300,300,CONT_BODY_N,430nymous_ ++B 29600,10600,300,300,CONT_POLY,591nymous_ ++B 10800,25000,300,300,CONT_DIF_N,1130ymous_ ++B 28000,22800,300,300,CONT_DIF_P,538nymous_ ++B 26000,35000,300,300,CONT_DIF_P,484nymous_ ++B 31600,22000,300,300,CONT_VIA2,645nymous_ ++B 32800,23000,300,300,CONT_VIA2,699nymous_ ++B 33800,36000,300,300,CONT_VIA,753nymous_ ++B 36000,23000,300,300,CONT_VIA2,807nymous_ ++B 37000,31000,300,300,CONT_VIA,861nymous_ ++B 4400,27000,300,300,CONT_DIF_N,915nymous_ ++B 5600,9000,300,300,CONT_DIF_N,969nymous_ ++B 17600,6000,300,300,CONT_VIA2,1291ymous_ ++B 15800,28000,300,300,CONT_VIA2,1237ymous_ ++B 20800,37600,300,300,CONT_BODY_P,377nymous_ ++B 7600,24000,300,300,CONT_VIA,1023ymous_ ++B 8600,19200,300,300,CONT_BODY_P,1077ymous_ ++B 18800,17000,300,300,CONT_VIA2,1345ymous_ ++B 26000,36400,300,300,CONT_DIF_P,485nymous_ ++B 24000,19200,300,300,CONT_BODY_N,431nymous_ ++B 29600,10600,300,300,CONT_VIA,592nymous_ ++B 31600,23000,300,300,CONT_VIA2,646nymous_ ++B 10800,26000,300,300,CONT_DIF_N,1131ymous_ ++B 28000,24000,300,300,CONT_DIF_P,539nymous_ ++B 32800,27000,300,300,CONT_VIA2,700nymous_ ++B 34000,19200,300,300,CONT_BODY_N,754nymous_ ++B 36000,27000,300,300,CONT_VIA2,808nymous_ ++B 37000,32000,300,300,CONT_DIF_P,862nymous_ ++B 4400,27000,300,300,CONT_VIA,916nymous_ ++B 14000,23000,300,300,CONT_DIF_N,1184ymous_ ++B 14000,21800,300,300,CONT_VIA2,1183ymous_ ++B 13600,19200,300,300,CONT_BODY_P,1180ymous_ ++B 15800,29000,300,300,CONT_VIA2,1238ymous_ ++B 5600,11800,300,300,CONT_DIF_P,970nymous_ ++B 7600,24000,300,300,CONT_VIA2,1024ymous_ ++B 19600,19200,300,300,CONT_BODY_P,1346ymous_ ++B 17600,8600,300,300,CONT_DIF_N,1292ymous_ ++B 20800,19200,300,300,CONT_BODY_P,378nymous_ ++B 8800,37600,300,300,CONT_BODY_P,1078ymous_ ++B 10800,27000,300,300,CONT_DIF_N,1132ymous_ ++B 26000,37600,300,300,CONT_BODY_N,486nymous_ ++B 24800,6000,300,300,CONT_BODY_P,432nymous_ ++B 29600,13000,300,300,CONT_DIF_P,593nymous_ ++B 31600,27000,300,300,CONT_VIA2,647nymous_ ++B 32800,28000,300,300,CONT_VIA2,701nymous_ ++B 3400,24000,300,300,CONT_VIA2,755nymous_ ++B 36000,28000,300,300,CONT_VIA2,809nymous_ ++B 37000,32000,300,300,CONT_VIA,863nymous_ ++B 4400,28000,300,300,CONT_DIF_N,917nymous_ ++B 15800,37600,300,300,CONT_BODY_P,1239ymous_ ++B 14000,24000,300,300,CONT_DIF_N,1185ymous_ ++B 5600,12800,300,300,CONT_DIF_P,971nymous_ ++B 7600,25000,300,300,CONT_DIF_N,1025ymous_ ++B 19800,22600,300,300,CONT_POLY,1347ymous_ ++B 17600,12800,300,300,CONT_DIF_P,1293ymous_ ++B 24800,6000,300,300,CONT_VIA,433nymous_ ++B 21200,6000,300,300,CONT_BODY_P,379nymous_ ++B 29600,14000,300,300,CONT_DIF_P,594nymous_ ++B 8800,37600,300,300,CONT_VIA,1079ymous_ ++B 10800,28000,300,300,CONT_DIF_N,1133ymous_ ++B 14000,21800,300,300,CONT_POLY,1181ymous_ ++B 26000,6000,300,300,CONT_BODY_P,487nymous_ ++B 31600,28000,300,300,CONT_VIA2,648nymous_ ++B 32800,29000,300,300,CONT_VIA2,702nymous_ ++B 3400,25000,300,300,CONT_VIA2,756nymous_ ++B 36000,29000,300,300,CONT_VIA2,810nymous_ ++B 37000,33000,300,300,CONT_DIF_P,864nymous_ ++B 14000,25000,300,300,CONT_DIF_N,1186ymous_ ++B 4400,28000,300,300,CONT_VIA,918nymous_ ++B 5600,13800,300,300,CONT_DIF_P,972nymous_ ++B 17600,16000,300,300,CONT_BODY_N,1294ymous_ ++B 1600,20400,300,300,CONT_BODY_P,1240ymous_ ++B 7600,25000,300,300,CONT_VIA,1026ymous_ ++B 8800,37600,300,300,CONT_VIA2,1080ymous_ ++B 19800,26200,300,300,CONT_POLY,1348ymous_ ++B 24800,6000,300,300,CONT_VIA2,434nymous_ ++B 21200,6000,300,300,CONT_VIA,380nymous_ ++B 29600,16000,300,300,CONT_BODY_N,595nymous_ ++B 10800,29000,300,300,CONT_DIF_N,1134ymous_ ++B 26000,6000,300,300,CONT_VIA,488nymous_ ++B 31600,29000,300,300,CONT_VIA2,649nymous_ ++B 32800,33000,300,300,CONT_VIA2,703nymous_ ++B 3400,26000,300,300,CONT_VIA2,757nymous_ ++B 36000,33000,300,300,CONT_VIA2,811nymous_ ++B 37000,33000,300,300,CONT_VIA,865nymous_ ++B 14000,26000,300,300,CONT_DIF_N,1187ymous_ ++B 4400,29000,300,300,CONT_DIF_N,919nymous_ ++B 5600,16000,300,300,CONT_BODY_N,973nymous_ ++B 17600,17000,300,300,CONT_VIA,1295ymous_ ++B 1600,21400,300,300,CONT_BODY_P,1241ymous_ ++B 21200,6000,300,300,CONT_VIA2,381nymous_ ++B 7600,25000,300,300,CONT_VIA2,1027ymous_ ++B 9200,23000,300,300,CONT_DIF_N,1081ymous_ ++B 19800,27400,300,300,CONT_POLY,1349ymous_ ++B 24800,8000,300,300,CONT_DIF_N,435nymous_ ++B 26000,6000,300,300,CONT_VIA2,489nymous_ ++B 29600,17000,300,300,CONT_VIA,596nymous_ ++B 31600,33000,300,300,CONT_VIA2,650nymous_ ++B 10800,30000,300,300,CONT_DIF_N,1135ymous_ ++B 32800,34000,300,300,CONT_VIA2,704nymous_ ++B 3400,30000,300,300,CONT_VIA2,758nymous_ ++B 36000,34000,300,300,CONT_VIA2,812nymous_ ++B 37000,33000,300,300,CONT_VIA2,866nymous_ ++B 4400,29000,300,300,CONT_VIA,920nymous_ ++B 1600,22400,300,300,CONT_BODY_P,1242ymous_ ++B 14000,27000,300,300,CONT_DIF_N,1188ymous_ ++B 5600,17000,300,300,CONT_VIA,974nymous_ ++B 7600,26000,300,300,CONT_DIF_N,1028ymous_ ++B 19800,28200,300,300,CONT_VIA,1350ymous_ ++B 17600,17000,300,300,CONT_VIA2,1296ymous_ ++B 21200,9000,300,300,CONT_DIF_N,382nymous_ ++B 28000,28800,300,300,CONT_DIF_P,543nymous_ ++B 9200,24000,300,300,CONT_DIF_N,1082ymous_ ++B 10800,31000,300,300,CONT_DIF_N,1136ymous_ ++B 26000,8000,300,300,CONT_DIF_N,490nymous_ ++B 24800,13000,300,300,CONT_DIF_P,436nymous_ ++B 29600,17000,300,300,CONT_VIA2,597nymous_ ++B 31600,34000,300,300,CONT_VIA2,651nymous_ ++B 32800,35000,300,300,CONT_VIA2,705nymous_ ++B 3400,31000,300,300,CONT_VIA2,759nymous_ ++B 36000,35000,300,300,CONT_VIA2,813nymous_ ++B 37000,34000,300,300,CONT_DIF_P,867nymous_ ++B 4400,30000,300,300,CONT_DIF_N,921nymous_ ++B 14000,28000,300,300,CONT_DIF_N,1189ymous_ ++B 5600,17000,300,300,CONT_VIA2,975nymous_ ++B 7600,26000,300,300,CONT_VIA,1029ymous_ ++B 28000,27600,300,300,CONT_DIF_P,542nymous_ ++B 1600,23400,300,300,CONT_BODY_P,1243ymous_ ++B 19800,31000,300,300,CONT_POLY,1351ymous_ ++B 17600,19200,300,300,CONT_BODY_P,1297ymous_ ++B 24800,13000,300,300,CONT_VIA,437nymous_ ++B 21200,16000,300,300,CONT_BODY_N,383nymous_ ++B 28000,30000,300,300,CONT_DIF_P,544nymous_ ++B 30000,0,300,300,CONT_VIA2,598nymous_ ++B 9200,25000,300,300,CONT_DIF_N,1083ymous_ ++B 10800,32000,300,300,CONT_DIF_N,1137ymous_ ++B 26000,12000,300,300,CONT_VIA2,491nymous_ ++B 31600,35000,300,300,CONT_VIA2,652nymous_ ++B 33000,19200,300,300,CONT_BODY_N,706nymous_ ++B 3400,32000,300,300,CONT_VIA2,760nymous_ ++B 36000,19200,300,300,CONT_BODY_N,814nymous_ ++B 37000,34000,300,300,CONT_VIA,868nymous_ ++B 14000,29000,300,300,CONT_DIF_N,1190ymous_ ++B 4400,30000,300,300,CONT_VIA,922nymous_ ++B 5600,19200,300,300,CONT_BODY_P,976nymous_ ++B 17800,23200,300,300,CONT_DIF_N,1298ymous_ ++B 1600,24400,300,300,CONT_BODY_P,1244ymous_ ++B 7600,26000,300,300,CONT_VIA2,1030ymous_ ++B 9200,26000,300,300,CONT_DIF_N,1084ymous_ ++B 19800,35200,300,300,CONT_VIA,1352ymous_ ++B 24800,14000,300,300,CONT_DIF_P,438nymous_ ++B 22000,22200,300,300,CONT_VIA,384nymous_ ++B 28000,31200,300,300,CONT_DIF_P,545nymous_ ++B 30000,0,300,300,CONT_VIA3,599nymous_ ++B 10800,33000,300,300,CONT_DIF_N,1138ymous_ ++B 26000,13000,300,300,CONT_DIF_P,492nymous_ ++B 31800,9000,300,300,CONT_POLY,653nymous_ ++B 33200,6000,300,300,CONT_BODY_P,707nymous_ ++B 3400,36000,300,300,CONT_VIA2,761nymous_ ++B 3600,37600,300,300,CONT_BODY_P,815nymous_ ++B 37000,34000,300,300,CONT_VIA2,869nymous_ ++B 14000,30000,300,300,CONT_DIF_N,1191ymous_ ++B 4400,30000,300,300,CONT_VIA2,923nymous_ ++B 6000,23000,300,300,CONT_DIF_N,977nymous_ ++B 17800,23200,300,300,CONT_VIA,1299ymous_ ++B 1600,25400,300,300,CONT_BODY_P,1245ymous_ ++B 22000,19200,300,300,CONT_VIA,385nymous_ ++B 28000,31200,300,300,CONT_VIA,546nymous_ ++B 7600,27000,300,300,CONT_DIF_N,1031ymous_ ++B 9200,27000,300,300,CONT_DIF_N,1085ymous_ ++B 19800,37600,300,300,CONT_BODY_P,1353ymous_ ++B 26000,13000,300,300,CONT_VIA2,493nymous_ ++B 24800,14000,300,300,CONT_VIA,439nymous_ ++B 30000,0,300,300,CONT_VIA4,600nymous_ ++B 31800,12200,300,300,CONT_POLY,654nymous_ ++B 10800,34000,300,300,CONT_DIF_N,1139ymous_ ++B 33200,6000,300,300,CONT_VIA,708nymous_ ++B 34400,6000,300,300,CONT_BODY_P,762nymous_ ++B 3600,37600,300,300,CONT_VIA,816nymous_ ++B 37000,35000,300,300,CONT_DIF_P,870nymous_ ++B 4400,31000,300,300,CONT_DIF_N,924nymous_ ++B 1600,26400,300,300,CONT_BODY_P,1246ymous_ ++B 14000,31000,300,300,CONT_DIF_N,1192ymous_ ++B 6000,24000,300,300,CONT_DIF_N,978nymous_ ++B 7600,27000,300,300,CONT_VIA,1032ymous_ ++B 17800,24400,300,300,CONT_DIF_N,1300ymous_ ++B 22400,6000,300,300,CONT_BODY_P,386nymous_ ++B 28000,32400,300,300,CONT_DIF_P,547nymous_ ++B 9200,28000,300,300,CONT_DIF_N,1086ymous_ ++B 24800,16000,300,300,CONT_BODY_N,440nymous_ ++B 10800,35000,300,300,CONT_DIF_N,1140ymous_ ++B 26000,14000,300,300,CONT_DIF_P,494nymous_ ++B 30000,20200,300,300,CONT_VIA,601nymous_ ++B 32000,6000,300,300,CONT_BODY_P,655nymous_ ++B 33200,6000,300,300,CONT_VIA2,709nymous_ ++B 34400,6000,300,300,CONT_VIA,763nymous_ ++B 3600,37600,300,300,CONT_VIA2,817nymous_ ++B 37000,35000,300,300,CONT_VIA,871nymous_ ++B 4400,31000,300,300,CONT_VIA,925nymous_ ++B 1600,27400,300,300,CONT_BODY_P,1247ymous_ ++B 14000,32000,300,300,CONT_DIF_N,1193ymous_ ++B 6000,25000,300,300,CONT_DIF_N,979nymous_ ++B 7600,28000,300,300,CONT_DIF_N,1033ymous_ ++B 17800,24400,300,300,CONT_VIA2,1301ymous_ ++B 25000,20400,300,300,CONT_DIF_P,441nymous_ ++B 22400,6000,300,300,CONT_VIA,387nymous_ ++B 28000,33600,300,300,CONT_DIF_P,548nymous_ ++B 30000,19200,300,300,CONT_BODY_N,602nymous_ ++B 9200,29000,300,300,CONT_DIF_N,1087ymous_ ++B 10800,36000,300,300,CONT_DIF_N,1141ymous_ ++B 26000,14000,300,300,CONT_VIA2,495nymous_ ++B 32000,6000,300,300,CONT_VIA,656nymous_ ++B 33200,8000,300,300,CONT_DIF_N,710nymous_ ++B 34400,6000,300,300,CONT_VIA2,764nymous_ ++B 3600,19200,300,300,CONT_BODY_P,818nymous_ ++B 37000,35000,300,300,CONT_VIA2,872nymous_ ++B 14000,33000,300,300,CONT_DIF_N,1194ymous_ ++B 4400,31000,300,300,CONT_VIA2,926nymous_ ++B 6000,26000,300,300,CONT_DIF_N,980nymous_ ++B 1600,28400,300,300,CONT_BODY_P,1248ymous_ ++B 7600,28000,300,300,CONT_VIA,1034ymous_ ++B 17800,25600,300,300,CONT_DIF_N,1302ymous_ ++B 9200,30000,300,300,CONT_DIF_N,1088ymous_ ++B 25000,20400,300,300,CONT_VIA,442nymous_ ++B 22400,6000,300,300,CONT_VIA2,388nymous_ ++B 28000,35000,300,300,CONT_DIF_P,549nymous_ ++B 30400,36600,300,300,CONT_POLY,603nymous_ ++B 11600,6000,300,300,CONT_BODY_P,1142ymous_ ++B 26000,16000,300,300,CONT_BODY_N,496nymous_ ++B 32000,6000,300,300,CONT_VIA2,657nymous_ ++B 33200,13000,300,300,CONT_DIF_P,711nymous_ ++B 34400,8000,300,300,CONT_DIF_N,765nymous_ ++B 36800,6000,300,300,CONT_BODY_P,819nymous_ ++B 37000,36000,300,300,CONT_DIF_P,873nymous_ ++B 14000,34000,300,300,CONT_DIF_N,1195ymous_ ++B 4400,32000,300,300,CONT_DIF_N,927nymous_ ++B 6000,27000,300,300,CONT_DIF_N,981nymous_ ++B 17800,25600,300,300,CONT_VIA,1303ymous_ ++B 1600,29400,300,300,CONT_BODY_P,1249ymous_ ++B 22400,8600,300,300,CONT_DIF_N,389nymous_ ++B 28000,19200,300,300,CONT_BODY_N,550nymous_ ++B 7600,29000,300,300,CONT_DIF_N,1035ymous_ ++B 9200,31000,300,300,CONT_DIF_N,1089ymous_ ++B 26000,17000,300,300,CONT_VIA,497nymous_ ++B 25000,21600,300,300,CONT_DIF_P,443nymous_ ++B 30400,36600,300,300,CONT_VIA,604nymous_ ++B 32000,8000,300,300,CONT_DIF_N,658nymous_ ++B 11600,6000,300,300,CONT_VIA,1143ymous_ ++B 33200,14000,300,300,CONT_DIF_P,712nymous_ ++B 34400,13000,300,300,CONT_DIF_P,766nymous_ ++B 36800,6000,300,300,CONT_VIA,820nymous_ ++B 37000,36000,300,300,CONT_VIA,874nymous_ ++B 4400,32000,300,300,CONT_VIA,928nymous_ ++B 1600,30400,300,300,CONT_BODY_P,1250ymous_ ++B 14000,35000,300,300,CONT_DIF_N,1196ymous_ ++B 6000,28000,300,300,CONT_DIF_N,982nymous_ ++B 7600,29000,300,300,CONT_VIA,1036ymous_ ++B 17800,25600,300,300,CONT_VIA2,1304ymous_ ++B 22400,16000,300,300,CONT_BODY_N,390nymous_ ++B 2800,23000,300,300,CONT_DIF_N,551nymous_ ++B 9200,32000,300,300,CONT_DIF_N,1090ymous_ ++B 11600,6000,300,300,CONT_VIA2,1144ymous_ ++B 26000,17000,300,300,CONT_VIA2,498nymous_ ++B 25000,22800,300,300,CONT_DIF_P,444nymous_ ++B 30400,36600,300,300,CONT_VIA2,605nymous_ ++B 32000,13000,300,300,CONT_DIF_P,659nymous_ ++B 33200,16000,300,300,CONT_BODY_N,713nymous_ ++B 34400,13000,300,300,CONT_VIA,767nymous_ ++B 36800,6000,300,300,CONT_VIA2,821nymous_ ++B 37000,19200,300,300,CONT_BODY_N,875nymous_ ++B 4400,32000,300,300,CONT_VIA2,929nymous_ ++B 1600,31400,300,300,CONT_BODY_P,1251ymous_ ++B 14000,36000,300,300,CONT_DIF_N,1197ymous_ ++B 6000,29000,300,300,CONT_DIF_N,983nymous_ ++B 7600,30000,300,300,CONT_DIF_N,1037ymous_ ++B 17800,26800,300,300,CONT_DIF_N,1305ymous_ ++B 22400,17000,300,300,CONT_VIA,391nymous_ ++B 2800,24000,300,300,CONT_DIF_N,552nymous_ ++B 9200,33000,300,300,CONT_DIF_N,1091ymous_ ++B 11600,8000,300,300,CONT_DIF_N,1145ymous_ ++B 26000,19200,300,300,CONT_BODY_N,499nymous_ ++B 25000,22800,300,300,CONT_VIA,445nymous_ ++B 30600,22000,300,300,CONT_DIF_P,606nymous_ ++B 32000,16000,300,300,CONT_BODY_N,660nymous_ ++B 33200,17000,300,300,CONT_VIA,714nymous_ ++B 34400,14000,300,300,CONT_DIF_P,768nymous_ ++B 36800,7000,300,300,CONT_BODY_P,822nymous_ ++B 37200,37600,300,300,CONT_BODY_N,876nymous_ ++B 14000,6000,300,300,CONT_BODY_P,1198ymous_ ++B 4400,33000,300,300,CONT_DIF_N,930nymous_ ++B 6000,30000,300,300,CONT_DIF_N,984nymous_ ++B 17800,28000,300,300,CONT_DIF_N,1306ymous_ ++B 1600,32400,300,300,CONT_BODY_P,1252ymous_ ++B 7600,30000,300,300,CONT_VIA,1038ymous_ ++B 9200,34000,300,300,CONT_DIF_N,1092ymous_ ++B 25000,24000,300,300,CONT_DIF_P,446nymous_ ++B 22400,17000,300,300,CONT_VIA2,392nymous_ ++B 2800,25000,300,300,CONT_DIF_N,553nymous_ ++B 30600,23000,300,300,CONT_DIF_P,607nymous_ ++B 11600,9000,300,300,CONT_DIF_N,1146ymous_ ++B 2600,37600,300,300,CONT_BODY_P,500nymous_ ++B 32000,17000,300,300,CONT_VIA,661nymous_ ++B 33200,17000,300,300,CONT_VIA2,715nymous_ ++B 34400,14000,300,300,CONT_VIA,769nymous_ ++B 36800,8000,300,300,CONT_BODY_P,823nymous_ ++B 38000,27000,300,300,CONT_VIA2,877nymous_ ++B 14000,6000,300,300,CONT_VIA,1199ymous_ ++B 4400,33000,300,300,CONT_VIA,931nymous_ ++B 6000,31000,300,300,CONT_DIF_N,985nymous_ ++B 1600,33400,300,300,CONT_BODY_P,1253ymous_ ++B 7600,30000,300,300,CONT_VIA2,1039ymous_ ++B 9200,35000,300,300,CONT_DIF_N,1093ymous_ ++B 17800,28000,300,300,CONT_VIA,1307ymous_ ++B 23000,20400,300,300,CONT_BODY_N,393nymous_ ++B 2800,26000,300,300,CONT_DIF_N,554nymous_ ++B 2600,19200,300,300,CONT_BODY_P,501nymous_ ++B 25000,25200,300,300,CONT_DIF_P,447nymous_ ++B 30600,24000,300,300,CONT_DIF_P,608nymous_ ++B 32000,17000,300,300,CONT_VIA2,662nymous_ ++B 11600,11800,300,300,CONT_DIF_P,1147ymous_ ++B 33800,22000,300,300,CONT_DIF_P,716nymous_ ++B 34400,16000,300,300,CONT_BODY_N,770nymous_ ++B 36800,9000,300,300,CONT_BODY_P,824nymous_ ++B 38000,28000,300,300,CONT_VIA2,878nymous_ ++B 4400,34000,300,300,CONT_DIF_N,932nymous_ ++B 1600,34400,300,300,CONT_BODY_P,1254ymous_ ++B 14000,6000,300,300,CONT_VIA2,1200ymous_ ++B 6000,32000,300,300,CONT_DIF_N,986nymous_ ++B 7600,31000,300,300,CONT_DIF_N,1040ymous_ ++B 17800,29200,300,300,CONT_DIF_N,1308ymous_ ++B 23000,21400,300,300,CONT_BODY_N,394nymous_ ++B 2800,27000,300,300,CONT_DIF_N,555nymous_ ++B 9200,36000,300,300,CONT_DIF_N,1094ymous_ ++B 11600,12800,300,300,CONT_DIF_P,1148ymous_ ++B 27000,20400,300,300,CONT_DIF_P,502nymous_ ++B 25000,26400,300,300,CONT_DIF_P,448nymous_ ++B 30600,25000,300,300,CONT_DIF_P,609nymous_ ++B 32000,19200,300,300,CONT_BODY_N,663nymous_ ++B 33800,22000,300,300,CONT_VIA,717nymous_ ++B 34800,20200,300,300,CONT_POLY,771nymous_ ++B 36800,9000,300,300,CONT_VIA2,825nymous_ ++B 38000,29000,300,300,CONT_VIA2,879nymous_ ++B 4400,34000,300,300,CONT_VIA,933nymous_ ++B 1600,35400,300,300,CONT_BODY_P,1255ymous_ ++B 14000,7200,300,300,CONT_DIF_N,1201ymous_ ++B 6000,33000,300,300,CONT_DIF_N,987nymous_ ++B 7600,31000,300,300,CONT_VIA,1041ymous_ ++B 17800,30400,300,300,CONT_DIF_N,1309ymous_ ++B 25000,27600,300,300,CONT_DIF_P,449nymous_ ++B 23000,22400,300,300,CONT_BODY_N,395nymous_ ++B 2800,28000,300,300,CONT_DIF_N,556nymous_ ++B 30600,26000,300,300,CONT_DIF_P,610nymous_ ++B 9200,6000,300,300,CONT_BODY_P,1095ymous_ ++B 11600,13800,300,300,CONT_DIF_P,1149ymous_ ++B 27000,21600,300,300,CONT_DIF_P,503nymous_ ++B 3200,6000,300,300,CONT_BODY_P,664nymous_ ++B 33800,22000,300,300,CONT_VIA2,718nymous_ ++B 34800,22000,300,300,CONT_VIA2,772nymous_ ++B 36800,10000,300,300,CONT_VIA2,826nymous_ ++B 38000,33000,300,300,CONT_VIA2,880nymous_ ++B 14000,8000,300,300,CONT_DIF_N,1202ymous_ ++B 4400,35000,300,300,CONT_DIF_N,934nymous_ ++B 6000,34000,300,300,CONT_DIF_N,988nymous_ ++B 17800,30400,300,300,CONT_VIA,1310ymous_ ++B 1600,36400,300,300,CONT_BODY_P,1256ymous_ ++B 7600,31000,300,300,CONT_VIA2,1042ymous_ ++B 9200,6000,300,300,CONT_VIA,1096ymous_ ++B 25000,27600,300,300,CONT_VIA,450nymous_ ++B 23000,23400,300,300,CONT_BODY_N,396nymous_ ++B 2800,29000,300,300,CONT_DIF_N,557nymous_ ++B 11600,14800,300,300,CONT_DIF_P,1150ymous_ ++B 27000,22800,300,300,CONT_DIF_P,504nymous_ ++B 30600,27000,300,300,CONT_DIF_P,611nymous_ ++B 3200,6000,300,300,CONT_VIA,665nymous_ ++B 33800,23000,300,300,CONT_DIF_P,719nymous_ ++B 34800,23000,300,300,CONT_VIA2,773nymous_ ++B 36800,11000,300,300,CONT_VIA2,827nymous_ ++B 38000,34000,300,300,CONT_VIA2,881nymous_ ++B 14000,10000,300,300,CONT_POLY,1203ymous_ ++B 4400,35000,300,300,CONT_VIA,935nymous_ ++B 6000,35000,300,300,CONT_DIF_N,989nymous_ ++B 17800,30400,300,300,CONT_VIA2,1311ymous_ ++B 1600,37600,300,300,CONT_BODY_P,1257ymous_ ++B 23000,24400,300,300,CONT_BODY_N,397nymous_ ++B 2800,30000,300,300,CONT_DIF_N,558nymous_ ++B 7600,32000,300,300,CONT_DIF_N,1043ymous_ ++B 9200,6000,300,300,CONT_VIA2,1097ymous_ ++B 27000,24000,300,300,CONT_DIF_P,505nymous_ ++B 25000,28800,300,300,CONT_DIF_P,451nymous_ ++B 30600,27000,300,300,CONT_VIA,612nymous_ ++B 3200,6000,300,300,CONT_VIA2,666nymous_ ++B 11600,16000,300,300,CONT_BODY_N,1151ymous_ ++B 33800,23000,300,300,CONT_VIA,720nymous_ ++B 34800,27000,300,300,CONT_VIA2,774nymous_ ++B 36800,12000,300,300,CONT_BODY_N,828nymous_ ++B 38000,35000,300,300,CONT_VIA2,882nymous_ ++B 4400,36000,300,300,CONT_DIF_N,936nymous_ ++B 1600,19200,300,300,CONT_BODY_P,1258ymous_ ++B 14000,12000,300,300,CONT_DIF_P,1204ymous_ ++B 6000,36000,300,300,CONT_DIF_N,990nymous_ ++B 7600,32000,300,300,CONT_VIA,1044ymous_ ++B 17800,31600,300,300,CONT_DIF_N,1312ymous_ ++B 9200,7000,300,300,CONT_VIA2,1098ymous_ ++B 4400,36000,300,300,CONT_VIA2,938nymous_ ++B 38200,21400,300,300,CONT_BODY_N,884nymous_ ++B 36800,14000,300,300,CONT_BODY_N,830nymous_ ++B 34800,29000,300,300,CONT_VIA2,776nymous_ ++B 33800,24000,300,300,CONT_DIF_P,722nymous_ ++B 3200,7000,300,300,CONT_VIA2,668nymous_ ++B 27000,25200,300,300,CONT_VIA,507nymous_ ++B 11600,17000,300,300,CONT_VIA2,1153ymous_ ++B 9200,7200,300,300,CONT_DIF_N,1099ymous_ ++B 30600,28000,300,300,CONT_DIF_P,614nymous_ ++B 2800,32000,300,300,CONT_DIF_N,560nymous_ ++B 23000,26400,300,300,CONT_BODY_N,399nymous_ ++B 25000,30000,300,300,CONT_VIA,453nymous_ ++B 17800,31600,300,300,CONT_VIA2,1313ymous_ ++B 7600,32000,300,300,CONT_VIA2,1045ymous_ ++B 6600,24000,300,300,CONT_VIA2,991nymous_ ++B 14000,12800,300,300,CONT_DIF_P,1205ymous_ ++B 16400,6000,300,300,CONT_BODY_P,1259ymous_ ++B 4400,36000,300,300,CONT_VIA,937nymous_ ++B 38200,20400,300,300,CONT_BODY_N,883nymous_ ++B 36800,13000,300,300,CONT_BODY_N,829nymous_ ++B 34800,28000,300,300,CONT_VIA2,775nymous_ ++B 33800,23000,300,300,CONT_VIA2,721nymous_ ++B 3200,7000,300,300,CONT_BODY_P,667nymous_ ++B 30600,27000,300,300,CONT_VIA2,613nymous_ ++B 23000,25400,300,300,CONT_BODY_N,398nymous_ ++B 2800,31000,300,300,CONT_DIF_N,559nymous_ ++B 11600,17000,300,300,CONT_VIA,1152ymous_ ++B 27000,25200,300,300,CONT_DIF_P,506nymous_ ++B 25000,30000,300,300,CONT_DIF_P,452nymous_ ++B 12400,23000,300,300,CONT_DIF_N,1155ymous_ ++B 30600,28000,300,300,CONT_VIA2,616nymous_ ++B 25000,32400,300,300,CONT_DIF_P,455nymous_ ++B 9200,8000,300,300,CONT_VIA2,1101ymous_ ++B 7600,33000,300,300,CONT_VIA,1047ymous_ ++B 2800,34000,300,300,CONT_DIF_N,562nymous_ ++B 23000,28400,300,300,CONT_BODY_N,401nymous_ ++B 16400,6000,300,300,CONT_VIA2,1261ymous_ ++B 17800,34000,300,300,CONT_DIF_N,1315ymous_ ++B 6600,26000,300,300,CONT_VIA2,993nymous_ ++B 4400,6000,300,300,CONT_BODY_P,939nymous_ ++B 14000,17000,300,300,CONT_VIA,1207ymous_ ++B 38200,22400,300,300,CONT_BODY_N,885nymous_ ++B 36800,15000,300,300,CONT_BODY_N,831nymous_ ++B 34800,33000,300,300,CONT_VIA2,777nymous_ ++B 33800,24000,300,300,CONT_VIA,723nymous_ ++B 3200,8000,300,300,CONT_BODY_P,669nymous_ ++B 27000,26400,300,300,CONT_DIF_P,508nymous_ ++B 11600,19200,300,300,CONT_BODY_P,1154ymous_ ++B 30600,28000,300,300,CONT_VIA,615nymous_ ++B 2800,33000,300,300,CONT_DIF_N,561nymous_ ++B 23000,27400,300,300,CONT_BODY_N,400nymous_ ++B 25000,31200,300,300,CONT_DIF_P,454nymous_ ++B 9200,8000,300,300,CONT_DIF_N,1100ymous_ ++B 7600,33000,300,300,CONT_DIF_N,1046ymous_ ++B 16400,6000,300,300,CONT_VIA,1260ymous_ ++B 17800,32800,300,300,CONT_DIF_N,1314ymous_ ++B 6600,25000,300,300,CONT_VIA2,992nymous_ ++B 14000,16000,300,300,CONT_BODY_N,1206ymous_ ++B 33800,28000,300,300,CONT_DIF_P,731nymous_ ++B 30600,29000,300,300,CONT_DIF_P,617nymous_ ++B 25000,32400,300,300,CONT_VIA,456nymous_ ++B 27000,28800,300,300,CONT_DIF_P,510nymous_ ++B 12400,24000,300,300,CONT_DIF_N,1156ymous_ ++B 9200,10000,300,300,CONT_POLY,1102ymous_ ++B 2800,35000,300,300,CONT_DIF_N,563nymous_ ++B 23000,29400,300,300,CONT_BODY_N,402nymous_ ++B 17800,35200,300,300,CONT_DIF_N,1316ymous_ ++B 7600,34000,300,300,CONT_DIF_N,1048ymous_ ++B 6600,30000,300,300,CONT_VIA2,994nymous_ ++B 14000,17000,300,300,CONT_VIA2,1208ymous_ ++B 16400,8000,300,300,CONT_DIF_N,1262ymous_ ++B 4400,6000,300,300,CONT_VIA,940nymous_ ++B 38200,23400,300,300,CONT_BODY_N,886nymous_ ++B 36800,15000,300,300,CONT_VIA2,832nymous_ ++B 34800,34000,300,300,CONT_VIA2,778nymous_ ++B 33800,25000,300,300,CONT_DIF_P,724nymous_ ++B 3200,8000,300,300,CONT_VIA2,670nymous_ ++B 27000,27600,300,300,CONT_DIF_P,509nymous_ ++B 12800,11600,300,300,CONT_DIF_P,1175ymous_ ++B 3200,9000,300,300,CONT_BODY_P,671nymous_ ++B 33800,25000,300,300,CONT_VIA,725nymous_ ++B 34800,35000,300,300,CONT_VIA2,779nymous_ ++B 36800,16000,300,300,CONT_BODY_N,833nymous_ ++B 38200,24400,300,300,CONT_BODY_N,887nymous_ ++B 4400,6000,300,300,CONT_VIA2,941nymous_ ++B 16400,9000,300,300,CONT_DIF_N,1263ymous_ ++B 14600,19200,300,300,CONT_BODY_P,1209ymous_ ++B 6600,31000,300,300,CONT_VIA2,995nymous_ ++B 7600,34000,300,300,CONT_VIA,1049ymous_ ++B 17800,36400,300,300,CONT_DIF_N,1317ymous_ ++B 28000,26400,300,300,CONT_DIF_P,541nymous_ ++B 25000,33600,300,300,CONT_DIF_P,457nymous_ ++B 23000,30400,300,300,CONT_BODY_N,403nymous_ ++B 2800,36000,300,300,CONT_DIF_N,564nymous_ ++B 30600,29000,300,300,CONT_VIA,618nymous_ ++B 9200,12000,300,300,CONT_DIF_P,1103ymous_ ++B 12400,25000,300,300,CONT_DIF_N,1157ymous_ ++B 27000,30000,300,300,CONT_DIF_P,511nymous_ ++B 3200,12000,300,300,CONT_BODY_N,672nymous_ ++B 33800,26000,300,300,CONT_DIF_P,726nymous_ ++B 35000,19200,300,300,CONT_BODY_N,780nymous_ ++B 36800,16000,300,300,CONT_VIA2,834nymous_ ++B 38200,25400,300,300,CONT_BODY_N,888nymous_ ++B 15200,6000,300,300,CONT_BODY_P,1210ymous_ ++B 4400,8000,300,300,CONT_DIF_N,942nymous_ ++B 6600,32000,300,300,CONT_VIA2,996nymous_ ++B 17800,37600,300,300,CONT_BODY_P,1318ymous_ ++B 16400,10000,300,300,CONT_POLY,1264ymous_ ++B 7600,35000,300,300,CONT_DIF_N,1050ymous_ ++B 9200,12800,300,300,CONT_DIF_P,1104ymous_ ++B 25000,35000,300,300,CONT_DIF_P,458nymous_ ++B 23000,31400,300,300,CONT_BODY_N,404nymous_ ++B 28200,10600,300,300,CONT_VIA,565nymous_ ++B 30600,29000,300,300,CONT_VIA2,619nymous_ ++B 12400,26000,300,300,CONT_DIF_N,1158ymous_ ++B 27000,31200,300,300,CONT_DIF_P,512nymous_ ++B 3200,12000,300,300,CONT_VIA2,673nymous_ ++B 33800,26000,300,300,CONT_VIA,727nymous_ ++B 35400,22000,300,300,CONT_DIF_P,781nymous_ ++B 36800,17000,300,300,CONT_VIA,835nymous_ ++B 20000,6000,300,300,CONT_BODY_P,354nymous_ ++B 20000,6000,300,300,CONT_VIA,355nymous_ ++B 38200,26400,300,300,CONT_BODY_N,889nymous_ ++B 15200,6000,300,300,CONT_VIA,1211ymous_ ++B 4400,9000,300,300,CONT_DIF_N,943nymous_ ++B 6600,36000,300,300,CONT_VIA2,997nymous_ ++B 18600,19200,300,300,CONT_BODY_P,1319ymous_ ++B 16400,12000,300,300,CONT_DIF_P,1265ymous_ ++B 23000,32400,300,300,CONT_BODY_N,405nymous_ ++B 28200,11800,300,300,CONT_POLY,566nymous_ ++B 7600,35000,300,300,CONT_VIA,1051ymous_ ++B 9200,13800,300,300,CONT_DIF_P,1105ymous_ ++B 27000,32400,300,300,CONT_DIF_P,513nymous_ ++B 25000,36400,300,300,CONT_DIF_P,459nymous_ ++B 30600,30000,300,300,CONT_DIF_P,620nymous_ ++B 3200,13000,300,300,CONT_BODY_N,674nymous_ ++B 12400,27000,300,300,CONT_DIF_N,1159ymous_ ++B 33800,27000,300,300,CONT_DIF_P,728nymous_ ++B 35400,23000,300,300,CONT_DIF_P,782nymous_ ++B 36800,17000,300,300,CONT_VIA2,836nymous_ ++B 38200,27400,300,300,CONT_BODY_N,890nymous_ ++B 4400,11800,300,300,CONT_DIF_P,944nymous_ ++B 16400,12800,300,300,CONT_DIF_P,1266ymous_ ++B 15200,6000,300,300,CONT_VIA2,1212ymous_ ++B 6600,19200,300,300,CONT_BODY_P,998nymous_ ++B 7600,36000,300,300,CONT_DIF_N,1052ymous_ ++B 18800,22000,300,300,CONT_DIF_N,1320ymous_ ++B 23000,33400,300,300,CONT_BODY_N,406nymous_ ++B 28400,6000,300,300,CONT_BODY_P,567nymous_ ++B 9200,14800,300,300,CONT_DIF_P,1106ymous_ ++B 12400,28000,300,300,CONT_DIF_N,1160ymous_ ++B 27000,33600,300,300,CONT_DIF_P,514nymous_ ++B 25000,37600,300,300,CONT_BODY_N,460nymous_ ++B 30600,30000,300,300,CONT_VIA,621nymous_ ++B 3200,13000,300,300,CONT_VIA2,675nymous_ ++B 33800,27000,300,300,CONT_VIA,729nymous_ ++B 35400,24000,300,300,CONT_DIF_P,783nymous_ ++B 37000,22000,300,300,CONT_DIF_P,837nymous_ ++B 38200,28400,300,300,CONT_BODY_N,891nymous_ ++B 4400,12800,300,300,CONT_DIF_P,945nymous_ ++B 16400,16000,300,300,CONT_BODY_N,1267ymous_ ++B 15200,8000,300,300,CONT_DIF_N,1213ymous_ ++B 6800,37600,300,300,CONT_BODY_P,999nymous_ ++B 7600,36000,300,300,CONT_VIA,1053ymous_ ++B 18800,22200,300,300,CONT_VIA,1321ymous_ ++B 25000,19200,300,300,CONT_BODY_N,461nymous_ ++B 23000,34400,300,300,CONT_BODY_N,407nymous_ ++B 28400,8000,300,300,CONT_DIF_N,568nymous_ ++B 30600,31000,300,300,CONT_DIF_P,622nymous_ ++B 9200,16000,300,300,CONT_BODY_N,1107ymous_ ++B 12400,29000,300,300,CONT_DIF_N,1161ymous_ ++B 27000,35000,300,300,CONT_DIF_P,515nymous_ ++B 3200,14000,300,300,CONT_BODY_N,676nymous_ ++B 33800,27000,300,300,CONT_VIA2,730nymous_ ++B 35400,25000,300,300,CONT_DIF_P,784nymous_ ++B 37000,22000,300,300,CONT_VIA,838nymous_ ++B 38200,29400,300,300,CONT_BODY_N,892nymous_ ++B 4400,13800,300,300,CONT_DIF_P,946nymous_ ++EOF +diff --git a/alliance/src/cells/src/mpxlib/pot_mpx.vbe b/alliance/src/cells/src/mpxlib/pot_mpx.vbe +new file mode 100644 +index 0000000..fd1e07a +--- /dev/null ++++ b/alliance/src/cells/src/mpxlib/pot_mpx.vbe +@@ -0,0 +1,42 @@ ++ENTITY pot_mpx IS ++ GENERIC ( ++ CONSTANT area : NATURAL := 80000; ++ CONSTANT rup : NATURAL := 684404; ++ CONSTANT rdown : NATURAL := 24 ++ ); ++ PORT ( ++ i : in BIT; ++ b : in BIT; ++ pad : out MUX_BIT BUS; ++ ck : in BIT; ++ vdde : in BIT; ++ vddi : in BIT; ++ vsse : in BIT; ++ vssi : in BIT ++ ); ++END pot_mpx; ++ ++ARCHITECTURE behaviour_data_flow OF pot_mpx IS ++ SIGNAL b1 : BIT; ++ SIGNAL b2 : BIT; ++ SIGNAL b3 : BIT; ++ SIGNAL b4 : BIT; ++ SIGNAL b5 : BIT; ++ SIGNAL b6 : BIT; ++ ++BEGIN ++ b6 <= b5; ++ b5 <= b4; ++ b4 <= b3; ++ b3 <= b2; ++ b2 <= b1; ++ b1 <= b; ++ label0 : BLOCK (b6 = '1') ++ BEGIN ++ pad <= GUARDED i; ++ END BLOCK label0; ++ ++ ASSERT ((((vddi and vdde) and not (vssi)) and not (vsse)) = '1') ++ REPORT "power supply is missing on pot_mpx" ++ SEVERITY WARNING; ++END; +diff --git a/alliance/src/cells/src/mpxlib/pvdde_mpx.ap b/alliance/src/cells/src/mpxlib/pvdde_mpx.ap +new file mode 100644 +index 0000000..cc24326 +--- /dev/null ++++ b/alliance/src/cells/src/mpxlib/pvdde_mpx.ap +@@ -0,0 +1,90 @@ ++V ALLIANCE : 6 ++H pvdde_mpx,P,14/9/2014,100 ++A 0,0,40000,80000 ++I 0,40000,padreal_mpx,padreal,NOSYM ++S 31200,6000,32800,6000,12000,13onymous_,RIGHT,TALU2 ++S 7200,6000,8800,6000,12000,11onymous_,RIGHT,TALU2 ++S 50,6000,2800,6000,12000,10onymous_,RIGHT,TALU2 ++S 13200,6000,26800,6000,12000,12onymous_,RIGHT,TALU2 ++S 13200,6000,26800,6000,12000,17onymous_,RIGHT,TALU4 ++S 37200,6000,39950,6000,12000,14onymous_,RIGHT,TALU2 ++S 7200,6000,8800,6000,12000,16onymous_,RIGHT,TALU4 ++S 50,6000,2800,6000,12000,15onymous_,RIGHT,TALU4 ++S 31200,6000,32800,6000,12000,18onymous_,RIGHT,TALU4 ++S 37200,6000,39950,6000,12000,19onymous_,RIGHT,TALU4 ++S 23000,18100,23000,59900,4400,21onymous_,UP,ALU1 ++S 8000,200,8000,2000,2000,1nonymous_,UP,TALU3 ++S 1400,200,1400,2000,3000,0nonymous_,UP,TALU3 ++S 0,6000,40000,6000,12000,20onymous_,RIGHT,TALU6 ++S 20000,200,20000,2000,14000,2nonymous_,UP,TALU3 ++S 32000,200,32000,2000,2000,3nonymous_,UP,TALU3 ++S 50,17000,39950,17000,10000,blockagenet,RIGHT,TALU2 ++S 38600,200,38600,2000,3000,4nonymous_,UP,TALU3 ++S 1400,200,1400,12000,3000,5nonymous_,UP,TALU5 ++S 17000,18100,17000,59900,4400,22onymous_,UP,ALU1 ++S 20000,200,20000,12000,14000,7nonymous_,UP,TALU5 ++S 8000,200,8000,12000,2000,6nonymous_,UP,TALU5 ++S 38600,200,38600,12000,3000,9nonymous_,UP,TALU5 ++S 32000,200,32000,12000,2000,8nonymous_,UP,TALU5 ++S 700,13000,39300,13000,2400,vssi,RIGHT,CALU3 ++S 700,7000,39300,7000,2400,vssi,RIGHT,CALU3 ++S 5000,-300,5000,17300,2400,vssi,UP,CALU2 ++S 5000,-300,5000,2300,2400,vssi,UP,CALU3 ++S 5000,0,5000,2000,2400,vssi,UP,CALU5 ++S 5000,0,5000,2000,2400,vssi,UP,CALU4 ++S 29000,-300,29000,17300,2400,vssi,UP,CALU2 ++S 29000,-300,29000,2300,2400,vssi,UP,CALU3 ++S 29000,0,29000,2000,2400,vssi,UP,CALU5 ++S 29000,0,29000,2000,2400,vssi,UP,CALU4 ++S 700,19000,39300,19000,2400,vsse,RIGHT,CALU3 ++S 700,37000,39300,37000,2400,vsse,RIGHT,CALU3 ++S 700,31000,39300,31000,2400,vsse,RIGHT,CALU3 ++S 700,25000,39300,25000,2400,vsse,RIGHT,CALU3 ++S 11000,-300,11000,17300,2400,vddi,UP,CALU2 ++S 11000,-300,11000,2300,2400,vddi,UP,CALU3 ++S 11000,0,11000,2000,2400,vddi,UP,CALU5 ++S 11000,0,11000,2000,2400,vddi,UP,CALU4 ++S 700,16000,39300,16000,2400,vddi,RIGHT,CALU3 ++S 700,10000,39300,10000,2400,vddi,RIGHT,CALU3 ++S 35000,-300,35000,17300,2400,vddi,UP,CALU2 ++S 35000,-300,35000,2300,2400,vddi,UP,CALU3 ++S 35000,0,35000,2000,2400,vddi,UP,CALU5 ++S 35000,0,35000,2000,2400,vddi,UP,CALU4 ++S 20000,48100,20000,71900,24400,vdde,UP,CALU1 ++S 700,34000,39300,34000,2400,vdde,RIGHT,CALU3 ++S 700,28000,39300,28000,2400,vdde,RIGHT,CALU3 ++S 700,22000,39300,22000,2400,vdde,RIGHT,CALU3 ++S 700,4000,39300,4000,1000,ck,RIGHT,CALU3 ++B 11000,16000,2300,2300,CONT_VIA2,48onymous_ ++B 17000,34000,4300,2300,CONT_VIA,53onymous_ ++B 11000,1000,2300,2300,CONT_VIA3,46onymous_ ++B 17000,28000,4300,2300,CONT_VIA,51onymous_ ++B 35000,1000,2300,2300,CONT_VIA4,37onymous_ ++B 11000,1000,2300,2300,CONT_VIA4,47onymous_ ++B 17000,28000,4300,2300,CONT_VIA2,52onymous_ ++B 35000,1000,2300,2300,CONT_VIA2,35onymous_ ++B 35000,1000,2300,2300,CONT_VIA3,36onymous_ ++B 5000,1000,2300,2300,CONT_VIA2,40onymous_ ++B 17000,34000,4300,2300,CONT_VIA2,54onymous_ ++B 17000,22000,4300,2300,CONT_VIA,49onymous_ ++B 5000,7000,2300,2300,CONT_VIA2,39onymous_ ++B 5000,1000,2300,2300,CONT_VIA3,41onymous_ ++B 35000,16000,2300,2300,CONT_VIA2,38onymous_ ++B 5000,1000,2300,2300,CONT_VIA4,42onymous_ ++B 5000,13000,2300,2300,CONT_VIA2,43onymous_ ++B 17000,22000,4300,2300,CONT_VIA2,50onymous_ ++B 23000,28000,4300,2300,CONT_VIA,25onymous_ ++B 23000,22000,4300,2300,CONT_VIA,23onymous_ ++B 23000,22000,4300,2300,CONT_VIA2,24onymous_ ++B 23000,34000,4300,2300,CONT_VIA2,28onymous_ ++B 23000,34000,4300,2300,CONT_VIA,27onymous_ ++B 23000,28000,4300,2300,CONT_VIA2,26onymous_ ++B 29000,1000,2300,2300,CONT_VIA3,31onymous_ ++B 29000,1000,2300,2300,CONT_VIA2,30onymous_ ++B 29000,7000,2300,2300,CONT_VIA2,29onymous_ ++B 29000,13000,2300,2300,CONT_VIA2,33onymous_ ++B 11000,1000,2300,2300,CONT_VIA2,45onymous_ ++B 29000,1000,2300,2300,CONT_VIA4,32onymous_ ++B 11000,10000,2300,2300,CONT_VIA2,44onymous_ ++B 35000,10000,2300,2300,CONT_VIA2,34onymous_ ++EOF +diff --git a/alliance/src/cells/src/mpxlib/pvdde_mpx.vbe b/alliance/src/cells/src/mpxlib/pvdde_mpx.vbe +new file mode 100644 +index 0000000..43fa446 +--- /dev/null ++++ b/alliance/src/cells/src/mpxlib/pvdde_mpx.vbe +@@ -0,0 +1,20 @@ ++ENTITY pvdde_mpx IS ++ GENERIC ( ++ CONSTANT area : NATURAL := 80000 ++ ); ++ PORT ( ++ ck : in BIT; ++ vdde : in BIT; ++ vddi : in BIT; ++ vsse : in BIT; ++ vssi : in BIT ++ ); ++END pvdde_mpx; ++ ++ARCHITECTURE behaviour_data_flow OF pvdde_mpx IS ++ ++BEGIN ++ ASSERT ((((not (vssi) and not (vsse)) and vddi) and vdde) = '1') ++ REPORT "power supply is missing on pvdde_mpx" ++ SEVERITY WARNING; ++END; +diff --git a/alliance/src/cells/src/mpxlib/pvddeck_mpx.ap b/alliance/src/cells/src/mpxlib/pvddeck_mpx.ap +new file mode 100644 +index 0000000..a054f08 +--- /dev/null ++++ b/alliance/src/cells/src/mpxlib/pvddeck_mpx.ap +@@ -0,0 +1,344 @@ ++V ALLIANCE : 6 ++H pvddeck_mpx,P,14/9/2014,100 ++A 0,0,40000,80000 ++I 0,40000,padreal_mpx,padreal,NOSYM ++S 700,4000,39300,4000,1000,ck,RIGHT,CALU3 ++S 700,34000,39300,34000,2400,vdde,RIGHT,CALU3 ++S 700,28000,39300,28000,2400,vdde,RIGHT,CALU3 ++S 700,22000,39300,22000,2400,vdde,RIGHT,CALU3 ++S 20000,48100,20000,71900,24400,vdde,UP,CALU1 ++S 26100,15600,31900,15600,1600,vddi,RIGHT,ALU1 ++S 700,10000,39300,10000,2400,vddi,RIGHT,CALU3 ++S 700,16000,39300,16000,2400,vddi,RIGHT,CALU3 ++S 8100,15600,13900,15600,1600,vddi,RIGHT,ALU1 ++S 35000,0,35000,2000,2400,vddi,UP,CALU4 ++S 35000,0,35000,2000,2400,vddi,UP,CALU5 ++S 35000,-300,35000,2300,2400,vddi,UP,CALU3 ++S 35000,-300,35000,17300,2400,vddi,UP,CALU2 ++S 9000,0,9000,2000,2400,vddi,UP,CALU4 ++S 9000,0,9000,2000,2400,vddi,UP,CALU5 ++S 9000,-300,9000,2300,2400,vddi,UP,CALU3 ++S 9000,-300,9000,17300,2400,vddi,UP,CALU2 ++S 700,19000,39300,19000,2400,vsse,RIGHT,CALU3 ++S 700,37000,39300,37000,2400,vsse,RIGHT,CALU3 ++S 700,31000,39300,31000,2400,vsse,RIGHT,CALU3 ++S 700,25000,39300,25000,2400,vsse,RIGHT,CALU3 ++S 5000,-300,5000,17300,2400,vssi,UP,CALU2 ++S 700,7000,39300,7000,2400,vssi,RIGHT,CALU3 ++S 700,13000,39300,13000,2400,vssi,RIGHT,CALU3 ++S 8100,6800,13900,6800,1600,vssi,RIGHT,ALU1 ++S 26100,6800,31900,6800,1600,vssi,RIGHT,ALU1 ++S 31000,0,31000,2000,2400,vssi,UP,CALU5 ++S 31000,-300,31000,2300,2400,vssi,UP,CALU3 ++S 31000,-300,31000,17300,2400,vssi,UP,CALU2 ++S 31000,0,31000,2000,2400,vssi,UP,CALU4 ++S 5000,0,5000,2000,2400,vssi,UP,CALU4 ++S 5000,0,5000,2000,2400,vssi,UP,CALU5 ++S 5000,-300,5000,2300,2400,vssi,UP,CALU3 ++S 26600,11100,26600,15100,200,93onymous_,UP,PTRANS ++S 37200,6000,39950,6000,12000,11onymous_,RIGHT,TALU4 ++S 26600,10200,30200,10200,600,92onymous_,RIGHT,POLY ++S 11000,7500,11000,9500,200,53onymous_,UP,NTRANS ++S 26600,9800,26600,10800,200,91onymous_,UP,POLY ++S 33000,200,33000,2000,0,13onymous_,UP,TALU3 ++S 30800,12100,30800,14900,400,127nymous_,UP,ALU1 ++S 11600,7700,11600,9300,620,51onymous_,UP,NDIF ++S 11600,11300,11600,14900,620,52onymous_,UP,PDIF ++S 26000,12300,26000,14900,400,126nymous_,UP,ALU1 ++S 0,6000,40000,6000,12000,12onymous_,RIGHT,TALU6 ++S 11000,9800,11000,10800,200,54onymous_,UP,POLY ++S 38600,200,38600,2000,3000,17onymous_,UP,TALU3 ++S 7000,200,7000,2000,0,16onymous_,UP,TALU3 ++S 27200,700,27200,11500,400,130nymous_,UP,ALU2 ++S 10400,7700,10400,9300,420,56onymous_,UP,NDIF ++S 11000,11100,11000,15100,200,55onymous_,UP,PTRANS ++S 27200,7700,27200,9300,420,94onymous_,UP,NDIF ++S 14000,200,14000,2000,6000,15onymous_,UP,TALU3 ++S 10400,11300,10400,14900,620,58onymous_,UP,PDIF ++S 28400,700,28400,11500,400,129nymous_,UP,ALU2 ++S 25000,200,25000,2000,8000,14onymous_,UP,TALU3 ++S 10400,11300,10400,13900,400,57onymous_,UP,ALU1 ++S 28400,12300,28400,14900,400,128nymous_,UP,ALU1 ++S 1400,200,1400,2000,3000,18onymous_,UP,TALU3 ++S 9800,11100,9800,15100,200,61onymous_,UP,PTRANS ++S 9800,9800,9800,10800,200,60onymous_,UP,POLY ++S 23000,18100,23000,59900,4400,131nymous_,UP,ALU1 ++S 9800,7500,9800,9500,200,59onymous_,UP,NTRANS ++S 27300,9200,29500,9200,400,95onymous_,RIGHT,ALU1 ++S 9200,7700,9200,9300,420,62onymous_,UP,NDIF ++S 33000,200,33000,12000,0,19onymous_,UP,TALU5 ++S 17000,18100,17000,59900,4400,132nymous_,UP,ALU1 ++S 27300,10200,31900,10200,400,96onymous_,RIGHT,ALU1 ++S 27200,11300,27200,13900,400,97onymous_,UP,ALU1 ++S 8600,9800,8600,10800,200,65onymous_,UP,POLY ++S 14000,200,14000,12000,6000,21onymous_,UP,TALU5 ++S 8600,7500,8600,9500,200,64onymous_,UP,NTRANS ++S 27800,9800,27800,10800,200,101nymous_,UP,POLY ++S 25000,200,25000,12000,8000,20onymous_,UP,TALU5 ++S 9200,11300,9200,14900,620,63onymous_,UP,PDIF ++S 27200,11300,27200,14900,620,98onymous_,UP,PDIF ++S 27300,11200,29500,11200,400,99onymous_,RIGHT,ALU1 ++S 27800,7500,27800,9500,200,100nymous_,UP,NTRANS ++S 7000,200,7000,12000,0,22onymous_,UP,TALU5 ++S 28400,7700,28400,9300,620,103nymous_,UP,NDIF ++S 27800,11100,27800,15100,200,102nymous_,UP,PTRANS ++S 7000,10200,8600,10200,600,66onymous_,RIGHT,POLY ++S 38600,200,38600,12000,3000,23onymous_,UP,TALU5 ++S 8600,11100,8600,15100,200,67onymous_,UP,PTRANS ++S 1400,200,1400,12000,3000,24onymous_,UP,TALU5 ++S 11300,1000,28700,1000,400,25onymous_,RIGHT,ALU3 ++S 11300,2000,28700,2000,400,26onymous_,RIGHT,ALU3 ++S 11300,16200,14300,16200,400,27onymous_,RIGHT,ALU2 ++S 28400,11300,28400,14900,620,104nymous_,UP,PDIF ++S 14000,5900,14000,7700,400,28onymous_,UP,ALU2 ++S 29000,7500,29000,9500,200,105nymous_,UP,NTRANS ++S 8000,7700,8000,9300,620,68onymous_,UP,NDIF ++S 7880,6200,14120,6200,600,30onymous_,RIGHT,PTIE ++S 29000,9800,29000,10800,200,106nymous_,UP,POLY ++S 7000,3700,7000,10500,400,29onymous_,UP,ALU2 ++S 12800,8500,12800,9100,400,31onymous_,UP,ALU1 ++S 29000,11100,29000,15100,200,107nymous_,UP,PTRANS ++S 10400,8500,10400,9100,400,32onymous_,UP,ALU1 ++S 12800,11300,12800,13900,400,45onymous_,UP,ALU1 ++S 29600,7700,29600,9300,420,108nymous_,UP,NDIF ++S 8000,11300,8000,14900,620,69onymous_,UP,PDIF ++S 8100,10200,12700,10200,400,44onymous_,RIGHT,ALU1 ++S 9200,7500,9200,9100,400,70onymous_,UP,ALU1 ++S 29600,11300,29600,13900,400,109nymous_,UP,ALU1 ++S 8000,8500,8000,12700,400,33onymous_,UP,ALU1 ++S 29600,11300,29600,14900,620,110nymous_,UP,PDIF ++S 7880,16200,14120,16200,600,34onymous_,RIGHT,NTIE ++S 30200,11100,30200,15100,200,113nymous_,UP,PTRANS ++S 14000,7700,14000,9300,620,36onymous_,UP,NDIF ++S 30200,9800,30200,10800,200,112nymous_,UP,POLY ++S 7000,13800,15000,13800,6800,35onymous_,RIGHT,NWELL ++S 9300,7400,13900,7400,400,73onymous_,RIGHT,ALU1 ++S 12200,7500,12200,9500,200,48onymous_,UP,NTRANS ++S 30200,7500,30200,9500,200,111nymous_,UP,NTRANS ++S 11600,7500,11600,8100,400,72onymous_,UP,ALU1 ++S 14000,11300,14000,14900,620,37onymous_,UP,PDIF ++S 30800,7700,30800,9300,420,114nymous_,UP,NDIF ++S 12800,11300,12800,14900,620,46onymous_,UP,PDIF ++S 14000,7500,14000,8100,400,71onymous_,UP,ALU1 ++S 10500,11200,12700,11200,400,47onymous_,RIGHT,ALU1 ++S 14000,12300,14000,14900,400,74onymous_,UP,ALU1 ++S 12200,9800,12200,10800,200,49onymous_,UP,POLY ++S 13400,11100,13400,15100,200,41onymous_,UP,PTRANS ++S 30800,11300,30800,14900,620,115nymous_,UP,PDIF ++S 11600,12300,11600,14900,400,76onymous_,UP,ALU1 ++S 13400,7500,13400,9500,200,38onymous_,UP,NTRANS ++S 9200,12100,9200,14900,400,75onymous_,UP,ALU1 ++S 13400,9800,13400,10800,200,39onymous_,UP,POLY ++S 11600,700,11600,11500,400,77onymous_,UP,ALU2 ++S 9800,10200,13400,10200,600,40onymous_,RIGHT,POLY ++S 26000,5900,26000,7700,400,80onymous_,UP,ALU2 ++S 10500,9200,12700,9200,400,43onymous_,RIGHT,ALU1 ++S 12200,11100,12200,15100,200,50onymous_,UP,PTRANS ++S 12800,7700,12800,9300,420,42onymous_,UP,NDIF ++S 25700,16200,28700,16200,400,79onymous_,RIGHT,ALU2 ++S 31400,9800,31400,10800,200,117nymous_,UP,POLY ++S 33000,3700,33000,10500,400,81onymous_,UP,ALU2 ++S 31400,7500,31400,9500,200,116nymous_,UP,NTRANS ++S 12800,700,12800,11500,400,78onymous_,UP,ALU2 ++S 31400,10200,33000,10200,600,118nymous_,RIGHT,POLY ++S 29600,8500,29600,9100,400,84onymous_,UP,ALU1 ++S 25880,6200,32120,6200,600,82onymous_,RIGHT,PTIE ++S 50,6000,2800,6000,12000,0nonymous_,RIGHT,TALU2 ++S 27200,8500,27200,9100,400,83onymous_,UP,ALU1 ++S 11200,6000,16800,6000,12000,2nonymous_,RIGHT,TALU2 ++S 37200,6000,39950,6000,12000,5nonymous_,RIGHT,TALU2 ++S 31400,11100,31400,15100,200,119nymous_,UP,PTRANS ++S 25880,16200,32120,16200,600,86onymous_,RIGHT,NTIE ++S 32000,8500,32000,12700,400,85onymous_,UP,ALU1 ++S 21200,6000,28800,6000,12000,3nonymous_,RIGHT,TALU2 ++S 32000,11300,32000,14900,620,121nymous_,UP,PDIF ++S 26000,7700,26000,9300,620,88onymous_,UP,NDIF ++S 32000,7700,32000,9300,620,120nymous_,UP,NDIF ++S 25000,13800,33000,13800,6800,87onymous_,RIGHT,NWELL ++S 50,17000,39950,17000,10000,blockagenet,RIGHT,TALU2 ++S 26100,7400,30700,7400,400,125nymous_,RIGHT,ALU1 ++S 28400,7500,28400,8100,400,124nymous_,UP,ALU1 ++S 19000,0,19000,2000,2400,cko,UP,CALU5 ++S 19000,0,19000,2000,2400,cko,UP,CALU4 ++S 50,6000,2800,6000,12000,6nonymous_,RIGHT,TALU4 ++S 26000,11300,26000,14900,620,89onymous_,UP,PDIF ++S 30800,7500,30800,9100,400,122nymous_,UP,ALU1 ++S 11200,6000,16800,6000,12000,8nonymous_,RIGHT,TALU4 ++S 26600,7500,26600,9500,200,90onymous_,UP,NTRANS ++S 26000,7500,26000,8100,400,123nymous_,UP,ALU1 ++S 21200,6000,28800,6000,12000,9nonymous_,RIGHT,TALU4 ++B 35000,1000,2300,2300,CONT_VIA3,286nymous_ ++B 26000,7400,300,300,CONT_VIA,211nymous_ ++B 35000,1000,2300,2300,CONT_VIA2,285nymous_ ++B 26000,7400,300,300,CONT_VIA2,210nymous_ ++B 12800,11200,300,300,CONT_VIA,169nymous_ ++B 28400,13000,300,300,CONT_DIF_P,249nymous_ ++B 28400,12200,300,300,CONT_DIF_P,248nymous_ ++B 29600,8400,300,300,CONT_DIF_N,214nymous_ ++B 35000,16000,2300,2300,CONT_VIA2,288nymous_ ++B 11600,7400,300,300,CONT_DIF_N,173nymous_ ++B 33000,4000,300,300,CONT_VIA2,213nymous_ ++B 35000,1000,2300,2300,CONT_VIA4,287nymous_ ++B 12800,14000,300,300,CONT_DIF_P,172nymous_ ++B 26000,6200,300,300,CONT_VIA,212nymous_ ++B 12800,13000,300,300,CONT_DIF_P,171nymous_ ++B 12800,12000,300,300,CONT_DIF_P,170nymous_ ++B 28400,14000,300,300,CONT_DIF_P,250nymous_ ++B 5000,1000,2300,2300,CONT_VIA2,290nymous_ ++B 32000,8400,300,300,CONT_DIF_N,215nymous_ ++B 5000,7000,2300,2300,CONT_VIA2,289nymous_ ++B 11600,8200,300,300,CONT_DIF_N,174nymous_ ++B 14000,16200,300,300,CONT_VIA,133nymous_ ++B 11600,9200,300,300,CONT_VIA,175nymous_ ++B 27200,8400,300,300,CONT_DIF_N,216nymous_ ++B 11600,10200,300,300,CONT_POLY,176nymous_ ++B 5000,1000,2300,2300,CONT_VIA3,291nymous_ ++B 32000,6200,300,300,CONT_BODY_P,217nymous_ ++B 28400,15000,300,300,CONT_DIF_P,251nymous_ ++B 11600,11200,300,300,CONT_VIA,177nymous_ ++B 5000,1000,2300,2300,CONT_VIA4,292nymous_ ++B 29600,9200,300,300,CONT_DIF_N,252nymous_ ++B 5000,13000,2300,2300,CONT_VIA2,293nymous_ ++B 29600,10200,300,300,CONT_POLY,253nymous_ ++B 9000,10000,2300,2300,CONT_VIA2,294nymous_ ++B 11600,12200,300,300,CONT_DIF_P,178nymous_ ++B 29600,6200,300,300,CONT_BODY_P,219nymous_ ++B 11600,13000,300,300,CONT_DIF_P,179nymous_ ++B 28400,6200,300,300,CONT_BODY_P,220nymous_ ++B 29600,12000,300,300,CONT_DIF_P,254nymous_ ++B 11600,14000,300,300,CONT_DIF_P,180nymous_ ++B 30800,6200,300,300,CONT_BODY_P,218nymous_ ++B 12800,16200,300,300,CONT_VIA2,137nymous_ ++B 30800,8200,300,300,CONT_DIF_N,257nymous_ ++B 11600,16200,300,300,CONT_VIA2,136nymous_ ++B 29600,14000,300,300,CONT_DIF_P,256nymous_ ++B 11600,16200,300,300,CONT_VIA,135nymous_ ++B 12800,16200,300,300,CONT_VIA,134nymous_ ++B 9000,1000,2300,2300,CONT_VIA2,295nymous_ ++B 29600,13000,300,300,CONT_DIF_P,255nymous_ ++B 14000,7400,300,300,CONT_VIA2,140nymous_ ++B 14000,6200,300,300,CONT_VIA2,139nymous_ ++B 14000,16200,300,300,CONT_VIA2,138nymous_ ++B 17000,22000,4300,2300,CONT_VIA,299nymous_ ++B 30800,9200,300,300,CONT_DIF_N,258nymous_ ++B 9000,16000,2300,2300,CONT_VIA2,298nymous_ ++B 10400,10200,300,300,CONT_POLY,183nymous_ ++B 9000,1000,2300,2300,CONT_VIA4,297nymous_ ++B 10400,9200,300,300,CONT_DIF_N,182nymous_ ++B 26000,6200,300,300,CONT_BODY_P,222nymous_ ++B 9000,1000,2300,2300,CONT_VIA3,296nymous_ ++B 14000,7400,300,300,CONT_VIA,141nymous_ ++B 11600,15000,300,300,CONT_DIF_P,181nymous_ ++B 27200,6200,300,300,CONT_BODY_P,221nymous_ ++B 17000,28000,4300,2300,CONT_VIA,301nymous_ ++B 10400,14000,300,300,CONT_DIF_P,186nymous_ ++B 30800,13000,300,300,CONT_DIF_P,260nymous_ ++B 28400,16200,300,300,CONT_BODY_N,226nymous_ ++B 17000,22000,4300,2300,CONT_VIA2,300nymous_ ++B 8000,8400,300,300,CONT_DIF_N,145nymous_ ++B 10400,13000,300,300,CONT_DIF_P,185nymous_ ++B 30800,12000,300,300,CONT_DIF_P,259nymous_ ++B 29600,16200,300,300,CONT_BODY_N,225nymous_ ++B 10400,8400,300,300,CONT_DIF_N,144nymous_ ++B 10400,12000,300,300,CONT_DIF_P,184nymous_ ++B 32000,16200,300,300,CONT_BODY_N,224nymous_ ++B 7000,4000,300,300,CONT_VIA2,143nymous_ ++B 30800,16200,300,300,CONT_BODY_N,223nymous_ ++B 14000,6200,300,300,CONT_VIA,142nymous_ ++B 17000,34000,4300,2300,CONT_VIA,303nymous_ ++B 30800,15000,300,300,CONT_DIF_P,262nymous_ ++B 30800,14000,300,300,CONT_DIF_P,261nymous_ ++B 9200,8200,300,300,CONT_DIF_N,187nymous_ ++B 17000,28000,4300,2300,CONT_VIA2,302nymous_ ++B 8000,6200,300,300,CONT_BODY_P,147nymous_ ++B 27200,16200,300,300,CONT_BODY_N,227nymous_ ++B 12800,8400,300,300,CONT_DIF_N,146nymous_ ++B 19000,1000,2300,2300,CONT_VIA4,306nymous_ ++B 32000,12800,300,300,CONT_DIF_P,265nymous_ ++B 19000,1000,2300,2300,CONT_VIA3,305nymous_ ++B 9200,13000,300,300,CONT_DIF_P,190nymous_ ++B 32000,11800,300,300,CONT_DIF_P,264nymous_ ++B 17000,34000,4300,2300,CONT_VIA2,304nymous_ ++B 10400,6200,300,300,CONT_BODY_P,149nymous_ ++B 9200,12000,300,300,CONT_DIF_P,189nymous_ ++B 32000,9200,300,300,CONT_DIF_N,263nymous_ ++B 9200,6200,300,300,CONT_BODY_P,148nymous_ ++B 9200,9200,300,300,CONT_DIF_N,188nymous_ ++B 26000,16200,300,300,CONT_BODY_N,228nymous_ ++B 8000,11800,300,300,CONT_DIF_P,194nymous_ ++B 29600,11200,200,200,CONT_TURN1,229nymous_ ++B 26000,7400,300,300,CONT_DIF_N,230nymous_ ++B 11600,6200,300,300,CONT_BODY_P,150nymous_ ++B 9200,14000,300,300,CONT_DIF_P,191nymous_ ++B 12800,6200,300,300,CONT_BODY_P,151nymous_ ++B 33000,10200,300,300,CONT_POLY,266nymous_ ++B 9200,15000,300,300,CONT_DIF_P,192nymous_ ++B 8000,9200,300,300,CONT_DIF_N,193nymous_ ++B 30800,7400,300,300,CONT_DIF_N,268nymous_ ++B 28400,2000,300,300,CONT_VIA2,269nymous_ ++B 8000,12800,300,300,CONT_DIF_P,195nymous_ ++B 27200,2000,300,300,CONT_VIA2,270nymous_ ++B 7000,10200,300,300,CONT_POLY,196nymous_ ++B 7000,10200,300,300,CONT_VIA,197nymous_ ++B 26000,8200,300,300,CONT_DIF_N,231nymous_ ++B 26000,12200,300,300,CONT_DIF_P,232nymous_ ++B 14000,6200,300,300,CONT_BODY_P,152nymous_ ++B 26000,13000,300,300,CONT_DIF_P,233nymous_ ++B 33000,10200,300,300,CONT_VIA,267nymous_ ++B 26000,14000,300,300,CONT_DIF_P,234nymous_ ++B 8000,16200,300,300,CONT_BODY_N,154nymous_ ++B 26000,15000,300,300,CONT_DIF_P,235nymous_ ++B 10400,16200,300,300,CONT_BODY_N,155nymous_ ++B 27200,9200,300,300,CONT_DIF_N,236nymous_ ++B 11600,16200,300,300,CONT_BODY_N,156nymous_ ++B 27200,9200,300,300,CONT_VIA,237nymous_ ++B 28400,1000,300,300,CONT_VIA2,271nymous_ ++B 27200,10200,300,300,CONT_POLY,238nymous_ ++B 27200,1000,300,300,CONT_VIA2,272nymous_ ++B 9200,7400,300,300,CONT_DIF_N,198nymous_ ++B 23000,22000,4300,2300,CONT_VIA,273nymous_ ++B 11600,2000,300,300,CONT_VIA2,199nymous_ ++B 9200,16200,300,300,CONT_BODY_N,153nymous_ ++B 12800,2000,300,300,CONT_VIA2,200nymous_ ++B 11600,1000,300,300,CONT_VIA2,201nymous_ ++B 27200,13000,300,300,CONT_DIF_P,241nymous_ ++B 12800,1000,300,300,CONT_VIA2,202nymous_ ++B 12800,16200,300,300,CONT_BODY_N,157nymous_ ++B 14000,16200,300,300,CONT_BODY_N,158nymous_ ++B 27200,11200,300,300,CONT_VIA,239nymous_ ++B 10400,11200,200,200,CONT_TURN1,159nymous_ ++B 27200,12000,300,300,CONT_DIF_P,240nymous_ ++B 23000,22000,4300,2300,CONT_VIA2,274nymous_ ++B 23000,28000,4300,2300,CONT_VIA,275nymous_ ++B 14000,7400,300,300,CONT_DIF_N,160nymous_ ++B 27200,14000,300,300,CONT_DIF_P,242nymous_ ++B 14000,8200,300,300,CONT_DIF_N,161nymous_ ++B 23000,28000,4300,2300,CONT_VIA2,276nymous_ ++B 14000,12200,300,300,CONT_DIF_P,162nymous_ ++B 23000,34000,4300,2300,CONT_VIA,277nymous_ ++B 26000,16200,300,300,CONT_VIA,203nymous_ ++B 28400,7400,300,300,CONT_DIF_N,243nymous_ ++B 14000,13000,300,300,CONT_DIF_P,163nymous_ ++B 28400,8200,300,300,CONT_DIF_N,244nymous_ ++B 23000,34000,4300,2300,CONT_VIA2,278nymous_ ++B 27200,16200,300,300,CONT_VIA,204nymous_ ++B 14000,14000,300,300,CONT_DIF_P,164nymous_ ++B 28400,9200,300,300,CONT_VIA,245nymous_ ++B 31000,7000,2300,2300,CONT_VIA2,279nymous_ ++B 28400,16200,300,300,CONT_VIA,205nymous_ ++B 14000,15000,300,300,CONT_DIF_P,165nymous_ ++B 31000,1000,2300,2300,CONT_VIA2,280nymous_ ++B 28400,16200,300,300,CONT_VIA2,206nymous_ ++B 31000,1000,2300,2300,CONT_VIA3,281nymous_ ++B 27200,16200,300,300,CONT_VIA2,207nymous_ ++B 31000,1000,2300,2300,CONT_VIA4,282nymous_ ++B 12800,9200,300,300,CONT_VIA,167nymous_ ++B 26000,16200,300,300,CONT_VIA2,208nymous_ ++B 12800,10200,300,300,CONT_POLY,168nymous_ ++B 31000,13000,2300,2300,CONT_VIA2,283nymous_ ++B 26000,6200,300,300,CONT_VIA2,209nymous_ ++B 35000,10000,2300,2300,CONT_VIA2,284nymous_ ++B 28400,10200,300,300,CONT_POLY,246nymous_ ++B 12800,9200,300,300,CONT_DIF_N,166nymous_ ++B 28400,11200,300,300,CONT_VIA,247nymous_ ++EOF +diff --git a/alliance/src/cells/src/mpxlib/pvddeck_mpx.vbe b/alliance/src/cells/src/mpxlib/pvddeck_mpx.vbe +new file mode 100644 +index 0000000..ddffa40 +--- /dev/null ++++ b/alliance/src/cells/src/mpxlib/pvddeck_mpx.vbe +@@ -0,0 +1,31 @@ ++ENTITY pvddeck_mpx IS ++ GENERIC ( ++ CONSTANT area : NATURAL := 80000; ++ CONSTANT cin_ck : NATURAL := 127; ++ CONSTANT tpll_ck : NATURAL := 1055; ++ CONSTANT rdown_ck : NATURAL := 126; ++ CONSTANT tphh_ck : NATURAL := 963; ++ CONSTANT rup_ck : NATURAL := 183 ++ ); ++ PORT ( ++ cko : out WOR_BIT BUS; ++ ck : in BIT; ++ vdde : in BIT; ++ vddi : in BIT; ++ vsse : in BIT; ++ vssi : in BIT ++ ); ++END pvddeck_mpx; ++ ++ARCHITECTURE behaviour_data_flow OF pvddeck_mpx IS ++ ++BEGIN ++ label0 : BLOCK ('1' = '1') ++ BEGIN ++ cko <= GUARDED ck; ++ END BLOCK label0; ++ ++ ASSERT ((((not (vssi) and not (vsse)) and vddi) and vdde) = '1') ++ REPORT "power supply is missing on pvddeck_mpx" ++ SEVERITY WARNING; ++END; +diff --git a/alliance/src/cells/src/mpxlib/pvddi_mpx.ap b/alliance/src/cells/src/mpxlib/pvddi_mpx.ap +new file mode 100644 +index 0000000..8465dc2 +--- /dev/null ++++ b/alliance/src/cells/src/mpxlib/pvddi_mpx.ap +@@ -0,0 +1,86 @@ ++V ALLIANCE : 6 ++H pvddi_mpx,P,14/9/2014,100 ++A 0,0,40000,80000 ++I 0,40000,padreal_mpx,padreal,NOSYM ++S 31200,6000,32800,6000,12000,13onymous_,RIGHT,TALU2 ++S 7200,6000,8800,6000,12000,11onymous_,RIGHT,TALU2 ++S 50,6000,2800,6000,12000,10onymous_,RIGHT,TALU2 ++S 13200,6000,26800,6000,12000,12onymous_,RIGHT,TALU2 ++S 13200,6000,26800,6000,12000,17onymous_,RIGHT,TALU4 ++S 50,6000,2800,6000,12000,15onymous_,RIGHT,TALU4 ++S 37200,6000,39950,6000,12000,14onymous_,RIGHT,TALU2 ++S 7200,6000,8800,6000,12000,16onymous_,RIGHT,TALU4 ++S 31200,6000,32800,6000,12000,18onymous_,RIGHT,TALU4 ++S 37200,6000,39950,6000,12000,19onymous_,RIGHT,TALU4 ++S 17000,6100,17000,59900,4400,21onymous_,UP,ALU1 ++S 8000,200,8000,2000,2000,1nonymous_,UP,TALU3 ++S 1400,200,1400,2000,3000,0nonymous_,UP,TALU3 ++S 0,6000,40000,6000,12000,20onymous_,RIGHT,TALU6 ++S 20000,200,20000,2000,14000,2nonymous_,UP,TALU3 ++S 23000,6100,23000,59900,4400,22onymous_,UP,ALU1 ++S 32000,200,32000,2000,2000,3nonymous_,UP,TALU3 ++S 50,17000,39950,17000,10000,blockagenet,RIGHT,TALU2 ++S 38600,200,38600,2000,3000,4nonymous_,UP,TALU3 ++S 1400,200,1400,12000,3000,5nonymous_,UP,TALU5 ++S 20000,200,20000,12000,14000,7nonymous_,UP,TALU5 ++S 8000,200,8000,12000,2000,6nonymous_,UP,TALU5 ++S 32000,200,32000,12000,2000,8nonymous_,UP,TALU5 ++S 38600,200,38600,12000,3000,9nonymous_,UP,TALU5 ++S 29000,0,29000,2000,2400,vssi,UP,CALU4 ++S 29000,0,29000,2000,2400,vssi,UP,CALU5 ++S 29000,-300,29000,2300,2400,vssi,UP,CALU3 ++S 29000,-300,29000,17300,2400,vssi,UP,CALU2 ++S 5000,0,5000,2000,2400,vssi,UP,CALU4 ++S 5000,0,5000,2000,2400,vssi,UP,CALU5 ++S 5000,-300,5000,2300,2400,vssi,UP,CALU3 ++S 5000,-300,5000,17300,2400,vssi,UP,CALU2 ++S 700,7000,39300,7000,2400,vssi,RIGHT,CALU3 ++S 700,13000,39300,13000,2400,vssi,RIGHT,CALU3 ++S 700,25000,39300,25000,2400,vsse,RIGHT,CALU3 ++S 700,31000,39300,31000,2400,vsse,RIGHT,CALU3 ++S 700,37000,39300,37000,2400,vsse,RIGHT,CALU3 ++S 700,19000,39300,19000,2400,vsse,RIGHT,CALU3 ++S 11000,0,11000,2000,2400,vddi,UP,CALU5 ++S 11000,0,11000,2000,2400,vddi,UP,CALU4 ++S 700,16000,39300,16000,2400,vddi,RIGHT,CALU3 ++S 700,10000,39300,10000,2400,vddi,RIGHT,CALU3 ++S 35000,-300,35000,17300,2400,vddi,UP,CALU2 ++S 35000,-300,35000,2300,2400,vddi,UP,CALU3 ++S 35000,0,35000,2000,2400,vddi,UP,CALU5 ++S 35000,0,35000,2000,2400,vddi,UP,CALU4 ++S 20000,48100,20000,71900,24400,vddi,UP,CALU1 ++S 11000,-300,11000,17300,2400,vddi,UP,CALU2 ++S 11000,-300,11000,2300,2400,vddi,UP,CALU3 ++S 700,22000,39300,22000,2400,vdde,RIGHT,CALU3 ++S 700,28000,39300,28000,2400,vdde,RIGHT,CALU3 ++S 700,34000,39300,34000,2400,vdde,RIGHT,CALU3 ++S 700,4000,39300,4000,1000,ck,RIGHT,CALU3 ++B 29000,7000,2300,2300,CONT_VIA2,46onymous_ ++B 35000,16000,2300,2300,CONT_VIA2,37onymous_ ++B 23000,16000,4300,2300,CONT_VIA2,47onymous_ ++B 5000,1000,2300,2300,CONT_VIA2,35onymous_ ++B 5000,7000,2300,2300,CONT_VIA2,36onymous_ ++B 23000,16000,4300,2300,CONT_VIA,48onymous_ ++B 35000,1000,2300,2300,CONT_VIA4,38onymous_ ++B 35000,10000,2300,2300,CONT_VIA2,41onymous_ ++B 35000,1000,2300,2300,CONT_VIA2,40onymous_ ++B 23000,10000,4300,2300,CONT_VIA2,49onymous_ ++B 35000,1000,2300,2300,CONT_VIA3,39onymous_ ++B 29000,13000,2300,2300,CONT_VIA2,42onymous_ ++B 29000,1000,2300,2300,CONT_VIA4,43onymous_ ++B 23000,10000,4300,2300,CONT_VIA,50onymous_ ++B 17000,10000,4300,2300,CONT_VIA2,25onymous_ ++B 17000,16000,4300,2300,CONT_VIA2,23onymous_ ++B 17000,16000,4300,2300,CONT_VIA,24onymous_ ++B 11000,1000,2300,2300,CONT_VIA4,28onymous_ ++B 17000,10000,4300,2300,CONT_VIA,26onymous_ ++B 11000,16000,2300,2300,CONT_VIA2,27onymous_ ++B 11000,10000,2300,2300,CONT_VIA2,31onymous_ ++B 11000,1000,2300,2300,CONT_VIA2,30onymous_ ++B 11000,1000,2300,2300,CONT_VIA3,29onymous_ ++B 29000,1000,2300,2300,CONT_VIA2,45onymous_ ++B 5000,1000,2300,2300,CONT_VIA4,33onymous_ ++B 5000,13000,2300,2300,CONT_VIA2,32onymous_ ++B 29000,1000,2300,2300,CONT_VIA3,44onymous_ ++B 5000,1000,2300,2300,CONT_VIA3,34onymous_ ++EOF +diff --git a/alliance/src/cells/src/mpxlib/pvddi_mpx.vbe b/alliance/src/cells/src/mpxlib/pvddi_mpx.vbe +new file mode 100644 +index 0000000..cb25d33 +--- /dev/null ++++ b/alliance/src/cells/src/mpxlib/pvddi_mpx.vbe +@@ -0,0 +1,20 @@ ++ENTITY pvddi_mpx IS ++ GENERIC ( ++ CONSTANT area : NATURAL := 80000 ++ ); ++ PORT ( ++ ck : in BIT; ++ vdde : in BIT; ++ vddi : in BIT; ++ vsse : in BIT; ++ vssi : in BIT ++ ); ++END pvddi_mpx; ++ ++ARCHITECTURE behaviour_data_flow OF pvddi_mpx IS ++ ++BEGIN ++ ASSERT ((((vddi and vdde) and not (vssi)) and not (vsse)) = '1') ++ REPORT "power supply is missing on pvddi_mpx" ++ SEVERITY WARNING; ++END; +diff --git a/alliance/src/cells/src/mpxlib/pvddick_mpx.ap b/alliance/src/cells/src/mpxlib/pvddick_mpx.ap +new file mode 100644 +index 0000000..0b164e8 +--- /dev/null ++++ b/alliance/src/cells/src/mpxlib/pvddick_mpx.ap +@@ -0,0 +1,340 @@ ++V ALLIANCE : 6 ++H pvddick_mpx,P,14/9/2014,100 ++A 0,0,40000,80000 ++I 0,40000,padreal_mpx,padreal,NOSYM ++S 700,4000,39300,4000,1000,ck,RIGHT,CALU3 ++S 700,22000,39300,22000,2400,vdde,RIGHT,CALU3 ++S 700,28000,39300,28000,2400,vdde,RIGHT,CALU3 ++S 700,34000,39300,34000,2400,vdde,RIGHT,CALU3 ++S 26100,15600,31900,15600,1600,vddi,RIGHT,ALU1 ++S 9000,-300,9000,17300,2400,vddi,UP,CALU2 ++S 9000,-300,9000,2300,2400,vddi,UP,CALU3 ++S 700,10000,39300,10000,2400,vddi,RIGHT,CALU3 ++S 700,16000,39300,16000,2400,vddi,RIGHT,CALU3 ++S 9000,0,9000,2000,2400,vddi,UP,CALU5 ++S 9000,0,9000,2000,2400,vddi,UP,CALU4 ++S 35000,-300,35000,17300,2400,vddi,UP,CALU2 ++S 20000,48100,20000,71900,24400,vddi,UP,CALU1 ++S 8100,15600,13900,15600,1600,vddi,RIGHT,ALU1 ++S 35000,-300,35000,2300,2400,vddi,UP,CALU3 ++S 35000,0,35000,2000,2400,vddi,UP,CALU5 ++S 35000,0,35000,2000,2400,vddi,UP,CALU4 ++S 700,25000,39300,25000,2400,vsse,RIGHT,CALU3 ++S 700,31000,39300,31000,2400,vsse,RIGHT,CALU3 ++S 700,37000,39300,37000,2400,vsse,RIGHT,CALU3 ++S 700,19000,39300,19000,2400,vsse,RIGHT,CALU3 ++S 31000,0,31000,2000,2400,vssi,UP,CALU4 ++S 26100,6800,31900,6800,1600,vssi,RIGHT,ALU1 ++S 8100,6800,13900,6800,1600,vssi,RIGHT,ALU1 ++S 700,13000,39300,13000,2400,vssi,RIGHT,CALU3 ++S 700,7000,39300,7000,2400,vssi,RIGHT,CALU3 ++S 5000,-300,5000,17300,2400,vssi,UP,CALU2 ++S 5000,-300,5000,2300,2400,vssi,UP,CALU3 ++S 5000,0,5000,2000,2400,vssi,UP,CALU5 ++S 5000,0,5000,2000,2400,vssi,UP,CALU4 ++S 31000,-300,31000,17300,2400,vssi,UP,CALU2 ++S 31000,-300,31000,2300,2400,vssi,UP,CALU3 ++S 31000,0,31000,2000,2400,vssi,UP,CALU5 ++S 10500,9200,12700,9200,400,91onymous_,RIGHT,ALU1 ++S 25880,6200,32120,6200,600,52onymous_,RIGHT,PTIE ++S 27200,8500,27200,9100,400,51onymous_,UP,ALU1 ++S 32000,11300,32000,14900,620,13onymous_,UP,PDIF ++S 26000,7500,26000,8100,400,11onymous_,UP,ALU1 ++S 13400,11100,13400,15100,200,93onymous_,UP,PTRANS ++S 28400,7500,28400,8100,400,10onymous_,UP,ALU1 ++S 50,6000,2800,6000,12000,126nymous_,RIGHT,TALU4 ++S 30800,7500,30800,9100,400,12onymous_,UP,ALU1 ++S 37200,6000,39950,6000,12000,127nymous_,RIGHT,TALU2 ++S 33000,3700,33000,10500,400,53onymous_,UP,ALU2 ++S 12800,7700,12800,9300,420,92onymous_,UP,NDIF ++S 31400,11100,31400,15100,200,15onymous_,UP,PTRANS ++S 11200,6000,16800,6000,12000,130nymous_,RIGHT,TALU2 ++S 11600,12300,11600,14900,400,58onymous_,UP,ALU1 ++S 32000,7700,32000,9300,620,14onymous_,UP,NDIF ++S 21200,6000,28800,6000,12000,129nymous_,RIGHT,TALU2 ++S 11600,700,11600,11500,400,57onymous_,UP,ALU2 ++S 31400,9800,31400,10800,200,17onymous_,UP,POLY ++S 12800,700,12800,11500,400,56onymous_,UP,ALU2 ++S 9800,10200,13400,10200,600,94onymous_,RIGHT,POLY ++S 26000,5900,26000,7700,400,54onymous_,UP,ALU2 ++S 31400,10200,33000,10200,600,16onymous_,RIGHT,POLY ++S 25700,16200,28700,16200,400,55onymous_,RIGHT,ALU2 ++S 9200,12100,9200,14900,400,59onymous_,UP,ALU1 ++S 14000,11300,14000,14900,620,97onymous_,UP,PDIF ++S 13400,7500,13400,9500,200,96onymous_,UP,NTRANS ++S 9300,7400,13900,7400,400,61onymous_,RIGHT,ALU1 ++S 50,6000,2800,6000,12000,132nymous_,RIGHT,TALU2 ++S 14000,12300,14000,14900,400,60onymous_,UP,ALU1 ++S 31400,7500,31400,9500,200,18onymous_,UP,NTRANS ++S 11600,7500,11600,8100,400,62onymous_,UP,ALU1 ++S 13400,9800,13400,10800,200,95onymous_,UP,POLY ++S 30800,11300,30800,14900,620,19onymous_,UP,PDIF ++S 14000,7500,14000,8100,400,63onymous_,UP,ALU1 ++S 8000,8500,8000,12700,400,101nymous_,UP,ALU1 ++S 7000,13800,15000,13800,6800,99onymous_,RIGHT,NWELL ++S 7880,16200,14120,16200,600,100nymous_,RIGHT,NTIE ++S 30800,7700,30800,9300,420,20onymous_,UP,NDIF ++S 9200,7500,9200,9100,400,64onymous_,UP,ALU1 ++S 30200,11100,30200,15100,200,21onymous_,UP,PTRANS ++S 8000,11300,8000,14900,620,65onymous_,UP,PDIF ++S 14000,7700,14000,9300,620,98onymous_,UP,NDIF ++S 10400,8500,10400,9100,400,102nymous_,UP,ALU1 ++S 29600,11300,29600,13900,400,25onymous_,UP,ALU1 ++S 30200,7500,30200,9500,200,23onymous_,UP,NTRANS ++S 8600,11100,8600,15100,200,67onymous_,UP,PTRANS ++S 29600,11300,29600,14900,620,24onymous_,UP,PDIF ++S 12800,8500,12800,9100,400,103nymous_,UP,ALU1 ++S 30200,9800,30200,10800,200,22onymous_,UP,POLY ++S 8000,7700,8000,9300,620,66onymous_,UP,NDIF ++S 29600,7700,29600,9300,420,26onymous_,UP,NDIF ++S 29000,11100,29000,15100,200,27onymous_,UP,PTRANS ++S 7880,6200,14120,6200,600,104nymous_,RIGHT,PTIE ++S 29000,9800,29000,10800,200,28onymous_,UP,POLY ++S 7000,3700,7000,10500,400,105nymous_,UP,ALU2 ++S 28400,7700,28400,9300,620,31onymous_,UP,NDIF ++S 7000,10200,8600,10200,600,68onymous_,RIGHT,POLY ++S 14000,5900,14000,7700,400,106nymous_,UP,ALU2 ++S 29000,7500,29000,9500,200,29onymous_,UP,NTRANS ++S 28400,11300,28400,14900,620,30onymous_,UP,PDIF ++S 11300,16200,14300,16200,400,107nymous_,RIGHT,ALU2 ++S 7000,200,7000,12000,0,110nymous_,UP,TALU5 ++S 27800,7500,27800,9500,200,34onymous_,UP,NTRANS ++S 26000,11300,26000,14900,620,45onymous_,UP,PDIF ++S 38600,200,38600,12000,3000,109nymous_,UP,TALU5 ++S 27800,9800,27800,10800,200,33onymous_,UP,POLY ++S 8600,7500,8600,9500,200,70onymous_,UP,NTRANS ++S 1400,200,1400,12000,3000,108nymous_,UP,TALU5 ++S 8600,9800,8600,10800,200,69onymous_,UP,POLY ++S 27800,11100,27800,15100,200,32onymous_,UP,PTRANS ++S 26600,7500,26600,9500,200,44onymous_,UP,NTRANS ++S 14000,200,14000,12000,6000,111nymous_,UP,TALU5 ++S 25000,13800,33000,13800,6800,47onymous_,RIGHT,NWELL ++S 27300,11200,29500,11200,400,35onymous_,RIGHT,ALU1 ++S 9200,7700,9200,9300,420,72onymous_,UP,NDIF ++S 26000,7700,26000,9300,620,46onymous_,UP,NDIF ++S 9200,11300,9200,14900,620,71onymous_,UP,PDIF ++S 25880,16200,32120,16200,600,48onymous_,RIGHT,NTIE ++S 9800,11100,9800,15100,200,73onymous_,UP,PTRANS ++S 25000,200,25000,12000,8000,112nymous_,UP,TALU5 ++S 33000,200,33000,12000,0,113nymous_,UP,TALU5 ++S 27200,11300,27200,14900,620,36onymous_,UP,PDIF ++S 1400,200,1400,2000,3000,114nymous_,UP,TALU3 ++S 27200,11300,27200,13900,400,37onymous_,UP,ALU1 ++S 27200,7700,27200,9300,420,40onymous_,UP,NDIF ++S 27300,9200,29500,9200,400,39onymous_,RIGHT,ALU1 ++S 10400,11300,10400,13900,400,77onymous_,UP,ALU1 ++S 27300,10200,31900,10200,400,38onymous_,RIGHT,ALU1 ++S 38600,200,38600,2000,3000,115nymous_,UP,TALU3 ++S 9800,9800,9800,10800,200,74onymous_,UP,POLY ++S 26600,11100,26600,15100,200,41onymous_,UP,PTRANS ++S 32000,8500,32000,12700,400,49onymous_,UP,ALU1 ++S 9800,7500,9800,9500,200,75onymous_,UP,NTRANS ++S 10400,11300,10400,14900,620,76onymous_,UP,PDIF ++S 14000,200,14000,2000,6000,117nymous_,UP,TALU3 ++S 10400,7700,10400,9300,420,78onymous_,UP,NDIF ++S 7000,200,7000,2000,0,116nymous_,UP,TALU3 ++S 26600,10200,30200,10200,600,42onymous_,RIGHT,POLY ++S 11000,9800,11000,10800,200,80onymous_,UP,POLY ++S 11000,11100,11000,15100,200,79onymous_,UP,PTRANS ++S 11000,7500,11000,9500,200,81onymous_,UP,NTRANS ++S 26600,9800,26600,10800,200,43onymous_,UP,POLY ++S 29600,8500,29600,9100,400,50onymous_,UP,ALU1 ++S 12200,11100,12200,15100,200,84onymous_,UP,PTRANS ++S 11600,7700,11600,9300,620,83onymous_,UP,NDIF ++S 25000,200,25000,2000,8000,118nymous_,UP,TALU3 ++S 11300,1000,28700,1000,400,0nonymous_,RIGHT,ALU3 ++S 11300,2000,28700,2000,400,1nonymous_,RIGHT,ALU3 ++S 17000,6100,17000,59900,4400,2nonymous_,UP,ALU1 ++S 11600,11300,11600,14900,620,82onymous_,UP,PDIF ++S 12200,9800,12200,10800,200,85onymous_,UP,POLY ++S 23000,6100,23000,59900,4400,3nonymous_,UP,ALU1 ++S 10500,11200,12700,11200,400,87onymous_,RIGHT,ALU1 ++S 33000,200,33000,2000,0,119nymous_,UP,TALU3 ++S 27200,700,27200,11500,400,4nonymous_,UP,ALU2 ++S 12200,7500,12200,9500,200,86onymous_,UP,NTRANS ++S 50,17000,39950,17000,10000,blockagenet,RIGHT,TALU2 ++S 0,6000,40000,6000,12000,120nymous_,RIGHT,TALU6 ++S 28400,700,28400,11500,400,5nonymous_,UP,ALU2 ++S 12800,11300,12800,14900,620,88onymous_,UP,PDIF ++S 37200,6000,39950,6000,12000,121nymous_,RIGHT,TALU4 ++S 26100,7400,30700,7400,400,9nonymous_,RIGHT,ALU1 ++S 11200,6000,16800,6000,12000,124nymous_,RIGHT,TALU4 ++S 26000,12300,26000,14900,400,8nonymous_,UP,ALU1 ++S 21200,6000,28800,6000,12000,123nymous_,RIGHT,TALU4 ++S 8100,10200,12700,10200,400,90onymous_,RIGHT,ALU1 ++S 30800,12100,30800,14900,400,7nonymous_,UP,ALU1 ++S 19000,0,19000,2000,2400,cko,UP,CALU4 ++S 19000,0,19000,2000,2400,cko,UP,CALU5 ++S 28400,12300,28400,14900,400,6nonymous_,UP,ALU1 ++S 12800,11300,12800,13900,400,89onymous_,UP,ALU1 ++B 10400,6200,300,300,CONT_BODY_P,286nymous_ ++B 32000,16200,300,300,CONT_BODY_N,211nymous_ ++B 11600,6200,300,300,CONT_BODY_P,285nymous_ ++B 29600,16200,300,300,CONT_BODY_N,210nymous_ ++B 33000,10200,300,300,CONT_POLY,169nymous_ ++B 10400,14000,300,300,CONT_DIF_P,249nymous_ ++B 9200,8200,300,300,CONT_DIF_N,248nymous_ ++B 27200,6200,300,300,CONT_BODY_P,214nymous_ ++B 8000,6200,300,300,CONT_BODY_P,288nymous_ ++B 30800,15000,300,300,CONT_DIF_P,173nymous_ ++B 26000,6200,300,300,CONT_BODY_P,213nymous_ ++B 9200,6200,300,300,CONT_BODY_P,287nymous_ ++B 32000,9200,300,300,CONT_DIF_N,172nymous_ ++B 30800,16200,300,300,CONT_BODY_N,212nymous_ ++B 32000,11800,300,300,CONT_DIF_P,171nymous_ ++B 32000,12800,300,300,CONT_DIF_P,170nymous_ ++B 10400,13000,300,300,CONT_DIF_P,250nymous_ ++B 8000,8400,300,300,CONT_DIF_N,290nymous_ ++B 28400,6200,300,300,CONT_BODY_P,215nymous_ ++B 12800,8400,300,300,CONT_DIF_N,289nymous_ ++B 30800,14000,300,300,CONT_DIF_P,174nymous_ ++B 19000,1000,2300,2300,CONT_VIA4,133nymous_ ++B 30800,13000,300,300,CONT_DIF_P,175nymous_ ++B 29600,6200,300,300,CONT_BODY_P,216nymous_ ++B 30800,12000,300,300,CONT_DIF_P,176nymous_ ++B 10400,8400,300,300,CONT_DIF_N,291nymous_ ++B 30800,6200,300,300,CONT_BODY_P,217nymous_ ++B 10400,12000,300,300,CONT_DIF_P,251nymous_ ++B 30800,9200,300,300,CONT_DIF_N,177nymous_ ++B 7000,4000,300,300,CONT_VIA2,292nymous_ ++B 10400,10200,300,300,CONT_POLY,252nymous_ ++B 14000,6200,300,300,CONT_VIA,293nymous_ ++B 10400,9200,300,300,CONT_DIF_N,253nymous_ ++B 14000,7400,300,300,CONT_VIA,294nymous_ ++B 30800,8200,300,300,CONT_DIF_N,178nymous_ ++B 27200,8400,300,300,CONT_DIF_N,219nymous_ ++B 29600,14000,300,300,CONT_DIF_P,179nymous_ ++B 32000,8400,300,300,CONT_DIF_N,220nymous_ ++B 11600,15000,300,300,CONT_DIF_P,254nymous_ ++B 29600,13000,300,300,CONT_DIF_P,180nymous_ ++B 32000,6200,300,300,CONT_BODY_P,218nymous_ ++B 17000,10000,4300,2300,CONT_VIA2,137nymous_ ++B 11600,12200,300,300,CONT_DIF_P,257nymous_ ++B 17000,16000,4300,2300,CONT_VIA,136nymous_ ++B 11600,13000,300,300,CONT_DIF_P,256nymous_ ++B 17000,16000,4300,2300,CONT_VIA2,135nymous_ ++B 19000,1000,2300,2300,CONT_VIA3,134nymous_ ++B 14000,7400,300,300,CONT_VIA2,295nymous_ ++B 11600,14000,300,300,CONT_DIF_P,255nymous_ ++B 9000,1000,2300,2300,CONT_VIA4,140nymous_ ++B 9000,16000,2300,2300,CONT_VIA2,139nymous_ ++B 17000,10000,4300,2300,CONT_VIA,138nymous_ ++B 11600,16200,300,300,CONT_VIA2,299nymous_ ++B 11600,11200,300,300,CONT_VIA,258nymous_ ++B 12800,16200,300,300,CONT_VIA2,298nymous_ ++B 29600,9200,300,300,CONT_DIF_N,183nymous_ ++B 14000,16200,300,300,CONT_VIA2,297nymous_ ++B 29600,10200,300,300,CONT_POLY,182nymous_ ++B 33000,4000,300,300,CONT_VIA2,222nymous_ ++B 14000,6200,300,300,CONT_VIA2,296nymous_ ++B 9000,1000,2300,2300,CONT_VIA3,141nymous_ ++B 29600,12000,300,300,CONT_DIF_P,181nymous_ ++B 29600,8400,300,300,CONT_DIF_N,221nymous_ ++B 12800,16200,300,300,CONT_VIA,301nymous_ ++B 28400,13000,300,300,CONT_DIF_P,186nymous_ ++B 11600,9200,300,300,CONT_VIA,260nymous_ ++B 26000,6200,300,300,CONT_VIA2,226nymous_ ++B 11600,16200,300,300,CONT_VIA,300nymous_ ++B 5000,1000,2300,2300,CONT_VIA4,145nymous_ ++B 28400,14000,300,300,CONT_DIF_P,185nymous_ ++B 11600,10200,300,300,CONT_POLY,259nymous_ ++B 26000,7400,300,300,CONT_VIA2,225nymous_ ++B 5000,13000,2300,2300,CONT_VIA2,144nymous_ ++B 28400,15000,300,300,CONT_DIF_P,184nymous_ ++B 26000,7400,300,300,CONT_VIA,224nymous_ ++B 9000,10000,2300,2300,CONT_VIA2,143nymous_ ++B 26000,6200,300,300,CONT_VIA,223nymous_ ++B 9000,1000,2300,2300,CONT_VIA2,142nymous_ ++B 11600,7400,300,300,CONT_DIF_N,262nymous_ ++B 11600,8200,300,300,CONT_DIF_N,261nymous_ ++B 28400,12200,300,300,CONT_DIF_P,187nymous_ ++B 14000,16200,300,300,CONT_VIA,302nymous_ ++B 5000,1000,2300,2300,CONT_VIA2,147nymous_ ++B 26000,16200,300,300,CONT_VIA2,227nymous_ ++B 5000,1000,2300,2300,CONT_VIA3,146nymous_ ++B 12800,12000,300,300,CONT_DIF_P,265nymous_ ++B 28400,9200,300,300,CONT_VIA,190nymous_ ++B 12800,13000,300,300,CONT_DIF_P,264nymous_ ++B 35000,16000,2300,2300,CONT_VIA2,149nymous_ ++B 28400,10200,300,300,CONT_POLY,189nymous_ ++B 12800,14000,300,300,CONT_DIF_P,263nymous_ ++B 5000,7000,2300,2300,CONT_VIA2,148nymous_ ++B 28400,11200,300,300,CONT_VIA,188nymous_ ++B 27200,16200,300,300,CONT_VIA2,228nymous_ ++B 27200,13000,300,300,CONT_DIF_P,194nymous_ ++B 28400,16200,300,300,CONT_VIA2,229nymous_ ++B 28400,16200,300,300,CONT_VIA,230nymous_ ++B 35000,1000,2300,2300,CONT_VIA4,150nymous_ ++B 28400,8200,300,300,CONT_DIF_N,191nymous_ ++B 35000,1000,2300,2300,CONT_VIA3,151nymous_ ++B 12800,11200,300,300,CONT_VIA,266nymous_ ++B 28400,7400,300,300,CONT_DIF_N,192nymous_ ++B 27200,14000,300,300,CONT_DIF_P,193nymous_ ++B 12800,9200,300,300,CONT_VIA,268nymous_ ++B 12800,9200,300,300,CONT_DIF_N,269nymous_ ++B 27200,12000,300,300,CONT_DIF_P,195nymous_ ++B 14000,15000,300,300,CONT_DIF_P,270nymous_ ++B 27200,11200,300,300,CONT_VIA,196nymous_ ++B 27200,10200,300,300,CONT_POLY,197nymous_ ++B 27200,16200,300,300,CONT_VIA,231nymous_ ++B 26000,16200,300,300,CONT_VIA,232nymous_ ++B 35000,1000,2300,2300,CONT_VIA2,152nymous_ ++B 12800,1000,300,300,CONT_VIA2,233nymous_ ++B 12800,10200,300,300,CONT_POLY,267nymous_ ++B 11600,1000,300,300,CONT_VIA2,234nymous_ ++B 31000,13000,2300,2300,CONT_VIA2,154nymous_ ++B 12800,2000,300,300,CONT_VIA2,235nymous_ ++B 31000,1000,2300,2300,CONT_VIA4,155nymous_ ++B 11600,2000,300,300,CONT_VIA2,236nymous_ ++B 31000,1000,2300,2300,CONT_VIA3,156nymous_ ++B 9200,7400,300,300,CONT_DIF_N,237nymous_ ++B 14000,14000,300,300,CONT_DIF_P,271nymous_ ++B 7000,10200,300,300,CONT_VIA,238nymous_ ++B 14000,13000,300,300,CONT_DIF_P,272nymous_ ++B 27200,9200,300,300,CONT_VIA,198nymous_ ++B 14000,12200,300,300,CONT_DIF_P,273nymous_ ++B 27200,9200,300,300,CONT_DIF_N,199nymous_ ++B 35000,10000,2300,2300,CONT_VIA2,153nymous_ ++B 26000,15000,300,300,CONT_DIF_P,200nymous_ ++B 26000,14000,300,300,CONT_DIF_P,201nymous_ ++B 8000,11800,300,300,CONT_DIF_P,241nymous_ ++B 26000,13000,300,300,CONT_DIF_P,202nymous_ ++B 31000,1000,2300,2300,CONT_VIA2,157nymous_ ++B 31000,7000,2300,2300,CONT_VIA2,158nymous_ ++B 7000,10200,300,300,CONT_POLY,239nymous_ ++B 23000,16000,4300,2300,CONT_VIA2,159nymous_ ++B 8000,12800,300,300,CONT_DIF_P,240nymous_ ++B 14000,8200,300,300,CONT_DIF_N,274nymous_ ++B 14000,7400,300,300,CONT_DIF_N,275nymous_ ++B 23000,16000,4300,2300,CONT_VIA,160nymous_ ++B 8000,9200,300,300,CONT_DIF_N,242nymous_ ++B 23000,10000,4300,2300,CONT_VIA2,161nymous_ ++B 10400,11200,200,200,CONT_TURN1,276nymous_ ++B 23000,10000,4300,2300,CONT_VIA,162nymous_ ++B 14000,16200,300,300,CONT_BODY_N,277nymous_ ++B 26000,12200,300,300,CONT_DIF_P,203nymous_ ++B 9200,15000,300,300,CONT_DIF_P,243nymous_ ++B 27200,1000,300,300,CONT_VIA2,163nymous_ ++B 9200,14000,300,300,CONT_DIF_P,244nymous_ ++B 12800,16200,300,300,CONT_BODY_N,278nymous_ ++B 26000,8200,300,300,CONT_DIF_N,204nymous_ ++B 28400,1000,300,300,CONT_VIA2,164nymous_ ++B 9200,13000,300,300,CONT_DIF_P,245nymous_ ++B 11600,16200,300,300,CONT_BODY_N,279nymous_ ++B 26000,7400,300,300,CONT_DIF_N,205nymous_ ++B 27200,2000,300,300,CONT_VIA2,165nymous_ ++B 10400,16200,300,300,CONT_BODY_N,280nymous_ ++B 29600,11200,200,200,CONT_TURN1,206nymous_ ++B 8000,16200,300,300,CONT_BODY_N,281nymous_ ++B 26000,16200,300,300,CONT_BODY_N,207nymous_ ++B 9200,16200,300,300,CONT_BODY_N,282nymous_ ++B 30800,7400,300,300,CONT_DIF_N,167nymous_ ++B 27200,16200,300,300,CONT_BODY_N,208nymous_ ++B 33000,10200,300,300,CONT_VIA,168nymous_ ++B 14000,6200,300,300,CONT_BODY_P,283nymous_ ++B 28400,16200,300,300,CONT_BODY_N,209nymous_ ++B 12800,6200,300,300,CONT_BODY_P,284nymous_ ++B 9200,12000,300,300,CONT_DIF_P,246nymous_ ++B 28400,2000,300,300,CONT_VIA2,166nymous_ ++B 9200,9200,300,300,CONT_DIF_N,247nymous_ ++EOF +diff --git a/alliance/src/cells/src/mpxlib/pvddick_mpx.vbe b/alliance/src/cells/src/mpxlib/pvddick_mpx.vbe +new file mode 100644 +index 0000000..a195fbd +--- /dev/null ++++ b/alliance/src/cells/src/mpxlib/pvddick_mpx.vbe +@@ -0,0 +1,31 @@ ++ENTITY pvddick_mpx IS ++ GENERIC ( ++ CONSTANT area : NATURAL := 80000; ++ CONSTANT cin_ck : NATURAL := 127; ++ CONSTANT tpll_ck : NATURAL := 1235; ++ CONSTANT rdown_ck : NATURAL := 253; ++ CONSTANT tphh_ck : NATURAL := 1109; ++ CONSTANT rup_ck : NATURAL := 311 ++ ); ++ PORT ( ++ cko : out WOR_BIT BUS; ++ ck : in BIT; ++ vdde : in BIT; ++ vddi : in BIT; ++ vsse : in BIT; ++ vssi : in BIT ++ ); ++END pvddick_mpx; ++ ++ARCHITECTURE behaviour_data_flow OF pvddick_mpx IS ++ ++BEGIN ++ label0 : BLOCK ('1' = '1') ++ BEGIN ++ cko <= GUARDED ck; ++ END BLOCK label0; ++ ++ ASSERT ((((vddi and vdde) and not (vssi)) and not (vsse)) = '1') ++ REPORT "power supply is missing on pvddick_mpx" ++ SEVERITY WARNING; ++END; +diff --git a/alliance/src/cells/src/mpxlib/pvsse_mpx.ap b/alliance/src/cells/src/mpxlib/pvsse_mpx.ap +new file mode 100644 +index 0000000..54ce412 +--- /dev/null ++++ b/alliance/src/cells/src/mpxlib/pvsse_mpx.ap +@@ -0,0 +1,94 @@ ++V ALLIANCE : 6 ++H pvsse_mpx,P,14/9/2014,100 ++A 0,0,40000,80000 ++I 0,40000,padreal_mpx,padreal,NOSYM ++S 31200,6000,32800,6000,12000,13onymous_,RIGHT,TALU2 ++S 7200,6000,8800,6000,12000,11onymous_,RIGHT,TALU2 ++S 50,6000,2800,6000,12000,10onymous_,RIGHT,TALU2 ++S 13200,6000,26800,6000,12000,12onymous_,RIGHT,TALU2 ++S 37200,6000,39950,6000,12000,14onymous_,RIGHT,TALU2 ++S 7200,6000,8800,6000,12000,16onymous_,RIGHT,TALU4 ++S 50,6000,2800,6000,12000,15onymous_,RIGHT,TALU4 ++S 13200,6000,26800,6000,12000,17onymous_,RIGHT,TALU4 ++S 31200,6000,32800,6000,12000,18onymous_,RIGHT,TALU4 ++S 37200,6000,39950,6000,12000,19onymous_,RIGHT,TALU4 ++S 17000,18100,17000,59900,4400,21onymous_,UP,ALU1 ++S 8000,200,8000,2000,2000,1nonymous_,UP,TALU3 ++S 1400,200,1400,2000,3000,0nonymous_,UP,TALU3 ++S 0,6000,40000,6000,12000,20onymous_,RIGHT,TALU6 ++S 20000,200,20000,2000,14000,2nonymous_,UP,TALU3 ++S 1400,200,1400,12000,3000,5nonymous_,UP,TALU5 ++S 38600,200,38600,2000,3000,4nonymous_,UP,TALU3 ++S 23000,18100,23000,59900,4400,22onymous_,UP,ALU1 ++S 32000,200,32000,2000,2000,3nonymous_,UP,TALU3 ++S 50,17000,39950,17000,10000,blockagenet,RIGHT,TALU2 ++S 20000,200,20000,12000,14000,7nonymous_,UP,TALU5 ++S 8000,200,8000,12000,2000,6nonymous_,UP,TALU5 ++S 38600,200,38600,12000,3000,9nonymous_,UP,TALU5 ++S 32000,200,32000,12000,2000,8nonymous_,UP,TALU5 ++S 29000,0,29000,2000,2400,vssi,UP,CALU4 ++S 29000,0,29000,2000,2400,vssi,UP,CALU5 ++S 29000,-300,29000,2300,2400,vssi,UP,CALU3 ++S 29000,-300,29000,17300,2400,vssi,UP,CALU2 ++S 5000,0,5000,2000,2400,vssi,UP,CALU4 ++S 5000,0,5000,2000,2400,vssi,UP,CALU5 ++S 5000,-300,5000,2300,2400,vssi,UP,CALU3 ++S 5000,-300,5000,17300,2400,vssi,UP,CALU2 ++S 700,7000,39300,7000,2400,vssi,RIGHT,CALU3 ++S 700,13000,39300,13000,2400,vssi,RIGHT,CALU3 ++S 700,25000,39300,25000,2400,vsse,RIGHT,CALU3 ++S 700,31000,39300,31000,2400,vsse,RIGHT,CALU3 ++S 700,37000,39300,37000,2400,vsse,RIGHT,CALU3 ++S 700,19000,39300,19000,2400,vsse,RIGHT,CALU3 ++S 20000,48100,20000,71900,24400,vsse,UP,CALU1 ++S 35000,0,35000,2000,2400,vddi,UP,CALU4 ++S 35000,0,35000,2000,2400,vddi,UP,CALU5 ++S 35000,-300,35000,2300,2400,vddi,UP,CALU3 ++S 35000,-300,35000,17300,2400,vddi,UP,CALU2 ++S 700,10000,39300,10000,2400,vddi,RIGHT,CALU3 ++S 700,16000,39300,16000,2400,vddi,RIGHT,CALU3 ++S 11000,0,11000,2000,2400,vddi,UP,CALU4 ++S 11000,0,11000,2000,2400,vddi,UP,CALU5 ++S 11000,-300,11000,2300,2400,vddi,UP,CALU3 ++S 11000,-300,11000,17300,2400,vddi,UP,CALU2 ++S 700,22000,39300,22000,2400,vdde,RIGHT,CALU3 ++S 700,28000,39300,28000,2400,vdde,RIGHT,CALU3 ++S 700,34000,39300,34000,2400,vdde,RIGHT,CALU3 ++S 700,4000,39300,4000,1000,ck,RIGHT,CALU3 ++B 29000,1000,2300,2300,CONT_VIA3,48onymous_ ++B 23000,37000,4300,2300,CONT_VIA2,53onymous_ ++B 29000,13000,2300,2300,CONT_VIA2,46onymous_ ++B 23000,19000,4300,2300,CONT_VIA2,51onymous_ ++B 5000,1000,2300,2300,CONT_VIA4,37onymous_ ++B 29000,1000,2300,2300,CONT_VIA4,47onymous_ ++B 23000,19000,4300,2300,CONT_VIA,52onymous_ ++B 11000,10000,2300,2300,CONT_VIA2,35onymous_ ++B 5000,13000,2300,2300,CONT_VIA2,36onymous_ ++B 5000,7000,2300,2300,CONT_VIA2,40onymous_ ++B 23000,25000,4300,2300,CONT_VIA2,57onymous_ ++B 23000,37000,4300,2300,CONT_VIA,54onymous_ ++B 29000,1000,2300,2300,CONT_VIA2,49onymous_ ++B 5000,1000,2300,2300,CONT_VIA2,39onymous_ ++B 23000,31000,4300,2300,CONT_VIA,56onymous_ ++B 23000,25000,4300,2300,CONT_VIA,58onymous_ ++B 35000,16000,2300,2300,CONT_VIA2,41onymous_ ++B 5000,1000,2300,2300,CONT_VIA3,38onymous_ ++B 23000,31000,4300,2300,CONT_VIA2,55onymous_ ++B 35000,1000,2300,2300,CONT_VIA4,42onymous_ ++B 35000,1000,2300,2300,CONT_VIA3,43onymous_ ++B 29000,7000,2300,2300,CONT_VIA2,50onymous_ ++B 17000,19000,4300,2300,CONT_VIA,24onymous_ ++B 17000,19000,4300,2300,CONT_VIA2,23onymous_ ++B 17000,37000,4300,2300,CONT_VIA2,25onymous_ ++B 17000,31000,4300,2300,CONT_VIA,28onymous_ ++B 17000,31000,4300,2300,CONT_VIA2,27onymous_ ++B 17000,37000,4300,2300,CONT_VIA,26onymous_ ++B 11000,16000,2300,2300,CONT_VIA2,31onymous_ ++B 17000,25000,4300,2300,CONT_VIA,30onymous_ ++B 17000,25000,4300,2300,CONT_VIA2,29onymous_ ++B 11000,1000,2300,2300,CONT_VIA3,33onymous_ ++B 35000,10000,2300,2300,CONT_VIA2,45onymous_ ++B 11000,1000,2300,2300,CONT_VIA4,32onymous_ ++B 35000,1000,2300,2300,CONT_VIA2,44onymous_ ++B 11000,1000,2300,2300,CONT_VIA2,34onymous_ ++EOF +diff --git a/alliance/src/cells/src/mpxlib/pvsse_mpx.vbe b/alliance/src/cells/src/mpxlib/pvsse_mpx.vbe +new file mode 100644 +index 0000000..413e4b4 +--- /dev/null ++++ b/alliance/src/cells/src/mpxlib/pvsse_mpx.vbe +@@ -0,0 +1,20 @@ ++ENTITY pvsse_mpx IS ++ GENERIC ( ++ CONSTANT area : NATURAL := 80000 ++ ); ++ PORT ( ++ ck : in BIT; ++ vdde : in BIT; ++ vddi : in BIT; ++ vsse : in BIT; ++ vssi : in BIT ++ ); ++END pvsse_mpx; ++ ++ARCHITECTURE behaviour_data_flow OF pvsse_mpx IS ++ ++BEGIN ++ ASSERT ((((vddi and vdde) and not (vssi)) and not (vsse)) = '1') ++ REPORT "power supply is missing on pvsse_mpx" ++ SEVERITY WARNING; ++END; +diff --git a/alliance/src/cells/src/mpxlib/pvsseck_mpx.ap b/alliance/src/cells/src/mpxlib/pvsseck_mpx.ap +new file mode 100644 +index 0000000..76c42d5 +--- /dev/null ++++ b/alliance/src/cells/src/mpxlib/pvsseck_mpx.ap +@@ -0,0 +1,348 @@ ++V ALLIANCE : 6 ++H pvsseck_mpx,P,14/9/2014,100 ++A 0,0,40000,80000 ++I 0,40000,padreal_mpx,padreal,NOSYM ++S 700,4000,39300,4000,1000,ck,RIGHT,CALU3 ++S 700,34000,39300,34000,2400,vdde,RIGHT,CALU3 ++S 700,28000,39300,28000,2400,vdde,RIGHT,CALU3 ++S 700,22000,39300,22000,2400,vdde,RIGHT,CALU3 ++S 35000,-300,35000,17300,2400,vddi,UP,CALU2 ++S 9000,-300,9000,17300,2400,vddi,UP,CALU2 ++S 700,16000,39300,16000,2400,vddi,RIGHT,CALU3 ++S 8100,15600,13900,15600,1600,vddi,RIGHT,ALU1 ++S 35000,0,35000,2000,2400,vddi,UP,CALU4 ++S 35000,0,35000,2000,2400,vddi,UP,CALU5 ++S 35000,-300,35000,2300,2400,vddi,UP,CALU3 ++S 9000,0,9000,2000,2400,vddi,UP,CALU4 ++S 9000,0,9000,2000,2400,vddi,UP,CALU5 ++S 9000,-300,9000,2300,2400,vddi,UP,CALU3 ++S 700,10000,39300,10000,2400,vddi,RIGHT,CALU3 ++S 26100,15600,31900,15600,1600,vddi,RIGHT,ALU1 ++S 700,19000,39300,19000,2400,vsse,RIGHT,CALU3 ++S 700,37000,39300,37000,2400,vsse,RIGHT,CALU3 ++S 700,31000,39300,31000,2400,vsse,RIGHT,CALU3 ++S 700,25000,39300,25000,2400,vsse,RIGHT,CALU3 ++S 20000,48100,20000,71900,24400,vsse,UP,CALU1 ++S 5000,0,5000,2000,2400,vssi,UP,CALU5 ++S 700,7000,39300,7000,2400,vssi,RIGHT,CALU3 ++S 5000,-300,5000,2300,2400,vssi,UP,CALU3 ++S 700,13000,39300,13000,2400,vssi,RIGHT,CALU3 ++S 8100,6800,13900,6800,1600,vssi,RIGHT,ALU1 ++S 31000,0,31000,2000,2400,vssi,UP,CALU5 ++S 31000,-300,31000,2300,2400,vssi,UP,CALU3 ++S 31000,-300,31000,17300,2400,vssi,UP,CALU2 ++S 5000,-300,5000,17300,2400,vssi,UP,CALU2 ++S 26100,6800,31900,6800,1600,vssi,RIGHT,ALU1 ++S 31000,0,31000,2000,2400,vssi,UP,CALU4 ++S 5000,0,5000,2000,2400,vssi,UP,CALU4 ++S 31400,9800,31400,10800,200,92onymous_,UP,POLY ++S 12800,700,12800,11500,400,53onymous_,UP,ALU2 ++S 31400,7500,31400,9500,200,91onymous_,UP,NTRANS ++S 50,6000,2800,6000,12000,126nymous_,RIGHT,TALU4 ++S 14000,11300,14000,14900,620,12onymous_,UP,PDIF ++S 14000,7700,14000,9300,620,11onymous_,UP,NDIF ++S 13400,7500,13400,9500,200,13onymous_,UP,NTRANS ++S 11600,12300,11600,14900,400,51onymous_,UP,ALU1 ++S 37200,6000,39950,6000,12000,127nymous_,RIGHT,TALU2 ++S 11600,700,11600,11500,400,52onymous_,UP,ALU2 ++S 7000,13800,15000,13800,6800,10onymous_,RIGHT,NWELL ++S 31400,10200,33000,10200,600,93onymous_,RIGHT,POLY ++S 12800,7700,12800,9300,420,17onymous_,UP,NDIF ++S 25700,16200,28700,16200,400,54onymous_,RIGHT,ALU2 ++S 11200,6000,16800,6000,12000,130nymous_,RIGHT,TALU2 ++S 13400,11100,13400,15100,200,16onymous_,UP,PTRANS ++S 21200,6000,28800,6000,12000,129nymous_,RIGHT,TALU2 ++S 9800,10200,13400,10200,600,15onymous_,RIGHT,POLY ++S 13400,9800,13400,10800,200,14onymous_,UP,POLY ++S 27200,8500,27200,9100,400,58onymous_,UP,ALU1 ++S 25880,6200,32120,6200,600,57onymous_,RIGHT,PTIE ++S 31400,11100,31400,15100,200,94onymous_,UP,PTRANS ++S 26000,5900,26000,7700,400,55onymous_,UP,ALU2 ++S 33000,3700,33000,10500,400,56onymous_,UP,ALU2 ++S 25880,16200,32120,16200,600,61onymous_,RIGHT,NTIE ++S 32000,8500,32000,12700,400,60onymous_,UP,ALU1 ++S 29600,8500,29600,9100,400,59onymous_,UP,ALU1 ++S 8100,10200,12700,10200,400,19onymous_,RIGHT,ALU1 ++S 32000,7700,32000,9300,620,95onymous_,UP,NDIF ++S 25000,13800,33000,13800,6800,62onymous_,RIGHT,NWELL ++S 50,6000,2800,6000,12000,132nymous_,RIGHT,TALU2 ++S 10500,9200,12700,9200,400,18onymous_,RIGHT,ALU1 ++S 32000,11300,32000,14900,620,96onymous_,UP,PDIF ++S 30800,7500,30800,9100,400,97onymous_,UP,ALU1 ++S 26000,11300,26000,14900,620,64onymous_,UP,PDIF ++S 12800,11300,12800,13900,400,20onymous_,UP,ALU1 ++S 26000,7700,26000,9300,620,63onymous_,UP,NDIF ++S 26000,12300,26000,14900,400,101nymous_,UP,ALU1 ++S 12800,11300,12800,14900,620,21onymous_,UP,PDIF ++S 26600,7500,26600,9500,200,65onymous_,UP,NTRANS ++S 26000,7500,26000,8100,400,98onymous_,UP,ALU1 ++S 28400,7500,28400,8100,400,99onymous_,UP,ALU1 ++S 26100,7400,30700,7400,400,100nymous_,RIGHT,ALU1 ++S 28400,12300,28400,14900,400,103nymous_,UP,ALU1 ++S 30800,12100,30800,14900,400,102nymous_,UP,ALU1 ++S 12200,9800,12200,10800,200,24onymous_,UP,POLY ++S 12200,11100,12200,15100,200,25onymous_,UP,PTRANS ++S 10500,11200,12700,11200,400,22onymous_,RIGHT,ALU1 ++S 26600,9800,26600,10800,200,66onymous_,UP,POLY ++S 12200,7500,12200,9500,200,23onymous_,UP,NTRANS ++S 26600,10200,30200,10200,600,67onymous_,RIGHT,POLY ++S 11600,11300,11600,14900,620,27onymous_,UP,PDIF ++S 11600,7700,11600,9300,620,26onymous_,UP,NDIF ++S 28400,700,28400,11500,400,104nymous_,UP,ALU2 ++S 11000,7500,11000,9500,200,28onymous_,UP,NTRANS ++S 27200,700,27200,11500,400,105nymous_,UP,ALU2 ++S 11000,11100,11000,15100,200,30onymous_,UP,PTRANS ++S 23000,18100,23000,59900,4400,106nymous_,UP,ALU1 ++S 11000,9800,11000,10800,200,29onymous_,UP,POLY ++S 26600,11100,26600,15100,200,68onymous_,UP,PTRANS ++S 10400,7700,10400,9300,420,31onymous_,UP,NDIF ++S 17000,18100,17000,59900,4400,107nymous_,UP,ALU1 ++S 7000,200,7000,12000,0,110nymous_,UP,TALU5 ++S 38600,200,38600,12000,3000,109nymous_,UP,TALU5 ++S 10400,11300,10400,13900,400,32onymous_,UP,ALU1 ++S 9200,7500,9200,9100,400,45onymous_,UP,ALU1 ++S 27200,7700,27200,9300,420,69onymous_,UP,NDIF ++S 8000,11300,8000,14900,620,44onymous_,UP,PDIF ++S 1400,200,1400,12000,3000,108nymous_,UP,TALU5 ++S 27300,9200,29500,9200,400,70onymous_,RIGHT,ALU1 ++S 10400,11300,10400,14900,620,33onymous_,UP,PDIF ++S 9800,7500,9800,9500,200,34onymous_,UP,NTRANS ++S 14000,200,14000,12000,6000,111nymous_,UP,TALU5 ++S 9800,11100,9800,15100,200,36onymous_,UP,PTRANS ++S 27200,11300,27200,14900,620,73onymous_,UP,PDIF ++S 9800,9800,9800,10800,200,35onymous_,UP,POLY ++S 9300,7400,13900,7400,400,48onymous_,RIGHT,ALU1 ++S 27200,11300,27200,13900,400,72onymous_,UP,ALU1 ++S 33000,200,33000,12000,0,113nymous_,UP,TALU5 ++S 9200,7700,9200,9300,420,37onymous_,UP,NDIF ++S 25000,200,25000,12000,8000,112nymous_,UP,TALU5 ++S 14000,7500,14000,8100,400,46onymous_,UP,ALU1 ++S 1400,200,1400,2000,3000,114nymous_,UP,TALU3 ++S 27300,10200,31900,10200,400,71onymous_,RIGHT,ALU1 ++S 11600,7500,11600,8100,400,47onymous_,UP,ALU1 ++S 27300,11200,29500,11200,400,74onymous_,RIGHT,ALU1 ++S 14000,12300,14000,14900,400,49onymous_,UP,ALU1 ++S 7000,10200,8600,10200,600,41onymous_,RIGHT,POLY ++S 27800,7500,27800,9500,200,75onymous_,UP,NTRANS ++S 9200,11300,9200,14900,620,38onymous_,UP,PDIF ++S 8600,7500,8600,9500,200,39onymous_,UP,NTRANS ++S 27800,9800,27800,10800,200,76onymous_,UP,POLY ++S 8600,9800,8600,10800,200,40onymous_,UP,POLY ++S 27800,11100,27800,15100,200,77onymous_,UP,PTRANS ++S 38600,200,38600,2000,3000,115nymous_,UP,TALU3 ++S 29000,7500,29000,9500,200,80onymous_,UP,NTRANS ++S 8000,7700,8000,9300,620,43onymous_,UP,NDIF ++S 9200,12100,9200,14900,400,50onymous_,UP,ALU1 ++S 14000,200,14000,2000,6000,117nymous_,UP,TALU3 ++S 28400,11300,28400,14900,620,79onymous_,UP,PDIF ++S 8600,11100,8600,15100,200,42onymous_,UP,PTRANS ++S 7000,200,7000,2000,0,116nymous_,UP,TALU3 ++S 28400,7700,28400,9300,620,78onymous_,UP,NDIF ++S 29000,9800,29000,10800,200,81onymous_,UP,POLY ++S 29000,11100,29000,15100,200,82onymous_,UP,PTRANS ++S 25000,200,25000,2000,8000,118nymous_,UP,TALU3 ++S 11300,1000,28700,1000,400,0nonymous_,RIGHT,ALU3 ++S 11300,2000,28700,2000,400,1nonymous_,RIGHT,ALU3 ++S 29600,7700,29600,9300,420,83onymous_,UP,NDIF ++S 11300,16200,14300,16200,400,2nonymous_,RIGHT,ALU2 ++S 29600,11300,29600,13900,400,84onymous_,UP,ALU1 ++S 7000,3700,7000,10500,400,4nonymous_,UP,ALU2 ++S 30200,7500,30200,9500,200,86onymous_,UP,NTRANS ++S 14000,5900,14000,7700,400,3nonymous_,UP,ALU2 ++S 29600,11300,29600,14900,620,85onymous_,UP,PDIF ++S 50,17000,39950,17000,10000,blockagenet,RIGHT,TALU2 ++S 33000,200,33000,2000,0,119nymous_,UP,TALU3 ++S 30200,11100,30200,15100,200,88onymous_,UP,PTRANS ++S 7880,6200,14120,6200,600,5nonymous_,RIGHT,PTIE ++S 30200,9800,30200,10800,200,87onymous_,UP,POLY ++S 0,6000,40000,6000,12000,120nymous_,RIGHT,TALU6 ++S 37200,6000,39950,6000,12000,121nymous_,RIGHT,TALU4 ++S 11200,6000,16800,6000,12000,124nymous_,RIGHT,TALU4 ++S 21200,6000,28800,6000,12000,123nymous_,RIGHT,TALU4 ++S 7880,16200,14120,16200,600,9nonymous_,RIGHT,NTIE ++S 8000,8500,8000,12700,400,8nonymous_,UP,ALU1 ++S 19000,0,19000,2000,2400,cko,UP,CALU5 ++S 19000,0,19000,2000,2400,cko,UP,CALU4 ++S 12800,8500,12800,9100,400,6nonymous_,UP,ALU1 ++S 30800,7700,30800,9300,420,89onymous_,UP,NDIF ++S 10400,8500,10400,9100,400,7nonymous_,UP,ALU1 ++S 30800,11300,30800,14900,620,90onymous_,UP,PDIF ++B 35000,10000,2300,2300,CONT_VIA2,286nymous_ ++B 26000,7400,300,300,CONT_VIA,211nymous_ ++B 31000,13000,2300,2300,CONT_VIA2,285nymous_ ++B 26000,7400,300,300,CONT_VIA2,210nymous_ ++B 12800,11200,300,300,CONT_VIA,169nymous_ ++B 28400,13000,300,300,CONT_DIF_P,249nymous_ ++B 28400,12200,300,300,CONT_DIF_P,248nymous_ ++B 29600,8400,300,300,CONT_DIF_N,214nymous_ ++B 35000,1000,2300,2300,CONT_VIA3,288nymous_ ++B 11600,7400,300,300,CONT_DIF_N,173nymous_ ++B 33000,4000,300,300,CONT_VIA2,213nymous_ ++B 35000,1000,2300,2300,CONT_VIA2,287nymous_ ++B 12800,14000,300,300,CONT_DIF_P,172nymous_ ++B 26000,6200,300,300,CONT_VIA,212nymous_ ++B 12800,13000,300,300,CONT_DIF_P,171nymous_ ++B 12800,12000,300,300,CONT_DIF_P,170nymous_ ++B 28400,14000,300,300,CONT_DIF_P,250nymous_ ++B 35000,16000,2300,2300,CONT_VIA2,290nymous_ ++B 32000,8400,300,300,CONT_DIF_N,215nymous_ ++B 35000,1000,2300,2300,CONT_VIA4,289nymous_ ++B 11600,8200,300,300,CONT_DIF_N,174nymous_ ++B 14000,16200,300,300,CONT_VIA,133nymous_ ++B 11600,9200,300,300,CONT_VIA,175nymous_ ++B 27200,8400,300,300,CONT_DIF_N,216nymous_ ++B 11600,10200,300,300,CONT_POLY,176nymous_ ++B 5000,7000,2300,2300,CONT_VIA2,291nymous_ ++B 32000,6200,300,300,CONT_BODY_P,217nymous_ ++B 28400,15000,300,300,CONT_DIF_P,251nymous_ ++B 11600,11200,300,300,CONT_VIA,177nymous_ ++B 5000,1000,2300,2300,CONT_VIA2,292nymous_ ++B 29600,9200,300,300,CONT_DIF_N,252nymous_ ++B 5000,1000,2300,2300,CONT_VIA3,293nymous_ ++B 29600,10200,300,300,CONT_POLY,253nymous_ ++B 5000,1000,2300,2300,CONT_VIA4,294nymous_ ++B 11600,12200,300,300,CONT_DIF_P,178nymous_ ++B 29600,6200,300,300,CONT_BODY_P,219nymous_ ++B 11600,13000,300,300,CONT_DIF_P,179nymous_ ++B 28400,6200,300,300,CONT_BODY_P,220nymous_ ++B 29600,12000,300,300,CONT_DIF_P,254nymous_ ++B 11600,14000,300,300,CONT_DIF_P,180nymous_ ++B 30800,6200,300,300,CONT_BODY_P,218nymous_ ++B 12800,16200,300,300,CONT_VIA2,137nymous_ ++B 30800,8200,300,300,CONT_DIF_N,257nymous_ ++B 11600,16200,300,300,CONT_VIA2,136nymous_ ++B 29600,14000,300,300,CONT_DIF_P,256nymous_ ++B 11600,16200,300,300,CONT_VIA,135nymous_ ++B 12800,16200,300,300,CONT_VIA,134nymous_ ++B 5000,13000,2300,2300,CONT_VIA2,295nymous_ ++B 29600,13000,300,300,CONT_DIF_P,255nymous_ ++B 14000,7400,300,300,CONT_VIA2,140nymous_ ++B 14000,6200,300,300,CONT_VIA2,139nymous_ ++B 14000,16200,300,300,CONT_VIA2,138nymous_ ++B 9000,1000,2300,2300,CONT_VIA4,299nymous_ ++B 30800,9200,300,300,CONT_DIF_N,258nymous_ ++B 9000,1000,2300,2300,CONT_VIA3,298nymous_ ++B 10400,10200,300,300,CONT_POLY,183nymous_ ++B 9000,1000,2300,2300,CONT_VIA2,297nymous_ ++B 10400,9200,300,300,CONT_DIF_N,182nymous_ ++B 26000,6200,300,300,CONT_BODY_P,222nymous_ ++B 9000,10000,2300,2300,CONT_VIA2,296nymous_ ++B 14000,7400,300,300,CONT_VIA,141nymous_ ++B 11600,15000,300,300,CONT_DIF_P,181nymous_ ++B 27200,6200,300,300,CONT_BODY_P,221nymous_ ++B 17000,25000,4300,2300,CONT_VIA,301nymous_ ++B 10400,14000,300,300,CONT_DIF_P,186nymous_ ++B 30800,13000,300,300,CONT_DIF_P,260nymous_ ++B 28400,16200,300,300,CONT_BODY_N,226nymous_ ++B 9000,16000,2300,2300,CONT_VIA2,300nymous_ ++B 8000,8400,300,300,CONT_DIF_N,145nymous_ ++B 10400,13000,300,300,CONT_DIF_P,185nymous_ ++B 30800,12000,300,300,CONT_DIF_P,259nymous_ ++B 29600,16200,300,300,CONT_BODY_N,225nymous_ ++B 10400,8400,300,300,CONT_DIF_N,144nymous_ ++B 10400,12000,300,300,CONT_DIF_P,184nymous_ ++B 32000,16200,300,300,CONT_BODY_N,224nymous_ ++B 7000,4000,300,300,CONT_VIA2,143nymous_ ++B 30800,16200,300,300,CONT_BODY_N,223nymous_ ++B 14000,6200,300,300,CONT_VIA,142nymous_ ++B 17000,31000,4300,2300,CONT_VIA,303nymous_ ++B 30800,15000,300,300,CONT_DIF_P,262nymous_ ++B 30800,14000,300,300,CONT_DIF_P,261nymous_ ++B 9200,8200,300,300,CONT_DIF_N,187nymous_ ++B 17000,25000,4300,2300,CONT_VIA2,302nymous_ ++B 8000,6200,300,300,CONT_BODY_P,147nymous_ ++B 27200,16200,300,300,CONT_BODY_N,227nymous_ ++B 12800,8400,300,300,CONT_DIF_N,146nymous_ ++B 17000,19000,4300,2300,CONT_VIA,307nymous_ ++B 17000,37000,4300,2300,CONT_VIA2,306nymous_ ++B 32000,12800,300,300,CONT_DIF_P,265nymous_ ++B 17000,37000,4300,2300,CONT_VIA,305nymous_ ++B 9200,13000,300,300,CONT_DIF_P,190nymous_ ++B 32000,11800,300,300,CONT_DIF_P,264nymous_ ++B 17000,31000,4300,2300,CONT_VIA2,304nymous_ ++B 10400,6200,300,300,CONT_BODY_P,149nymous_ ++B 9200,12000,300,300,CONT_DIF_P,189nymous_ ++B 32000,9200,300,300,CONT_DIF_N,263nymous_ ++B 9200,6200,300,300,CONT_BODY_P,148nymous_ ++B 9200,9200,300,300,CONT_DIF_N,188nymous_ ++B 26000,16200,300,300,CONT_BODY_N,228nymous_ ++B 8000,11800,300,300,CONT_DIF_P,194nymous_ ++B 19000,1000,2300,2300,CONT_VIA3,309nymous_ ++B 19000,1000,2300,2300,CONT_VIA4,310nymous_ ++B 29600,11200,200,200,CONT_TURN1,229nymous_ ++B 26000,7400,300,300,CONT_DIF_N,230nymous_ ++B 11600,6200,300,300,CONT_BODY_P,150nymous_ ++B 9200,14000,300,300,CONT_DIF_P,191nymous_ ++B 12800,6200,300,300,CONT_BODY_P,151nymous_ ++B 33000,10200,300,300,CONT_POLY,266nymous_ ++B 9200,15000,300,300,CONT_DIF_P,192nymous_ ++B 8000,9200,300,300,CONT_DIF_N,193nymous_ ++B 17000,19000,4300,2300,CONT_VIA2,308nymous_ ++B 30800,7400,300,300,CONT_DIF_N,268nymous_ ++B 28400,2000,300,300,CONT_VIA2,269nymous_ ++B 8000,12800,300,300,CONT_DIF_P,195nymous_ ++B 27200,2000,300,300,CONT_VIA2,270nymous_ ++B 7000,10200,300,300,CONT_POLY,196nymous_ ++B 7000,10200,300,300,CONT_VIA,197nymous_ ++B 26000,8200,300,300,CONT_DIF_N,231nymous_ ++B 26000,12200,300,300,CONT_DIF_P,232nymous_ ++B 14000,6200,300,300,CONT_BODY_P,152nymous_ ++B 26000,13000,300,300,CONT_DIF_P,233nymous_ ++B 33000,10200,300,300,CONT_VIA,267nymous_ ++B 26000,14000,300,300,CONT_DIF_P,234nymous_ ++B 8000,16200,300,300,CONT_BODY_N,154nymous_ ++B 26000,15000,300,300,CONT_DIF_P,235nymous_ ++B 10400,16200,300,300,CONT_BODY_N,155nymous_ ++B 27200,9200,300,300,CONT_DIF_N,236nymous_ ++B 11600,16200,300,300,CONT_BODY_N,156nymous_ ++B 27200,9200,300,300,CONT_VIA,237nymous_ ++B 28400,1000,300,300,CONT_VIA2,271nymous_ ++B 27200,10200,300,300,CONT_POLY,238nymous_ ++B 27200,1000,300,300,CONT_VIA2,272nymous_ ++B 9200,7400,300,300,CONT_DIF_N,198nymous_ ++B 23000,25000,4300,2300,CONT_VIA,273nymous_ ++B 11600,2000,300,300,CONT_VIA2,199nymous_ ++B 9200,16200,300,300,CONT_BODY_N,153nymous_ ++B 12800,2000,300,300,CONT_VIA2,200nymous_ ++B 11600,1000,300,300,CONT_VIA2,201nymous_ ++B 27200,13000,300,300,CONT_DIF_P,241nymous_ ++B 12800,1000,300,300,CONT_VIA2,202nymous_ ++B 12800,16200,300,300,CONT_BODY_N,157nymous_ ++B 14000,16200,300,300,CONT_BODY_N,158nymous_ ++B 27200,11200,300,300,CONT_VIA,239nymous_ ++B 10400,11200,200,200,CONT_TURN1,159nymous_ ++B 27200,12000,300,300,CONT_DIF_P,240nymous_ ++B 23000,25000,4300,2300,CONT_VIA2,274nymous_ ++B 23000,31000,4300,2300,CONT_VIA,275nymous_ ++B 14000,7400,300,300,CONT_DIF_N,160nymous_ ++B 27200,14000,300,300,CONT_DIF_P,242nymous_ ++B 14000,8200,300,300,CONT_DIF_N,161nymous_ ++B 23000,31000,4300,2300,CONT_VIA2,276nymous_ ++B 14000,12200,300,300,CONT_DIF_P,162nymous_ ++B 23000,37000,4300,2300,CONT_VIA,277nymous_ ++B 26000,16200,300,300,CONT_VIA,203nymous_ ++B 28400,7400,300,300,CONT_DIF_N,243nymous_ ++B 14000,13000,300,300,CONT_DIF_P,163nymous_ ++B 28400,8200,300,300,CONT_DIF_N,244nymous_ ++B 23000,37000,4300,2300,CONT_VIA2,278nymous_ ++B 27200,16200,300,300,CONT_VIA,204nymous_ ++B 14000,14000,300,300,CONT_DIF_P,164nymous_ ++B 28400,9200,300,300,CONT_VIA,245nymous_ ++B 23000,19000,4300,2300,CONT_VIA,279nymous_ ++B 28400,16200,300,300,CONT_VIA,205nymous_ ++B 14000,15000,300,300,CONT_DIF_P,165nymous_ ++B 23000,19000,4300,2300,CONT_VIA2,280nymous_ ++B 28400,16200,300,300,CONT_VIA2,206nymous_ ++B 31000,7000,2300,2300,CONT_VIA2,281nymous_ ++B 27200,16200,300,300,CONT_VIA2,207nymous_ ++B 31000,1000,2300,2300,CONT_VIA2,282nymous_ ++B 12800,9200,300,300,CONT_VIA,167nymous_ ++B 26000,16200,300,300,CONT_VIA2,208nymous_ ++B 12800,10200,300,300,CONT_POLY,168nymous_ ++B 31000,1000,2300,2300,CONT_VIA3,283nymous_ ++B 26000,6200,300,300,CONT_VIA2,209nymous_ ++B 31000,1000,2300,2300,CONT_VIA4,284nymous_ ++B 28400,10200,300,300,CONT_POLY,246nymous_ ++B 12800,9200,300,300,CONT_DIF_N,166nymous_ ++B 28400,11200,300,300,CONT_VIA,247nymous_ ++EOF +diff --git a/alliance/src/cells/src/mpxlib/pvsseck_mpx.vbe b/alliance/src/cells/src/mpxlib/pvsseck_mpx.vbe +new file mode 100644 +index 0000000..3ef6010 +--- /dev/null ++++ b/alliance/src/cells/src/mpxlib/pvsseck_mpx.vbe +@@ -0,0 +1,31 @@ ++ENTITY pvsseck_mpx IS ++ GENERIC ( ++ CONSTANT area : NATURAL := 80000; ++ CONSTANT cin_ck : NATURAL := 127; ++ CONSTANT tpll_ck : NATURAL := 1055; ++ CONSTANT rdown_ck : NATURAL := 126; ++ CONSTANT tphh_ck : NATURAL := 963; ++ CONSTANT rup_ck : NATURAL := 183 ++ ); ++ PORT ( ++ cko : out WOR_BIT BUS; ++ ck : in BIT; ++ vdde : in BIT; ++ vddi : in BIT; ++ vsse : in BIT; ++ vssi : in BIT ++ ); ++END pvsseck_mpx; ++ ++ARCHITECTURE behaviour_data_flow OF pvsseck_mpx IS ++ ++BEGIN ++ label0 : BLOCK ('1' = '1') ++ BEGIN ++ cko <= GUARDED ck; ++ END BLOCK label0; ++ ++ ASSERT ((((vddi and vdde) and not (vssi)) and not (vsse)) = '1') ++ REPORT "power supply is missing on pvsseck_mpx" ++ SEVERITY WARNING; ++END; +diff --git a/alliance/src/cells/src/mpxlib/pvssi_mpx.ap b/alliance/src/cells/src/mpxlib/pvssi_mpx.ap +new file mode 100644 +index 0000000..1073dd8 +--- /dev/null ++++ b/alliance/src/cells/src/mpxlib/pvssi_mpx.ap +@@ -0,0 +1,86 @@ ++V ALLIANCE : 6 ++H pvssi_mpx,P,14/9/2014,100 ++A 0,0,40000,80000 ++I 0,40000,padreal_mpx,padreal,NOSYM ++S 31200,6000,32800,6000,12000,13onymous_,RIGHT,TALU2 ++S 7200,6000,8800,6000,12000,11onymous_,RIGHT,TALU2 ++S 50,6000,2800,6000,12000,10onymous_,RIGHT,TALU2 ++S 13200,6000,26800,6000,12000,12onymous_,RIGHT,TALU2 ++S 13200,6000,26800,6000,12000,17onymous_,RIGHT,TALU4 ++S 50,6000,2800,6000,12000,15onymous_,RIGHT,TALU4 ++S 37200,6000,39950,6000,12000,14onymous_,RIGHT,TALU2 ++S 7200,6000,8800,6000,12000,16onymous_,RIGHT,TALU4 ++S 31200,6000,32800,6000,12000,18onymous_,RIGHT,TALU4 ++S 37200,6000,39950,6000,12000,19onymous_,RIGHT,TALU4 ++S 17000,6100,17000,59900,4400,21onymous_,UP,ALU1 ++S 8000,200,8000,2000,2000,1nonymous_,UP,TALU3 ++S 1400,200,1400,2000,3000,0nonymous_,UP,TALU3 ++S 0,6000,40000,6000,12000,20onymous_,RIGHT,TALU6 ++S 20000,200,20000,2000,14000,2nonymous_,UP,TALU3 ++S 23000,6100,23000,59900,4400,22onymous_,UP,ALU1 ++S 32000,200,32000,2000,2000,3nonymous_,UP,TALU3 ++S 50,17000,39950,17000,10000,blockagenet,RIGHT,TALU2 ++S 38600,200,38600,2000,3000,4nonymous_,UP,TALU3 ++S 1400,200,1400,12000,3000,5nonymous_,UP,TALU5 ++S 20000,200,20000,12000,14000,7nonymous_,UP,TALU5 ++S 8000,200,8000,12000,2000,6nonymous_,UP,TALU5 ++S 32000,200,32000,12000,2000,8nonymous_,UP,TALU5 ++S 38600,200,38600,12000,3000,9nonymous_,UP,TALU5 ++S 700,7000,39300,7000,2400,vssi,RIGHT,CALU3 ++S 20000,48100,20000,71900,24400,vssi,UP,CALU1 ++S 700,13000,39300,13000,2400,vssi,RIGHT,CALU3 ++S 5000,-300,5000,17300,2400,vssi,UP,CALU2 ++S 5000,-300,5000,2300,2400,vssi,UP,CALU3 ++S 5000,0,5000,2000,2400,vssi,UP,CALU5 ++S 5000,0,5000,2000,2400,vssi,UP,CALU4 ++S 29000,-300,29000,17300,2400,vssi,UP,CALU2 ++S 29000,-300,29000,2300,2400,vssi,UP,CALU3 ++S 29000,0,29000,2000,2400,vssi,UP,CALU5 ++S 29000,0,29000,2000,2400,vssi,UP,CALU4 ++S 700,25000,39300,25000,2400,vsse,RIGHT,CALU3 ++S 700,31000,39300,31000,2400,vsse,RIGHT,CALU3 ++S 700,37000,39300,37000,2400,vsse,RIGHT,CALU3 ++S 700,19000,39300,19000,2400,vsse,RIGHT,CALU3 ++S 35000,0,35000,2000,2400,vddi,UP,CALU4 ++S 35000,0,35000,2000,2400,vddi,UP,CALU5 ++S 35000,-300,35000,2300,2400,vddi,UP,CALU3 ++S 35000,-300,35000,17300,2400,vddi,UP,CALU2 ++S 700,10000,39300,10000,2400,vddi,RIGHT,CALU3 ++S 700,16000,39300,16000,2400,vddi,RIGHT,CALU3 ++S 11000,0,11000,2000,2400,vddi,UP,CALU4 ++S 11000,0,11000,2000,2400,vddi,UP,CALU5 ++S 11000,-300,11000,2300,2400,vddi,UP,CALU3 ++S 11000,-300,11000,17300,2400,vddi,UP,CALU2 ++S 700,22000,39300,22000,2400,vdde,RIGHT,CALU3 ++S 700,28000,39300,28000,2400,vdde,RIGHT,CALU3 ++S 700,34000,39300,34000,2400,vdde,RIGHT,CALU3 ++S 700,4000,39300,4000,1000,ck,RIGHT,CALU3 ++B 29000,7000,2300,2300,CONT_VIA2,46onymous_ ++B 35000,16000,2300,2300,CONT_VIA2,37onymous_ ++B 23000,13000,4300,2300,CONT_VIA2,47onymous_ ++B 5000,1000,2300,2300,CONT_VIA2,35onymous_ ++B 5000,7000,2300,2300,CONT_VIA2,36onymous_ ++B 23000,13000,4300,2300,CONT_VIA,48onymous_ ++B 35000,1000,2300,2300,CONT_VIA4,38onymous_ ++B 35000,10000,2300,2300,CONT_VIA2,41onymous_ ++B 35000,1000,2300,2300,CONT_VIA2,40onymous_ ++B 23000,7000,4300,2300,CONT_VIA2,49onymous_ ++B 35000,1000,2300,2300,CONT_VIA3,39onymous_ ++B 29000,13000,2300,2300,CONT_VIA2,42onymous_ ++B 29000,1000,2300,2300,CONT_VIA4,43onymous_ ++B 23000,7000,4300,2300,CONT_VIA,50onymous_ ++B 17000,7000,4300,2300,CONT_VIA2,25onymous_ ++B 17000,13000,4300,2300,CONT_VIA2,23onymous_ ++B 17000,13000,4300,2300,CONT_VIA,24onymous_ ++B 11000,1000,2300,2300,CONT_VIA4,28onymous_ ++B 17000,7000,4300,2300,CONT_VIA,26onymous_ ++B 11000,16000,2300,2300,CONT_VIA2,27onymous_ ++B 11000,10000,2300,2300,CONT_VIA2,31onymous_ ++B 11000,1000,2300,2300,CONT_VIA2,30onymous_ ++B 11000,1000,2300,2300,CONT_VIA3,29onymous_ ++B 29000,1000,2300,2300,CONT_VIA2,45onymous_ ++B 5000,1000,2300,2300,CONT_VIA4,33onymous_ ++B 5000,13000,2300,2300,CONT_VIA2,32onymous_ ++B 29000,1000,2300,2300,CONT_VIA3,44onymous_ ++B 5000,1000,2300,2300,CONT_VIA3,34onymous_ ++EOF +diff --git a/alliance/src/cells/src/mpxlib/pvssi_mpx.vbe b/alliance/src/cells/src/mpxlib/pvssi_mpx.vbe +new file mode 100644 +index 0000000..a2d978a +--- /dev/null ++++ b/alliance/src/cells/src/mpxlib/pvssi_mpx.vbe +@@ -0,0 +1,20 @@ ++ENTITY pvssi_mpx IS ++ GENERIC ( ++ CONSTANT area : NATURAL := 80000 ++ ); ++ PORT ( ++ ck : in BIT; ++ vdde : in BIT; ++ vddi : in BIT; ++ vsse : in BIT; ++ vssi : in BIT ++ ); ++END pvssi_mpx; ++ ++ARCHITECTURE behaviour_data_flow OF pvssi_mpx IS ++ ++BEGIN ++ ASSERT ((((vddi and vdde) and not (vssi)) and not (vsse)) = '1') ++ REPORT "power supply is missing on pvssi_mpx" ++ SEVERITY WARNING; ++END; +diff --git a/alliance/src/cells/src/mpxlib/pvssick_mpx.ap b/alliance/src/cells/src/mpxlib/pvssick_mpx.ap +new file mode 100644 +index 0000000..5f10aff +--- /dev/null ++++ b/alliance/src/cells/src/mpxlib/pvssick_mpx.ap +@@ -0,0 +1,337 @@ ++V ALLIANCE : 6 ++H pvssick_mpx,P,14/9/2014,100 ++A 0,0,40000,80000 ++I 0,40000,padreal_mpx,padreal,NOSYM ++S 700,4000,39300,4000,1000,ck,RIGHT,CALU3 ++S 700,22000,39300,22000,2400,vdde,RIGHT,CALU3 ++S 700,28000,39300,28000,2400,vdde,RIGHT,CALU3 ++S 700,34000,39300,34000,2400,vdde,RIGHT,CALU3 ++S 35000,-300,35000,2300,2400,vddi,UP,CALU3 ++S 35000,0,35000,2000,2400,vddi,UP,CALU5 ++S 8100,15600,13900,15600,1600,vddi,RIGHT,ALU1 ++S 9000,-300,9000,17300,2400,vddi,UP,CALU2 ++S 700,16000,39300,16000,2400,vddi,RIGHT,CALU3 ++S 700,10000,39300,10000,2400,vddi,RIGHT,CALU3 ++S 35000,-300,35000,17300,2400,vddi,UP,CALU2 ++S 35000,0,35000,2000,2400,vddi,UP,CALU4 ++S 26100,15600,31900,15600,1600,vddi,RIGHT,ALU1 ++S 9000,-300,9000,2300,2400,vddi,UP,CALU3 ++S 9000,0,9000,2000,2400,vddi,UP,CALU4 ++S 9000,0,9000,2000,2400,vddi,UP,CALU5 ++S 700,25000,39300,25000,2400,vsse,RIGHT,CALU3 ++S 700,31000,39300,31000,2400,vsse,RIGHT,CALU3 ++S 700,37000,39300,37000,2400,vsse,RIGHT,CALU3 ++S 700,19000,39300,19000,2400,vsse,RIGHT,CALU3 ++S 5000,-300,5000,17300,2400,vssi,UP,CALU2 ++S 700,7000,39300,7000,2400,vssi,RIGHT,CALU3 ++S 8100,6800,13900,6800,1600,vssi,RIGHT,ALU1 ++S 700,13000,39300,13000,2400,vssi,RIGHT,CALU3 ++S 5000,-300,5000,2300,2400,vssi,UP,CALU3 ++S 5000,0,5000,2000,2400,vssi,UP,CALU5 ++S 26100,6800,31900,6800,1600,vssi,RIGHT,ALU1 ++S 20000,48100,20000,71900,24400,vssi,UP,CALU1 ++S 5000,0,5000,2000,2400,vssi,UP,CALU4 ++S 31000,0,31000,2000,2400,vssi,UP,CALU5 ++S 31000,0,31000,2000,2400,vssi,UP,CALU4 ++S 31000,-300,31000,17300,2400,vssi,UP,CALU2 ++S 31000,-300,31000,2300,2400,vssi,UP,CALU3 ++S 26000,12300,26000,14900,400,10onymous_,UP,ALU1 ++S 12800,7700,12800,9300,420,92onymous_,UP,NDIF ++S 27200,8500,27200,9100,400,53onymous_,UP,ALU1 ++S 10500,9200,12700,9200,400,91onymous_,RIGHT,ALU1 ++S 26000,7500,26000,8100,400,13onymous_,UP,ALU1 ++S 50,6000,2800,6000,12000,126nymous_,RIGHT,TALU4 ++S 28400,7500,28400,8100,400,12onymous_,UP,ALU1 ++S 32000,8500,32000,12700,400,51onymous_,UP,ALU1 ++S 37200,6000,39950,6000,12000,127nymous_,RIGHT,TALU2 ++S 29600,8500,29600,9100,400,52onymous_,UP,ALU1 ++S 13400,11100,13400,15100,200,93onymous_,UP,PTRANS ++S 26100,7400,30700,7400,400,11onymous_,RIGHT,ALU1 ++S 33000,3700,33000,10500,400,55onymous_,UP,ALU2 ++S 31400,11100,31400,15100,200,17onymous_,UP,PTRANS ++S 11200,6000,16800,6000,12000,130nymous_,RIGHT,TALU2 ++S 25880,6200,32120,6200,600,54onymous_,RIGHT,PTIE ++S 32000,7700,32000,9300,620,16onymous_,UP,NDIF ++S 21200,6000,28800,6000,12000,129nymous_,RIGHT,TALU2 ++S 32000,11300,32000,14900,620,15onymous_,UP,PDIF ++S 11600,12300,11600,14900,400,58onymous_,UP,ALU1 ++S 30800,7500,30800,9100,400,14onymous_,UP,ALU1 ++S 11600,700,11600,11500,400,57onymous_,UP,ALU2 ++S 9800,10200,13400,10200,600,94onymous_,RIGHT,POLY ++S 12800,700,12800,11500,400,56onymous_,UP,ALU2 ++S 9300,7400,13900,7400,400,61onymous_,RIGHT,ALU1 ++S 14000,12300,14000,14900,400,60onymous_,UP,ALU1 ++S 9200,12100,9200,14900,400,59onymous_,UP,ALU1 ++S 13400,9800,13400,10800,200,95onymous_,UP,POLY ++S 31400,9800,31400,10800,200,19onymous_,UP,POLY ++S 50,6000,2800,6000,12000,132nymous_,RIGHT,TALU2 ++S 11600,7500,11600,8100,400,62onymous_,UP,ALU1 ++S 31400,10200,33000,10200,600,18onymous_,RIGHT,POLY ++S 13400,7500,13400,9500,200,96onymous_,UP,NTRANS ++S 14000,11300,14000,14900,620,97onymous_,UP,PDIF ++S 30800,11300,30800,14900,620,21onymous_,UP,PDIF ++S 9200,7500,9200,9100,400,64onymous_,UP,ALU1 ++S 31400,7500,31400,9500,200,20onymous_,UP,NTRANS ++S 14000,7500,14000,8100,400,63onymous_,UP,ALU1 ++S 8000,8500,8000,12700,400,101nymous_,UP,ALU1 ++S 8000,11300,8000,14900,620,65onymous_,UP,PDIF ++S 14000,7700,14000,9300,620,98onymous_,UP,NDIF ++S 7000,13800,15000,13800,6800,99onymous_,RIGHT,NWELL ++S 7880,16200,14120,16200,600,100nymous_,RIGHT,NTIE ++S 12800,8500,12800,9100,400,103nymous_,UP,ALU1 ++S 30200,7500,30200,9500,200,25onymous_,UP,NTRANS ++S 10400,8500,10400,9100,400,102nymous_,UP,ALU1 ++S 30800,7700,30800,9300,420,22onymous_,UP,NDIF ++S 8000,7700,8000,9300,620,66onymous_,UP,NDIF ++S 30200,11100,30200,15100,200,23onymous_,UP,PTRANS ++S 8600,11100,8600,15100,200,67onymous_,UP,PTRANS ++S 30200,9800,30200,10800,200,24onymous_,UP,POLY ++S 29600,7700,29600,9300,420,28onymous_,UP,NDIF ++S 29600,11300,29600,13900,400,27onymous_,UP,ALU1 ++S 29600,11300,29600,14900,620,26onymous_,UP,PDIF ++S 7880,6200,14120,6200,600,104nymous_,RIGHT,PTIE ++S 7000,3700,7000,10500,400,105nymous_,UP,ALU2 ++S 23000,6100,23000,59900,4400,107nymous_,UP,ALU1 ++S 29000,7500,29000,9500,200,31onymous_,UP,NTRANS ++S 7000,10200,8600,10200,600,68onymous_,RIGHT,POLY ++S 29000,11100,29000,15100,200,29onymous_,UP,PTRANS ++S 29000,9800,29000,10800,200,30onymous_,UP,POLY ++S 17000,6100,17000,59900,4400,106nymous_,UP,ALU1 ++S 7000,200,7000,12000,0,110nymous_,UP,TALU5 ++S 38600,200,38600,12000,3000,109nymous_,UP,TALU5 ++S 1400,200,1400,12000,3000,108nymous_,UP,TALU5 ++S 8600,9800,8600,10800,200,69onymous_,UP,POLY ++S 28400,11300,28400,14900,620,32onymous_,UP,PDIF ++S 26600,9800,26600,10800,200,45onymous_,UP,POLY ++S 26600,10200,30200,10200,600,44onymous_,RIGHT,POLY ++S 28400,7700,28400,9300,620,33onymous_,UP,NDIF ++S 8600,7500,8600,9500,200,70onymous_,UP,NTRANS ++S 27800,11100,27800,15100,200,34onymous_,UP,PTRANS ++S 14000,200,14000,12000,6000,111nymous_,UP,TALU5 ++S 27300,11200,29500,11200,400,37onymous_,RIGHT,ALU1 ++S 9800,11100,9800,15100,200,73onymous_,UP,PTRANS ++S 27800,7500,27800,9500,200,36onymous_,UP,NTRANS ++S 9200,7700,9200,9300,420,72onymous_,UP,NDIF ++S 27800,9800,27800,10800,200,35onymous_,UP,POLY ++S 26000,7700,26000,9300,620,48onymous_,UP,NDIF ++S 33000,200,33000,12000,0,113nymous_,UP,TALU5 ++S 25000,200,25000,12000,8000,112nymous_,UP,TALU5 ++S 26600,7500,26600,9500,200,46onymous_,UP,NTRANS ++S 1400,200,1400,2000,3000,114nymous_,UP,TALU3 ++S 26000,11300,26000,14900,620,47onymous_,UP,PDIF ++S 9200,11300,9200,14900,620,71onymous_,UP,PDIF ++S 9800,9800,9800,10800,200,74onymous_,UP,POLY ++S 25000,13800,33000,13800,6800,49onymous_,RIGHT,NWELL ++S 38600,200,38600,2000,3000,115nymous_,UP,TALU3 ++S 27200,11300,27200,13900,400,39onymous_,UP,ALU1 ++S 9800,7500,9800,9500,200,75onymous_,UP,NTRANS ++S 27200,11300,27200,14900,620,38onymous_,UP,PDIF ++S 10400,11300,10400,14900,620,76onymous_,UP,PDIF ++S 27300,10200,31900,10200,400,40onymous_,RIGHT,ALU1 ++S 10400,11300,10400,13900,400,77onymous_,UP,ALU1 ++S 27300,9200,29500,9200,400,41onymous_,RIGHT,ALU1 ++S 11000,9800,11000,10800,200,80onymous_,UP,POLY ++S 14000,200,14000,2000,6000,117nymous_,UP,TALU3 ++S 26600,11100,26600,15100,200,43onymous_,UP,PTRANS ++S 11000,11100,11000,15100,200,79onymous_,UP,PTRANS ++S 7000,200,7000,2000,0,116nymous_,UP,TALU3 ++S 27200,7700,27200,9300,420,42onymous_,UP,NDIF ++S 10400,7700,10400,9300,420,78onymous_,UP,NDIF ++S 11000,7500,11000,9500,200,81onymous_,UP,NTRANS ++S 25880,16200,32120,16200,600,50onymous_,RIGHT,NTIE ++S 11600,11300,11600,14900,620,82onymous_,UP,PDIF ++S 25000,200,25000,2000,8000,118nymous_,UP,TALU3 ++S 11300,1000,28700,1000,400,0nonymous_,RIGHT,ALU3 ++S 11300,2000,28700,2000,400,1nonymous_,RIGHT,ALU3 ++S 11600,7700,11600,9300,620,83onymous_,UP,NDIF ++S 25700,16200,28700,16200,400,2nonymous_,RIGHT,ALU2 ++S 12200,11100,12200,15100,200,84onymous_,UP,PTRANS ++S 10500,11200,12700,11200,400,87onymous_,RIGHT,ALU1 ++S 14000,5900,14000,7700,400,4nonymous_,UP,ALU2 ++S 12200,7500,12200,9500,200,86onymous_,UP,NTRANS ++S 26000,5900,26000,7700,400,3nonymous_,UP,ALU2 ++S 12200,9800,12200,10800,200,85onymous_,UP,POLY ++S 33000,200,33000,2000,0,119nymous_,UP,TALU3 ++S 12800,11300,12800,14900,620,88onymous_,UP,PDIF ++S 8700,16200,14300,16200,400,5nonymous_,RIGHT,ALU2 ++S 50,17000,39950,17000,10000,blockagenet,RIGHT,TALU2 ++S 0,6000,40000,6000,12000,120nymous_,RIGHT,TALU6 ++S 37200,6000,39950,6000,12000,121nymous_,RIGHT,TALU4 ++S 11200,6000,16800,6000,12000,124nymous_,RIGHT,TALU4 ++S 21200,6000,28800,6000,12000,123nymous_,RIGHT,TALU4 ++S 30800,12100,30800,14900,400,9nonymous_,UP,ALU1 ++S 27200,700,27200,11500,400,6nonymous_,UP,ALU2 ++S 19000,0,19000,2000,2400,cko,UP,CALU4 ++S 19000,0,19000,2000,2400,cko,UP,CALU5 ++S 12800,11300,12800,13900,400,89onymous_,UP,ALU1 ++S 28400,700,28400,11500,400,7nonymous_,UP,ALU2 ++S 8100,10200,12700,10200,400,90onymous_,RIGHT,ALU1 ++S 28400,12300,28400,14900,400,8nonymous_,UP,ALU1 ++B 35000,16000,2300,2300,CONT_VIA2,286nymous_ ++B 11600,1000,300,300,CONT_VIA2,211nymous_ ++B 5000,7000,2300,2300,CONT_VIA2,285nymous_ ++B 12800,1000,300,300,CONT_VIA2,210nymous_ ++B 29600,10200,300,300,CONT_POLY,169nymous_ ++B 14000,13000,300,300,CONT_DIF_P,249nymous_ ++B 14000,14000,300,300,CONT_DIF_P,248nymous_ ++B 9200,7400,300,300,CONT_DIF_N,214nymous_ ++B 35000,1000,2300,2300,CONT_VIA3,288nymous_ ++B 28400,13000,300,300,CONT_DIF_P,173nymous_ ++B 11600,2000,300,300,CONT_VIA2,213nymous_ ++B 35000,1000,2300,2300,CONT_VIA4,287nymous_ ++B 28400,14000,300,300,CONT_DIF_P,172nymous_ ++B 12800,2000,300,300,CONT_VIA2,212nymous_ ++B 28400,15000,300,300,CONT_DIF_P,171nymous_ ++B 29600,9200,300,300,CONT_DIF_N,170nymous_ ++B 14000,12200,300,300,CONT_DIF_P,250nymous_ ++B 35000,10000,2300,2300,CONT_VIA2,290nymous_ ++B 7000,10200,300,300,CONT_VIA,215nymous_ ++B 35000,1000,2300,2300,CONT_VIA2,289nymous_ ++B 28400,12200,300,300,CONT_DIF_P,174nymous_ ++B 26000,16200,300,300,CONT_VIA2,133nymous_ ++B 28400,11200,300,300,CONT_VIA,175nymous_ ++B 7000,10200,300,300,CONT_POLY,216nymous_ ++B 28400,10200,300,300,CONT_POLY,176nymous_ ++B 23000,13000,4300,2300,CONT_VIA2,291nymous_ ++B 8000,12800,300,300,CONT_DIF_P,217nymous_ ++B 14000,8200,300,300,CONT_DIF_N,251nymous_ ++B 28400,9200,300,300,CONT_VIA,177nymous_ ++B 23000,13000,4300,2300,CONT_VIA,292nymous_ ++B 14000,7400,300,300,CONT_DIF_N,252nymous_ ++B 23000,7000,4300,2300,CONT_VIA2,293nymous_ ++B 10400,11200,200,200,CONT_TURN1,253nymous_ ++B 23000,7000,4300,2300,CONT_VIA,294nymous_ ++B 28400,8200,300,300,CONT_DIF_N,178nymous_ ++B 8000,9200,300,300,CONT_DIF_N,219nymous_ ++B 28400,7400,300,300,CONT_DIF_N,179nymous_ ++B 9200,15000,300,300,CONT_DIF_P,220nymous_ ++B 14000,16200,300,300,CONT_BODY_N,254nymous_ ++B 27200,14000,300,300,CONT_DIF_P,180nymous_ ++B 8000,11800,300,300,CONT_DIF_P,218nymous_ ++B 27200,16200,300,300,CONT_VIA,137nymous_ ++B 10400,16200,300,300,CONT_BODY_N,257nymous_ ++B 28400,16200,300,300,CONT_VIA,136nymous_ ++B 11600,16200,300,300,CONT_BODY_N,256nymous_ ++B 28400,16200,300,300,CONT_VIA2,135nymous_ ++B 27200,16200,300,300,CONT_VIA2,134nymous_ ++B 31000,1000,2300,2300,CONT_VIA4,295nymous_ ++B 12800,16200,300,300,CONT_BODY_N,255nymous_ ++B 26000,7400,300,300,CONT_VIA,140nymous_ ++B 26000,6200,300,300,CONT_VIA,139nymous_ ++B 26000,16200,300,300,CONT_VIA,138nymous_ ++B 31000,1000,2300,2300,CONT_VIA2,299nymous_ ++B 8000,16200,300,300,CONT_BODY_N,258nymous_ ++B 31000,7000,2300,2300,CONT_VIA2,298nymous_ ++B 27200,11200,300,300,CONT_VIA,183nymous_ ++B 31000,13000,2300,2300,CONT_VIA2,297nymous_ ++B 27200,12000,300,300,CONT_DIF_P,182nymous_ ++B 9200,13000,300,300,CONT_DIF_P,222nymous_ ++B 31000,1000,2300,2300,CONT_VIA3,296nymous_ ++B 27200,13000,300,300,CONT_DIF_P,181nymous_ ++B 9200,14000,300,300,CONT_DIF_P,221nymous_ ++B 26000,7400,300,300,CONT_VIA2,141nymous_ ++B 27200,9200,300,300,CONT_DIF_N,186nymous_ ++B 14000,6200,300,300,CONT_BODY_P,260nymous_ ++B 10400,14000,300,300,CONT_DIF_P,226nymous_ ++B 27200,9200,300,300,CONT_VIA,185nymous_ ++B 14000,6200,300,300,CONT_VIA,145nymous_ ++B 9200,16200,300,300,CONT_BODY_N,259nymous_ ++B 9200,8200,300,300,CONT_DIF_N,225nymous_ ++B 14000,6200,300,300,CONT_VIA2,144nymous_ ++B 27200,10200,300,300,CONT_POLY,184nymous_ ++B 9200,9200,300,300,CONT_DIF_N,224nymous_ ++B 14000,7400,300,300,CONT_VIA2,143nymous_ ++B 9200,12000,300,300,CONT_DIF_P,223nymous_ ++B 26000,6200,300,300,CONT_VIA2,142nymous_ ++B 11600,6200,300,300,CONT_BODY_P,262nymous_ ++B 12800,6200,300,300,CONT_BODY_P,261nymous_ ++B 26000,15000,300,300,CONT_DIF_P,187nymous_ ++B 10400,13000,300,300,CONT_DIF_P,227nymous_ ++B 14000,7400,300,300,CONT_VIA,146nymous_ ++B 8000,6200,300,300,CONT_BODY_P,265nymous_ ++B 26000,12200,300,300,CONT_DIF_P,190nymous_ ++B 9200,6200,300,300,CONT_BODY_P,264nymous_ ++B 26000,13000,300,300,CONT_DIF_P,189nymous_ ++B 11600,16200,300,300,CONT_VIA,149nymous_ ++B 10400,6200,300,300,CONT_BODY_P,263nymous_ ++B 12800,16200,300,300,CONT_VIA,148nymous_ ++B 26000,14000,300,300,CONT_DIF_P,188nymous_ ++B 14000,16200,300,300,CONT_VIA,147nymous_ ++B 10400,12000,300,300,CONT_DIF_P,228nymous_ ++B 26000,16200,300,300,CONT_BODY_N,194nymous_ ++B 10400,10200,300,300,CONT_POLY,229nymous_ ++B 10400,9200,300,300,CONT_DIF_N,230nymous_ ++B 27200,1000,300,300,CONT_VIA2,150nymous_ ++B 26000,8200,300,300,CONT_DIF_N,191nymous_ ++B 28400,1000,300,300,CONT_VIA2,151nymous_ ++B 12800,8400,300,300,CONT_DIF_N,266nymous_ ++B 29600,11200,200,200,CONT_TURN1,193nymous_ ++B 26000,7400,300,300,CONT_DIF_N,192nymous_ ++B 10400,8400,300,300,CONT_DIF_N,268nymous_ ++B 7000,4000,300,300,CONT_VIA2,269nymous_ ++B 27200,16200,300,300,CONT_BODY_N,195nymous_ ++B 9000,1000,2300,2300,CONT_VIA2,270nymous_ ++B 28400,16200,300,300,CONT_BODY_N,196nymous_ ++B 29600,16200,300,300,CONT_BODY_N,197nymous_ ++B 11600,15000,300,300,CONT_DIF_P,231nymous_ ++B 11600,14000,300,300,CONT_DIF_P,232nymous_ ++B 27200,2000,300,300,CONT_VIA2,152nymous_ ++B 11600,13000,300,300,CONT_DIF_P,233nymous_ ++B 8000,8400,300,300,CONT_DIF_N,267nymous_ ++B 11600,12200,300,300,CONT_DIF_P,234nymous_ ++B 30800,7400,300,300,CONT_DIF_N,154nymous_ ++B 11600,11200,300,300,CONT_VIA,235nymous_ ++B 33000,10200,300,300,CONT_VIA,155nymous_ ++B 11600,10200,300,300,CONT_POLY,236nymous_ ++B 33000,10200,300,300,CONT_POLY,156nymous_ ++B 11600,9200,300,300,CONT_VIA,237nymous_ ++B 9000,16000,2300,2300,CONT_VIA2,271nymous_ ++B 11600,8200,300,300,CONT_DIF_N,238nymous_ ++B 9000,10000,2300,2300,CONT_VIA2,272nymous_ ++B 32000,16200,300,300,CONT_BODY_N,198nymous_ ++B 9000,1000,2300,2300,CONT_VIA3,273nymous_ ++B 30800,16200,300,300,CONT_BODY_N,199nymous_ ++B 28400,2000,300,300,CONT_VIA2,153nymous_ ++B 26000,6200,300,300,CONT_BODY_P,200nymous_ ++B 27200,6200,300,300,CONT_BODY_P,201nymous_ ++B 12800,13000,300,300,CONT_DIF_P,241nymous_ ++B 28400,6200,300,300,CONT_BODY_P,202nymous_ ++B 32000,12800,300,300,CONT_DIF_P,157nymous_ ++B 32000,11800,300,300,CONT_DIF_P,158nymous_ ++B 11600,7400,300,300,CONT_DIF_N,239nymous_ ++B 32000,9200,300,300,CONT_DIF_N,159nymous_ ++B 12800,14000,300,300,CONT_DIF_P,240nymous_ ++B 9000,1000,2300,2300,CONT_VIA4,274nymous_ ++B 19000,1000,2300,2300,CONT_VIA4,275nymous_ ++B 30800,15000,300,300,CONT_DIF_P,160nymous_ ++B 12800,12000,300,300,CONT_DIF_P,242nymous_ ++B 30800,14000,300,300,CONT_DIF_P,161nymous_ ++B 19000,1000,2300,2300,CONT_VIA3,276nymous_ ++B 30800,13000,300,300,CONT_DIF_P,162nymous_ ++B 17000,13000,4300,2300,CONT_VIA2,277nymous_ ++B 29600,6200,300,300,CONT_BODY_P,203nymous_ ++B 12800,11200,300,300,CONT_VIA,243nymous_ ++B 30800,12000,300,300,CONT_DIF_P,163nymous_ ++B 12800,10200,300,300,CONT_POLY,244nymous_ ++B 17000,13000,4300,2300,CONT_VIA,278nymous_ ++B 30800,6200,300,300,CONT_BODY_P,204nymous_ ++B 30800,9200,300,300,CONT_DIF_N,164nymous_ ++B 12800,9200,300,300,CONT_VIA,245nymous_ ++B 17000,7000,4300,2300,CONT_VIA2,279nymous_ ++B 32000,6200,300,300,CONT_BODY_P,205nymous_ ++B 30800,8200,300,300,CONT_DIF_N,165nymous_ ++B 17000,7000,4300,2300,CONT_VIA,280nymous_ ++B 27200,8400,300,300,CONT_DIF_N,206nymous_ ++B 5000,13000,2300,2300,CONT_VIA2,281nymous_ ++B 32000,8400,300,300,CONT_DIF_N,207nymous_ ++B 5000,1000,2300,2300,CONT_VIA4,282nymous_ ++B 29600,13000,300,300,CONT_DIF_P,167nymous_ ++B 29600,8400,300,300,CONT_DIF_N,208nymous_ ++B 29600,12000,300,300,CONT_DIF_P,168nymous_ ++B 5000,1000,2300,2300,CONT_VIA3,283nymous_ ++B 33000,4000,300,300,CONT_VIA2,209nymous_ ++B 5000,1000,2300,2300,CONT_VIA2,284nymous_ ++B 12800,9200,300,300,CONT_DIF_N,246nymous_ ++B 29600,14000,300,300,CONT_DIF_P,166nymous_ ++B 14000,15000,300,300,CONT_DIF_P,247nymous_ ++EOF +diff --git a/alliance/src/cells/src/mpxlib/pvssick_mpx.vbe b/alliance/src/cells/src/mpxlib/pvssick_mpx.vbe +new file mode 100644 +index 0000000..95d24f3 +--- /dev/null ++++ b/alliance/src/cells/src/mpxlib/pvssick_mpx.vbe +@@ -0,0 +1,32 @@ ++ENTITY pvssick_mpx IS ++ GENERIC ( ++ CONSTANT area : NATURAL := 80000; ++ CONSTANT cin_ck : NATURAL := 127; ++ CONSTANT tpll_ck : NATURAL := 1235; ++ CONSTANT rdown_ck : NATURAL := 253; ++ CONSTANT tphh_ck : NATURAL := 1109; ++ CONSTANT rup_ck : NATURAL := 311 ++ ); ++ PORT ( ++ cko : out WOR_BIT BUS; ++ ck : in BIT; ++ vdde : in BIT; ++ vddi : in BIT; ++ vsse : in BIT; ++ vssi : in BIT ++ ); ++END pvssick_mpx; ++ ++ARCHITECTURE behaviour_data_flow OF pvssick_mpx IS ++ ++BEGIN ++ ++ label0 : BLOCK ('1' = '1') ++ BEGIN ++ cko <= GUARDED ck; ++ END BLOCK label0; ++ ++ ASSERT ((((vddi and vdde) and not (vssi)) and not (vsse)) = '1') ++ REPORT "power supply is missing on pvssick_mpx" ++ SEVERITY WARNING; ++END; +diff --git a/alliance/src/cells/src/msxlib/CATAL b/alliance/src/cells/src/msxlib/CATAL +new file mode 100644 +index 0000000..6fd9b7e +--- /dev/null ++++ b/alliance/src/cells/src/msxlib/CATAL +@@ -0,0 +1,123 @@ ++an2_x05 C ++an2_x1 C ++an2_x2 C ++an3_x1 C ++an3_x2 C ++an4_x1 C ++an4_x2 C ++an4_x3 C ++aoi21_x05 C ++aoi21_x1 C ++aoi21_x2 C ++aoi22_x05 C ++aoi22_x1 C ++aoi22_x2 C ++aon21_x1 C ++aon21_x2 C ++aon22_x1 C ++aon22_x2 C ++bf1_w05 C ++bf1_w2 C ++bf1_x1 C ++bf1_x2 C ++bf1_x4 C ++bf1_x8 C ++bf1_y05 C ++bf1_y1 C ++bf1_y2 C ++cgi2a_x05 C ++cgi2a_x1 C ++cgi2a_x2 C ++cgi2_x05 C ++cgi2_x1 C ++cgi2_x2 C ++cgn2_x1 C ++cgn2_x2 C ++cgn2_x3 C ++cgn2_x4 C ++ha2_x2 C ++iv1_w2 C ++iv1_x05 C ++iv1_x1 C ++iv1_x2 C ++iv1_x3 C ++iv1_x4 C ++iv1_x8 C ++iv1_y2 C ++mxi2_x05 C ++mxi2_x1 C ++nd2ab_x1 C ++nd2ab_x2 C ++nd2a_x1 C ++nd2a_x2 C ++nd2_x05 C ++nd2_x1 C ++nd2_x2 C ++nd2_x4 C ++nd3_x05 C ++nd3_x1 C ++nd3_x2 C ++nd3_x4 C ++nd4_x05 C ++nd4_x1 C ++nd4_x2 C ++nd4_x3 C ++nr2a_x05 C ++nr2a_x1 C ++nr2_x05 C ++nr2_x1 C ++nr2_x2 C ++nr3_x05 C ++nr3_x1 C ++nr4_x05 C ++nr4_x1 C ++oai21_x05 C ++oai21_x1 C ++oai21_x2 C ++oai22_x05 C ++oai22_x1 C ++oai22_x2 C ++oan21_x1 C ++oan21_x2 C ++oan22_x1 C ++oan22_x2 C ++or2_x1 C ++or3_x1 C ++or4_x1 C ++powmid_x0 C ++powmid_x0 F ++rowend_x0 C ++rowend_x0 F ++sff1_x4 C ++sff2_x4 C ++sff3_x4 C ++tie_x0 C ++tie_x0 F ++vddtie C ++vfeed1 C ++vfeed1 F ++vfeed2 C ++vfeed2 F ++vfeed3 C ++vfeed3 F ++vfeed4 C ++vfeed4 F ++vfeed5 C ++vfeed5 F ++vfeed6 C ++vfeed6 F ++vfeed7 C ++vfeed7 F ++vfeed8 C ++vfeed8 F ++vsstie C ++xaoi21_x05 C ++xaoi21_x1 C ++xaon21_x05 C ++xaon21_x1 C ++xaon22_x05 C ++xaon22_x1 C ++xnr2_x05 C ++xnr2_x1 C ++xor2_x05 C ++xor2_x1 C +diff --git a/alliance/src/cells/src/msxlib/Makefile.am b/alliance/src/cells/src/msxlib/Makefile.am +new file mode 100644 +index 0000000..d67fc5b +--- /dev/null ++++ b/alliance/src/cells/src/msxlib/Makefile.am +@@ -0,0 +1,232 @@ ++ ++msxlibdir=$(prefix)/cells/msxlib ++ ++msxlib_DATA=CATAL \ ++ an2_x05.ap \ ++ an2_x05.vbe \ ++ an2_x1.ap \ ++ an2_x1.vbe \ ++ an2_x2.ap \ ++ an2_x2.vbe \ ++ an3_x1.ap \ ++ an3_x1.vbe \ ++ an3_x2.ap \ ++ an3_x2.vbe \ ++ an4_x1.ap \ ++ an4_x1.vbe \ ++ an4_x2.ap \ ++ an4_x2.vbe \ ++ an4_x3.ap \ ++ an4_x3.vbe \ ++ aoi21_x05.ap \ ++ aoi21_x05.vbe \ ++ aoi21_x1.ap \ ++ aoi21_x1.vbe \ ++ aoi21_x2.ap \ ++ aoi21_x2.vbe \ ++ aoi22_x05.ap \ ++ aoi22_x05.vbe \ ++ aoi22_x1.ap \ ++ aoi22_x1.vbe \ ++ aoi22_x2.ap \ ++ aoi22_x2.vbe \ ++ aon21_x1.ap \ ++ aon21_x1.vbe \ ++ aon21_x2.ap \ ++ aon21_x2.vbe \ ++ aon22_x1.ap \ ++ aon22_x1.vbe \ ++ aon22_x2.ap \ ++ aon22_x2.vbe \ ++ bf1_w05.ap \ ++ bf1_w05.vbe \ ++ bf1_w2.ap \ ++ bf1_w2.vbe \ ++ bf1_x1.ap \ ++ bf1_x1.vbe \ ++ bf1_x2.ap \ ++ bf1_x2.vbe \ ++ bf1_x4.ap \ ++ bf1_x4.vbe \ ++ bf1_x8.ap \ ++ bf1_x8.vbe \ ++ bf1_y05.ap \ ++ bf1_y05.vbe \ ++ bf1_y1.ap \ ++ bf1_y1.vbe \ ++ bf1_y2.ap \ ++ bf1_y2.vbe \ ++ cgi2a_x05.ap \ ++ cgi2a_x05.vbe \ ++ cgi2a_x1.ap \ ++ cgi2a_x1.vbe \ ++ cgi2a_x2.ap \ ++ cgi2a_x2.vbe \ ++ cgi2_x05.ap \ ++ cgi2_x05.vbe \ ++ cgi2_x1.ap \ ++ cgi2_x1.vbe \ ++ cgi2_x2.ap \ ++ cgi2_x2.vbe \ ++ cgn2_x1.ap \ ++ cgn2_x1.vbe \ ++ cgn2_x2.ap \ ++ cgn2_x2.vbe \ ++ cgn2_x3.ap \ ++ cgn2_x3.vbe \ ++ cgn2_x4.ap \ ++ cgn2_x4.vbe \ ++ ha2_x2.ap \ ++ ha2_x2.vbe \ ++ iv1_w2.ap \ ++ iv1_w2.vbe \ ++ iv1_x05.ap \ ++ iv1_x05.vbe \ ++ iv1_x1.ap \ ++ iv1_x1.vbe \ ++ iv1_x2.ap \ ++ iv1_x2.vbe \ ++ iv1_x3.ap \ ++ iv1_x3.vbe \ ++ iv1_x4.ap \ ++ iv1_x4.vbe \ ++ iv1_x8.ap \ ++ iv1_x8.vbe \ ++ iv1_y2.ap \ ++ iv1_y2.vbe \ ++ Makefile.am \ ++ mxi2_x05.ap \ ++ mxi2_x05.vbe \ ++ mxi2_x1.ap \ ++ mxi2_x1.vbe \ ++ nd2ab_x1.ap \ ++ nd2ab_x1.vbe \ ++ nd2ab_x2.ap \ ++ nd2ab_x2.vbe \ ++ nd2a_x1.ap \ ++ nd2a_x1.vbe \ ++ nd2a_x2.ap \ ++ nd2a_x2.vbe \ ++ nd2_x05.ap \ ++ nd2_x05.vbe \ ++ nd2_x1.ap \ ++ nd2_x1.vbe \ ++ nd2_x2.ap \ ++ nd2_x2.vbe \ ++ nd2_x4.ap \ ++ nd2_x4.vbe \ ++ nd3_x05.ap \ ++ nd3_x05.vbe \ ++ nd3_x1.ap \ ++ nd3_x1.vbe \ ++ nd3_x2.ap \ ++ nd3_x2.vbe \ ++ nd3_x4.ap \ ++ nd3_x4.vbe \ ++ nd4_x05.ap \ ++ nd4_x05.vbe \ ++ nd4_x1.ap \ ++ nd4_x1.vbe \ ++ nd4_x2.ap \ ++ nd4_x2.vbe \ ++ nd4_x3.ap \ ++ nd4_x3.vbe \ ++ nr2a_x05.ap \ ++ nr2a_x05.vbe \ ++ nr2a_x1.ap \ ++ nr2a_x1.vbe \ ++ nr2_x05.ap \ ++ nr2_x05.vbe \ ++ nr2_x1.ap \ ++ nr2_x1.vbe \ ++ nr2_x2.ap \ ++ nr2_x2.vbe \ ++ nr3_x05.ap \ ++ nr3_x05.vbe \ ++ nr3_x1.ap \ ++ nr3_x1.vbe \ ++ nr4_x05.ap \ ++ nr4_x05.vbe \ ++ nr4_x1.ap \ ++ nr4_x1.vbe \ ++ oai21_x05.ap \ ++ oai21_x05.vbe \ ++ oai21_x1.ap \ ++ oai21_x1.vbe \ ++ oai21_x2.ap \ ++ oai21_x2.vbe \ ++ oai22_x05.ap \ ++ oai22_x05.vbe \ ++ oai22_x1.ap \ ++ oai22_x1.vbe \ ++ oai22_x2.ap \ ++ oai22_x2.vbe \ ++ oan21_x1.ap \ ++ oan21_x1.vbe \ ++ oan21_x2.ap \ ++ oan21_x2.vbe \ ++ oan22_x1.ap \ ++ oan22_x1.vbe \ ++ oan22_x2.ap \ ++ oan22_x2.vbe \ ++ or2_x1.ap \ ++ or2_x1.vbe \ ++ or3_x1.ap \ ++ or3_x1.vbe \ ++ or4_x1.ap \ ++ or4_x1.vbe \ ++ powmid_x0.ap \ ++ powmid_x0.vbe \ ++ rowend_x0.ap \ ++ rowend_x0.vbe \ ++ sff1_x4.ap \ ++ sff1_x4.vbe \ ++ sff2_x4.ap \ ++ sff2_x4.vbe \ ++ sff3_x4.ap \ ++ sff3_x4.vbe \ ++ tie_x0.ap \ ++ tie_x0.vbe \ ++ vddtie.ap \ ++ vddtie.vbe \ ++ vfeed1.ap \ ++ vfeed1.vbe \ ++ vfeed2.ap \ ++ vfeed2.vbe \ ++ vfeed3.ap \ ++ vfeed3.vbe \ ++ vfeed4.ap \ ++ vfeed4.vbe \ ++ vfeed5.ap \ ++ vfeed5.vbe \ ++ vfeed6.ap \ ++ vfeed6.vbe \ ++ vfeed7.ap \ ++ vfeed7.vbe \ ++ vfeed8.ap \ ++ vfeed8.vbe \ ++ vsstie.ap \ ++ vsstie.vbe \ ++ xaoi21_x05.ap \ ++ xaoi21_x05.vbe \ ++ xaoi21_x1.ap \ ++ xaoi21_x1.vbe \ ++ xaon21_x05.ap \ ++ xaon21_x05.vbe \ ++ xaon21_x1.ap \ ++ xaon21_x1.vbe \ ++ xaon22_x05.ap \ ++ xaon22_x05.vbe \ ++ xaon22_x1.ap \ ++ xaon22_x1.vbe \ ++ xnr2_x05.ap \ ++ xnr2_x05.vbe \ ++ xnr2_x1.ap \ ++ xnr2_x1.vbe \ ++ xor2_x05.ap \ ++ xor2_x05.vbe \ ++ xor2_x1.ap \ ++ xor2_x1.vbe ++ ++EXTRA_DIST=$(msxlib_DATA) ++ +diff --git a/alliance/src/cells/src/msxlib/README b/alliance/src/cells/src/msxlib/README +new file mode 100644 +index 0000000..5455f04 +--- /dev/null ++++ b/alliance/src/cells/src/msxlib/README +@@ -0,0 +1,5 @@ ++ ++This library is derived from the 130um vsxlib from Graham Petley . ++ ++It has been modificated to better fit the MOSIS scn6m_deep technology. ++ +diff --git a/alliance/src/cells/src/msxlib/an2_x05.ap b/alliance/src/cells/src/msxlib/an2_x05.ap +new file mode 100644 +index 0000000..dd93d6d +--- /dev/null ++++ b/alliance/src/cells/src/msxlib/an2_x05.ap +@@ -0,0 +1,85 @@ ++V ALLIANCE : 6 ++H an2_x05,P, 8/ 8/2014,100 ++A 0,0,5000,10000 ++R 3000,5000,ref_ref,a_50 ++R 3000,4000,ref_ref,a_40 ++R 1000,7000,ref_ref,z_70 ++R 1000,6000,ref_ref,z_60 ++R 1000,5000,ref_ref,z_50 ++R 1000,4000,ref_ref,z_40 ++R 4000,6000,ref_ref,b_60 ++R 4000,7000,ref_ref,b_70 ++R 3000,7000,ref_ref,b_70 ++R 4000,5000,ref_ref,b_50 ++R 2000,7000,ref_ref,z_70 ++R 4000,4000,ref_ref,a_40 ++S 1100,700,1700,700,600,*,LEFT,PTIE ++S 1100,9300,1900,9300,600,*,LEFT,NTIE ++S 4000,4900,4000,7000,400,*,UP,ALU1 ++S 3000,7000,3000,7000,400,b,LEFT,CALU1 ++S 2000,7000,2000,7000,400,z,LEFT,CALU1 ++S 0,600,5000,600,1200,vss,RIGHT,CALU1 ++S 0,5000,5000,5000,10000,an2_x05,LEFT,TALU8 ++S 0,2200,5000,2200,5200,*,LEFT,PWELL ++S 0,7600,5000,7600,5600,*,LEFT,NWELL ++S 0,9400,5000,9400,1200,vdd,RIGHT,CALU1 ++S 2000,6100,3200,6100,600,*,LEFT,ALU1 ++S 4000,5000,4000,7000,400,b,UP,CALU1 ++S 4400,6000,4400,8100,600,*,DOWN,PDIF ++S 2600,5200,2600,5800,200,*,DOWN,POLY ++S 1000,7000,2100,7000,400,*,RIGHT,ALU1 ++S 1000,7100,2100,7100,400,*,RIGHT,ALU1 ++S 2900,7100,4000,7100,400,*,LEFT,ALU1 ++S 2900,7000,4000,7000,400,*,LEFT,ALU1 ++S 2000,6000,2000,7600,600,*,DOWN,PDIF ++S 2000,7900,2000,9300,400,*,DOWN,ALU1 ++S 4400,7900,4400,9300,400,*,DOWN,ALU1 ++S 1000,4000,1000,7000,400,z,DOWN,CALU1 ++S 1600,3800,1600,4600,200,*,UP,POLY ++S 1400,4500,1400,5500,200,*,DOWN,POLY ++S 1000,6000,1000,6800,400,*,UP,PDIF ++S 1400,5800,1400,7000,200,1z,DOWN,PTRANS ++S 1400,7000,1400,7400,200,*,DOWN,POLY ++S 900,6000,900,6200,600,*,UP,ALU1 ++S 2600,5800,2600,7000,200,1a,DOWN,PTRANS ++S 3800,5800,3800,7000,200,1b,DOWN,PTRANS ++S 3200,6000,3200,6800,400,*,UP,PDIF ++S 2600,7000,2600,7400,200,*,DOWN,POLY ++S 3800,7000,3800,7400,200,*,DOWN,POLY ++S 1600,3200,1600,3800,200,2z,UP,NTRANS ++S 1600,2800,1600,3200,200,*,UP,POLY ++S 1000,3400,1000,7100,400,*,DOWN,ALU1 ++S 3000,3900,4100,3900,400,*,RIGHT,ALU1 ++S 3000,4000,4100,4000,400,*,RIGHT,ALU1 ++S 4000,4000,4000,4000,400,a,LEFT,CALU1 ++S 3000,3900,3000,5200,400,*,DOWN,ALU1 ++S 3000,4000,3000,5000,400,a,DOWN,CALU1 ++S 2000,3000,4500,3000,400,*,LEFT,ALU1 ++S 3400,2500,3400,3100,600,n1,DOWN,NDIF ++S 3000,2300,3000,3300,200,2a,UP,NTRANS ++S 4200,2500,4200,3100,400,*,UP,NDIF ++S 3800,2300,3800,3300,200,2b,UP,NTRANS ++S 3000,1900,3000,2300,200,*,UP,POLY ++S 3800,1900,3800,2300,200,*,UP,POLY ++S 3000,3300,3000,4900,200,*,UP,POLY ++S 3800,3300,3800,5800,200,*,DOWN,POLY ++S 2000,3000,2000,6200,400,*,UP,ALU1 ++S 2300,700,2300,2100,400,*,DOWN,ALU1 ++S 2300,1900,2300,3600,800,*,UP,NDIF ++S 2600,5300,3000,5300,200,*,RIGHT,POLY ++S 1400,4400,2200,4400,600,*,LEFT,POLY ++V 1800,700,CONT_BODY_P,* ++V 1100,700,CONT_BODY_P,* ++V 2000,9300,CONT_BODY_N,* ++V 1100,9300,CONT_BODY_N,* ++V 3000,5100,CONT_POLY,* ++V 3200,6100,CONT_DIF_P,zn ++V 2000,4400,CONT_POLY,zn ++V 1000,3500,CONT_DIF_N,* ++V 2000,8000,CONT_DIF_P,* ++V 4400,8000,CONT_DIF_P,* ++V 4000,5000,CONT_POLY,* ++V 800,6100,CONT_DIF_P,* ++V 4400,3000,CONT_DIF_N,zn ++V 2300,2000,CONT_DIF_N,* ++EOF +diff --git a/alliance/src/cells/src/msxlib/an2_x05.vbe b/alliance/src/cells/src/msxlib/an2_x05.vbe +new file mode 100644 +index 0000000..2f01024 +--- /dev/null ++++ b/alliance/src/cells/src/msxlib/an2_x05.vbe +@@ -0,0 +1,32 @@ ++ENTITY an2_x05 IS ++GENERIC ( ++ CONSTANT area : NATURAL := 5000; ++ CONSTANT cin_b : NATURAL := 3; ++ CONSTANT cin_a : NATURAL := 3; ++ CONSTANT rdown_b_z : NATURAL := 3810; ++ CONSTANT rdown_a_z : NATURAL := 3830; ++ CONSTANT rup_b_z : NATURAL := 4940; ++ CONSTANT rup_a_z : NATURAL := 4940; ++ CONSTANT tphh_a_z : NATURAL := 71; ++ CONSTANT tphh_b_z : NATURAL := 70; ++ CONSTANT tpll_b_z : NATURAL := 87; ++ CONSTANT tpll_a_z : NATURAL := 97; ++ CONSTANT transistors : NATURAL := 6 ++); ++PORT ( ++ b : in BIT; ++ a : in BIT; ++ z : out BIT; ++ vdd : in BIT; ++ vss : in BIT ++); ++END an2_x05; ++ ++ARCHITECTURE behaviour_data_flow OF an2_x05 IS ++ ++BEGIN ++ ASSERT ((vdd and not (vss)) = '1') ++ REPORT "power supply is missing on an2_x05" ++ SEVERITY WARNING; ++ z <= (b and a) after 1000 ps; ++END; +diff --git a/alliance/src/cells/src/msxlib/an2_x1.ap b/alliance/src/cells/src/msxlib/an2_x1.ap +new file mode 100644 +index 0000000..3637824 +--- /dev/null ++++ b/alliance/src/cells/src/msxlib/an2_x1.ap +@@ -0,0 +1,90 @@ ++V ALLIANCE : 6 ++H an2_x1,P, 8/ 8/2014,100 ++A 0,0,5000,10000 ++R 4000,4000,ref_ref,a_40 ++R 2000,7000,ref_ref,z_70 ++R 4000,5000,ref_ref,b_50 ++R 3000,7000,ref_ref,b_70 ++R 4000,7000,ref_ref,b_70 ++R 4000,6000,ref_ref,b_60 ++R 1000,4000,ref_ref,z_40 ++R 1000,5000,ref_ref,z_50 ++R 1000,6000,ref_ref,z_60 ++R 1000,7000,ref_ref,z_70 ++R 3000,4000,ref_ref,a_40 ++R 3000,5000,ref_ref,a_50 ++S 1100,700,1700,700,600,*,LEFT,PTIE ++S 1100,9300,1900,9300,600,*,LEFT,NTIE ++S 2300,700,2300,2000,600,*,DOWN,ALU1 ++S 2300,1900,2300,3600,800,*,UP,NDIF ++S 4400,2100,4400,2700,600,*,DOWN,NDIF ++S 4400,2000,4400,2800,600,*,DOWN,ALU1 ++S 2000,2800,2000,6200,400,*,UP,ALU1 ++S 2000,2800,4500,2800,400,*,LEFT,ALU1 ++S 3000,4000,3000,5000,400,a,DOWN,CALU1 ++S 3000,3900,3000,5200,400,*,DOWN,ALU1 ++S 4000,4000,4000,4000,400,a,LEFT,CALU1 ++S 3000,4000,4100,4000,400,*,RIGHT,ALU1 ++S 3000,3900,4100,3900,400,*,RIGHT,ALU1 ++S 900,6000,900,7000,600,*,UP,ALU1 ++S 800,7000,2100,7000,400,*,RIGHT,ALU1 ++S 3000,2700,3000,4900,200,*,UP,POLY ++S 3800,2700,3800,5800,200,*,DOWN,POLY ++S 1400,4500,1400,5500,200,*,DOWN,POLY ++S 1600,3800,1600,4600,200,*,UP,POLY ++S 1000,3400,1000,7000,400,*,DOWN,ALU1 ++S 1000,4000,1000,7000,400,z,DOWN,CALU1 ++S 4400,7900,4400,9300,400,*,DOWN,ALU1 ++S 2000,7900,2000,9300,400,*,DOWN,ALU1 ++S 2000,6000,2000,7600,600,*,DOWN,PDIF ++S 2900,7000,4000,7000,400,*,LEFT,ALU1 ++S 2900,7100,4000,7100,400,*,LEFT,ALU1 ++S 2600,5200,2600,5800,200,*,DOWN,POLY ++S 4400,6000,4400,8100,600,*,DOWN,PDIF ++S 4000,5000,4000,7000,400,b,UP,CALU1 ++S 2000,6100,3200,6100,600,*,LEFT,ALU1 ++S 0,9400,5000,9400,1200,vdd,RIGHT,CALU1 ++S 0,5000,5000,5000,10000,an2_x1,LEFT,TALU8 ++S 0,2200,5000,2200,5200,*,LEFT,PWELL ++S 0,7600,5000,7600,5600,*,LEFT,NWELL ++S 0,600,5000,600,1200,vss,RIGHT,CALU1 ++S 3000,1300,3000,1700,200,*,UP,POLY ++S 3800,1300,3800,1700,200,*,UP,POLY ++S 2000,7000,2000,7000,400,z,LEFT,CALU1 ++S 3000,7000,3000,7000,400,b,LEFT,CALU1 ++S 4000,4900,4000,7000,400,*,UP,ALU1 ++S 1400,5800,1400,7800,200,1z,DOWN,PTRANS ++S 1000,6000,1000,7600,400,*,UP,PDIF ++S 1400,7800,1400,8200,200,*,DOWN,POLY ++S 3800,5800,3800,7400,200,1b,DOWN,PTRANS ++S 2600,5800,2600,7400,200,1a,DOWN,PTRANS ++S 3200,6000,3200,7200,400,*,UP,PDIF ++S 2600,7400,2600,7800,200,*,DOWN,POLY ++S 3800,7400,3800,7800,200,*,DOWN,POLY ++S 800,6200,800,6800,600,*,UP,PDIF ++S 1600,2800,1600,3800,200,2z,UP,NTRANS ++S 1600,2400,1600,2800,200,*,UP,POLY ++S 1200,3000,1200,3600,400,*,UP,NDIF ++S 3400,1900,3400,2900,600,n1,DOWN,NDIF ++S 3000,1700,3000,3100,200,2a,UP,NTRANS ++S 3800,1700,3800,3100,200,2b,UP,NTRANS ++S 4200,1900,4200,2900,400,*,UP,NDIF ++S 2600,5300,3000,5300,200,*,RIGHT,POLY ++S 1400,4400,2200,4400,600,*,LEFT,POLY ++V 1800,700,CONT_BODY_P,* ++V 1100,700,CONT_BODY_P,* ++V 2000,9300,CONT_BODY_N,* ++V 1100,9300,CONT_BODY_N,* ++V 2300,2000,CONT_DIF_N,* ++V 4400,2000,CONT_DIF_N,zn ++V 4400,2800,CONT_DIF_N,zn ++V 800,6100,CONT_DIF_P,* ++V 4000,5000,CONT_POLY,* ++V 4400,8000,CONT_DIF_P,* ++V 2000,8000,CONT_DIF_P,* ++V 1000,3500,CONT_DIF_N,* ++V 2000,4400,CONT_POLY,zn ++V 3200,6100,CONT_DIF_P,zn ++V 3000,5100,CONT_POLY,* ++V 800,6900,CONT_DIF_P,* ++EOF +diff --git a/alliance/src/cells/src/msxlib/an2_x1.vbe b/alliance/src/cells/src/msxlib/an2_x1.vbe +new file mode 100644 +index 0000000..11d6ba4 +--- /dev/null ++++ b/alliance/src/cells/src/msxlib/an2_x1.vbe +@@ -0,0 +1,32 @@ ++ENTITY an2_x1 IS ++GENERIC ( ++ CONSTANT area : NATURAL := 5000; ++ CONSTANT cin_b : NATURAL := 4; ++ CONSTANT cin_a : NATURAL := 4; ++ CONSTANT rdown_b_z : NATURAL := 2290; ++ CONSTANT rdown_a_z : NATURAL := 2290; ++ CONSTANT rup_b_z : NATURAL := 2960; ++ CONSTANT rup_a_z : NATURAL := 2960; ++ CONSTANT tphh_a_z : NATURAL := 68; ++ CONSTANT tphh_b_z : NATURAL := 68; ++ CONSTANT tpll_b_z : NATURAL := 87; ++ CONSTANT tpll_a_z : NATURAL := 97; ++ CONSTANT transistors : NATURAL := 6 ++); ++PORT ( ++ b : in BIT; ++ a : in BIT; ++ z : out BIT; ++ vdd : in BIT; ++ vss : in BIT ++); ++END an2_x1; ++ ++ARCHITECTURE behaviour_data_flow OF an2_x1 IS ++ ++BEGIN ++ ASSERT ((vdd and not (vss)) = '1') ++ REPORT "power supply is missing on an2_x1" ++ SEVERITY WARNING; ++ z <= (b and a) after 1000 ps; ++END; +diff --git a/alliance/src/cells/src/msxlib/an2_x2.ap b/alliance/src/cells/src/msxlib/an2_x2.ap +new file mode 100644 +index 0000000..c747c4c +--- /dev/null ++++ b/alliance/src/cells/src/msxlib/an2_x2.ap +@@ -0,0 +1,94 @@ ++V ALLIANCE : 6 ++H an2_x2,P, 8/ 8/2014,100 ++A 0,0,5000,10000 ++R 4000,4000,ref_ref,a_40 ++R 3000,5000,ref_ref,a_50 ++R 3000,4000,ref_ref,a_40 ++R 1000,7000,ref_ref,z_70 ++R 1000,6000,ref_ref,z_60 ++R 1000,5000,ref_ref,z_50 ++R 1000,4000,ref_ref,z_40 ++R 1000,3000,ref_ref,z_30 ++R 4000,6000,ref_ref,b_60 ++R 4000,7000,ref_ref,b_70 ++R 3000,7000,ref_ref,b_70 ++R 4000,5000,ref_ref,b_50 ++R 2000,7000,ref_ref,z_70 ++S 1100,700,1700,700,600,*,RIGHT,PTIE ++S 3300,9300,3900,9300,600,*,LEFT,NTIE ++S 2600,5300,3000,5300,200,*,RIGHT,POLY ++S 0,9400,5000,9400,1200,vdd,RIGHT,CALU1 ++S 4400,1900,4400,3000,400,*,DOWN,ALU1 ++S 2000,3000,4400,3000,400,*,LEFT,ALU1 ++S 4400,2100,4400,2700,600,*,UP,NDIF ++S 2300,700,2300,2200,400,*,DOWN,ALU1 ++S 2300,1900,2300,3600,800,*,UP,NDIF ++S 2000,3000,2000,6200,400,*,UP,ALU1 ++S 3000,3900,3000,5200,400,*,DOWN,ALU1 ++S 3000,4000,3000,5000,400,a,DOWN,CALU1 ++S 3000,3900,4100,3900,400,*,RIGHT,ALU1 ++S 3000,4000,4100,4000,400,*,RIGHT,ALU1 ++S 4000,4000,4000,4000,400,a,LEFT,CALU1 ++S 800,7000,2100,7000,400,*,RIGHT,ALU1 ++S 900,5700,900,7000,600,*,UP,ALU1 ++S 4000,4900,4000,7100,400,*,UP,ALU1 ++S 3000,7000,3000,7000,400,b,LEFT,CALU1 ++S 2000,7000,2000,7000,400,z,LEFT,CALU1 ++S 1400,4200,1400,5500,200,*,DOWN,POLY ++S 1000,2600,1000,7000,400,*,DOWN,ALU1 ++S 1000,2800,1000,3400,600,*,DOWN,NDIF ++S 1600,1900,1600,3800,200,2z,UP,NTRANS ++S 3000,1700,3000,3800,200,2a,UP,NTRANS ++S 3800,1700,3800,3800,200,2b,UP,NTRANS ++S 1400,5500,1400,9300,200,1z,DOWN,PTRANS ++S 2600,5800,2600,8300,200,1a,DOWN,PTRANS ++S 3800,5800,3800,8300,200,1b,DOWN,PTRANS ++S 4200,1900,4200,3600,400,*,UP,NDIF ++S 3800,1300,3800,1700,200,*,UP,POLY ++S 3000,1300,3000,1700,200,*,UP,POLY ++S 3400,1900,3400,3600,600,n1,DOWN,NDIF ++S 1200,2100,1200,3600,400,*,UP,NDIF ++S 1400,9300,1400,9700,200,*,DOWN,POLY ++S 1000,5700,1000,9100,400,*,UP,PDIF ++S 0,600,5000,600,1200,vss,RIGHT,CALU1 ++S 0,5000,5000,5000,10000,an2_x2,LEFT,TALU8 ++S 0,2200,5000,2200,5200,*,LEFT,PWELL ++S 0,7600,5000,7600,5600,*,LEFT,NWELL ++S 0,9400,5000,9400,1200,vdd,RIGHT,CALU1 ++S 3000,3800,3000,4900,200,*,UP,POLY ++S 2000,6100,3200,6100,600,*,LEFT,ALU1 ++S 4000,5000,4000,7000,400,b,UP,CALU1 ++S 3200,6000,3200,8100,400,*,UP,PDIF ++S 4400,6000,4400,8100,600,*,DOWN,PDIF ++S 2600,5200,2600,5800,200,*,DOWN,POLY ++S 3800,3800,3800,5800,200,*,DOWN,POLY ++S 3800,8300,3800,8700,200,*,DOWN,POLY ++S 2600,8300,2600,8700,200,*,DOWN,POLY ++S 2900,7100,4000,7100,400,*,LEFT,ALU1 ++S 2900,7000,4000,7000,400,*,LEFT,ALU1 ++S 1000,3000,1000,7000,400,z,DOWN,CALU1 ++S 1600,1500,1600,1900,200,*,UP,POLY ++S 2000,7900,2000,9300,400,*,DOWN,ALU1 ++S 4400,7900,4400,9300,400,*,DOWN,ALU1 ++S 1600,3800,1600,4600,200,*,UP,POLY ++S 2000,5700,2000,9100,600,*,DOWN,PDIF ++S 800,6200,800,7000,600,*,UP,PDIF ++V 1800,700,CONT_BODY_P,* ++V 1100,700,CONT_BODY_P,* ++V 3200,9300,CONT_BODY_N,* ++V 3900,9300,CONT_BODY_N,* ++V 4400,2800,CONT_DIF_N,zn ++V 4400,2000,CONT_DIF_N,zn ++V 2300,2100,CONT_DIF_N,* ++V 3000,5100,CONT_POLY,* ++V 1000,2700,CONT_DIF_N,* ++V 3200,6100,CONT_DIF_P,zn ++V 2000,4400,CONT_POLY,zn ++V 1000,3500,CONT_DIF_N,* ++V 2000,8000,CONT_DIF_P,* ++V 2000,9000,CONT_DIF_P,* ++V 4400,8000,CONT_DIF_P,* ++V 4000,5000,CONT_POLY,* ++V 800,6900,CONT_DIF_P,* ++V 800,6100,CONT_DIF_P,* ++EOF +diff --git a/alliance/src/cells/src/msxlib/an2_x2.vbe b/alliance/src/cells/src/msxlib/an2_x2.vbe +new file mode 100644 +index 0000000..e0be85f +--- /dev/null ++++ b/alliance/src/cells/src/msxlib/an2_x2.vbe +@@ -0,0 +1,32 @@ ++ENTITY an2_x2 IS ++GENERIC ( ++ CONSTANT area : NATURAL := 5000; ++ CONSTANT cin_b : NATURAL := 6; ++ CONSTANT cin_a : NATURAL := 6; ++ CONSTANT rdown_b_z : NATURAL := 1200; ++ CONSTANT rdown_a_z : NATURAL := 1200; ++ CONSTANT rup_b_z : NATURAL := 1560; ++ CONSTANT rup_a_z : NATURAL := 1560; ++ CONSTANT tphh_a_z : NATURAL := 68; ++ CONSTANT tphh_b_z : NATURAL := 68; ++ CONSTANT tpll_b_z : NATURAL := 87; ++ CONSTANT tpll_a_z : NATURAL := 96; ++ CONSTANT transistors : NATURAL := 6 ++); ++PORT ( ++ b : in BIT; ++ a : in BIT; ++ z : out BIT; ++ vdd : in BIT; ++ vss : in BIT ++); ++END an2_x2; ++ ++ARCHITECTURE behaviour_data_flow OF an2_x2 IS ++ ++BEGIN ++ ASSERT ((vdd and not (vss)) = '1') ++ REPORT "power supply is missing on an2_x2" ++ SEVERITY WARNING; ++ z <= (b and a) after 1000 ps; ++END; +diff --git a/alliance/src/cells/src/msxlib/an3_x1.ap b/alliance/src/cells/src/msxlib/an3_x1.ap +new file mode 100644 +index 0000000..0d5304a +--- /dev/null ++++ b/alliance/src/cells/src/msxlib/an3_x1.ap +@@ -0,0 +1,110 @@ ++V ALLIANCE : 6 ++H an3_x1,P, 8/ 8/2014,100 ++A 0,0,6000,10000 ++R 2000,3000,ref_ref,z_30 ++R 5000,3000,ref_ref,c_30 ++R 4000,3000,ref_ref,c_30 ++R 4000,6000,ref_ref,b_60 ++R 5000,6000,ref_ref,b_60 ++R 3000,5000,ref_ref,a_50 ++R 3000,6000,ref_ref,a_60 ++R 3000,7000,ref_ref,a_70 ++R 4000,7000,ref_ref,a_70 ++R 5000,7000,ref_ref,a_70 ++R 5000,4000,ref_ref,c_40 ++R 5000,5000,ref_ref,c_50 ++R 4000,5000,ref_ref,b_50 ++R 1000,3000,ref_ref,z_30 ++R 1000,7000,ref_ref,z_70 ++R 1000,4000,ref_ref,z_40 ++R 1000,6000,ref_ref,z_60 ++R 1000,5000,ref_ref,z_50 ++R 4000,4000,ref_ref,b_40 ++S 1100,700,1900,700,600,*,RIGHT,PTIE ++S 2200,700,2200,2100,400,*,UP,ALU1 ++S 1000,3000,1000,7000,400,z,DOWN,CALU1 ++S 2000,3000,2000,3000,400,z,LEFT,CALU1 ++S 3000,5000,3000,7000,400,a,DOWN,CALU1 ++S 4000,3000,4000,3000,400,c,LEFT,CALU1 ++S 5000,3000,5000,5000,400,c,DOWN,CALU1 ++S 5000,2900,5000,5100,400,*,DOWN,ALU1 ++S 3900,3000,5000,3000,400,*,RIGHT,ALU1 ++S 4000,6100,5100,6100,400,*,RIGHT,ALU1 ++S 4000,6000,5100,6000,400,*,RIGHT,ALU1 ++S 4000,4000,4000,6000,400,b,DOWN,CALU1 ++S 4000,3900,4000,6100,400,*,DOWN,ALU1 ++S 5000,6000,5000,6000,400,b,LEFT,CALU1 ++S 3900,2900,5000,2900,400,*,RIGHT,ALU1 ++S 5000,7000,5000,7000,400,a,LEFT,CALU1 ++S 4000,7000,4000,7000,400,a,LEFT,CALU1 ++S 0,600,6000,600,1200,vss,RIGHT,CALU1 ++S 0,5000,6000,5000,10000,an3_x1,LEFT,TALU8 ++S 0,2200,6000,2200,5200,*,LEFT,PWELL ++S 0,7600,6000,7600,5600,*,LEFT,NWELL ++S 0,9400,6000,9400,1200,vdd,RIGHT,CALU1 ++S 2000,8000,5500,8000,400,*,RIGHT,ALU1 ++S 3000,7000,5100,7000,400,*,RIGHT,ALU1 ++S 3000,7100,5100,7100,400,*,RIGHT,ALU1 ++S 3000,2000,5300,2000,400,*,LEFT,ALU1 ++S 3600,6700,3600,8300,200,1b,UP,PTRANS ++S 2400,6700,2400,8300,200,1a,UP,PTRANS ++S 3000,6900,3000,8100,1000,*,DOWN,PDIF ++S 4200,6900,4200,9100,600,*,UP,PDIF ++S 4800,6700,4800,8300,200,1c,UP,PTRANS ++S 5200,6900,5200,8100,400,*,DOWN,PDIF ++S 2400,8300,2400,8700,200,*,DOWN,POLY ++S 3600,8300,3600,8700,200,*,DOWN,POLY ++S 4800,8300,4800,8700,200,*,DOWN,POLY ++S 3400,1900,3400,3100,600,n1,UP,NDIF ++S 3000,1700,3000,3300,200,2a,DOWN,NTRANS ++S 3800,1700,3800,3300,200,2b,DOWN,NTRANS ++S 4200,1900,4200,3100,600,n2,UP,NDIF ++S 4600,1700,4600,3300,200,2c,DOWN,NTRANS ++S 5000,1900,5000,3100,400,*,UP,NDIF ++S 1200,2500,1200,3100,400,*,UP,NDIF ++S 1600,2300,1600,3300,200,2z,DOWN,NTRANS ++S 1600,1900,1600,2300,200,*,DOWN,POLY ++S 3000,1300,3000,1700,200,*,DOWN,POLY ++S 3800,1300,3800,1700,200,*,DOWN,POLY ++S 4600,1300,4600,1700,200,*,DOWN,POLY ++S 2300,1900,2300,3100,800,*,UP,NDIF ++S 3600,6100,3600,6700,200,*,DOWN,POLY ++S 4600,3300,4600,3800,200,*,UP,POLY ++S 4800,3900,4800,6700,200,*,DOWN,POLY ++S 3800,3300,3800,6000,200,*,UP,POLY ++S 2400,5200,2400,6700,200,*,DOWN,POLY ++S 2400,5200,3000,5200,200,*,RIGHT,POLY ++S 3000,3300,3000,5200,200,*,DOWN,POLY ++S 1000,2900,1000,7100,400,*,DOWN,ALU1 ++S 1000,3000,2000,3000,600,*,RIGHT,ALU1 ++S 3000,4900,3000,7000,400,*,DOWN,ALU1 ++S 2000,4000,3000,4000,400,*,RIGHT,ALU1 ++S 2000,4000,2000,8000,400,*,UP,ALU1 ++S 3000,2000,3000,4000,400,*,DOWN,ALU1 ++S 1200,4300,1800,4300,200,*,RIGHT,POLY ++S 1600,3300,1600,4300,200,*,UP,POLY ++S 500,7100,1000,7100,400,*,RIGHT,ALU1 ++S 1200,6000,1200,8000,200,1z,UP,PTRANS ++S 800,6200,800,7800,400,*,UP,PDIF ++S 600,6400,600,7000,600,*,UP,PDIF ++S 1800,6200,1800,9100,600,*,DOWN,PDIF ++S 500,6300,1000,6300,400,*,RIGHT,ALU1 ++S 1200,8000,1200,8400,200,*,DOWN,POLY ++S 1200,4300,1200,6000,200,*,DOWN,POLY ++V 2000,700,CONT_BODY_P,* ++V 1000,700,CONT_BODY_P,* ++V 3000,9300,CONT_BODY_N,* ++V 2200,2000,CONT_DIF_N,* ++V 5400,8000,CONT_DIF_P,zn ++V 3000,8000,CONT_DIF_P,zn ++V 5200,2000,CONT_DIF_N,zn ++V 1800,9000,CONT_DIF_P,* ++V 4200,9000,CONT_DIF_P,* ++V 4000,6000,CONT_POLY,* ++V 5000,3900,CONT_POLY,* ++V 3000,5000,CONT_POLY,* ++V 1000,3000,CONT_DIF_N,* ++V 2000,4100,CONT_POLY,zn ++V 600,7100,CONT_DIF_P,* ++V 600,6300,CONT_DIF_P,* ++EOF +diff --git a/alliance/src/cells/src/msxlib/an3_x1.vbe b/alliance/src/cells/src/msxlib/an3_x1.vbe +new file mode 100644 +index 0000000..0f9f78c +--- /dev/null ++++ b/alliance/src/cells/src/msxlib/an3_x1.vbe +@@ -0,0 +1,38 @@ ++ENTITY an3_x1 IS ++GENERIC ( ++ CONSTANT area : NATURAL := 6000; ++ CONSTANT cin_a : NATURAL := 5; ++ CONSTANT cin_b : NATURAL := 4; ++ CONSTANT cin_c : NATURAL := 4; ++ CONSTANT rdown_a_z : NATURAL := 2310; ++ CONSTANT rdown_b_z : NATURAL := 2300; ++ CONSTANT rdown_c_z : NATURAL := 2290; ++ CONSTANT rup_a_z : NATURAL := 2970; ++ CONSTANT rup_b_z : NATURAL := 2970; ++ CONSTANT rup_c_z : NATURAL := 2970; ++ CONSTANT tphh_c_z : NATURAL := 88; ++ CONSTANT tphh_b_z : NATURAL := 91; ++ CONSTANT tphh_a_z : NATURAL := 93; ++ CONSTANT tpll_a_z : NATURAL := 121; ++ CONSTANT tpll_b_z : NATURAL := 111; ++ CONSTANT tpll_c_z : NATURAL := 100; ++ CONSTANT transistors : NATURAL := 8 ++); ++PORT ( ++ a : in BIT; ++ b : in BIT; ++ c : in BIT; ++ z : out BIT; ++ vdd : in BIT; ++ vss : in BIT ++); ++END an3_x1; ++ ++ARCHITECTURE behaviour_data_flow OF an3_x1 IS ++ ++BEGIN ++ ASSERT ((vdd and not (vss)) = '1') ++ REPORT "power supply is missing on an3_x1" ++ SEVERITY WARNING; ++ z <= ((a and b) and c) after 1100 ps; ++END; +diff --git a/alliance/src/cells/src/msxlib/an3_x2.ap b/alliance/src/cells/src/msxlib/an3_x2.ap +new file mode 100644 +index 0000000..291cb56 +--- /dev/null ++++ b/alliance/src/cells/src/msxlib/an3_x2.ap +@@ -0,0 +1,114 @@ ++V ALLIANCE : 6 ++H an3_x2,P, 8/ 8/2014,100 ++A 0,0,6000,10000 ++R 2000,8000,ref_ref,z_80 ++R 1000,8000,ref_ref,z_80 ++R 4000,4000,ref_ref,a_40 ++R 3000,4000,ref_ref,a_40 ++R 5000,7000,ref_ref,b_70 ++R 5000,3000,ref_ref,c_30 ++R 4000,3000,ref_ref,c_30 ++R 4000,6000,ref_ref,b_60 ++R 5000,6000,ref_ref,b_60 ++R 3000,5000,ref_ref,a_50 ++R 3000,6000,ref_ref,a_60 ++R 5000,4000,ref_ref,c_40 ++R 5000,5000,ref_ref,c_50 ++R 4000,5000,ref_ref,b_50 ++R 1000,3000,ref_ref,z_30 ++R 1000,7000,ref_ref,z_70 ++R 1000,4000,ref_ref,z_40 ++R 1000,6000,ref_ref,z_60 ++R 1000,5000,ref_ref,z_50 ++S 4800,4200,4800,6900,200,*,DOWN,POLY ++S 4800,9300,4800,9700,200,*,DOWN,POLY ++S 5200,7100,5200,9100,400,*,DOWN,PDIF ++S 4800,6900,4800,9300,200,1c,UP,PTRANS ++S 500,6200,1000,6200,400,*,RIGHT,ALU1 ++S 600,6300,600,6900,600,*,UP,PDIF ++S 500,7000,1000,7000,400,*,RIGHT,ALU1 ++S 2000,8000,2000,8000,400,z,LEFT,CALU1 ++S 1000,8000,2000,8000,600,*,RIGHT,ALU1 ++S 1000,2600,1000,8100,400,*,DOWN,ALU1 ++S 1000,3000,1000,8000,400,z,DOWN,CALU1 ++S 3000,8000,5500,8000,400,*,RIGHT,ALU1 ++S 3000,7000,3000,8000,400,*,UP,ALU1 ++S 2000,7000,3000,7000,400,*,RIGHT,ALU1 ++S 2000,3000,2000,7000,400,*,UP,ALU1 ++S 3000,3900,3000,6100,400,*,DOWN,ALU1 ++S 3000,4000,3000,6000,400,a,DOWN,CALU1 ++S 3000,3900,4100,3900,400,*,RIGHT,ALU1 ++S 3000,4000,4100,4000,400,*,RIGHT,ALU1 ++S 4000,4000,4000,4000,400,a,LEFT,CALU1 ++S 3000,2000,3000,3000,400,*,DOWN,ALU1 ++S 2000,3000,3000,3000,400,*,RIGHT,ALU1 ++S 4000,5000,4000,6000,400,b,DOWN,CALU1 ++S 4000,4900,4000,6100,400,*,DOWN,ALU1 ++S 5000,6000,5000,7000,600,*,UP,ALU1 ++S 5000,6000,5000,7000,400,b,UP,CALU1 ++S 1200,9300,1200,9700,200,*,DOWN,POLY ++S 3600,8400,3600,8800,200,*,DOWN,POLY ++S 2400,8400,2400,8800,200,*,DOWN,POLY ++S 3600,5500,3600,6000,200,*,DOWN,POLY ++S 2800,4600,2800,5600,200,*,DOWN,POLY ++S 2400,5600,2800,5600,200,*,RIGHT,POLY ++S 4200,6200,4200,9100,600,*,UP,PDIF ++S 3000,6200,3000,8200,1000,*,DOWN,PDIF ++S 2400,6000,2400,8400,200,1a,UP,PTRANS ++S 3600,6000,3600,8400,200,1b,UP,PTRANS ++S 2200,700,2200,2100,400,*,UP,ALU1 ++S 3000,3800,3000,4600,200,*,UP,POLY ++S 4600,3800,4600,4300,200,*,UP,POLY ++S 4000,3000,4000,3000,400,c,LEFT,CALU1 ++S 5000,3000,5000,5000,400,c,DOWN,CALU1 ++S 5000,2900,5000,5100,400,*,DOWN,ALU1 ++S 3900,3000,5000,3000,400,*,RIGHT,ALU1 ++S 3800,4100,3800,5300,200,*,UP,POLY ++S 4000,6100,5100,6100,400,*,RIGHT,ALU1 ++S 4000,6000,5100,6000,400,*,RIGHT,ALU1 ++S 3900,2900,5000,2900,400,*,RIGHT,ALU1 ++S 1000,2800,1000,3400,600,*,DOWN,NDIF ++S 1600,1900,1600,3800,200,2z,DOWN,NTRANS ++S 3000,1400,3000,3800,200,2a,DOWN,NTRANS ++S 3800,1400,3800,3800,200,2b,DOWN,NTRANS ++S 4600,1400,4600,3800,200,2c,DOWN,NTRANS ++S 1200,5500,1200,9300,200,1z,UP,PTRANS ++S 1200,4600,1800,4600,200,*,RIGHT,POLY ++S 0,600,6000,600,1200,vss,RIGHT,CALU1 ++S 0,5000,6000,5000,10000,an3_x2,LEFT,TALU8 ++S 0,2200,6000,2200,5200,*,LEFT,PWELL ++S 0,7600,6000,7600,5600,*,LEFT,NWELL ++S 0,9400,6000,9400,1200,vdd,RIGHT,CALU1 ++S 1800,5700,1800,9100,600,*,DOWN,PDIF ++S 800,5700,800,9100,400,*,UP,PDIF ++S 3000,1000,3000,1400,200,*,DOWN,POLY ++S 3800,1000,3800,1400,200,*,DOWN,POLY ++S 4600,1000,4600,1400,200,*,DOWN,POLY ++S 5000,1600,5000,3600,400,*,UP,NDIF ++S 1600,1500,1600,1900,200,*,DOWN,POLY ++S 1200,2100,1200,3600,400,*,UP,NDIF ++S 2300,900,2300,3600,800,*,UP,NDIF ++S 1200,4600,1200,5500,200,*,DOWN,POLY ++S 1600,3800,1600,4600,200,*,UP,POLY ++S 3000,2000,5300,2000,400,*,LEFT,ALU1 ++S 3400,1600,3400,3600,600,n1,UP,NDIF ++S 4200,1600,4200,3600,600,n2,UP,NDIF ++V 1000,700,CONT_BODY_P,* ++V 3000,9300,CONT_BODY_N,* ++V 5400,8000,CONT_DIF_P,zn ++V 600,6200,CONT_DIF_P,* ++V 600,7000,CONT_DIF_P,* ++V 3000,7900,CONT_DIF_P,zn ++V 3000,7100,CONT_DIF_P,zn ++V 4000,5400,CONT_POLY,* ++V 3000,4700,CONT_POLY,* ++V 2200,1000,CONT_DIF_N,* ++V 2200,2000,CONT_DIF_N,* ++V 5000,4400,CONT_POLY,* ++V 1000,2700,CONT_DIF_N,* ++V 2000,4400,CONT_POLY,zn ++V 5200,2000,CONT_DIF_N,zn ++V 1800,9000,CONT_DIF_P,* ++V 1000,3500,CONT_DIF_N,* ++V 4200,9000,CONT_DIF_P,* ++EOF +diff --git a/alliance/src/cells/src/msxlib/an3_x2.vbe b/alliance/src/cells/src/msxlib/an3_x2.vbe +new file mode 100644 +index 0000000..2fb10d6 +--- /dev/null ++++ b/alliance/src/cells/src/msxlib/an3_x2.vbe +@@ -0,0 +1,38 @@ ++ENTITY an3_x2 IS ++GENERIC ( ++ CONSTANT area : NATURAL := 6000; ++ CONSTANT cin_a : NATURAL := 6; ++ CONSTANT cin_b : NATURAL := 6; ++ CONSTANT cin_c : NATURAL := 6; ++ CONSTANT rdown_a_z : NATURAL := 1210; ++ CONSTANT rdown_b_z : NATURAL := 1210; ++ CONSTANT rdown_c_z : NATURAL := 1210; ++ CONSTANT rup_a_z : NATURAL := 1560; ++ CONSTANT rup_b_z : NATURAL := 1560; ++ CONSTANT rup_c_z : NATURAL := 1560; ++ CONSTANT tphh_c_z : NATURAL := 86; ++ CONSTANT tphh_b_z : NATURAL := 89; ++ CONSTANT tphh_a_z : NATURAL := 91; ++ CONSTANT tpll_a_z : NATURAL := 119; ++ CONSTANT tpll_b_z : NATURAL := 109; ++ CONSTANT tpll_c_z : NATURAL := 98; ++ CONSTANT transistors : NATURAL := 8 ++); ++PORT ( ++ a : in BIT; ++ b : in BIT; ++ c : in BIT; ++ z : out BIT; ++ vdd : in BIT; ++ vss : in BIT ++); ++END an3_x2; ++ ++ARCHITECTURE behaviour_data_flow OF an3_x2 IS ++ ++BEGIN ++ ASSERT ((vdd and not (vss)) = '1') ++ REPORT "power supply is missing on an3_x2" ++ SEVERITY WARNING; ++ z <= ((a and b) and c) after 1100 ps; ++END; +diff --git a/alliance/src/cells/src/msxlib/an4_x1.ap b/alliance/src/cells/src/msxlib/an4_x1.ap +new file mode 100644 +index 0000000..73b6d84 +--- /dev/null ++++ b/alliance/src/cells/src/msxlib/an4_x1.ap +@@ -0,0 +1,132 @@ ++V ALLIANCE : 6 ++H an4_x1,P, 8/ 8/2014,100 ++A 0,0,7000,10000 ++R 2000,3000,ref_ref,z_30 ++R 4000,5000,ref_ref,b_50 ++R 1000,3000,ref_ref,z_30 ++R 1000,7000,ref_ref,z_70 ++R 1000,4000,ref_ref,z_40 ++R 1000,6000,ref_ref,z_60 ++R 1000,5000,ref_ref,z_50 ++R 4000,4000,ref_ref,b_40 ++R 4000,3000,ref_ref,b_30 ++R 5000,3000,ref_ref,b_30 ++R 5000,7000,ref_ref,d_70 ++R 6000,7000,ref_ref,d_70 ++R 6000,6000,ref_ref,d_60 ++R 6000,5000,ref_ref,d_50 ++R 4000,6000,ref_ref,c_60 ++R 5000,6000,ref_ref,c_60 ++R 5000,5000,ref_ref,c_50 ++R 5000,4000,ref_ref,c_40 ++R 4000,7000,ref_ref,a_70 ++R 3000,7000,ref_ref,a_70 ++R 3000,6000,ref_ref,a_60 ++R 3000,5000,ref_ref,a_50 ++R 1000,8000,ref_ref,z_80 ++S 1100,700,1900,700,600,*,RIGHT,PTIE ++S 4000,2900,4000,5200,400,*,DOWN,ALU1 ++S 3100,2000,6000,2000,400,*,LEFT,ALU1 ++S 2000,3000,2000,3000,400,z,LEFT,CALU1 ++S 6000,8300,6000,8600,200,*,DOWN,POLY ++S 2000,8000,5500,8000,400,*,RIGHT,ALU1 ++S 0,9400,7000,9400,1200,vdd,RIGHT,CALU1 ++S 0,600,7000,600,1200,vss,RIGHT,CALU1 ++S 0,5000,7000,5000,10000,an4_x1,LEFT,TALU8 ++S 0,2200,7000,2200,5200,*,LEFT,PWELL ++S 0,7600,7000,7600,5600,*,LEFT,NWELL ++S 4800,8300,4800,8700,200,*,DOWN,POLY ++S 500,6600,1000,6600,400,*,RIGHT,ALU1 ++S 3600,8300,3600,8700,200,*,DOWN,POLY ++S 2400,8300,2400,8700,200,*,DOWN,POLY ++S 5000,7000,5000,7000,400,d,LEFT,CALU1 ++S 5000,3000,5000,3000,400,b,LEFT,CALU1 ++S 4000,6000,4000,6000,400,c,LEFT,CALU1 ++S 4000,7000,4000,7000,400,a,LEFT,CALU1 ++S 4000,3000,4000,5000,400,b,DOWN,CALU1 ++S 4000,2900,5100,2900,400,*,RIGHT,ALU1 ++S 4000,3000,5100,3000,400,*,RIGHT,ALU1 ++S 5000,3900,5000,6100,400,*,DOWN,ALU1 ++S 3900,6000,5000,6000,400,*,RIGHT,ALU1 ++S 3900,6100,5000,6100,400,*,RIGHT,ALU1 ++S 3000,7000,4100,7000,400,*,RIGHT,ALU1 ++S 3000,7100,4100,7100,400,*,RIGHT,ALU1 ++S 6000,5000,6000,7000,400,d,UP,CALU1 ++S 6000,4900,6000,7000,400,*,UP,ALU1 ++S 4900,7000,6000,7000,400,*,LEFT,ALU1 ++S 4900,7100,6000,7100,400,*,LEFT,ALU1 ++S 5000,4000,5000,6000,400,c,DOWN,CALU1 ++S 3000,4900,3000,7000,400,*,DOWN,ALU1 ++S 3000,5000,3000,7000,400,a,DOWN,CALU1 ++S 3600,6700,3600,8300,200,1b,UP,PTRANS ++S 3000,6900,3000,8100,1000,*,DOWN,PDIF ++S 2400,6700,2400,8300,200,1a,UP,PTRANS ++S 5400,6900,5400,8100,600,*,DOWN,PDIF ++S 6000,6700,6000,8300,200,1d,UP,PTRANS ++S 4800,6700,4800,8300,200,1c,UP,PTRANS ++S 4200,6900,4200,9100,600,*,UP,PDIF ++S 6500,6900,6500,9300,400,*,UP,PDIF ++S 6000,4800,6000,6700,200,*,DOWN,POLY ++S 1800,6500,1800,9100,600,*,DOWN,PDIF ++S 1200,6300,1200,8300,200,1z,UP,PTRANS ++S 800,6500,800,8100,400,*,UP,PDIF ++S 1200,8300,1200,8700,200,*,DOWN,POLY ++S 1000,3000,2000,3000,600,*,RIGHT,ALU1 ++S 2300,1900,2300,3400,800,*,UP,NDIF ++S 2300,700,2300,2100,400,*,DOWN,ALU1 ++S 1600,2600,1600,3600,200,2z,DOWN,NTRANS ++S 1200,2800,1200,3400,400,*,UP,NDIF ++S 1600,2200,1600,2600,200,*,DOWN,POLY ++S 3000,1300,3000,1700,200,*,DOWN,POLY ++S 3800,1300,3800,1700,200,*,DOWN,POLY ++S 4600,1300,4600,1700,200,*,DOWN,POLY ++S 5400,1300,5400,1700,200,*,DOWN,POLY ++S 3000,1700,3000,3600,200,2a,DOWN,NTRANS ++S 3400,1900,3400,3400,600,n1,UP,NDIF ++S 3800,1700,3800,3600,200,2b,DOWN,NTRANS ++S 5000,1900,5000,3400,600,n3,UP,NDIF ++S 4600,1700,4600,3600,200,2c,DOWN,NTRANS ++S 5400,1700,5400,3600,200,2d,DOWN,NTRANS ++S 5800,1900,5800,3400,400,*,UP,NDIF ++S 4200,1900,4200,3400,600,n2,UP,NDIF ++S 3800,3600,3800,4800,200,*,UP,POLY ++S 6000,2100,6000,2700,600,*,UP,NDIF ++S 6000,2000,6000,2800,600,*,UP,ALU1 ++S 5400,4000,5800,4000,200,*,RIGHT,POLY ++S 5800,4000,5800,4800,200,*,UP,POLY ++S 4800,4000,4800,6700,200,*,DOWN,POLY ++S 4600,3600,4600,4100,200,*,UP,POLY ++S 3600,4700,3600,6700,200,*,DOWN,POLY ++S 2000,4100,3100,4100,400,*,RIGHT,ALU1 ++S 2000,4100,2000,8000,400,*,UP,ALU1 ++S 3100,2000,3100,4100,400,*,DOWN,ALU1 ++S 1200,4400,1600,4400,200,*,RIGHT,POLY ++S 1200,4400,1200,6300,200,*,DOWN,POLY ++S 1600,3600,1600,4400,200,*,UP,POLY ++S 2400,5800,2400,6700,200,*,DOWN,POLY ++S 3000,3600,3000,5900,200,*,UP,POLY ++S 2800,6000,3000,6000,600,*,RIGHT,ALU1 ++S 600,6700,600,7300,600,*,DOWN,PDIF ++S 500,7400,1000,7400,400,*,RIGHT,ALU1 ++S 1000,3000,1000,8000,400,z,DOWN,CALU1 ++S 1000,2900,1000,8100,400,*,DOWN,ALU1 ++V 2000,700,CONT_BODY_P,* ++V 1000,700,CONT_BODY_P,* ++V 3000,9300,CONT_BODY_N,* ++V 6400,9200,CONT_DIF_P,* ++V 5400,8000,CONT_DIF_P,zn ++V 4200,9000,CONT_DIF_P,* ++V 3000,8000,CONT_DIF_P,zn ++V 1800,9000,CONT_DIF_P,* ++V 600,6600,CONT_DIF_P,* ++V 6000,5000,CONT_POLY,* ++V 2300,2000,CONT_DIF_N,* ++V 1000,3300,CONT_DIF_N,* ++V 6000,2000,CONT_DIF_N,zn ++V 6000,2800,CONT_DIF_N,zn ++V 4000,4900,CONT_POLY,* ++V 5000,6000,CONT_POLY,* ++V 2000,4200,CONT_POLY,zn ++V 2800,6000,CONT_POLY,* ++V 600,7400,CONT_DIF_P,* ++EOF +diff --git a/alliance/src/cells/src/msxlib/an4_x1.vbe b/alliance/src/cells/src/msxlib/an4_x1.vbe +new file mode 100644 +index 0000000..bdfe74f +--- /dev/null ++++ b/alliance/src/cells/src/msxlib/an4_x1.vbe +@@ -0,0 +1,44 @@ ++ENTITY an4_x1 IS ++GENERIC ( ++ CONSTANT area : NATURAL := 7000; ++ CONSTANT cin_a : NATURAL := 5; ++ CONSTANT cin_b : NATURAL := 5; ++ CONSTANT cin_c : NATURAL := 5; ++ CONSTANT cin_d : NATURAL := 4; ++ CONSTANT rdown_a_z : NATURAL := 2330; ++ CONSTANT rdown_b_z : NATURAL := 2320; ++ CONSTANT rdown_c_z : NATURAL := 2310; ++ CONSTANT rdown_d_z : NATURAL := 2300; ++ CONSTANT rup_a_z : NATURAL := 2980; ++ CONSTANT rup_b_z : NATURAL := 2980; ++ CONSTANT rup_c_z : NATURAL := 2980; ++ CONSTANT rup_d_z : NATURAL := 2980; ++ CONSTANT tphh_a_z : NATURAL := 115; ++ CONSTANT tphh_b_z : NATURAL := 112; ++ CONSTANT tpll_d_z : NATURAL := 107; ++ CONSTANT tphh_c_z : NATURAL := 106; ++ CONSTANT tpll_c_z : NATURAL := 121; ++ CONSTANT tphh_d_z : NATURAL := 98; ++ CONSTANT tpll_b_z : NATURAL := 133; ++ CONSTANT tpll_a_z : NATURAL := 142; ++ CONSTANT transistors : NATURAL := 10 ++); ++PORT ( ++ a : in BIT; ++ b : in BIT; ++ c : in BIT; ++ d : in BIT; ++ z : out BIT; ++ vdd : in BIT; ++ vss : in BIT ++); ++END an4_x1; ++ ++ARCHITECTURE behaviour_data_flow OF an4_x1 IS ++ ++BEGIN ++ ASSERT ((vdd and not (vss)) = '1') ++ REPORT "power supply is missing on an4_x1" ++ SEVERITY WARNING; ++ z <= (((a and b) and c) and d) after 1200 ps; ++END; +diff --git a/alliance/src/cells/src/msxlib/an4_x2.ap b/alliance/src/cells/src/msxlib/an4_x2.ap +new file mode 100644 +index 0000000..fda7322 +--- /dev/null ++++ b/alliance/src/cells/src/msxlib/an4_x2.ap +@@ -0,0 +1,133 @@ ++V ALLIANCE : 6 ++H an4_x2,P, 8/ 8/2014,100 ++A 0,0,7000,10000 ++R 2000,3000,ref_ref,z_30 ++R 4000,5000,ref_ref,b_50 ++R 1000,3000,ref_ref,z_30 ++R 1000,7000,ref_ref,z_70 ++R 1000,4000,ref_ref,z_40 ++R 1000,6000,ref_ref,z_60 ++R 1000,5000,ref_ref,z_50 ++R 4000,4000,ref_ref,b_40 ++R 4000,3000,ref_ref,b_30 ++R 5000,3000,ref_ref,b_30 ++R 5000,7000,ref_ref,d_70 ++R 6000,7000,ref_ref,d_70 ++R 6000,6000,ref_ref,d_60 ++R 6000,5000,ref_ref,d_50 ++R 4000,6000,ref_ref,c_60 ++R 5000,6000,ref_ref,c_60 ++R 5000,5000,ref_ref,c_50 ++R 5000,4000,ref_ref,c_40 ++R 4000,7000,ref_ref,a_70 ++R 3000,7000,ref_ref,a_70 ++R 3000,6000,ref_ref,a_60 ++R 3000,5000,ref_ref,a_50 ++R 1000,2000,ref_ref,z_20 ++S 3800,3800,3800,5100,200,*,UP,POLY ++S 4600,3800,4600,4300,200,*,UP,POLY ++S 4000,2900,4000,5200,400,*,DOWN,ALU1 ++S 3600,4900,3600,5900,200,*,DOWN,POLY ++S 2300,700,2300,2200,400,*,DOWN,ALU1 ++S 2300,1200,2300,3600,800,*,UP,NDIF ++S 2000,4000,3100,4000,400,*,RIGHT,ALU1 ++S 3100,2000,6000,2000,400,*,LEFT,ALU1 ++S 3100,2000,3100,4000,400,*,DOWN,ALU1 ++S 1000,3000,2100,3000,400,*,RIGHT,ALU1 ++S 2000,3000,2000,3000,400,z,LEFT,CALU1 ++S 6000,2300,6000,2900,600,*,UP,NDIF ++S 6000,2000,6000,3100,400,*,UP,ALU1 ++S 6000,8300,6000,8600,200,*,DOWN,POLY ++S 6500,6100,6500,9300,400,*,UP,PDIF ++S 2000,8000,5500,8000,400,*,RIGHT,ALU1 ++S 0,9400,7000,9400,1200,vdd,RIGHT,CALU1 ++S 0,600,7000,600,1200,vss,RIGHT,CALU1 ++S 0,5000,7000,5000,10000,an4_x2,LEFT,TALU8 ++S 0,2200,7000,2200,5200,*,LEFT,PWELL ++S 0,7600,7000,7600,5600,*,LEFT,NWELL ++S 6000,4800,6000,5900,200,*,DOWN,POLY ++S 4800,4200,4800,5900,200,*,DOWN,POLY ++S 4800,8300,4800,8700,200,*,DOWN,POLY ++S 5400,6100,5400,8100,600,*,DOWN,PDIF ++S 6000,5900,6000,8300,200,1d,UP,PTRANS ++S 4800,5900,4800,8300,200,1c,UP,PTRANS ++S 4200,6100,4200,9100,600,*,UP,PDIF ++S 500,6600,1000,6600,400,*,RIGHT,ALU1 ++S 500,5800,1000,5800,400,*,RIGHT,ALU1 ++S 2900,4900,2900,5200,600,*,UP,ALU1 ++S 2400,5200,2400,5900,200,*,DOWN,POLY ++S 1800,4400,2000,4400,600,*,RIGHT,ALU1 ++S 1200,4600,1600,4600,200,*,RIGHT,POLY ++S 1200,4600,1200,5500,200,*,DOWN,POLY ++S 3600,8300,3600,8700,200,*,DOWN,POLY ++S 2400,8300,2400,8700,200,*,DOWN,POLY ++S 3600,5900,3600,8300,200,1b,UP,PTRANS ++S 2400,5900,2400,8300,200,1a,UP,PTRANS ++S 3000,6100,3000,8100,1000,*,DOWN,PDIF ++S 1800,5700,1800,9100,600,*,DOWN,PDIF ++S 1200,9300,1200,9700,200,*,DOWN,POLY ++S 600,5900,600,6700,600,*,UP,PDIF ++S 1200,5500,1200,9300,200,1z,UP,PTRANS ++S 800,5700,800,9100,400,*,UP,PDIF ++S 5000,7000,5000,7000,400,d,LEFT,CALU1 ++S 5000,3000,5000,3000,400,b,LEFT,CALU1 ++S 4000,6000,4000,6000,400,c,LEFT,CALU1 ++S 4000,7000,4000,7000,400,a,LEFT,CALU1 ++S 1000,2800,1000,3400,600,*,DOWN,NDIF ++S 5400,600,5400,1000,200,*,DOWN,POLY ++S 4600,600,4600,1000,200,*,DOWN,POLY ++S 3800,600,3800,1000,200,*,DOWN,POLY ++S 3000,600,3000,1000,200,*,DOWN,POLY ++S 5800,1200,5800,3600,400,*,UP,NDIF ++S 5400,1000,5400,3800,200,2d,DOWN,NTRANS ++S 5000,1200,5000,3600,600,n3,UP,NDIF ++S 4600,1000,4600,3800,200,2c,DOWN,NTRANS ++S 4200,1200,4200,3600,600,n2,UP,NDIF ++S 3000,1000,3000,3800,200,2a,DOWN,NTRANS ++S 3800,1000,3800,3800,200,2b,DOWN,NTRANS ++S 3400,1200,3400,3600,600,n1,UP,NDIF ++S 4000,3000,4000,5000,400,b,DOWN,CALU1 ++S 4000,2900,5100,2900,400,*,RIGHT,ALU1 ++S 4000,3000,5100,3000,400,*,RIGHT,ALU1 ++S 5000,3900,5000,6100,400,*,DOWN,ALU1 ++S 3900,6000,5000,6000,400,*,RIGHT,ALU1 ++S 3900,6100,5000,6100,400,*,RIGHT,ALU1 ++S 1600,1500,1600,1900,200,*,DOWN,POLY ++S 1200,2100,1200,3600,400,*,UP,NDIF ++S 3000,3800,3000,4900,200,*,UP,POLY ++S 5400,4200,5800,4200,200,*,RIGHT,POLY ++S 5800,4200,5800,4800,200,*,UP,POLY ++S 3000,7000,4100,7000,400,*,RIGHT,ALU1 ++S 3000,7100,4100,7100,400,*,RIGHT,ALU1 ++S 6000,5000,6000,7000,400,d,UP,CALU1 ++S 6000,4900,6000,7000,400,*,UP,ALU1 ++S 4900,7000,6000,7000,400,*,LEFT,ALU1 ++S 4900,7100,6000,7100,400,*,LEFT,ALU1 ++S 5000,4000,5000,6000,400,c,DOWN,CALU1 ++S 3000,4900,3000,7000,400,*,DOWN,ALU1 ++S 3000,5000,3000,7000,400,a,DOWN,CALU1 ++S 2000,4000,2000,8000,400,*,UP,ALU1 ++S 1600,1900,1600,3800,200,2z,DOWN,NTRANS ++S 1000,2000,1000,7000,400,z,DOWN,CALU1 ++S 1000,1900,1000,7100,400,*,DOWN,ALU1 ++V 1000,700,CONT_BODY_P,* ++V 3000,9300,CONT_BODY_N,* ++V 5000,5100,CONT_POLY,* ++V 4000,5100,CONT_POLY,* ++V 2300,1300,CONT_DIF_N,* ++V 2300,2100,CONT_DIF_N,* ++V 6000,2200,CONT_DIF_N,zn ++V 6000,3000,CONT_DIF_N,zn ++V 6400,9200,CONT_DIF_P,* ++V 5400,8000,CONT_DIF_P,zn ++V 4200,9000,CONT_DIF_P,* ++V 2800,5100,CONT_POLY,* ++V 1800,4400,CONT_POLY,zn ++V 3000,8000,CONT_DIF_P,zn ++V 1800,9000,CONT_DIF_P,* ++V 600,6600,CONT_DIF_P,* ++V 600,5800,CONT_DIF_P,* ++V 1000,2700,CONT_DIF_N,* ++V 1000,3500,CONT_DIF_N,* ++V 6000,5000,CONT_POLY,* ++EOF +diff --git a/alliance/src/cells/src/msxlib/an4_x2.vbe b/alliance/src/cells/src/msxlib/an4_x2.vbe +new file mode 100644 +index 0000000..ac82e4f +--- /dev/null ++++ b/alliance/src/cells/src/msxlib/an4_x2.vbe +@@ -0,0 +1,44 @@ ++ENTITY an4_x2 IS ++GENERIC ( ++ CONSTANT area : NATURAL := 7000; ++ CONSTANT cin_a : NATURAL := 7; ++ CONSTANT cin_b : NATURAL := 6; ++ CONSTANT cin_c : NATURAL := 6; ++ CONSTANT cin_d : NATURAL := 6; ++ CONSTANT rdown_a_z : NATURAL := 1220; ++ CONSTANT rdown_b_z : NATURAL := 1220; ++ CONSTANT rdown_c_z : NATURAL := 1210; ++ CONSTANT rdown_d_z : NATURAL := 1210; ++ CONSTANT rup_a_z : NATURAL := 1570; ++ CONSTANT rup_b_z : NATURAL := 1570; ++ CONSTANT rup_c_z : NATURAL := 1570; ++ CONSTANT rup_d_z : NATURAL := 1570; ++ CONSTANT tphh_a_z : NATURAL := 112; ++ CONSTANT tphh_b_z : NATURAL := 110; ++ CONSTANT tpll_d_z : NATURAL := 105; ++ CONSTANT tphh_c_z : NATURAL := 104; ++ CONSTANT tpll_c_z : NATURAL := 118; ++ CONSTANT tphh_d_z : NATURAL := 97; ++ CONSTANT tpll_b_z : NATURAL := 130; ++ CONSTANT tpll_a_z : NATURAL := 139; ++ CONSTANT transistors : NATURAL := 10 ++); ++PORT ( ++ a : in BIT; ++ b : in BIT; ++ c : in BIT; ++ d : in BIT; ++ z : out BIT; ++ vdd : in BIT; ++ vss : in BIT ++); ++END an4_x2; ++ ++ARCHITECTURE behaviour_data_flow OF an4_x2 IS ++ ++BEGIN ++ ASSERT ((vdd and not (vss)) = '1') ++ REPORT "power supply is missing on an4_x2" ++ SEVERITY WARNING; ++ z <= (((a and b) and c) and d) after 1200 ps; ++END; +diff --git a/alliance/src/cells/src/msxlib/an4_x3.ap b/alliance/src/cells/src/msxlib/an4_x3.ap +new file mode 100644 +index 0000000..d1daacf +--- /dev/null ++++ b/alliance/src/cells/src/msxlib/an4_x3.ap +@@ -0,0 +1,137 @@ ++V ALLIANCE : 6 ++H an4_x3,P, 8/ 8/2014,100 ++A 0,0,9000,10000 ++R 8000,5000,ref_ref,d_50 ++R 8000,7000,ref_ref,d_70 ++R 8000,6000,ref_ref,d_60 ++R 1000,7000,ref_ref,z_70 ++R 6000,6000,ref_ref,d_60 ++R 7000,5000,ref_ref,d_50 ++R 6000,5000,ref_ref,c_50 ++R 6000,6000,ref_ref,c_60 ++R 5000,6000,ref_ref,c_60 ++R 5000,7000,ref_ref,a_70 ++R 4000,7000,ref_ref,a_70 ++R 4000,6000,ref_ref,a_60 ++R 6000,3000,ref_ref,b_30 ++R 6000,4000,ref_ref,c_40 ++R 5000,3000,ref_ref,b_30 ++R 5000,4000,ref_ref,b_40 ++R 5000,5000,ref_ref,b_50 ++R 4000,5000,ref_ref,a_50 ++R 2000,7000,ref_ref,z_70 ++R 2000,8000,ref_ref,z_80 ++R 2000,3000,ref_ref,z_30 ++R 2000,4000,ref_ref,z_40 ++R 2000,5000,ref_ref,z_50 ++R 2000,6000,ref_ref,z_60 ++S 8000,4900,8000,7100,400,*,UP,ALU1 ++S 3000,8000,6600,8000,400,*,RIGHT,ALU1 ++S 6600,6900,6600,8000,400,*,DOWN,ALU1 ++S 6900,5000,8000,5000,600,*,LEFT,ALU1 ++S 7000,5000,7000,5000,400,d,LEFT,CALU1 ++S 8000,5000,8000,7000,400,d,UP,CALU1 ++S 7800,7900,7800,9300,400,*,DOWN,ALU1 ++S 1200,9300,1200,9700,200,*,DOWN,POLY ++S 7200,2300,7200,2900,600,*,UP,NDIF ++S 0,600,9000,600,1200,vss,RIGHT,CALU1 ++S 0,9400,9000,9400,1200,vdd,RIGHT,CALU1 ++S 0,5000,9000,5000,10000,an4_x3,LEFT,TALU8 ++S 0,2200,9000,2200,5200,*,LEFT,PWELL ++S 0,7600,9000,7600,5600,*,LEFT,NWELL ++S 6000,4000,6000,6000,400,c,DOWN,CALU1 ++S 6000,3900,6000,6100,400,*,DOWN,ALU1 ++S 4900,6000,6000,6000,400,*,RIGHT,ALU1 ++S 4900,6100,6000,6100,400,*,RIGHT,ALU1 ++S 5000,6000,5000,6000,400,c,LEFT,CALU1 ++S 4000,7000,5100,7000,400,*,RIGHT,ALU1 ++S 4000,7100,5100,7100,400,*,RIGHT,ALU1 ++S 5000,7000,5000,7000,400,a,LEFT,CALU1 ++S 4000,4900,4000,7000,400,*,DOWN,ALU1 ++S 4000,5000,4000,7000,400,a,DOWN,CALU1 ++S 7200,2000,7200,3100,400,*,UP,ALU1 ++S 5000,3000,6100,3000,400,*,RIGHT,ALU1 ++S 6000,3000,6000,3000,400,b,LEFT,CALU1 ++S 5000,2900,6100,2900,400,*,RIGHT,ALU1 ++S 5000,3000,5000,5000,400,b,DOWN,CALU1 ++S 5400,1200,5400,3700,600,n2,UP,NDIF ++S 5800,3900,5800,6000,200,*,UP,POLY ++S 5000,3900,5000,5100,200,*,UP,POLY ++S 1200,6700,1200,9300,200,1z,UP,PTRANS ++S 1800,6900,1800,9100,600,*,DOWN,PDIF ++S 4800,6400,4800,9300,200,1b,UP,PTRANS ++S 4200,6600,4200,9100,1000,*,DOWN,PDIF ++S 3600,6400,3600,9300,200,1a,UP,PTRANS ++S 3000,6600,3000,9100,600,*,DOWN,PDIF ++S 5400,6600,5400,9100,600,*,UP,PDIF ++S 6000,6400,6000,9300,200,1c,UP,PTRANS ++S 7200,6400,7200,9300,200,1d,UP,PTRANS ++S 6600,6600,6600,9100,600,*,DOWN,PDIF ++S 4200,3900,4200,5800,200,*,UP,POLY ++S 6600,3900,6600,4900,200,*,UP,POLY ++S 5000,2900,5000,5100,400,*,DOWN,ALU1 ++S 7200,4800,7200,6400,200,*,DOWN,POLY ++S 4800,4900,4800,6400,200,*,DOWN,POLY ++S 3600,5600,3600,6400,200,*,DOWN,POLY ++S 1000,7000,1800,7000,600,*,RIGHT,ALU1 ++S 1900,6900,1900,8100,600,*,DOWN,ALU1 ++S 1200,6300,2400,6300,200,*,RIGHT,POLY ++S 2400,6700,2400,9300,200,2z,UP,PTRANS ++S 600,6900,600,9100,600,*,DOWN,PDIF ++S 600,7900,600,9300,400,*,UP,ALU1 ++S 7900,6600,7900,9100,600,*,DOWN,PDIF ++S 4000,2000,4000,4000,400,*,UP,ALU1 ++S 3000,4000,4000,4000,400,*,LEFT,ALU1 ++S 3000,4000,3000,8000,400,*,DOWN,ALU1 ++S 4000,2000,7200,2000,400,*,LEFT,ALU1 ++S 3200,700,3200,3100,400,*,DOWN,ALU1 ++S 2600,1300,2600,3900,200,3z,DOWN,NTRANS ++S 2600,3900,2600,5000,200,*,UP,POLY ++S 2400,4600,2400,6700,200,*,DOWN,POLY ++S 2200,1500,2200,3700,400,*,UP,NDIF ++S 2000,2900,2000,3500,600,*,DOWN,NDIF ++S 2000,3000,2000,8000,400,z,UP,CALU1 ++S 2000,2700,2000,8100,400,*,DOWN,ALU1 ++S 1000,7000,1000,7000,400,z,LEFT,CALU1 ++S 2400,9300,2400,9700,200,*,UP,POLY ++S 3600,9300,3600,9700,200,*,UP,POLY ++S 4800,9300,4800,9700,200,*,UP,POLY ++S 6000,9300,6000,9700,200,*,UP,POLY ++S 7200,9300,7200,9700,200,*,UP,POLY ++S 6200,800,6200,3700,600,n3,UP,NDIF ++S 5800,600,5800,3900,200,2c,DOWN,NTRANS ++S 6600,600,6600,3900,200,2d,DOWN,NTRANS ++S 4600,800,4600,3700,600,n1,UP,NDIF ++S 4200,600,4200,3900,200,2a,DOWN,NTRANS ++S 5000,600,5000,3900,200,2b,DOWN,NTRANS ++S 7000,800,7000,3700,400,*,UP,NDIF ++S 3300,800,3300,3700,800,*,UP,NDIF ++S 4200,300,4200,600,200,*,DOWN,POLY ++S 5000,300,5000,600,200,*,DOWN,POLY ++S 5800,300,5800,600,200,*,DOWN,POLY ++S 6600,300,6600,600,200,*,DOWN,POLY ++S 2600,1000,2600,1300,200,*,DOWN,POLY ++V 1000,700,CONT_BODY_P,* ++V 6600,7800,CONT_DIF_P,zn ++V 6600,7000,CONT_DIF_P,zn ++V 7800,8000,CONT_DIF_P,* ++V 4200,8000,CONT_DIF_P,zn ++V 7000,5000,CONT_POLY,* ++V 7200,3000,CONT_DIF_N,zn ++V 7200,2200,CONT_DIF_N,zn ++V 5400,9000,CONT_DIF_P,* ++V 3000,9000,CONT_DIF_P,* ++V 600,9000,CONT_DIF_P,* ++V 7800,9000,CONT_DIF_P,* ++V 3000,4800,CONT_POLY,zn ++V 1800,7000,CONT_DIF_P,* ++V 1800,8000,CONT_DIF_P,* ++V 4000,5800,CONT_POLY,* ++V 6000,5800,CONT_POLY,* ++V 5000,5000,CONT_POLY,* ++V 600,8000,CONT_DIF_P,* ++V 3200,2100,CONT_DIF_N,* ++V 3200,3000,CONT_DIF_N,* ++V 2000,3600,CONT_DIF_N,* ++V 2000,2800,CONT_DIF_N,* ++EOF +diff --git a/alliance/src/cells/src/msxlib/an4_x3.vbe b/alliance/src/cells/src/msxlib/an4_x3.vbe +new file mode 100644 +index 0000000..f5dae13 +--- /dev/null ++++ b/alliance/src/cells/src/msxlib/an4_x3.vbe +@@ -0,0 +1,44 @@ ++ENTITY an4_x3 IS ++GENERIC ( ++ CONSTANT area : NATURAL := 9000; ++ CONSTANT cin_a : NATURAL := 8; ++ CONSTANT cin_b : NATURAL := 8; ++ CONSTANT cin_c : NATURAL := 7; ++ CONSTANT cin_d : NATURAL := 7; ++ CONSTANT rdown_a_z : NATURAL := 890; ++ CONSTANT rdown_b_z : NATURAL := 890; ++ CONSTANT rdown_c_z : NATURAL := 880; ++ CONSTANT rdown_d_z : NATURAL := 880; ++ CONSTANT rup_a_z : NATURAL := 1140; ++ CONSTANT rup_b_z : NATURAL := 1140; ++ CONSTANT rup_c_z : NATURAL := 1140; ++ CONSTANT rup_d_z : NATURAL := 1150; ++ CONSTANT tphh_a_z : NATURAL := 114; ++ CONSTANT tphh_b_z : NATURAL := 111; ++ CONSTANT tpll_d_z : NATURAL := 105; ++ CONSTANT tphh_c_z : NATURAL := 105; ++ CONSTANT tpll_c_z : NATURAL := 118; ++ CONSTANT tphh_d_z : NATURAL := 98; ++ CONSTANT tpll_b_z : NATURAL := 129; ++ CONSTANT tpll_a_z : NATURAL := 138; ++ CONSTANT transistors : NATURAL := 12 ++); ++PORT ( ++ a : in BIT; ++ b : in BIT; ++ c : in BIT; ++ d : in BIT; ++ z : out BIT; ++ vdd : in BIT; ++ vss : in BIT ++); ++END an4_x3; ++ ++ARCHITECTURE behaviour_data_flow OF an4_x3 IS ++ ++BEGIN ++ ASSERT ((vdd and not (vss)) = '1') ++ REPORT "power supply is missing on an4_x3" ++ SEVERITY WARNING; ++ z <= (((a and b) and c) and d) after 1200 ps; ++END; +diff --git a/alliance/src/cells/src/msxlib/aoi21_x05.ap b/alliance/src/cells/src/msxlib/aoi21_x05.ap +new file mode 100644 +index 0000000..0a9ddcc +--- /dev/null ++++ b/alliance/src/cells/src/msxlib/aoi21_x05.ap +@@ -0,0 +1,94 @@ ++V ALLIANCE : 6 ++H aoi21_x05,P, 8/ 8/2014,100 ++A 0,0,5000,10000 ++R 2000,7000,ref_ref,b_70 ++R 3000,6000,ref_ref,a2_60 ++R 3000,3000,ref_ref,a1_30 ++R 2000,4000,ref_ref,z_40 ++R 4000,4000,ref_ref,a1_40 ++R 2000,3000,ref_ref,z_30 ++R 1000,8000,ref_ref,z_80 ++R 1000,7000,ref_ref,z_70 ++R 1000,6000,ref_ref,z_60 ++R 1000,5000,ref_ref,z_50 ++R 1000,4000,ref_ref,z_40 ++R 2000,5000,ref_ref,b_50 ++R 2000,6000,ref_ref,b_60 ++R 3000,7000,ref_ref,b_70 ++R 3000,5000,ref_ref,a2_50 ++R 4000,6000,ref_ref,a2_60 ++R 4000,5000,ref_ref,a1_50 ++R 3000,4000,ref_ref,a1_40 ++R 4000,7000,ref_ref,a2_70 ++S 1100,700,1900,700,600,*,RIGHT,PTIE ++S 1100,9300,1900,9300,600,*,RIGHT,NTIE ++S 3800,8300,3800,8700,200,*,DOWN,POLY ++S 2600,8300,2600,8700,200,*,DOWN,POLY ++S 1400,8300,1400,8700,200,*,DOWN,POLY ++S 1900,4900,1900,5100,600,*,UP,ALU1 ++S 2000,7100,3100,7100,400,*,RIGHT,ALU1 ++S 2000,5000,2000,7000,400,b,DOWN,CALU1 ++S 2000,4900,2000,7000,400,*,DOWN,ALU1 ++S 4000,6000,4000,7000,400,a2,DOWN,CALU1 ++S 4000,6000,4000,7100,400,*,UP,ALU1 ++S 3000,6000,4000,6000,600,*,RIGHT,ALU1 ++S 3000,4900,3000,6000,400,*,UP,ALU1 ++S 3000,5000,3000,6000,400,a2,DOWN,CALU1 ++S 1400,3300,1400,6300,200,*,DOWN,POLY ++S 2600,3600,2600,6300,200,*,DOWN,POLY ++S 3800,4000,3800,6300,200,*,UP,POLY ++S 3400,4000,3800,4000,200,*,RIGHT,POLY ++S 4000,700,4000,3100,400,*,UP,ALU1 ++S 4000,2900,4000,3400,600,*,UP,NDIF ++S 3000,2900,3000,4000,400,*,DOWN,ALU1 ++S 3000,4000,4000,4000,600,*,RIGHT,ALU1 ++S 4000,4000,4000,5100,400,*,UP,ALU1 ++S 4000,4000,4000,5000,400,a1,UP,CALU1 ++S 3000,3000,3000,4000,400,a1,DOWN,CALU1 ++S 2200,2900,2200,3400,400,*,UP,NDIF ++S 3000,2900,3000,3400,600,n1,UP,NDIF ++S 3400,2700,3400,3600,200,4,UP,NTRANS ++S 3400,2300,3400,2700,200,*,UP,POLY ++S 2600,2700,2600,3600,200,5,UP,NTRANS ++S 2600,2300,2600,2700,200,*,UP,POLY ++S 1400,2700,1400,3300,200,6,UP,NTRANS ++S 1400,2300,1400,2700,200,*,UP,POLY ++S 800,700,800,3100,400,*,UP,ALU1 ++S 2000,2900,2000,4000,400,*,DOWN,ALU1 ++S 1000,4000,2000,4000,600,*,RIGHT,ALU1 ++S 2000,3000,2000,4000,400,z,DOWN,CALU1 ++S 1000,4000,1000,8000,400,z,DOWN,CALU1 ++S 1000,4000,1000,6600,400,*,DOWN,ALU1 ++S 0,5000,5000,5000,10000,aoi21_x05,LEFT,TALU8 ++S 0,2200,5000,2200,5200,*,LEFT,PWELL ++S 0,7600,5000,7600,5600,*,LEFT,NWELL ++S 3200,6500,3200,9100,600,*,UP,PDIF ++S 1000,6500,1000,8100,400,*,UP,PDIF ++S 3800,6300,3800,8300,200,1,DOWN,PTRANS ++S 4200,6500,4200,8100,400,*,UP,PDIF ++S 2600,6300,2600,8300,200,2,DOWN,PTRANS ++S 2000,6500,2000,8100,1000,*,UP,PDIF ++S 1400,6300,1400,8300,200,3,DOWN,PTRANS ++S 1900,8000,4500,8000,400,*,RIGHT,ALU1 ++S 0,600,5000,600,1200,vss,RIGHT,CALU1 ++S 0,9400,5000,9400,1200,vdd,RIGHT,CALU1 ++S 2000,7000,3100,7000,400,*,RIGHT,ALU1 ++S 3000,7000,3000,7000,400,b,LEFT,CALU1 ++S 800,7100,800,8100,600,*,UP,PDIF ++S 900,7100,900,8100,600,*,UP,ALU1 ++V 2000,700,CONT_BODY_P,* ++V 1000,700,CONT_BODY_P,* ++V 2000,9300,CONT_BODY_N,* ++V 1000,9300,CONT_BODY_N,* ++V 4000,3000,CONT_DIF_N,* ++V 2000,3000,CONT_DIF_N,* ++V 800,3000,CONT_DIF_N,* ++V 3000,5700,CONT_POLY,* ++V 1800,5000,CONT_POLY,* ++V 3200,9000,CONT_DIF_P,* ++V 2000,8000,CONT_DIF_P,n2 ++V 4400,8000,CONT_DIF_P,n2 ++V 800,8000,CONT_DIF_P,* ++V 4000,5000,CONT_POLY,* ++V 800,7200,CONT_DIF_P,* ++EOF +diff --git a/alliance/src/cells/src/msxlib/aoi21_x05.vbe b/alliance/src/cells/src/msxlib/aoi21_x05.vbe +new file mode 100644 +index 0000000..db51972 +--- /dev/null ++++ b/alliance/src/cells/src/msxlib/aoi21_x05.vbe +@@ -0,0 +1,38 @@ ++ENTITY aoi21_x05 IS ++GENERIC ( ++ CONSTANT area : NATURAL := 5000; ++ CONSTANT cin_a1 : NATURAL := 4; ++ CONSTANT cin_a2 : NATURAL := 4; ++ CONSTANT cin_b : NATURAL := 3; ++ CONSTANT rdown_a1_z : NATURAL := 4130; ++ CONSTANT rdown_a2_z : NATURAL := 4130; ++ CONSTANT rdown_b_z : NATURAL := 3810; ++ CONSTANT rup_a1_z : NATURAL := 5810; ++ CONSTANT rup_a2_z : NATURAL := 5830; ++ CONSTANT rup_b_z : NATURAL := 5310; ++ CONSTANT tphl_a1_z : NATURAL := 57; ++ CONSTANT tphl_a2_z : NATURAL := 58; ++ CONSTANT tphl_b_z : NATURAL := 45; ++ CONSTANT tplh_b_z : NATURAL := 48; ++ CONSTANT tplh_a2_z : NATURAL := 69; ++ CONSTANT tplh_a1_z : NATURAL := 76; ++ CONSTANT transistors : NATURAL := 6 ++); ++PORT ( ++ a1 : in BIT; ++ a2 : in BIT; ++ b : in BIT; ++ z : out BIT; ++ vdd : in BIT; ++ vss : in BIT ++); ++END aoi21_x05; ++ ++ARCHITECTURE behaviour_data_flow OF aoi21_x05 IS ++ ++BEGIN ++ ASSERT ((vdd and not (vss)) = '1') ++ REPORT "power supply is missing on aoi21_x05" ++ SEVERITY WARNING; ++ z <= not (((a1 and a2) or b)) after 900 ps; ++END; +diff --git a/alliance/src/cells/src/msxlib/aoi21_x1.ap b/alliance/src/cells/src/msxlib/aoi21_x1.ap +new file mode 100644 +index 0000000..d16aa44 +--- /dev/null ++++ b/alliance/src/cells/src/msxlib/aoi21_x1.ap +@@ -0,0 +1,102 @@ ++V ALLIANCE : 6 ++H aoi21_x1,P, 8/ 8/2014,100 ++A 0,0,5000,10000 ++R 3000,3000,ref_ref,a1_30 ++R 4000,4000,ref_ref,a1_40 ++R 2000,3000,ref_ref,z_30 ++R 1000,7000,ref_ref,z_70 ++R 1000,6000,ref_ref,z_60 ++R 1000,5000,ref_ref,z_50 ++R 1000,4000,ref_ref,z_40 ++R 2000,5000,ref_ref,b_50 ++R 2000,6000,ref_ref,b_60 ++R 3000,5000,ref_ref,a2_50 ++R 4000,6000,ref_ref,a2_60 ++R 4000,3000,ref_ref,a1_30 ++R 2000,2000,ref_ref,z_20 ++R 1000,3000,ref_ref,z_30 ++R 3000,2000,ref_ref,a1_20 ++R 3000,4000,ref_ref,a2_40 ++R 4000,5000,ref_ref,a2_50 ++R 3000,6000,ref_ref,b_60 ++R 2000,4000,ref_ref,b_40 ++S 1100,700,1900,700,600,*,RIGHT,PTIE ++S 4100,1900,4100,3200,600,*,UP,NDIF ++S 3400,3800,3800,3800,200,*,RIGHT,POLY ++S 1900,4800,1900,5000,600,*,UP,ALU1 ++S 3400,1300,3400,1700,200,*,UP,POLY ++S 3400,1700,3400,3400,200,4,UP,NTRANS ++S 3000,1900,3000,3200,600,n1,UP,NDIF ++S 2600,1300,2600,1700,200,*,UP,POLY ++S 2600,3400,2600,5500,200,*,DOWN,POLY ++S 2600,1700,2600,3400,200,5,UP,NTRANS ++S 2200,1900,2200,3200,400,*,UP,NDIF ++S 900,5700,900,7100,600,*,UP,ALU1 ++S 800,5700,800,6500,600,*,UP,PDIF ++S 2000,5700,2000,9200,600,*,UP,PDIF ++S 3200,5700,3200,9200,600,*,UP,PDIF ++S 4200,5700,4200,9200,400,*,UP,PDIF ++S 3800,5500,3800,9400,200,1,DOWN,PTRANS ++S 2600,5500,2600,9400,200,2,DOWN,PTRANS ++S 1000,5700,1000,9200,400,*,UP,PDIF ++S 1400,5500,1400,9400,200,3,DOWN,PTRANS ++S 3800,9400,3800,9700,200,*,DOWN,POLY ++S 2600,9400,2600,9700,200,*,DOWN,POLY ++S 1400,9400,1400,9700,200,*,DOWN,POLY ++S 0,600,5000,600,1200,vss,RIGHT,CALU1 ++S 0,5000,5000,5000,10000,aoi21_x1,LEFT,TALU8 ++S 0,2200,5000,2200,5200,*,LEFT,PWELL ++S 0,7600,5000,7600,5600,*,LEFT,NWELL ++S 0,9400,5000,9400,1200,vdd,RIGHT,CALU1 ++S 4000,700,4000,2100,400,*,UP,ALU1 ++S 3000,3000,4000,3000,600,*,RIGHT,ALU1 ++S 1400,1700,1400,2700,200,6,UP,NTRANS ++S 1400,1300,1400,1700,200,*,UP,POLY ++S 2000,1900,2000,2500,1000,*,UP,NDIF ++S 1400,2700,1400,5500,200,*,DOWN,POLY ++S 800,1900,800,2500,600,*,UP,NDIF ++S 700,1900,700,2500,600,*,UP,NDIF ++S 800,700,800,2100,400,*,UP,ALU1 ++S 1000,3000,2000,3000,400,*,RIGHT,ALU1 ++S 1000,2900,2000,2900,400,*,RIGHT,ALU1 ++S 2000,2000,2000,3000,600,*,DOWN,ALU1 ++S 2000,2000,2000,3000,400,z,DOWN,CALU1 ++S 1000,2900,1000,7000,400,*,DOWN,ALU1 ++S 1000,3000,1000,7000,400,z,DOWN,CALU1 ++S 2000,4000,2000,6000,400,b,DOWN,CALU1 ++S 3000,2000,3000,3000,400,a1,DOWN,CALU1 ++S 3000,1900,3000,3100,400,*,DOWN,ALU1 ++S 3800,3800,3800,5500,200,*,UP,POLY ++S 4000,3000,4000,4100,400,*,UP,ALU1 ++S 4000,3000,4000,4000,400,a1,UP,CALU1 ++S 3000,5000,4000,5000,600,*,RIGHT,ALU1 ++S 4000,5000,4000,6000,400,a2,DOWN,CALU1 ++S 3000,3900,3000,5100,400,*,UP,ALU1 ++S 3000,4000,3000,5000,400,a2,DOWN,CALU1 ++S 4000,4900,4000,6100,400,*,UP,ALU1 ++S 2000,6100,3100,6100,400,*,RIGHT,ALU1 ++S 2000,6000,3100,6000,400,*,RIGHT,ALU1 ++S 3000,6000,3000,6000,400,b,LEFT,CALU1 ++S 2000,3900,2000,6100,400,*,DOWN,ALU1 ++S 3200,7900,3200,9300,400,*,DOWN,ALU1 ++S 4400,7000,4400,8100,400,*,DOWN,ALU1 ++S 2000,7000,2000,8100,400,*,DOWN,ALU1 ++S 2000,7000,4400,7000,400,*,RIGHT,ALU1 ++S 4400,7300,4400,7900,600,*,UP,PDIF ++V 2100,700,CONT_BODY_P,* ++V 1000,700,CONT_BODY_P,* ++V 1800,4900,CONT_POLY,* ++V 4000,2000,CONT_DIF_N,* ++V 3000,4900,CONT_POLY,* ++V 800,6600,CONT_DIF_P,* ++V 800,5800,CONT_DIF_P,* ++V 3200,9000,CONT_DIF_P,* ++V 800,2000,CONT_DIF_N,* ++V 2000,2000,CONT_DIF_N,* ++V 4000,4000,CONT_POLY,* ++V 3200,8000,CONT_DIF_P,* ++V 2000,8000,CONT_DIF_P,n2 ++V 4400,8000,CONT_DIF_P,n2 ++V 2000,7200,CONT_DIF_P,n2 ++V 4400,7200,CONT_DIF_P,n2 ++EOF +diff --git a/alliance/src/cells/src/msxlib/aoi21_x1.vbe b/alliance/src/cells/src/msxlib/aoi21_x1.vbe +new file mode 100644 +index 0000000..b53540f +--- /dev/null ++++ b/alliance/src/cells/src/msxlib/aoi21_x1.vbe +@@ -0,0 +1,38 @@ ++ENTITY aoi21_x1 IS ++GENERIC ( ++ CONSTANT area : NATURAL := 5000; ++ CONSTANT cin_a1 : NATURAL := 6; ++ CONSTANT cin_a2 : NATURAL := 6; ++ CONSTANT cin_b : NATURAL := 6; ++ CONSTANT rdown_a1_z : NATURAL := 2190; ++ CONSTANT rdown_a2_z : NATURAL := 2180; ++ CONSTANT rdown_b_z : NATURAL := 2280; ++ CONSTANT rup_a1_z : NATURAL := 2980; ++ CONSTANT rup_a2_z : NATURAL := 2990; ++ CONSTANT rup_b_z : NATURAL := 2720; ++ CONSTANT tphl_a1_z : NATURAL := 55; ++ CONSTANT tphl_a2_z : NATURAL := 56; ++ CONSTANT tphl_b_z : NATURAL := 45; ++ CONSTANT tplh_b_z : NATURAL := 45; ++ CONSTANT tplh_a2_z : NATURAL := 64; ++ CONSTANT tplh_a1_z : NATURAL := 71; ++ CONSTANT transistors : NATURAL := 6 ++); ++PORT ( ++ a1 : in BIT; ++ a2 : in BIT; ++ b : in BIT; ++ z : out BIT; ++ vdd : in BIT; ++ vss : in BIT ++); ++END aoi21_x1; ++ ++ARCHITECTURE behaviour_data_flow OF aoi21_x1 IS ++ ++BEGIN ++ ASSERT ((vdd and not (vss)) = '1') ++ REPORT "power supply is missing on aoi21_x1" ++ SEVERITY WARNING; ++ z <= not (((a1 and a2) or b)) after 900 ps; ++END; +diff --git a/alliance/src/cells/src/msxlib/aoi21_x2.ap b/alliance/src/cells/src/msxlib/aoi21_x2.ap +new file mode 100644 +index 0000000..c4a05d0 +--- /dev/null ++++ b/alliance/src/cells/src/msxlib/aoi21_x2.ap +@@ -0,0 +1,136 @@ ++V ALLIANCE : 6 ++H aoi21_x2,P, 8/ 8/2014,100 ++A 0,0,9000,10000 ++R 1000,3000,ref_ref,z_30 ++R 4000,4000,ref_ref,b_40 ++R 8000,4000,ref_ref,a1_40 ++R 8000,6000,ref_ref,a1_60 ++R 3000,5000,ref_ref,b_50 ++R 3000,7000,ref_ref,z_70 ++R 2000,7000,ref_ref,z_70 ++R 3000,3000,ref_ref,z_30 ++R 2000,3000,ref_ref,z_30 ++R 1000,6000,ref_ref,z_60 ++R 1000,5000,ref_ref,z_50 ++R 1000,4000,ref_ref,z_40 ++R 4000,3000,ref_ref,z_30 ++R 2000,5000,ref_ref,a1_50 ++R 8000,5000,ref_ref,a1_50 ++R 7000,6000,ref_ref,a1_60 ++R 6000,6000,ref_ref,a1_60 ++R 5000,6000,ref_ref,a1_60 ++R 4000,6000,ref_ref,a1_60 ++R 3000,6000,ref_ref,a1_60 ++R 6000,5000,ref_ref,a2_50 ++R 5000,5000,ref_ref,a2_50 ++R 1000,7000,ref_ref,z_70 ++R 2000,6000,ref_ref,a1_60 ++R 4000,5000,ref_ref,b_50 ++R 6000,4000,ref_ref,a2_40 ++R 6000,3000,ref_ref,a2_30 ++S 1100,700,1900,700,600,*,RIGHT,PTIE ++S 4900,5000,6000,5000,600,*,RIGHT,ALU1 ++S 3800,3900,3800,5100,200,*,UP,POLY ++S 3100,1900,3100,3700,600,*,UP,NDIF ++S 3200,700,3200,2100,400,*,UP,ALU1 ++S 3800,1700,3800,3900,200,09,UP,NTRANS ++S 3800,1300,3800,1700,200,*,DOWN,POLY ++S 4400,1900,4400,3700,1000,*,UP,NDIF ++S 4600,800,4600,3700,400,*,UP,NDIF ++S 5800,4300,7600,4300,200,*,LEFT,POLY ++S 5000,3900,5000,4800,200,*,UP,POLY ++S 5000,300,5000,600,200,*,DOWN,POLY ++S 5000,600,5000,3900,200,08,UP,NTRANS ++S 5800,300,5800,600,200,*,DOWN,POLY ++S 5800,600,5800,3900,200,07,UP,NTRANS ++S 6500,800,6500,3700,600,*,UP,NDIF ++S 6400,700,6400,2000,400,*,UP,ALU1 ++S 5000,5000,5000,5000,400,a2,LEFT,CALU1 ++S 3000,5000,3000,5000,400,b,LEFT,CALU1 ++S 7000,6000,7000,6000,400,a1,LEFT,CALU1 ++S 6000,6000,6000,6000,400,a1,LEFT,CALU1 ++S 5000,6000,5000,6000,400,a1,LEFT,CALU1 ++S 4000,6000,4000,6000,400,a1,LEFT,CALU1 ++S 3000,6000,3000,6000,400,a1,LEFT,CALU1 ++S 4000,3000,4000,3000,400,z,LEFT,CALU1 ++S 3000,3000,3000,3000,400,z,LEFT,CALU1 ++S 2000,3000,2000,3000,400,z,LEFT,CALU1 ++S 3000,7000,3000,7000,400,z,LEFT,CALU1 ++S 2000,7000,2000,7000,400,z,LEFT,CALU1 ++S 0,9400,9000,9400,1200,vdd,RIGHT,CALU1 ++S 0,5000,9000,5000,10000,aoi21_x2,LEFT,TALU8 ++S 0,2200,9000,2200,5200,*,LEFT,PWELL ++S 0,7600,9000,7600,5600,*,LEFT,NWELL ++S 2000,6000,8000,6000,400,*,RIGHT,ALU1 ++S 0,600,9000,600,1200,vss,RIGHT,CALU1 ++S 1600,5500,1600,9400,200,02,DOWN,PTRANS ++S 900,5700,900,9200,600,*,DOWN,PDIF ++S 2800,5500,2800,9400,200,06,DOWN,PTRANS ++S 2200,5700,2200,9200,1000,*,UP,PDIF ++S 4000,5500,4000,9400,200,05,DOWN,PTRANS ++S 3400,5700,3400,9200,1000,*,UP,PDIF ++S 4600,5700,4600,9200,1000,*,UP,PDIF ++S 5200,5500,5200,9400,200,04,DOWN,PTRANS ++S 5800,5700,5800,9200,1000,*,UP,PDIF ++S 6400,5500,6400,9400,200,03,DOWN,PTRANS ++S 7000,5700,7000,9200,1000,*,UP,PDIF ++S 7600,5500,7600,9400,200,01,DOWN,PTRANS ++S 8300,5700,8300,9200,600,*,DOWN,PDIF ++S 1000,7000,3500,7000,400,*,RIGHT,ALU1 ++S 1000,7100,3500,7100,400,*,RIGHT,ALU1 ++S 8000,4000,8000,6000,400,a1,DOWN,CALU1 ++S 8000,4000,8000,6000,600,*,UP,ALU1 ++S 2000,5000,2000,6000,400,a1,DOWN,CALU1 ++S 2000,4900,2000,6000,600,*,UP,ALU1 ++S 1600,5000,1600,5500,200,*,DOWN,POLY ++S 2800,5100,4000,5100,200,*,LEFT,POLY ++S 5200,5100,6400,5100,200,*,RIGHT,POLY ++S 1600,9400,1600,9700,200,*,DOWN,POLY ++S 2800,9400,2800,9700,200,*,DOWN,POLY ++S 4000,9400,4000,9700,200,*,DOWN,POLY ++S 5200,9400,5200,9700,200,*,DOWN,POLY ++S 6400,9400,6400,9700,200,*,DOWN,POLY ++S 7600,9400,7600,9700,200,*,DOWN,POLY ++S 7600,4300,7600,5500,200,*,DOWN,POLY ++S 4000,3900,4000,5000,400,*,DOWN,ALU1 ++S 4000,4000,4000,5000,400,b,DOWN,CALU1 ++S 6000,2900,6000,5000,400,*,DOWN,ALU1 ++S 6000,3000,6000,5000,400,a2,DOWN,CALU1 ++S 1000,3000,1000,7000,400,z,DOWN,CALU1 ++S 1000,3000,1000,7000,400,*,DOWN,ALU1 ++S 3000,5000,4000,5000,600,*,RIGHT,ALU1 ++S 1000,3000,4400,3000,400,*,RIGHT,ALU1 ++S 1000,2900,4400,2900,400,*,RIGHT,ALU1 ++S 4400,1900,4400,3000,400,*,DOWN,ALU1 ++S 2100,8000,4600,8000,400,*,RIGHT,ALU1 ++S 4600,7000,7000,7000,400,*,RIGHT,ALU1 ++S 4600,7000,4600,8000,400,*,UP,ALU1 ++S 7000,7000,7000,8000,400,*,UP,ALU1 ++S 5800,7900,5800,9300,400,*,DOWN,ALU1 ++S 1000,7900,1000,9300,400,*,UP,ALU1 ++S 8200,6900,8200,9300,400,*,UP,ALU1 ++V 2000,700,CONT_BODY_P,* ++V 1000,700,CONT_BODY_P,* ++V 3200,2000,CONT_DIF_N,* ++V 5000,4900,CONT_POLY,* ++V 6400,900,CONT_DIF_N,* ++V 6400,1900,CONT_DIF_N,* ++V 3400,7000,CONT_DIF_P,* ++V 2200,8000,CONT_DIF_P,n2 ++V 1000,8000,CONT_DIF_P,* ++V 8200,8000,CONT_DIF_P,* ++V 8200,9000,CONT_DIF_P,* ++V 5800,9000,CONT_DIF_P,* ++V 1000,9000,CONT_DIF_P,* ++V 2000,4900,CONT_POLY,* ++V 8000,4500,CONT_POLY,* ++V 3800,4900,CONT_POLY,* ++V 8200,7000,CONT_DIF_P,* ++V 4400,2000,CONT_DIF_N,* ++V 4400,2800,CONT_DIF_N,* ++V 4600,7900,CONT_DIF_P,n2 ++V 4600,7100,CONT_DIF_P,n2 ++V 7000,7100,CONT_DIF_P,n2 ++V 7000,7900,CONT_DIF_P,n2 ++V 5800,8000,CONT_DIF_P,* ++EOF +diff --git a/alliance/src/cells/src/msxlib/aoi21_x2.vbe b/alliance/src/cells/src/msxlib/aoi21_x2.vbe +new file mode 100644 +index 0000000..705fdb4 +--- /dev/null ++++ b/alliance/src/cells/src/msxlib/aoi21_x2.vbe +@@ -0,0 +1,38 @@ ++ENTITY aoi21_x2 IS ++GENERIC ( ++ CONSTANT area : NATURAL := 9000; ++ CONSTANT cin_a1 : NATURAL := 13; ++ CONSTANT cin_a2 : NATURAL := 12; ++ CONSTANT cin_b : NATURAL := 10; ++ CONSTANT rdown_a1_z : NATURAL := 1120; ++ CONSTANT rdown_a2_z : NATURAL := 1120; ++ CONSTANT rdown_b_z : NATURAL := 1040; ++ CONSTANT rup_a1_z : NATURAL := 1490; ++ CONSTANT rup_a2_z : NATURAL := 1490; ++ CONSTANT rup_b_z : NATURAL := 1360; ++ CONSTANT tphl_a1_z : NATURAL := 53; ++ CONSTANT tphl_a2_z : NATURAL := 54; ++ CONSTANT tphl_b_z : NATURAL := 41; ++ CONSTANT tplh_b_z : NATURAL := 43; ++ CONSTANT tplh_a2_z : NATURAL := 60; ++ CONSTANT tplh_a1_z : NATURAL := 68; ++ CONSTANT transistors : NATURAL := 9 ++); ++PORT ( ++ a1 : in BIT; ++ a2 : in BIT; ++ b : in BIT; ++ z : out BIT; ++ vdd : in BIT; ++ vss : in BIT ++); ++END aoi21_x2; ++ ++ARCHITECTURE behaviour_data_flow OF aoi21_x2 IS ++ ++BEGIN ++ ASSERT ((vdd and not (vss)) = '1') ++ REPORT "power supply is missing on aoi21_x2" ++ SEVERITY WARNING; ++ z <= not (((a1 and a2) or b)) after 900 ps; ++END; +diff --git a/alliance/src/cells/src/msxlib/aoi22_x05.ap b/alliance/src/cells/src/msxlib/aoi22_x05.ap +new file mode 100644 +index 0000000..dab8c9b +--- /dev/null ++++ b/alliance/src/cells/src/msxlib/aoi22_x05.ap +@@ -0,0 +1,126 @@ ++V ALLIANCE : 6 ++H aoi22_x05,P, 8/ 8/2014,100 ++A 0,0,6000,10000 ++R 2000,7000,ref_ref,z_70 ++R 2000,2000,ref_ref,z_20 ++R 1000,3000,ref_ref,z_30 ++R 3000,2000,ref_ref,z_20 ++R 1000,6000,ref_ref,z_60 ++R 1000,5000,ref_ref,z_50 ++R 1000,4000,ref_ref,z_40 ++R 2000,5000,ref_ref,b1_50 ++R 2000,4000,ref_ref,b1_40 ++R 3000,3000,ref_ref,b1_30 ++R 3000,6000,ref_ref,b2_60 ++R 2000,6000,ref_ref,b2_60 ++R 3000,5000,ref_ref,b2_50 ++R 3000,4000,ref_ref,b2_40 ++R 4000,6000,ref_ref,a2_60 ++R 4000,5000,ref_ref,a2_50 ++R 4000,4000,ref_ref,a2_40 ++R 5000,4000,ref_ref,a1_40 ++R 4000,3000,ref_ref,a1_30 ++R 1000,7000,ref_ref,z_70 ++R 5000,6000,ref_ref,a2_60 ++R 5000,3000,ref_ref,a1_30 ++R 2000,3000,ref_ref,b1_30 ++R 1000,2000,ref_ref,z_20 ++R 4000,2000,ref_ref,a1_20 ++S 4100,700,4900,700,600,*,RIGHT,PTIE ++S 1100,9300,1900,9300,600,*,RIGHT,NTIE ++S 3000,7000,5400,7000,400,*,LEFT,ALU1 ++S 5400,7000,5400,8100,400,*,DOWN,ALU1 ++S 5400,7300,5400,7900,600,*,UP,PDIF ++S 2000,3000,2000,5100,400,*,UP,ALU1 ++S 5000,6000,5000,6000,400,a2,LEFT,CALU1 ++S 2000,6000,2000,6000,400,b2,LEFT,CALU1 ++S 3000,3000,3000,3000,400,b1,LEFT,CALU1 ++S 2000,7000,2000,7000,400,z,LEFT,CALU1 ++S 3000,2000,3000,2000,400,z,LEFT,CALU1 ++S 2000,2000,2000,2000,400,z,LEFT,CALU1 ++S 3600,5600,3600,6300,200,*,DOWN,POLY ++S 2400,4600,2400,6300,200,*,DOWN,POLY ++S 4600,2600,4600,3400,200,*,UP,POLY ++S 1000,2000,1000,7000,400,z,DOWN,CALU1 ++S 2600,1700,2600,2600,200,7,UP,NTRANS ++S 3800,1700,3800,2600,200,8,UP,NTRANS ++S 4600,1700,4600,2600,200,6,UP,NTRANS ++S 2200,1900,2200,2400,600,n2,UP,NDIF ++S 5300,1900,5300,2400,600,*,UP,NDIF ++S 4200,1900,4200,2400,600,n1,UP,NDIF ++S 3200,1900,3200,2400,1000,*,UP,NDIF ++S 1200,900,1200,2400,600,*,UP,NDIF ++S 1800,1700,1800,2600,200,5,UP,NTRANS ++S 2000,4900,2000,5100,400,*,UP,ALU1 ++S 2000,3000,3100,3000,400,*,LEFT,ALU1 ++S 1800,1300,1800,1700,200,*,UP,POLY ++S 2600,1300,2600,1700,200,*,UP,POLY ++S 3800,1300,3800,1700,200,*,UP,POLY ++S 4600,1300,4600,1700,200,*,UP,POLY ++S 0,5000,6000,5000,10000,aoi22_x05,LEFT,TALU8 ++S 0,2200,6000,2200,5200,*,LEFT,PWELL ++S 0,7600,6000,7600,5600,*,LEFT,NWELL ++S 0,600,6000,600,1200,vss,RIGHT,CALU1 ++S 0,9400,6000,9400,1200,vdd,RIGHT,CALU1 ++S 1800,6500,1800,8100,1000,*,UP,PDIF ++S 2400,6300,2400,8300,200,3,DOWN,PTRANS ++S 1200,6300,1200,8300,200,1,DOWN,PTRANS ++S 3600,6300,3600,8300,200,4,DOWN,PTRANS ++S 4800,6300,4800,8300,200,2,DOWN,PTRANS ++S 800,6500,800,8100,400,*,UP,PDIF ++S 5200,6500,5200,8100,400,*,UP,PDIF ++S 3000,6500,3000,8100,1000,*,UP,PDIF ++S 1200,8300,1200,8700,200,*,DOWN,POLY ++S 2400,8300,2400,8700,200,*,DOWN,POLY ++S 3600,8300,3600,8700,200,*,DOWN,POLY ++S 4800,8300,4800,8700,200,*,DOWN,POLY ++S 3000,4000,3000,6000,400,b2,DOWN,CALU1 ++S 3000,3900,3000,6000,400,*,DOWN,ALU1 ++S 1900,6000,3000,6000,400,*,RIGHT,ALU1 ++S 1900,6100,3000,6100,400,*,RIGHT,ALU1 ++S 1000,7000,2100,7000,400,*,RIGHT,ALU1 ++S 1000,7100,2100,7100,400,*,RIGHT,ALU1 ++S 4000,6000,5100,6000,400,*,RIGHT,ALU1 ++S 4000,6100,5100,6100,400,*,RIGHT,ALU1 ++S 4000,3900,4000,6000,400,*,UP,ALU1 ++S 4000,4000,4000,6000,400,a2,DOWN,CALU1 ++S 500,8000,3000,8000,400,*,RIGHT,ALU1 ++S 3000,7000,3000,8000,600,*,UP,ALU1 ++S 4200,7900,4200,9300,400,*,UP,ALU1 ++S 4200,6500,4200,8100,600,*,UP,PDIF ++S 2000,3000,2000,5000,400,b1,UP,CALU1 ++S 2000,2900,3100,2900,400,*,LEFT,ALU1 ++S 5200,700,5200,2100,400,*,UP,ALU1 ++S 3800,2600,3800,5300,200,*,UP,POLY ++S 4800,3600,4800,6300,200,*,DOWN,POLY ++S 1800,2600,1800,3400,200,*,UP,POLY ++S 1200,3700,1500,3700,200,*,RIGHT,POLY ++S 1200,3700,1200,6300,200,*,DOWN,POLY ++S 2600,2600,2600,4700,200,*,DOWN,POLY ++S 1800,3500,2000,3500,600,*,RIGHT,ALU1 ++S 4000,2000,4000,3000,400,a1,DOWN,CALU1 ++S 4000,1900,4000,3100,400,*,DOWN,ALU1 ++S 4000,3000,5000,3000,600,*,RIGHT,ALU1 ++S 1000,1900,1000,7000,400,*,DOWN,ALU1 ++S 1000,2000,3200,2000,600,*,RIGHT,ALU1 ++S 5000,3000,5000,4100,400,*,UP,ALU1 ++S 5000,3000,5000,4000,400,a1,UP,CALU1 ++V 5000,700,CONT_BODY_P,* ++V 4000,700,CONT_BODY_P,* ++V 2000,9300,CONT_BODY_N,* ++V 1000,9300,CONT_BODY_N,* ++V 5400,7200,CONT_DIF_P,n3 ++V 5400,8000,CONT_DIF_P,n3 ++V 1800,7000,CONT_DIF_P,* ++V 5200,2000,CONT_DIF_N,* ++V 1200,1000,CONT_DIF_N,* ++V 3200,2000,CONT_DIF_N,* ++V 3000,8000,CONT_DIF_P,n3 ++V 600,8000,CONT_DIF_P,n3 ++V 3000,7000,CONT_DIF_P,n3 ++V 4200,8000,CONT_DIF_P,* ++V 4000,5500,CONT_POLY,* ++V 5000,3500,CONT_POLY,* ++V 1800,3500,CONT_POLY,* ++V 3000,4500,CONT_POLY,* ++EOF +diff --git a/alliance/src/cells/src/msxlib/aoi22_x05.vbe b/alliance/src/cells/src/msxlib/aoi22_x05.vbe +new file mode 100644 +index 0000000..995b188 +--- /dev/null ++++ b/alliance/src/cells/src/msxlib/aoi22_x05.vbe +@@ -0,0 +1,44 @@ ++ENTITY aoi22_x05 IS ++GENERIC ( ++ CONSTANT area : NATURAL := 6000; ++ CONSTANT cin_b1 : NATURAL := 4; ++ CONSTANT cin_b2 : NATURAL := 4; ++ CONSTANT cin_a1 : NATURAL := 4; ++ CONSTANT cin_a2 : NATURAL := 4; ++ CONSTANT rdown_b1_z : NATURAL := 4100; ++ CONSTANT rdown_b2_z : NATURAL := 4090; ++ CONSTANT rdown_a1_z : NATURAL := 4140; ++ CONSTANT rdown_a2_z : NATURAL := 4140; ++ CONSTANT rup_b1_z : NATURAL := 5310; ++ CONSTANT rup_b2_z : NATURAL := 5310; ++ CONSTANT rup_a1_z : NATURAL := 5370; ++ CONSTANT rup_a2_z : NATURAL := 5390; ++ CONSTANT tphl_b1_z : NATURAL := 49; ++ CONSTANT tphl_b2_z : NATURAL := 49; ++ CONSTANT tplh_a2_z : NATURAL := 83; ++ CONSTANT tphl_a1_z : NATURAL := 70; ++ CONSTANT tplh_b2_z : NATURAL := 55; ++ CONSTANT tplh_a1_z : NATURAL := 90; ++ CONSTANT tplh_b1_z : NATURAL := 63; ++ CONSTANT tphl_a2_z : NATURAL := 71; ++ CONSTANT transistors : NATURAL := 8 ++); ++PORT ( ++ b1 : in BIT; ++ b2 : in BIT; ++ a1 : in BIT; ++ a2 : in BIT; ++ z : out BIT; ++ vdd : in BIT; ++ vss : in BIT ++); ++END aoi22_x05; ++ ++ARCHITECTURE behaviour_data_flow OF aoi22_x05 IS ++ ++BEGIN ++ ASSERT ((vdd and not (vss)) = '1') ++ REPORT "power supply is missing on aoi22_x05" ++ SEVERITY WARNING; ++ z <= not (((b1 and b2) or (a1 and a2))) after 1000 ps; ++END; +diff --git a/alliance/src/cells/src/msxlib/aoi22_x1.ap b/alliance/src/cells/src/msxlib/aoi22_x1.ap +new file mode 100644 +index 0000000..14246d4 +--- /dev/null ++++ b/alliance/src/cells/src/msxlib/aoi22_x1.ap +@@ -0,0 +1,124 @@ ++V ALLIANCE : 6 ++H aoi22_x1,P, 8/ 8/2014,100 ++A 0,0,6000,10000 ++R 3000,6000,ref_ref,b2_60 ++R 1000,4000,ref_ref,z_40 ++R 1000,5000,ref_ref,z_50 ++R 1000,6000,ref_ref,z_60 ++R 3000,2000,ref_ref,z_20 ++R 1000,3000,ref_ref,z_30 ++R 2000,2000,ref_ref,z_20 ++R 2000,7000,ref_ref,z_70 ++R 2000,5000,ref_ref,b1_50 ++R 2000,4000,ref_ref,b1_40 ++R 3000,3000,ref_ref,b1_30 ++R 2000,6000,ref_ref,b2_60 ++R 3000,5000,ref_ref,b2_50 ++R 3000,4000,ref_ref,b2_40 ++R 4000,6000,ref_ref,a2_60 ++R 4000,5000,ref_ref,a2_50 ++R 5000,4000,ref_ref,a1_40 ++R 5000,5000,ref_ref,a1_50 ++R 5000,3000,ref_ref,a1_30 ++R 4000,3000,ref_ref,a1_30 ++R 5000,6000,ref_ref,a2_60 ++R 4000,4000,ref_ref,a2_40 ++R 2000,3000,ref_ref,b1_30 ++R 1000,7000,ref_ref,z_70 ++R 1000,2000,ref_ref,z_20 ++S 4100,700,4900,700,600,*,RIGHT,PTIE ++S 3600,5000,3600,5500,200,*,DOWN,POLY ++S 4600,3400,4600,3900,200,*,UP,POLY ++S 3000,7000,5400,7000,400,*,RIGHT,ALU1 ++S 5400,7000,5400,8100,400,*,DOWN,ALU1 ++S 5400,7300,5400,7900,600,*,DOWN,PDIF ++S 5000,6000,5000,6000,400,a2,LEFT,CALU1 ++S 4000,3000,4000,3000,400,a1,LEFT,CALU1 ++S 3000,3000,3000,3000,400,b1,LEFT,CALU1 ++S 2000,6000,2000,6000,400,b2,LEFT,CALU1 ++S 2000,7000,2000,7000,400,z,LEFT,CALU1 ++S 3000,2000,3000,2000,400,z,LEFT,CALU1 ++S 2000,2000,2000,2000,400,z,LEFT,CALU1 ++S 2600,1700,2600,3400,200,7,UP,NTRANS ++S 3800,1700,3800,3400,200,8,UP,NTRANS ++S 4600,1700,4600,3400,200,6,UP,NTRANS ++S 0,9400,6000,9400,1200,vdd,RIGHT,CALU1 ++S 0,600,6000,600,1200,vss,RIGHT,CALU1 ++S 0,5000,6000,5000,10000,aoi22_x1,LEFT,TALU8 ++S 0,2200,6000,2200,5200,*,LEFT,PWELL ++S 0,7600,6000,7600,5600,*,LEFT,NWELL ++S 4600,1300,4600,1700,200,*,UP,POLY ++S 3800,1300,3800,1700,200,*,UP,POLY ++S 2200,1900,2200,3200,600,n2,UP,NDIF ++S 1800,1700,1800,3400,200,5,UP,NTRANS ++S 4200,1900,4200,3200,600,n1,UP,NDIF ++S 3200,1900,3200,3200,1000,*,UP,NDIF ++S 5300,1900,5300,3200,600,*,UP,NDIF ++S 2600,1300,2600,1700,200,*,UP,POLY ++S 1800,1300,1800,1700,200,*,UP,POLY ++S 1200,900,1200,3200,600,*,UP,NDIF ++S 2000,3000,3100,3000,400,*,LEFT,ALU1 ++S 2000,4900,2000,5100,400,*,UP,ALU1 ++S 1000,2000,1000,7000,400,z,DOWN,CALU1 ++S 1000,2000,1000,7000,400,*,DOWN,ALU1 ++S 1800,5700,1800,9200,1000,*,UP,PDIF ++S 1200,5500,1200,9400,200,1,DOWN,PTRANS ++S 2400,5500,2400,9400,200,3,DOWN,PTRANS ++S 800,5700,800,9200,400,*,UP,PDIF ++S 3600,5500,3600,9400,200,4,DOWN,PTRANS ++S 4800,5500,4800,9400,200,2,DOWN,PTRANS ++S 4200,5700,4200,9200,1000,*,UP,PDIF ++S 3000,5700,3000,9200,1000,*,UP,PDIF ++S 5200,5700,5200,9200,400,*,UP,PDIF ++S 3900,2900,5000,2900,400,*,RIGHT,ALU1 ++S 3900,3000,5000,3000,400,*,RIGHT,ALU1 ++S 5000,3000,5000,5000,400,a1,UP,CALU1 ++S 5000,3000,5000,5100,400,*,UP,ALU1 ++S 4000,4000,4000,6000,400,a2,DOWN,CALU1 ++S 4000,3900,4000,6000,400,*,UP,ALU1 ++S 4000,6000,5100,6000,400,*,RIGHT,ALU1 ++S 4000,6100,5100,6100,400,*,RIGHT,ALU1 ++S 3000,4000,3000,6000,400,b2,DOWN,CALU1 ++S 3000,3900,3000,6000,400,*,DOWN,ALU1 ++S 1900,6000,3000,6000,400,*,RIGHT,ALU1 ++S 1900,6100,3000,6100,400,*,RIGHT,ALU1 ++S 500,8000,3000,8000,400,*,RIGHT,ALU1 ++S 3000,7000,3000,8000,600,*,DOWN,ALU1 ++S 4200,7900,4200,9300,400,*,DOWN,ALU1 ++S 2000,3000,2000,5000,400,b1,UP,CALU1 ++S 2000,3000,2000,3900,400,*,UP,ALU1 ++S 2000,2900,3100,2900,400,*,LEFT,ALU1 ++S 1000,2000,3300,2000,400,*,RIGHT,ALU1 ++S 1000,7000,2100,7000,400,*,RIGHT,ALU1 ++S 1800,4000,2000,4000,600,*,RIGHT,ALU1 ++S 1200,4200,1500,4200,200,*,RIGHT,POLY ++S 1200,4200,1200,5500,200,*,DOWN,POLY ++S 3800,3400,3800,4700,200,*,UP,POLY ++S 4800,3800,4800,5500,200,*,DOWN,POLY ++S 5200,700,5200,2100,400,*,UP,ALU1 ++S 1000,7100,2100,7100,400,*,RIGHT,ALU1 ++S 1000,1900,3300,1900,400,*,RIGHT,ALU1 ++S 2600,3400,2600,5100,200,*,DOWN,POLY ++S 2400,5000,2400,5500,200,*,DOWN,POLY ++S 1200,9400,1200,9700,200,*,DOWN,POLY ++S 2400,9400,2400,9700,200,*,DOWN,POLY ++S 3600,9400,3600,9700,200,*,DOWN,POLY ++S 4800,9400,4800,9700,200,*,DOWN,POLY ++V 5000,700,CONT_BODY_P,* ++V 4000,700,CONT_BODY_P,* ++V 5400,7200,CONT_DIF_P,n3 ++V 5400,8000,CONT_DIF_P,n3 ++V 3200,2000,CONT_DIF_N,* ++V 1200,1000,CONT_DIF_N,* ++V 5200,2000,CONT_DIF_N,* ++V 600,8000,CONT_DIF_P,n3 ++V 3000,8000,CONT_DIF_P,n3 ++V 1800,7000,CONT_DIF_P,* ++V 4200,9000,CONT_DIF_P,* ++V 4000,4900,CONT_POLY,* ++V 3000,7000,CONT_DIF_P,n3 ++V 4200,8000,CONT_DIF_P,* ++V 1800,4000,CONT_POLY,* ++V 3000,4000,CONT_POLY,* ++V 5000,4000,CONT_POLY,* ++EOF +diff --git a/alliance/src/cells/src/msxlib/aoi22_x1.vbe b/alliance/src/cells/src/msxlib/aoi22_x1.vbe +new file mode 100644 +index 0000000..c6b647e +--- /dev/null ++++ b/alliance/src/cells/src/msxlib/aoi22_x1.vbe +@@ -0,0 +1,44 @@ ++ENTITY aoi22_x1 IS ++GENERIC ( ++ CONSTANT area : NATURAL := 6000; ++ CONSTANT cin_b1 : NATURAL := 6; ++ CONSTANT cin_b2 : NATURAL := 6; ++ CONSTANT cin_a1 : NATURAL := 6; ++ CONSTANT cin_a2 : NATURAL := 6; ++ CONSTANT rdown_b1_z : NATURAL := 2170; ++ CONSTANT rdown_b2_z : NATURAL := 2160; ++ CONSTANT rdown_a1_z : NATURAL := 2190; ++ CONSTANT rdown_a2_z : NATURAL := 2190; ++ CONSTANT rup_b1_z : NATURAL := 2720; ++ CONSTANT rup_b2_z : NATURAL := 2720; ++ CONSTANT rup_a1_z : NATURAL := 2750; ++ CONSTANT rup_a2_z : NATURAL := 2760; ++ CONSTANT tphl_b1_z : NATURAL := 46; ++ CONSTANT tphl_b2_z : NATURAL := 47; ++ CONSTANT tplh_a2_z : NATURAL := 77; ++ CONSTANT tphl_a1_z : NATURAL := 67; ++ CONSTANT tplh_b2_z : NATURAL := 51; ++ CONSTANT tplh_a1_z : NATURAL := 83; ++ CONSTANT tplh_b1_z : NATURAL := 58; ++ CONSTANT tphl_a2_z : NATURAL := 68; ++ CONSTANT transistors : NATURAL := 8 ++); ++PORT ( ++ b1 : in BIT; ++ b2 : in BIT; ++ a1 : in BIT; ++ a2 : in BIT; ++ z : out BIT; ++ vdd : in BIT; ++ vss : in BIT ++); ++END aoi22_x1; ++ ++ARCHITECTURE behaviour_data_flow OF aoi22_x1 IS ++ ++BEGIN ++ ASSERT ((vdd and not (vss)) = '1') ++ REPORT "power supply is missing on aoi22_x1" ++ SEVERITY WARNING; ++ z <= not (((b1 and b2) or (a1 and a2))) after 1000 ps; ++END; +diff --git a/alliance/src/cells/src/msxlib/aoi22_x2.ap b/alliance/src/cells/src/msxlib/aoi22_x2.ap +new file mode 100644 +index 0000000..4677497 +--- /dev/null ++++ b/alliance/src/cells/src/msxlib/aoi22_x2.ap +@@ -0,0 +1,168 @@ ++V ALLIANCE : 6 ++H aoi22_x2,P, 8/ 8/2014,100 ++A 0,0,11000,10000 ++R 1000,2000,ref_ref,z_20 ++R 9000,5000,ref_ref,a2_50 ++R 9000,4000,ref_ref,a2_40 ++R 7000,5000,ref_ref,a1_50 ++R 4000,5000,ref_ref,b1_50 ++R 5000,6000,ref_ref,b2_60 ++R 2000,6000,ref_ref,b2_60 ++R 1000,7000,ref_ref,z_70 ++R 3000,7000,ref_ref,z_70 ++R 2000,7000,ref_ref,z_70 ++R 4000,6000,ref_ref,b2_60 ++R 2000,2000,ref_ref,z_20 ++R 1000,3000,ref_ref,z_30 ++R 3000,2000,ref_ref,z_20 ++R 1000,6000,ref_ref,z_60 ++R 1000,5000,ref_ref,z_50 ++R 1000,4000,ref_ref,z_40 ++R 6000,5000,ref_ref,a2_50 ++R 10000,5000,ref_ref,a2_50 ++R 7000,6000,ref_ref,a2_60 ++R 8000,6000,ref_ref,a2_60 ++R 9000,6000,ref_ref,a2_60 ++R 2000,5000,ref_ref,b2_50 ++R 5000,5000,ref_ref,b2_50 ++R 3000,6000,ref_ref,b2_60 ++R 2000,4000,ref_ref,b2_40 ++R 4000,7000,ref_ref,z_70 ++R 4000,2000,ref_ref,z_20 ++R 5000,2000,ref_ref,z_20 ++R 4000,4000,ref_ref,b1_40 ++R 4000,3000,ref_ref,b1_30 ++R 3000,5000,ref_ref,b1_50 ++R 7000,4000,ref_ref,a1_40 ++R 7000,3000,ref_ref,a1_30 ++R 8000,5000,ref_ref,a1_50 ++R 6000,6000,ref_ref,a2_60 ++S 9100,700,9900,700,600,*,RIGHT,PTIE ++S 10200,5800,10200,7000,400,*,UP,ALU1 ++S 10200,6000,10200,6600,600,*,DOWN,PDIF ++S 5400,7000,10200,7000,400,*,RIGHT,ALU1 ++S 6800,3900,6800,5200,200,*,UP,POLY ++S 6000,3900,6000,4700,200,*,UP,POLY ++S 4000,3900,4000,4700,200,*,UP,POLY ++S 4800,3900,4800,4700,200,*,UP,POLY ++S 1200,4600,1200,5600,200,*,DOWN,POLY ++S 9600,9300,9600,9700,200,*,DOWN,POLY ++S 8400,9300,8400,9700,200,*,DOWN,POLY ++S 7200,9300,7200,9700,200,*,DOWN,POLY ++S 6000,9300,6000,9700,200,*,DOWN,POLY ++S 4800,9300,4800,9700,200,*,DOWN,POLY ++S 3600,9300,3600,9700,200,*,DOWN,POLY ++S 2400,9300,2400,9700,200,*,DOWN,POLY ++S 1200,9300,1200,9700,200,*,DOWN,POLY ++S 7400,700,7400,2100,400,*,DOWN,ALU1 ++S 5400,1900,5400,3100,400,*,UP,ALU1 ++S 1000,1900,5400,1900,400,*,RIGHT,ALU1 ++S 9000,5000,10100,5000,400,*,RIGHT,ALU1 ++S 6000,6000,9000,6000,400,*,RIGHT,ALU1 ++S 9000,4000,9000,6000,600,*,UP,ALU1 ++S 9000,4000,9000,6000,400,a2,UP,CALU1 ++S 7000,3000,7000,5000,400,a1,DOWN,CALU1 ++S 7000,2900,7000,5000,400,*,DOWN,ALU1 ++S 7000,5100,8100,5100,400,*,RIGHT,ALU1 ++S 1000,2000,5400,2000,400,*,RIGHT,ALU1 ++S 2000,4000,2000,6000,600,*,DOWN,ALU1 ++S 2900,5100,4000,5100,400,*,RIGHT,ALU1 ++S 4000,2900,4000,5000,400,*,DOWN,ALU1 ++S 4000,3000,4000,5000,400,b1,UP,CALU1 ++S 2000,4000,2000,6000,400,b2,UP,CALU1 ++S 6000,5000,6000,6000,600,*,UP,ALU1 ++S 5000,5000,5000,6000,600,*,DOWN,ALU1 ++S 5000,5000,5000,6000,400,b2,UP,CALU1 ++S 6600,7900,6600,9300,400,*,UP,ALU1 ++S 5400,7000,5400,8000,600,*,UP,ALU1 ++S 7800,7000,7800,8100,400,*,DOWN,ALU1 ++S 500,8000,5400,8000,400,*,RIGHT,ALU1 ++S 6000,5000,6000,6000,400,a2,UP,CALU1 ++S 1000,7000,4300,7000,400,*,RIGHT,ALU1 ++S 1000,7100,4300,7100,400,*,RIGHT,ALU1 ++S 9000,7900,9000,9300,400,*,UP,ALU1 ++S 4800,5600,4800,9300,200,4b,DOWN,PTRANS ++S 1200,5600,1200,9300,200,4a,DOWN,PTRANS ++S 3600,5600,3600,9300,200,3b,DOWN,PTRANS ++S 2400,5600,2400,9300,200,3a,DOWN,PTRANS ++S 6000,5600,6000,9300,200,2a,DOWN,PTRANS ++S 7200,5600,7200,9300,200,1a,DOWN,PTRANS ++S 8400,5600,8400,9300,200,1b,DOWN,PTRANS ++S 9600,5600,9600,9300,200,2b,DOWN,PTRANS ++S 4000,300,4000,600,200,*,UP,POLY ++S 4800,300,4800,600,200,*,UP,POLY ++S 6000,300,6000,600,200,*,UP,POLY ++S 6800,300,6800,600,200,*,UP,POLY ++S 7500,800,7500,3700,600,*,UP,NDIF ++S 5400,800,5400,3700,1000,*,UP,NDIF ++S 6000,600,6000,3900,200,6,UP,NTRANS ++S 6800,600,6800,3900,200,5,UP,NTRANS ++S 6400,800,6400,3700,600,n1,UP,NDIF ++S 3300,800,3300,3700,600,*,UP,NDIF ++S 4000,600,4000,3900,200,7,UP,NTRANS ++S 4800,600,4800,3900,200,8,UP,NTRANS ++S 4400,800,4400,3600,600,n2,UP,NDIF ++S 0,9400,11000,9400,1200,vdd,RIGHT,CALU1 ++S 0,5000,11000,5000,10000,aoi22_x2,LEFT,TALU8 ++S 0,2200,11000,2200,5200,*,LEFT,PWELL ++S 0,7600,11000,7600,5600,*,LEFT,NWELL ++S 0,600,11000,600,1200,vss,RIGHT,CALU1 ++S 1000,2000,1000,7000,400,z,DOWN,CALU1 ++S 1000,2000,1000,7000,400,*,DOWN,ALU1 ++S 4200,5800,4200,9100,1000,*,UP,PDIF ++S 3000,5800,3000,9100,1000,*,UP,PDIF ++S 1800,5800,1800,9100,1000,*,UP,PDIF ++S 7200,5200,8400,5200,200,*,RIGHT,POLY ++S 2000,6000,5000,6000,400,*,RIGHT,ALU1 ++S 2400,5200,3600,5200,200,*,RIGHT,POLY ++S 1200,4600,1700,4600,200,*,RIGHT,POLY ++S 5400,5800,5400,9100,1000,*,UP,PDIF ++S 6600,5800,6600,9100,1000,*,UP,PDIF ++S 7800,5800,7800,9100,1000,*,UP,PDIF ++S 9000,5800,9000,9100,1000,*,UP,PDIF ++S 2900,5000,4000,5000,400,*,RIGHT,ALU1 ++S 7000,5000,8100,5000,400,*,RIGHT,ALU1 ++S 10000,5800,10000,9100,400,*,UP,PDIF ++S 800,5800,800,9100,400,*,UP,PDIF ++S 7000,6000,7000,6000,400,a2,LEFT,CALU1 ++S 8000,6000,8000,6000,400,a2,LEFT,CALU1 ++S 10000,5000,10000,5000,400,a2,LEFT,CALU1 ++S 8000,5000,8000,5000,400,a1,LEFT,CALU1 ++S 3000,6000,3000,6000,400,b2,LEFT,CALU1 ++S 4000,6000,4000,6000,400,b2,LEFT,CALU1 ++S 3000,5000,3000,5000,400,b1,LEFT,CALU1 ++S 2000,7000,2000,7000,400,z,LEFT,CALU1 ++S 3000,7000,3000,7000,400,z,LEFT,CALU1 ++S 4000,7000,4000,7000,400,z,LEFT,CALU1 ++S 2000,2000,2000,2000,400,z,LEFT,CALU1 ++S 3000,2000,3000,2000,400,z,LEFT,CALU1 ++S 4000,2000,4000,2000,400,z,LEFT,CALU1 ++S 5000,2000,5000,2000,400,z,LEFT,CALU1 ++V 10000,700,CONT_BODY_P,* ++V 9000,700,CONT_BODY_P,* ++V 10200,6700,CONT_DIF_P,n3 ++V 10200,5900,CONT_DIF_P,n3 ++V 9400,5000,CONT_POLY,* ++V 7400,2000,CONT_DIF_N,* ++V 6600,8000,CONT_DIF_P,* ++V 5400,7000,CONT_DIF_P,n3 ++V 9000,8000,CONT_DIF_P,* ++V 7800,7000,CONT_DIF_P,n3 ++V 5000,5000,CONT_POLY,* ++V 600,8000,CONT_DIF_P,n3 ++V 3000,8000,CONT_DIF_P,n3 ++V 5400,8000,CONT_DIF_P,n3 ++V 7800,8000,CONT_DIF_P,n3 ++V 6000,5000,CONT_POLY,* ++V 2000,4400,CONT_POLY,* ++V 3800,5000,CONT_POLY,* ++V 6600,9000,CONT_DIF_P,* ++V 9000,9000,CONT_DIF_P,* ++V 1800,7000,CONT_DIF_P,* ++V 4200,7000,CONT_DIF_P,* ++V 5400,2000,CONT_DIF_N,* ++V 7400,1000,CONT_DIF_N,* ++V 3400,1000,CONT_DIF_N,* ++V 5400,3000,CONT_DIF_N,* ++V 7100,5000,CONT_POLY,* ++EOF +diff --git a/alliance/src/cells/src/msxlib/aoi22_x2.vbe b/alliance/src/cells/src/msxlib/aoi22_x2.vbe +new file mode 100644 +index 0000000..329506d +--- /dev/null ++++ b/alliance/src/cells/src/msxlib/aoi22_x2.vbe +@@ -0,0 +1,44 @@ ++ENTITY aoi22_x2 IS ++GENERIC ( ++ CONSTANT area : NATURAL := 11000; ++ CONSTANT cin_b1 : NATURAL := 11; ++ CONSTANT cin_b2 : NATURAL := 12; ++ CONSTANT cin_a1 : NATURAL := 11; ++ CONSTANT cin_a2 : NATURAL := 12; ++ CONSTANT rdown_b1_z : NATURAL := 1110; ++ CONSTANT rdown_b2_z : NATURAL := 1110; ++ CONSTANT rdown_a1_z : NATURAL := 1120; ++ CONSTANT rdown_a2_z : NATURAL := 1120; ++ CONSTANT rup_b1_z : NATURAL := 1430; ++ CONSTANT rup_b2_z : NATURAL := 1430; ++ CONSTANT rup_a1_z : NATURAL := 1450; ++ CONSTANT rup_a2_z : NATURAL := 1450; ++ CONSTANT tphl_b1_z : NATURAL := 44; ++ CONSTANT tphl_b2_z : NATURAL := 46; ++ CONSTANT tplh_a2_z : NATURAL := 75; ++ CONSTANT tphl_a1_z : NATURAL := 64; ++ CONSTANT tplh_b2_z : NATURAL := 51; ++ CONSTANT tplh_a1_z : NATURAL := 81; ++ CONSTANT tplh_b1_z : NATURAL := 57; ++ CONSTANT tphl_a2_z : NATURAL := 66; ++ CONSTANT transistors : NATURAL := 12 ++); ++PORT ( ++ b1 : in BIT; ++ b2 : in BIT; ++ a1 : in BIT; ++ a2 : in BIT; ++ z : out BIT; ++ vdd : in BIT; ++ vss : in BIT ++); ++END aoi22_x2; ++ ++ARCHITECTURE behaviour_data_flow OF aoi22_x2 IS ++ ++BEGIN ++ ASSERT ((vdd and not (vss)) = '1') ++ REPORT "power supply is missing on aoi22_x2" ++ SEVERITY WARNING; ++ z <= not (((b1 and b2) or (a1 and a2))) after 1000 ps; ++END; +diff --git a/alliance/src/cells/src/msxlib/aon21_x1.ap b/alliance/src/cells/src/msxlib/aon21_x1.ap +new file mode 100644 +index 0000000..bfdcb14 +--- /dev/null ++++ b/alliance/src/cells/src/msxlib/aon21_x1.ap +@@ -0,0 +1,110 @@ ++V ALLIANCE : 6 ++H aon21_x1,P, 8/ 8/2014,100 ++A 0,0,7000,10000 ++R 6000,6000,ref_ref,a2_60 ++R 5000,5000,ref_ref,a2_50 ++R 5000,7000,ref_ref,b_70 ++R 4000,6000,ref_ref,b_60 ++R 4000,5000,ref_ref,b_50 ++R 6000,4000,ref_ref,a1_40 ++R 6000,7000,ref_ref,a2_70 ++R 4000,7000,ref_ref,b_70 ++R 5000,6000,ref_ref,a2_60 ++R 5000,4000,ref_ref,a1_40 ++R 6000,5000,ref_ref,a1_50 ++R 5000,3000,ref_ref,a1_30 ++R 1000,7000,ref_ref,z_70 ++R 1000,6000,ref_ref,z_60 ++R 1000,5000,ref_ref,z_50 ++R 1000,4000,ref_ref,z_40 ++R 1000,3000,ref_ref,z_30 ++R 2000,7000,ref_ref,z_70 ++R 5000,2000,ref_ref,a1_20 ++S 1100,700,1900,700,600,*,RIGHT,PTIE ++S 5800,8900,5800,9300,200,*,DOWN,POLY ++S 4600,8900,4600,9300,200,*,DOWN,POLY ++S 3400,8900,3400,9300,200,*,DOWN,POLY ++S 5800,6300,5800,8900,200,1,DOWN,PTRANS ++S 6200,6500,6200,8700,400,*,UP,PDIF ++S 3000,6500,3000,8700,400,*,UP,PDIF ++S 4600,6300,4600,8900,200,2,DOWN,PTRANS ++S 3400,6300,3400,8900,200,3,DOWN,PTRANS ++S 4000,6500,4000,8700,600,*,UP,PDIF ++S 6100,2700,6100,3500,600,*,UP,NDIF ++S 4200,2700,4200,3500,400,*,UP,NDIF ++S 4600,2500,4600,3700,200,5,UP,NTRANS ++S 5400,2500,5400,3700,200,4,UP,NTRANS ++S 5000,2700,5000,3500,600,n1,UP,NDIF ++S 5400,2100,5400,2500,200,*,UP,POLY ++S 4600,2100,4600,2500,200,*,UP,POLY ++S 3400,3000,3400,3700,200,6,UP,NTRANS ++S 4000,3200,4000,3500,1000,*,UP,NDIF ++S 3400,2600,3400,3000,200,*,UP,POLY ++S 4600,3700,4600,6300,200,*,DOWN,POLY ++S 1600,3700,1600,5100,200,*,UP,POLY ++S 3400,3700,3400,6300,200,*,DOWN,POLY ++S 4000,3300,4000,4000,400,*,DOWN,ALU1 ++S 5800,4100,5800,6300,200,*,UP,POLY ++S 5400,4100,5800,4100,200,*,RIGHT,POLY ++S 1200,5100,1200,6300,200,*,DOWN,POLY ++S 1600,2300,1600,2700,200,*,UP,POLY ++S 1000,2900,1000,7100,400,*,DOWN,ALU1 ++S 1000,3000,1000,7000,400,z,DOWN,CALU1 ++S 2500,2900,2500,3500,1200,*,UP,NDIF ++S 1600,2700,1600,3700,200,5,UP,NTRANS ++S 1200,2900,1200,3500,400,*,DOWN,NDIF ++S 5200,6500,5200,8800,600,*,UP,PDIF ++S 1200,8300,1200,8700,200,*,DOWN,POLY ++S 800,6500,800,8100,400,*,UP,PDIF ++S 1700,6500,1700,8100,400,*,UP,PDIF ++S 1200,6300,1200,8300,200,3,DOWN,PTRANS ++S 1800,7700,1800,8100,600,*,UP,PDIF ++S 4000,7000,5100,7000,400,*,RIGHT,ALU1 ++S 3900,8000,6500,8000,400,*,RIGHT,ALU1 ++S 4000,7100,5100,7100,400,*,RIGHT,ALU1 ++S 5000,5000,5000,6000,400,a2,DOWN,CALU1 ++S 5000,4800,5000,6000,400,*,UP,ALU1 ++S 5000,6000,6000,6000,600,*,RIGHT,ALU1 ++S 6000,6000,6000,7100,400,*,UP,ALU1 ++S 6000,6000,6000,7000,400,a2,UP,CALU1 ++S 3900,4800,3900,5000,600,*,UP,ALU1 ++S 4000,5000,4000,7000,400,b,DOWN,CALU1 ++S 4000,5000,4000,7000,400,*,DOWN,ALU1 ++S 6000,4000,6000,5000,400,a1,UP,CALU1 ++S 6000,4000,6000,5000,600,*,UP,ALU1 ++S 5000,4000,6000,4000,400,*,RIGHT,ALU1 ++S 6000,700,6000,3100,400,*,UP,ALU1 ++S 5000,7000,5000,7000,400,b,LEFT,CALU1 ++S 0,600,7000,600,1200,vss,RIGHT,CALU1 ++S 0,9400,7000,9400,1200,vdd,RIGHT,CALU1 ++S 0,5000,7000,5000,10000,aon21_x1,LEFT,TALU8 ++S 0,2200,7000,2200,5200,*,LEFT,PWELL ++S 0,7600,7000,7600,5600,*,LEFT,NWELL ++S 2200,700,2200,3100,400,*,UP,ALU1 ++S 1200,5100,1900,5100,200,*,RIGHT,POLY ++S 2000,7000,2000,7000,400,z,LEFT,CALU1 ++S 2800,4000,4000,4000,400,*,RIGHT,ALU1 ++S 1800,4900,2800,4900,400,*,RIGHT,ALU1 ++S 1800,7900,1800,9300,400,*,UP,ALU1 ++S 600,7000,2000,7000,600,*,LEFT,ALU1 ++S 2800,4000,2800,6700,400,*,DOWN,ALU1 ++S 5000,2000,5000,4000,600,*,DOWN,ALU1 ++S 5000,2000,5000,4000,400,a1,DOWN,CALU1 ++V 2000,700,CONT_BODY_P,* ++V 1000,700,CONT_BODY_P,* ++V 1000,9300,CONT_BODY_N,* ++V 4000,3400,CONT_DIF_N,zn ++V 1000,3400,CONT_DIF_N,* ++V 5000,4900,CONT_POLY,* ++V 6000,4900,CONT_POLY,* ++V 3800,4900,CONT_POLY,* ++V 6000,3000,CONT_DIF_N,* ++V 5200,9000,CONT_DIF_P,* ++V 6400,8000,CONT_DIF_P,n2 ++V 4000,8000,CONT_DIF_P,n2 ++V 1800,8000,CONT_DIF_P,* ++V 2200,3000,CONT_DIF_N,* ++V 1900,4900,CONT_POLY,zn ++V 2800,6600,CONT_DIF_P,zn ++V 600,7000,CONT_DIF_P,* ++EOF +diff --git a/alliance/src/cells/src/msxlib/aon21_x1.vbe b/alliance/src/cells/src/msxlib/aon21_x1.vbe +new file mode 100644 +index 0000000..b1daf14 +--- /dev/null ++++ b/alliance/src/cells/src/msxlib/aon21_x1.vbe +@@ -0,0 +1,38 @@ ++ENTITY aon21_x1 IS ++GENERIC ( ++ CONSTANT area : NATURAL := 7000; ++ CONSTANT cin_a1 : NATURAL := 5; ++ CONSTANT cin_a2 : NATURAL := 5; ++ CONSTANT cin_b : NATURAL := 4; ++ CONSTANT rdown_a1_z : NATURAL := 2310; ++ CONSTANT rdown_a2_z : NATURAL := 2300; ++ CONSTANT rdown_b_z : NATURAL := 2290; ++ CONSTANT rup_a1_z : NATURAL := 2980; ++ CONSTANT rup_a2_z : NATURAL := 2980; ++ CONSTANT rup_b_z : NATURAL := 2960; ++ CONSTANT tphh_a1_z : NATURAL := 94; ++ CONSTANT tphh_b_z : NATURAL := 80; ++ CONSTANT tpll_b_z : NATURAL := 91; ++ CONSTANT tphh_a2_z : NATURAL := 95; ++ CONSTANT tpll_a2_z : NATURAL := 113; ++ CONSTANT tpll_a1_z : NATURAL := 123; ++ CONSTANT transistors : NATURAL := 8 ++); ++PORT ( ++ a1 : in BIT; ++ a2 : in BIT; ++ b : in BIT; ++ z : out BIT; ++ vdd : in BIT; ++ vss : in BIT ++); ++END aon21_x1; ++ ++ARCHITECTURE behaviour_data_flow OF aon21_x1 IS ++ ++BEGIN ++ ASSERT ((vdd and not (vss)) = '1') ++ REPORT "power supply is missing on aon21_x1" ++ SEVERITY WARNING; ++ z <= ((a1 and a2) or b) after 1200 ps; ++END; +diff --git a/alliance/src/cells/src/msxlib/aon21_x2.ap b/alliance/src/cells/src/msxlib/aon21_x2.ap +new file mode 100644 +index 0000000..cb0ae11 +--- /dev/null ++++ b/alliance/src/cells/src/msxlib/aon21_x2.ap +@@ -0,0 +1,119 @@ ++V ALLIANCE : 6 ++H aon21_x2,P, 8/ 8/2014,100 ++A 0,0,7000,10000 ++R 6000,6000,ref_ref,a2_60 ++R 5000,5000,ref_ref,a2_50 ++R 5000,7000,ref_ref,b_70 ++R 4000,6000,ref_ref,b_60 ++R 4000,5000,ref_ref,b_50 ++R 6000,4000,ref_ref,a1_40 ++R 6000,7000,ref_ref,a2_70 ++R 4000,7000,ref_ref,b_70 ++R 5000,6000,ref_ref,a2_60 ++R 5000,4000,ref_ref,a1_40 ++R 6000,5000,ref_ref,a1_50 ++R 5000,3000,ref_ref,a1_30 ++R 1000,7000,ref_ref,z_70 ++R 1000,6000,ref_ref,z_60 ++R 1000,5000,ref_ref,z_50 ++R 1000,4000,ref_ref,z_40 ++R 1000,3000,ref_ref,z_30 ++R 1000,2000,ref_ref,z_20 ++R 2000,7000,ref_ref,z_70 ++R 5000,2000,ref_ref,a1_20 ++S 1100,700,1900,700,600,*,RIGHT,PTIE ++S 4600,1400,4600,1800,200,*,UP,POLY ++S 5400,1400,5400,1800,200,*,UP,POLY ++S 6100,2000,6100,3300,600,*,UP,NDIF ++S 5400,1800,5400,3500,200,4,UP,NTRANS ++S 5000,2000,5000,3300,600,n1,UP,NDIF ++S 4600,1800,4600,3500,200,5,UP,NTRANS ++S 4200,2000,4200,3300,400,*,UP,NDIF ++S 1600,1200,1600,1600,200,*,UP,POLY ++S 1000,2500,1000,3100,600,*,UP,NDIF ++S 1200,1800,1200,3300,400,*,DOWN,NDIF ++S 1600,1600,1600,3500,200,5,UP,NTRANS ++S 2500,1800,2500,3300,1200,*,UP,NDIF ++S 4000,3100,4000,4000,400,*,DOWN,ALU1 ++S 4600,3500,4600,5500,200,*,DOWN,POLY ++S 3400,2100,3400,2500,200,*,UP,POLY ++S 3400,2500,3400,3500,200,6,UP,NTRANS ++S 4000,2700,4000,3300,1000,*,UP,NDIF ++S 5800,3900,5800,4700,200,*,UP,POLY ++S 5400,3900,5800,3900,200,*,RIGHT,POLY ++S 3400,3300,3400,5500,200,*,DOWN,POLY ++S 4000,7000,5100,7000,400,*,RIGHT,ALU1 ++S 3900,8000,6500,8000,400,*,RIGHT,ALU1 ++S 4000,7100,5100,7100,400,*,RIGHT,ALU1 ++S 5000,5000,5000,6000,400,a2,DOWN,CALU1 ++S 5000,4800,5000,6000,400,*,UP,ALU1 ++S 5000,6000,6000,6000,600,*,RIGHT,ALU1 ++S 6000,6000,6000,7100,400,*,UP,ALU1 ++S 6000,6000,6000,7000,400,a2,UP,CALU1 ++S 3900,4800,3900,5000,600,*,UP,ALU1 ++S 4000,5000,4000,7000,400,b,DOWN,CALU1 ++S 4000,5000,4000,7000,400,*,DOWN,ALU1 ++S 6000,4000,6000,5000,400,a1,UP,CALU1 ++S 6000,4000,6000,5000,600,*,UP,ALU1 ++S 5000,4000,6000,4000,400,*,RIGHT,ALU1 ++S 6000,700,6000,3100,400,*,UP,ALU1 ++S 5000,7000,5000,7000,400,b,LEFT,CALU1 ++S 0,600,7000,600,1200,vss,RIGHT,CALU1 ++S 0,9400,7000,9400,1200,vdd,RIGHT,CALU1 ++S 0,5000,7000,5000,10000,aon21_x2,LEFT,TALU8 ++S 0,2200,7000,2200,5200,*,LEFT,PWELL ++S 0,7600,7000,7600,5600,*,LEFT,NWELL ++S 1000,2000,1000,7000,400,z,DOWN,CALU1 ++S 2200,700,2200,3100,400,*,UP,ALU1 ++S 1600,3600,1600,5100,200,*,UP,POLY ++S 1200,5100,1900,5100,200,*,RIGHT,POLY ++S 2000,7000,2000,7000,400,z,LEFT,CALU1 ++S 2800,4000,4000,4000,400,*,RIGHT,ALU1 ++S 1800,4900,2800,4900,400,*,RIGHT,ALU1 ++S 1800,7900,1800,9300,400,*,UP,ALU1 ++S 600,7000,2000,7000,600,*,LEFT,ALU1 ++S 600,6100,600,6900,600,*,DOWN,PDIF ++S 1000,1900,1000,7100,400,*,DOWN,ALU1 ++S 600,6000,1000,6000,600,*,RIGHT,ALU1 ++S 2800,4000,2800,6700,400,*,DOWN,ALU1 ++S 2800,5900,2800,6500,600,*,UP,PDIF ++S 1200,5500,1200,9300,200,3,DOWN,PTRANS ++S 1700,5700,1700,9100,400,*,UP,PDIF ++S 1800,7700,1800,9100,600,*,UP,PDIF ++S 800,5700,800,9100,400,*,UP,PDIF ++S 4000,5700,4000,9100,600,*,UP,PDIF ++S 4600,5500,4600,9300,200,2,DOWN,PTRANS ++S 3400,5500,3400,9300,200,3,DOWN,PTRANS ++S 3000,5700,3000,9100,400,*,UP,PDIF ++S 6200,5700,6200,9100,400,*,UP,PDIF ++S 5800,5500,5800,9300,200,1,DOWN,PTRANS ++S 5200,5700,5200,9100,600,*,UP,PDIF ++S 5800,9300,5800,9700,200,*,DOWN,POLY ++S 4600,9300,4600,9700,200,*,DOWN,POLY ++S 3400,9300,3400,9700,200,*,DOWN,POLY ++S 1200,9300,1200,9700,200,*,DOWN,POLY ++S 5000,2000,5000,4000,600,*,DOWN,ALU1 ++S 5000,2000,5000,4000,400,a1,DOWN,CALU1 ++V 2000,700,CONT_BODY_P,* ++V 1000,700,CONT_BODY_P,* ++V 6000,2100,CONT_DIF_N,* ++V 1000,2400,CONT_DIF_N,* ++V 1000,3200,CONT_DIF_N,* ++V 4000,3200,CONT_DIF_N,zn ++V 5000,4900,CONT_POLY,* ++V 6000,4900,CONT_POLY,* ++V 3800,4900,CONT_POLY,* ++V 6000,3000,CONT_DIF_N,* ++V 5200,9000,CONT_DIF_P,* ++V 6400,8000,CONT_DIF_P,n2 ++V 4000,8000,CONT_DIF_P,n2 ++V 1800,9000,CONT_DIF_P,* ++V 1800,8000,CONT_DIF_P,* ++V 2200,2000,CONT_DIF_N,* ++V 2200,3000,CONT_DIF_N,* ++V 2800,5800,CONT_DIF_P,zn ++V 1900,4900,CONT_POLY,zn ++V 2800,6600,CONT_DIF_P,zn ++V 600,7000,CONT_DIF_P,* ++V 600,6000,CONT_DIF_P,* ++EOF +diff --git a/alliance/src/cells/src/msxlib/aon21_x2.vbe b/alliance/src/cells/src/msxlib/aon21_x2.vbe +new file mode 100644 +index 0000000..cec020d +--- /dev/null ++++ b/alliance/src/cells/src/msxlib/aon21_x2.vbe +@@ -0,0 +1,38 @@ ++ENTITY aon21_x2 IS ++GENERIC ( ++ CONSTANT area : NATURAL := 7000; ++ CONSTANT cin_a1 : NATURAL := 7; ++ CONSTANT cin_a2 : NATURAL := 7; ++ CONSTANT cin_b : NATURAL := 6; ++ CONSTANT rdown_a1_z : NATURAL := 1210; ++ CONSTANT rdown_a2_z : NATURAL := 1210; ++ CONSTANT rdown_b_z : NATURAL := 1210; ++ CONSTANT rup_a1_z : NATURAL := 1570; ++ CONSTANT rup_a2_z : NATURAL := 1570; ++ CONSTANT rup_b_z : NATURAL := 1560; ++ CONSTANT tphh_a1_z : NATURAL := 97; ++ CONSTANT tphh_b_z : NATURAL := 83; ++ CONSTANT tpll_b_z : NATURAL := 94; ++ CONSTANT tphh_a2_z : NATURAL := 98; ++ CONSTANT tpll_a2_z : NATURAL := 116; ++ CONSTANT tpll_a1_z : NATURAL := 126; ++ CONSTANT transistors : NATURAL := 8 ++); ++PORT ( ++ a1 : in BIT; ++ a2 : in BIT; ++ b : in BIT; ++ z : out BIT; ++ vdd : in BIT; ++ vss : in BIT ++); ++END aon21_x2; ++ ++ARCHITECTURE behaviour_data_flow OF aon21_x2 IS ++ ++BEGIN ++ ASSERT ((vdd and not (vss)) = '1') ++ REPORT "power supply is missing on aon21_x2" ++ SEVERITY WARNING; ++ z <= ((a1 and a2) or b) after 1200 ps; ++END; +diff --git a/alliance/src/cells/src/msxlib/aon22_x1.ap b/alliance/src/cells/src/msxlib/aon22_x1.ap +new file mode 100644 +index 0000000..a1f15c4 +--- /dev/null ++++ b/alliance/src/cells/src/msxlib/aon22_x1.ap +@@ -0,0 +1,140 @@ ++V ALLIANCE : 6 ++H aon22_x1,P, 8/ 8/2014,100 ++A 0,0,8000,10000 ++R 6000,7000,ref_ref,a2_70 ++R 5000,7000,ref_ref,b2_70 ++R 6000,6000,ref_ref,a2_60 ++R 6000,5000,ref_ref,a2_50 ++R 7000,5000,ref_ref,a1_50 ++R 7000,3000,ref_ref,a1_30 ++R 6000,3000,ref_ref,a1_30 ++R 7000,6000,ref_ref,a2_60 ++R 6000,4000,ref_ref,a2_40 ++R 4000,3000,ref_ref,b1_30 ++R 4000,5000,ref_ref,b1_50 ++R 5000,6000,ref_ref,b2_60 ++R 7000,4000,ref_ref,a1_40 ++R 4000,4000,ref_ref,b1_40 ++R 5000,3000,ref_ref,b1_30 ++R 4000,6000,ref_ref,b2_60 ++R 5000,5000,ref_ref,b2_50 ++R 5000,4000,ref_ref,b2_40 ++R 2000,6000,ref_ref,z_60 ++R 1000,6000,ref_ref,z_60 ++R 1000,5000,ref_ref,z_50 ++R 1000,4000,ref_ref,z_40 ++R 1000,3000,ref_ref,z_30 ++R 1000,2000,ref_ref,z_20 ++S 2100,9300,2900,9300,600,*,RIGHT,NTIE ++S 1100,700,1900,700,600,*,RIGHT,PTIE ++S 6200,5900,6200,9100,600,*,UP,PDIF ++S 6000,4000,6000,7000,400,a2,DOWN,CALU1 ++S 5000,4000,5000,7000,400,b2,DOWN,CALU1 ++S 5000,3900,5000,7100,400,*,DOWN,ALU1 ++S 6000,3900,6000,7100,400,*,UP,ALU1 ++S 7400,7300,7400,8100,600,*,DOWN,PDIF ++S 7400,7000,7400,8000,400,*,DOWN,ALU1 ++S 2500,8000,7400,8000,400,*,RIGHT,ALU1 ++S 4000,3000,4000,5000,400,b1,UP,CALU1 ++S 4000,3000,4000,3900,400,*,UP,ALU1 ++S 4000,2900,5100,2900,400,*,LEFT,ALU1 ++S 3000,2000,5300,2000,400,*,RIGHT,ALU1 ++S 7200,700,7200,2100,400,*,UP,ALU1 ++S 6000,6000,7100,6000,400,*,RIGHT,ALU1 ++S 3900,6000,5000,6000,400,*,RIGHT,ALU1 ++S 3000,2000,3000,7000,400,*,DOWN,ALU1 ++S 5900,2900,7000,2900,400,*,RIGHT,ALU1 ++S 5900,3000,7000,3000,400,*,RIGHT,ALU1 ++S 7000,3000,7000,5000,400,a1,UP,CALU1 ++S 7000,3000,7000,5100,400,*,UP,ALU1 ++S 7000,6000,7000,6000,400,a2,LEFT,CALU1 ++S 6000,3000,6000,3000,400,a1,LEFT,CALU1 ++S 5000,3000,5000,3000,400,b1,LEFT,CALU1 ++S 4000,6000,4000,6000,400,b2,LEFT,CALU1 ++S 4000,3000,5100,3000,400,*,LEFT,ALU1 ++S 4000,4900,4000,5100,400,*,UP,ALU1 ++S 1000,6000,2000,6000,600,*,LEFT,ALU1 ++S 2000,6000,2000,6000,400,z,LEFT,CALU1 ++S 3000,7000,3900,7000,400,*,RIGHT,ALU1 ++S 600,8400,600,9300,400,*,UP,ALU1 ++S 1800,4900,3000,4900,400,*,RIGHT,ALU1 ++S 1700,5900,1700,6900,400,*,DOWN,ALU1 ++S 6600,1300,6600,1700,200,*,UP,POLY ++S 5800,1300,5800,1700,200,*,UP,POLY ++S 4600,1300,4600,1700,200,*,UP,POLY ++S 3800,1300,3800,1700,200,*,UP,POLY ++S 6600,2900,6600,3900,200,*,UP,POLY ++S 5800,2900,5800,4700,200,*,UP,POLY ++S 4600,2900,4600,5100,200,*,DOWN,POLY ++S 3800,2900,3800,4000,200,*,UP,POLY ++S 1100,5100,1900,5100,200,*,RIGHT,POLY ++S 1100,7500,1100,7900,200,*,UP,POLY ++S 6800,8300,6800,8700,200,*,DOWN,POLY ++S 5600,8300,5600,8700,200,*,DOWN,POLY ++S 3200,8300,3200,8700,200,*,DOWN,POLY ++S 4400,8300,4400,8700,200,*,DOWN,POLY ++S 4200,1900,4200,2700,600,n2,UP,NDIF ++S 5200,1900,5200,2700,1000,*,UP,NDIF ++S 7300,1900,7300,2700,600,*,UP,NDIF ++S 6200,1900,6200,2700,600,n1,UP,NDIF ++S 6600,1700,6600,2900,200,6,UP,NTRANS ++S 3800,1700,3800,2900,200,5,UP,NTRANS ++S 4600,1700,4600,2900,200,7,UP,NTRANS ++S 5800,1700,5800,2900,200,8,UP,NTRANS ++S 600,5700,600,8600,400,*,DOWN,PDIF ++S 500,5700,500,8600,400,*,DOWN,PDIF ++S 3800,5900,3800,8100,1000,*,UP,PDIF ++S 5000,5900,5000,8100,1000,*,UP,PDIF ++S 6800,5700,6800,8300,200,2,DOWN,PTRANS ++S 2800,5900,2800,8100,400,*,UP,PDIF ++S 1100,5500,1100,7500,200,1z,DOWN,PTRANS ++S 4400,5700,4400,8300,200,3,DOWN,PTRANS ++S 3200,5700,3200,8300,200,1,DOWN,PTRANS ++S 1500,5700,1500,7300,400,*,UP,PDIF ++S 1700,6100,1700,6700,600,*,UP,PDIF ++S 5600,5700,5600,8300,200,4,DOWN,PTRANS ++S 7200,5900,7200,8100,400,*,UP,PDIF ++S 0,600,8000,600,1200,vss,RIGHT,CALU1 ++S 0,5000,8000,5000,10000,aon22_x1,LEFT,TALU8 ++S 0,2200,8000,2200,5200,*,LEFT,PWELL ++S 0,7600,8000,7600,5600,*,LEFT,NWELL ++S 0,9400,8000,9400,1200,vdd,RIGHT,CALU1 ++S 1600,2900,1600,3900,200,2z,UP,NTRANS ++S 1200,3100,1200,3700,400,*,UP,NDIF ++S 1600,2500,1600,2900,200,*,DOWN,POLY ++S 2500,1900,2500,3700,1200,*,UP,NDIF ++S 2200,700,2200,3100,400,*,DOWN,ALU1 ++S 3200,1900,3200,2700,600,*,UP,NDIF ++S 3200,4300,3500,4300,200,*,RIGHT,POLY ++S 3200,4300,3200,5700,200,*,DOWN,POLY ++S 4400,5000,4400,5700,200,*,DOWN,POLY ++S 5600,5000,5600,5700,200,*,DOWN,POLY ++S 6800,3800,6800,5700,200,*,DOWN,POLY ++S 3800,4100,4000,4100,600,*,RIGHT,ALU1 ++S 1600,3900,1600,5100,200,*,UP,POLY ++S 1000,1900,1000,6000,400,*,DOWN,ALU1 ++S 1000,2000,1000,6000,400,z,DOWN,CALU1 ++V 3000,9300,CONT_BODY_N,* ++V 2000,9300,CONT_BODY_N,* ++V 2000,700,CONT_BODY_P,* ++V 1000,700,CONT_BODY_P,* ++V 7400,7100,CONT_DIF_P,n3 ++V 7400,7900,CONT_DIF_P,n3 ++V 6200,9000,CONT_DIF_P,* ++V 5000,4000,CONT_POLY,* ++V 6000,4900,CONT_POLY,* ++V 7000,4000,CONT_POLY,* ++V 1900,4900,CONT_POLY,zn ++V 7200,2000,CONT_DIF_N,* ++V 5200,2000,CONT_DIF_N,zn ++V 2200,2000,CONT_DIF_N,* ++V 1700,6000,CONT_DIF_P,* ++V 600,8500,CONT_DIF_P,* ++V 1700,6800,CONT_DIF_P,* ++V 2600,8000,CONT_DIF_P,n3 ++V 5000,8000,CONT_DIF_P,n3 ++V 3800,7000,CONT_DIF_P,zn ++V 1000,3600,CONT_DIF_N,* ++V 2200,3000,CONT_DIF_N,* ++V 3800,4100,CONT_POLY,* ++EOF +diff --git a/alliance/src/cells/src/msxlib/aon22_x1.vbe b/alliance/src/cells/src/msxlib/aon22_x1.vbe +new file mode 100644 +index 0000000..ffdc6d2 +--- /dev/null ++++ b/alliance/src/cells/src/msxlib/aon22_x1.vbe +@@ -0,0 +1,44 @@ ++ENTITY aon22_x1 IS ++GENERIC ( ++ CONSTANT area : NATURAL := 8000; ++ CONSTANT cin_b1 : NATURAL := 5; ++ CONSTANT cin_b2 : NATURAL := 5; ++ CONSTANT cin_a2 : NATURAL := 5; ++ CONSTANT cin_a1 : NATURAL := 5; ++ CONSTANT rdown_b1_z : NATURAL := 2310; ++ CONSTANT rdown_b2_z : NATURAL := 2310; ++ CONSTANT rdown_a2_z : NATURAL := 2320; ++ CONSTANT rdown_a1_z : NATURAL := 2320; ++ CONSTANT rup_b1_z : NATURAL := 2960; ++ CONSTANT rup_b2_z : NATURAL := 2960; ++ CONSTANT rup_a2_z : NATURAL := 2990; ++ CONSTANT rup_a1_z : NATURAL := 2990; ++ CONSTANT tphh_b1_z : NATURAL := 87; ++ CONSTANT tpll_a2_z : NATURAL := 133; ++ CONSTANT tphh_b2_z : NATURAL := 88; ++ CONSTANT tpll_a1_z : NATURAL := 142; ++ CONSTANT tpll_b2_z : NATURAL := 104; ++ CONSTANT tphh_a1_z : NATURAL := 114; ++ CONSTANT tpll_b1_z : NATURAL := 114; ++ CONSTANT tphh_a2_z : NATURAL := 115; ++ CONSTANT transistors : NATURAL := 10 ++); ++PORT ( ++ b1 : in BIT; ++ b2 : in BIT; ++ a2 : in BIT; ++ a1 : in BIT; ++ z : out BIT; ++ vdd : in BIT; ++ vss : in BIT ++); ++END aon22_x1; ++ ++ARCHITECTURE behaviour_data_flow OF aon22_x1 IS ++ ++BEGIN ++ ASSERT ((vdd and not (vss)) = '1') ++ REPORT "power supply is missing on aon22_x1" ++ SEVERITY WARNING; ++ z <= ((b1 and b2) or (a2 and a1)) after 1200 ps; ++END; +diff --git a/alliance/src/cells/src/msxlib/aon22_x2.ap b/alliance/src/cells/src/msxlib/aon22_x2.ap +new file mode 100644 +index 0000000..c7a228c +--- /dev/null ++++ b/alliance/src/cells/src/msxlib/aon22_x2.ap +@@ -0,0 +1,142 @@ ++V ALLIANCE : 6 ++H aon22_x2,P, 8/ 8/2014,100 ++A 0,0,9000,10000 ++R 1000,6000,ref_ref,z_60 ++R 2000,7000,ref_ref,z_70 ++R 2000,6000,ref_ref,z_60 ++R 2000,5000,ref_ref,z_50 ++R 2000,4000,ref_ref,z_40 ++R 2000,3000,ref_ref,z_30 ++R 2000,2000,ref_ref,z_20 ++R 5000,5000,ref_ref,b1_50 ++R 6000,6000,ref_ref,b2_60 ++R 8000,4000,ref_ref,a1_40 ++R 5000,4000,ref_ref,b1_40 ++R 6000,3000,ref_ref,b1_30 ++R 5000,6000,ref_ref,b2_60 ++R 6000,5000,ref_ref,b2_50 ++R 6000,4000,ref_ref,b2_40 ++R 7000,6000,ref_ref,a2_60 ++R 7000,5000,ref_ref,a2_50 ++R 8000,5000,ref_ref,a1_50 ++R 8000,3000,ref_ref,a1_30 ++R 7000,3000,ref_ref,a1_30 ++R 8000,6000,ref_ref,a2_60 ++R 7000,4000,ref_ref,a2_40 ++R 5000,3000,ref_ref,b1_30 ++R 6000,7000,ref_ref,b2_70 ++R 7000,7000,ref_ref,a2_70 ++S 1100,700,1900,700,600,*,RIGHT,PTIE ++S 1200,5500,1200,9300,200,1z,DOWN,PTRANS ++S 5400,5000,5400,5500,200,*,DOWN,POLY ++S 5600,3400,5600,5100,200,*,DOWN,POLY ++S 2800,4900,4000,4900,400,*,RIGHT,ALU1 ++S 1200,5100,2900,5100,200,*,RIGHT,POLY ++S 1900,6000,1900,7100,600,*,UP,ALU1 ++S 2000,1900,2000,6000,400,*,DOWN,ALU1 ++S 900,6000,2000,6000,400,*,LEFT,ALU1 ++S 1000,6000,1000,6000,400,z,LEFT,CALU1 ++S 1800,6100,1800,6700,600,*,UP,PDIF ++S 2000,2000,2000,7000,400,z,DOWN,CALU1 ++S 600,5700,600,9100,600,*,DOWN,PDIF ++S 1600,5700,1600,9100,400,*,UP,PDIF ++S 1200,9300,1200,9700,200,*,UP,POLY ++S 600,6900,600,9300,400,*,UP,ALU1 ++S 4000,7000,4900,7000,400,*,RIGHT,ALU1 ++S 3200,700,3200,3100,400,*,DOWN,ALU1 ++S 4200,9300,4200,9700,200,*,DOWN,POLY ++S 5400,9300,5400,9700,200,*,DOWN,POLY ++S 6600,9300,6600,9700,200,*,DOWN,POLY ++S 7800,9300,7800,9700,200,*,DOWN,POLY ++S 8200,5700,8200,9100,400,*,UP,PDIF ++S 6000,5700,6000,9100,1000,*,UP,PDIF ++S 7200,5700,7200,9100,1000,*,UP,PDIF ++S 7800,5500,7800,9300,200,2,DOWN,PTRANS ++S 6600,5500,6600,9300,200,4,DOWN,PTRANS ++S 3800,5700,3800,9100,400,*,UP,PDIF ++S 4800,5700,4800,9100,1000,*,UP,PDIF ++S 5400,5500,5400,9300,200,3,DOWN,PTRANS ++S 4200,5500,4200,9300,200,1,DOWN,PTRANS ++S 0,5000,9000,5000,10000,aon22_x2,LEFT,TALU8 ++S 0,2200,9000,2200,5200,*,LEFT,PWELL ++S 0,7600,9000,7600,5600,*,LEFT,NWELL ++S 0,9400,9000,9400,1200,vdd,RIGHT,CALU1 ++S 0,600,9000,600,1200,vss,RIGHT,CALU1 ++S 7600,3400,7600,3900,200,*,UP,POLY ++S 6800,3400,6800,4700,200,*,UP,POLY ++S 7800,3800,7800,5500,200,*,DOWN,POLY ++S 7600,1300,7600,1700,200,*,UP,POLY ++S 6800,1300,6800,1700,200,*,UP,POLY ++S 5600,1300,5600,1700,200,*,UP,POLY ++S 4800,1300,4800,1700,200,*,UP,POLY ++S 6600,5000,6600,5500,200,*,DOWN,POLY ++S 4200,4200,4500,4200,200,*,RIGHT,POLY ++S 4200,4200,4200,5500,200,*,DOWN,POLY ++S 8000,6000,8000,6000,400,a2,LEFT,CALU1 ++S 7000,3000,7000,3000,400,a1,LEFT,CALU1 ++S 6000,3000,6000,3000,400,b1,LEFT,CALU1 ++S 5000,6000,5000,6000,400,b2,LEFT,CALU1 ++S 5000,3000,6100,3000,400,*,LEFT,ALU1 ++S 5000,4900,5000,5100,400,*,UP,ALU1 ++S 4000,2000,4000,7000,400,*,DOWN,ALU1 ++S 6900,2900,8000,2900,400,*,RIGHT,ALU1 ++S 6900,3000,8000,3000,400,*,RIGHT,ALU1 ++S 8000,3000,8000,5000,400,a1,UP,CALU1 ++S 8000,3000,8000,5100,400,*,UP,ALU1 ++S 7000,6000,8100,6000,400,*,RIGHT,ALU1 ++S 4900,6000,6000,6000,400,*,RIGHT,ALU1 ++S 5000,3000,5000,5000,400,b1,UP,CALU1 ++S 5000,3000,5000,3900,400,*,UP,ALU1 ++S 5000,2900,6100,2900,400,*,LEFT,ALU1 ++S 4000,2000,6300,2000,400,*,RIGHT,ALU1 ++S 4800,4000,5000,4000,600,*,RIGHT,ALU1 ++S 8200,700,8200,2100,400,*,UP,ALU1 ++S 8300,1900,8300,3200,600,*,UP,NDIF ++S 7200,1900,7200,3200,600,n1,UP,NDIF ++S 7600,1700,7600,3400,200,6,UP,NTRANS ++S 6800,1700,6800,3400,200,8,UP,NTRANS ++S 5200,1900,5200,3200,600,n2,UP,NDIF ++S 4800,1700,4800,3400,200,5,UP,NTRANS ++S 5600,1700,5600,3400,200,7,UP,NTRANS ++S 6200,1900,6200,3200,1000,*,UP,NDIF ++S 4200,1900,4200,3200,600,*,UP,NDIF ++S 4800,3400,4800,4000,200,*,UP,POLY ++S 2600,1300,2600,1700,200,*,DOWN,POLY ++S 2200,1900,2200,3400,400,*,UP,NDIF ++S 2600,1700,2600,3600,200,2z,UP,NTRANS ++S 2000,2600,2000,3200,600,*,UP,NDIF ++S 3500,1900,3500,3400,1200,*,UP,NDIF ++S 2600,3600,2600,5100,200,*,UP,POLY ++S 3500,8000,8400,8000,400,*,RIGHT,ALU1 ++S 8400,7200,8400,7800,600,*,DOWN,PDIF ++S 8400,7000,8400,8000,400,*,DOWN,ALU1 ++S 6000,3900,6000,7100,400,*,DOWN,ALU1 ++S 6000,4000,6000,7000,400,b2,DOWN,CALU1 ++S 7000,3900,7000,7100,400,*,UP,ALU1 ++S 7000,4000,7000,7000,400,a2,DOWN,CALU1 ++V 2700,9300,CONT_BODY_N,* ++V 2000,700,CONT_BODY_P,* ++V 1000,700,CONT_BODY_P,* ++V 2900,4900,CONT_POLY,zn ++V 6200,2000,CONT_DIF_N,zn ++V 4800,7000,CONT_DIF_P,zn ++V 1800,6800,CONT_DIF_P,* ++V 1800,6000,CONT_DIF_P,* ++V 600,9000,CONT_DIF_P,* ++V 600,7000,CONT_DIF_P,* ++V 600,8000,CONT_DIF_P,* ++V 3200,3000,CONT_DIF_N,* ++V 3200,2000,CONT_DIF_N,* ++V 3600,8000,CONT_DIF_P,n3 ++V 6000,8000,CONT_DIF_P,n3 ++V 7200,9000,CONT_DIF_P,* ++V 8200,2000,CONT_DIF_N,* ++V 7000,4900,CONT_POLY,* ++V 4800,4000,CONT_POLY,* ++V 6000,4000,CONT_POLY,* ++V 8000,4000,CONT_POLY,* ++V 2000,2500,CONT_DIF_N,* ++V 2000,3300,CONT_DIF_N,* ++V 8400,7100,CONT_DIF_P,n3 ++V 8400,7900,CONT_DIF_P,n3 ++EOF +diff --git a/alliance/src/cells/src/msxlib/aon22_x2.vbe b/alliance/src/cells/src/msxlib/aon22_x2.vbe +new file mode 100644 +index 0000000..2b7c10b +--- /dev/null ++++ b/alliance/src/cells/src/msxlib/aon22_x2.vbe +@@ -0,0 +1,44 @@ ++ENTITY aon22_x2 IS ++GENERIC ( ++ CONSTANT area : NATURAL := 9000; ++ CONSTANT cin_b1 : NATURAL := 7; ++ CONSTANT cin_b2 : NATURAL := 7; ++ CONSTANT cin_a2 : NATURAL := 6; ++ CONSTANT cin_a1 : NATURAL := 6; ++ CONSTANT rdown_b1_z : NATURAL := 1220; ++ CONSTANT rdown_b2_z : NATURAL := 1210; ++ CONSTANT rdown_a2_z : NATURAL := 1220; ++ CONSTANT rdown_a1_z : NATURAL := 1220; ++ CONSTANT rup_b1_z : NATURAL := 1560; ++ CONSTANT rup_b2_z : NATURAL := 1560; ++ CONSTANT rup_a2_z : NATURAL := 1570; ++ CONSTANT rup_a1_z : NATURAL := 1570; ++ CONSTANT tphh_b1_z : NATURAL := 88; ++ CONSTANT tpll_a2_z : NATURAL := 132; ++ CONSTANT tphh_b2_z : NATURAL := 89; ++ CONSTANT tpll_a1_z : NATURAL := 141; ++ CONSTANT tpll_b2_z : NATURAL := 105; ++ CONSTANT tphh_a1_z : NATURAL := 115; ++ CONSTANT tpll_b1_z : NATURAL := 114; ++ CONSTANT tphh_a2_z : NATURAL := 117; ++ CONSTANT transistors : NATURAL := 10 ++); ++PORT ( ++ b1 : in BIT; ++ b2 : in BIT; ++ a2 : in BIT; ++ a1 : in BIT; ++ z : out BIT; ++ vdd : in BIT; ++ vss : in BIT ++); ++END aon22_x2; ++ ++ARCHITECTURE behaviour_data_flow OF aon22_x2 IS ++ ++BEGIN ++ ASSERT ((vdd and not (vss)) = '1') ++ REPORT "power supply is missing on aon22_x2" ++ SEVERITY WARNING; ++ z <= ((b1 and b2) or (a2 and a1)) after 1200 ps; ++END; +diff --git a/alliance/src/cells/src/msxlib/bf1_w05.ap b/alliance/src/cells/src/msxlib/bf1_w05.ap +new file mode 100644 +index 0000000..5fba830 +--- /dev/null ++++ b/alliance/src/cells/src/msxlib/bf1_w05.ap +@@ -0,0 +1,59 @@ ++V ALLIANCE : 6 ++H bf1_w05,P, 8/ 8/2014,100 ++A 0,0,3000,10000 ++R 2000,5000,ref_ref,z_50 ++R 2000,4000,ref_ref,z_40 ++R 2000,6000,ref_ref,z_60 ++R 2000,8000,ref_ref,a_80 ++R 2000,7000,ref_ref,a_70 ++R 1000,5000,ref_ref,z_50 ++S 2000,7000,2300,7000,600,*,RIGHT,ALU1 ++S 0,5000,3000,5000,10000,bf1_w05,LEFT,TALU8 ++S 0,2200,3000,2200,5200,*,LEFT,PWELL ++S 0,7600,3000,7600,5600,*,LEFT,NWELL ++S 0,9400,3000,9400,1200,vdd,RIGHT,CALU1 ++S 1200,5500,1200,6400,200,1z,UP,PTRANS ++S 800,5700,800,6200,400,*,UP,PDIF ++S 1600,5700,1600,6200,400,*,DOWN,PDIF ++S 1200,3300,1200,3900,200,2z,DOWN,NTRANS ++S 400,6100,700,6100,400,*,LEFT,ALU1 ++S 400,6100,400,9300,400,*,UP,ALU1 ++S 400,6000,700,6000,400,*,LEFT,ALU1 ++S 1200,3900,1200,5500,200,*,DOWN,POLY ++S 400,700,400,3600,400,*,DOWN,ALU1 ++S 400,3600,700,3600,400,*,RIGHT,ALU1 ++S 400,3700,700,3700,400,*,LEFT,ALU1 ++S 1600,7800,1600,8300,400,*,DOWN,PDIF ++S 2000,7600,2000,8500,200,1a,UP,PTRANS ++S 2000,8500,2000,8800,200,*,UP,POLY ++S 2500,7800,2500,9500,400,*,DOWN,PDIF ++S 2000,4000,2000,6000,400,z,DOWN,CALU1 ++S 1200,6900,1200,8000,400,*,DOWN,ALU1 ++S 2000,7000,2000,8000,400,a,UP,CALU1 ++S 2000,6900,2000,8100,400,*,DOWN,ALU1 ++S 2000,6800,2000,7600,200,*,DOWN,POLY ++S 0,600,3000,600,1200,vss,RIGHT,CALU1 ++S 1900,3600,1900,6100,600,*,UP,ALU1 ++S 900,5000,2000,5000,400,*,LEFT,ALU1 ++S 1000,5000,1000,5000,400,z,LEFT,CALU1 ++S 2000,1600,2000,2200,200,2a,DOWN,NTRANS ++S 2000,2600,2500,2600,200,*,RIGHT,POLY ++S 2500,2600,2500,7200,200,*,DOWN,POLY ++S 2500,500,2500,2000,400,*,UP,NDIF ++S 2000,1200,2000,1600,200,*,DOWN,POLY ++S 1300,1900,1300,2800,600,*,DOWN,ALU1 ++S 2000,2200,2000,2600,200,*,UP,POLY ++V 1000,700,CONT_BODY_P,* ++V 1000,9300,CONT_BODY_N,* ++V 2200,7000,CONT_POLY,* ++V 1800,5800,CONT_DIF_P,* ++V 600,6100,CONT_DIF_P,* ++V 600,3600,CONT_DIF_N,* ++V 2400,9400,CONT_DIF_P,* ++V 1200,2700,CONT_POLY,an ++V 1200,7900,CONT_DIF_P,an ++V 2400,600,CONT_DIF_N,* ++V 1900,3600,CONT_DIF_N,* ++V 1200,7000,CONT_POLY,an ++V 1300,1900,CONT_DIF_N,an ++EOF +diff --git a/alliance/src/cells/src/msxlib/bf1_w05.vbe b/alliance/src/cells/src/msxlib/bf1_w05.vbe +new file mode 100644 +index 0000000..aee4efe +--- /dev/null ++++ b/alliance/src/cells/src/msxlib/bf1_w05.vbe +@@ -0,0 +1,26 @@ ++ENTITY bf1_w05 IS ++GENERIC ( ++ CONSTANT area : NATURAL := 3000; ++ CONSTANT cin_a : NATURAL := 2; ++ CONSTANT rdown_a_z : NATURAL := 3810; ++ CONSTANT rup_a_z : NATURAL := 6580; ++ CONSTANT tpll_a_z : NATURAL := 80; ++ CONSTANT tphh_a_z : NATURAL := 61; ++ CONSTANT transistors : NATURAL := 4 ++); ++PORT ( ++ a : in BIT; ++ z : out BIT; ++ vdd : in BIT; ++ vss : in BIT ++); ++END bf1_w05; ++ ++ARCHITECTURE behaviour_data_flow OF bf1_w05 IS ++ ++BEGIN ++ ASSERT ((vdd and not (vss)) = '1') ++ REPORT "power supply is missing on bf1_w05" ++ SEVERITY WARNING; ++ z <= a after 1000 ps; ++END; +diff --git a/alliance/src/cells/src/msxlib/bf1_w2.ap b/alliance/src/cells/src/msxlib/bf1_w2.ap +new file mode 100644 +index 0000000..47d5bb1 +--- /dev/null ++++ b/alliance/src/cells/src/msxlib/bf1_w2.ap +@@ -0,0 +1,65 @@ ++V ALLIANCE : 6 ++H bf1_w2,P, 8/ 8/2014,100 ++A 0,0,4000,10000 ++R 1000,2000,ref_ref,z_20 ++R 1000,3000,ref_ref,z_30 ++R 1000,7000,ref_ref,z_70 ++R 1000,6000,ref_ref,z_60 ++R 1000,4000,ref_ref,z_40 ++R 1000,5000,ref_ref,z_50 ++R 3000,4000,ref_ref,a_40 ++R 3000,6000,ref_ref,a_60 ++R 3000,5000,ref_ref,a_50 ++S 1100,700,1900,700,600,*,LEFT,PTIE ++S 2200,1900,2200,3400,600,*,UP,NDIF ++S 3400,7000,3400,7900,400,*,UP,ALU1 ++S 2000,6900,3400,6900,400,*,RIGHT,ALU1 ++S 1600,9300,1600,9700,200,*,DOWN,POLY ++S 2200,5700,2200,9100,600,*,DOWN,PDIF ++S 2200,7900,2200,9300,400,*,UP,ALU1 ++S 1200,5700,1200,9100,400,*,UP,PDIF ++S 1200,1900,1200,3400,400,*,DOWN,NDIF ++S 1600,3600,1600,5500,200,*,UP,POLY ++S 1600,1300,1600,1700,200,*,UP,POLY ++S 2200,700,2200,2100,400,*,UP,ALU1 ++S 1000,1900,1000,7100,400,*,UP,ALU1 ++S 1000,2000,1000,7000,400,z,DOWN,CALU1 ++S 0,600,4000,600,1200,vss,RIGHT,CALU1 ++S 0,9400,4000,9400,1200,vdd,RIGHT,CALU1 ++S 0,5000,4000,5000,10000,bf1_w2,LEFT,TALU8 ++S 0,2200,4000,2200,5200,*,LEFT,PWELL ++S 0,7600,4000,7600,5600,*,LEFT,NWELL ++S 3000,3900,3000,6100,400,*,DOWN,ALU1 ++S 3000,4000,3000,6000,400,a,DOWN,CALU1 ++S 2800,3600,2800,5500,200,*,UP,POLY ++S 3400,7300,3400,7900,600,*,UP,PDIF ++S 1000,5700,1000,6500,600,*,UP,PDIF ++S 1000,2900,1000,3310,600,*,UP,NDIF ++S 1600,5500,1600,9300,200,1z,UP,PTRANS ++S 1600,1700,1600,3600,200,2z,DOWN,NTRANS ++S 2800,9300,2800,9700,200,*,DOWN,POLY ++S 2800,5500,2800,9300,200,1a,UP,PTRANS ++S 3200,5700,3200,9100,400,*,UP,PDIF ++S 2800,1300,2800,1700,200,*,UP,POLY ++S 3200,1900,3200,3400,400,*,DOWN,NDIF ++S 2800,1700,2800,3600,200,2a,DOWN,NTRANS ++S 2000,3000,2000,6900,400,*,UP,ALU1 ++S 3400,1900,3400,3000,400,*,UP,ALU1 ++S 2000,3000,3400,3000,400,*,LEFT,ALU1 ++S 3400,2100,3400,2700,600,*,UP,NDIF ++V 2000,700,CONT_BODY_P,* ++V 1000,700,CONT_BODY_P,* ++V 3400,7800,CONT_DIF_P,an ++V 3400,7000,CONT_DIF_P,an ++V 2200,8000,CONT_DIF_P,* ++V 2200,9000,CONT_DIF_P,* ++V 2200,2000,CONT_DIF_N,* ++V 3000,4700,CONT_POLY,* ++V 2000,4700,CONT_POLY,an ++V 1000,5800,CONT_DIF_P,* ++V 1000,6600,CONT_DIF_P,* ++V 1000,3300,CONT_DIF_N,* ++V 1000,2500,CONT_DIF_N,* ++V 3400,2000,CONT_DIF_N,an ++V 3400,2800,CONT_DIF_N,an ++EOF +diff --git a/alliance/src/cells/src/msxlib/bf1_w2.vbe b/alliance/src/cells/src/msxlib/bf1_w2.vbe +new file mode 100644 +index 0000000..b4b7b0d +--- /dev/null ++++ b/alliance/src/cells/src/msxlib/bf1_w2.vbe +@@ -0,0 +1,26 @@ ++ENTITY bf1_w2 IS ++GENERIC ( ++ CONSTANT area : NATURAL := 4000; ++ CONSTANT cin_a : NATURAL := 7; ++ CONSTANT rdown_a_z : NATURAL := 1200; ++ CONSTANT rup_a_z : NATURAL := 1560; ++ CONSTANT tpll_a_z : NATURAL := 69; ++ CONSTANT tphh_a_z : NATURAL := 56; ++ CONSTANT transistors : NATURAL := 4 ++); ++PORT ( ++ a : in BIT; ++ z : out BIT; ++ vdd : in BIT; ++ vss : in BIT ++); ++END bf1_w2; ++ ++ARCHITECTURE behaviour_data_flow OF bf1_w2 IS ++ ++BEGIN ++ ASSERT ((vdd and not (vss)) = '1') ++ REPORT "power supply is missing on bf1_w2" ++ SEVERITY WARNING; ++ z <= a after 1000 ps; ++END; +diff --git a/alliance/src/cells/src/msxlib/bf1_x1.ap b/alliance/src/cells/src/msxlib/bf1_x1.ap +new file mode 100644 +index 0000000..78c6bb1 +--- /dev/null ++++ b/alliance/src/cells/src/msxlib/bf1_x1.ap +@@ -0,0 +1,61 @@ ++V ALLIANCE : 6 ++H bf1_x1,P, 8/ 8/2014,100 ++A 0,0,4000,10000 ++R 1000,3000,ref_ref,z_30 ++R 1000,7000,ref_ref,z_70 ++R 1000,6000,ref_ref,z_60 ++R 1000,4000,ref_ref,z_40 ++R 1000,5000,ref_ref,z_50 ++R 3000,4000,ref_ref,a_40 ++R 3000,6000,ref_ref,a_60 ++R 3000,5000,ref_ref,a_50 ++S 1100,9300,1900,9300,600,*,RIGHT,NTIE ++S 1100,700,1900,700,600,*,LEFT,PTIE ++S 1000,3000,1000,7000,400,z,DOWN,CALU1 ++S 2000,3000,3500,3000,400,*,LEFT,ALU1 ++S 2200,7900,2200,9300,400,*,UP,ALU1 ++S 2200,700,2200,2100,400,*,UP,ALU1 ++S 0,600,4000,600,1200,vss,RIGHT,CALU1 ++S 0,9400,4000,9400,1200,vdd,RIGHT,CALU1 ++S 0,5000,4000,5000,10000,bf1_x1,LEFT,TALU8 ++S 0,2200,4000,2200,5200,*,LEFT,PWELL ++S 0,7600,4000,7600,5600,*,LEFT,NWELL ++S 3000,3900,3000,6100,400,*,DOWN,ALU1 ++S 3000,4000,3000,6000,400,a,DOWN,CALU1 ++S 1600,6300,1600,8300,200,1z,UP,PTRANS ++S 1600,8300,1600,8700,200,*,DOWN,POLY ++S 2800,8300,2800,8700,200,*,DOWN,POLY ++S 3200,6500,3200,8100,400,*,UP,PDIF ++S 2800,6300,2800,8300,200,1a,UP,PTRANS ++S 1200,6500,1200,8100,400,*,UP,PDIF ++S 1000,6590,1000,7200,600,*,UP,PDIF ++S 1000,2900,1000,7500,400,*,UP,ALU1 ++S 3400,7300,3400,7900,600,*,DOWN,PDIF ++S 2000,7000,3400,7000,400,*,RIGHT,ALU1 ++S 3400,7000,3400,8100,400,*,DOWN,ALU1 ++S 2000,3000,2000,7000,400,*,UP,ALU1 ++S 2200,6500,2200,8100,600,*,DOWN,PDIF ++S 3200,2500,3200,3100,400,*,DOWN,NDIF ++S 2200,1900,2200,3100,600,*,UP,NDIF ++S 1200,2500,1200,3100,400,*,DOWN,NDIF ++S 1600,2300,1600,3300,200,2z,DOWN,NTRANS ++S 1600,3300,1600,6300,200,*,UP,POLY ++S 2800,3300,2800,6300,200,*,UP,POLY ++S 2800,2300,2800,3300,200,2a,DOWN,NTRANS ++S 2800,1900,2800,2300,200,*,UP,POLY ++S 1600,1900,1600,2300,200,*,UP,POLY ++V 2000,9300,CONT_BODY_N,* ++V 1000,9300,CONT_BODY_N,* ++V 2000,700,CONT_BODY_P,* ++V 1000,700,CONT_BODY_P,* ++V 3400,3000,CONT_DIF_N,an ++V 2200,8000,CONT_DIF_P,* ++V 2200,2000,CONT_DIF_N,* ++V 3000,4700,CONT_POLY,* ++V 2000,4700,CONT_POLY,an ++V 1000,6600,CONT_DIF_P,* ++V 1000,7400,CONT_DIF_P,* ++V 3400,8000,CONT_DIF_P,an ++V 3400,7200,CONT_DIF_P,an ++V 1000,3000,CONT_DIF_N,* ++EOF +diff --git a/alliance/src/cells/src/msxlib/bf1_x1.vbe b/alliance/src/cells/src/msxlib/bf1_x1.vbe +new file mode 100644 +index 0000000..c296d8e +--- /dev/null ++++ b/alliance/src/cells/src/msxlib/bf1_x1.vbe +@@ -0,0 +1,26 @@ ++ENTITY bf1_x1 IS ++GENERIC ( ++ CONSTANT area : NATURAL := 4000; ++ CONSTANT cin_a : NATURAL := 4; ++ CONSTANT rdown_a_z : NATURAL := 2280; ++ CONSTANT rup_a_z : NATURAL := 2960; ++ CONSTANT tpll_a_z : NATURAL := 73; ++ CONSTANT tphh_a_z : NATURAL := 61; ++ CONSTANT transistors : NATURAL := 4 ++); ++PORT ( ++ a : in BIT; ++ z : out BIT; ++ vdd : in BIT; ++ vss : in BIT ++); ++END bf1_x1; ++ ++ARCHITECTURE behaviour_data_flow OF bf1_x1 IS ++ ++BEGIN ++ ASSERT ((vdd and not (vss)) = '1') ++ REPORT "power supply is missing on bf1_x1" ++ SEVERITY WARNING; ++ z <= a after 1000 ps; ++END; +diff --git a/alliance/src/cells/src/msxlib/bf1_x2.ap b/alliance/src/cells/src/msxlib/bf1_x2.ap +new file mode 100644 +index 0000000..25ca522 +--- /dev/null ++++ b/alliance/src/cells/src/msxlib/bf1_x2.ap +@@ -0,0 +1,63 @@ ++V ALLIANCE : 6 ++H bf1_x2,P, 8/ 8/2014,100 ++A 0,0,4000,10000 ++R 1000,2000,ref_ref,z_20 ++R 3000,5000,ref_ref,a_50 ++R 3000,6000,ref_ref,a_60 ++R 3000,4000,ref_ref,a_40 ++R 1000,5000,ref_ref,z_50 ++R 1000,4000,ref_ref,z_40 ++R 1000,6000,ref_ref,z_60 ++R 1000,7000,ref_ref,z_70 ++R 1000,3000,ref_ref,z_30 ++S 1100,700,1900,700,600,*,LEFT,PTIE ++S 1600,1700,1600,3600,200,2z,DOWN,NTRANS ++S 1600,5500,1600,9300,200,1z,UP,PTRANS ++S 1000,2900,1000,3310,600,*,UP,NDIF ++S 1000,5700,1000,6500,600,*,UP,PDIF ++S 3000,4000,3000,6000,400,a,DOWN,CALU1 ++S 3000,3900,3000,6100,400,*,DOWN,ALU1 ++S 0,5000,4000,5000,10000,bf1_x2,LEFT,TALU8 ++S 0,2200,4000,2200,5200,*,LEFT,PWELL ++S 0,7600,4000,7600,5600,*,LEFT,NWELL ++S 0,9400,4000,9400,1200,vdd,RIGHT,CALU1 ++S 0,600,4000,600,1200,vss,RIGHT,CALU1 ++S 1000,2000,1000,7000,400,z,DOWN,CALU1 ++S 1000,1900,1000,7100,400,*,UP,ALU1 ++S 2200,700,2200,2100,400,*,UP,ALU1 ++S 1600,1300,1600,1700,200,*,UP,POLY ++S 1600,3600,1600,5500,200,*,UP,POLY ++S 1200,1900,1200,3400,400,*,DOWN,NDIF ++S 1200,5700,1200,9100,400,*,UP,PDIF ++S 2200,7900,2200,9300,400,*,UP,ALU1 ++S 2200,5700,2200,9100,600,*,DOWN,PDIF ++S 1600,9300,1600,9700,200,*,DOWN,POLY ++S 2200,1900,2200,3400,600,*,UP,NDIF ++S 2000,3000,3500,3000,400,*,LEFT,ALU1 ++S 3200,2200,3200,3100,400,*,DOWN,NDIF ++S 2800,2000,2800,3300,200,2a,DOWN,NTRANS ++S 2800,1600,2800,2000,200,*,UP,POLY ++S 3400,7500,3400,8100,600,*,UP,PDIF ++S 2800,5700,2800,8300,200,1a,UP,PTRANS ++S 3200,5900,3200,8100,400,*,UP,PDIF ++S 2000,7000,3400,7000,400,*,RIGHT,ALU1 ++S 2000,3000,2000,7000,400,*,UP,ALU1 ++S 3400,7000,3400,8100,400,*,UP,ALU1 ++S 2800,8300,2800,8700,200,*,DOWN,POLY ++S 2800,3300,2800,5700,200,*,UP,POLY ++V 2000,700,CONT_BODY_P,* ++V 1000,700,CONT_BODY_P,* ++V 3300,9300,CONT_BODY_N,* ++V 1000,2500,CONT_DIF_N,* ++V 1000,3300,CONT_DIF_N,* ++V 1000,6600,CONT_DIF_P,* ++V 1000,5800,CONT_DIF_P,* ++V 2000,4700,CONT_POLY,an ++V 3000,4700,CONT_POLY,* ++V 2200,2000,CONT_DIF_N,* ++V 2200,9000,CONT_DIF_P,* ++V 2200,8000,CONT_DIF_P,* ++V 3400,3000,CONT_DIF_N,an ++V 3400,8000,CONT_DIF_P,an ++V 3400,7200,CONT_DIF_P,an ++EOF +diff --git a/alliance/src/cells/src/msxlib/bf1_x2.vbe b/alliance/src/cells/src/msxlib/bf1_x2.vbe +new file mode 100644 +index 0000000..ef9a368 +--- /dev/null ++++ b/alliance/src/cells/src/msxlib/bf1_x2.vbe +@@ -0,0 +1,26 @@ ++ENTITY bf1_x2 IS ++GENERIC ( ++ CONSTANT area : NATURAL := 4000; ++ CONSTANT cin_a : NATURAL := 5; ++ CONSTANT rdown_a_z : NATURAL := 1200; ++ CONSTANT rup_a_z : NATURAL := 1560; ++ CONSTANT tpll_a_z : NATURAL := 78; ++ CONSTANT tphh_a_z : NATURAL := 64; ++ CONSTANT transistors : NATURAL := 4 ++); ++PORT ( ++ a : in BIT; ++ z : out BIT; ++ vdd : in BIT; ++ vss : in BIT ++); ++END bf1_x2; ++ ++ARCHITECTURE behaviour_data_flow OF bf1_x2 IS ++ ++BEGIN ++ ASSERT ((vdd and not (vss)) = '1') ++ REPORT "power supply is missing on bf1_x2" ++ SEVERITY WARNING; ++ z <= a after 1000 ps; ++END; +diff --git a/alliance/src/cells/src/msxlib/bf1_x4.ap b/alliance/src/cells/src/msxlib/bf1_x4.ap +new file mode 100644 +index 0000000..bcdef37 +--- /dev/null ++++ b/alliance/src/cells/src/msxlib/bf1_x4.ap +@@ -0,0 +1,88 @@ ++V ALLIANCE : 6 ++H bf1_x4,P, 8/ 8/2014,100 ++A 0,0,5000,10000 ++R 3000,6000,ref_ref,a_60 ++R 2000,5000,ref_ref,a_50 ++R 2000,7000,ref_ref,z_70 ++R 1000,6000,ref_ref,z_60 ++R 1000,4000,ref_ref,z_40 ++R 2000,3000,ref_ref,z_30 ++R 2000,6000,ref_ref,z_60 ++R 1000,5000,ref_ref,z_50 ++R 3000,5000,ref_ref,a_50 ++R 2000,2000,ref_ref,z_20 ++R 1000,3000,ref_ref,z_30 ++R 3000,7000,ref_ref,a_70 ++S 1100,700,1900,700,600,*,LEFT,PTIE ++S 800,6900,800,9300,400,*,UP,ALU1 ++S 1400,3600,1400,5600,200,*,UP,POLY ++S 2600,3600,2600,5600,200,*,UP,POLY ++S 3200,700,3200,3100,400,*,DOWN,ALU1 ++S 2600,9400,2600,9700,200,*,DOWN,POLY ++S 1400,9400,1400,9700,200,*,DOWN,POLY ++S 2000,5800,2000,9200,1000,*,DOWN,PDIF ++S 1000,6000,2000,6000,600,*,RIGHT,ALU1 ++S 800,5800,800,9200,800,*,DOWN,PDIF ++S 3200,5800,3200,9200,800,*,DOWN,PDIF ++S 2000,6000,2000,7100,400,*,UP,ALU1 ++S 2000,5000,2000,5000,400,a,LEFT,CALU1 ++S 2000,6000,2000,7000,400,z,UP,CALU1 ++S 3800,9400,3800,9700,200,*,DOWN,POLY ++S 0,9400,5000,9400,1200,vdd,RIGHT,CALU1 ++S 0,600,5000,600,1200,vss,RIGHT,CALU1 ++S 0,5000,5000,5000,10000,bf1_x4,LEFT,TALU8 ++S 0,2200,5000,2200,5200,*,LEFT,PWELL ++S 0,7600,5000,7600,5600,*,LEFT,NWELL ++S 3800,3600,3800,5600,200,*,DOWN,POLY ++S 3000,5000,3000,7000,400,a,DOWN,CALU1 ++S 800,700,800,2100,400,*,DOWN,ALU1 ++S 1000,3000,2000,3000,600,*,LEFT,ALU1 ++S 1000,3000,1000,6000,400,z,DOWN,CALU1 ++S 1000,3000,1000,6000,400,*,UP,ALU1 ++S 2000,2000,2000,3000,400,z,DOWN,CALU1 ++S 2000,1900,2000,3000,400,*,UP,ALU1 ++S 1400,4000,2600,4000,600,*,RIGHT,POLY ++S 800,1700,800,3200,600,*,UP,NDIF ++S 700,1700,700,3200,600,*,UP,NDIF ++S 2000,1700,2000,3200,600,*,UP,NDIF ++S 3300,1700,3300,3200,600,*,UP,NDIF ++S 3200,1700,3200,3200,600,*,UP,NDIF ++S 4400,2200,4400,6800,400,*,UP,ALU1 ++S 4400,2400,4400,3000,600,*,UP,NDIF ++S 4200,1700,4200,3200,400,*,UP,NDIF ++S 2300,4000,4400,4000,400,*,RIGHT,ALU1 ++S 1900,5000,3600,5000,400,*,RIGHT,ALU1 ++S 3000,5000,3000,7100,400,*,UP,ALU1 ++S 3200,7900,3200,9300,400,*,UP,ALU1 ++S 4200,5800,4200,9200,400,*,DOWN,PDIF ++S 4400,6000,4400,6600,600,*,UP,PDIF ++S 3800,5600,3800,9400,200,1a,UP,PTRANS ++S 3800,1500,3800,3400,200,1b,DOWN,NTRANS ++S 2600,5600,2600,9400,200,1z,UP,PTRANS ++S 1400,5600,1400,9400,200,2z,UP,PTRANS ++S 2600,1500,2600,3400,200,3z,DOWN,NTRANS ++S 1400,1500,1400,3400,200,4z,DOWN,NTRANS ++S 1400,1200,1400,1500,200,*,UP,POLY ++S 2600,1100,2600,1500,200,*,UP,POLY ++S 3800,1100,3800,1500,200,*,UP,POLY ++V 2000,700,CONT_BODY_P,* ++V 1000,700,CONT_BODY_P,* ++V 800,9000,CONT_DIF_P,* ++V 3200,9000,CONT_DIF_P,* ++V 3200,8000,CONT_DIF_P,* ++V 800,8000,CONT_DIF_P,* ++V 800,7000,CONT_DIF_P,* ++V 2000,3000,CONT_DIF_N,* ++V 2000,7000,CONT_DIF_P,* ++V 2000,6000,CONT_DIF_P,* ++V 3200,3000,CONT_DIF_N,* ++V 800,2000,CONT_DIF_N,* ++V 4400,6700,CONT_DIF_P,an ++V 4400,5900,CONT_DIF_P,an ++V 4400,2300,CONT_DIF_N,an ++V 4400,3100,CONT_DIF_N,an ++V 3200,2000,CONT_DIF_N,* ++V 2000,2000,CONT_DIF_N,* ++V 2400,4000,CONT_POLY,an ++V 3500,5000,CONT_POLY,* ++EOF +diff --git a/alliance/src/cells/src/msxlib/bf1_x4.vbe b/alliance/src/cells/src/msxlib/bf1_x4.vbe +new file mode 100644 +index 0000000..475fb08 +--- /dev/null ++++ b/alliance/src/cells/src/msxlib/bf1_x4.vbe +@@ -0,0 +1,26 @@ ++ENTITY bf1_x4 IS ++GENERIC ( ++ CONSTANT area : NATURAL := 5000; ++ CONSTANT cin_a : NATURAL := 7; ++ CONSTANT rdown_a_z : NATURAL := 600; ++ CONSTANT rup_a_z : NATURAL := 780; ++ CONSTANT tpll_a_z : NATURAL := 82; ++ CONSTANT tphh_a_z : NATURAL := 66; ++ CONSTANT transistors : NATURAL := 6 ++); ++PORT ( ++ a : in BIT; ++ z : out BIT; ++ vdd : in BIT; ++ vss : in BIT ++); ++END bf1_x4; ++ ++ARCHITECTURE behaviour_data_flow OF bf1_x4 IS ++ ++BEGIN ++ ASSERT ((vdd and not (vss)) = '1') ++ REPORT "power supply is missing on bf1_x4" ++ SEVERITY WARNING; ++ z <= a after 1000 ps; ++END; +diff --git a/alliance/src/cells/src/msxlib/bf1_x8.ap b/alliance/src/cells/src/msxlib/bf1_x8.ap +new file mode 100644 +index 0000000..971f02e +--- /dev/null ++++ b/alliance/src/cells/src/msxlib/bf1_x8.ap +@@ -0,0 +1,138 @@ ++V ALLIANCE : 6 ++H bf1_x8,P, 8/ 8/2014,100 ++A 0,0,9000,10000 ++R 4000,2000,ref_ref,z_20 ++R 2000,2000,ref_ref,z_20 ++R 2000,7000,ref_ref,z_70 ++R 2000,4000,ref_ref,z_40 ++R 2000,3000,ref_ref,z_30 ++R 2000,6000,ref_ref,z_60 ++R 3000,6000,ref_ref,z_60 ++R 4000,6000,ref_ref,z_60 ++R 4000,7000,ref_ref,z_70 ++R 3000,4000,ref_ref,z_40 ++R 4000,4000,ref_ref,z_40 ++R 4000,3000,ref_ref,z_30 ++R 8000,6000,ref_ref,a_60 ++R 8000,5000,ref_ref,a_50 ++R 8000,4000,ref_ref,a_40 ++R 2000,5000,ref_ref,z_50 ++R 7000,4000,ref_ref,a_40 ++S 2400,700,3200,700,600,*,LEFT,PTIE ++S 5400,700,5400,3100,400,*,DOWN,ALU1 ++S 3000,4000,3000,4000,400,z,LEFT,CALU1 ++S 4000,2000,4000,4000,400,z,DOWN,CALU1 ++S 3000,6000,3000,6000,400,z,LEFT,CALU1 ++S 4000,6000,4000,7000,400,z,UP,CALU1 ++S 4100,6000,4100,7100,600,*,DOWN,ALU1 ++S 1200,9400,1200,9700,200,*,DOWN,POLY ++S 2400,9400,2400,9700,200,*,DOWN,POLY ++S 3600,9400,3600,9700,200,*,DOWN,POLY ++S 600,6900,600,9300,400,*,UP,ALU1 ++S 3000,6900,3000,9300,400,*,UP,ALU1 ++S 5400,6900,5400,9300,400,*,UP,ALU1 ++S 600,700,600,3100,400,*,DOWN,ALU1 ++S 4100,1900,4100,4000,600,*,DOWN,ALU1 ++S 3000,700,3000,3100,400,*,DOWN,ALU1 ++S 4800,1300,4800,1700,200,*,UP,POLY ++S 3600,1300,3600,1700,200,*,UP,POLY ++S 2400,1300,2400,1700,200,*,UP,POLY ++S 1200,1300,1200,1700,200,*,UP,POLY ++S 1200,5500,1200,9400,200,1,UP,PTRANS ++S 600,5700,600,9200,600,*,DOWN,PDIF ++S 1800,5700,1800,9200,600,*,DOWN,PDIF ++S 2400,5500,2400,9400,200,2,UP,PTRANS ++S 3600,5500,3600,9400,200,3,UP,PTRANS ++S 3000,5700,3000,9200,600,*,DOWN,PDIF ++S 5400,5700,5400,8100,600,*,DOWN,PDIF ++S 4800,5500,4800,8300,200,4,UP,PTRANS ++S 4200,5700,4200,8100,600,*,UP,PDIF ++S 4000,8500,4000,9200,400,*,UP,PDIF ++S 4800,8400,4800,8700,200,*,DOWN,POLY ++S 6600,5700,6600,8100,600,*,UP,PDIF ++S 6000,8400,6000,8700,200,*,DOWN,POLY ++S 0,9400,9000,9400,1200,vdd,RIGHT,CALU1 ++S 0,5000,9000,5000,10000,bf1_x8,LEFT,TALU8 ++S 0,2200,9000,2200,5200,*,LEFT,PWELL ++S 0,7600,9000,7600,5600,*,LEFT,NWELL ++S 7800,6900,7800,9300,400,*,UP,ALU1 ++S 8000,3900,8000,6100,400,*,DOWN,ALU1 ++S 8000,4000,8000,6000,400,a,DOWN,CALU1 ++S 6600,1900,6600,2800,600,*,UP,NDIF ++S 7600,1900,7600,3100,400,*,UP,NDIF ++S 7800,700,7800,3100,400,*,DOWN,ALU1 ++S 0,600,9000,600,1200,vss,RIGHT,CALU1 ++S 7900,1900,7900,3100,600,*,UP,NDIF ++S 7900,5700,7900,8900,600,*,DOWN,PDIF ++S 6800,5700,6800,8900,400,*,UP,PDIF ++S 7200,9100,7200,9500,200,*,DOWN,POLY ++S 7200,5500,7200,9100,200,1a,UP,PTRANS ++S 6000,5500,6000,8300,200,2a,UP,PTRANS ++S 7200,1700,7200,3300,200,3a,DOWN,NTRANS ++S 6000,1700,6000,3300,200,4a,DOWN,NTRANS ++S 6000,1300,6000,1700,200,*,UP,POLY ++S 7200,1300,7200,1700,200,*,UP,POLY ++S 2400,4900,3600,4900,600,*,RIGHT,POLY ++S 1200,5100,4800,5100,200,*,RIGHT,POLY ++S 1800,6000,4200,6000,400,*,LEFT,ALU1 ++S 1800,4000,4200,4000,400,*,RIGHT,ALU1 ++S 1900,1900,1900,7100,600,*,DOWN,ALU1 ++S 2000,2000,2000,7000,400,z,UP,CALU1 ++S 6000,4000,7200,4000,600,*,RIGHT,POLY ++S 7200,3300,7200,5500,200,*,DOWN,POLY ++S 6000,3300,6000,5500,200,*,UP,POLY ++S 7000,4000,8000,4000,600,*,RIGHT,ALU1 ++S 7000,4000,7000,4000,400,a,LEFT,CALU1 ++S 6200,3100,6200,4900,400,*,DOWN,ALU1 ++S 2900,4900,6600,4900,400,*,RIGHT,ALU1 ++S 6600,4900,6600,7100,400,*,DOWN,ALU1 ++S 6600,1900,6600,3100,400,*,UP,ALU1 ++S 700,1900,700,3300,800,*,UP,NDIF ++S 1200,1700,1200,3500,200,5,DOWN,NTRANS ++S 1800,1900,1800,3300,1000,*,UP,NDIF ++S 3000,1900,3000,3300,1000,*,UP,NDIF ++S 2400,1700,2400,3500,200,6,DOWN,NTRANS ++S 1200,3500,1200,5500,200,*,UP,POLY ++S 2400,3500,2400,5500,200,*,UP,POLY ++S 3600,1700,3600,3500,200,7,DOWN,NTRANS ++S 3600,3500,3600,5500,200,*,UP,POLY ++S 4200,1900,4200,3300,1000,*,UP,NDIF ++S 4800,1700,4800,3500,200,8,DOWN,NTRANS ++S 4800,3500,4800,5500,200,*,UP,POLY ++S 5300,1900,5300,3300,800,*,UP,NDIF ++V 5400,9300,CONT_BODY_N,* ++V 3300,700,CONT_BODY_P,* ++V 2300,700,CONT_BODY_P,* ++V 5400,3000,CONT_DIF_N,* ++V 1800,7000,CONT_DIF_P,* ++V 4200,7000,CONT_DIF_P,* ++V 600,7000,CONT_DIF_P,* ++V 600,8000,CONT_DIF_P,* ++V 600,9000,CONT_DIF_P,* ++V 3000,7000,CONT_DIF_P,* ++V 3000,8000,CONT_DIF_P,* ++V 3000,9000,CONT_DIF_P,* ++V 5400,7000,CONT_DIF_P,* ++V 5400,8000,CONT_DIF_P,* ++V 600,3000,CONT_DIF_N,* ++V 600,2000,CONT_DIF_N,* ++V 3000,3000,CONT_DIF_N,* ++V 3000,2000,CONT_DIF_N,* ++V 1800,2000,CONT_DIF_N,* ++V 1800,3000,CONT_DIF_N,* ++V 4200,3000,CONT_DIF_N,* ++V 4200,2000,CONT_DIF_N,* ++V 5400,2000,CONT_DIF_N,* ++V 7800,8000,CONT_DIF_P,* ++V 7800,7000,CONT_DIF_P,* ++V 6600,6000,CONT_DIF_P,an ++V 6600,7000,CONT_DIF_P,an ++V 7800,3000,CONT_DIF_N,* ++V 7800,2200,CONT_DIF_N,* ++V 6600,3000,CONT_DIF_N,an ++V 3000,4900,CONT_POLY,* ++V 1800,6200,CONT_DIF_P,* ++V 4200,6200,CONT_DIF_P,* ++V 7000,4000,CONT_POLY,* ++V 6600,2000,CONT_DIF_N,an ++EOF +diff --git a/alliance/src/cells/src/msxlib/bf1_x8.vbe b/alliance/src/cells/src/msxlib/bf1_x8.vbe +new file mode 100644 +index 0000000..9d99611 +--- /dev/null ++++ b/alliance/src/cells/src/msxlib/bf1_x8.vbe +@@ -0,0 +1,26 @@ ++ENTITY bf1_x8 IS ++GENERIC ( ++ CONSTANT area : NATURAL := 9000; ++ CONSTANT cin_a : NATURAL := 11; ++ CONSTANT rdown_a_z : NATURAL := 320; ++ CONSTANT rup_a_z : NATURAL := 410; ++ CONSTANT tpll_a_z : NATURAL := 84; ++ CONSTANT tphh_a_z : NATURAL := 68; ++ CONSTANT transistors : NATURAL := 12 ++); ++PORT ( ++ a : in BIT; ++ z : out BIT; ++ vdd : in BIT; ++ vss : in BIT ++); ++END bf1_x8; ++ ++ARCHITECTURE behaviour_data_flow OF bf1_x8 IS ++ ++BEGIN ++ ASSERT ((vdd and not (vss)) = '1') ++ REPORT "power supply is missing on bf1_x8" ++ SEVERITY WARNING; ++ z <= a after 1000 ps; ++END; +diff --git a/alliance/src/cells/src/msxlib/bf1_y05.ap b/alliance/src/cells/src/msxlib/bf1_y05.ap +new file mode 100644 +index 0000000..d82bc19 +--- /dev/null ++++ b/alliance/src/cells/src/msxlib/bf1_y05.ap +@@ -0,0 +1,55 @@ ++V ALLIANCE : 6 ++H bf1_y05,P, 8/ 8/2014,100 ++A 0,0,4000,10000 ++R 1000,3000,ref_ref,z_30 ++R 1000,7000,ref_ref,z_70 ++R 1000,6000,ref_ref,z_60 ++R 1000,4000,ref_ref,z_40 ++R 1000,5000,ref_ref,z_50 ++R 3000,4000,ref_ref,a_40 ++R 3000,6000,ref_ref,a_60 ++R 3000,5000,ref_ref,a_50 ++S 1100,9300,1900,9300,600,*,RIGHT,NTIE ++S 1100,700,1900,700,600,*,LEFT,PTIE ++S 1600,2300,1600,2700,200,*,UP,POLY ++S 1600,2700,1600,3300,200,2z,DOWN,NTRANS ++S 1200,2900,1200,3100,400,*,DOWN,NDIF ++S 1000,2900,1000,7100,400,*,UP,ALU1 ++S 1000,3000,1000,7000,400,z,DOWN,CALU1 ++S 2200,1900,2200,3100,600,*,UP,NDIF ++S 2000,3000,3500,3000,400,*,LEFT,ALU1 ++S 2000,7000,3500,7000,400,*,RIGHT,ALU1 ++S 2200,7900,2200,9300,400,*,UP,ALU1 ++S 2200,700,2200,2100,400,*,UP,ALU1 ++S 0,600,4000,600,1200,vss,RIGHT,CALU1 ++S 0,9400,4000,9400,1200,vdd,RIGHT,CALU1 ++S 0,5000,4000,5000,10000,bf1_y05,LEFT,TALU8 ++S 0,2200,4000,2200,5200,*,LEFT,PWELL ++S 0,7600,4000,7600,5600,*,LEFT,NWELL ++S 3000,3900,3000,6100,400,*,DOWN,ALU1 ++S 3000,4000,3000,6000,400,a,DOWN,CALU1 ++S 2000,3000,2000,7000,400,*,UP,ALU1 ++S 2800,2700,2800,3300,200,2a,DOWN,NTRANS ++S 2800,2300,2800,2700,200,*,UP,POLY ++S 3200,6900,3200,7700,400,*,UP,PDIF ++S 2800,6700,2800,7900,200,1a,UP,PTRANS ++S 1200,6900,1200,7700,400,*,UP,PDIF ++S 1600,6700,1600,7900,200,1z,UP,PTRANS ++S 2200,6900,2200,8100,600,*,DOWN,PDIF ++S 1600,3300,1600,6700,200,*,UP,POLY ++S 2800,3300,2800,6700,200,*,UP,POLY ++S 1600,7900,1600,8300,200,*,DOWN,POLY ++S 2800,7900,2800,8300,200,*,DOWN,POLY ++V 2000,9300,CONT_BODY_N,* ++V 1000,9300,CONT_BODY_N,* ++V 2000,700,CONT_BODY_P,* ++V 1000,700,CONT_BODY_P,* ++V 1000,3000,CONT_DIF_N,* ++V 3400,3000,CONT_DIF_N,an ++V 3400,7000,CONT_DIF_P,an ++V 2200,8000,CONT_DIF_P,* ++V 2200,2000,CONT_DIF_N,* ++V 3000,4700,CONT_POLY,* ++V 2000,4700,CONT_POLY,an ++V 1000,7000,CONT_DIF_P,* ++EOF +diff --git a/alliance/src/cells/src/msxlib/bf1_y05.vbe b/alliance/src/cells/src/msxlib/bf1_y05.vbe +new file mode 100644 +index 0000000..9d7eeb6 +--- /dev/null ++++ b/alliance/src/cells/src/msxlib/bf1_y05.vbe +@@ -0,0 +1,26 @@ ++ENTITY bf1_y05 IS ++GENERIC ( ++ CONSTANT area : NATURAL := 4000; ++ CONSTANT cin_a : NATURAL := 3; ++ CONSTANT rdown_a_z : NATURAL := 3810; ++ CONSTANT rup_a_z : NATURAL := 4940; ++ CONSTANT tpll_a_z : NATURAL := 78; ++ CONSTANT tphh_a_z : NATURAL := 66; ++ CONSTANT transistors : NATURAL := 4 ++); ++PORT ( ++ a : in BIT; ++ z : out BIT; ++ vdd : in BIT; ++ vss : in BIT ++); ++END bf1_y05; ++ ++ARCHITECTURE behaviour_data_flow OF bf1_y05 IS ++ ++BEGIN ++ ASSERT ((vdd and not (vss)) = '1') ++ REPORT "power supply is missing on bf1_y05" ++ SEVERITY WARNING; ++ z <= a after 1000 ps; ++END; +diff --git a/alliance/src/cells/src/msxlib/bf1_y1.ap b/alliance/src/cells/src/msxlib/bf1_y1.ap +new file mode 100644 +index 0000000..1a88dac +--- /dev/null ++++ b/alliance/src/cells/src/msxlib/bf1_y1.ap +@@ -0,0 +1,57 @@ ++V ALLIANCE : 6 ++H bf1_y1,P, 8/ 8/2014,100 ++A 0,0,4000,10000 ++R 1000,3000,ref_ref,z_30 ++R 1000,7000,ref_ref,z_70 ++R 1000,6000,ref_ref,z_60 ++R 1000,4000,ref_ref,z_40 ++R 1000,5000,ref_ref,z_50 ++R 3000,4000,ref_ref,a_40 ++R 3000,6000,ref_ref,a_60 ++R 3000,5000,ref_ref,a_50 ++S 1100,700,1900,700,600,*,LEFT,PTIE ++S 1100,9300,1900,9300,600,*,RIGHT,NTIE ++S 1600,3300,1600,6300,200,*,UP,POLY ++S 1000,2900,1000,7500,400,*,UP,ALU1 ++S 1000,3000,1000,7000,400,z,DOWN,CALU1 ++S 1600,1900,1600,2300,200,*,UP,POLY ++S 1600,2300,1600,3300,200,2z,DOWN,NTRANS ++S 1200,2500,1200,3100,400,*,DOWN,NDIF ++S 2200,1900,2200,3100,600,*,UP,NDIF ++S 1600,8300,1600,8700,200,*,DOWN,POLY ++S 2200,6500,2200,8100,600,*,DOWN,PDIF ++S 1000,6500,1000,7300,600,*,UP,PDIF ++S 1600,6300,1600,8300,200,1z,UP,PTRANS ++S 1200,6500,1200,8100,400,*,UP,PDIF ++S 2000,3000,3500,3000,400,*,LEFT,ALU1 ++S 2000,7000,3500,7000,400,*,RIGHT,ALU1 ++S 2200,7900,2200,9300,400,*,UP,ALU1 ++S 2200,700,2200,2100,400,*,UP,ALU1 ++S 0,600,4000,600,1200,vss,RIGHT,CALU1 ++S 0,9400,4000,9400,1200,vdd,RIGHT,CALU1 ++S 0,5000,4000,5000,10000,bf1_y1,LEFT,TALU8 ++S 0,2200,4000,2200,5200,*,LEFT,PWELL ++S 0,7600,4000,7600,5600,*,LEFT,NWELL ++S 3000,3900,3000,6100,400,*,DOWN,ALU1 ++S 3000,4000,3000,6000,400,a,DOWN,CALU1 ++S 2000,3000,2000,7000,400,*,UP,ALU1 ++S 2800,2700,2800,3300,200,2a,DOWN,NTRANS ++S 2800,2300,2800,2700,200,*,UP,POLY ++S 3200,6900,3200,7700,400,*,UP,PDIF ++S 2800,6700,2800,7900,200,1a,UP,PTRANS ++S 2800,3300,2800,6700,200,*,UP,POLY ++S 2800,7900,2800,8300,200,*,DOWN,POLY ++V 2000,700,CONT_BODY_P,* ++V 1000,700,CONT_BODY_P,* ++V 2000,9300,CONT_BODY_N,* ++V 1000,9300,CONT_BODY_N,* ++V 1000,3000,CONT_DIF_N,* ++V 1000,6600,CONT_DIF_P,* ++V 1000,7400,CONT_DIF_P,* ++V 3400,3000,CONT_DIF_N,an ++V 3400,7000,CONT_DIF_P,an ++V 2200,8000,CONT_DIF_P,* ++V 2200,2000,CONT_DIF_N,* ++V 3000,4700,CONT_POLY,* ++V 2000,4700,CONT_POLY,an ++EOF +diff --git a/alliance/src/cells/src/msxlib/bf1_y1.vbe b/alliance/src/cells/src/msxlib/bf1_y1.vbe +new file mode 100644 +index 0000000..c63f067 +--- /dev/null ++++ b/alliance/src/cells/src/msxlib/bf1_y1.vbe +@@ -0,0 +1,26 @@ ++ENTITY bf1_y1 IS ++GENERIC ( ++ CONSTANT area : NATURAL := 4000; ++ CONSTANT cin_a : NATURAL := 3; ++ CONSTANT rdown_a_z : NATURAL := 2290; ++ CONSTANT rup_a_z : NATURAL := 2960; ++ CONSTANT tpll_a_z : NATURAL := 87; ++ CONSTANT tphh_a_z : NATURAL := 72; ++ CONSTANT transistors : NATURAL := 4 ++); ++PORT ( ++ a : in BIT; ++ z : out BIT; ++ vdd : in BIT; ++ vss : in BIT ++); ++END bf1_y1; ++ ++ARCHITECTURE behaviour_data_flow OF bf1_y1 IS ++ ++BEGIN ++ ASSERT ((vdd and not (vss)) = '1') ++ REPORT "power supply is missing on bf1_y1" ++ SEVERITY WARNING; ++ z <= a after 1000 ps; ++END; +diff --git a/alliance/src/cells/src/msxlib/bf1_y2.ap b/alliance/src/cells/src/msxlib/bf1_y2.ap +new file mode 100644 +index 0000000..0692c2b +--- /dev/null ++++ b/alliance/src/cells/src/msxlib/bf1_y2.ap +@@ -0,0 +1,59 @@ ++V ALLIANCE : 6 ++H bf1_y2,P, 8/ 8/2014,100 ++A 0,0,4000,10000 ++R 1000,3000,ref_ref,z_30 ++R 1000,7000,ref_ref,z_70 ++R 1000,6000,ref_ref,z_60 ++R 1000,4000,ref_ref,z_40 ++R 1000,5000,ref_ref,z_50 ++R 3000,4000,ref_ref,a_40 ++R 3000,6000,ref_ref,a_60 ++R 3000,5000,ref_ref,a_50 ++R 1000,2000,ref_ref,z_20 ++S 1100,700,1900,700,600,*,LEFT,PTIE ++S 2800,3300,2800,6700,200,*,UP,POLY ++S 2800,6700,2800,7900,200,1a,UP,PTRANS ++S 3200,6900,3200,7700,400,*,UP,PDIF ++S 2000,3000,3500,3000,400,*,LEFT,ALU1 ++S 2000,7000,3500,7000,400,*,RIGHT,ALU1 ++S 2200,1900,2200,3400,600,*,UP,NDIF ++S 1600,9300,1600,9700,200,*,DOWN,POLY ++S 2200,5700,2200,9100,600,*,DOWN,PDIF ++S 2200,7900,2200,9300,400,*,UP,ALU1 ++S 1200,5700,1200,9100,400,*,UP,PDIF ++S 1200,1900,1200,3400,400,*,DOWN,NDIF ++S 1600,3600,1600,5500,200,*,UP,POLY ++S 1600,1300,1600,1700,200,*,UP,POLY ++S 2200,700,2200,2100,400,*,UP,ALU1 ++S 1000,1900,1000,7100,400,*,UP,ALU1 ++S 1000,2000,1000,7000,400,z,DOWN,CALU1 ++S 0,600,4000,600,1200,vss,RIGHT,CALU1 ++S 0,9400,4000,9400,1200,vdd,RIGHT,CALU1 ++S 0,5000,4000,5000,10000,bf1_y2,LEFT,TALU8 ++S 0,2200,4000,2200,5200,*,LEFT,PWELL ++S 0,7600,4000,7600,5600,*,LEFT,NWELL ++S 3000,3900,3000,6100,400,*,DOWN,ALU1 ++S 3000,4000,3000,6000,400,a,DOWN,CALU1 ++S 2000,3000,2000,7000,400,*,UP,ALU1 ++S 1000,5700,1000,6500,600,*,UP,PDIF ++S 1000,2900,1000,3310,600,*,UP,NDIF ++S 1600,5500,1600,9300,200,1z,UP,PTRANS ++S 1600,1700,1600,3600,200,2z,DOWN,NTRANS ++S 2800,2700,2800,3300,200,2a,DOWN,NTRANS ++S 2800,2300,2800,2700,200,*,UP,POLY ++S 2800,7900,2800,8300,200,*,DOWN,POLY ++V 2000,700,CONT_BODY_P,* ++V 1000,700,CONT_BODY_P,* ++V 3300,9300,CONT_BODY_N,* ++V 3400,3000,CONT_DIF_N,an ++V 3400,7000,CONT_DIF_P,an ++V 2200,8000,CONT_DIF_P,* ++V 2200,9000,CONT_DIF_P,* ++V 2200,2000,CONT_DIF_N,* ++V 3000,4700,CONT_POLY,* ++V 2000,4700,CONT_POLY,an ++V 1000,5800,CONT_DIF_P,* ++V 1000,6600,CONT_DIF_P,* ++V 1000,3300,CONT_DIF_N,* ++V 1000,2500,CONT_DIF_N,* ++EOF +diff --git a/alliance/src/cells/src/msxlib/bf1_y2.vbe b/alliance/src/cells/src/msxlib/bf1_y2.vbe +new file mode 100644 +index 0000000..adcc717 +--- /dev/null ++++ b/alliance/src/cells/src/msxlib/bf1_y2.vbe +@@ -0,0 +1,26 @@ ++ENTITY bf1_y2 IS ++GENERIC ( ++ CONSTANT area : NATURAL := 4000; ++ CONSTANT cin_a : NATURAL := 2; ++ CONSTANT rdown_a_z : NATURAL := 1210; ++ CONSTANT rup_a_z : NATURAL := 1560; ++ CONSTANT tpll_a_z : NATURAL := 106; ++ CONSTANT tphh_a_z : NATURAL := 87; ++ CONSTANT transistors : NATURAL := 4 ++); ++PORT ( ++ a : in BIT; ++ z : out BIT; ++ vdd : in BIT; ++ vss : in BIT ++); ++END bf1_y2; ++ ++ARCHITECTURE behaviour_data_flow OF bf1_y2 IS ++ ++BEGIN ++ ASSERT ((vdd and not (vss)) = '1') ++ REPORT "power supply is missing on bf1_y2" ++ SEVERITY WARNING; ++ z <= a after 1000 ps; ++END; +diff --git a/alliance/src/cells/src/msxlib/cgi2_x05.ap b/alliance/src/cells/src/msxlib/cgi2_x05.ap +new file mode 100644 +index 0000000..817c429 +--- /dev/null ++++ b/alliance/src/cells/src/msxlib/cgi2_x05.ap +@@ -0,0 +1,120 @@ ++V ALLIANCE : 6 ++H cgi2_x05,P, 8/ 8/2014,100 ++A 0,0,7000,10000 ++R 4000,6000,ref_ref,z_60 ++R 6000,4000,ref_ref,b_40 ++R 5000,4000,ref_ref,b_40 ++R 6000,7000,ref_ref,c_70 ++R 5000,7000,ref_ref,c_70 ++R 5000,6000,ref_ref,c_60 ++R 3000,3000,ref_ref,z_30 ++R 1000,6000,ref_ref,a_60 ++R 1000,5000,ref_ref,a_50 ++R 6000,6000,ref_ref,b_60 ++R 3000,6000,ref_ref,z_60 ++R 3000,5000,ref_ref,z_50 ++R 3000,4000,ref_ref,z_40 ++R 4000,3000,ref_ref,z_30 ++R 4000,7000,ref_ref,z_70 ++R 2000,5000,ref_ref,a_50 ++R 4000,4000,ref_ref,b_40 ++R 6000,5000,ref_ref,b_50 ++R 5000,5000,ref_ref,c_50 ++R 1000,4000,ref_ref,a_40 ++S 5100,700,5900,700,600,*,RIGHT,PTIE ++S 4100,9300,4900,9300,600,*,RIGHT,NTIE ++S 2000,6500,2000,8100,600,*,UP,PDIF ++S 800,7000,800,8100,400,*,UP,ALU1 ++S 3000,7000,3000,8000,400,*,UP,ALU1 ++S 800,7000,3000,7000,400,*,RIGHT,ALU1 ++S 2000,7900,2000,9300,400,*,DOWN,ALU1 ++S 3000,8000,5300,8000,400,*,RIGHT,ALU1 ++S 3000,6000,4000,6000,600,*,RIGHT,ALU1 ++S 4000,5900,4000,7100,400,*,UP,ALU1 ++S 3000,2900,3000,6100,400,*,UP,ALU1 ++S 3000,3000,3000,6000,400,z,DOWN,CALU1 ++S 4000,6000,4000,7000,400,z,DOWN,CALU1 ++S 1400,1300,1400,1700,200,*,DOWN,POLY ++S 700,2000,5200,2000,400,*,RIGHT,ALU1 ++S 1400,2600,1400,6300,200,*,UP,POLY ++S 1400,1700,1400,2600,200,07,UP,NTRANS ++S 1000,1900,1000,2400,400,*,DOWN,NDIF ++S 6400,7900,6400,9300,400,*,UP,ALU1 ++S 6400,6500,6400,8100,600,*,DOWN,PDIF ++S 1400,8300,1400,8700,200,*,DOWN,POLY ++S 2600,8300,2600,8700,200,*,DOWN,POLY ++S 3400,8300,3400,8700,200,*,DOWN,POLY ++S 4600,8300,4600,8700,200,*,DOWN,POLY ++S 5800,8300,5800,8700,200,*,DOWN,POLY ++S 2600,2100,2600,2500,200,*,DOWN,POLY ++S 6400,700,6400,3100,400,*,DOWN,ALU1 ++S 5200,2000,5200,3100,400,*,UP,ALU1 ++S 5800,2100,5800,2500,200,*,DOWN,POLY ++S 4600,2100,4600,2500,200,*,DOWN,POLY ++S 3400,2100,3400,2500,200,*,DOWN,POLY ++S 1000,5000,2100,5000,600,*,LEFT,ALU1 ++S 1400,5000,2600,5000,600,*,RIGHT,POLY ++S 5800,3400,5800,6300,200,*,UP,POLY ++S 4600,3400,4600,6300,200,*,UP,POLY ++S 2600,3400,2600,6300,200,*,UP,POLY ++S 3400,3400,3400,6300,200,*,UP,POLY ++S 2600,2500,2600,3400,200,06,UP,NTRANS ++S 3000,2700,3000,3200,600,n3,UP,NDIF ++S 3400,2500,3400,3400,200,08,UP,NTRANS ++S 4000,2700,4000,3200,1000,*,UP,NDIF ++S 4600,2500,4600,3400,200,10,UP,NTRANS ++S 5200,2700,5200,3200,1000,*,UP,NDIF ++S 5800,2500,5800,3400,200,09,UP,NTRANS ++S 6400,2700,6400,3200,600,*,UP,NDIF ++S 3800,4000,6000,4000,600,*,RIGHT,ALU1 ++S 6000,4000,6000,6100,400,*,DOWN,ALU1 ++S 5000,4900,5000,7000,400,*,UP,ALU1 ++S 5000,7100,6100,7100,400,*,LEFT,ALU1 ++S 5000,7000,6100,7000,400,*,LEFT,ALU1 ++S 5000,5000,5000,7000,400,c,DOWN,CALU1 ++S 6000,4000,6000,6000,400,b,UP,CALU1 ++S 3000,2900,4100,2900,400,*,RIGHT,ALU1 ++S 0,9400,7000,9400,1200,vdd,RIGHT,CALU1 ++S 0,600,7000,600,1200,vss,RIGHT,CALU1 ++S 0,5000,7000,5000,10000,cgi2_x05,LEFT,TALU8 ++S 0,2200,7000,2200,5200,*,LEFT,PWELL ++S 0,7600,7000,7600,5600,*,LEFT,NWELL ++S 3000,3000,4100,3000,400,*,RIGHT,ALU1 ++S 5800,6300,5800,8300,200,04,DOWN,PTRANS ++S 4600,6300,4600,8300,200,05,DOWN,PTRANS ++S 5200,6500,5200,8100,1000,*,UP,PDIF ++S 3000,6500,3000,8100,600,n1,DOWN,PDIF ++S 2600,6300,2600,8300,200,01,DOWN,PTRANS ++S 3400,6300,3400,8300,200,03,DOWN,PTRANS ++S 1400,6300,1400,8300,200,02,DOWN,PTRANS ++S 1000,6500,1000,8100,400,*,UP,PDIF ++S 4000,6500,4000,8100,1000,*,UP,PDIF ++S 2000,5000,2000,5000,400,a,LEFT,CALU1 ++S 4000,3000,4000,3000,400,z,LEFT,CALU1 ++S 4000,4000,4000,4000,400,b,LEFT,CALU1 ++S 5000,4000,5000,4000,400,b,LEFT,CALU1 ++S 6000,7000,6000,7000,400,c,LEFT,CALU1 ++S 2000,900,2000,3200,600,*,UP,NDIF ++S 1000,4000,1000,6000,400,a,DOWN,CALU1 ++S 1000,3900,1000,6100,400,*,DOWN,ALU1 ++S 800,7300,800,7900,600,*,UP,PDIF ++V 5000,700,CONT_BODY_P,* ++V 6000,700,CONT_BODY_P,* ++V 5000,9300,CONT_BODY_N,* ++V 4000,9300,CONT_BODY_N,* ++V 2000,8000,CONT_DIF_P,* ++V 800,2000,CONT_DIF_N,n4 ++V 6400,8000,CONT_DIF_P,* ++V 5200,3000,CONT_DIF_N,n4 ++V 4000,3000,CONT_DIF_N,* ++V 2000,5000,CONT_POLY,* ++V 3800,4000,CONT_POLY,* ++V 6000,5000,CONT_POLY,* ++V 5000,5000,CONT_POLY,* ++V 4000,7000,CONT_DIF_P,* ++V 2000,1000,CONT_DIF_N,* ++V 800,8000,CONT_DIF_P,n2 ++V 5200,8000,CONT_DIF_P,n2 ++V 6400,3000,CONT_DIF_N,* ++V 800,7200,CONT_DIF_P,n2 ++EOF +diff --git a/alliance/src/cells/src/msxlib/cgi2_x05.vbe b/alliance/src/cells/src/msxlib/cgi2_x05.vbe +new file mode 100644 +index 0000000..889ec26 +--- /dev/null ++++ b/alliance/src/cells/src/msxlib/cgi2_x05.vbe +@@ -0,0 +1,38 @@ ++ENTITY cgi2_x05 IS ++GENERIC ( ++ CONSTANT area : NATURAL := 7000; ++ CONSTANT cin_a : NATURAL := 6; ++ CONSTANT cin_b : NATURAL := 6; ++ CONSTANT cin_c : NATURAL := 3; ++ CONSTANT rdown_a_z : NATURAL := 4120; ++ CONSTANT rdown_b_z : NATURAL := 4130; ++ CONSTANT rdown_c_z : NATURAL := 4100; ++ CONSTANT rup_a_z : NATURAL := 5810; ++ CONSTANT rup_b_z : NATURAL := 5850; ++ CONSTANT rup_c_z : NATURAL := 5850; ++ CONSTANT tphl_c_z : NATURAL := 53; ++ CONSTANT tphl_b_z : NATURAL := 62; ++ CONSTANT tplh_a_z : NATURAL := 81; ++ CONSTANT tplh_c_z : NATURAL := 58; ++ CONSTANT tplh_b_z : NATURAL := 75; ++ CONSTANT tphl_a_z : NATURAL := 61; ++ CONSTANT transistors : NATURAL := 10 ++); ++PORT ( ++ a : in BIT; ++ b : in BIT; ++ c : in BIT; ++ z : out BIT; ++ vdd : in BIT; ++ vss : in BIT ++); ++END cgi2_x05; ++ ++ARCHITECTURE behaviour_data_flow OF cgi2_x05 IS ++ ++BEGIN ++ ASSERT ((vdd and not (vss)) = '1') ++ REPORT "power supply is missing on cgi2_x05" ++ SEVERITY WARNING; ++ z <= not((b or (a and c)) and (a or c)) after 1100 ps; ++END; +diff --git a/alliance/src/cells/src/msxlib/cgi2_x1.ap b/alliance/src/cells/src/msxlib/cgi2_x1.ap +new file mode 100644 +index 0000000..5dd80f3 +--- /dev/null ++++ b/alliance/src/cells/src/msxlib/cgi2_x1.ap +@@ -0,0 +1,128 @@ ++V ALLIANCE : 6 ++H cgi2_x1,P, 8/ 8/2014,100 ++A 0,0,7000,10000 ++R 4000,5000,ref_ref,b_50 ++R 4000,6000,ref_ref,z_60 ++R 1000,6000,ref_ref,a_60 ++R 1000,5000,ref_ref,a_50 ++R 6000,6000,ref_ref,b_60 ++R 3000,6000,ref_ref,z_60 ++R 3000,5000,ref_ref,z_50 ++R 3000,4000,ref_ref,z_40 ++R 4000,3000,ref_ref,z_30 ++R 4000,7000,ref_ref,z_70 ++R 1000,4000,ref_ref,a_40 ++R 2000,5000,ref_ref,a_50 ++R 4000,4000,ref_ref,b_40 ++R 6000,5000,ref_ref,b_50 ++R 5000,5000,ref_ref,c_50 ++R 3000,3000,ref_ref,z_30 ++R 5000,6000,ref_ref,c_60 ++R 5000,7000,ref_ref,c_70 ++R 6000,7000,ref_ref,c_70 ++R 5000,4000,ref_ref,b_40 ++R 6000,4000,ref_ref,b_40 ++S 5100,700,5900,700,600,*,RIGHT,PTIE ++S 1400,9400,1400,9700,200,*,DOWN,POLY ++S 2600,9400,2600,9700,200,*,DOWN,POLY ++S 3400,9400,3400,9700,200,*,DOWN,POLY ++S 4600,9400,4600,9700,200,*,DOWN,POLY ++S 5800,9400,5800,9700,200,*,DOWN,POLY ++S 1400,1300,1400,1700,200,*,DOWN,POLY ++S 2600,1300,2600,1700,200,*,DOWN,POLY ++S 3400,1300,3400,1700,200,*,DOWN,POLY ++S 4600,1300,4600,1700,200,*,DOWN,POLY ++S 5800,1300,5800,1700,200,*,DOWN,POLY ++S 4000,4000,4000,5000,400,b,UP,CALU1 ++S 3900,3900,3900,5100,600,*,UP,ALU1 ++S 4000,4000,6000,4000,400,*,RIGHT,ALU1 ++S 4000,3900,6000,3900,400,*,RIGHT,ALU1 ++S 6000,4000,6000,6100,400,*,DOWN,ALU1 ++S 700,2000,5200,2000,400,*,RIGHT,ALU1 ++S 2000,900,2000,3300,600,*,UP,NDIF ++S 1400,1700,1400,3500,200,07,UP,NTRANS ++S 1000,1900,1000,3300,400,*,DOWN,NDIF ++S 2000,7900,2000,9300,400,*,DOWN,ALU1 ++S 3000,8000,5300,8000,400,*,RIGHT,ALU1 ++S 3000,7000,3000,8000,400,*,UP,ALU1 ++S 1000,3900,1000,6100,400,*,DOWN,ALU1 ++S 1000,4000,1000,6000,400,a,DOWN,CALU1 ++S 5000,4900,5000,7000,600,*,UP,ALU1 ++S 1400,3900,1400,5500,200,*,UP,POLY ++S 2600,3500,2600,5500,200,*,UP,POLY ++S 1400,4900,2600,4900,600,*,RIGHT,POLY ++S 1000,4900,2100,4900,600,*,LEFT,ALU1 ++S 4000,6000,4000,7100,400,*,UP,ALU1 ++S 4000,6000,4000,7000,400,z,UP,CALU1 ++S 3000,3000,3000,6000,400,*,UP,ALU1 ++S 3000,3000,3000,6000,400,z,DOWN,CALU1 ++S 3000,6000,4000,6000,600,*,RIGHT,ALU1 ++S 0,600,7000,600,1200,vss,RIGHT,CALU1 ++S 0,9400,7000,9400,1200,vdd,RIGHT,CALU1 ++S 0,5000,7000,5000,10000,cgi2_x1,LEFT,TALU8 ++S 0,2200,7000,2200,5200,*,LEFT,PWELL ++S 0,7600,7000,7600,5600,*,LEFT,NWELL ++S 3000,3000,4100,3000,400,*,RIGHT,ALU1 ++S 6400,5700,6400,9200,600,*,DOWN,PDIF ++S 1000,5700,1000,9200,400,*,UP,PDIF ++S 5200,5700,5200,9200,1000,*,UP,PDIF ++S 4000,5700,4000,9200,1000,*,UP,PDIF ++S 2000,5700,2000,9200,1000,*,UP,PDIF ++S 2600,5500,2600,9400,200,01,DOWN,PTRANS ++S 1400,5500,1400,9400,200,02,DOWN,PTRANS ++S 3400,5500,3400,9400,200,03,DOWN,PTRANS ++S 5800,5500,5800,9400,200,04,DOWN,PTRANS ++S 4600,5500,4600,9400,200,05,DOWN,PTRANS ++S 3000,5700,3000,9200,600,n1,DOWN,PDIF ++S 6400,7900,6400,9300,400,*,UP,ALU1 ++S 6400,1900,6400,3300,600,*,UP,NDIF ++S 5800,1700,5800,3500,200,09,UP,NTRANS ++S 5200,1900,5200,3300,1000,*,UP,NDIF ++S 4600,1700,4600,3500,200,10,UP,NTRANS ++S 4000,1900,4000,3300,1000,*,UP,NDIF ++S 3400,1700,3400,3500,200,08,UP,NTRANS ++S 3000,1900,3000,3300,600,n3,UP,NDIF ++S 2600,1700,2600,3500,200,06,UP,NTRANS ++S 5300,2000,5300,3100,400,*,UP,ALU1 ++S 5200,2000,5200,3100,400,*,UP,ALU1 ++S 6400,700,6400,3100,400,*,DOWN,ALU1 ++S 3000,2900,4100,2900,400,*,RIGHT,ALU1 ++S 5000,7000,6100,7000,400,*,LEFT,ALU1 ++S 6000,4000,6000,6000,400,b,UP,CALU1 ++S 3400,3500,3400,5500,200,*,UP,POLY ++S 4600,3500,4600,5500,200,*,UP,POLY ++S 5800,3500,5800,5500,200,*,UP,POLY ++S 5000,5000,5000,7000,400,c,DOWN,CALU1 ++S 800,7000,3000,7000,400,*,RIGHT,ALU1 ++S 800,7000,800,8100,400,*,DOWN,ALU1 ++S 800,7300,800,7900,600,*,DOWN,PDIF ++S 2000,5000,2000,5000,400,a,LEFT,CALU1 ++S 4000,3000,4000,3000,400,z,LEFT,CALU1 ++S 5000,4000,5000,4000,400,b,LEFT,CALU1 ++S 6000,7000,6000,7000,400,c,LEFT,CALU1 ++S 800,2100,800,2700,600,*,UP,NDIF ++S 800,2000,800,2800,600,*,DOWN,ALU1 ++V 6000,700,CONT_BODY_P,* ++V 5000,700,CONT_BODY_P,* ++V 4000,7000,CONT_DIF_P,* ++V 3800,4900,CONT_POLY,* ++V 800,2000,CONT_DIF_N,n4 ++V 2000,8000,CONT_DIF_P,* ++V 4000,6000,CONT_DIF_P,* ++V 2000,4900,CONT_POLY,* ++V 6000,4900,CONT_POLY,* ++V 5000,4900,CONT_POLY,* ++V 4000,3000,CONT_DIF_N,* ++V 2000,1000,CONT_DIF_N,* ++V 5200,8000,CONT_DIF_P,n2 ++V 2000,9000,CONT_DIF_P,* ++V 6400,9000,CONT_DIF_P,* ++V 6400,8000,CONT_DIF_P,* ++V 6400,2000,CONT_DIF_N,* ++V 5200,2000,CONT_DIF_N,n4 ++V 5200,3000,CONT_DIF_N,n4 ++V 6400,3000,CONT_DIF_N,* ++V 800,8000,CONT_DIF_P,n2 ++V 800,7200,CONT_DIF_P,n2 ++V 800,2800,CONT_DIF_N,n4 ++EOF +diff --git a/alliance/src/cells/src/msxlib/cgi2_x1.vbe b/alliance/src/cells/src/msxlib/cgi2_x1.vbe +new file mode 100644 +index 0000000..161a55e +--- /dev/null ++++ b/alliance/src/cells/src/msxlib/cgi2_x1.vbe +@@ -0,0 +1,38 @@ ++ENTITY cgi2_x1 IS ++GENERIC ( ++ CONSTANT area : NATURAL := 7000; ++ CONSTANT cin_a : NATURAL := 12; ++ CONSTANT cin_b : NATURAL := 12; ++ CONSTANT cin_c : NATURAL := 6; ++ CONSTANT rdown_a_z : NATURAL := 2050; ++ CONSTANT rdown_b_z : NATURAL := 2060; ++ CONSTANT rdown_c_z : NATURAL := 2050; ++ CONSTANT rup_a_z : NATURAL := 2980; ++ CONSTANT rup_b_z : NATURAL := 3000; ++ CONSTANT rup_c_z : NATURAL := 3000; ++ CONSTANT tphl_c_z : NATURAL := 51; ++ CONSTANT tphl_b_z : NATURAL := 58; ++ CONSTANT tplh_a_z : NATURAL := 76; ++ CONSTANT tplh_c_z : NATURAL := 56; ++ CONSTANT tplh_b_z : NATURAL := 71; ++ CONSTANT tphl_a_z : NATURAL := 57; ++ CONSTANT transistors : NATURAL := 10 ++); ++PORT ( ++ a : in BIT; ++ b : in BIT; ++ c : in BIT; ++ z : out BIT; ++ vdd : in BIT; ++ vss : in BIT ++); ++END cgi2_x1; ++ ++ARCHITECTURE behaviour_data_flow OF cgi2_x1 IS ++ ++BEGIN ++ ASSERT ((vdd and not (vss)) = '1') ++ REPORT "power supply is missing on cgi2_x1" ++ SEVERITY WARNING; ++ z <= not((b or (a and c)) and (a or c)) after 1100 ps; ++END; +diff --git a/alliance/src/cells/src/msxlib/cgi2_x2.ap b/alliance/src/cells/src/msxlib/cgi2_x2.ap +new file mode 100644 +index 0000000..190441e +--- /dev/null ++++ b/alliance/src/cells/src/msxlib/cgi2_x2.ap +@@ -0,0 +1,214 @@ ++V ALLIANCE : 6 ++H cgi2_x2,P, 8/ 8/2014,100 ++A 0,0,13000,10000 ++R 1000,4000,ref_ref,a_50 ++R 8000,2000,ref_ref,z_20 ++R 5000,5000,ref_ref,b_50 ++R 2000,3000,ref_ref,c_30 ++R 6000,4000,ref_ref,b_40 ++R 7000,4000,ref_ref,b_40 ++R 8000,4000,ref_ref,b_40 ++R 9000,4000,ref_ref,b_40 ++R 5000,4000,ref_ref,b_40 ++R 9000,6000,ref_ref,a_60 ++R 1000,6000,ref_ref,a_60 ++R 2000,7000,ref_ref,a_70 ++R 3000,7000,ref_ref,a_70 ++R 4000,7000,ref_ref,a_70 ++R 5000,7000,ref_ref,a_70 ++R 6000,7000,ref_ref,a_70 ++R 7000,7000,ref_ref,a_70 ++R 8000,7000,ref_ref,a_70 ++R 8000,5000,ref_ref,a_50 ++R 7000,5000,ref_ref,a_50 ++R 9000,7000,ref_ref,a_70 ++R 9000,5000,ref_ref,a_50 ++R 6000,5000,ref_ref,a_50 ++R 1000,5000,ref_ref,a_50 ++R 7000,3000,ref_ref,z_30 ++R 6000,3000,ref_ref,z_30 ++R 5000,3000,ref_ref,z_30 ++R 3000,3000,ref_ref,z_30 ++R 4000,3000,ref_ref,z_30 ++R 4000,4000,ref_ref,z_40 ++R 4000,5000,ref_ref,z_50 ++R 3000,6000,ref_ref,z_60 ++R 4000,6000,ref_ref,z_60 ++R 5000,6000,ref_ref,z_60 ++R 6000,6000,ref_ref,z_60 ++R 7000,6000,ref_ref,z_60 ++R 10000,4000,ref_ref,b_40 ++R 2000,5000,ref_ref,c_50 ++R 2000,6000,ref_ref,c_60 ++R 3000,5000,ref_ref,c_50 ++R 2000,4000,ref_ref,c_40 ++R 11000,5000,ref_ref,b_50 ++R 11000,3000,ref_ref,b_30 ++R 11000,4000,ref_ref,b_40 ++S 11100,700,11900,700,600,*,RIGHT,PTIE ++S 1000,3900,1000,7000,400,*,UP,ALU1 ++S 5700,800,5700,3700,1200,*,UP,NDIF ++S 5700,700,5700,2100,400,*,DOWN,ALU1 ++S 5800,4600,6600,4600,200,*,LEFT,POLY ++S 6600,3400,6600,4600,200,*,UP,POLY ++S 6000,5000,6000,5700,200,*,DOWN,POLY ++S 6600,1300,6600,1700,200,*,DOWN,POLY ++S 6600,1700,6600,3400,200,7a,UP,NTRANS ++S 7000,1900,7000,3200,400,n3b,UP,NDIF ++S 7400,3400,7400,5300,200,*,UP,POLY ++S 6800,5300,8000,5300,200,*,LEFT,POLY ++S 8000,2000,8000,2000,400,z,LEFT,CALU1 ++S 2900,3000,8000,3000,400,*,RIGHT,ALU1 ++S 7400,1300,7400,1700,200,*,DOWN,POLY ++S 7400,1700,7400,3400,200,7b,UP,NTRANS ++S 8000,1900,8000,3200,600,*,DOWN,NDIF ++S 8000,1900,8000,3000,400,*,DOWN,ALU1 ++S 7800,3800,8600,3800,200,*,LEFT,POLY ++S 8600,1300,8600,1700,200,*,DOWN,POLY ++S 8600,1700,8600,3400,200,8b,UP,NTRANS ++S 9000,1900,9000,3200,400,n3a,UP,NDIF ++S 9400,3400,9400,5200,200,*,UP,POLY ++S 8800,5000,8800,5700,200,*,DOWN,POLY ++S 9400,1700,9400,3400,200,8a,UP,NTRANS ++S 9400,1300,9400,1700,200,*,DOWN,POLY ++S 10100,1900,10100,3200,600,*,UP,NDIF ++S 10000,700,10000,3100,400,*,DOWN,ALU1 ++S 5000,4000,5000,5000,400,b,UP,CALU1 ++S 5000,4000,5000,5000,600,*,DOWN,ALU1 ++S 2000,3000,2000,6000,400,c,DOWN,CALU1 ++S 2000,2900,2000,6100,400,*,DOWN,ALU1 ++S 1700,2000,4300,2000,400,*,RIGHT,ALU1 ++S 6400,5900,6400,9200,400,n1b,UP,PDIF ++S 8400,5900,8400,9200,400,n1a,UP,PDIF ++S 4800,600,4800,3900,200,5b,UP,NTRANS ++S 8000,5700,8000,9400,200,4b,DOWN,PTRANS ++S 6800,5700,6800,9400,200,3b,DOWN,PTRANS ++S 10000,5700,10000,9400,200,2b,DOWN,PTRANS ++S 11200,5700,11200,9400,200,1b,DOWN,PTRANS ++S 1200,600,1200,3900,200,5a,UP,NTRANS ++S 8800,5700,8800,9400,200,4a,DOWN,PTRANS ++S 6000,5700,6000,9400,200,3a,DOWN,PTRANS ++S 4800,5700,4800,9400,200,2a,DOWN,PTRANS ++S 1200,5700,1200,9400,200,1a,DOWN,PTRANS ++S 3600,1700,3600,3400,200,4c,UP,NTRANS ++S 2400,1700,2400,3400,200,3c,UP,NTRANS ++S 3600,5700,3600,9400,200,2c,DOWN,PTRANS ++S 2400,5700,2400,9400,200,1c,DOWN,PTRANS ++S 11200,9400,11200,9700,200,*,DOWN,POLY ++S 10000,9400,10000,9700,200,*,DOWN,POLY ++S 8800,9400,8800,9700,200,*,DOWN,POLY ++S 8000,9400,8000,9700,200,*,DOWN,POLY ++S 6800,9400,6800,9700,200,*,DOWN,POLY ++S 6000,9400,6000,9700,200,*,DOWN,POLY ++S 4800,9400,4800,9700,200,*,DOWN,POLY ++S 3600,9400,3600,9700,200,*,DOWN,POLY ++S 2400,9400,2400,9700,200,*,DOWN,POLY ++S 1200,9400,1200,9700,200,*,DOWN,POLY ++S 1200,300,1200,600,200,*,DOWN,POLY ++S 3600,1300,3600,1700,200,*,DOWN,POLY ++S 4800,300,4800,600,200,*,DOWN,POLY ++S 600,700,600,3100,400,*,DOWN,ALU1 ++S 11800,6900,11800,9300,400,*,UP,ALU1 ++S 10600,6900,10600,8000,400,*,DOWN,ALU1 ++S 1700,8000,10600,8000,400,*,RIGHT,ALU1 ++S 600,7900,600,9300,400,*,UP,ALU1 ++S 600,5900,600,9200,600,*,DOWN,PDIF ++S 10600,5900,10600,9200,600,*,UP,PDIF ++S 9400,5900,9400,9200,600,*,UP,PDIF ++S 7400,5900,7400,9200,600,*,UP,PDIF ++S 5400,5900,5400,9200,600,*,UP,PDIF ++S 4200,5900,4200,9200,600,*,UP,PDIF ++S 1800,5900,1800,9200,600,*,DOWN,PDIF ++S 2400,3400,2400,5700,200,*,DOWN,POLY ++S 3600,3400,3600,5700,200,*,DOWN,POLY ++S 1200,3900,1200,5700,200,*,DOWN,POLY ++S 4800,5300,6200,5300,200,*,RIGHT,POLY ++S 10000,5200,10000,5700,200,*,DOWN,POLY ++S 11200,5200,11200,5700,200,*,DOWN,POLY ++S 10000,5200,11200,5200,200,*,LEFT,POLY ++S 11900,5900,11900,9200,600,*,DOWN,PDIF ++S 3000,5900,3000,9200,1000,*,UP,PDIF ++S 4400,800,4400,3700,400,*,DOWN,NDIF ++S 4200,1900,4200,3200,600,*,UP,NDIF ++S 1600,800,1600,3700,400,*,UP,NDIF ++S 1800,1900,1800,3200,600,*,UP,NDIF ++S 600,800,600,3700,600,*,UP,NDIF ++S 3000,1900,3000,3200,600,*,DOWN,NDIF ++S 9000,4000,9000,4000,400,b,LEFT,CALU1 ++S 8000,4000,8000,4000,400,b,LEFT,CALU1 ++S 7000,4000,7000,4000,400,b,LEFT,CALU1 ++S 6000,4000,6000,4000,400,b,LEFT,CALU1 ++S 9000,5000,9000,7000,600,*,UP,ALU1 ++S 9000,5000,9000,7000,400,a,UP,CALU1 ++S 6000,5000,6000,5000,400,a,LEFT,CALU1 ++S 8000,5000,8000,5000,400,a,LEFT,CALU1 ++S 7000,5000,7000,5000,400,a,LEFT,CALU1 ++S 5900,5000,9000,5000,400,*,RIGHT,ALU1 ++S 8000,7000,8000,7000,400,a,LEFT,CALU1 ++S 7000,7000,7000,7000,400,a,LEFT,CALU1 ++S 6000,7000,6000,7000,400,a,LEFT,CALU1 ++S 5000,7000,5000,7000,400,a,LEFT,CALU1 ++S 4000,7000,4000,7000,400,a,LEFT,CALU1 ++S 3000,7000,3000,7000,400,a,LEFT,CALU1 ++S 2000,7000,2000,7000,400,a,LEFT,CALU1 ++S 2900,6000,7500,6000,400,*,RIGHT,ALU1 ++S 5000,6000,5000,6000,400,z,LEFT,CALU1 ++S 6000,6000,6000,6000,400,z,LEFT,CALU1 ++S 7000,6000,7000,6000,400,z,LEFT,CALU1 ++S 0,5000,13000,5000,10000,cgi2_x2,LEFT,TALU8 ++S 0,2200,13000,2200,5200,*,LEFT,PWELL ++S 0,7600,13000,7600,5600,*,LEFT,NWELL ++S 0,600,13000,600,1200,vss,RIGHT,CALU1 ++S 0,9400,13000,9400,1200,vdd,RIGHT,CALU1 ++S 5000,3000,5000,3000,400,z,LEFT,CALU1 ++S 3000,6000,3000,6000,400,z,LEFT,CALU1 ++S 3000,3000,3000,3000,400,z,LEFT,CALU1 ++S 6000,3000,6000,3000,400,z,LEFT,CALU1 ++S 7000,3000,7000,3000,400,z,LEFT,CALU1 ++S 4000,3000,4000,6000,400,*,DOWN,ALU1 ++S 4000,3000,4000,6000,400,z,DOWN,CALU1 ++S 3000,5000,3000,5000,400,c,LEFT,CALU1 ++S 2400,5000,3600,5000,600,*,RIGHT,POLY ++S 2000,5000,3100,5000,400,*,LEFT,ALU1 ++S 1000,7000,9000,7000,400,*,RIGHT,ALU1 ++S 2400,1300,2400,1700,200,*,DOWN,POLY ++S 11000,3000,11000,5000,400,b,DOWN,CALU1 ++S 11000,2900,11000,5100,400,*,DOWN,ALU1 ++S 10000,4000,10000,4000,400,b,LEFT,CALU1 ++S 4900,4000,11000,4000,400,*,RIGHT,ALU1 ++S 1000,4000,1000,6000,400,a,UP,CALU1 ++V 12000,700,CONT_BODY_P,* ++V 11000,700,CONT_BODY_P,* ++V 5700,1000,CONT_DIF_N,* ++V 5700,2000,CONT_DIF_N,* ++V 7600,4000,CONT_POLY,* ++V 8000,2800,CONT_DIF_N,* ++V 8000,2000,CONT_DIF_N,* ++V 10000,3000,CONT_DIF_N,* ++V 10000,2000,CONT_DIF_N,* ++V 1800,2000,CONT_DIF_N,n4 ++V 9400,9000,CONT_DIF_P,* ++V 600,3000,CONT_DIF_N,* ++V 600,2000,CONT_DIF_N,* ++V 11800,7000,CONT_DIF_P,* ++V 10600,7800,CONT_DIF_P,n2 ++V 10600,7000,CONT_DIF_P,n2 ++V 600,8000,CONT_DIF_P,* ++V 5000,4500,CONT_POLY,* ++V 9000,5000,CONT_POLY,* ++V 6000,5000,CONT_POLY,* ++V 3000,6000,CONT_DIF_P,* ++V 11800,9000,CONT_DIF_P,* ++V 11800,8000,CONT_DIF_P,* ++V 7400,6000,CONT_DIF_P,* ++V 4200,8000,CONT_DIF_P,n2 ++V 5400,9000,CONT_DIF_P,* ++V 1800,8000,CONT_DIF_P,n2 ++V 4200,2000,CONT_DIF_N,n4 ++V 3000,3000,CONT_DIF_N,* ++V 600,1000,CONT_DIF_N,* ++V 600,9000,CONT_DIF_P,* ++V 3000,5000,CONT_POLY,* ++V 1000,5000,CONT_POLY,* ++V 11000,5000,CONT_POLY,* ++EOF +diff --git a/alliance/src/cells/src/msxlib/cgi2_x2.vbe b/alliance/src/cells/src/msxlib/cgi2_x2.vbe +new file mode 100644 +index 0000000..f45887b +--- /dev/null ++++ b/alliance/src/cells/src/msxlib/cgi2_x2.vbe +@@ -0,0 +1,38 @@ ++ENTITY cgi2_x2 IS ++GENERIC ( ++ CONSTANT area : NATURAL := 13000; ++ CONSTANT cin_a : NATURAL := 24; ++ CONSTANT cin_b : NATURAL := 21; ++ CONSTANT cin_c : NATURAL := 11; ++ CONSTANT rdown_a_z : NATURAL := 1090; ++ CONSTANT rdown_b_z : NATURAL := 1100; ++ CONSTANT rdown_c_z : NATURAL := 1100; ++ CONSTANT rup_a_z : NATURAL := 1570; ++ CONSTANT rup_b_z : NATURAL := 1580; ++ CONSTANT rup_c_z : NATURAL := 1580; ++ CONSTANT tphl_c_z : NATURAL := 52; ++ CONSTANT tphl_b_z : NATURAL := 58; ++ CONSTANT tplh_a_z : NATURAL := 77; ++ CONSTANT tplh_c_z : NATURAL := 57; ++ CONSTANT tplh_b_z : NATURAL := 70; ++ CONSTANT tphl_a_z : NATURAL := 58; ++ CONSTANT transistors : NATURAL := 18 ++); ++PORT ( ++ a : in BIT; ++ b : in BIT; ++ c : in BIT; ++ z : out BIT; ++ vdd : in BIT; ++ vss : in BIT ++); ++END cgi2_x2; ++ ++ARCHITECTURE behaviour_data_flow OF cgi2_x2 IS ++ ++BEGIN ++ ASSERT ((vdd and not (vss)) = '1') ++ REPORT "power supply is missing on cgi2_x2" ++ SEVERITY WARNING; ++ z <= not((b or (a and c)) and (a or c)) after 1100 ps; ++END; +diff --git a/alliance/src/cells/src/msxlib/cgi2a_x05.ap b/alliance/src/cells/src/msxlib/cgi2a_x05.ap +new file mode 100644 +index 0000000..d4dd197 +--- /dev/null ++++ b/alliance/src/cells/src/msxlib/cgi2a_x05.ap +@@ -0,0 +1,138 @@ ++V ALLIANCE : 6 ++H cgi2a_x05,P, 8/ 8/2014,100 ++A 0,0,8000,10000 ++R 7000,7000,ref_ref,a_70 ++R 6000,7000,ref_ref,a_70 ++R 6000,6000,ref_ref,a_60 ++R 6000,5000,ref_ref,a_50 ++R 5000,7000,ref_ref,c_70 ++R 4000,5000,ref_ref,c_50 ++R 5000,6000,ref_ref,c_60 ++R 3000,3000,ref_ref,z_30 ++R 4000,7000,ref_ref,z_70 ++R 3000,4000,ref_ref,z_40 ++R 3000,5000,ref_ref,z_50 ++R 3000,6000,ref_ref,z_60 ++R 4000,6000,ref_ref,z_60 ++R 1000,4000,ref_ref,b_40 ++R 2000,5000,ref_ref,b_50 ++R 1000,5000,ref_ref,b_50 ++R 1000,6000,ref_ref,b_60 ++R 5000,5000,ref_ref,c_50 ++R 4000,3000,ref_ref,z_30 ++S 4100,700,4900,700,600,*,LEFT,PTIE ++S 1100,9300,1900,9300,600,*,LEFT,NTIE ++S 1400,1300,1400,1700,200,*,DOWN,POLY ++S 1400,2600,1400,5200,200,*,UP,POLY ++S 1400,1700,1400,2600,200,3b,UP,NTRANS ++S 1000,1900,1000,2400,400,*,DOWN,NDIF ++S 2400,4800,2400,6300,200,*,UP,POLY ++S 1800,5000,2400,5000,600,*,RIGHT,POLY ++S 6800,3800,6800,5700,200,*,DOWN,POLY ++S 5600,3700,5600,6300,200,*,UP,POLY ++S 4400,5100,4400,6300,200,*,DOWN,POLY ++S 3200,4000,3200,6300,200,*,UP,POLY ++S 6400,700,6400,1500,400,*,UP,ALU1 ++S 6300,1300,6300,3500,400,*,UP,NDIF ++S 6800,2000,6800,2400,200,*,DOWN,POLY ++S 7400,3300,7400,6100,400,*,UP,ALU1 ++S 6800,2400,6800,3700,200,2a,UP,NTRANS ++S 7200,2600,7200,3500,400,*,UP,NDIF ++S 2600,2000,2600,2400,200,*,DOWN,POLY ++S 3400,2000,3400,2400,200,*,DOWN,POLY ++S 4600,2000,4600,2400,200,*,DOWN,POLY ++S 5800,2000,5800,2400,200,*,DOWN,POLY ++S 700,2000,5300,2000,400,*,RIGHT,ALU1 ++S 5200,2000,5200,2700,600,*,UP,ALU1 ++S 2600,2400,2600,3300,200,4b,UP,NTRANS ++S 3000,2600,3000,3100,600,n3,UP,NDIF ++S 3400,2400,3400,3300,200,5a,UP,NTRANS ++S 4000,2600,4000,3100,1000,*,UP,NDIF ++S 5800,2400,5800,3300,200,6a,UP,NTRANS ++S 4600,2400,4600,3300,200,2c,UP,NTRANS ++S 5200,2600,5200,3100,1000,*,UP,NDIF ++S 6200,7900,6200,9300,400,*,UP,ALU1 ++S 6200,5900,6200,8100,600,*,DOWN,PDIF ++S 6000,4800,6000,7100,400,*,DOWN,ALU1 ++S 6000,5000,6000,7000,400,a,DOWN,CALU1 ++S 7000,7000,7000,7000,400,a,LEFT,CALU1 ++S 6000,7000,7000,7000,600,*,LEFT,ALU1 ++S 4000,6000,4000,7000,400,z,UP,CALU1 ++S 2000,5000,2000,5000,400,b,LEFT,CALU1 ++S 1000,4000,1000,6000,400,b,DOWN,CALU1 ++S 3400,3300,3400,4100,200,*,UP,POLY ++S 5800,3300,5800,4100,200,*,UP,POLY ++S 4600,3300,4600,5100,200,*,UP,POLY ++S 3000,2900,3000,6000,400,*,UP,ALU1 ++S 3000,3000,4100,3000,400,*,RIGHT,ALU1 ++S 3000,2900,4100,2900,400,*,RIGHT,ALU1 ++S 2000,900,2000,3100,600,*,UP,NDIF ++S 6000,4900,6600,4900,600,*,LEFT,ALU1 ++S 5000,4900,5000,7100,400,*,DOWN,ALU1 ++S 4000,5000,5000,5000,600,*,LEFT,ALU1 ++S 5000,5000,5000,7000,400,c,UP,CALU1 ++S 2800,8000,5100,8000,400,*,RIGHT,ALU1 ++S 3800,3900,7400,3900,600,*,RIGHT,ALU1 ++S 1800,7900,1800,9300,400,*,DOWN,ALU1 ++S 2800,7000,2800,8000,400,*,UP,ALU1 ++S 600,7000,600,8100,400,*,DOWN,ALU1 ++S 600,7000,2800,7000,400,*,RIGHT,ALU1 ++S 600,7300,600,7900,600,*,DOWN,PDIF ++S 1000,3900,1000,6100,400,*,DOWN,ALU1 ++S 1000,5000,2000,5000,600,*,LEFT,ALU1 ++S 0,5000,8000,5000,10000,cgi2a_x05,LEFT,TALU8 ++S 0,2200,8000,2200,5200,*,LEFT,PWELL ++S 0,7600,8000,7600,5600,*,LEFT,NWELL ++S 0,9400,8000,9400,1200,vdd,RIGHT,CALU1 ++S 0,600,8000,600,1200,vss,RIGHT,CALU1 ++S 3000,3000,3000,6000,400,z,DOWN,CALU1 ++S 3900,6000,3900,7100,600,*,UP,ALU1 ++S 3000,6000,4000,6000,600,*,RIGHT,ALU1 ++S 4000,3000,4000,3000,400,z,LEFT,CALU1 ++S 7200,5900,7200,8100,400,*,DOWN,PDIF ++S 6800,5700,6800,8300,200,1a,DOWN,PTRANS ++S 6200,5900,6200,8100,600,*,DOWN,PDIF ++S 5600,6300,5600,8300,200,4a,DOWN,PTRANS ++S 5000,6500,5000,8100,1000,*,UP,PDIF ++S 4400,6300,4400,8300,200,1c,DOWN,PTRANS ++S 3200,6300,3200,8300,200,3a,DOWN,PTRANS ++S 3800,6500,3800,8100,1000,*,UP,PDIF ++S 1800,6500,1800,8100,1000,*,UP,PDIF ++S 1200,6300,1200,8300,200,1b,DOWN,PTRANS ++S 2400,6300,2400,8300,200,2b,DOWN,PTRANS ++S 800,6500,800,8100,400,*,UP,PDIF ++S 2800,6500,2800,8100,600,n1,DOWN,PDIF ++S 3200,8300,3200,8700,200,*,DOWN,POLY ++S 4400,8300,4400,8700,200,*,DOWN,POLY ++S 5600,8300,5600,8700,200,*,DOWN,POLY ++S 6800,8300,6800,8700,200,*,DOWN,POLY ++S 1200,8300,1200,8700,200,*,DOWN,POLY ++S 2400,8300,2400,8700,200,*,DOWN,POLY ++S 4000,5000,4000,5000,400,c,LEFT,CALU1 ++S 2600,3300,2600,5200,200,*,UP,POLY ++S 1200,4800,1200,6300,200,*,UP,POLY ++S 1200,5000,2600,5000,600,*,LEFT,POLY ++S 3200,3900,4000,3900,600,*,LEFT,POLY ++V 5000,700,CONT_BODY_P,* ++V 4000,700,CONT_BODY_P,* ++V 2000,9300,CONT_BODY_N,* ++V 1000,9300,CONT_BODY_N,* ++V 800,2000,CONT_DIF_N,n4 ++V 1800,5000,CONT_POLY,* ++V 6400,1400,CONT_DIF_N,* ++V 7400,3400,CONT_DIF_N,an ++V 5200,2700,CONT_DIF_N,n4 ++V 6200,8000,CONT_DIF_P,* ++V 5600,3900,CONT_POLY,an ++V 4000,3000,CONT_DIF_N,* ++V 5000,8000,CONT_DIF_P,n2 ++V 3800,3900,CONT_POLY,an ++V 2000,1000,CONT_DIF_N,* ++V 6600,4900,CONT_POLY,* ++V 1800,8000,CONT_DIF_P,* ++V 3800,7000,CONT_DIF_P,* ++V 600,7200,CONT_DIF_P,n2 ++V 600,8000,CONT_DIF_P,n2 ++V 7400,6000,CONT_DIF_P,an ++V 4600,5100,CONT_POLY,* ++EOF +diff --git a/alliance/src/cells/src/msxlib/cgi2a_x05.vbe b/alliance/src/cells/src/msxlib/cgi2a_x05.vbe +new file mode 100644 +index 0000000..2695f96 +--- /dev/null ++++ b/alliance/src/cells/src/msxlib/cgi2a_x05.vbe +@@ -0,0 +1,38 @@ ++ENTITY cgi2a_x05 IS ++GENERIC ( ++ CONSTANT area : NATURAL := 8000; ++ CONSTANT cin_a : NATURAL := 5; ++ CONSTANT cin_b : NATURAL := 6; ++ CONSTANT cin_c : NATURAL := 4; ++ CONSTANT rdown_a_z : NATURAL := 4130; ++ CONSTANT rdown_b_z : NATURAL := 4120; ++ CONSTANT rdown_c_z : NATURAL := 4110; ++ CONSTANT rup_a_z : NATURAL := 5840; ++ CONSTANT rup_b_z : NATURAL := 5820; ++ CONSTANT rup_c_z : NATURAL := 5850; ++ CONSTANT tphl_c_z : NATURAL := 54; ++ CONSTANT tphl_b_z : NATURAL := 62; ++ CONSTANT tphh_a_z : NATURAL := 103; ++ CONSTANT tplh_c_z : NATURAL := 59; ++ CONSTANT tplh_b_z : NATURAL := 81; ++ CONSTANT tpll_a_z : NATURAL := 107; ++ CONSTANT transistors : NATURAL := 12 ++); ++PORT ( ++ a : in BIT; ++ b : in BIT; ++ c : in BIT; ++ z : out BIT; ++ vdd : in BIT; ++ vss : in BIT ++); ++END cgi2a_x05; ++ ++ARCHITECTURE behaviour_data_flow OF cgi2a_x05 IS ++ ++BEGIN ++ ASSERT ((vdd and not (vss)) = '1') ++ REPORT "power supply is missing on cgi2a_x05" ++ SEVERITY WARNING; ++ z <= not((not(a) or (b and c)) and (b or c)) after 1100 ps; ++END; +diff --git a/alliance/src/cells/src/msxlib/cgi2a_x1.ap b/alliance/src/cells/src/msxlib/cgi2a_x1.ap +new file mode 100644 +index 0000000..791922e +--- /dev/null ++++ b/alliance/src/cells/src/msxlib/cgi2a_x1.ap +@@ -0,0 +1,132 @@ ++V ALLIANCE : 6 ++H cgi2a_x1,P, 8/ 8/2014,100 ++A 0,0,8000,10000 ++R 4000,5000,ref_ref,z_50 ++R 4000,4000,ref_ref,z_40 ++R 6000,7000,ref_ref,a_70 ++R 6000,6000,ref_ref,a_60 ++R 6000,5000,ref_ref,a_50 ++R 5000,7000,ref_ref,c_70 ++R 5000,6000,ref_ref,c_60 ++R 3000,6000,ref_ref,z_60 ++R 4000,6000,ref_ref,z_60 ++R 1000,4000,ref_ref,b_40 ++R 2000,5000,ref_ref,b_50 ++R 1000,5000,ref_ref,b_50 ++R 1000,6000,ref_ref,b_60 ++R 5000,5000,ref_ref,c_50 ++R 4000,3000,ref_ref,z_30 ++R 7000,7000,ref_ref,a_70 ++R 4000,7000,ref_ref,c_70 ++S 4000,7000,4000,7000,400,c,LEFT,CALU1 ++S 3800,3000,4000,3000,600,*,RIGHT,ALU1 ++S 3000,6000,3000,6000,400,z,LEFT,CALU1 ++S 4000,3000,4000,6000,400,z,DOWN,CALU1 ++S 4000,2900,4000,6000,400,*,UP,ALU1 ++S 5300,3900,7400,3900,400,*,RIGHT,ALU1 ++S 3200,500,3200,1500,200,*,DOWN,POLY ++S 5600,500,5600,1500,200,*,DOWN,POLY ++S 3200,500,5600,500,200,*,RIGHT,POLY ++S 2000,5000,2000,5000,400,b,LEFT,CALU1 ++S 1000,4000,1000,6000,400,b,DOWN,CALU1 ++S 5000,5000,5000,7000,400,c,UP,CALU1 ++S 2800,8000,5100,8000,400,*,RIGHT,ALU1 ++S 1800,7900,1800,9300,400,*,DOWN,ALU1 ++S 2800,7000,2800,8000,400,*,UP,ALU1 ++S 600,7000,600,8100,400,*,DOWN,ALU1 ++S 600,7000,2800,7000,400,*,RIGHT,ALU1 ++S 5600,9400,5600,9700,200,*,DOWN,POLY ++S 4400,9400,4400,9700,200,*,DOWN,POLY ++S 3200,9400,3200,9700,200,*,DOWN,POLY ++S 2400,9400,2400,9700,200,*,DOWN,POLY ++S 1200,9400,1200,9700,200,*,DOWN,POLY ++S 1800,5700,1800,9200,1000,*,UP,PDIF ++S 3800,5700,3800,9200,1000,*,UP,PDIF ++S 5000,5700,5000,9200,1000,*,UP,PDIF ++S 800,5700,800,9200,400,*,UP,PDIF ++S 600,7300,600,7900,600,*,DOWN,PDIF ++S 2800,5700,2800,9200,600,n1,DOWN,PDIF ++S 1000,3900,1000,6100,400,*,DOWN,ALU1 ++S 1000,5000,2000,5000,600,*,LEFT,ALU1 ++S 0,5000,8000,5000,10000,cgi2a_x1,LEFT,TALU8 ++S 0,2200,8000,2200,5200,*,LEFT,PWELL ++S 0,7600,8000,7600,5600,*,LEFT,NWELL ++S 0,9400,8000,9400,1200,vdd,RIGHT,CALU1 ++S 0,600,8000,600,1200,vss,RIGHT,CALU1 ++S 3000,6000,4000,6000,600,*,RIGHT,ALU1 ++S 6200,5700,6200,9200,600,*,DOWN,PDIF ++S 7200,5700,7200,9200,400,*,DOWN,PDIF ++S 6800,9400,6800,9700,200,*,DOWN,POLY ++S 6800,5500,6800,9400,200,1a,DOWN,PTRANS ++S 1200,5500,1200,9400,200,1b,DOWN,PTRANS ++S 2400,5500,2400,9400,200,2b,DOWN,PTRANS ++S 4400,5500,4400,9400,200,1c,DOWN,PTRANS ++S 3200,5500,3200,9400,200,3a,DOWN,PTRANS ++S 5600,5500,5600,9400,200,4a,DOWN,PTRANS ++S 7000,7000,7000,7000,400,a,LEFT,CALU1 ++S 6000,7000,7000,7000,600,*,LEFT,ALU1 ++S 6000,5000,6000,7000,400,a,DOWN,CALU1 ++S 6000,4800,6000,7100,400,*,DOWN,ALU1 ++S 6200,7900,6200,9300,400,*,UP,ALU1 ++S 4000,7000,5000,7000,600,*,LEFT,ALU1 ++S 600,2300,600,2900,600,*,UP,NDIF ++S 1200,4900,2400,4900,600,*,RIGHT,POLY ++S 2400,1100,2400,1500,200,*,DOWN,POLY ++S 2400,1500,2400,3300,200,4b,UP,NTRANS ++S 2400,3300,2400,5500,200,*,UP,POLY ++S 2800,1700,2800,3100,600,n3,UP,NDIF ++S 3200,1500,3200,3300,200,5a,UP,NTRANS ++S 3200,3300,3200,5500,200,*,UP,POLY ++S 3800,1700,3800,3100,1000,*,UP,NDIF ++S 4400,1500,4400,3300,200,2c,UP,NTRANS ++S 4400,1100,4400,1500,200,*,DOWN,POLY ++S 4400,3300,4400,5500,200,*,DOWN,POLY ++S 5000,1700,5000,3100,1000,*,UP,NDIF ++S 5600,1500,5600,3300,200,6a,UP,NTRANS ++S 5000,2000,5000,3100,400,*,UP,ALU1 ++S 6800,1700,6800,2100,200,*,DOWN,POLY ++S 6800,2100,6800,3900,200,2a,UP,NTRANS ++S 7200,2300,7200,3700,400,*,UP,NDIF ++S 7400,3000,7400,3610,600,*,DOWN,NDIF ++S 7400,2700,7400,5900,400,*,UP,ALU1 ++S 6800,3900,6800,5500,200,*,DOWN,POLY ++S 5600,3300,5600,5500,200,*,UP,POLY ++S 6200,1700,6200,3700,600,*,UP,NDIF ++S 6200,700,6200,3100,400,*,DOWN,ALU1 ++S 6000,4900,6400,4900,600,*,LEFT,ALU1 ++S 3000,2000,5000,2000,400,*,RIGHT,ALU1 ++S 600,3100,3000,3100,400,*,LEFT,ALU1 ++S 3000,2000,3000,3100,400,*,UP,ALU1 ++S 600,2100,600,3100,400,*,DOWN,ALU1 ++S 1800,700,1800,2100,400,*,DOWN,ALU1 ++S 800,1700,800,3100,400,*,DOWN,NDIF ++S 1200,1500,1200,3300,200,3b,UP,NTRANS ++S 1200,1100,1200,1500,200,*,DOWN,POLY ++S 1800,1700,1800,3100,600,*,UP,NDIF ++S 1200,3300,1200,5500,200,*,UP,POLY ++S 4900,4800,4900,7100,600,*,DOWN,ALU1 ++V 7000,700,CONT_BODY_P,* ++V 5000,8000,CONT_DIF_P,n2 ++V 1800,4900,CONT_POLY,* ++V 3800,6000,CONT_DIF_P,* ++V 1800,8000,CONT_DIF_P,* ++V 600,7200,CONT_DIF_P,n2 ++V 600,8000,CONT_DIF_P,n2 ++V 6200,9000,CONT_DIF_P,* ++V 1800,9000,CONT_DIF_P,* ++V 7400,5800,CONT_DIF_P,an ++V 6200,8000,CONT_DIF_P,* ++V 4800,4900,CONT_POLY,* ++V 600,3000,CONT_DIF_N,n4 ++V 600,2200,CONT_DIF_N,n4 ++V 3800,3000,CONT_DIF_N,* ++V 5000,3000,CONT_DIF_N,n4 ++V 5000,2200,CONT_DIF_N,n4 ++V 5400,3900,CONT_POLY,an ++V 7400,3600,CONT_DIF_N,an ++V 7400,2800,CONT_DIF_N,an ++V 6200,3000,CONT_DIF_N,* ++V 6200,2000,CONT_DIF_N,* ++V 6400,4900,CONT_POLY,* ++V 1800,2000,CONT_DIF_N,* ++EOF +diff --git a/alliance/src/cells/src/msxlib/cgi2a_x1.vbe b/alliance/src/cells/src/msxlib/cgi2a_x1.vbe +new file mode 100644 +index 0000000..4c4a0aa +--- /dev/null ++++ b/alliance/src/cells/src/msxlib/cgi2a_x1.vbe +@@ -0,0 +1,38 @@ ++ENTITY cgi2a_x1 IS ++GENERIC ( ++ CONSTANT area : NATURAL := 8000; ++ CONSTANT cin_a : NATURAL := 7; ++ CONSTANT cin_b : NATURAL := 12; ++ CONSTANT cin_c : NATURAL := 6; ++ CONSTANT rdown_a_z : NATURAL := 2060; ++ CONSTANT rdown_b_z : NATURAL := 2060; ++ CONSTANT rdown_c_z : NATURAL := 2050; ++ CONSTANT rup_a_z : NATURAL := 3000; ++ CONSTANT rup_b_z : NATURAL := 2980; ++ CONSTANT rup_c_z : NATURAL := 3000; ++ CONSTANT tphl_c_z : NATURAL := 50; ++ CONSTANT tphl_b_z : NATURAL := 57; ++ CONSTANT tphh_a_z : NATURAL := 103; ++ CONSTANT tplh_c_z : NATURAL := 56; ++ CONSTANT tplh_b_z : NATURAL := 76; ++ CONSTANT tpll_a_z : NATURAL := 105; ++ CONSTANT transistors : NATURAL := 12 ++); ++PORT ( ++ a : in BIT; ++ b : in BIT; ++ c : in BIT; ++ z : out BIT; ++ vdd : in BIT; ++ vss : in BIT ++); ++END cgi2a_x1; ++ ++ARCHITECTURE behaviour_data_flow OF cgi2a_x1 IS ++ ++BEGIN ++ ASSERT ((vdd and not (vss)) = '1') ++ REPORT "power supply is missing on cgi2a_x1" ++ SEVERITY WARNING; ++ z <= not((not(a) or (b and c)) and (b or c)) after 1100 ps; ++END; +diff --git a/alliance/src/cells/src/msxlib/cgi2a_x2.ap b/alliance/src/cells/src/msxlib/cgi2a_x2.ap +new file mode 100644 +index 0000000..8992b3b +--- /dev/null ++++ b/alliance/src/cells/src/msxlib/cgi2a_x2.ap +@@ -0,0 +1,238 @@ ++V ALLIANCE : 6 ++H cgi2a_x2,P, 8/ 8/2014,100 ++A 0,0,15000,10000 ++R 14000,6000,ref_ref,a_60 ++R 14000,4000,ref_ref,a_40 ++R 14000,5000,ref_ref,a_50 ++R 13000,5000,ref_ref,a_50 ++R 1000,5000,ref_ref,b_50 ++R 1000,6000,ref_ref,b_60 ++R 1000,7000,ref_ref,b_70 ++R 2000,7000,ref_ref,b_70 ++R 3000,7000,ref_ref,b_70 ++R 4000,7000,ref_ref,b_70 ++R 5000,7000,ref_ref,b_70 ++R 6000,7000,ref_ref,b_70 ++R 7000,7000,ref_ref,b_70 ++R 8000,7000,ref_ref,b_70 ++R 9000,7000,ref_ref,b_70 ++R 9000,6000,ref_ref,b_60 ++R 9000,5000,ref_ref,b_50 ++R 8000,5000,ref_ref,b_50 ++R 7000,5000,ref_ref,b_50 ++R 6000,5000,ref_ref,b_50 ++R 2000,4000,ref_ref,c_40 ++R 3000,5000,ref_ref,c_50 ++R 2000,6000,ref_ref,c_60 ++R 2000,5000,ref_ref,c_50 ++R 7000,6000,ref_ref,z_60 ++R 6000,6000,ref_ref,z_60 ++R 5000,6000,ref_ref,z_60 ++R 4000,6000,ref_ref,z_60 ++R 3000,6000,ref_ref,z_60 ++R 4000,5000,ref_ref,z_50 ++R 4000,4000,ref_ref,z_40 ++R 4000,3000,ref_ref,z_30 ++R 3000,3000,ref_ref,z_30 ++R 5000,3000,ref_ref,z_30 ++R 6000,3000,ref_ref,z_30 ++R 7000,3000,ref_ref,z_30 ++S 13100,9300,13900,9300,600,*,RIGHT,NTIE ++S 11100,700,11900,700,600,*,RIGHT,PTIE ++S 13600,1900,13600,3400,200,4i,UP,NTRANS ++S 12400,1900,12400,3400,200,3i,UP,NTRANS ++S 11200,5100,11200,5700,200,*,DOWN,POLY ++S 10000,5100,10000,5700,200,*,DOWN,POLY ++S 13000,5000,14000,5000,600,*,LEFT,ALU1 ++S 10000,5100,11200,5100,200,*,LEFT,POLY ++S 12400,4900,13600,4900,600,*,LEFT,POLY ++S 11800,5700,11800,9200,600,*,DOWN,PDIF ++S 12400,8500,12400,8900,200,*,UP,POLY ++S 14300,5700,14300,8300,600,*,DOWN,PDIF ++S 13600,5500,13600,8500,200,2i,DOWN,PTRANS ++S 13000,5700,13000,8300,600,*,UP,PDIF ++S 12400,5500,12400,8500,200,1i,DOWN,PTRANS ++S 13600,1500,13600,1900,200,*,DOWN,POLY ++S 12400,1500,12400,1900,200,*,DOWN,POLY ++S 11800,700,11800,3100,400,*,DOWN,ALU1 ++S 9400,700,9400,3100,400,*,DOWN,ALU1 ++S 11600,6000,13000,6000,400,*,RIGHT,ALU1 ++S 11600,4000,11600,6000,400,*,DOWN,ALU1 ++S 14000,3900,14000,6100,400,*,UP,ALU1 ++S 13000,5000,13000,5000,400,a,LEFT,CALU1 ++S 14000,4000,14000,6000,400,a,DOWN,CALU1 ++S 12400,3400,12400,5700,200,*,DOWN,POLY ++S 13600,3400,13600,5700,200,*,DOWN,POLY ++S 14200,700,14200,3100,400,*,DOWN,ALU1 ++S 13000,2100,13000,3200,600,*,UP,NDIF ++S 14300,2100,14300,3200,600,*,UP,NDIF ++S 11700,2100,11700,3200,600,*,UP,NDIF ++S 4900,4000,13000,4000,400,*,RIGHT,ALU1 ++S 13000,6000,13000,7100,400,*,UP,ALU1 ++S 6000,5000,6000,5000,400,b,LEFT,CALU1 ++S 7000,5000,7000,5000,400,b,LEFT,CALU1 ++S 8000,5000,8000,5000,400,b,LEFT,CALU1 ++S 8000,7000,8000,7000,400,b,LEFT,CALU1 ++S 9000,5000,9000,7000,400,b,UP,CALU1 ++S 7000,7000,7000,7000,400,b,LEFT,CALU1 ++S 6000,7000,6000,7000,400,b,LEFT,CALU1 ++S 5000,7000,5000,7000,400,b,LEFT,CALU1 ++S 4000,7000,4000,7000,400,b,LEFT,CALU1 ++S 3000,7000,3000,7000,400,b,LEFT,CALU1 ++S 2000,7000,2000,7000,400,b,LEFT,CALU1 ++S 1000,5000,1000,7000,400,b,UP,CALU1 ++S 14200,6900,14200,9300,400,*,UP,ALU1 ++S 0,5000,15000,5000,10000,cgi2a_x2,LEFT,TALU8 ++S 0,2200,15000,2200,5200,*,LEFT,PWELL ++S 0,7600,15000,7600,5600,*,LEFT,NWELL ++S 0,600,15000,600,1200,vss,RIGHT,CALU1 ++S 0,9400,15000,9400,1200,vdd,RIGHT,CALU1 ++S 2400,1300,2400,1700,200,*,DOWN,POLY ++S 1000,7000,9000,7000,400,*,RIGHT,ALU1 ++S 1000,4900,1000,7000,400,*,UP,ALU1 ++S 2000,5000,3100,5000,400,*,LEFT,ALU1 ++S 2400,5000,3600,5000,600,*,RIGHT,POLY ++S 2000,3900,2000,6100,400,*,DOWN,ALU1 ++S 3000,5000,3000,5000,400,c,LEFT,CALU1 ++S 2000,4000,2000,6000,400,c,DOWN,CALU1 ++S 4000,3000,4000,6000,400,z,DOWN,CALU1 ++S 4000,3000,4000,6000,400,*,DOWN,ALU1 ++S 7000,3000,7000,3000,400,z,LEFT,CALU1 ++S 6000,3000,6000,3000,400,z,LEFT,CALU1 ++S 3000,3000,3000,3000,400,z,LEFT,CALU1 ++S 3000,6000,3000,6000,400,z,LEFT,CALU1 ++S 5000,3000,5000,3000,400,z,LEFT,CALU1 ++S 7000,6000,7000,6000,400,z,LEFT,CALU1 ++S 6000,6000,6000,6000,400,z,LEFT,CALU1 ++S 5000,6000,5000,6000,400,z,LEFT,CALU1 ++S 2900,6000,7500,6000,400,*,RIGHT,ALU1 ++S 5900,5000,9000,5000,400,*,RIGHT,ALU1 ++S 9000,5000,9000,7000,600,*,UP,ALU1 ++S 5400,800,5400,3700,600,*,UP,NDIF ++S 7400,1900,7400,3200,600,*,DOWN,NDIF ++S 3000,1900,3000,3200,600,*,DOWN,NDIF ++S 600,800,600,3700,600,*,UP,NDIF ++S 1800,1900,1800,3200,600,*,UP,NDIF ++S 1600,800,1600,3700,400,*,UP,NDIF ++S 4200,1900,4200,3200,600,*,UP,NDIF ++S 4400,800,4400,3700,400,*,DOWN,NDIF ++S 3000,5900,3000,9200,1000,*,UP,PDIF ++S 4800,5300,6200,5300,200,*,RIGHT,POLY ++S 8800,3400,8800,5700,200,*,DOWN,POLY ++S 8000,3400,8000,5700,200,*,DOWN,POLY ++S 6800,3400,6800,5700,200,*,DOWN,POLY ++S 6000,3400,6000,5700,200,*,DOWN,POLY ++S 1200,3900,1200,5700,200,*,DOWN,POLY ++S 3600,3400,3600,5700,200,*,DOWN,POLY ++S 2400,3400,2400,5700,200,*,DOWN,POLY ++S 5000,4000,5000,4600,600,*,DOWN,ALU1 ++S 1800,5900,1800,9200,600,*,DOWN,PDIF ++S 4200,5900,4200,9200,600,*,UP,PDIF ++S 5400,5900,5400,9200,600,*,UP,PDIF ++S 7400,5900,7400,9200,600,*,UP,PDIF ++S 9400,5900,9400,9200,600,*,UP,PDIF ++S 10600,5900,10600,9200,600,*,UP,PDIF ++S 600,5900,600,9200,600,*,DOWN,PDIF ++S 600,7900,600,9300,400,*,UP,ALU1 ++S 1700,8000,10600,8000,400,*,RIGHT,ALU1 ++S 10600,6900,10600,8000,400,*,DOWN,ALU1 ++S 11800,6900,11800,9300,400,*,UP,ALU1 ++S 600,700,600,3100,400,*,DOWN,ALU1 ++S 1800,2000,4300,2000,400,*,RIGHT,ALU1 ++S 1800,2000,1800,3100,400,*,DOWN,ALU1 ++S 5400,700,5400,2100,400,*,DOWN,ALU1 ++S 2900,3000,7400,3000,400,*,RIGHT,ALU1 ++S 7400,1900,7400,3000,400,*,DOWN,ALU1 ++S 9500,1900,9500,3200,600,*,UP,NDIF ++S 9400,1900,9400,3200,600,*,UP,NDIF ++S 8800,1300,8800,1700,200,*,DOWN,POLY ++S 8000,1300,8000,1700,200,*,DOWN,POLY ++S 6800,1300,6800,1700,200,*,DOWN,POLY ++S 6000,1300,6000,1700,200,*,DOWN,POLY ++S 4800,300,4800,600,200,*,DOWN,POLY ++S 3600,1300,3600,1700,200,*,DOWN,POLY ++S 1200,300,1200,600,200,*,DOWN,POLY ++S 1200,9400,1200,9700,200,*,DOWN,POLY ++S 2400,9400,2400,9700,200,*,DOWN,POLY ++S 3600,9400,3600,9700,200,*,DOWN,POLY ++S 4800,9400,4800,9700,200,*,DOWN,POLY ++S 6000,9400,6000,9700,200,*,DOWN,POLY ++S 6800,9400,6800,9700,200,*,DOWN,POLY ++S 8000,9400,8000,9700,200,*,DOWN,POLY ++S 8800,9400,8800,9700,200,*,DOWN,POLY ++S 10000,9400,10000,9700,200,*,DOWN,POLY ++S 11200,9400,11200,9700,200,*,DOWN,POLY ++S 2400,5700,2400,9400,200,1c,DOWN,PTRANS ++S 3600,5700,3600,9400,200,2c,DOWN,PTRANS ++S 2400,1700,2400,3400,200,3c,UP,NTRANS ++S 3600,1700,3600,3400,200,4c,UP,NTRANS ++S 1200,5700,1200,9400,200,1a,DOWN,PTRANS ++S 4800,5700,4800,9400,200,2a,DOWN,PTRANS ++S 6000,5700,6000,9400,200,3a,DOWN,PTRANS ++S 8800,5700,8800,9400,200,4a,DOWN,PTRANS ++S 1200,600,1200,3900,200,5a,UP,NTRANS ++S 6000,1700,6000,3400,200,7a,UP,NTRANS ++S 8800,1700,8800,3400,200,8a,UP,NTRANS ++S 11200,5700,11200,9400,200,1b,DOWN,PTRANS ++S 10000,5700,10000,9400,200,2b,DOWN,PTRANS ++S 6800,4000,8000,4000,600,*,RIGHT,POLY ++S 6800,5700,6800,9400,200,3b,DOWN,PTRANS ++S 8000,5700,8000,9400,200,4b,DOWN,PTRANS ++S 4800,600,4800,3900,200,5b,UP,NTRANS ++S 6800,1700,6800,3400,200,7b,UP,NTRANS ++S 8000,1700,8000,3400,200,8b,UP,NTRANS ++S 8400,5900,8400,9200,400,n1a,UP,PDIF ++S 6400,5900,6400,9200,400,n1b,UP,PDIF ++S 8400,1900,8400,3200,400,n3a,UP,NDIF ++S 6400,1900,6400,3200,400,n3b,UP,NDIF ++S 13600,8500,13600,8800,200,*,UP,POLY ++S 13000,2200,13000,4000,400,*,UP,ALU1 ++V 14000,9300,CONT_BODY_N,* ++V 13000,9300,CONT_BODY_N,* ++V 12000,700,CONT_BODY_P,* ++V 11000,700,CONT_BODY_P,* ++V 13000,6100,CONT_DIF_P,an ++V 13300,4900,CONT_POLY,* ++V 13000,2300,CONT_DIF_N,an ++V 13000,3100,CONT_DIF_N,an ++V 13000,7000,CONT_DIF_P,an ++V 11600,4900,CONT_POLY,an ++V 7400,4000,CONT_POLY,an ++V 5000,4500,CONT_POLY,an ++V 11800,3000,CONT_DIF_N,* ++V 9400,3000,CONT_DIF_N,* ++V 14200,3000,CONT_DIF_N,* ++V 11800,2200,CONT_DIF_N,* ++V 14200,2200,CONT_DIF_N,* ++V 14200,8000,CONT_DIF_P,* ++V 14200,7000,CONT_DIF_P,* ++V 1000,5000,CONT_POLY,* ++V 3000,5000,CONT_POLY,* ++V 600,9000,CONT_DIF_P,* ++V 600,1000,CONT_DIF_N,* ++V 5400,1000,CONT_DIF_N,* ++V 3000,3000,CONT_DIF_N,* ++V 4200,2000,CONT_DIF_N,n4 ++V 1800,8000,CONT_DIF_P,n2 ++V 5400,9000,CONT_DIF_P,* ++V 4200,8000,CONT_DIF_P,n2 ++V 7400,6000,CONT_DIF_P,* ++V 11800,8000,CONT_DIF_P,* ++V 11800,9000,CONT_DIF_P,* ++V 3000,6000,CONT_DIF_P,* ++V 6000,5000,CONT_POLY,* ++V 9000,5000,CONT_POLY,* ++V 600,8000,CONT_DIF_P,* ++V 10600,7000,CONT_DIF_P,n2 ++V 10600,7800,CONT_DIF_P,n2 ++V 11800,7000,CONT_DIF_P,* ++V 600,2000,CONT_DIF_N,* ++V 600,3000,CONT_DIF_N,* ++V 1800,3000,CONT_DIF_N,n4 ++V 1800,2200,CONT_DIF_N,n4 ++V 5400,2000,CONT_DIF_N,* ++V 7400,2000,CONT_DIF_N,* ++V 7400,2800,CONT_DIF_N,* ++V 9400,2000,CONT_DIF_N,* ++V 9400,9000,CONT_DIF_P,* ++EOF +diff --git a/alliance/src/cells/src/msxlib/cgi2a_x2.vbe b/alliance/src/cells/src/msxlib/cgi2a_x2.vbe +new file mode 100644 +index 0000000..61ab612 +--- /dev/null ++++ b/alliance/src/cells/src/msxlib/cgi2a_x2.vbe +@@ -0,0 +1,38 @@ ++ENTITY cgi2a_x2 IS ++GENERIC ( ++ CONSTANT area : NATURAL := 15000; ++ CONSTANT cin_a : NATURAL := 11; ++ CONSTANT cin_b : NATURAL := 24; ++ CONSTANT cin_c : NATURAL := 11; ++ CONSTANT rdown_a_z : NATURAL := 1100; ++ CONSTANT rdown_b_z : NATURAL := 1090; ++ CONSTANT rdown_c_z : NATURAL := 1100; ++ CONSTANT rup_a_z : NATURAL := 1580; ++ CONSTANT rup_b_z : NATURAL := 1570; ++ CONSTANT rup_c_z : NATURAL := 1580; ++ CONSTANT tphl_c_z : NATURAL := 51; ++ CONSTANT tphl_b_z : NATURAL := 58; ++ CONSTANT tphh_a_z : NATURAL := 103; ++ CONSTANT tplh_c_z : NATURAL := 56; ++ CONSTANT tplh_b_z : NATURAL := 77; ++ CONSTANT tpll_a_z : NATURAL := 110; ++ CONSTANT transistors : NATURAL := 22 ++); ++PORT ( ++ a : in BIT; ++ b : in BIT; ++ c : in BIT; ++ z : out BIT; ++ vdd : in BIT; ++ vss : in BIT ++); ++END cgi2a_x2; ++ ++ARCHITECTURE behaviour_data_flow OF cgi2a_x2 IS ++ ++BEGIN ++ ASSERT ((vdd and not (vss)) = '1') ++ REPORT "power supply is missing on cgi2a_x2" ++ SEVERITY WARNING; ++ z <= not((not(a) or (b and c)) and (b or c)) after 1100 ps; ++END; +diff --git a/alliance/src/cells/src/msxlib/cgn2_x1.ap b/alliance/src/cells/src/msxlib/cgn2_x1.ap +new file mode 100644 +index 0000000..f8ecadf +--- /dev/null ++++ b/alliance/src/cells/src/msxlib/cgn2_x1.ap +@@ -0,0 +1,136 @@ ++V ALLIANCE : 6 ++H cgn2_x1,P, 8/ 8/2014,100 ++A 0,0,8000,10000 ++R 7000,7000,ref_ref,c_70 ++R 7000,8000,ref_ref,c_80 ++R 4000,5000,ref_ref,b_50 ++R 1000,6000,ref_ref,a_60 ++R 1000,5000,ref_ref,a_50 ++R 1000,4000,ref_ref,a_40 ++R 2000,5000,ref_ref,a_50 ++R 4000,4000,ref_ref,b_40 ++R 5000,6000,ref_ref,c_60 ++R 5000,7000,ref_ref,c_70 ++R 6000,7000,ref_ref,c_70 ++R 7000,4000,ref_ref,z_40 ++R 7000,5000,ref_ref,z_50 ++R 7000,6000,ref_ref,z_60 ++R 7000,3000,ref_ref,z_30 ++R 4000,6000,ref_ref,b_60 ++R 6000,6000,ref_ref,z_60 ++R 5000,5000,ref_ref,b_50 ++S 2800,700,3600,700,600,*,RIGHT,PTIE ++S 7100,7000,7100,8100,400,*,UP,ALU1 ++S 7000,7000,7000,8100,400,*,UP,ALU1 ++S 6200,7900,6200,9300,400,*,UP,ALU1 ++S 5000,7000,7000,7000,400,*,LEFT,ALU1 ++S 7000,7000,7000,8000,400,c,DOWN,CALU1 ++S 6800,7700,6800,8100,200,*,DOWN,POLY ++S 6200,5900,6200,9100,600,*,DOWN,PDIF ++S 7000,3000,7000,6000,400,z,DOWN,CALU1 ++S 5900,6000,7500,6000,400,*,LEFT,ALU1 ++S 6800,5700,6800,7700,200,1z,DOWN,PTRANS ++S 7200,5900,7200,7500,400,*,UP,PDIF ++S 2400,6700,2400,9300,200,2a,DOWN,PTRANS ++S 1200,6700,1200,9300,200,1a,DOWN,PTRANS ++S 5600,6700,5600,9300,200,2b,DOWN,PTRANS ++S 3200,6700,3200,9300,200,1b,DOWN,PTRANS ++S 4400,6700,4400,9300,200,1c,DOWN,PTRANS ++S 500,1900,4900,1900,400,*,RIGHT,ALU1 ++S 1000,3900,1000,6100,400,*,DOWN,ALU1 ++S 1000,4000,1000,6000,400,a,DOWN,CALU1 ++S 0,9400,8000,9400,1200,vdd,RIGHT,CALU1 ++S 0,5000,8000,5000,10000,cgn2_x1,LEFT,TALU8 ++S 0,2200,8000,2200,5200,*,LEFT,PWELL ++S 0,7600,8000,7600,5600,*,LEFT,NWELL ++S 0,600,8000,600,1200,vss,RIGHT,CALU1 ++S 1200,5000,2400,5000,600,*,RIGHT,POLY ++S 1000,5000,2000,5000,600,*,LEFT,ALU1 ++S 3600,5000,4000,5000,600,*,LEFT,ALU1 ++S 4000,4000,4000,6000,400,b,UP,CALU1 ++S 3800,6900,3800,9100,1000,*,UP,PDIF ++S 5000,6900,5000,9100,1000,*,UP,PDIF ++S 2800,7000,3900,7000,400,*,RIGHT,ALU1 ++S 2800,3000,2800,7000,400,*,UP,ALU1 ++S 5600,9300,5600,9700,200,*,DOWN,POLY ++S 4400,9300,4400,9700,200,*,DOWN,POLY ++S 3200,9300,3200,9700,200,*,DOWN,POLY ++S 2400,9300,2400,9700,200,*,DOWN,POLY ++S 2800,6900,2800,9100,600,n1,DOWN,PDIF ++S 1800,6900,1800,9100,1000,*,UP,PDIF ++S 800,6900,800,9100,400,*,UP,PDIF ++S 1200,9300,1200,9700,200,*,DOWN,POLY ++S 4400,3800,4400,6700,200,*,UP,POLY ++S 3200,4800,3200,6700,200,*,UP,POLY ++S 2400,4800,2400,6700,200,*,UP,POLY ++S 5000,6000,5000,7000,400,c,DOWN,CALU1 ++S 4900,5900,4900,7000,600,*,UP,ALU1 ++S 4000,5000,5300,5000,600,*,RIGHT,ALU1 ++S 5600,4800,5600,6700,200,*,UP,POLY ++S 4000,3900,4000,6100,400,*,UP,ALU1 ++S 600,6900,600,8000,400,*,UP,ALU1 ++S 600,8000,5100,8000,400,*,RIGHT,ALU1 ++S 600,7100,600,7700,600,*,UP,PDIF ++S 2800,3000,5000,3000,400,*,RIGHT,ALU1 ++S 5000,4000,6200,4000,600,*,RIGHT,ALU1 ++S 5000,3000,5000,4100,400,*,UP,ALU1 ++S 7000,3000,7200,3000,600,*,LEFT,ALU1 ++S 7000,2500,7000,3100,400,*,UP,NDIF ++S 6600,2300,6600,3300,200,2z,UP,NTRANS ++S 6800,4100,6800,6700,200,*,DOWN,POLY ++S 6600,3300,6600,4200,200,*,UP,POLY ++S 7000,3000,7000,6000,400,*,DOWN,ALU1 ++S 6000,700,6000,3100,400,*,DOWN,ALU1 ++S 6600,1900,6600,2300,200,*,UP,POLY ++S 6000,2100,6000,3100,600,*,UP,NDIF ++S 5400,1500,5400,1900,200,*,DOWN,POLY ++S 5400,1900,5400,3100,200,4b,UP,NTRANS ++S 4200,1500,4200,1900,200,*,DOWN,POLY ++S 4200,1900,4200,3100,200,2c,UP,NTRANS ++S 3000,1500,3000,1900,200,*,DOWN,POLY ++S 3000,1900,3000,3100,200,3b,UP,NTRANS ++S 2200,1500,2200,1900,200,*,DOWN,POLY ++S 2200,1900,2200,3100,200,4a,UP,NTRANS ++S 3600,2100,3600,2900,600,*,UP,NDIF ++S 2600,2100,2600,2900,600,n3,UP,NDIF ++S 4800,2100,4800,2900,600,*,UP,NDIF ++S 4800,1900,4800,2200,600,*,UP,ALU1 ++S 3600,2800,3600,3000,600,*,DOWN,ALU1 ++S 1200,1900,1200,3100,200,3a,UP,NTRANS ++S 800,2100,800,2900,400,*,DOWN,NDIF ++S 600,1900,600,2200,600,*,UP,ALU1 ++S 1700,900,1700,2900,400,*,UP,NDIF ++S 1200,1600,1200,1900,200,*,DOWN,POLY ++S 1200,3100,1200,6700,200,*,UP,POLY ++S 2200,3100,2200,4700,200,*,UP,POLY ++S 3000,3100,3000,5200,200,*,UP,POLY ++S 4200,3100,4200,3900,200,*,UP,POLY ++S 5400,3100,5400,4700,200,*,UP,POLY ++S 2000,5000,2000,5000,400,a,LEFT,CALU1 ++S 5000,5000,5000,5000,400,b,LEFT,CALU1 ++S 6000,6000,6000,6000,400,z,LEFT,CALU1 ++S 6000,7000,6000,7000,400,c,LEFT,CALU1 ++V 3800,700,CONT_BODY_P,* ++V 2800,700,CONT_BODY_P,* ++V 7300,9300,CONT_BODY_N,* ++V 6200,8000,CONT_DIF_P,* ++V 7400,6000,CONT_DIF_P,* ++V 1800,9000,CONT_DIF_P,* ++V 5000,8000,CONT_DIF_P,n2 ++V 6200,9000,CONT_DIF_P,* ++V 2000,5000,CONT_POLY,* ++V 3600,5000,CONT_POLY,* ++V 3800,7000,CONT_DIF_P,zn ++V 4800,6000,CONT_POLY,* ++V 5200,5000,CONT_POLY,* ++V 600,7000,CONT_DIF_P,n2 ++V 600,7800,CONT_DIF_P,n2 ++V 6200,4000,CONT_POLY,zn ++V 6000,3000,CONT_DIF_N,* ++V 7200,3000,CONT_DIF_N,* ++V 6000,2200,CONT_DIF_N,* ++V 4800,2200,CONT_DIF_N,n4 ++V 3600,2800,CONT_DIF_N,zn ++V 600,2200,CONT_DIF_N,n4 ++V 1600,1000,CONT_DIF_N,* ++EOF +diff --git a/alliance/src/cells/src/msxlib/cgn2_x1.vbe b/alliance/src/cells/src/msxlib/cgn2_x1.vbe +new file mode 100644 +index 0000000..b86bf48 +--- /dev/null ++++ b/alliance/src/cells/src/msxlib/cgn2_x1.vbe +@@ -0,0 +1,38 @@ ++ENTITY cgn2_x1 IS ++GENERIC ( ++ CONSTANT area : NATURAL := 8000; ++ CONSTANT cin_a : NATURAL := 8; ++ CONSTANT cin_b : NATURAL := 9; ++ CONSTANT cin_c : NATURAL := 5; ++ CONSTANT rdown_a_z : NATURAL := 2320; ++ CONSTANT rdown_b_z : NATURAL := 2330; ++ CONSTANT rdown_c_z : NATURAL := 2340; ++ CONSTANT rup_a_z : NATURAL := 2980; ++ CONSTANT rup_b_z : NATURAL := 2970; ++ CONSTANT rup_c_z : NATURAL := 2970; ++ CONSTANT tphh_c_z : NATURAL := 95; ++ CONSTANT tpll_c_z : NATURAL := 118; ++ CONSTANT tpll_a_z : NATURAL := 134; ++ CONSTANT tphh_b_z : NATURAL := 104; ++ CONSTANT tpll_b_z : NATURAL := 132; ++ CONSTANT tphh_a_z : NATURAL := 102; ++ CONSTANT transistors : NATURAL := 12 ++); ++PORT ( ++ a : in BIT; ++ b : in BIT; ++ c : in BIT; ++ z : out BIT; ++ vdd : in BIT; ++ vss : in BIT ++); ++END cgn2_x1; ++ ++ARCHITECTURE behaviour_data_flow OF cgn2_x1 IS ++ ++BEGIN ++ ASSERT ((vdd and not (vss)) = '1') ++ REPORT "power supply is missing on cgn2_x1" ++ SEVERITY WARNING; ++ z <= ((b and (a or c)) or (a and c)) after 1200 ps; ++END; +diff --git a/alliance/src/cells/src/msxlib/cgn2_x2.ap b/alliance/src/cells/src/msxlib/cgn2_x2.ap +new file mode 100644 +index 0000000..c708cbc +--- /dev/null ++++ b/alliance/src/cells/src/msxlib/cgn2_x2.ap +@@ -0,0 +1,137 @@ ++V ALLIANCE : 6 ++H cgn2_x2,P, 8/ 8/2014,100 ++A 0,0,8000,10000 ++R 4000,5000,ref_ref,b_50 ++R 1000,6000,ref_ref,a_60 ++R 1000,5000,ref_ref,a_50 ++R 1000,4000,ref_ref,a_40 ++R 2000,5000,ref_ref,a_50 ++R 4000,4000,ref_ref,b_40 ++R 5000,5000,ref_ref,c_50 ++R 5000,6000,ref_ref,c_60 ++R 5000,7000,ref_ref,c_70 ++R 6000,7000,ref_ref,c_70 ++R 5000,4000,ref_ref,b_40 ++R 7000,4000,ref_ref,z_40 ++R 7000,5000,ref_ref,z_50 ++R 7000,6000,ref_ref,z_60 ++R 7000,3000,ref_ref,z_30 ++R 4000,6000,ref_ref,b_60 ++R 7000,7000,ref_ref,z_70 ++R 7000,2000,ref_ref,z_20 ++R 6000,5000,ref_ref,z_50 ++S 2800,700,3600,700,600,*,RIGHT,PTIE ++S 6800,5600,6800,9400,200,1z,DOWN,PTRANS ++S 4400,5600,4400,9400,200,1c,DOWN,PTRANS ++S 5600,5600,5600,9400,200,2b,DOWN,PTRANS ++S 3200,5600,3200,9400,200,1b,DOWN,PTRANS ++S 1200,5600,1200,9400,200,2a,DOWN,PTRANS ++S 2400,5600,2400,9400,200,1a,DOWN,PTRANS ++S 1000,3900,1000,6100,400,*,DOWN,ALU1 ++S 1000,4000,1000,6000,400,a,DOWN,CALU1 ++S 5000,7000,6100,7000,400,*,LEFT,ALU1 ++S 5000,5000,5000,7000,400,c,DOWN,CALU1 ++S 3200,9400,3200,9700,200,*,DOWN,POLY ++S 4400,9400,4400,9700,200,*,DOWN,POLY ++S 5600,9400,5600,9700,200,*,DOWN,POLY ++S 1200,9400,1200,9700,200,*,DOWN,POLY ++S 2400,9400,2400,9700,200,*,DOWN,POLY ++S 6200,7900,6200,9300,400,*,UP,ALU1 ++S 0,9400,8000,9400,1200,vdd,RIGHT,CALU1 ++S 0,5000,8000,5000,10000,cgn2_x2,LEFT,TALU8 ++S 0,2200,8000,2200,5200,*,LEFT,PWELL ++S 0,7600,8000,7600,5600,*,LEFT,NWELL ++S 0,600,8000,600,1200,vss,RIGHT,CALU1 ++S 1000,5000,2000,5000,600,*,LEFT,ALU1 ++S 3600,5000,4000,5000,600,*,LEFT,ALU1 ++S 4900,4900,4900,7000,600,*,UP,ALU1 ++S 4000,4000,4000,6000,400,b,UP,CALU1 ++S 4000,4000,4000,6100,400,*,UP,ALU1 ++S 2800,3000,6200,3000,400,*,RIGHT,ALU1 ++S 6000,700,6000,2100,400,*,DOWN,ALU1 ++S 600,2000,4900,2000,400,*,RIGHT,ALU1 ++S 7000,7100,7500,7100,400,*,LEFT,ALU1 ++S 4000,4000,5300,4000,600,*,RIGHT,ALU1 ++S 800,5800,800,9200,400,*,UP,PDIF ++S 1800,5800,1800,9200,1000,*,UP,PDIF ++S 3800,5800,3800,9200,1000,*,UP,PDIF ++S 2800,5800,2800,9200,600,n1,DOWN,PDIF ++S 5000,5800,5000,9200,1000,*,UP,PDIF ++S 6200,5800,6200,9200,600,*,DOWN,PDIF ++S 7200,5800,7200,9200,400,*,UP,PDIF ++S 6800,9400,6800,9700,200,*,DOWN,POLY ++S 2800,7000,3900,7000,400,*,RIGHT,ALU1 ++S 2800,3000,2800,7000,400,*,UP,ALU1 ++S 600,7100,600,7700,600,*,UP,PDIF ++S 600,6900,600,8000,400,*,UP,ALU1 ++S 600,8000,5100,8000,400,*,RIGHT,ALU1 ++S 1200,5000,2200,5000,600,*,RIGHT,POLY ++S 2400,5100,2400,5600,200,*,UP,POLY ++S 3200,4800,3200,5600,200,*,UP,POLY ++S 4400,3800,4400,5600,200,*,UP,POLY ++S 5600,4100,5600,5600,200,*,UP,POLY ++S 7000,2000,7200,2000,600,*,LEFT,ALU1 ++S 7000,2000,7000,7100,400,*,DOWN,ALU1 ++S 7000,2000,7000,7000,400,z,DOWN,CALU1 ++S 6200,3000,6200,3400,400,*,UP,ALU1 ++S 6800,3400,6800,5600,200,*,DOWN,POLY ++S 2200,1600,2200,3300,200,3a,UP,NTRANS ++S 1200,1600,1200,3300,200,4a,UP,NTRANS ++S 800,1800,800,3100,400,*,DOWN,NDIF ++S 2600,1800,2600,3100,600,n3,UP,NDIF ++S 3600,1800,3600,3100,1000,*,UP,NDIF ++S 4200,1600,4200,3300,200,2c,UP,NTRANS ++S 3000,1600,3000,3300,200,3b,UP,NTRANS ++S 4600,1800,4600,3100,400,*,UP,NDIF ++S 600,2000,600,3100,400,*,DOWN,ALU1 ++S 600,2300,600,2900,600,*,UP,NDIF ++S 1200,3300,1200,5500,200,*,UP,POLY ++S 2200,3300,2200,4700,200,*,UP,POLY ++S 3000,3300,3000,4900,200,*,UP,POLY ++S 4200,3300,4200,3900,200,*,UP,POLY ++S 1200,1200,1200,1600,200,*,DOWN,POLY ++S 2200,1200,2200,1600,200,*,DOWN,POLY ++S 3000,1200,3000,1600,200,*,DOWN,POLY ++S 4200,1200,4200,1600,200,*,DOWN,POLY ++S 1700,500,1700,3100,400,*,UP,NDIF ++S 2000,5000,2000,5000,400,a,LEFT,CALU1 ++S 5000,4000,5000,4000,400,b,LEFT,CALU1 ++S 6000,7000,6000,7000,400,c,LEFT,CALU1 ++S 6000,5000,6000,5000,400,z,LEFT,CALU1 ++S 5900,5000,7000,5000,400,*,LEFT,ALU1 ++S 7000,6300,7500,6300,400,*,LEFT,ALU1 ++S 7400,6200,7400,7000,600,*,UP,PDIF ++S 6600,300,6600,700,200,*,UP,POLY ++S 6600,700,6600,2600,200,2z,UP,NTRANS ++S 7000,900,7000,2400,400,*,UP,NDIF ++S 6000,900,6000,2400,600,*,UP,NDIF ++S 5400,500,5400,900,200,*,DOWN,POLY ++S 5400,900,5400,2600,200,4b,UP,NTRANS ++S 5000,1100,5000,2400,400,*,UP,NDIF ++S 5400,2600,5400,3800,200,*,UP,POLY ++S 6600,2600,6600,3500,200,*,UP,POLY ++V 3800,700,CONT_BODY_P,* ++V 2800,700,CONT_BODY_P,* ++V 1800,9000,CONT_DIF_P,* ++V 5000,8000,CONT_DIF_P,n2 ++V 6200,8000,CONT_DIF_P,* ++V 6200,9000,CONT_DIF_P,* ++V 2000,5000,CONT_POLY,* ++V 3600,5000,CONT_POLY,* ++V 4800,5000,CONT_POLY,* ++V 4800,2000,CONT_DIF_N,n4 ++V 5200,4000,CONT_POLY,* ++V 6000,2000,CONT_DIF_N,* ++V 7400,7100,CONT_DIF_P,* ++V 3600,3000,CONT_DIF_N,zn ++V 3800,7000,CONT_DIF_P,zn ++V 600,7000,CONT_DIF_P,n2 ++V 600,7800,CONT_DIF_P,n2 ++V 6200,3300,CONT_POLY,zn ++V 7200,2000,CONT_DIF_N,* ++V 600,3000,CONT_DIF_N,n4 ++V 600,2200,CONT_DIF_N,n4 ++V 1600,600,CONT_DIF_N,* ++V 7400,6300,CONT_DIF_P,* ++V 6000,1000,CONT_DIF_N,* ++EOF +diff --git a/alliance/src/cells/src/msxlib/cgn2_x2.vbe b/alliance/src/cells/src/msxlib/cgn2_x2.vbe +new file mode 100644 +index 0000000..1812601 +--- /dev/null ++++ b/alliance/src/cells/src/msxlib/cgn2_x2.vbe +@@ -0,0 +1,38 @@ ++ENTITY cgn2_x2 IS ++GENERIC ( ++ CONSTANT area : NATURAL := 8000; ++ CONSTANT cin_a : NATURAL := 12; ++ CONSTANT cin_b : NATURAL := 12; ++ CONSTANT cin_c : NATURAL := 7; ++ CONSTANT rdown_a_z : NATURAL := 1220; ++ CONSTANT rdown_b_z : NATURAL := 1230; ++ CONSTANT rdown_c_z : NATURAL := 1230; ++ CONSTANT rup_a_z : NATURAL := 1560; ++ CONSTANT rup_b_z : NATURAL := 1560; ++ CONSTANT rup_c_z : NATURAL := 1560; ++ CONSTANT tphh_c_z : NATURAL := 98; ++ CONSTANT tpll_c_z : NATURAL := 120; ++ CONSTANT tpll_a_z : NATURAL := 135; ++ CONSTANT tphh_b_z : NATURAL := 106; ++ CONSTANT tpll_b_z : NATURAL := 133; ++ CONSTANT tphh_a_z : NATURAL := 105; ++ CONSTANT transistors : NATURAL := 12 ++); ++PORT ( ++ a : in BIT; ++ b : in BIT; ++ c : in BIT; ++ z : out BIT; ++ vdd : in BIT; ++ vss : in BIT ++); ++END cgn2_x2; ++ ++ARCHITECTURE behaviour_data_flow OF cgn2_x2 IS ++ ++BEGIN ++ ASSERT ((vdd and not (vss)) = '1') ++ REPORT "power supply is missing on cgn2_x2" ++ SEVERITY WARNING; ++ z <= ((b and (a or c)) or (a and c)) after 1200 ps; ++END; +diff --git a/alliance/src/cells/src/msxlib/cgn2_x3.ap b/alliance/src/cells/src/msxlib/cgn2_x3.ap +new file mode 100644 +index 0000000..684e15a +--- /dev/null ++++ b/alliance/src/cells/src/msxlib/cgn2_x3.ap +@@ -0,0 +1,226 @@ ++V ALLIANCE : 6 ++H cgn2_x3,P, 8/ 8/2014,100 ++A 0,0,15000,10000 ++R 13000,7000,ref_ref,z_70 ++R 13000,6000,ref_ref,z_60 ++R 14000,5000,ref_ref,z_50 ++R 13000,5000,ref_ref,z_50 ++R 13000,3000,ref_ref,z_30 ++R 13000,4000,ref_ref,z_40 ++R 10000,6000,ref_ref,b_60 ++R 2000,4000,ref_ref,c_40 ++R 3000,5000,ref_ref,c_50 ++R 2000,6000,ref_ref,c_60 ++R 2000,5000,ref_ref,c_50 ++R 10000,4000,ref_ref,b_40 ++R 10000,5000,ref_ref,b_50 ++R 1000,5000,ref_ref,a_50 ++R 6000,5000,ref_ref,a_50 ++R 9000,5000,ref_ref,a_50 ++R 9000,7000,ref_ref,a_70 ++R 7000,5000,ref_ref,a_50 ++R 8000,5000,ref_ref,a_50 ++R 8000,7000,ref_ref,a_70 ++R 7000,7000,ref_ref,a_70 ++R 6000,7000,ref_ref,a_70 ++R 5000,7000,ref_ref,a_70 ++R 4000,7000,ref_ref,a_70 ++R 3000,7000,ref_ref,a_70 ++R 2000,7000,ref_ref,a_70 ++R 1000,7000,ref_ref,a_70 ++R 1000,6000,ref_ref,a_60 ++R 9000,6000,ref_ref,a_60 ++R 5000,4000,ref_ref,b_40 ++R 9000,4000,ref_ref,b_40 ++R 8000,4000,ref_ref,b_40 ++R 7000,4000,ref_ref,b_40 ++R 6000,4000,ref_ref,b_40 ++S 1100,9300,1900,9300,600,*,RIGHT,NTIE ++S 1100,700,1900,700,600,*,RIGHT,PTIE ++S 9400,700,9400,2200,400,*,DOWN,ALU1 ++S 6000,3000,6000,5700,200,*,DOWN,POLY ++S 6800,3000,6800,5700,200,*,DOWN,POLY ++S 8000,3000,8000,5700,200,*,DOWN,POLY ++S 8800,3000,8800,5700,200,*,DOWN,POLY ++S 9500,2000,9500,2800,600,*,UP,NDIF ++S 7400,2500,7400,3000,400,*,DOWN,ALU1 ++S 7400,2000,7400,2800,600,*,DOWN,NDIF ++S 8000,1800,8000,3000,200,8b,UP,NTRANS ++S 8800,1800,8800,3000,200,8a,UP,NTRANS ++S 8400,2000,8400,2800,400,n3a,UP,NDIF ++S 6800,1800,6800,3000,200,7b,UP,NTRANS ++S 6000,1800,6000,3000,200,7a,UP,NTRANS ++S 6400,2000,6400,2800,400,n3b,UP,NDIF ++S 3000,2700,3000,3000,600,*,UP,ALU1 ++S 4200,2000,4200,2800,600,*,DOWN,NDIF ++S 1800,2000,1800,2800,600,*,DOWN,NDIF ++S 5400,700,5400,2200,400,*,DOWN,ALU1 ++S 5400,2000,5400,3700,600,*,UP,NDIF ++S 4800,1800,4800,3900,200,5b,UP,NTRANS ++S 4400,2000,4400,3700,400,*,DOWN,NDIF ++S 3600,3000,3600,5700,200,*,DOWN,POLY ++S 2400,3000,2400,5700,200,*,DOWN,POLY ++S 1200,3900,1200,5700,200,*,DOWN,POLY ++S 600,2000,600,3700,600,*,UP,NDIF ++S 1800,1900,1800,2100,600,*,DOWN,ALU1 ++S 1700,1900,4300,1900,400,*,RIGHT,ALU1 ++S 1200,1800,1200,3900,200,5a,UP,NTRANS ++S 1600,2000,1600,3700,400,*,UP,NDIF ++S 4200,1900,4200,2100,600,*,DOWN,ALU1 ++S 3600,1800,3600,3000,200,4c,UP,NTRANS ++S 2400,1800,2400,3000,200,3c,UP,NTRANS ++S 3000,2000,3000,2800,600,*,DOWN,NDIF ++S 2900,3000,11000,3000,400,*,RIGHT,ALU1 ++S 11700,2400,11700,3500,600,*,UP,NDIF ++S 14300,2400,14300,3500,600,*,UP,NDIF ++S 14200,700,14200,3500,400,*,DOWN,ALU1 ++S 11800,700,11800,3500,400,*,DOWN,ALU1 ++S 13600,2200,13600,3700,200,4z,UP,NTRANS ++S 12400,2200,12400,3700,200,3z,UP,NTRANS ++S 13000,2400,13000,3500,600,*,UP,NDIF ++S 14300,5700,14300,8100,600,*,DOWN,PDIF ++S 11800,5700,11800,8100,600,*,DOWN,PDIF ++S 13100,5700,13100,8100,600,*,DOWN,PDIF ++S 13600,5500,13600,8300,200,2z,DOWN,PTRANS ++S 12400,5500,12400,8300,200,1z,DOWN,PTRANS ++S 11200,5700,11200,8300,200,1b,DOWN,PTRANS ++S 10600,5900,10600,8100,600,*,UP,PDIF ++S 9400,5900,9400,9100,600,*,UP,PDIF ++S 5400,5900,5400,9100,600,*,UP,PDIF ++S 8400,5900,8400,8100,400,n1a,UP,PDIF ++S 10000,5700,10000,8300,200,2b,DOWN,PTRANS ++S 8800,5700,8800,8300,200,4a,DOWN,PTRANS ++S 6400,5900,6400,8100,400,n1b,UP,PDIF ++S 6000,5700,6000,8300,200,3a,DOWN,PTRANS ++S 6800,5700,6800,8300,200,3b,DOWN,PTRANS ++S 8000,5700,8000,8300,200,4b,DOWN,PTRANS ++S 7400,5900,7400,8100,600,*,UP,PDIF ++S 3000,5900,3000,8100,600,*,UP,PDIF ++S 3600,5700,3600,8300,200,2c,DOWN,PTRANS ++S 4800,5700,4800,8300,200,2a,DOWN,PTRANS ++S 4200,5900,4200,8100,600,*,UP,PDIF ++S 600,5900,600,8100,600,*,DOWN,PDIF ++S 2400,5700,2400,8300,200,1c,DOWN,PTRANS ++S 1200,5700,1200,8300,200,1a,DOWN,PTRANS ++S 1800,5900,1800,8100,600,*,DOWN,PDIF ++S 14000,5000,14000,5000,400,z,LEFT,CALU1 ++S 13000,5000,14100,5000,400,*,RIGHT,ALU1 ++S 13000,3000,13000,7000,400,z,UP,CALU1 ++S 12400,4600,13600,4600,200,*,RIGHT,POLY ++S 11000,4400,12200,4400,400,*,RIGHT,ALU1 ++S 11000,3000,11000,4400,400,*,UP,ALU1 ++S 10000,4000,10000,6000,600,*,DOWN,ALU1 ++S 10000,4000,10000,6000,400,b,DOWN,CALU1 ++S 13600,3700,13600,5700,200,*,DOWN,POLY ++S 12400,3700,12400,5700,200,*,DOWN,POLY ++S 13000,2500,13000,7100,400,*,DOWN,ALU1 ++S 14200,6900,14200,9300,400,*,UP,ALU1 ++S 0,5000,15000,5000,10000,cgn2_x3,LEFT,TALU8 ++S 0,2200,15000,2200,5200,*,LEFT,PWELL ++S 0,7600,15000,7600,5600,*,LEFT,NWELL ++S 0,9400,15000,9400,1200,vdd,RIGHT,CALU1 ++S 0,600,15000,600,1200,vss,RIGHT,CALU1 ++S 1000,7000,9000,7000,400,*,RIGHT,ALU1 ++S 1000,4900,1000,7000,400,*,UP,ALU1 ++S 2000,5000,3100,5000,400,*,LEFT,ALU1 ++S 2400,5000,3600,5000,600,*,RIGHT,POLY ++S 2000,3900,2000,6100,400,*,DOWN,ALU1 ++S 3000,5000,3000,5000,400,c,LEFT,CALU1 ++S 2000,4000,2000,6000,400,c,DOWN,CALU1 ++S 4000,3000,4000,6000,400,*,DOWN,ALU1 ++S 2900,6000,7500,6000,400,*,RIGHT,ALU1 ++S 1000,5000,1000,7000,400,a,UP,CALU1 ++S 2000,7000,2000,7000,400,a,LEFT,CALU1 ++S 3000,7000,3000,7000,400,a,LEFT,CALU1 ++S 4000,7000,4000,7000,400,a,LEFT,CALU1 ++S 5000,7000,5000,7000,400,a,LEFT,CALU1 ++S 6000,7000,6000,7000,400,a,LEFT,CALU1 ++S 7000,7000,7000,7000,400,a,LEFT,CALU1 ++S 8000,7000,8000,7000,400,a,LEFT,CALU1 ++S 5900,5000,9000,5000,400,*,RIGHT,ALU1 ++S 7000,5000,7000,5000,400,a,LEFT,CALU1 ++S 8000,5000,8000,5000,400,a,LEFT,CALU1 ++S 6000,5000,6000,5000,400,a,LEFT,CALU1 ++S 9000,5000,9000,7000,400,a,UP,CALU1 ++S 9000,5000,9000,7000,600,*,UP,ALU1 ++S 5000,4000,5000,4000,400,b,LEFT,CALU1 ++S 6000,4000,6000,4000,400,b,LEFT,CALU1 ++S 7000,4000,7000,4000,400,b,LEFT,CALU1 ++S 8000,4000,8000,4000,400,b,LEFT,CALU1 ++S 9000,4000,9000,4000,400,b,LEFT,CALU1 ++S 4900,4000,10000,4000,400,*,RIGHT,ALU1 ++S 10000,5200,11200,5200,200,*,LEFT,POLY ++S 11200,5200,11200,5700,200,*,DOWN,POLY ++S 10000,5200,10000,5700,200,*,DOWN,POLY ++S 4800,5300,6200,5300,200,*,RIGHT,POLY ++S 5000,4000,5000,4600,600,*,DOWN,ALU1 ++S 600,7900,600,9300,400,*,UP,ALU1 ++S 1700,8000,10600,8000,400,*,RIGHT,ALU1 ++S 10600,6900,10600,8000,400,*,DOWN,ALU1 ++S 11800,6900,11800,9300,400,*,UP,ALU1 ++S 600,700,600,3100,400,*,DOWN,ALU1 ++S 6800,4000,8000,4000,600,*,RIGHT,POLY ++S 1200,8300,1200,8700,200,*,UP,POLY ++S 2400,8300,2400,8700,200,*,UP,POLY ++S 3600,8300,3600,8700,200,*,UP,POLY ++S 4800,8300,4800,8700,200,*,UP,POLY ++S 6000,8300,6000,8700,200,*,UP,POLY ++S 6800,8300,6800,8700,200,*,UP,POLY ++S 8000,8300,8000,8700,200,*,UP,POLY ++S 8800,8300,8800,8700,200,*,UP,POLY ++S 10000,8300,10000,8700,200,*,UP,POLY ++S 11200,8300,11200,8700,200,*,UP,POLY ++S 12400,8300,12400,8700,200,*,UP,POLY ++S 13600,8300,13600,8700,200,*,UP,POLY ++S 1200,1400,1200,1800,200,*,DOWN,POLY ++S 2400,1400,2400,1800,200,*,DOWN,POLY ++S 3600,1400,3600,1800,200,*,DOWN,POLY ++S 4800,1400,4800,1800,200,*,DOWN,POLY ++S 6000,1400,6000,1800,200,*,DOWN,POLY ++S 6800,1400,6800,1800,200,*,DOWN,POLY ++S 8000,1400,8000,1800,200,*,DOWN,POLY ++S 8800,1400,8800,1800,200,*,DOWN,POLY ++S 13600,1800,13600,2200,200,*,DOWN,POLY ++S 12400,1800,12400,2200,200,*,DOWN,POLY ++V 2000,9300,CONT_BODY_N,* ++V 1000,9300,CONT_BODY_N,* ++V 2000,700,CONT_BODY_P,* ++V 1000,700,CONT_BODY_P,* ++V 9400,2100,CONT_DIF_N,* ++V 7400,2600,CONT_DIF_N,zn ++V 5400,2100,CONT_DIF_N,* ++V 600,2200,CONT_DIF_N,* ++V 1800,2100,CONT_DIF_N,n4 ++V 4200,2100,CONT_DIF_N,n4 ++V 3000,2700,CONT_DIF_N,zn ++V 14200,2600,CONT_DIF_N,* ++V 14200,3400,CONT_DIF_N,* ++V 11800,2600,CONT_DIF_N,* ++V 11800,3400,CONT_DIF_N,* ++V 7400,6000,CONT_DIF_P,zn ++V 3000,6000,CONT_DIF_P,zn ++V 12100,4400,CONT_POLY,zn ++V 13000,2600,CONT_DIF_N,* ++V 13000,3400,CONT_DIF_N,* ++V 13000,7000,CONT_DIF_P,* ++V 13000,6000,CONT_DIF_P,* ++V 14200,7000,CONT_DIF_P,* ++V 14200,8000,CONT_DIF_P,* ++V 1000,5000,CONT_POLY,* ++V 3000,5000,CONT_POLY,* ++V 1800,8000,CONT_DIF_P,n2 ++V 5400,9000,CONT_DIF_P,* ++V 4200,8000,CONT_DIF_P,n2 ++V 11800,8000,CONT_DIF_P,* ++V 6000,5000,CONT_POLY,* ++V 9000,5000,CONT_POLY,* ++V 10000,5000,CONT_POLY,* ++V 5000,4500,CONT_POLY,* ++V 600,8000,CONT_DIF_P,* ++V 10600,7000,CONT_DIF_P,n2 ++V 10600,7800,CONT_DIF_P,n2 ++V 11800,7000,CONT_DIF_P,* ++V 600,3000,CONT_DIF_N,* ++V 9400,9000,CONT_DIF_P,* ++V 7400,4000,CONT_POLY,* ++EOF +diff --git a/alliance/src/cells/src/msxlib/cgn2_x3.vbe b/alliance/src/cells/src/msxlib/cgn2_x3.vbe +new file mode 100644 +index 0000000..d2b043a +--- /dev/null ++++ b/alliance/src/cells/src/msxlib/cgn2_x3.vbe +@@ -0,0 +1,38 @@ ++ENTITY cgn2_x3 IS ++GENERIC ( ++ CONSTANT area : NATURAL := 15000; ++ CONSTANT cin_a : NATURAL := 18; ++ CONSTANT cin_b : NATURAL := 17; ++ CONSTANT cin_c : NATURAL := 8; ++ CONSTANT rdown_a_z : NATURAL := 770; ++ CONSTANT rdown_b_z : NATURAL := 780; ++ CONSTANT rdown_c_z : NATURAL := 780; ++ CONSTANT rup_a_z : NATURAL := 1060; ++ CONSTANT rup_b_z : NATURAL := 1060; ++ CONSTANT rup_c_z : NATURAL := 1060; ++ CONSTANT tphh_c_z : NATURAL := 102; ++ CONSTANT tpll_c_z : NATURAL := 122; ++ CONSTANT tpll_a_z : NATURAL := 138; ++ CONSTANT tphh_b_z : NATURAL := 108; ++ CONSTANT tpll_b_z : NATURAL := 134; ++ CONSTANT tphh_a_z : NATURAL := 108; ++ CONSTANT transistors : NATURAL := 22 ++); ++PORT ( ++ a : in BIT; ++ b : in BIT; ++ c : in BIT; ++ z : out BIT; ++ vdd : in BIT; ++ vss : in BIT ++); ++END cgn2_x3; ++ ++ARCHITECTURE behaviour_data_flow OF cgn2_x3 IS ++ ++BEGIN ++ ASSERT ((vdd and not (vss)) = '1') ++ REPORT "power supply is missing on cgn2_x3" ++ SEVERITY WARNING; ++ z <= ((b and (a or c)) or (a and c)) after 1200 ps; ++END; +diff --git a/alliance/src/cells/src/msxlib/cgn2_x4.ap b/alliance/src/cells/src/msxlib/cgn2_x4.ap +new file mode 100644 +index 0000000..9b6749f +--- /dev/null ++++ b/alliance/src/cells/src/msxlib/cgn2_x4.ap +@@ -0,0 +1,227 @@ ++V ALLIANCE : 6 ++H cgn2_x4,P, 8/ 8/2014,100 ++A 0,0,15000,10000 ++R 6000,4000,ref_ref,b_40 ++R 7000,4000,ref_ref,b_40 ++R 8000,4000,ref_ref,b_40 ++R 9000,4000,ref_ref,b_40 ++R 5000,4000,ref_ref,b_40 ++R 9000,6000,ref_ref,a_60 ++R 1000,6000,ref_ref,a_60 ++R 1000,7000,ref_ref,a_70 ++R 2000,7000,ref_ref,a_70 ++R 3000,7000,ref_ref,a_70 ++R 4000,7000,ref_ref,a_70 ++R 5000,7000,ref_ref,a_70 ++R 6000,7000,ref_ref,a_70 ++R 7000,7000,ref_ref,a_70 ++R 8000,7000,ref_ref,a_70 ++R 8000,5000,ref_ref,a_50 ++R 7000,5000,ref_ref,a_50 ++R 9000,7000,ref_ref,a_70 ++R 9000,5000,ref_ref,a_50 ++R 6000,5000,ref_ref,a_50 ++R 1000,5000,ref_ref,a_50 ++R 10000,5000,ref_ref,b_50 ++R 10000,4000,ref_ref,b_40 ++R 2000,5000,ref_ref,c_50 ++R 2000,6000,ref_ref,c_60 ++R 3000,5000,ref_ref,c_50 ++R 2000,4000,ref_ref,c_40 ++R 10000,6000,ref_ref,b_60 ++R 13000,4000,ref_ref,z_40 ++R 13000,3000,ref_ref,z_30 ++R 13000,5000,ref_ref,z_50 ++R 14000,5000,ref_ref,z_50 ++R 13000,6000,ref_ref,z_60 ++R 13000,7000,ref_ref,z_70 ++S 11100,700,11900,700,600,*,RIGHT,PTIE ++S 13600,9300,13600,9700,200,*,DOWN,POLY ++S 12400,9300,12400,9700,200,*,DOWN,POLY ++S 11200,8700,11200,9100,200,*,DOWN,POLY ++S 10000,8700,10000,9100,200,*,DOWN,POLY ++S 8800,8700,8800,9100,200,*,DOWN,POLY ++S 8000,8700,8000,9100,200,*,DOWN,POLY ++S 6800,8700,6800,9100,200,*,DOWN,POLY ++S 6000,8700,6000,9100,200,*,DOWN,POLY ++S 4800,8700,4800,9100,200,*,DOWN,POLY ++S 3600,8700,3600,9100,200,*,DOWN,POLY ++S 2400,8700,2400,9100,200,*,DOWN,POLY ++S 1200,8700,1200,9100,200,*,DOWN,POLY ++S 10000,5600,10000,8700,200,2b,DOWN,PTRANS ++S 11200,5600,11200,8700,200,1b,DOWN,PTRANS ++S 10600,5800,10600,8500,600,*,UP,PDIF ++S 7400,5800,7400,8500,600,*,UP,PDIF ++S 8400,5800,8400,8500,400,n1a,UP,PDIF ++S 8800,5600,8800,8700,200,4a,DOWN,PTRANS ++S 8000,5600,8000,8700,200,4b,DOWN,PTRANS ++S 6400,5800,6400,8500,400,n1b,UP,PDIF ++S 6000,5600,6000,8700,200,3a,DOWN,PTRANS ++S 6800,5600,6800,8700,200,3b,DOWN,PTRANS ++S 4800,5600,4800,8700,200,2a,DOWN,PTRANS ++S 4200,5800,4200,8500,600,*,UP,PDIF ++S 600,5800,600,8500,600,*,DOWN,PDIF ++S 1800,5800,1800,8500,600,*,DOWN,PDIF ++S 1200,5600,1200,8700,200,1a,DOWN,PTRANS ++S 3600,5600,3600,8700,200,2c,DOWN,PTRANS ++S 3000,5800,3000,8500,1000,*,UP,PDIF ++S 2400,5600,2400,8700,200,1c,DOWN,PTRANS ++S 14300,5800,14300,9100,600,*,DOWN,PDIF ++S 13600,5600,13600,9300,200,2z,DOWN,PTRANS ++S 13100,5800,13100,9100,600,*,DOWN,PDIF ++S 12400,5600,12400,9300,200,1z,DOWN,PTRANS ++S 11900,5800,11900,9100,600,*,DOWN,PDIF ++S 9400,5800,9400,9100,600,*,UP,PDIF ++S 5400,5800,5400,9100,600,*,UP,PDIF ++S 4800,5200,6200,5200,200,*,RIGHT,POLY ++S 4800,3300,4800,4000,200,*,UP,POLY ++S 8800,1500,8800,1900,200,*,DOWN,POLY ++S 8000,1500,8000,1900,200,*,DOWN,POLY ++S 6800,1500,6800,1900,200,*,DOWN,POLY ++S 6000,1500,6000,1900,200,*,DOWN,POLY ++S 8800,3300,8800,5700,200,*,DOWN,POLY ++S 8000,3300,8000,5700,200,*,DOWN,POLY ++S 6800,3300,6800,5700,200,*,DOWN,POLY ++S 6000,3300,6000,5700,200,*,DOWN,POLY ++S 9400,700,9400,2200,600,*,DOWN,ALU1 ++S 6000,1900,6000,3300,200,7a,UP,NTRANS ++S 6400,2100,6400,3100,400,n3b,UP,NDIF ++S 9500,2100,9500,3100,600,*,UP,NDIF ++S 8800,1900,8800,3300,200,8a,UP,NTRANS ++S 8400,2100,8400,3100,400,n3a,UP,NDIF ++S 8000,1900,8000,3300,200,8b,UP,NTRANS ++S 6800,1900,6800,3300,200,7b,UP,NTRANS ++S 7400,2100,7400,3100,600,*,DOWN,NDIF ++S 5400,800,5400,3100,600,*,UP,NDIF ++S 4800,600,4800,3300,200,5b,UP,NTRANS ++S 4400,800,4400,3100,400,*,DOWN,NDIF ++S 1200,3300,1200,5700,200,*,DOWN,POLY ++S 600,800,600,3100,600,*,UP,NDIF ++S 1200,600,1200,3300,200,5a,UP,NTRANS ++S 1600,800,1600,3100,400,*,UP,NDIF ++S 4200,2100,4200,3100,600,*,UP,NDIF ++S 3600,3300,3600,5600,200,*,DOWN,POLY ++S 2400,3300,2400,5600,200,*,DOWN,POLY ++S 2400,1500,2400,1900,200,*,DOWN,POLY ++S 3600,1500,3600,1900,200,*,DOWN,POLY ++S 1800,2100,1800,3100,600,*,UP,NDIF ++S 1800,2200,1800,3000,600,*,DOWN,ALU1 ++S 1800,2200,4300,2200,400,*,RIGHT,ALU1 ++S 3600,1900,3600,3300,200,4c,UP,NTRANS ++S 2400,1900,2400,3300,200,3c,UP,NTRANS ++S 3000,2100,3000,3100,600,*,DOWN,NDIF ++S 6800,4000,8000,4000,600,*,RIGHT,POLY ++S 1200,300,1200,600,200,*,DOWN,POLY ++S 4800,300,4800,600,200,*,DOWN,POLY ++S 5400,700,5400,2100,400,*,DOWN,ALU1 ++S 600,700,600,3100,400,*,DOWN,ALU1 ++S 11800,6900,11800,9300,400,*,UP,ALU1 ++S 10600,6900,10600,8000,400,*,DOWN,ALU1 ++S 1700,8000,10600,8000,400,*,RIGHT,ALU1 ++S 600,7900,600,9300,400,*,UP,ALU1 ++S 10000,5200,10000,5700,200,*,DOWN,POLY ++S 11200,5200,11200,5700,200,*,DOWN,POLY ++S 10000,5200,11200,5200,200,*,LEFT,POLY ++S 4900,4000,10000,4000,400,*,RIGHT,ALU1 ++S 9000,4000,9000,4000,400,b,LEFT,CALU1 ++S 8000,4000,8000,4000,400,b,LEFT,CALU1 ++S 7000,4000,7000,4000,400,b,LEFT,CALU1 ++S 6000,4000,6000,4000,400,b,LEFT,CALU1 ++S 5000,4000,5000,4000,400,b,LEFT,CALU1 ++S 9000,5000,9000,7000,600,*,UP,ALU1 ++S 9000,5000,9000,7000,400,a,UP,CALU1 ++S 6000,5000,6000,5000,400,a,LEFT,CALU1 ++S 8000,5000,8000,5000,400,a,LEFT,CALU1 ++S 7000,5000,7000,5000,400,a,LEFT,CALU1 ++S 5900,5000,9000,5000,400,*,RIGHT,ALU1 ++S 8000,7000,8000,7000,400,a,LEFT,CALU1 ++S 7000,7000,7000,7000,400,a,LEFT,CALU1 ++S 6000,7000,6000,7000,400,a,LEFT,CALU1 ++S 5000,7000,5000,7000,400,a,LEFT,CALU1 ++S 4000,7000,4000,7000,400,a,LEFT,CALU1 ++S 3000,7000,3000,7000,400,a,LEFT,CALU1 ++S 2000,7000,2000,7000,400,a,LEFT,CALU1 ++S 1000,5000,1000,7000,400,a,UP,CALU1 ++S 2900,6000,7500,6000,400,*,RIGHT,ALU1 ++S 4000,3000,4000,6000,400,*,DOWN,ALU1 ++S 2000,4000,2000,6000,400,c,DOWN,CALU1 ++S 3000,5000,3000,5000,400,c,LEFT,CALU1 ++S 2000,3900,2000,6100,400,*,DOWN,ALU1 ++S 2400,5000,3600,5000,600,*,RIGHT,POLY ++S 2000,5000,3100,5000,400,*,LEFT,ALU1 ++S 1000,4900,1000,7000,400,*,UP,ALU1 ++S 1000,7000,9000,7000,400,*,RIGHT,ALU1 ++S 0,600,15000,600,1200,vss,RIGHT,CALU1 ++S 0,9400,15000,9400,1200,vdd,RIGHT,CALU1 ++S 0,5000,15000,5000,10000,cgn2_x4,LEFT,TALU8 ++S 0,2200,15000,2200,5200,*,LEFT,PWELL ++S 0,7600,15000,7600,5600,*,LEFT,NWELL ++S 14200,6900,14200,9300,400,*,UP,ALU1 ++S 13000,2500,13000,7100,400,*,DOWN,ALU1 ++S 14200,700,14200,3100,400,*,DOWN,ALU1 ++S 11800,700,11800,3100,400,*,DOWN,ALU1 ++S 14300,2100,14300,3500,600,*,UP,NDIF ++S 11700,2100,11700,3500,600,*,UP,NDIF ++S 13000,2100,13000,3500,600,*,UP,NDIF ++S 12400,1900,12400,3700,200,3z,UP,NTRANS ++S 13600,1900,13600,3700,200,4z,UP,NTRANS ++S 12400,3700,12400,5700,200,*,DOWN,POLY ++S 13600,3700,13600,5700,200,*,DOWN,POLY ++S 10000,4000,10000,6000,400,b,DOWN,CALU1 ++S 10000,4000,10000,6000,600,*,DOWN,ALU1 ++S 7400,2100,7400,3000,400,*,DOWN,ALU1 ++S 2900,3000,11000,3000,400,*,RIGHT,ALU1 ++S 11000,3000,11000,4400,400,*,UP,ALU1 ++S 11000,4400,12200,4400,400,*,RIGHT,ALU1 ++S 12400,4600,13600,4600,200,*,RIGHT,POLY ++S 13000,3000,13000,7000,400,z,UP,CALU1 ++S 13000,5000,14100,5000,400,*,RIGHT,ALU1 ++S 14000,5000,14000,5000,400,z,LEFT,CALU1 ++S 12400,1500,12400,1900,200,*,DOWN,POLY ++S 13600,1500,13600,1900,200,*,DOWN,POLY ++V 12000,700,CONT_BODY_P,* ++V 11000,700,CONT_BODY_P,* ++V 5000,4000,CONT_POLY,* ++V 9400,2200,CONT_DIF_N,* ++V 4200,2200,CONT_DIF_N,n4 ++V 7400,4000,CONT_POLY,* ++V 9400,9000,CONT_DIF_P,* ++V 5400,2000,CONT_DIF_N,* ++V 1800,2200,CONT_DIF_N,n4 ++V 1800,3000,CONT_DIF_N,n4 ++V 600,3000,CONT_DIF_N,* ++V 600,2000,CONT_DIF_N,* ++V 11800,7000,CONT_DIF_P,* ++V 10600,7800,CONT_DIF_P,n2 ++V 10600,7000,CONT_DIF_P,n2 ++V 600,8000,CONT_DIF_P,* ++V 10000,5000,CONT_POLY,* ++V 9000,5000,CONT_POLY,* ++V 6000,5000,CONT_POLY,* ++V 11800,9000,CONT_DIF_P,* ++V 11800,8000,CONT_DIF_P,* ++V 4200,8000,CONT_DIF_P,n2 ++V 5400,9000,CONT_DIF_P,* ++V 1800,8000,CONT_DIF_P,n2 ++V 5400,1000,CONT_DIF_N,* ++V 600,1000,CONT_DIF_N,* ++V 3000,5000,CONT_POLY,* ++V 1000,5000,CONT_POLY,* ++V 14200,9000,CONT_DIF_P,* ++V 14200,8000,CONT_DIF_P,* ++V 14200,7000,CONT_DIF_P,* ++V 13000,6000,CONT_DIF_P,* ++V 13000,7000,CONT_DIF_P,* ++V 14200,2200,CONT_DIF_N,* ++V 11800,2200,CONT_DIF_N,* ++V 11800,3000,CONT_DIF_N,* ++V 14200,3000,CONT_DIF_N,* ++V 13000,3400,CONT_DIF_N,* ++V 13000,2600,CONT_DIF_N,* ++V 12100,4400,CONT_POLY,zn ++V 7400,3000,CONT_DIF_N,zn ++V 7400,2200,CONT_DIF_N,zn ++V 3000,3000,CONT_DIF_N,zn ++V 3000,6000,CONT_DIF_P,zn ++V 7400,6000,CONT_DIF_P,zn ++EOF +diff --git a/alliance/src/cells/src/msxlib/cgn2_x4.vbe b/alliance/src/cells/src/msxlib/cgn2_x4.vbe +new file mode 100644 +index 0000000..4092bec +--- /dev/null ++++ b/alliance/src/cells/src/msxlib/cgn2_x4.vbe +@@ -0,0 +1,38 @@ ++ENTITY cgn2_x4 IS ++GENERIC ( ++ CONSTANT area : NATURAL := 15000; ++ CONSTANT cin_a : NATURAL := 21; ++ CONSTANT cin_b : NATURAL := 19; ++ CONSTANT cin_c : NATURAL := 10; ++ CONSTANT rdown_a_z : NATURAL := 640; ++ CONSTANT rdown_b_z : NATURAL := 650; ++ CONSTANT rdown_c_z : NATURAL := 650; ++ CONSTANT rup_a_z : NATURAL := 800; ++ CONSTANT rup_b_z : NATURAL := 800; ++ CONSTANT rup_c_z : NATURAL := 800; ++ CONSTANT tphh_c_z : NATURAL := 100; ++ CONSTANT tpll_c_z : NATURAL := 123; ++ CONSTANT tpll_a_z : NATURAL := 139; ++ CONSTANT tphh_b_z : NATURAL := 107; ++ CONSTANT tpll_b_z : NATURAL := 135; ++ CONSTANT tphh_a_z : NATURAL := 107; ++ CONSTANT transistors : NATURAL := 22 ++); ++PORT ( ++ a : in BIT; ++ b : in BIT; ++ c : in BIT; ++ z : out BIT; ++ vdd : in BIT; ++ vss : in BIT ++); ++END cgn2_x4; ++ ++ARCHITECTURE behaviour_data_flow OF cgn2_x4 IS ++ ++BEGIN ++ ASSERT ((vdd and not (vss)) = '1') ++ REPORT "power supply is missing on cgn2_x4" ++ SEVERITY WARNING; ++ z <= ((b and (a or c)) or (a and c)) after 1200 ps; ++END; +diff --git a/alliance/src/cells/src/msxlib/ha2_x2.ap b/alliance/src/cells/src/msxlib/ha2_x2.ap +new file mode 100644 +index 0000000..bb459fe +--- /dev/null ++++ b/alliance/src/cells/src/msxlib/ha2_x2.ap +@@ -0,0 +1,161 @@ ++V ALLIANCE : 6 ++H ha2_x2,P, 8/ 8/2014,100 ++A 0,0,10000,10000 ++R 6000,5000,ref_ref,a_50 ++R 9000,3000,ref_ref,co_30 ++R 5000,4000,ref_ref,a_40 ++R 5000,3000,ref_ref,a_30 ++R 5000,5000,ref_ref,a_50 ++R 7000,5000,ref_ref,b_50 ++R 6000,6000,ref_ref,b_60 ++R 5000,6000,ref_ref,b_60 ++R 7000,6000,ref_ref,b_60 ++R 4000,5000,ref_ref,b_50 ++R 4000,4000,ref_ref,b_40 ++R 4000,6000,ref_ref,b_60 ++R 9000,4000,ref_ref,co_40 ++R 9000,5000,ref_ref,co_50 ++R 9000,6000,ref_ref,co_60 ++R 9000,7000,ref_ref,co_70 ++R 1000,7000,ref_ref,so_70 ++R 1000,6000,ref_ref,so_60 ++R 1000,5000,ref_ref,so_50 ++R 1000,4000,ref_ref,so_40 ++R 1000,3000,ref_ref,so_30 ++S 8800,900,8800,1300,200,*,DOWN,POLY ++S 7600,300,7600,600,200,*,DOWN,POLY ++S 6800,300,6800,600,200,*,DOWN,POLY ++S 4600,1200,4600,1600,200,*,DOWN,POLY ++S 3400,900,3400,1300,200,*,DOWN,POLY ++S 2200,900,2200,1300,200,*,DOWN,POLY ++S 1200,1200,1200,1500,200,*,DOWN,POLY ++S 8400,9400,8400,9700,200,*,UP,POLY ++S 7200,9400,7200,9700,200,*,UP,POLY ++S 6000,9400,6000,9700,200,*,UP,POLY ++S 4600,9000,4600,9400,200,*,UP,POLY ++S 3800,9000,3800,9400,200,*,UP,POLY ++S 2600,7400,2600,7800,200,*,UP,POLY ++S 1400,9400,1400,9700,200,*,UP,POLY ++S 6000,5000,6000,5000,400,a,LEFT,CALU1 ++S 6000,6000,6000,6000,400,b,LEFT,CALU1 ++S 5000,6000,5000,6000,400,b,LEFT,CALU1 ++S 7000,5000,7000,6000,400,b,DOWN,CALU1 ++S 4000,4000,4000,6000,400,b,UP,CALU1 ++S 5000,3000,5000,5000,400,a,UP,CALU1 ++S 9000,3000,9000,7000,400,co,UP,CALU1 ++S 1000,3000,1000,7000,400,so,UP,CALU1 ++S 4200,5800,4200,8800,400,n3,UP,PDIF ++S 7200,800,7200,3600,400,n1,UP,NDIF ++S 7600,3800,7600,4200,200,*,UP,POLY ++S 3800,4000,4000,4000,600,*,LEFT,ALU1 ++S 3800,4000,3800,5600,200,*,DOWN,POLY ++S 3400,2800,3400,4200,200,*,UP,POLY ++S 4600,3100,4600,5600,200,*,DOWN,POLY ++S 2700,1900,5300,1900,400,*,RIGHT,ALU1 ++S 2200,3200,2600,3200,200,*,LEFT,POLY ++S 2200,1300,2200,2800,200,2,UP,NTRANS ++S 4600,1600,4600,3100,200,3a,UP,NTRANS ++S 3400,1300,3400,2800,200,3b,UP,NTRANS ++S 5000,1800,5000,2900,400,*,UP,NDIF ++S 3800,1500,3800,2600,400,*,UP,NDIF ++S 4000,1800,4000,2900,600,*,UP,NDIF ++S 2800,1500,2800,2600,600,*,UP,NDIF ++S 8400,5600,8400,9400,200,1c,DOWN,PTRANS ++S 2600,5600,2600,7400,200,1,DOWN,PTRANS ++S 6800,600,6800,3800,200,4a,UP,NTRANS ++S 4600,5600,4600,9000,200,1a,DOWN,PTRANS ++S 7600,600,7600,3800,200,4b,UP,NTRANS ++S 7200,5600,7200,9400,200,2b,DOWN,PTRANS ++S 3800,5600,3800,9000,200,1b,DOWN,PTRANS ++S 8800,1300,8800,3200,200,2c,UP,NTRANS ++S 1200,1500,1200,3400,200,2s,UP,NTRANS ++S 1400,5600,1400,9400,200,1s,DOWN,PTRANS ++S 5000,5000,6000,5000,600,*,LEFT,ALU1 ++S 5000,5000,5800,5000,600,*,LEFT,POLY ++S 6000,4200,6800,4200,200,*,RIGHT,POLY ++S 600,2200,600,3200,400,*,UP,ALU1 ++S 600,2400,600,3000,600,*,DOWN,NDIF ++S 1000,2900,1000,7100,400,*,DOWN,ALU1 ++S 8800,3200,8800,4800,200,*,UP,POLY ++S 9400,2000,9400,3000,400,*,UP,ALU1 ++S 9400,2200,9400,2700,600,*,UP,NDIF ++S 9200,1500,9200,3000,400,*,UP,NDIF ++S 9000,2900,9000,7100,400,*,DOWN,ALU1 ++S 5200,5800,5200,9200,600,*,DOWN,PDIF ++S 8200,700,8200,2100,400,*,DOWN,ALU1 ++S 4000,3900,4000,6000,400,*,DOWN,ALU1 ++S 4000,6000,7000,6000,400,*,RIGHT,ALU1 ++S 3000,6000,3200,6000,600,*,RIGHT,ALU1 ++S 3000,2800,3000,6100,400,*,DOWN,ALU1 ++S 3000,2800,4100,2800,400,*,LEFT,ALU1 ++S 2200,7000,8200,7000,400,*,LEFT,ALU1 ++S 1800,4000,3000,4000,600,*,RIGHT,ALU1 ++S 2200,4900,2200,7000,400,*,UP,ALU1 ++S 2600,3200,2600,5600,200,*,DOWN,POLY ++S 9000,6000,9000,6600,600,*,UP,PDIF ++S 8800,5800,8800,9200,400,*,DOWN,PDIF ++S 6600,7000,6600,8100,400,*,UP,ALU1 ++S 7800,5800,7800,9200,600,*,UP,PDIF ++S 6600,5800,6600,9200,600,*,DOWN,PDIF ++S 3400,5800,3400,8800,400,*,DOWN,PDIF ++S 3200,5800,3200,7200,600,*,UP,PDIF ++S 6100,3500,8200,3500,400,*,RIGHT,ALU1 ++S 8200,800,8200,3600,600,*,UP,NDIF ++S 6400,800,6400,3600,400,*,UP,NDIF ++S 8200,4800,8800,4800,200,*,LEFT,POLY ++S 7400,4200,7400,5200,200,*,UP,POLY ++S 1700,500,1700,3200,400,*,UP,NDIF ++S 800,1700,800,3200,400,*,UP,NDIF ++S 1400,3800,1400,5600,200,*,DOWN,POLY ++S 1200,3400,1200,4200,200,*,DOWN,POLY ++S 900,5800,900,7100,600,*,UP,ALU1 ++S 800,6000,800,6600,600,*,DOWN,PDIF ++S 1000,5800,1000,9200,400,*,DOWN,PDIF ++S 2000,7900,2000,9300,400,*,UP,ALU1 ++S 1900,5800,1900,9200,800,*,DOWN,PDIF ++S 8200,3500,8200,7000,400,*,DOWN,ALU1 ++S 7000,4900,7000,6000,400,*,DOWN,ALU1 ++S 6000,4200,6000,5600,200,*,DOWN,POLY ++S 5000,2900,5000,5100,400,*,UP,ALU1 ++S 7800,7900,7800,9300,400,*,UP,ALU1 ++S 5400,7900,5400,9300,400,*,UP,ALU1 ++S 0,600,10000,600,1200,vss,RIGHT,CALU1 ++S 0,9400,10000,9400,1200,vdd,RIGHT,CALU1 ++S 0,5000,10000,5000,10000,ha2_x2,LEFT,TALU8 ++S 0,2200,10000,2200,5200,*,LEFT,PWELL ++S 0,7600,10000,7600,5600,*,LEFT,NWELL ++S 6000,5600,6000,9400,200,2a,DOWN,PTRANS ++S 4000,6100,7000,6100,400,*,RIGHT,ALU1 ++V 5000,700,CONT_BODY_P,* ++V 3800,4000,CONT_POLY,* ++V 5200,1900,CONT_DIF_N,n2 ++V 4000,2800,CONT_DIF_N,son ++V 2800,1900,CONT_DIF_N,n2 ++V 1600,600,CONT_DIF_N,* ++V 5000,5000,CONT_POLY,* ++V 5800,5000,CONT_POLY,* ++V 600,2300,CONT_DIF_N,* ++V 600,3100,CONT_DIF_N,* ++V 9400,2100,CONT_DIF_N,* ++V 9400,2900,CONT_DIF_N,* ++V 8200,2000,CONT_DIF_N,* ++V 2200,5000,CONT_POLY,con ++V 2000,9000,CONT_DIF_P,* ++V 8200,1000,CONT_DIF_N,* ++V 6200,3500,CONT_DIF_N,con ++V 800,6700,CONT_DIF_P,* ++V 800,5900,CONT_DIF_P,* ++V 2000,8000,CONT_DIF_P,* ++V 8200,5000,CONT_POLY,con ++V 7000,5000,CONT_POLY,* ++V 1800,4000,CONT_POLY,son ++V 3200,6000,CONT_DIF_P,son ++V 6600,8000,CONT_DIF_P,con ++V 6600,7000,CONT_DIF_P,con ++V 7800,9000,CONT_DIF_P,* ++V 7800,8000,CONT_DIF_P,* ++V 5400,8000,CONT_DIF_P,* ++V 9000,6700,CONT_DIF_P,* ++V 9000,5900,CONT_DIF_P,* ++V 5400,9000,CONT_DIF_P,* ++EOF +diff --git a/alliance/src/cells/src/msxlib/ha2_x2.vbe b/alliance/src/cells/src/msxlib/ha2_x2.vbe +new file mode 100644 +index 0000000..7315db1 +--- /dev/null ++++ b/alliance/src/cells/src/msxlib/ha2_x2.vbe +@@ -0,0 +1,46 @@ ++ENTITY ha2_x2 IS ++GENERIC ( ++ CONSTANT area : NATURAL := 10000; ++ CONSTANT cin_a : NATURAL := 13; ++ CONSTANT cin_b : NATURAL := 13; ++ CONSTANT rdown_a_co : NATURAL := 1210; ++ CONSTANT rdown_a_so : NATURAL := 1210; ++ CONSTANT rdown_b_co : NATURAL := 1210; ++ CONSTANT rdown_b_so : NATURAL := 1210; ++ CONSTANT rup_a_co : NATURAL := 1560; ++ CONSTANT rup_a_so : NATURAL := 1560; ++ CONSTANT rup_b_co : NATURAL := 1560; ++ CONSTANT rup_b_so : NATURAL := 1560; ++ CONSTANT tphh_a_co : NATURAL := 70; ++ CONSTANT tpll_b_co : NATURAL := 99; ++ CONSTANT tphh_b_co : NATURAL := 70; ++ CONSTANT tpll_a_co : NATURAL := 89; ++ CONSTANT tphh_a_so : NATURAL := 100; ++ CONSTANT tpll_b_so : NATURAL := 108; ++ CONSTANT tphl_b_so : NATURAL := 154; ++ CONSTANT tplh_b_so : NATURAL := 160; ++ CONSTANT tphh_b_so : NATURAL := 87; ++ CONSTANT tpll_a_so : NATURAL := 117; ++ CONSTANT tphl_a_so : NATURAL := 155; ++ CONSTANT tplh_a_so : NATURAL := 144; ++ CONSTANT transistors : NATURAL := 14 ++); ++PORT ( ++ a : in BIT; ++ b : in BIT; ++ co : out BIT; ++ so : out BIT; ++ vdd : in BIT; ++ vss : in BIT ++); ++END ha2_x2; ++ ++ARCHITECTURE behaviour_data_flow OF ha2_x2 IS ++ ++BEGIN ++ ASSERT ((vdd and not (vss)) = '1') ++ REPORT "power supply is missing on ha2_x2" ++ SEVERITY WARNING; ++ so <= (a xor b) after 1200 ps; ++ co <= (a and b) after 1000 ps; ++END; +diff --git a/alliance/src/cells/src/msxlib/iv1_w2.ap b/alliance/src/cells/src/msxlib/iv1_w2.ap +new file mode 100644 +index 0000000..edb6592 +--- /dev/null ++++ b/alliance/src/cells/src/msxlib/iv1_w2.ap +@@ -0,0 +1,46 @@ ++V ALLIANCE : 6 ++H iv1_w2,P, 7/ 8/2004,100 ++A 0,0,3000,10000 ++R 1000,3000,ref_ref,z_30 ++R 2000,4000,ref_ref,a_40 ++R 1000,7000,ref_ref,z_70 ++R 2000,6000,ref_ref,a_60 ++R 2000,5000,ref_ref,a_50 ++R 1000,6000,ref_ref,z_60 ++R 1000,4000,ref_ref,z_40 ++R 1000,5000,ref_ref,z_50 ++R 2000,7000,ref_ref,z_70 ++S 1000,2700,1000,7100,400,*,UP,ALU1 ++S 1000,3000,1000,7000,400,z,DOWN,CALU1 ++S 1000,2900,1000,3500,600,*,UP,NDIF ++S 1000,5900,1000,6500,600,*,UP,PDIF ++S 0,600,3000,600,1200,vss,RIGHT,CALU1 ++S 0,7600,3000,7600,5600,*,LEFT,NWELL ++S 0,2200,3000,2200,5200,*,LEFT,PWELL ++S 0,5000,3000,5000,10000,iv1_w2,LEFT,TALU8 ++S 0,9400,3000,9400,1200,vdd,RIGHT,CALU1 ++S 1600,9400,1600,9700,200,*,DOWN,POLY ++S 2200,5700,2200,9200,800,*,DOWN,PDIF ++S 1600,5500,1600,9400,200,1,UP,PTRANS ++S 1200,5700,1200,9200,400,*,UP,PDIF ++S 1200,1500,1200,3700,400,*,DOWN,NDIF ++S 1600,1300,1600,3900,200,2,DOWN,NTRANS ++S 2300,1500,2300,3700,600,*,UP,NDIF ++S 1600,900,1600,1300,200,*,UP,POLY ++S 1600,3900,1600,5500,200,*,UP,POLY ++S 2000,4000,2000,6000,400,a,DOWN,CALU1 ++S 2000,3900,2000,6100,400,*,DOWN,ALU1 ++S 2200,7900,2200,9300,400,*,UP,ALU1 ++S 2000,7000,2000,7000,400,z,LEFT,CALU1 ++S 1000,7000,2000,7000,600,*,RIGHT,ALU1 ++S 2200,700,2200,3100,400,*,UP,ALU1 ++V 1000,2800,CONT_DIF_N,* ++V 1000,6600,CONT_DIF_P,* ++V 2200,8000,CONT_DIF_P,* ++V 2200,9000,CONT_DIF_P,* ++V 2200,2000,CONT_DIF_N,* ++V 2000,4700,CONT_POLY,* ++V 1000,5800,CONT_DIF_P,* ++V 1000,3600,CONT_DIF_N,* ++V 2200,3000,CONT_DIF_N,* ++EOF +diff --git a/alliance/src/cells/src/msxlib/iv1_w2.vbe b/alliance/src/cells/src/msxlib/iv1_w2.vbe +new file mode 100644 +index 0000000..def2c41 +--- /dev/null ++++ b/alliance/src/cells/src/msxlib/iv1_w2.vbe +@@ -0,0 +1,26 @@ ++ENTITY iv1_w2 IS ++GENERIC ( ++ CONSTANT area : NATURAL := 3000; ++ CONSTANT cin_a : NATURAL := 7; ++ CONSTANT rdown_a_z : NATURAL := 880; ++ CONSTANT rup_a_z : NATURAL := 1520; ++ CONSTANT tphl_a_z : NATURAL := 32; ++ CONSTANT tplh_a_z : NATURAL := 39; ++ CONSTANT transistors : NATURAL := 2 ++); ++PORT ( ++ a : in BIT; ++ z : out BIT; ++ vdd : in BIT; ++ vss : in BIT ++); ++END iv1_w2; ++ ++ARCHITECTURE behaviour_data_flow OF iv1_w2 IS ++ ++BEGIN ++ ASSERT ((vdd and not (vss)) = '1') ++ REPORT "power supply is missing on iv1_w2" ++ SEVERITY WARNING; ++ z <= not (a) after 700 ps; ++END; +diff --git a/alliance/src/cells/src/msxlib/iv1_x05.ap b/alliance/src/cells/src/msxlib/iv1_x05.ap +new file mode 100644 +index 0000000..d97eef5 +--- /dev/null ++++ b/alliance/src/cells/src/msxlib/iv1_x05.ap +@@ -0,0 +1,47 @@ ++V ALLIANCE : 6 ++H iv1_x05,P, 8/ 8/2014,100 ++A 0,0,3000,10000 ++R 1000,3000,ref_ref,z_30 ++R 2000,6000,ref_ref,a_60 ++R 2000,5000,ref_ref,a_50 ++R 1000,6000,ref_ref,z_60 ++R 1000,4000,ref_ref,z_40 ++R 1000,5000,ref_ref,z_50 ++R 2000,3000,ref_ref,z_30 ++R 2000,4000,ref_ref,a_40 ++R 1000,7000,ref_ref,z_70 ++R 1000,2000,ref_ref,z_20 ++S 1100,9300,1900,9300,600,*,RIGHT,NTIE ++S 1100,700,1900,700,600,*,LEFT,PTIE ++S 2300,6300,2300,7100,600,*,DOWN,PDIF ++S 1600,7300,1600,7700,200,*,DOWN,POLY ++S 1600,6100,1600,7300,200,1,UP,PTRANS ++S 1200,6300,1200,7100,400,*,UP,PDIF ++S 2200,700,2200,2100,400,*,UP,ALU1 ++S 2200,6900,2200,9300,400,*,UP,ALU1 ++S 1000,2900,2100,2900,400,*,RIGHT,ALU1 ++S 1000,3000,2100,3000,400,*,RIGHT,ALU1 ++S 2000,3900,2000,6100,400,*,DOWN,ALU1 ++S 2000,4000,2000,6000,400,a,DOWN,CALU1 ++S 0,600,3000,600,1200,vss,RIGHT,CALU1 ++S 0,5000,3000,5000,10000,iv1_x05,LEFT,TALU8 ++S 0,2200,3000,2200,5200,*,LEFT,PWELL ++S 0,7600,3000,7600,5600,*,LEFT,NWELL ++S 0,9400,3000,9400,1200,vdd,RIGHT,CALU1 ++S 2000,3000,2000,3000,400,z,LEFT,CALU1 ++S 1600,1300,1600,1700,200,*,UP,POLY ++S 1600,1700,1600,2300,200,2,DOWN,NTRANS ++S 1000,2000,1000,7000,400,z,DOWN,CALU1 ++S 1000,1900,1000,7100,400,*,UP,ALU1 ++S 1600,2300,1600,6100,200,*,UP,POLY ++S 2300,1900,2300,2100,600,*,UP,NDIF ++V 2000,9300,CONT_BODY_N,* ++V 1000,9300,CONT_BODY_N,* ++V 2000,700,CONT_BODY_P,* ++V 1000,700,CONT_BODY_P,* ++V 1000,6400,CONT_DIF_P,* ++V 2200,2000,CONT_DIF_N,* ++V 2000,4700,CONT_POLY,* ++V 2200,7000,CONT_DIF_P,* ++V 1000,2000,CONT_DIF_N,* ++EOF +diff --git a/alliance/src/cells/src/msxlib/iv1_x05.vbe b/alliance/src/cells/src/msxlib/iv1_x05.vbe +new file mode 100644 +index 0000000..5542313 +--- /dev/null ++++ b/alliance/src/cells/src/msxlib/iv1_x05.vbe +@@ -0,0 +1,26 @@ ++ENTITY iv1_x05 IS ++GENERIC ( ++ CONSTANT area : NATURAL := 3000; ++ CONSTANT cin_a : NATURAL := 2; ++ CONSTANT rdown_a_z : NATURAL := 3800; ++ CONSTANT rup_a_z : NATURAL := 4930; ++ CONSTANT tphl_a_z : NATURAL := 36; ++ CONSTANT tplh_a_z : NATURAL := 41; ++ CONSTANT transistors : NATURAL := 2 ++); ++PORT ( ++ a : in BIT; ++ z : out BIT; ++ vdd : in BIT; ++ vss : in BIT ++); ++END iv1_x05; ++ ++ARCHITECTURE behaviour_data_flow OF iv1_x05 IS ++ ++BEGIN ++ ASSERT ((vdd and not (vss)) = '1') ++ REPORT "power supply is missing on iv1_x05" ++ SEVERITY WARNING; ++ z <= not (a) after 700 ps; ++END; +diff --git a/alliance/src/cells/src/msxlib/iv1_x1.ap b/alliance/src/cells/src/msxlib/iv1_x1.ap +new file mode 100644 +index 0000000..2cd20f6 +--- /dev/null ++++ b/alliance/src/cells/src/msxlib/iv1_x1.ap +@@ -0,0 +1,50 @@ ++V ALLIANCE : 6 ++H iv1_x1,P, 8/ 8/2014,100 ++A 0,0,3000,10000 ++R 2000,4000,ref_ref,a_40 ++R 1000,7000,ref_ref,z_70 ++R 2000,6000,ref_ref,a_60 ++R 2000,5000,ref_ref,a_50 ++R 1000,6000,ref_ref,z_60 ++R 1000,4000,ref_ref,z_40 ++R 1000,5000,ref_ref,z_50 ++R 2000,3000,ref_ref,z_30 ++R 1000,3000,ref_ref,z_30 ++S 1100,700,1900,700,600,*,LEFT,PTIE ++S 1100,9300,1900,9300,600,*,RIGHT,NTIE ++S 2000,3000,2000,3000,400,z,LEFT,CALU1 ++S 1600,7500,1600,7900,200,*,DOWN,POLY ++S 0,600,3000,600,1200,vss,RIGHT,CALU1 ++S 0,5000,3000,5000,10000,iv1_x1,LEFT,TALU8 ++S 0,2200,3000,2200,5200,*,LEFT,PWELL ++S 0,7600,3000,7600,5600,*,LEFT,NWELL ++S 0,9400,3000,9400,1200,vdd,RIGHT,CALU1 ++S 2000,4000,2000,6000,400,a,DOWN,CALU1 ++S 2000,3900,2000,6100,400,*,DOWN,ALU1 ++S 2200,6900,2200,9300,400,*,UP,ALU1 ++S 1600,5500,1600,7500,200,1,UP,PTRANS ++S 2200,5700,2200,7300,800,*,DOWN,PDIF ++S 1200,5700,1200,7300,400,*,UP,PDIF ++S 1000,3000,1000,7100,400,*,UP,ALU1 ++S 1000,3000,1000,7000,400,z,DOWN,CALU1 ++S 1000,3000,2100,3000,400,*,RIGHT,ALU1 ++S 1000,2900,2100,2900,400,*,RIGHT,ALU1 ++S 2200,700,2200,2100,400,*,UP,ALU1 ++S 1200,2500,1200,3100,400,*,UP,NDIF ++S 1600,2300,1600,3300,200,2,DOWN,NTRANS ++S 2300,1900,2300,3100,600,*,UP,NDIF ++S 2200,1900,2200,3100,600,*,UP,NDIF ++S 1600,3300,1600,5500,200,*,UP,POLY ++S 1600,1900,1600,2300,200,*,UP,POLY ++S 1000,6100,1000,6700,600,*,UP,PDIF ++V 2000,700,CONT_BODY_P,* ++V 1000,700,CONT_BODY_P,* ++V 2000,9300,CONT_BODY_N,* ++V 1000,9300,CONT_BODY_N,* ++V 2200,7000,CONT_DIF_P,* ++V 1000,6800,CONT_DIF_P,* ++V 2000,4700,CONT_POLY,* ++V 2200,2000,CONT_DIF_N,* ++V 1000,3000,CONT_DIF_N,* ++V 1000,6000,CONT_DIF_P,* ++EOF +diff --git a/alliance/src/cells/src/msxlib/iv1_x1.vbe b/alliance/src/cells/src/msxlib/iv1_x1.vbe +new file mode 100644 +index 0000000..7b09188 +--- /dev/null ++++ b/alliance/src/cells/src/msxlib/iv1_x1.vbe +@@ -0,0 +1,26 @@ ++ENTITY iv1_x1 IS ++GENERIC ( ++ CONSTANT area : NATURAL := 3000; ++ CONSTANT cin_a : NATURAL := 3; ++ CONSTANT rdown_a_z : NATURAL := 2280; ++ CONSTANT rup_a_z : NATURAL := 2960; ++ CONSTANT tphl_a_z : NATURAL := 35; ++ CONSTANT tplh_a_z : NATURAL := 39; ++ CONSTANT transistors : NATURAL := 2 ++); ++PORT ( ++ a : in BIT; ++ z : out BIT; ++ vdd : in BIT; ++ vss : in BIT ++); ++END iv1_x1; ++ ++ARCHITECTURE behaviour_data_flow OF iv1_x1 IS ++ ++BEGIN ++ ASSERT ((vdd and not (vss)) = '1') ++ REPORT "power supply is missing on iv1_x1" ++ SEVERITY WARNING; ++ z <= not (a) after 700 ps; ++END; +diff --git a/alliance/src/cells/src/msxlib/iv1_x2.ap b/alliance/src/cells/src/msxlib/iv1_x2.ap +new file mode 100644 +index 0000000..3a53b27 +--- /dev/null ++++ b/alliance/src/cells/src/msxlib/iv1_x2.ap +@@ -0,0 +1,50 @@ ++V ALLIANCE : 6 ++H iv1_x2,P, 8/ 8/2014,100 ++A 0,0,3000,10000 ++R 1000,5000,ref_ref,z_50 ++R 1000,4000,ref_ref,z_40 ++R 1000,6000,ref_ref,z_60 ++R 2000,5000,ref_ref,a_50 ++R 2000,6000,ref_ref,a_60 ++R 1000,7000,ref_ref,z_70 ++R 2000,4000,ref_ref,a_40 ++R 1000,3000,ref_ref,z_30 ++R 1000,2000,ref_ref,z_20 ++R 2000,7000,ref_ref,z_70 ++S 1100,700,1900,700,600,*,LEFT,PTIE ++S 1000,5900,1000,6500,600,*,UP,PDIF ++S 1000,2000,1000,7000,400,z,DOWN,CALU1 ++S 1000,1900,1000,7100,400,*,UP,ALU1 ++S 1600,1300,1600,1700,200,*,UP,POLY ++S 1600,1700,1600,3600,200,2,DOWN,NTRANS ++S 0,9400,3000,9400,1200,vdd,RIGHT,CALU1 ++S 0,5000,3000,5000,10000,iv1_x2,LEFT,TALU8 ++S 0,2200,3000,2200,5200,*,LEFT,PWELL ++S 0,7600,3000,7600,5600,*,LEFT,NWELL ++S 0,600,3000,600,1200,vss,RIGHT,CALU1 ++S 1600,3600,1600,5500,200,*,UP,POLY ++S 1200,1900,1200,3400,400,*,DOWN,NDIF ++S 1600,5500,1600,9300,200,1,UP,PTRANS ++S 2200,5700,2200,9100,800,*,DOWN,PDIF ++S 1200,5700,1200,9100,400,*,UP,PDIF ++S 2300,1900,2300,3400,600,*,UP,NDIF ++S 2000,3900,2000,6100,400,*,DOWN,ALU1 ++S 2000,4000,2000,6000,400,a,DOWN,CALU1 ++S 1600,9300,1600,9700,200,*,DOWN,POLY ++S 2200,7900,2200,9300,400,*,UP,ALU1 ++S 2000,7000,2000,7000,400,z,LEFT,CALU1 ++S 1000,7000,2000,7000,600,*,RIGHT,ALU1 ++S 2200,700,2200,3100,400,*,UP,ALU1 ++S 1000,2600,1000,3200,600,*,UP,NDIF ++V 2000,700,CONT_BODY_P,* ++V 1000,700,CONT_BODY_P,* ++V 1000,6600,CONT_DIF_P,* ++V 1000,5800,CONT_DIF_P,* ++V 2000,4700,CONT_POLY,* ++V 2200,2000,CONT_DIF_N,* ++V 1000,3300,CONT_DIF_N,* ++V 2200,9000,CONT_DIF_P,* ++V 2200,8000,CONT_DIF_P,* ++V 2200,3000,CONT_DIF_N,* ++V 1000,2500,CONT_DIF_N,* ++EOF +diff --git a/alliance/src/cells/src/msxlib/iv1_x2.vbe b/alliance/src/cells/src/msxlib/iv1_x2.vbe +new file mode 100644 +index 0000000..0e18871 +--- /dev/null ++++ b/alliance/src/cells/src/msxlib/iv1_x2.vbe +@@ -0,0 +1,26 @@ ++ENTITY iv1_x2 IS ++GENERIC ( ++ CONSTANT area : NATURAL := 3000; ++ CONSTANT cin_a : NATURAL := 6; ++ CONSTANT rdown_a_z : NATURAL := 1200; ++ CONSTANT rup_a_z : NATURAL := 1560; ++ CONSTANT tphl_a_z : NATURAL := 34; ++ CONSTANT tplh_a_z : NATURAL := 38; ++ CONSTANT transistors : NATURAL := 2 ++); ++PORT ( ++ a : in BIT; ++ z : out BIT; ++ vdd : in BIT; ++ vss : in BIT ++); ++END iv1_x2; ++ ++ARCHITECTURE behaviour_data_flow OF iv1_x2 IS ++ ++BEGIN ++ ASSERT ((vdd and not (vss)) = '1') ++ REPORT "power supply is missing on iv1_x2" ++ SEVERITY WARNING; ++ z <= not (a) after 700 ps; ++END; +diff --git a/alliance/src/cells/src/msxlib/iv1_x3.ap b/alliance/src/cells/src/msxlib/iv1_x3.ap +new file mode 100644 +index 0000000..447a9df +--- /dev/null ++++ b/alliance/src/cells/src/msxlib/iv1_x3.ap +@@ -0,0 +1,70 @@ ++V ALLIANCE : 6 ++H iv1_x3,P, 8/ 8/2014,100 ++A 0,0,4000,10000 ++R 3000,6000,ref_ref,a_60 ++R 3000,5000,ref_ref,a_50 ++R 3000,4000,ref_ref,a_40 ++R 2000,5000,ref_ref,a_50 ++R 2000,7000,ref_ref,z_70 ++R 1000,6000,ref_ref,z_60 ++R 1000,4000,ref_ref,z_40 ++R 2000,4000,ref_ref,z_40 ++R 2000,3000,ref_ref,z_30 ++R 2000,6000,ref_ref,z_60 ++R 1000,5000,ref_ref,z_50 ++S 1100,9300,1900,9300,600,*,RIGHT,NTIE ++S 1100,700,1900,700,600,*,LEFT,PTIE ++S 2000,3000,2000,4000,400,z,DOWN,CALU1 ++S 2000,6000,2000,7000,400,z,UP,CALU1 ++S 2000,5000,2000,5000,400,a,LEFT,CALU1 ++S 2000,2700,2000,3700,600,*,UP,NDIF ++S 3300,2700,3300,3700,600,*,UP,NDIF ++S 700,2700,700,3700,600,*,UP,NDIF ++S 1400,8500,1400,8800,200,*,DOWN,POLY ++S 2600,8500,2600,8800,200,*,DOWN,POLY ++S 2000,5800,2000,8200,1000,*,DOWN,PDIF ++S 2600,5600,2600,8400,200,2,UP,PTRANS ++S 1400,5600,1400,8400,200,1,UP,PTRANS ++S 1400,5000,2600,5000,600,*,RIGHT,POLY ++S 0,5000,4000,5000,10000,iv1_x3,LEFT,TALU8 ++S 0,2200,4000,2200,5200,*,LEFT,PWELL ++S 0,7600,4000,7600,5600,*,LEFT,NWELL ++S 0,9400,4000,9400,1200,vdd,RIGHT,CALU1 ++S 0,600,4000,600,1200,vss,RIGHT,CALU1 ++S 1000,4000,2000,4000,600,*,LEFT,ALU1 ++S 1000,6000,2000,6000,600,*,RIGHT,ALU1 ++S 800,6900,800,9300,400,*,UP,ALU1 ++S 800,5800,800,8200,800,*,DOWN,PDIF ++S 3200,5800,3200,8200,800,*,DOWN,PDIF ++S 2600,4100,2600,5600,200,*,UP,POLY ++S 1400,4100,1400,5600,200,*,UP,POLY ++S 3200,700,3200,3100,400,*,DOWN,ALU1 ++S 800,700,800,3100,400,*,DOWN,ALU1 ++S 1900,5000,3000,5000,400,*,RIGHT,ALU1 ++S 1000,4000,1000,6000,400,*,UP,ALU1 ++S 1400,2100,1400,2500,200,*,UP,POLY ++S 1400,2500,1400,3900,200,3,DOWN,NTRANS ++S 2600,2100,2600,2500,200,*,UP,POLY ++S 2600,2500,2600,3900,200,4,DOWN,NTRANS ++S 2000,6000,2000,7100,400,*,UP,ALU1 ++S 3000,3900,3000,6100,400,*,DOWN,ALU1 ++S 3000,4000,3000,6000,400,a,DOWN,CALU1 ++S 3200,6900,3200,9300,400,*,UP,ALU1 ++S 1000,4000,1000,6000,400,z,DOWN,CALU1 ++S 2000,2700,2000,4000,400,*,UP,ALU1 ++V 2000,9300,CONT_BODY_N,* ++V 1000,9300,CONT_BODY_N,* ++V 2000,700,CONT_BODY_P,* ++V 1000,700,CONT_BODY_P,* ++V 2000,7000,CONT_DIF_P,* ++V 2000,6000,CONT_DIF_P,* ++V 2200,5000,CONT_POLY,* ++V 800,7000,CONT_DIF_P,* ++V 800,8000,CONT_DIF_P,* ++V 3200,8000,CONT_DIF_P,* ++V 800,3000,CONT_DIF_N,* ++V 3200,3000,CONT_DIF_N,* ++V 2000,2800,CONT_DIF_N,* ++V 2000,3600,CONT_DIF_N,* ++V 3200,7000,CONT_DIF_P,* ++EOF +diff --git a/alliance/src/cells/src/msxlib/iv1_x3.vbe b/alliance/src/cells/src/msxlib/iv1_x3.vbe +new file mode 100644 +index 0000000..b064273 +--- /dev/null ++++ b/alliance/src/cells/src/msxlib/iv1_x3.vbe +@@ -0,0 +1,26 @@ ++ENTITY iv1_x3 IS ++GENERIC ( ++ CONSTANT area : NATURAL := 4000; ++ CONSTANT cin_a : NATURAL := 9; ++ CONSTANT rdown_a_z : NATURAL := 810; ++ CONSTANT rup_a_z : NATURAL := 1060; ++ CONSTANT tphl_a_z : NATURAL := 33; ++ CONSTANT tplh_a_z : NATURAL := 37; ++ CONSTANT transistors : NATURAL := 4 ++); ++PORT ( ++ a : in BIT; ++ z : out BIT; ++ vdd : in BIT; ++ vss : in BIT ++); ++END iv1_x3; ++ ++ARCHITECTURE behaviour_data_flow OF iv1_x3 IS ++ ++BEGIN ++ ASSERT ((vdd and not (vss)) = '1') ++ REPORT "power supply is missing on iv1_x3" ++ SEVERITY WARNING; ++ z <= not (a) after 700 ps; ++END; +diff --git a/alliance/src/cells/src/msxlib/iv1_x4.ap b/alliance/src/cells/src/msxlib/iv1_x4.ap +new file mode 100644 +index 0000000..da8d69d +--- /dev/null ++++ b/alliance/src/cells/src/msxlib/iv1_x4.ap +@@ -0,0 +1,74 @@ ++V ALLIANCE : 6 ++H iv1_x4,P, 8/ 8/2014,100 ++A 0,0,4000,10000 ++R 2000,2000,ref_ref,z_20 ++R 3000,5000,ref_ref,a_50 ++R 1000,5000,ref_ref,z_50 ++R 2000,6000,ref_ref,z_60 ++R 2000,3000,ref_ref,z_30 ++R 2000,4000,ref_ref,z_40 ++R 1000,4000,ref_ref,z_40 ++R 1000,6000,ref_ref,z_60 ++R 2000,7000,ref_ref,z_70 ++R 2000,5000,ref_ref,a_50 ++R 3000,4000,ref_ref,a_40 ++R 3000,6000,ref_ref,a_60 ++S 1100,700,1900,700,600,*,LEFT,PTIE ++S 2000,2000,2000,4000,400,z,DOWN,CALU1 ++S 2000,6000,2000,7000,400,z,UP,CALU1 ++S 3200,6900,3200,9300,400,*,UP,ALU1 ++S 2000,5000,2000,5000,400,a,LEFT,CALU1 ++S 3000,3900,3000,6100,400,*,UP,ALU1 ++S 3000,4000,3000,6000,400,a,DOWN,CALU1 ++S 2000,6000,2000,7100,400,*,UP,ALU1 ++S 3200,5800,3200,9200,800,*,DOWN,PDIF ++S 800,5800,800,9200,800,*,DOWN,PDIF ++S 1000,6000,2000,6000,600,*,RIGHT,ALU1 ++S 1000,4000,2000,4000,600,*,LEFT,ALU1 ++S 0,600,4000,600,1200,vss,RIGHT,CALU1 ++S 0,9400,4000,9400,1200,vdd,RIGHT,CALU1 ++S 0,5000,4000,5000,10000,iv1_x4,LEFT,TALU8 ++S 0,2200,4000,2200,5200,*,LEFT,PWELL ++S 0,7600,4000,7600,5600,*,LEFT,NWELL ++S 1400,1300,1400,1700,200,*,UP,POLY ++S 2600,1300,2600,1700,200,*,UP,POLY ++S 1400,1700,1400,3600,200,3,DOWN,NTRANS ++S 2600,1700,2600,3600,200,4,DOWN,NTRANS ++S 1400,5000,2600,5000,600,*,RIGHT,POLY ++S 2000,5800,2000,9200,1000,*,DOWN,PDIF ++S 1400,5600,1400,9400,200,1,UP,PTRANS ++S 2600,5600,2600,9400,200,2,UP,PTRANS ++S 1400,9400,1400,9700,200,*,DOWN,POLY ++S 2600,9400,2600,9700,200,*,DOWN,POLY ++S 3300,1900,3300,3400,600,*,UP,NDIF ++S 700,1900,700,3400,600,*,UP,NDIF ++S 2000,1900,2000,3400,600,*,UP,NDIF ++S 800,700,800,3100,400,*,DOWN,ALU1 ++S 3200,700,3200,3100,400,*,DOWN,ALU1 ++S 2600,3600,2600,5600,200,*,UP,POLY ++S 1400,3600,1400,5600,200,*,UP,POLY ++S 800,6900,800,9300,400,*,UP,ALU1 ++S 2000,1900,2000,4000,400,*,UP,ALU1 ++S 1900,5000,3000,5000,400,*,RIGHT,ALU1 ++S 1000,4000,1000,6000,400,*,UP,ALU1 ++S 800,1900,800,3400,600,*,UP,NDIF ++S 3200,1900,3200,3400,600,*,UP,NDIF ++S 1000,4000,1000,6000,400,z,DOWN,CALU1 ++V 2000,700,CONT_BODY_P,* ++V 1000,700,CONT_BODY_P,* ++V 3200,7000,CONT_DIF_P,* ++V 2200,5000,CONT_POLY,* ++V 800,3000,CONT_DIF_N,* ++V 800,2000,CONT_DIF_N,* ++V 3200,2000,CONT_DIF_N,* ++V 3200,3000,CONT_DIF_N,* ++V 2000,6000,CONT_DIF_P,* ++V 2000,7000,CONT_DIF_P,* ++V 2000,2000,CONT_DIF_N,* ++V 2000,3000,CONT_DIF_N,* ++V 800,7000,CONT_DIF_P,* ++V 800,8000,CONT_DIF_P,* ++V 3200,8000,CONT_DIF_P,* ++V 3200,9000,CONT_DIF_P,* ++V 800,9000,CONT_DIF_P,* ++EOF +diff --git a/alliance/src/cells/src/msxlib/iv1_x4.vbe b/alliance/src/cells/src/msxlib/iv1_x4.vbe +new file mode 100644 +index 0000000..ddeb12e +--- /dev/null ++++ b/alliance/src/cells/src/msxlib/iv1_x4.vbe +@@ -0,0 +1,26 @@ ++ENTITY iv1_x4 IS ++GENERIC ( ++ CONSTANT area : NATURAL := 4000; ++ CONSTANT cin_a : NATURAL := 12; ++ CONSTANT rdown_a_z : NATURAL := 600; ++ CONSTANT rup_a_z : NATURAL := 780; ++ CONSTANT tphl_a_z : NATURAL := 33; ++ CONSTANT tplh_a_z : NATURAL := 37; ++ CONSTANT transistors : NATURAL := 4 ++); ++PORT ( ++ a : in BIT; ++ z : out BIT; ++ vdd : in BIT; ++ vss : in BIT ++); ++END iv1_x4; ++ ++ARCHITECTURE behaviour_data_flow OF iv1_x4 IS ++ ++BEGIN ++ ASSERT ((vdd and not (vss)) = '1') ++ REPORT "power supply is missing on iv1_x4" ++ SEVERITY WARNING; ++ z <= not (a) after 700 ps; ++END; +diff --git a/alliance/src/cells/src/msxlib/iv1_x8.ap b/alliance/src/cells/src/msxlib/iv1_x8.ap +new file mode 100644 +index 0000000..9c363c1 +--- /dev/null ++++ b/alliance/src/cells/src/msxlib/iv1_x8.ap +@@ -0,0 +1,120 @@ ++V ALLIANCE : 6 ++H iv1_x8,P, 8/ 8/2014,100 ++A 0,0,6000,10000 ++R 5000,4000,ref_ref,a_40 ++R 5000,6000,ref_ref,a_60 ++R 5000,5000,ref_ref,a_50 ++R 4000,2000,ref_ref,z_20 ++R 2000,2000,ref_ref,z_20 ++R 2000,5000,ref_ref,a_50 ++R 2000,7000,ref_ref,z_70 ++R 2000,4000,ref_ref,z_40 ++R 2000,3000,ref_ref,z_30 ++R 2000,6000,ref_ref,z_60 ++R 1000,5000,ref_ref,z_50 ++R 3000,5000,ref_ref,a_50 ++R 3000,6000,ref_ref,z_60 ++R 4000,6000,ref_ref,z_60 ++R 4000,7000,ref_ref,z_70 ++R 4000,5000,ref_ref,a_50 ++R 3000,4000,ref_ref,z_40 ++R 4000,4000,ref_ref,z_40 ++R 4000,3000,ref_ref,z_30 ++R 1000,6000,ref_ref,z_60 ++R 1000,4000,ref_ref,z_40 ++S 2400,700,3200,700,600,*,LEFT,PTIE ++S 5400,700,5400,3100,400,*,DOWN,ALU1 ++S 5000,4000,5000,6000,400,a,DOWN,CALU1 ++S 5000,3900,5000,6100,400,*,DOWN,ALU1 ++S 2000,5000,2000,5000,400,a,LEFT,CALU1 ++S 3000,5000,3000,5000,400,a,LEFT,CALU1 ++S 4000,5000,4000,5000,400,a,LEFT,CALU1 ++S 3000,4000,3000,4000,400,z,LEFT,CALU1 ++S 4000,2000,4000,4000,400,z,DOWN,CALU1 ++S 2000,2000,2000,4000,400,z,DOWN,CALU1 ++S 3000,6000,3000,6000,400,z,LEFT,CALU1 ++S 4000,6000,4000,7000,400,z,UP,CALU1 ++S 2000,6000,2000,7000,400,z,UP,CALU1 ++S 4100,6000,4100,7100,600,*,DOWN,ALU1 ++S 1900,6000,1900,7100,600,*,DOWN,ALU1 ++S 1000,4000,4200,4000,400,*,RIGHT,ALU1 ++S 1000,6000,4200,6000,400,*,LEFT,ALU1 ++S 0,9400,6000,9400,1200,vdd,RIGHT,CALU1 ++S 0,5000,6000,5000,10000,iv1_x8,LEFT,TALU8 ++S 0,2200,6000,2200,5200,*,LEFT,PWELL ++S 0,7600,6000,7600,5600,*,LEFT,NWELL ++S 0,600,6000,600,1200,vss,RIGHT,CALU1 ++S 1200,9400,1200,9700,200,*,DOWN,POLY ++S 2400,9400,2400,9700,200,*,DOWN,POLY ++S 3600,9400,3600,9700,200,*,DOWN,POLY ++S 600,6900,600,9300,400,*,UP,ALU1 ++S 3000,6900,3000,9300,400,*,UP,ALU1 ++S 1000,4000,1000,6000,400,*,DOWN,ALU1 ++S 1000,6100,4200,6100,400,*,LEFT,ALU1 ++S 1900,5000,5000,5000,400,*,LEFT,ALU1 ++S 5400,6900,5400,9300,400,*,UP,ALU1 ++S 700,1900,700,3300,800,*,UP,NDIF ++S 1800,1900,1800,3300,1000,*,UP,NDIF ++S 1200,1700,1200,3500,200,5,DOWN,NTRANS ++S 3000,1900,3000,3300,1000,*,UP,NDIF ++S 2400,1700,2400,3500,200,6,DOWN,NTRANS ++S 3600,1700,3600,3500,200,7,DOWN,NTRANS ++S 4200,1900,4200,3300,1000,*,UP,NDIF ++S 4800,1700,4800,3500,200,8,DOWN,NTRANS ++S 5300,1900,5300,3300,800,*,UP,NDIF ++S 600,700,600,3100,400,*,DOWN,ALU1 ++S 1900,1900,1900,4000,600,*,DOWN,ALU1 ++S 4100,1900,4100,4000,600,*,DOWN,ALU1 ++S 3000,700,3000,3100,400,*,DOWN,ALU1 ++S 4800,1300,4800,1700,200,*,UP,POLY ++S 3600,1300,3600,1700,200,*,UP,POLY ++S 2400,1300,2400,1700,200,*,UP,POLY ++S 1200,1300,1200,1700,200,*,UP,POLY ++S 1200,3500,1200,5500,200,*,UP,POLY ++S 2400,3500,2400,5500,200,*,UP,POLY ++S 3600,3500,3600,5500,200,*,UP,POLY ++S 4800,3500,4800,5500,200,*,UP,POLY ++S 1000,3900,4200,3900,400,*,RIGHT,ALU1 ++S 1200,5500,1200,9400,200,1,UP,PTRANS ++S 600,5700,600,9200,600,*,DOWN,PDIF ++S 1800,5700,1800,9200,600,*,DOWN,PDIF ++S 2400,5500,2400,9400,200,2,UP,PTRANS ++S 3600,5500,3600,9400,200,3,UP,PTRANS ++S 3000,5700,3000,9200,600,*,DOWN,PDIF ++S 1200,4900,2400,4900,600,*,RIGHT,POLY ++S 3600,4900,4800,4900,600,*,RIGHT,POLY ++S 1900,4900,5000,4900,400,*,LEFT,ALU1 ++S 5400,5700,5400,8100,600,*,DOWN,PDIF ++S 4800,5500,4800,8300,200,4,UP,PTRANS ++S 4200,5700,4200,8100,600,*,UP,PDIF ++S 4000,8500,4000,9200,400,*,UP,PDIF ++S 4800,8400,4800,8700,200,*,DOWN,POLY ++S 1000,4000,1000,6000,400,z,DOWN,CALU1 ++V 5100,9300,CONT_BODY_N,* ++V 3300,700,CONT_BODY_P,* ++V 2300,700,CONT_BODY_P,* ++V 5400,3000,CONT_DIF_N,* ++V 1800,7000,CONT_DIF_P,* ++V 1800,6000,CONT_DIF_P,* ++V 4200,7000,CONT_DIF_P,* ++V 4200,6000,CONT_DIF_P,* ++V 600,7000,CONT_DIF_P,* ++V 600,8000,CONT_DIF_P,* ++V 600,9000,CONT_DIF_P,* ++V 3000,7000,CONT_DIF_P,* ++V 3000,8000,CONT_DIF_P,* ++V 3000,9000,CONT_DIF_P,* ++V 5400,7000,CONT_DIF_P,* ++V 5400,8000,CONT_DIF_P,* ++V 600,3000,CONT_DIF_N,* ++V 600,2000,CONT_DIF_N,* ++V 3000,3000,CONT_DIF_N,* ++V 3000,2000,CONT_DIF_N,* ++V 1800,2000,CONT_DIF_N,* ++V 1800,3000,CONT_DIF_N,* ++V 4200,3000,CONT_DIF_N,* ++V 4200,2000,CONT_DIF_N,* ++V 5400,2000,CONT_DIF_N,* ++V 2200,4900,CONT_POLY,* ++V 3800,4900,CONT_POLY,* ++EOF +diff --git a/alliance/src/cells/src/msxlib/iv1_x8.vbe b/alliance/src/cells/src/msxlib/iv1_x8.vbe +new file mode 100644 +index 0000000..02c61a0 +--- /dev/null ++++ b/alliance/src/cells/src/msxlib/iv1_x8.vbe +@@ -0,0 +1,26 @@ ++ENTITY iv1_x8 IS ++GENERIC ( ++ CONSTANT area : NATURAL := 6000; ++ CONSTANT cin_a : NATURAL := 22; ++ CONSTANT rdown_a_z : NATURAL := 320; ++ CONSTANT rup_a_z : NATURAL := 410; ++ CONSTANT tphl_a_z : NATURAL := 33; ++ CONSTANT tplh_a_z : NATURAL := 37; ++ CONSTANT transistors : NATURAL := 8 ++); ++PORT ( ++ a : in BIT; ++ z : out BIT; ++ vdd : in BIT; ++ vss : in BIT ++); ++END iv1_x8; ++ ++ARCHITECTURE behaviour_data_flow OF iv1_x8 IS ++ ++BEGIN ++ ASSERT ((vdd and not (vss)) = '1') ++ REPORT "power supply is missing on iv1_x8" ++ SEVERITY WARNING; ++ z <= not (a) after 700 ps; ++END; +diff --git a/alliance/src/cells/src/msxlib/iv1_y2.ap b/alliance/src/cells/src/msxlib/iv1_y2.ap +new file mode 100644 +index 0000000..7df6e39 +--- /dev/null ++++ b/alliance/src/cells/src/msxlib/iv1_y2.ap +@@ -0,0 +1,50 @@ ++V ALLIANCE : 6 ++H iv1_y2,P, 8/ 8/2014,100 ++A 0,0,3000,10000 ++R 1000,2000,ref_ref,z_20 ++R 1000,5000,ref_ref,z_50 ++R 1000,4000,ref_ref,z_40 ++R 1000,6000,ref_ref,z_60 ++R 2000,5000,ref_ref,a_50 ++R 2000,6000,ref_ref,a_60 ++R 1000,7000,ref_ref,z_70 ++R 2000,4000,ref_ref,a_40 ++R 1000,3000,ref_ref,z_30 ++R 2000,7000,ref_ref,z_70 ++S 1100,700,1900,700,600,*,RIGHT,PTIE ++S 2000,3900,2000,6100,400,*,DOWN,ALU1 ++S 2000,4000,2000,6000,400,a,DOWN,CALU1 ++S 1000,2300,1000,2900,600,*,UP,NDIF ++S 1600,1300,1600,1700,200,*,UP,POLY ++S 1600,3300,1600,5500,200,*,UP,POLY ++S 2300,1900,2300,3100,600,*,UP,NDIF ++S 1600,1700,1600,3300,200,2,DOWN,NTRANS ++S 1200,1900,1200,3100,400,*,DOWN,NDIF ++S 1200,5900,1200,9100,400,*,UP,PDIF ++S 1600,5700,1600,9300,200,1,UP,PTRANS ++S 2200,5900,2200,9100,800,*,DOWN,PDIF ++S 1600,9300,1600,9700,200,*,DOWN,POLY ++S 1000,2000,1000,7000,400,z,DOWN,CALU1 ++S 1000,1900,1000,7100,400,*,UP,ALU1 ++S 0,9400,3000,9400,1200,vdd,RIGHT,CALU1 ++S 0,5000,3000,5000,10000,iv1_y2,LEFT,TALU8 ++S 0,2200,3000,2200,5200,*,LEFT,PWELL ++S 0,7600,3000,7600,5600,*,LEFT,NWELL ++S 0,600,3000,600,1200,vss,RIGHT,CALU1 ++S 1000,6100,1000,6700,600,*,UP,PDIF ++S 2200,7900,2200,9300,400,*,UP,ALU1 ++S 2000,7000,2000,7000,400,z,LEFT,CALU1 ++S 1000,7000,2000,7000,600,*,RIGHT,ALU1 ++S 2200,700,2200,3100,400,*,UP,ALU1 ++V 2000,700,CONT_BODY_P,* ++V 1000,700,CONT_BODY_P,* ++V 1000,2200,CONT_DIF_N,* ++V 1000,3000,CONT_DIF_N,* ++V 1000,6000,CONT_DIF_P,* ++V 2000,4700,CONT_POLY,* ++V 2200,2000,CONT_DIF_N,* ++V 2200,9000,CONT_DIF_P,* ++V 2200,8000,CONT_DIF_P,* ++V 1000,6800,CONT_DIF_P,* ++V 2200,3000,CONT_DIF_N,* ++EOF +diff --git a/alliance/src/cells/src/msxlib/iv1_y2.vbe b/alliance/src/cells/src/msxlib/iv1_y2.vbe +new file mode 100644 +index 0000000..db20bd0 +--- /dev/null ++++ b/alliance/src/cells/src/msxlib/iv1_y2.vbe +@@ -0,0 +1,26 @@ ++ENTITY iv1_y2 IS ++GENERIC ( ++ CONSTANT area : NATURAL := 3000; ++ CONSTANT cin_a : NATURAL := 5; ++ CONSTANT rdown_a_z : NATURAL := 1420; ++ CONSTANT rup_a_z : NATURAL := 1640; ++ CONSTANT tphl_a_z : NATURAL := 36; ++ CONSTANT tplh_a_z : NATURAL := 38; ++ CONSTANT transistors : NATURAL := 2 ++); ++PORT ( ++ a : in BIT; ++ z : out BIT; ++ vdd : in BIT; ++ vss : in BIT ++); ++END iv1_y2; ++ ++ARCHITECTURE behaviour_data_flow OF iv1_y2 IS ++ ++BEGIN ++ ASSERT ((vdd and not (vss)) = '1') ++ REPORT "power supply is missing on iv1_y2" ++ SEVERITY WARNING; ++ z <= not (a) after 700 ps; ++END; +diff --git a/alliance/src/cells/src/msxlib/mxi2_x05.ap b/alliance/src/cells/src/msxlib/mxi2_x05.ap +new file mode 100644 +index 0000000..618a5c1 +--- /dev/null ++++ b/alliance/src/cells/src/msxlib/mxi2_x05.ap +@@ -0,0 +1,136 @@ ++V ALLIANCE : 6 ++H mxi2_x05,P, 8/ 8/2014,100 ++A 0,0,7000,10000 ++R 3000,2000,ref_ref,z_20 ++R 1000,5000,ref_ref,s_50 ++R 1000,6000,ref_ref,s_60 ++R 1000,7000,ref_ref,s_70 ++R 2000,7000,ref_ref,s_70 ++R 3000,7000,ref_ref,s_70 ++R 4000,7000,ref_ref,s_70 ++R 5000,7000,ref_ref,s_70 ++R 1000,4000,ref_ref,a1_40 ++R 2000,4000,ref_ref,a1_40 ++R 2000,5000,ref_ref,a1_50 ++R 3000,5000,ref_ref,a1_50 ++R 2000,6000,ref_ref,a1_60 ++R 3000,6000,ref_ref,z_60 ++R 4000,6000,ref_ref,z_60 ++R 4000,2000,ref_ref,z_20 ++R 3000,4000,ref_ref,a0_40 ++R 3000,3000,ref_ref,a0_30 ++R 2000,3000,ref_ref,a0_30 ++R 1000,3000,ref_ref,a0_30 ++R 1000,2000,ref_ref,a0_30 ++R 5000,6000,ref_ref,s_60 ++R 5000,5000,ref_ref,s_50 ++R 4000,3000,ref_ref,z_30 ++R 4000,4000,ref_ref,z_40 ++R 4000,5000,ref_ref,z_50 ++S 1100,9300,1900,9300,600,*,RIGHT,NTIE ++S 2100,700,2900,700,600,*,RIGHT,PTIE ++S 0,600,7000,600,1200,vss,RIGHT,CALU1 ++S 0,9400,7000,9400,1200,vdd,RIGHT,CALU1 ++S 0,5000,7000,5000,10000,mxi2_x05,LEFT,TALU8 ++S 0,2200,7000,2200,5200,*,LEFT,PWELL ++S 0,7600,7000,7600,5600,*,LEFT,NWELL ++S 900,4000,2000,4000,600,*,RIGHT,ALU1 ++S 1000,3000,3000,3000,400,*,LEFT,ALU1 ++S 1000,4900,1000,7000,600,*,UP,ALU1 ++S 2000,3900,2000,6100,400,*,UP,ALU1 ++S 1000,7900,1000,9300,400,*,UP,ALU1 ++S 5000,7900,5000,9300,400,*,UP,ALU1 ++S 6400,6000,6400,6600,600,*,UP,PDIF ++S 1000,5000,1600,5000,600,*,RIGHT,POLY ++S 2000,5000,3200,5000,600,*,RIGHT,ALU1 ++S 4000,2000,4000,6000,400,*,DOWN,ALU1 ++S 2500,2000,4000,2000,400,*,LEFT,ALU1 ++S 3000,6000,4000,6000,600,*,RIGHT,ALU1 ++S 2500,1900,4000,1900,400,*,LEFT,ALU1 ++S 2400,4200,2400,5600,200,*,DOWN,POLY ++S 2400,4200,3000,4200,200,*,RIGHT,POLY ++S 3200,5000,3600,5000,600,*,RIGHT,POLY ++S 1000,2000,1000,3000,600,*,DOWN,ALU1 ++S 3000,3000,3000,4100,600,*,DOWN,ALU1 ++S 5000,4900,5000,7000,600,*,DOWN,ALU1 ++S 1000,7000,5100,7000,400,*,RIGHT,ALU1 ++S 4900,5000,5500,5000,600,*,RIGHT,ALU1 ++S 1000,2000,1000,3000,400,a0,UP,CALU1 ++S 2000,3000,2000,3000,400,a0,LEFT,CALU1 ++S 3000,3000,3000,4000,400,a0,UP,CALU1 ++S 4000,2000,4000,6000,400,z,UP,CALU1 ++S 3000,2000,3000,2000,400,z,LEFT,CALU1 ++S 3000,6000,3000,6000,400,z,LEFT,CALU1 ++S 2000,4000,2000,6000,400,a1,UP,CALU1 ++S 1000,4000,1000,4000,400,a1,LEFT,CALU1 ++S 3000,5000,3000,5000,400,a1,LEFT,CALU1 ++S 1000,5000,1000,7000,400,s,UP,CALU1 ++S 5000,5000,5000,7000,400,s,DOWN,CALU1 ++S 2000,7000,2000,7000,400,s,LEFT,CALU1 ++S 3000,7000,3000,7000,400,s,LEFT,CALU1 ++S 4000,7000,4000,7000,400,s,LEFT,CALU1 ++S 3600,5600,3600,7600,200,4,DOWN,PTRANS ++S 3000,5800,3000,7400,600,*,UP,PDIF ++S 2400,5600,2400,7600,200,3,DOWN,PTRANS ++S 2000,5800,2000,7400,400,n1,UP,PDIF ++S 1600,5600,1600,7600,200,1,DOWN,PTRANS ++S 4400,5600,4400,7600,200,2,DOWN,PTRANS ++S 4000,5800,4000,7400,400,n2,UP,PDIF ++S 900,5800,900,8100,600,*,DOWN,PDIF ++S 1000,5800,1000,8100,600,*,DOWN,PDIF ++S 1600,7600,1600,8000,200,*,UP,POLY ++S 2400,7600,2400,8000,200,*,UP,POLY ++S 3600,7600,3600,8000,200,*,UP,POLY ++S 4400,7600,4400,8000,200,*,UP,POLY ++S 5100,5800,5100,8100,800,*,DOWN,PDIF ++S 5800,5600,5800,7400,200,1s,DOWN,PTRANS ++S 6200,5800,6200,7200,400,*,DOWN,PDIF ++S 5800,7400,5800,7800,200,*,UP,POLY ++S 1800,3500,1800,4900,200,*,UP,POLY ++S 2600,1900,2600,2400,1000,*,UP,NDIF ++S 3200,1700,3200,2600,200,8,UP,NTRANS ++S 2000,1700,2000,2600,200,7,UP,NTRANS ++S 3600,1900,3600,2400,600,n4,UP,NDIF ++S 4000,1700,4000,2600,200,6,UP,NTRANS ++S 1600,1900,1600,2400,600,n3,UP,NDIF ++S 1200,1700,1200,2600,200,5,UP,NTRANS ++S 600,800,600,2400,600,*,UP,NDIF ++S 4900,1900,4900,2400,1200,*,UP,NDIF ++S 4000,1300,4000,1700,200,*,DOWN,POLY ++S 3200,1300,3200,1700,200,*,DOWN,POLY ++S 2000,1300,2000,1700,200,*,DOWN,POLY ++S 1200,1300,1200,1700,200,*,DOWN,POLY ++S 5800,1300,5800,1700,200,*,DOWN,POLY ++S 5800,1700,5800,2600,200,2s,UP,NTRANS ++S 6200,1900,6200,2400,400,*,UP,NDIF ++S 6400,2200,6400,6800,400,*,DOWN,ALU1 ++S 5800,2600,5800,5200,200,*,UP,POLY ++S 5000,700,5000,2100,400,*,DOWN,ALU1 ++S 4800,3400,6400,3400,400,*,RIGHT,ALU1 ++S 4400,3400,5000,3400,600,*,LEFT,POLY ++S 4000,3200,5000,3200,200,*,RIGHT,POLY ++S 4400,3200,4400,5600,200,*,DOWN,POLY ++S 4000,2600,4000,3200,200,*,UP,POLY ++S 3200,2600,3200,4000,200,*,UP,POLY ++S 2000,2600,2000,3600,200,*,UP,POLY ++S 1200,2600,1200,4000,200,*,UP,POLY ++V 2000,9300,CONT_BODY_N,* ++V 1000,9300,CONT_BODY_N,* ++V 3000,700,CONT_BODY_P,* ++V 2000,700,CONT_BODY_P,* ++V 600,900,CONT_DIF_N,* ++V 3000,4000,CONT_POLY,* ++V 1000,4000,CONT_POLY,* ++V 2600,2000,CONT_DIF_N,* ++V 1000,8000,CONT_DIF_P,* ++V 3000,6000,CONT_DIF_P,* ++V 5000,8000,CONT_DIF_P,* ++V 3200,5000,CONT_POLY,* ++V 1100,5000,CONT_POLY,* ++V 5400,5000,CONT_POLY,* ++V 6400,5900,CONT_DIF_P,sn ++V 6400,6700,CONT_DIF_P,sn ++V 5000,2000,CONT_DIF_N,* ++V 6400,2300,CONT_DIF_N,sn ++V 4900,3400,CONT_POLY,sn ++EOF +diff --git a/alliance/src/cells/src/msxlib/mxi2_x05.vbe b/alliance/src/cells/src/msxlib/mxi2_x05.vbe +new file mode 100644 +index 0000000..1d94014 +--- /dev/null ++++ b/alliance/src/cells/src/msxlib/mxi2_x05.vbe +@@ -0,0 +1,40 @@ ++ENTITY mxi2_x05 IS ++GENERIC ( ++ CONSTANT area : NATURAL := 7000; ++ CONSTANT cin_s : NATURAL := 8; ++ CONSTANT cin_a0 : NATURAL := 4; ++ CONSTANT cin_a1 : NATURAL := 4; ++ CONSTANT rdown_s_z : NATURAL := 4090; ++ CONSTANT rdown_a0_z : NATURAL := 4100; ++ CONSTANT rdown_a1_z : NATURAL := 4110; ++ CONSTANT rup_s_z : NATURAL := 5780; ++ CONSTANT rup_a0_z : NATURAL := 5850; ++ CONSTANT rup_a1_z : NATURAL := 5840; ++ CONSTANT tphl_a0_z : NATURAL := 54; ++ CONSTANT tphl_a1_z : NATURAL := 54; ++ CONSTANT tphl_s_z : NATURAL := 58; ++ CONSTANT tplh_a0_z : NATURAL := 58; ++ CONSTANT tplh_a1_z : NATURAL := 69; ++ CONSTANT tplh_s_z : NATURAL := 66; ++ CONSTANT tphh_s_z : NATURAL := 101; ++ CONSTANT tpll_s_z : NATURAL := 97; ++ CONSTANT transistors : NATURAL := 10 ++); ++PORT ( ++ s : in BIT; ++ a0 : in BIT; ++ a1 : in BIT; ++ z : out BIT; ++ vdd : in BIT; ++ vss : in BIT ++); ++END mxi2_x05; ++ ++ARCHITECTURE behaviour_data_flow OF mxi2_x05 IS ++ ++BEGIN ++ ASSERT ((vdd and not (vss)) = '1') ++ REPORT "power supply is missing on mxi2_x05" ++ SEVERITY WARNING; ++ z <= not (((a0 and not (s)) or (a1 and s))) after 1000 ps; ++END; +diff --git a/alliance/src/cells/src/msxlib/mxi2_x1.ap b/alliance/src/cells/src/msxlib/mxi2_x1.ap +new file mode 100644 +index 0000000..35332b1 +--- /dev/null ++++ b/alliance/src/cells/src/msxlib/mxi2_x1.ap +@@ -0,0 +1,134 @@ ++V ALLIANCE : 6 ++H mxi2_x1,P, 8/ 8/2014,100 ++A 0,0,7000,10000 ++R 3000,2000,ref_ref,z_20 ++R 1000,5000,ref_ref,s_50 ++R 1000,6000,ref_ref,s_60 ++R 1000,7000,ref_ref,s_70 ++R 2000,7000,ref_ref,s_70 ++R 3000,7000,ref_ref,s_70 ++R 4000,7000,ref_ref,s_70 ++R 5000,7000,ref_ref,s_70 ++R 1000,4000,ref_ref,a1_40 ++R 2000,4000,ref_ref,a1_40 ++R 2000,5000,ref_ref,a1_50 ++R 3000,5000,ref_ref,a1_50 ++R 2000,6000,ref_ref,a1_60 ++R 3000,6000,ref_ref,z_60 ++R 4000,6000,ref_ref,z_60 ++R 4000,2000,ref_ref,z_20 ++R 3000,4000,ref_ref,a0_40 ++R 3000,3000,ref_ref,a0_30 ++R 2000,3000,ref_ref,a0_30 ++R 1000,3000,ref_ref,a0_30 ++R 1000,2000,ref_ref,a0_30 ++R 5000,6000,ref_ref,s_60 ++R 5000,5000,ref_ref,s_50 ++R 4000,3000,ref_ref,z_30 ++R 4000,4000,ref_ref,z_40 ++R 4000,5000,ref_ref,z_50 ++S 4400,3800,4400,5600,200,*,DOWN,POLY ++S 0,600,7000,600,1200,vss,RIGHT,CALU1 ++S 0,9400,7000,9400,1200,vdd,RIGHT,CALU1 ++S 0,5000,7000,5000,10000,mxi2_x1,LEFT,TALU8 ++S 0,2200,7000,2200,5200,*,LEFT,PWELL ++S 0,7600,7000,7600,5600,*,LEFT,NWELL ++S 5800,3400,5800,5200,200,*,UP,POLY ++S 900,4000,2000,4000,600,*,RIGHT,ALU1 ++S 1000,3000,3000,3000,400,*,LEFT,ALU1 ++S 5200,5800,5200,9200,600,*,DOWN,PDIF ++S 6200,5800,6200,7800,400,*,DOWN,PDIF ++S 5800,8000,5800,8400,200,*,UP,POLY ++S 1000,4900,1000,7000,600,*,UP,ALU1 ++S 2000,3900,2000,6100,400,*,UP,ALU1 ++S 1000,7900,1000,9300,400,*,UP,ALU1 ++S 1600,5600,1600,9400,200,1,DOWN,PTRANS ++S 900,5800,900,9200,600,*,DOWN,PDIF ++S 2400,5600,2400,9400,200,3,DOWN,PTRANS ++S 3600,5600,3600,9400,200,4,DOWN,PTRANS ++S 3000,5800,3000,9200,600,*,UP,PDIF ++S 4400,5600,4400,9400,200,2,DOWN,PTRANS ++S 5000,7900,5000,9300,400,*,UP,ALU1 ++S 1600,9400,1600,9700,200,*,UP,POLY ++S 2400,9400,2400,9700,200,*,UP,POLY ++S 3600,9400,3600,9700,200,*,UP,POLY ++S 4400,9400,4400,9700,200,*,UP,POLY ++S 6400,6000,6400,6600,600,*,UP,PDIF ++S 1000,5000,1600,5000,600,*,RIGHT,POLY ++S 2000,5000,3200,5000,600,*,RIGHT,ALU1 ++S 4000,2000,4000,6000,400,*,DOWN,ALU1 ++S 2500,2000,4000,2000,400,*,LEFT,ALU1 ++S 3000,6000,4000,6000,600,*,RIGHT,ALU1 ++S 2500,1900,4000,1900,400,*,LEFT,ALU1 ++S 2400,4200,2400,5600,200,*,DOWN,POLY ++S 2400,4200,3000,4200,200,*,RIGHT,POLY ++S 3200,5000,3600,5000,600,*,RIGHT,POLY ++S 1000,2000,1000,3000,600,*,DOWN,ALU1 ++S 3000,3000,3000,4100,600,*,DOWN,ALU1 ++S 5000,4900,5000,7000,600,*,DOWN,ALU1 ++S 1000,7000,5100,7000,400,*,RIGHT,ALU1 ++S 4900,5000,5500,5000,600,*,RIGHT,ALU1 ++S 5800,5600,5800,8000,200,1s,DOWN,PTRANS ++S 2000,5800,2000,9200,400,n1,UP,PDIF ++S 4000,5800,4000,9200,400,n2,UP,PDIF ++S 1000,2000,1000,3000,400,a0,UP,CALU1 ++S 2000,3000,2000,3000,400,a0,LEFT,CALU1 ++S 3000,3000,3000,4000,400,a0,UP,CALU1 ++S 4000,2000,4000,6000,400,z,UP,CALU1 ++S 3000,2000,3000,2000,400,z,LEFT,CALU1 ++S 3000,6000,3000,6000,400,z,LEFT,CALU1 ++S 2000,4000,2000,6000,400,a1,UP,CALU1 ++S 1000,4000,1000,4000,400,a1,LEFT,CALU1 ++S 3000,5000,3000,5000,400,a1,LEFT,CALU1 ++S 1000,5000,1000,7000,400,s,UP,CALU1 ++S 5000,5000,5000,7000,400,s,DOWN,CALU1 ++S 2000,7000,2000,7000,400,s,LEFT,CALU1 ++S 3000,7000,3000,7000,400,s,LEFT,CALU1 ++S 4000,7000,4000,7000,400,s,LEFT,CALU1 ++S 1800,3500,1800,4900,200,*,UP,POLY ++S 1600,1600,1600,2900,600,n3,UP,NDIF ++S 2000,1400,2000,3100,200,7,UP,NTRANS ++S 1200,1400,1200,3100,200,5,UP,NTRANS ++S 2600,1600,2600,2900,1000,*,UP,NDIF ++S 3200,1400,3200,3100,200,8,UP,NTRANS ++S 3600,1600,3600,2900,600,n4,UP,NDIF ++S 4000,1400,4000,3100,200,6,UP,NTRANS ++S 4000,1000,4000,1400,200,*,DOWN,POLY ++S 3200,1000,3200,1400,200,*,DOWN,POLY ++S 2000,1000,2000,1400,200,*,DOWN,POLY ++S 1200,1000,1200,1400,200,*,DOWN,POLY ++S 600,890,600,2900,600,*,UP,NDIF ++S 6200,2100,6200,2900,400,*,UP,NDIF ++S 4900,1600,4900,2900,1200,*,UP,NDIF ++S 5000,700,5000,2900,400,*,DOWN,ALU1 ++S 6400,2700,6400,6800,400,*,DOWN,ALU1 ++S 5800,1900,5800,3100,200,2s,UP,NTRANS ++S 5800,1500,5800,1900,200,*,DOWN,POLY ++S 4800,3800,6400,3800,400,*,RIGHT,ALU1 ++S 4400,3800,5000,3800,600,*,LEFT,POLY ++S 4000,3600,5000,3600,200,*,RIGHT,POLY ++S 4000,3100,4000,3600,200,*,UP,POLY ++S 3200,3100,3200,4000,200,*,UP,POLY ++S 2000,3100,2000,3600,200,*,UP,POLY ++S 1200,3100,1200,4000,200,*,UP,POLY ++V 6300,9300,CONT_BODY_N,* ++V 6300,700,CONT_BODY_P,* ++V 600,900,CONT_DIF_N,* ++V 3000,4000,CONT_POLY,* ++V 1000,4000,CONT_POLY,* ++V 2600,2000,CONT_DIF_N,* ++V 1000,8000,CONT_DIF_P,* ++V 3000,6000,CONT_DIF_P,* ++V 5000,8000,CONT_DIF_P,* ++V 5000,9000,CONT_DIF_P,* ++V 1000,9000,CONT_DIF_P,* ++V 3200,5000,CONT_POLY,* ++V 1100,5000,CONT_POLY,* ++V 5400,5000,CONT_POLY,* ++V 6400,5900,CONT_DIF_P,sn ++V 6400,6700,CONT_DIF_P,sn ++V 5000,2000,CONT_DIF_N,* ++V 5000,2800,CONT_DIF_N,* ++V 6400,2800,CONT_DIF_N,sn ++V 4900,3800,CONT_POLY,sn ++EOF +diff --git a/alliance/src/cells/src/msxlib/mxi2_x1.vbe b/alliance/src/cells/src/msxlib/mxi2_x1.vbe +new file mode 100644 +index 0000000..9867123 +--- /dev/null ++++ b/alliance/src/cells/src/msxlib/mxi2_x1.vbe +@@ -0,0 +1,40 @@ ++ENTITY mxi2_x1 IS ++GENERIC ( ++ CONSTANT area : NATURAL := 7000; ++ CONSTANT cin_s : NATURAL := 11; ++ CONSTANT cin_a0 : NATURAL := 6; ++ CONSTANT cin_a1 : NATURAL := 6; ++ CONSTANT rdown_s_z : NATURAL := 2170; ++ CONSTANT rdown_a0_z : NATURAL := 2170; ++ CONSTANT rdown_a1_z : NATURAL := 2180; ++ CONSTANT rup_s_z : NATURAL := 3040; ++ CONSTANT rup_a0_z : NATURAL := 3080; ++ CONSTANT rup_a1_z : NATURAL := 3070; ++ CONSTANT tphl_a0_z : NATURAL := 51; ++ CONSTANT tphl_a1_z : NATURAL := 51; ++ CONSTANT tphl_s_z : NATURAL := 55; ++ CONSTANT tplh_a0_z : NATURAL := 54; ++ CONSTANT tplh_a1_z : NATURAL := 65; ++ CONSTANT tplh_s_z : NATURAL := 62; ++ CONSTANT tphh_s_z : NATURAL := 101; ++ CONSTANT tpll_s_z : NATURAL := 99; ++ CONSTANT transistors : NATURAL := 10 ++); ++PORT ( ++ s : in BIT; ++ a0 : in BIT; ++ a1 : in BIT; ++ z : out BIT; ++ vdd : in BIT; ++ vss : in BIT ++); ++END mxi2_x1; ++ ++ARCHITECTURE behaviour_data_flow OF mxi2_x1 IS ++ ++BEGIN ++ ASSERT ((vdd and not (vss)) = '1') ++ REPORT "power supply is missing on mxi2_x1" ++ SEVERITY WARNING; ++ z <= not (((a0 and not (s)) or (a1 and s))) after 1000 ps; ++END; +diff --git a/alliance/src/cells/src/msxlib/nd2_x05.ap b/alliance/src/cells/src/msxlib/nd2_x05.ap +new file mode 100644 +index 0000000..930e7fb +--- /dev/null ++++ b/alliance/src/cells/src/msxlib/nd2_x05.ap +@@ -0,0 +1,72 @@ ++V ALLIANCE : 6 ++H nd2_x05,P, 8/ 8/2014,100 ++A 0,0,4000,10000 ++R 2000,6000,ref_ref,a_60 ++R 3000,5000,ref_ref,a_50 ++R 2000,5000,ref_ref,b_50 ++R 2000,7000,ref_ref,z_70 ++R 1000,6000,ref_ref,z_60 ++R 1000,5000,ref_ref,z_50 ++R 1000,4000,ref_ref,z_40 ++R 1000,3000,ref_ref,z_30 ++R 3000,4000,ref_ref,b_40 ++R 3000,6000,ref_ref,a_60 ++R 2000,4000,ref_ref,b_40 ++R 1000,7000,ref_ref,z_70 ++S 1100,700,1900,700,600,*,RIGHT,PTIE ++S 1100,9300,1900,9300,600,*,RIGHT,NTIE ++S 3000,4000,3000,4000,400,b,LEFT,CALU1 ++S 2000,7000,2000,7400,600,*,DOWN,ALU1 ++S 700,7300,700,8100,800,*,DOWN,PDIF ++S 3300,7300,3300,8100,800,*,DOWN,PDIF ++S 1400,7100,1400,8300,200,1,UP,PTRANS ++S 2000,7300,2000,8100,1000,*,DOWN,PDIF ++S 2600,7100,2600,8300,200,2,UP,PTRANS ++S 1400,4500,1400,7200,200,*,DOWN,POLY ++S 2600,6000,2600,7200,200,*,DOWN,POLY ++S 3000,5000,3000,6000,400,a,DOWN,CALU1 ++S 3000,4900,3000,6100,400,*,DOWN,ALU1 ++S 2000,6000,3000,6000,600,*,RIGHT,ALU1 ++S 2800,2300,2800,2700,200,*,UP,POLY ++S 2000,2300,2000,2700,200,*,UP,POLY ++S 2000,3700,2000,4300,200,*,UP,POLY ++S 2800,3700,2800,6000,200,*,UP,POLY ++S 3400,2900,3400,3500,600,*,UP,NDIF ++S 1600,2900,1600,3500,400,*,UP,NDIF ++S 2000,2700,2000,3700,200,3,DOWN,NTRANS ++S 2800,2700,2800,3700,200,4,DOWN,NTRANS ++S 2400,2900,2400,3500,600,n1,UP,NDIF ++S 3400,700,3400,3100,400,*,DOWN,ALU1 ++S 1500,4500,1700,4500,200,*,RIGHT,POLY ++S 2000,7000,2000,7000,400,z,LEFT,CALU1 ++S 2000,6000,2000,6000,400,a,LEFT,CALU1 ++S 2000,4000,3000,4000,600,*,LEFT,ALU1 ++S 1000,7000,2100,7000,400,*,RIGHT,ALU1 ++S 0,600,4000,600,1200,vss,RIGHT,CALU1 ++S 0,9400,4000,9400,1200,vdd,RIGHT,CALU1 ++S 0,5000,4000,5000,10000,nd2_x05,LEFT,TALU8 ++S 0,2200,4000,2200,5200,*,LEFT,PWELL ++S 0,7600,4000,7600,5600,*,LEFT,NWELL ++S 1000,2900,1500,2900,400,*,RIGHT,ALU1 ++S 1000,3000,1500,3000,400,*,RIGHT,ALU1 ++S 2000,4000,2000,5100,400,*,UP,ALU1 ++S 2000,4000,2000,5000,400,b,DOWN,CALU1 ++S 1000,3000,1000,7000,400,z,DOWN,CALU1 ++S 1000,2900,1000,7000,400,*,DOWN,ALU1 ++S 1000,7100,2100,7100,400,*,RIGHT,ALU1 ++S 800,7900,800,9300,400,*,UP,ALU1 ++S 3200,7900,3200,9300,400,*,UP,ALU1 ++S 1400,8300,1400,8700,200,*,DOWN,POLY ++S 2600,8300,2600,8700,200,*,DOWN,POLY ++V 2000,700,CONT_BODY_P,* ++V 1000,700,CONT_BODY_P,* ++V 2000,9300,CONT_BODY_N,* ++V 1000,9300,CONT_BODY_N,* ++V 2000,7400,CONT_DIF_P,* ++V 3400,3000,CONT_DIF_N,* ++V 2000,4300,CONT_POLY,* ++V 1400,3000,CONT_DIF_N,* ++V 800,8000,CONT_DIF_P,* ++V 3200,8000,CONT_DIF_P,* ++V 2800,6000,CONT_POLY,* ++EOF +diff --git a/alliance/src/cells/src/msxlib/nd2_x05.vbe b/alliance/src/cells/src/msxlib/nd2_x05.vbe +new file mode 100644 +index 0000000..fa5b61e +--- /dev/null ++++ b/alliance/src/cells/src/msxlib/nd2_x05.vbe +@@ -0,0 +1,32 @@ ++ENTITY nd2_x05 IS ++GENERIC ( ++ CONSTANT area : NATURAL := 4000; ++ CONSTANT cin_a : NATURAL := 3; ++ CONSTANT cin_b : NATURAL := 3; ++ CONSTANT rdown_a_z : NATURAL := 3680; ++ CONSTANT rdown_b_z : NATURAL := 3680; ++ CONSTANT rup_a_z : NATURAL := 4930; ++ CONSTANT rup_b_z : NATURAL := 4940; ++ CONSTANT tphl_a_z : NATURAL := 35; ++ CONSTANT tphl_b_z : NATURAL := 36; ++ CONSTANT tplh_b_z : NATURAL := 46; ++ CONSTANT tplh_a_z : NATURAL := 52; ++ CONSTANT transistors : NATURAL := 4 ++); ++PORT ( ++ a : in BIT; ++ b : in BIT; ++ z : out BIT; ++ vdd : in BIT; ++ vss : in BIT ++); ++END nd2_x05; ++ ++ARCHITECTURE behaviour_data_flow OF nd2_x05 IS ++ ++BEGIN ++ ASSERT ((vdd and not (vss)) = '1') ++ REPORT "power supply is missing on nd2_x05" ++ SEVERITY WARNING; ++ z <= not ((a and b)) after 900 ps; ++END; +diff --git a/alliance/src/cells/src/msxlib/nd2_x1.ap b/alliance/src/cells/src/msxlib/nd2_x1.ap +new file mode 100644 +index 0000000..99a3aa2 +--- /dev/null ++++ b/alliance/src/cells/src/msxlib/nd2_x1.ap +@@ -0,0 +1,75 @@ ++V ALLIANCE : 6 ++H nd2_x1,P, 8/ 8/2014,100 ++A 0,0,4000,10000 ++R 2000,4000,ref_ref,b_40 ++R 1000,3000,ref_ref,z_30 ++R 1000,4000,ref_ref,z_40 ++R 1000,5000,ref_ref,z_50 ++R 1000,6000,ref_ref,z_60 ++R 3000,4000,ref_ref,a_40 ++R 2000,7000,ref_ref,z_70 ++R 2000,6000,ref_ref,z_60 ++R 2000,5000,ref_ref,b_50 ++R 3000,5000,ref_ref,b_50 ++R 3000,3000,ref_ref,a_30 ++R 2000,3000,ref_ref,a_30 ++R 1000,2000,ref_ref,z_20 ++S 1100,700,1900,700,600,*,RIGHT,PTIE ++S 1100,9300,1900,9300,600,*,RIGHT,NTIE ++S 2000,3000,3000,3000,600,*,LEFT,ALU1 ++S 0,5000,4000,5000,10000,nd2_x1,LEFT,TALU8 ++S 0,2200,4000,2200,5200,*,LEFT,PWELL ++S 0,7600,4000,7600,5600,*,LEFT,NWELL ++S 0,9400,4000,9400,1200,vdd,RIGHT,CALU1 ++S 0,600,4000,600,1200,vss,RIGHT,CALU1 ++S 1400,7700,1400,8000,200,*,DOWN,POLY ++S 1400,5600,1400,7600,200,1,UP,PTRANS ++S 2000,5800,2000,7400,1000,*,DOWN,PDIF ++S 2600,7700,2600,8000,200,*,DOWN,POLY ++S 2600,5600,2600,7600,200,2,UP,PTRANS ++S 1000,6000,2000,6000,600,*,LEFT,ALU1 ++S 2000,6000,2000,7100,400,*,UP,ALU1 ++S 2000,6000,2000,7000,400,z,UP,CALU1 ++S 3200,5900,3200,9300,400,*,UP,ALU1 ++S 800,6900,800,9300,400,*,UP,ALU1 ++S 3300,5800,3300,7400,600,*,DOWN,PDIF ++S 700,5800,700,7400,600,*,DOWN,PDIF ++S 1000,2300,1000,2900,600,*,UP,NDIF ++S 1200,1800,1200,3100,400,*,UP,NDIF ++S 2000,1800,2000,3100,600,n1,UP,NDIF ++S 1600,1600,1600,3300,200,3,DOWN,NTRANS ++S 2400,1600,2400,3300,200,4,DOWN,NTRANS ++S 1600,1200,1600,1600,200,*,UP,POLY ++S 2400,1200,2400,1600,200,*,UP,POLY ++S 3000,700,3000,2100,400,*,DOWN,ALU1 ++S 3100,1800,3100,3100,600,*,UP,NDIF ++S 3000,5000,3000,5000,400,b,LEFT,CALU1 ++S 3000,2900,3000,4100,400,*,DOWN,ALU1 ++S 3000,3000,3000,4000,400,a,DOWN,CALU1 ++S 2000,4000,2000,5000,400,b,DOWN,CALU1 ++S 2000,3900,2000,5100,400,*,DOWN,ALU1 ++S 2000,3000,2000,3000,400,a,LEFT,CALU1 ++S 1400,4800,1400,5600,200,*,DOWN,POLY ++S 1600,3300,1600,5200,200,*,UP,POLY ++S 1400,5000,1800,5000,600,*,LEFT,POLY ++S 1800,5000,3000,5000,600,*,RIGHT,ALU1 ++S 2600,3800,2600,5600,200,*,DOWN,POLY ++S 2400,3300,2400,4200,200,*,UP,POLY ++S 2400,4000,3000,4000,600,*,LEFT,POLY ++S 1000,2000,1000,6000,400,z,DOWN,CALU1 ++S 1000,1900,1000,6000,400,*,DOWN,ALU1 ++V 2000,700,CONT_BODY_P,* ++V 1000,700,CONT_BODY_P,* ++V 2000,9300,CONT_BODY_N,* ++V 1000,9300,CONT_BODY_N,* ++V 2000,7000,CONT_DIF_P,* ++V 2000,6000,CONT_DIF_P,* ++V 800,7000,CONT_DIF_P,* ++V 3200,7000,CONT_DIF_P,* ++V 3200,6000,CONT_DIF_P,* ++V 1000,3000,CONT_DIF_N,* ++V 1000,2200,CONT_DIF_N,* ++V 3000,2000,CONT_DIF_N,* ++V 3000,4000,CONT_POLY,* ++V 1800,5000,CONT_POLY,* ++EOF +diff --git a/alliance/src/cells/src/msxlib/nd2_x1.vbe b/alliance/src/cells/src/msxlib/nd2_x1.vbe +new file mode 100644 +index 0000000..e179081 +--- /dev/null ++++ b/alliance/src/cells/src/msxlib/nd2_x1.vbe +@@ -0,0 +1,32 @@ ++ENTITY nd2_x1 IS ++GENERIC ( ++ CONSTANT area : NATURAL := 4000; ++ CONSTANT cin_a : NATURAL := 4; ++ CONSTANT cin_b : NATURAL := 4; ++ CONSTANT rdown_a_z : NATURAL := 2160; ++ CONSTANT rdown_b_z : NATURAL := 2160; ++ CONSTANT rup_a_z : NATURAL := 2960; ++ CONSTANT rup_b_z : NATURAL := 2960; ++ CONSTANT tphl_a_z : NATURAL := 34; ++ CONSTANT tphl_b_z : NATURAL := 35; ++ CONSTANT tplh_b_z : NATURAL := 45; ++ CONSTANT tplh_a_z : NATURAL := 51; ++ CONSTANT transistors : NATURAL := 4 ++); ++PORT ( ++ a : in BIT; ++ b : in BIT; ++ z : out BIT; ++ vdd : in BIT; ++ vss : in BIT ++); ++END nd2_x1; ++ ++ARCHITECTURE behaviour_data_flow OF nd2_x1 IS ++ ++BEGIN ++ ASSERT ((vdd and not (vss)) = '1') ++ REPORT "power supply is missing on nd2_x1" ++ SEVERITY WARNING; ++ z <= not ((a and b)) after 900 ps; ++END; +diff --git a/alliance/src/cells/src/msxlib/nd2_x2.ap b/alliance/src/cells/src/msxlib/nd2_x2.ap +new file mode 100644 +index 0000000..946cd48 +--- /dev/null ++++ b/alliance/src/cells/src/msxlib/nd2_x2.ap +@@ -0,0 +1,74 @@ ++V ALLIANCE : 6 ++H nd2_x2,P, 9/10/2005,100 ++A 0,0,4000,10000 ++R 3000,5000,ref_ref,a_50 ++R 2000,5000,ref_ref,b_50 ++R 2000,7000,ref_ref,z_70 ++R 1000,6000,ref_ref,z_60 ++R 1000,5000,ref_ref,z_50 ++R 1000,4000,ref_ref,z_40 ++R 2000,8000,ref_ref,z_80 ++R 2000,6000,ref_ref,b_60 ++R 3000,6000,ref_ref,b_60 ++R 3000,4000,ref_ref,a_40 ++R 2000,4000,ref_ref,a_40 ++R 1000,7000,ref_ref,z_70 ++R 1000,3000,ref_ref,z_30 ++R 1000,2000,ref_ref,z_20 ++R 3000,3000,ref_ref,a_30 ++S 3000,3000,3000,5000,400,a,DOWN,CALU1 ++S 1800,3900,1800,4900,200,*,UP,POLY ++S 2600,4900,3200,4900,600,*,LEFT,POLY ++S 1900,4000,3000,4000,400,*,LEFT,ALU1 ++S 3000,6000,3000,6000,400,b,LEFT,CALU1 ++S 2800,9400,2800,9700,200,*,UP,POLY ++S 1600,9400,1600,9700,200,*,UP,POLY ++S 1000,7000,2200,7000,600,*,LEFT,ALU1 ++S 0,600,4000,600,1200,vss,RIGHT,CALU1 ++S 0,9400,4000,9400,1200,vdd,RIGHT,CALU1 ++S 0,7600,4000,7600,5600,*,LEFT,NWELL ++S 0,2200,4000,2200,5200,*,LEFT,PWELL ++S 0,5000,4000,5000,10000,nd2_x2,LEFT,TALU8 ++S 2000,6000,3000,6000,600,*,RIGHT,ALU1 ++S 2000,5000,2000,6000,400,b,UP,CALU1 ++S 1000,8000,1000,9300,400,*,UP,ALU1 ++S 3400,8000,3400,9300,400,*,UP,ALU1 ++S 2100,7000,2100,8100,600,*,DOWN,ALU1 ++S 2000,7000,2000,8000,400,z,UP,CALU1 ++S 3400,5700,3400,9100,600,*,DOWN,PDIF ++S 2800,5500,2800,9400,200,2,UP,PTRANS ++S 2200,5700,2200,9200,1000,*,DOWN,PDIF ++S 1600,5500,1600,9400,200,1,UP,PTRANS ++S 1000,5700,1000,9200,1000,*,DOWN,PDIF ++S 2000,4800,2000,6000,400,*,UP,ALU1 ++S 1600,5100,1600,5500,200,*,DOWN,POLY ++S 1200,2100,1200,2900,600,*,UP,NDIF ++S 1400,800,1400,3700,400,*,UP,NDIF ++S 1800,600,1800,3900,200,3,DOWN,NTRANS ++S 1800,300,1800,600,200,*,UP,POLY ++S 2200,800,2200,3700,600,n1,UP,NDIF ++S 2600,600,2600,3900,200,4,DOWN,NTRANS ++S 2600,300,2600,600,200,*,UP,POLY ++S 3200,700,3200,2100,400,*,DOWN,ALU1 ++S 3300,800,3300,3700,600,*,UP,NDIF ++S 1100,1900,1100,3100,600,*,UP,ALU1 ++S 2000,4000,2000,4000,400,a,LEFT,CALU1 ++S 1800,4900,2000,4900,600,*,RIGHT,ALU1 ++S 2800,4700,2800,5500,200,*,UP,POLY ++S 2600,3900,2600,5100,200,*,UP,POLY ++S 1000,1900,1000,7000,400,*,DOWN,ALU1 ++S 1000,2000,1000,7000,400,z,DOWN,CALU1 ++S 3000,2900,3000,5100,400,*,DOWN,ALU1 ++V 1200,2200,CONT_DIF_N,* ++V 1000,8100,CONT_DIF_P,* ++V 3400,8100,CONT_DIF_P,* ++V 1000,9100,CONT_DIF_P,* ++V 3400,9100,CONT_DIF_P,* ++V 2200,7000,CONT_DIF_P,* ++V 2200,8000,CONT_DIF_P,* ++V 3000,4900,CONT_POLY,* ++V 1800,4900,CONT_POLY,* ++V 1200,3000,CONT_DIF_N,* ++V 3200,2000,CONT_DIF_N,* ++V 3200,1000,CONT_DIF_N,* ++EOF +diff --git a/alliance/src/cells/src/msxlib/nd2_x2.vbe b/alliance/src/cells/src/msxlib/nd2_x2.vbe +new file mode 100644 +index 0000000..3b871e5 +--- /dev/null ++++ b/alliance/src/cells/src/msxlib/nd2_x2.vbe +@@ -0,0 +1,32 @@ ++ENTITY nd2_x2 IS ++GENERIC ( ++ CONSTANT area : NATURAL := 4000; ++ CONSTANT cin_a : NATURAL := 8; ++ CONSTANT cin_b : NATURAL := 8; ++ CONSTANT rdown_a_z : NATURAL := 1110; ++ CONSTANT rdown_b_z : NATURAL := 1110; ++ CONSTANT rup_a_z : NATURAL := 1520; ++ CONSTANT rup_b_z : NATURAL := 1520; ++ CONSTANT tphl_a_z : NATURAL := 33; ++ CONSTANT tphl_b_z : NATURAL := 34; ++ CONSTANT tplh_b_z : NATURAL := 44; ++ CONSTANT tplh_a_z : NATURAL := 50; ++ CONSTANT transistors : NATURAL := 4 ++); ++PORT ( ++ a : in BIT; ++ b : in BIT; ++ z : out BIT; ++ vdd : in BIT; ++ vss : in BIT ++); ++END nd2_x2; ++ ++ARCHITECTURE behaviour_data_flow OF nd2_x2 IS ++ ++BEGIN ++ ASSERT ((vdd and not (vss)) = '1') ++ REPORT "power supply is missing on nd2_x2" ++ SEVERITY WARNING; ++ z <= not ((a and b)) after 900 ps; ++END; +diff --git a/alliance/src/cells/src/msxlib/nd2_x4.ap b/alliance/src/cells/src/msxlib/nd2_x4.ap +new file mode 100644 +index 0000000..7868c0c +--- /dev/null ++++ b/alliance/src/cells/src/msxlib/nd2_x4.ap +@@ -0,0 +1,114 @@ ++V ALLIANCE : 6 ++H nd2_x4,P,29/ 9/2005,100 ++A 0,0,6000,10000 ++R 3000,2000,ref_ref,z_20 ++R 2000,4000,ref_ref,a_40 ++R 1000,3000,ref_ref,z_30 ++R 5000,6000,ref_ref,b_60 ++R 4000,8000,ref_ref,z_80 ++R 5000,4000,ref_ref,a_40 ++R 4000,6000,ref_ref,b_60 ++R 2000,7000,ref_ref,z_70 ++R 1000,6000,ref_ref,z_60 ++R 1000,5000,ref_ref,z_50 ++R 1000,4000,ref_ref,z_40 ++R 2000,3000,ref_ref,z_30 ++R 3000,3000,ref_ref,z_30 ++R 3000,7000,ref_ref,z_70 ++R 4000,7000,ref_ref,z_70 ++R 2000,5000,ref_ref,a_50 ++R 3000,4000,ref_ref,a_40 ++R 4000,4000,ref_ref,a_40 ++R 4000,5000,ref_ref,b_50 ++R 5000,5000,ref_ref,a_50 ++R 2000,6000,ref_ref,z_60 ++S 4600,4200,5000,4200,200,*,RIGHT,POLY ++S 4600,3800,4600,4300,200,*,UP,POLY ++S 3800,6000,5100,6000,400,*,RIGHT,ALU1 ++S 5000,6000,5000,6000,400,b,UP,CALU1 ++S 5000,3900,5000,5100,400,*,UP,ALU1 ++S 5000,4000,5000,5000,400,a,UP,CALU1 ++S 1000,2900,1000,6100,400,*,DOWN,ALU1 ++S 600,7900,600,9300,400,*,UP,ALU1 ++S 2400,4800,2400,5600,200,*,DOWN,POLY ++S 4600,300,4600,600,200,*,UP,POLY ++S 3800,300,3800,600,200,*,UP,POLY ++S 2600,300,2600,600,200,*,UP,POLY ++S 1800,300,1800,600,200,*,UP,POLY ++S 3000,7000,3000,7000,400,z,LEFT,CALU1 ++S 4000,4000,4000,4000,400,a,LEFT,CALU1 ++S 3000,4000,3000,4000,400,a,LEFT,CALU1 ++S 3100,1900,3100,3000,600,*,DOWN,ALU1 ++S 2000,3000,2000,3000,400,z,LEFT,CALU1 ++S 3000,2000,3000,3000,400,z,DOWN,CALU1 ++S 1000,3000,3200,3000,600,*,RIGHT,ALU1 ++S 3900,4900,3900,6000,600,*,DOWN,ALU1 ++S 3700,4300,3700,4800,400,*,UP,POLY ++S 1800,3800,1800,4700,200,*,UP,POLY ++S 5200,800,5200,3600,600,*,UP,NDIF ++S 5200,700,5200,2100,400,*,DOWN,ALU1 ++S 4600,600,4600,3800,200,8,DOWN,NTRANS ++S 4200,900,4200,3600,600,n2,UP,NDIF ++S 2600,4200,3800,4200,200,*,RIGHT,POLY ++S 3800,600,3800,3800,200,7,DOWN,NTRANS ++S 3200,800,3200,3600,600,*,UP,NDIF ++S 2600,600,2600,3800,200,6,DOWN,NTRANS ++S 2200,900,2200,3600,600,n1,UP,NDIF ++S 1800,600,1800,3800,200,5,DOWN,NTRANS ++S 1100,800,1100,3600,600,*,UP,NDIF ++S 1200,700,1200,2100,400,*,DOWN,ALU1 ++S 2000,3900,5000,3900,400,*,RIGHT,ALU1 ++S 2000,4000,5000,4000,400,*,RIGHT,ALU1 ++S 4000,5000,4000,6000,400,b,DOWN,CALU1 ++S 4000,7000,4000,8000,400,z,UP,CALU1 ++S 4100,7000,4100,8100,600,*,DOWN,ALU1 ++S 3000,5800,3000,9200,600,*,DOWN,PDIF ++S 5400,7900,5400,9300,400,*,UP,ALU1 ++S 3000,7900,3000,9300,400,*,UP,ALU1 ++S 0,7600,6000,7600,5600,*,LEFT,NWELL ++S 0,2200,6000,2200,5200,*,LEFT,PWELL ++S 0,5000,6000,5000,10000,nd2_x4,LEFT,TALU8 ++S 1200,5600,1200,9400,200,1,UP,PTRANS ++S 600,5800,600,9200,600,*,DOWN,PDIF ++S 1200,9400,1200,9700,200,*,DOWN,POLY ++S 1800,5800,1800,9200,1000,*,DOWN,PDIF ++S 2400,5600,2400,9400,200,2,UP,PTRANS ++S 2400,9400,2400,9700,200,*,DOWN,POLY ++S 3600,5600,3600,9400,200,3,UP,PTRANS ++S 4800,5600,4800,9400,200,4,UP,PTRANS ++S 0,9400,6000,9400,1200,vdd,RIGHT,CALU1 ++S 0,600,6000,600,1200,vss,RIGHT,CALU1 ++S 5400,5800,5400,9200,600,*,DOWN,PDIF ++S 4200,5800,4200,9200,1000,*,DOWN,PDIF ++S 1200,5200,2400,5200,200,*,RIGHT,POLY ++S 3600,5200,4800,5200,200,*,RIGHT,POLY ++S 3600,9400,3600,9700,200,*,DOWN,POLY ++S 4800,9400,4800,9700,200,*,DOWN,POLY ++S 2000,4000,2000,5000,400,a,DOWN,CALU1 ++S 2000,4000,2000,5100,400,*,DOWN,ALU1 ++S 2000,6000,2000,7000,400,z,UP,CALU1 ++S 1000,3000,1000,6000,400,z,DOWN,CALU1 ++S 1800,7000,4200,7000,400,*,LEFT,ALU1 ++S 1800,7100,4200,7100,400,*,LEFT,ALU1 ++S 1000,6000,2000,6000,600,*,RIGHT,ALU1 ++S 1900,5900,1900,7100,600,*,DOWN,ALU1 ++V 4200,7100,CONT_DIF_P,* ++V 3800,5000,CONT_POLY,* ++V 5200,1000,CONT_DIF_N,* ++V 5200,2000,CONT_DIF_N,* ++V 3200,3000,CONT_DIF_N,* ++V 3200,2000,CONT_DIF_N,* ++V 1200,1000,CONT_DIF_N,* ++V 1200,2000,CONT_DIF_N,* ++V 5000,4400,CONT_POLY,* ++V 4200,8000,CONT_DIF_P,* ++V 5400,9000,CONT_DIF_P,* ++V 3000,9000,CONT_DIF_P,* ++V 600,9000,CONT_DIF_P,* ++V 5400,8000,CONT_DIF_P,* ++V 3000,8000,CONT_DIF_P,* ++V 600,8000,CONT_DIF_P,* ++V 2000,5000,CONT_POLY,* ++V 1800,7000,CONT_DIF_P,* ++V 1800,6000,CONT_DIF_P,* ++EOF +diff --git a/alliance/src/cells/src/msxlib/nd2_x4.vbe b/alliance/src/cells/src/msxlib/nd2_x4.vbe +new file mode 100644 +index 0000000..481418a +--- /dev/null ++++ b/alliance/src/cells/src/msxlib/nd2_x4.vbe +@@ -0,0 +1,32 @@ ++ENTITY nd2_x4 IS ++GENERIC ( ++ CONSTANT area : NATURAL := 6000; ++ CONSTANT cin_a : NATURAL := 15; ++ CONSTANT cin_b : NATURAL := 14; ++ CONSTANT rdown_a_z : NATURAL := 570; ++ CONSTANT rdown_b_z : NATURAL := 570; ++ CONSTANT rup_a_z : NATURAL := 780; ++ CONSTANT rup_b_z : NATURAL := 780; ++ CONSTANT tphl_a_z : NATURAL := 32; ++ CONSTANT tphl_b_z : NATURAL := 34; ++ CONSTANT tplh_b_z : NATURAL := 43; ++ CONSTANT tplh_a_z : NATURAL := 49; ++ CONSTANT transistors : NATURAL := 8 ++); ++PORT ( ++ a : in BIT; ++ b : in BIT; ++ z : out BIT; ++ vdd : in BIT; ++ vss : in BIT ++); ++END nd2_x4; ++ ++ARCHITECTURE behaviour_data_flow OF nd2_x4 IS ++ ++BEGIN ++ ASSERT ((vdd and not (vss)) = '1') ++ REPORT "power supply is missing on nd2_x4" ++ SEVERITY WARNING; ++ z <= not ((a and b)) after 900 ps; ++END; +diff --git a/alliance/src/cells/src/msxlib/nd2a_x1.ap b/alliance/src/cells/src/msxlib/nd2a_x1.ap +new file mode 100644 +index 0000000..a56c70a +--- /dev/null ++++ b/alliance/src/cells/src/msxlib/nd2a_x1.ap +@@ -0,0 +1,91 @@ ++V ALLIANCE : 6 ++H nd2a_x1,P, 8/ 8/2014,100 ++A 0,0,5000,10000 ++R 2000,2000,ref_ref,a_20 ++R 3000,2000,ref_ref,a_20 ++R 2000,5000,ref_ref,b_50 ++R 2000,7000,ref_ref,z_70 ++R 1000,6000,ref_ref,z_60 ++R 1000,5000,ref_ref,z_50 ++R 1000,4000,ref_ref,z_40 ++R 2000,8000,ref_ref,z_80 ++R 2000,6000,ref_ref,b_60 ++R 3000,6000,ref_ref,b_60 ++R 3000,7000,ref_ref,b_70 ++R 3000,4000,ref_ref,a_40 ++R 3000,3000,ref_ref,a_30 ++R 1000,7000,ref_ref,z_70 ++R 1000,3000,ref_ref,z_30 ++R 1000,2000,ref_ref,z_20 ++S 1100,700,1900,700,600,*,RIGHT,PTIE ++S 1100,9300,1900,9300,600,*,RIGHT,NTIE ++S 3800,8300,3800,8700,200,*,UP,POLY ++S 2600,8300,2600,8700,200,*,UP,POLY ++S 1400,8300,1400,8700,200,*,UP,POLY ++S 1400,4700,1400,6300,200,*,DOWN,POLY ++S 3800,3300,3800,6300,200,*,DOWN,POLY ++S 3000,4000,3600,4000,600,*,LEFT,ALU1 ++S 2000,2000,3000,2000,600,*,RIGHT,ALU1 ++S 2000,2000,2000,2000,400,a,LEFT,CALU1 ++S 2600,3700,2600,6300,200,*,DOWN,POLY ++S 2400,3300,2400,3800,200,*,UP,POLY ++S 2400,1200,2400,1600,200,*,DOWN,POLY ++S 2400,1600,2400,3300,200,4,DOWN,NTRANS ++S 2000,1800,2000,3100,600,n1,UP,NDIF ++S 1600,3300,1600,4500,200,*,UP,POLY ++S 1600,1200,1600,1600,200,*,DOWN,POLY ++S 1600,1600,1600,3300,200,3,DOWN,NTRANS ++S 1200,1800,1200,3100,400,*,UP,NDIF ++S 1000,2100,1000,2900,600,*,UP,NDIF ++S 2800,5000,4400,5000,400,*,RIGHT,ALU1 ++S 4400,2900,4400,7500,400,*,DOWN,ALU1 ++S 3200,900,3200,3100,600,*,UP,NDIF ++S 3800,1900,3800,2300,200,*,DOWN,POLY ++S 4200,2500,4200,3100,400,*,UP,NDIF ++S 3800,2300,3800,3300,200,2a,DOWN,NTRANS ++S 4400,6700,4400,7300,600,*,UP,PDIF ++S 3200,6500,3200,8100,600,*,DOWN,PDIF ++S 4200,6500,4200,8100,400,*,DOWN,PDIF ++S 3800,6300,3800,8300,200,1a,UP,PTRANS ++S 700,6500,700,8100,600,*,DOWN,PDIF ++S 2000,6500,2000,8100,1000,*,DOWN,PDIF ++S 1400,6300,1400,8300,200,1,UP,PTRANS ++S 2600,6300,2600,8300,200,2,UP,PTRANS ++S 3200,7900,3200,9300,400,*,UP,ALU1 ++S 800,7900,800,9300,400,*,UP,ALU1 ++S 3000,1900,3000,4000,400,*,DOWN,ALU1 ++S 3000,2000,3000,4000,400,a,DOWN,CALU1 ++S 0,600,5000,600,1200,vss,RIGHT,CALU1 ++S 0,5000,5000,5000,10000,nd2a_x1,LEFT,TALU8 ++S 0,2200,5000,2200,5200,*,LEFT,PWELL ++S 0,7600,5000,7600,5600,*,LEFT,NWELL ++S 0,9400,5000,9400,1200,vdd,RIGHT,CALU1 ++S 1000,7000,2000,7000,600,*,LEFT,ALU1 ++S 2000,7000,2000,8100,400,*,DOWN,ALU1 ++S 3000,6000,3000,7100,400,*,UP,ALU1 ++S 2000,6000,3000,6000,600,*,RIGHT,ALU1 ++S 3000,6000,3000,7000,400,b,UP,CALU1 ++S 2000,5000,2000,6000,400,b,UP,CALU1 ++S 2000,7000,2000,8000,400,z,UP,CALU1 ++S 2000,4800,2000,6000,400,*,UP,ALU1 ++S 1800,4900,2000,4900,600,*,RIGHT,ALU1 ++S 1000,2000,1000,7000,400,z,DOWN,CALU1 ++S 1000,1900,1000,7000,400,*,DOWN,ALU1 ++V 2000,700,CONT_BODY_P,* ++V 1000,700,CONT_BODY_P,* ++V 2000,9300,CONT_BODY_N,* ++V 1000,9300,CONT_BODY_N,* ++V 2900,5000,CONT_POLY,an ++V 4400,3000,CONT_DIF_N,an ++V 4400,6600,CONT_DIF_P,an ++V 4400,7400,CONT_DIF_P,an ++V 1000,2200,CONT_DIF_N,* ++V 1000,3000,CONT_DIF_N,* ++V 3500,4000,CONT_POLY,* ++V 800,8000,CONT_DIF_P,* ++V 3200,8000,CONT_DIF_P,* ++V 2000,7000,CONT_DIF_P,* ++V 2000,8000,CONT_DIF_P,* ++V 1800,4900,CONT_POLY,* ++V 3200,1000,CONT_DIF_N,* ++EOF +diff --git a/alliance/src/cells/src/msxlib/nd2a_x1.vbe b/alliance/src/cells/src/msxlib/nd2a_x1.vbe +new file mode 100644 +index 0000000..d6c5c83 +--- /dev/null ++++ b/alliance/src/cells/src/msxlib/nd2a_x1.vbe +@@ -0,0 +1,32 @@ ++ENTITY nd2a_x1 IS ++GENERIC ( ++ CONSTANT area : NATURAL := 5000; ++ CONSTANT cin_b : NATURAL := 4; ++ CONSTANT cin_a : NATURAL := 4; ++ CONSTANT rdown_b_z : NATURAL := 2160; ++ CONSTANT rdown_a_z : NATURAL := 2160; ++ CONSTANT rup_b_z : NATURAL := 2960; ++ CONSTANT rup_a_z : NATURAL := 2960; ++ CONSTANT tphl_b_z : NATURAL := 36; ++ CONSTANT tplh_b_z : NATURAL := 45; ++ CONSTANT tpll_a_z : NATURAL := 78; ++ CONSTANT tphh_a_z : NATURAL := 75; ++ CONSTANT transistors : NATURAL := 6 ++); ++PORT ( ++ b : in BIT; ++ a : in BIT; ++ z : out BIT; ++ vdd : in BIT; ++ vss : in BIT ++); ++END nd2a_x1; ++ ++ARCHITECTURE behaviour_data_flow OF nd2a_x1 IS ++ ++BEGIN ++ ASSERT ((vdd and not (vss)) = '1') ++ REPORT "power supply is missing on nd2a_x1" ++ SEVERITY WARNING; ++ z <= (not (b) or a) after 900 ps; ++END; +diff --git a/alliance/src/cells/src/msxlib/nd2a_x2.ap b/alliance/src/cells/src/msxlib/nd2a_x2.ap +new file mode 100644 +index 0000000..657916c +--- /dev/null ++++ b/alliance/src/cells/src/msxlib/nd2a_x2.ap +@@ -0,0 +1,95 @@ ++V ALLIANCE : 6 ++H nd2a_x2,P, 8/ 8/2014,100 ++A 0,0,5000,10000 ++R 1000,3000,ref_ref,z_30 ++R 1000,7000,ref_ref,z_70 ++R 3000,4000,ref_ref,a_40 ++R 3000,7000,ref_ref,b_70 ++R 3000,6000,ref_ref,b_60 ++R 2000,6000,ref_ref,b_60 ++R 2000,8000,ref_ref,z_80 ++R 1000,4000,ref_ref,z_40 ++R 1000,5000,ref_ref,z_50 ++R 1000,6000,ref_ref,z_60 ++R 2000,7000,ref_ref,z_70 ++R 2000,5000,ref_ref,b_50 ++R 2000,2000,ref_ref,a_20 ++R 2000,3000,ref_ref,a_30 ++R 3000,3000,ref_ref,a_30 ++S 1800,4900,2000,4900,600,*,RIGHT,ALU1 ++S 2600,300,2600,600,200,*,UP,POLY ++S 2600,600,2600,3900,200,4,DOWN,NTRANS ++S 2200,800,2200,3700,600,n1,UP,NDIF ++S 1800,3900,1800,4500,200,*,UP,POLY ++S 1800,300,1800,600,200,*,UP,POLY ++S 1800,600,1800,3900,200,3,DOWN,NTRANS ++S 1400,800,1400,3700,400,*,UP,NDIF ++S 2000,4800,2000,6000,400,*,UP,ALU1 ++S 2000,7000,2000,8000,400,z,UP,CALU1 ++S 2000,5000,2000,6000,400,b,UP,CALU1 ++S 3000,6000,3000,7000,400,b,UP,CALU1 ++S 2000,6000,3000,6000,600,*,RIGHT,ALU1 ++S 3000,6000,3000,7100,400,*,UP,ALU1 ++S 1400,5500,1400,9400,200,1,UP,PTRANS ++S 1400,9400,1400,9700,200,*,UP,POLY ++S 2000,7000,2000,8100,400,*,DOWN,ALU1 ++S 1000,7000,2000,7000,600,*,LEFT,ALU1 ++S 1400,5000,1400,5500,200,*,DOWN,POLY ++S 2000,5700,2000,9200,1000,*,DOWN,PDIF ++S 2600,5500,2600,9400,200,2,UP,PTRANS ++S 2600,9400,2600,9700,200,*,UP,POLY ++S 2600,3900,2600,5500,200,*,UP,POLY ++S 3200,8000,3200,9300,400,*,UP,ALU1 ++S 0,9400,5000,9400,1200,vdd,RIGHT,CALU1 ++S 0,5000,5000,5000,10000,nd2a_x2,LEFT,TALU8 ++S 0,2200,5000,2200,5200,*,LEFT,PWELL ++S 0,7600,5000,7600,5600,*,LEFT,NWELL ++S 4400,5900,4400,6500,600,*,UP,PDIF ++S 4200,5700,4200,8300,400,*,DOWN,PDIF ++S 3200,5700,3200,9200,600,*,DOWN,PDIF ++S 3800,8400,3800,8900,200,*,UP,POLY ++S 0,600,5000,600,1200,vss,RIGHT,CALU1 ++S 3800,3900,3800,5500,200,*,DOWN,POLY ++S 3800,5500,3800,8500,200,1a,UP,PTRANS ++S 3000,800,3000,3700,400,*,DOWN,NDIF ++S 2800,4900,4600,4900,400,*,RIGHT,ALU1 ++S 4600,2100,4600,4900,400,*,DOWN,ALU1 ++S 4400,4900,4400,6700,400,*,DOWN,ALU1 ++S 3800,1800,3800,3300,200,2a,DOWN,NTRANS ++S 3200,800,3200,3100,600,*,UP,NDIF ++S 4500,2000,4500,3000,600,*,UP,ALU1 ++S 4400,2200,4400,3100,600,*,UP,NDIF ++S 3800,1400,3800,1800,200,*,DOWN,POLY ++S 700,5700,700,9200,600,*,DOWN,PDIF ++S 800,8000,800,9300,400,*,UP,ALU1 ++S 3200,700,3200,2100,400,*,DOWN,ALU1 ++S 3000,3000,3000,4000,400,a,DOWN,CALU1 ++S 2000,2000,2000,3000,400,a,DOWN,CALU1 ++S 2000,1900,2000,3100,400,*,DOWN,ALU1 ++S 1200,2700,1200,3500,600,*,UP,NDIF ++S 1000,2700,1000,7000,400,*,DOWN,ALU1 ++S 1000,3000,1000,7000,400,z,DOWN,CALU1 ++S 1100,2700,1100,3700,600,*,UP,ALU1 ++S 3000,3900,3800,3900,600,*,LEFT,ALU1 ++S 3000,2900,3000,4000,600,*,DOWN,ALU1 ++S 2000,3000,3100,3000,600,*,RIGHT,ALU1 ++V 4300,9300,CONT_BODY_N,* ++V 4300,700,CONT_BODY_P,* ++V 3200,1000,CONT_DIF_N,* ++V 1800,4900,CONT_POLY,* ++V 800,8100,CONT_DIF_P,* ++V 800,9100,CONT_DIF_P,* ++V 2000,8000,CONT_DIF_P,* ++V 2000,7000,CONT_DIF_P,* ++V 3200,8100,CONT_DIF_P,* ++V 3200,9100,CONT_DIF_P,* ++V 4400,5800,CONT_DIF_P,* ++V 4400,6600,CONT_DIF_P,* ++V 2900,4900,CONT_POLY,* ++V 4400,2100,CONT_DIF_N,* ++V 4400,2900,CONT_DIF_N,* ++V 3200,2000,CONT_DIF_N,* ++V 1200,3600,CONT_DIF_N,* ++V 1200,2800,CONT_DIF_N,* ++V 3800,3900,CONT_POLY,* ++EOF +diff --git a/alliance/src/cells/src/msxlib/nd2a_x2.vbe b/alliance/src/cells/src/msxlib/nd2a_x2.vbe +new file mode 100644 +index 0000000..535da81 +--- /dev/null ++++ b/alliance/src/cells/src/msxlib/nd2a_x2.vbe +@@ -0,0 +1,32 @@ ++ENTITY nd2a_x2 IS ++GENERIC ( ++ CONSTANT area : NATURAL := 5000; ++ CONSTANT cin_b : NATURAL := 8; ++ CONSTANT cin_a : NATURAL := 6; ++ CONSTANT rdown_b_z : NATURAL := 1110; ++ CONSTANT rdown_a_z : NATURAL := 1110; ++ CONSTANT rup_b_z : NATURAL := 1520; ++ CONSTANT rup_a_z : NATURAL := 1520; ++ CONSTANT tphl_b_z : NATURAL := 34; ++ CONSTANT tplh_b_z : NATURAL := 44; ++ CONSTANT tpll_a_z : NATURAL := 80; ++ CONSTANT tphh_a_z : NATURAL := 76; ++ CONSTANT transistors : NATURAL := 6 ++); ++PORT ( ++ b : in BIT; ++ a : in BIT; ++ z : out BIT; ++ vdd : in BIT; ++ vss : in BIT ++); ++END nd2a_x2; ++ ++ARCHITECTURE behaviour_data_flow OF nd2a_x2 IS ++ ++BEGIN ++ ASSERT ((vdd and not (vss)) = '1') ++ REPORT "power supply is missing on nd2a_x2" ++ SEVERITY WARNING; ++ z <= (not (b) or a) after 900 ps; ++END; +diff --git a/alliance/src/cells/src/msxlib/nd2ab_x1.ap b/alliance/src/cells/src/msxlib/nd2ab_x1.ap +new file mode 100644 +index 0000000..cec8334 +--- /dev/null ++++ b/alliance/src/cells/src/msxlib/nd2ab_x1.ap +@@ -0,0 +1,104 @@ ++V ALLIANCE : 6 ++H nd2ab_x1,P, 8/ 8/2014,100 ++A 0,0,6000,10000 ++R 3000,4000,ref_ref,z_40 ++R 3000,3000,ref_ref,z_30 ++R 3000,2000,ref_ref,z_20 ++R 2000,6000,ref_ref,b_60 ++R 3000,5000,ref_ref,z_50 ++R 2000,2000,ref_ref,z_20 ++R 4000,6000,ref_ref,a_60 ++R 4000,7000,ref_ref,a_70 ++R 1000,7000,ref_ref,b_70 ++R 2000,7000,ref_ref,b_70 ++R 1000,8000,ref_ref,b_80 ++R 5000,7000,ref_ref,a_70 ++R 4000,5000,ref_ref,a_50 ++R 3000,7000,ref_ref,z_70 ++R 3000,6000,ref_ref,z_60 ++S 1100,9300,1900,9300,600,*,RIGHT,NTIE ++S 600,700,600,3400,400,*,DOWN,ALU1 ++S 2000,6000,2000,7000,400,b,DOWN,CALU1 ++S 2000,5900,2000,7000,400,*,DOWN,ALU1 ++S 4200,700,4200,3100,400,*,DOWN,ALU1 ++S 0,600,6000,600,1200,vss,RIGHT,CALU1 ++S 5400,2900,5400,5900,400,*,UP,ALU1 ++S 4000,4900,4600,4900,400,*,LEFT,ALU1 ++S 4000,5000,4000,7000,400,*,DOWN,ALU1 ++S 4000,5000,4000,7000,400,a,DOWN,CALU1 ++S 600,4900,600,5900,400,*,UP,ALU1 ++S 1000,7000,2000,7000,600,*,RIGHT,ALU1 ++S 3000,2000,3000,7000,400,z,UP,CALU1 ++S 2000,2000,3000,2000,600,*,RIGHT,ALU1 ++S 4200,7900,4200,9300,400,*,UP,ALU1 ++S 4000,7000,5100,7000,400,*,LEFT,ALU1 ++S 4000,7100,5100,7100,400,*,LEFT,ALU1 ++S 3900,3900,5400,3900,400,*,RIGHT,ALU1 ++S 1000,7000,1000,8100,400,*,UP,ALU1 ++S 1800,3500,1800,4900,400,*,DOWN,ALU1 ++S 1800,7900,1800,9300,400,*,UP,ALU1 ++S 3000,2000,3000,7100,400,*,DOWN,ALU1 ++S 1000,7000,1000,8000,400,b,UP,CALU1 ++S 0,9400,6000,9400,1200,vdd,RIGHT,CALU1 ++S 600,4900,2100,4900,400,*,RIGHT,ALU1 ++S 2400,4700,2400,5500,200,*,DOWN,POLY ++S 2200,4700,2800,4700,200,*,LEFT,POLY ++S 2800,2300,2800,4700,200,*,UP,POLY ++S 3600,300,3600,700,200,*,DOWN,POLY ++S 3600,2400,3600,5500,200,*,DOWN,POLY ++S 4800,2000,4800,2400,200,*,DOWN,POLY ++S 1200,3900,1200,5500,200,*,DOWN,POLY ++S 2800,300,2800,700,200,*,DOWN,POLY ++S 4800,7300,4800,7700,200,*,UP,POLY ++S 3600,7500,3600,7900,200,*,UP,POLY ++S 2400,7500,2400,7900,200,*,UP,POLY ++S 1200,7300,1200,7800,200,*,UP,POLY ++S 4800,3300,4800,5500,200,*,UP,POLY ++S 1200,2600,1200,3000,200,*,DOWN,POLY ++S 5200,2600,5200,3100,400,*,UP,NDIF ++S 2400,900,2400,2200,400,*,UP,NDIF ++S 1600,3200,1600,3700,400,*,UP,NDIF ++S 3200,900,3200,2200,600,n1,UP,NDIF ++S 600,3200,600,3700,600,*,UP,NDIF ++S 4200,900,4200,3100,600,*,UP,NDIF ++S 3600,700,3600,2400,200,3z,DOWN,NTRANS ++S 2800,700,2800,2400,200,4z,DOWN,NTRANS ++S 1200,3000,1200,3900,200,2b,DOWN,NTRANS ++S 4800,2400,4800,3300,200,2a,DOWN,NTRANS ++S 1800,5700,1800,7300,600,*,DOWN,PDIF ++S 800,5700,800,7100,400,*,DOWN,PDIF ++S 3600,5500,3600,7500,200,1z,UP,PTRANS ++S 2400,5500,2400,7500,200,2z,UP,PTRANS ++S 3000,5700,3000,7300,600,*,DOWN,PDIF ++S 0,5000,6000,5000,10000,nd2ab_x1,LEFT,TALU8 ++S 0,2200,6000,2200,5200,*,LEFT,PWELL ++S 0,7600,6000,7600,5600,*,LEFT,NWELL ++S 1800,5700,1800,8100,600,*,DOWN,PDIF ++S 4200,5700,4200,8100,600,*,DOWN,PDIF ++S 5200,5700,5200,7100,400,*,DOWN,PDIF ++S 4800,5500,4800,7300,200,1a,UP,PTRANS ++S 4000,5700,4000,7300,400,*,UP,PDIF ++S 1200,5500,1200,7300,200,1b,UP,PTRANS ++S 5000,7000,5000,7000,400,a,LEFT,CALU1 ++S 2000,2000,2000,2000,400,z,LEFT,CALU1 ++V 2000,9300,CONT_BODY_N,* ++V 1000,9300,CONT_BODY_N,* ++V 1000,700,CONT_BODY_P,* ++V 1000,8000,CONT_POLY,* ++V 4500,4900,CONT_POLY,* ++V 4000,3900,CONT_POLY,an ++V 2000,4900,CONT_POLY,bn ++V 4200,2000,CONT_DIF_N,* ++V 5400,3000,CONT_DIF_N,an ++V 4200,3000,CONT_DIF_N,* ++V 4200,1000,CONT_DIF_N,* ++V 2200,2100,CONT_DIF_N,* ++V 1800,3600,CONT_DIF_N,bn ++V 600,3300,CONT_DIF_N,* ++V 1800,8000,CONT_DIF_P,* ++V 3000,7000,CONT_DIF_P,* ++V 600,5800,CONT_DIF_P,bn ++V 5400,5800,CONT_DIF_P,an ++V 3000,6000,CONT_DIF_P,* ++V 4200,8000,CONT_DIF_P,* ++EOF +diff --git a/alliance/src/cells/src/msxlib/nd2ab_x1.vbe b/alliance/src/cells/src/msxlib/nd2ab_x1.vbe +new file mode 100644 +index 0000000..755c209 +--- /dev/null ++++ b/alliance/src/cells/src/msxlib/nd2ab_x1.vbe +@@ -0,0 +1,32 @@ ++ENTITY nd2ab_x1 IS ++GENERIC ( ++ CONSTANT area : NATURAL := 6000; ++ CONSTANT cin_a : NATURAL := 4; ++ CONSTANT cin_b : NATURAL := 4; ++ CONSTANT rdown_a_z : NATURAL := 2160; ++ CONSTANT rdown_b_z : NATURAL := 2160; ++ CONSTANT rup_a_z : NATURAL := 2960; ++ CONSTANT rup_b_z : NATURAL := 2970; ++ CONSTANT tpll_a_z : NATURAL := 81; ++ CONSTANT tphh_b_z : NATURAL := 70; ++ CONSTANT tpll_b_z : NATURAL := 77; ++ CONSTANT tphh_a_z : NATURAL := 76; ++ CONSTANT transistors : NATURAL := 8 ++); ++PORT ( ++ a : in BIT; ++ b : in BIT; ++ z : out BIT; ++ vdd : in BIT; ++ vss : in BIT ++); ++END nd2ab_x1; ++ ++ARCHITECTURE behaviour_data_flow OF nd2ab_x1 IS ++ ++BEGIN ++ ASSERT ((vdd and not (vss)) = '1') ++ REPORT "power supply is missing on nd2ab_x1" ++ SEVERITY WARNING; ++ z <= (a or b) after 1100 ps; ++END; +diff --git a/alliance/src/cells/src/msxlib/nd2ab_x2.ap b/alliance/src/cells/src/msxlib/nd2ab_x2.ap +new file mode 100644 +index 0000000..e609e55 +--- /dev/null ++++ b/alliance/src/cells/src/msxlib/nd2ab_x2.ap +@@ -0,0 +1,118 @@ ++V ALLIANCE : 6 ++H nd2ab_x2,P, 8/ 8/2014,100 ++A 0,0,7000,10000 ++R 4000,7000,ref_ref,z_70 ++R 4000,6000,ref_ref,z_60 ++R 4000,5000,ref_ref,z_50 ++R 4000,4000,ref_ref,z_40 ++R 4000,3000,ref_ref,z_30 ++R 3000,2000,ref_ref,z_20 ++R 2000,3000,ref_ref,b_30 ++R 2000,4000,ref_ref,b_40 ++R 5000,6000,ref_ref,a_60 ++R 5000,7000,ref_ref,a_70 ++R 5000,8000,ref_ref,a_80 ++R 6000,8000,ref_ref,a_80 ++R 3000,3000,ref_ref,z_30 ++R 2000,5000,ref_ref,b_50 ++R 3000,4000,ref_ref,b_40 ++S 800,9300,1600,9300,600,*,RIGHT,NTIE ++S 1100,700,1900,700,600,*,RIGHT,PTIE ++S 800,1900,800,6000,400,*,DOWN,ALU1 ++S 1400,3100,1400,4700,200,*,UP,POLY ++S 1400,1300,1400,1700,200,*,DOWN,POLY ++S 2000,1900,2000,2900,600,*,UP,NDIF ++S 800,2100,800,2700,600,*,UP,NDIF ++S 1400,1700,1400,3100,200,2b,DOWN,NTRANS ++S 1000,1900,1000,2900,400,*,UP,NDIF ++S 0,5000,7000,5000,10000,nd2ab_x2,LEFT,TALU8 ++S 0,2200,7000,2200,5200,*,LEFT,PWELL ++S 0,7600,7000,7600,5600,*,LEFT,NWELL ++S 0,600,7000,600,1200,vss,RIGHT,CALU1 ++S 0,9400,7000,9400,1200,vdd,RIGHT,CALU1 ++S 4200,800,4200,3700,600,n1,UP,NDIF ++S 3400,800,3400,3700,400,*,UP,NDIF ++S 5000,6000,5000,8000,400,*,DOWN,ALU1 ++S 5000,6000,5000,8000,400,a,DOWN,CALU1 ++S 5000,6000,5800,6000,600,*,LEFT,ALU1 ++S 5000,8000,6100,8000,400,*,LEFT,ALU1 ++S 5000,8100,6100,8100,400,*,LEFT,ALU1 ++S 6300,7000,6600,7000,600,*,LEFT,ALU1 ++S 6600,4900,6600,7100,400,*,DOWN,ALU1 ++S 4900,4900,6600,4900,400,*,RIGHT,ALU1 ++S 5200,700,5200,3100,400,*,DOWN,ALU1 ++S 6400,2700,6400,4900,400,*,UP,ALU1 ++S 2800,6900,2800,9200,400,*,UP,ALU1 ++S 2800,5700,2800,9200,600,*,DOWN,PDIF ++S 4000,5700,4000,9200,600,*,DOWN,PDIF ++S 5000,5700,5000,9200,400,*,UP,PDIF ++S 6400,2900,6400,3500,600,*,DOWN,NDIF ++S 5200,800,5200,3700,600,*,UP,NDIF ++S 4600,3900,4600,5500,200,*,DOWN,POLY ++S 3400,4700,3400,5500,200,*,DOWN,POLY ++S 3800,3900,3800,4700,200,*,UP,POLY ++S 3200,4700,3800,4700,200,*,LEFT,POLY ++S 1800,5700,1800,8100,400,*,DOWN,PDIF ++S 6200,6800,6200,9200,400,*,DOWN,PDIF ++S 5200,6800,5200,9200,600,*,DOWN,PDIF ++S 6400,6800,6400,7100,600,*,UP,PDIF ++S 5800,3900,5800,5900,200,*,UP,POLY ++S 2200,8300,2200,8700,200,*,UP,POLY ++S 3400,9400,3400,9700,200,*,UP,POLY ++S 4600,9400,4600,9700,200,*,UP,POLY ++S 5800,9400,5800,9700,200,*,UP,POLY ++S 3800,300,3800,600,200,*,DOWN,POLY ++S 4600,300,4600,600,200,*,DOWN,POLY ++S 5800,2100,5800,2500,200,*,DOWN,POLY ++S 3000,3000,4000,3000,600,*,RIGHT,ALU1 ++S 3100,1900,3100,3100,600,*,DOWN,ALU1 ++S 3000,2000,3000,3000,400,z,DOWN,CALU1 ++S 4000,3000,4000,7000,400,z,UP,CALU1 ++S 4000,3000,4000,7100,400,*,DOWN,ALU1 ++S 3200,2100,3200,2900,600,*,UP,NDIF ++S 2200,5500,2200,8300,200,1b,UP,PTRANS ++S 5800,6600,5800,9400,200,1a,UP,PTRANS ++S 5800,2500,5800,3900,200,2a,DOWN,NTRANS ++S 4600,5500,4600,9400,200,1z,UP,PTRANS ++S 3400,5500,3400,9400,200,2z,UP,PTRANS ++S 4600,600,4600,3900,200,3z,DOWN,NTRANS ++S 3800,600,3800,3900,200,4z,DOWN,NTRANS ++S 6000,8000,6000,8000,400,a,LEFT,CALU1 ++S 1600,6100,1600,6700,600,*,UP,PDIF ++S 800,6000,3000,6000,400,*,LEFT,ALU1 ++S 3000,4800,3000,6000,400,*,UP,ALU1 ++S 2000,3000,2000,5000,400,b,UP,CALU1 ++S 2000,4000,3100,4000,400,*,RIGHT,ALU1 ++S 3000,4000,3000,4000,400,b,LEFT,CALU1 ++S 2000,2900,2000,5100,400,*,UP,ALU1 ++S 2000,700,2000,2100,400,*,DOWN,ALU1 ++S 1400,4700,1800,4700,200,*,RIGHT,POLY ++S 1600,6000,1600,6900,400,*,DOWN,ALU1 ++V 1600,9300,CONT_BODY_N,* ++V 700,9300,CONT_BODY_N,* ++V 2000,700,CONT_BODY_P,* ++V 1000,700,CONT_BODY_P,* ++V 800,2800,CONT_DIF_N,bn ++V 800,2000,CONT_DIF_N,bn ++V 5200,1000,CONT_DIF_N,* ++V 3200,2000,CONT_DIF_N,* ++V 3000,4900,CONT_POLY,* ++V 5800,6000,CONT_POLY,* ++V 5200,3000,CONT_DIF_N,* ++V 5200,2000,CONT_DIF_N,* ++V 4000,6000,CONT_DIF_P,* ++V 4000,7000,CONT_DIF_P,* ++V 2800,9000,CONT_DIF_P,* ++V 2800,8000,CONT_DIF_P,* ++V 2800,7000,CONT_DIF_P,* ++V 5200,9000,CONT_DIF_P,* ++V 6400,2800,CONT_DIF_N,an ++V 6400,3600,CONT_DIF_N,an ++V 5000,4900,CONT_POLY,an ++V 6400,7000,CONT_DIF_P,an ++V 3200,3000,CONT_DIF_N,* ++V 1600,6800,CONT_DIF_P,bn ++V 1600,6000,CONT_DIF_P,bn ++V 2000,4900,CONT_POLY,* ++V 2000,2000,CONT_DIF_N,* ++EOF +diff --git a/alliance/src/cells/src/msxlib/nd2ab_x2.vbe b/alliance/src/cells/src/msxlib/nd2ab_x2.vbe +new file mode 100644 +index 0000000..0e7a960 +--- /dev/null ++++ b/alliance/src/cells/src/msxlib/nd2ab_x2.vbe +@@ -0,0 +1,32 @@ ++ENTITY nd2ab_x2 IS ++GENERIC ( ++ CONSTANT area : NATURAL := 7000; ++ CONSTANT cin_a : NATURAL := 5; ++ CONSTANT cin_b : NATURAL := 5; ++ CONSTANT rdown_a_z : NATURAL := 1120; ++ CONSTANT rdown_b_z : NATURAL := 1110; ++ CONSTANT rup_a_z : NATURAL := 1520; ++ CONSTANT rup_b_z : NATURAL := 1520; ++ CONSTANT tpll_a_z : NATURAL := 84; ++ CONSTANT tphh_b_z : NATURAL := 73; ++ CONSTANT tpll_b_z : NATURAL := 80; ++ CONSTANT tphh_a_z : NATURAL := 78; ++ CONSTANT transistors : NATURAL := 8 ++); ++PORT ( ++ a : in BIT; ++ b : in BIT; ++ z : out BIT; ++ vdd : in BIT; ++ vss : in BIT ++); ++END nd2ab_x2; ++ ++ARCHITECTURE behaviour_data_flow OF nd2ab_x2 IS ++ ++BEGIN ++ ASSERT ((vdd and not (vss)) = '1') ++ REPORT "power supply is missing on nd2ab_x2" ++ SEVERITY WARNING; ++ z <= (a or b) after 1100 ps; ++END; +diff --git a/alliance/src/cells/src/msxlib/nd3_x05.ap b/alliance/src/cells/src/msxlib/nd3_x05.ap +new file mode 100644 +index 0000000..dc0610f +--- /dev/null ++++ b/alliance/src/cells/src/msxlib/nd3_x05.ap +@@ -0,0 +1,95 @@ ++V ALLIANCE : 6 ++H nd3_x05,P, 8/ 8/2014,100 ++A 0,0,5000,10000 ++R 2000,3000,ref_ref,z_30 ++R 3000,4000,ref_ref,a_40 ++R 3000,5000,ref_ref,c_50 ++R 1000,3000,ref_ref,z_30 ++R 2000,6000,ref_ref,c_60 ++R 4000,6000,ref_ref,b_60 ++R 3000,7000,ref_ref,z_70 ++R 2000,7000,ref_ref,z_70 ++R 2000,5000,ref_ref,c_50 ++R 4000,5000,ref_ref,a_50 ++R 3000,6000,ref_ref,b_60 ++R 1000,7000,ref_ref,z_70 ++R 1000,6000,ref_ref,z_60 ++R 1000,5000,ref_ref,z_50 ++R 1000,4000,ref_ref,z_40 ++R 4000,7000,ref_ref,b_70 ++R 4000,4000,ref_ref,a_40 ++R 3000,3000,ref_ref,a_30 ++R 2000,4000,ref_ref,c_40 ++R 4000,8000,ref_ref,b_80 ++S 1100,9300,1900,9300,600,*,RIGHT,NTIE ++S 1100,700,1900,700,600,*,RIGHT,PTIE ++S 4400,700,4400,3100,400,*,DOWN,ALU1 ++S 3800,2300,3800,2700,200,*,UP,POLY ++S 3000,2300,3000,2700,200,*,UP,POLY ++S 2200,2300,2200,2700,200,*,UP,POLY ++S 1000,2900,2100,2900,400,*,RIGHT,ALU1 ++S 1000,3000,2100,3000,400,*,RIGHT,ALU1 ++S 4400,2900,4400,3700,600,*,UP,NDIF ++S 3800,2700,3800,3900,200,6,UP,NTRANS ++S 3400,2900,3400,3700,600,n1,DOWN,NDIF ++S 3000,2700,3000,3900,200,5,UP,NTRANS ++S 2600,2900,2600,3700,600,n2,UP,NDIF ++S 2200,2700,2200,3900,200,4,UP,NTRANS ++S 1800,2900,1800,3700,400,*,UP,NDIF ++S 3800,3900,3800,7100,200,*,DOWN,POLY ++S 3000,3900,3000,5900,200,*,UP,POLY ++S 2200,3900,2200,4800,200,*,UP,POLY ++S 4000,4000,4000,5100,400,*,DOWN,ALU1 ++S 4000,4000,4000,5000,400,a,DOWN,CALU1 ++S 1400,5200,1400,7100,200,*,DOWN,POLY ++S 1400,5200,1800,5200,200,*,LEFT,POLY ++S 2600,5800,2600,7100,200,*,DOWN,POLY ++S 3200,7000,3200,7500,400,*,DOWN,ALU1 ++S 3800,8300,3800,8700,200,*,DOWN,POLY ++S 2600,8300,2600,8700,200,*,DOWN,POLY ++S 2000,7300,2000,8100,600,*,DOWN,PDIF ++S 3200,7300,3200,8100,1000,*,UP,PDIF ++S 3800,7100,3800,8300,200,3,DOWN,PTRANS ++S 2600,7100,2600,8300,200,2,DOWN,PTRANS ++S 1000,7300,1000,8100,400,*,UP,PDIF ++S 1400,7100,1400,8300,200,1,DOWN,PTRANS ++S 1400,8300,1400,8700,200,*,DOWN,POLY ++S 3000,6000,4000,6000,600,*,RIGHT,ALU1 ++S 2000,7900,2000,9300,400,*,DOWN,ALU1 ++S 0,600,5000,600,1200,vss,RIGHT,CALU1 ++S 0,5000,5000,5000,10000,nd3_x05,LEFT,TALU8 ++S 0,2200,5000,2200,5200,*,LEFT,PWELL ++S 0,7600,5000,7600,5600,*,LEFT,NWELL ++S 0,9400,5000,9400,1200,vdd,RIGHT,CALU1 ++S 800,7000,3200,7000,400,*,LEFT,ALU1 ++S 900,7000,900,7500,600,*,DOWN,ALU1 ++S 3000,3000,3000,4000,400,a,UP,CALU1 ++S 3000,4000,4000,4000,600,*,RIGHT,ALU1 ++S 3000,2900,3000,4000,400,*,DOWN,ALU1 ++S 2000,4000,2000,6000,400,c,DOWN,CALU1 ++S 2000,3900,2000,6100,400,*,UP,ALU1 ++S 2000,5000,3000,5000,600,*,LEFT,ALU1 ++S 4000,6000,4000,8100,400,*,UP,ALU1 ++S 4000,6000,4000,8000,400,b,UP,CALU1 ++S 4400,7300,4400,9100,600,*,DOWN,PDIF ++S 2000,7000,2000,7000,400,z,LEFT,CALU1 ++S 3000,7000,3000,7000,400,z,LEFT,CALU1 ++S 2000,3000,2000,3000,400,z,LEFT,CALU1 ++S 1000,3000,1000,7000,400,z,DOWN,CALU1 ++S 1000,3000,1000,7500,400,*,DOWN,ALU1 ++S 3000,6000,3000,6000,400,b,LEFT,CALU1 ++S 3000,5000,3000,5000,400,c,LEFT,CALU1 ++V 2000,9300,CONT_BODY_N,* ++V 1000,9300,CONT_BODY_N,* ++V 2000,700,CONT_BODY_P,* ++V 1000,700,CONT_BODY_P,* ++V 1600,3000,CONT_DIF_N,* ++V 4400,3000,CONT_DIF_N,* ++V 4000,4500,CONT_POLY,* ++V 2000,5000,CONT_POLY,* ++V 3200,7400,CONT_DIF_P,* ++V 800,7400,CONT_DIF_P,* ++V 3000,6000,CONT_POLY,* ++V 2000,8000,CONT_DIF_P,* ++V 4400,9000,CONT_DIF_P,* ++EOF +diff --git a/alliance/src/cells/src/msxlib/nd3_x05.vbe b/alliance/src/cells/src/msxlib/nd3_x05.vbe +new file mode 100644 +index 0000000..b18016d +--- /dev/null ++++ b/alliance/src/cells/src/msxlib/nd3_x05.vbe +@@ -0,0 +1,38 @@ ++ENTITY nd3_x05 IS ++GENERIC ( ++ CONSTANT area : NATURAL := 5000; ++ CONSTANT cin_a : NATURAL := 3; ++ CONSTANT cin_b : NATURAL := 3; ++ CONSTANT cin_c : NATURAL := 3; ++ CONSTANT rdown_a_z : NATURAL := 4240; ++ CONSTANT rdown_b_z : NATURAL := 4240; ++ CONSTANT rdown_c_z : NATURAL := 4240; ++ CONSTANT rup_a_z : NATURAL := 4940; ++ CONSTANT rup_b_z : NATURAL := 4940; ++ CONSTANT rup_c_z : NATURAL := 4950; ++ CONSTANT tphl_a_z : NATURAL := 47; ++ CONSTANT tphl_b_z : NATURAL := 46; ++ CONSTANT tphl_c_z : NATURAL := 43; ++ CONSTANT tplh_c_z : NATURAL := 54; ++ CONSTANT tplh_b_z : NATURAL := 62; ++ CONSTANT tplh_a_z : NATURAL := 69; ++ CONSTANT transistors : NATURAL := 6 ++); ++PORT ( ++ a : in BIT; ++ b : in BIT; ++ c : in BIT; ++ z : out BIT; ++ vdd : in BIT; ++ vss : in BIT ++); ++END nd3_x05; ++ ++ARCHITECTURE behaviour_data_flow OF nd3_x05 IS ++ ++BEGIN ++ ASSERT ((vdd and not (vss)) = '1') ++ REPORT "power supply is missing on nd3_x05" ++ SEVERITY WARNING; ++ z <= not (((a and b) and c)) after 1000 ps; ++END; +diff --git a/alliance/src/cells/src/msxlib/nd3_x1.ap b/alliance/src/cells/src/msxlib/nd3_x1.ap +new file mode 100644 +index 0000000..5e402ae +--- /dev/null ++++ b/alliance/src/cells/src/msxlib/nd3_x1.ap +@@ -0,0 +1,101 @@ ++V ALLIANCE : 6 ++H nd3_x1,P, 8/ 8/2014,100 ++A 0,0,5000,10000 ++R 3000,8000,ref_ref,z_80 ++R 4000,4000,ref_ref,a_40 ++R 4000,7000,ref_ref,b_70 ++R 1000,4000,ref_ref,z_40 ++R 1000,5000,ref_ref,z_50 ++R 1000,6000,ref_ref,z_60 ++R 1000,7000,ref_ref,z_70 ++R 3000,4000,ref_ref,c_40 ++R 3000,6000,ref_ref,b_60 ++R 4000,5000,ref_ref,a_50 ++R 2000,5000,ref_ref,c_50 ++R 2000,7000,ref_ref,z_70 ++R 3000,7000,ref_ref,z_70 ++R 4000,6000,ref_ref,b_60 ++R 2000,6000,ref_ref,c_60 ++R 2000,4000,ref_ref,c_40 ++R 3000,5000,ref_ref,b_50 ++R 4000,3000,ref_ref,a_30 ++R 3000,3000,ref_ref,a_30 ++R 1000,3000,ref_ref,z_30 ++R 1000,2000,ref_ref,z_20 ++R 2000,2000,ref_ref,z_20 ++R 2000,3000,ref_ref,a_30 ++S 1100,9300,1900,9300,600,*,RIGHT,NTIE ++S 1100,700,1900,700,600,*,RIGHT,PTIE ++S 3000,3000,3000,3000,400,a,LEFT,CALU1 ++S 3000,4000,3000,4000,400,c,LEFT,CALU1 ++S 2000,3000,2000,3000,400,a,LEFT,CALU1 ++S 2000,2000,2000,2000,400,z,LEFT,CALU1 ++S 2000,7000,2000,7000,400,z,LEFT,CALU1 ++S 3000,7000,3000,8000,400,z,DOWN,CALU1 ++S 3100,6900,3100,8100,600,*,DOWN,ALU1 ++S 0,9400,5000,9400,1200,vdd,RIGHT,CALU1 ++S 0,5000,5000,5000,10000,nd3_x1,LEFT,TALU8 ++S 0,2200,5000,2200,5200,*,LEFT,PWELL ++S 0,7600,5000,7600,5600,*,LEFT,NWELL ++S 0,600,5000,600,1200,vss,RIGHT,CALU1 ++S 1000,6600,1000,8200,400,*,UP,PDIF ++S 1400,6400,1400,8400,200,1,DOWN,PTRANS ++S 2600,6400,2600,8400,200,2,DOWN,PTRANS ++S 2000,6600,2000,8200,1000,*,DOWN,PDIF ++S 3800,6400,3800,8400,200,3,DOWN,PTRANS ++S 3200,6600,3200,8200,1000,*,UP,PDIF ++S 4400,6600,4400,8200,600,*,UP,PDIF ++S 1400,8400,1400,8800,200,*,DOWN,POLY ++S 2600,8400,2600,8800,200,*,DOWN,POLY ++S 3800,8400,3800,8800,200,*,DOWN,POLY ++S 2000,7900,2000,9300,400,*,DOWN,ALU1 ++S 4400,7900,4400,9300,400,*,DOWN,ALU1 ++S 700,7000,3200,7000,600,*,LEFT,ALU1 ++S 4000,6000,4000,7100,400,*,UP,ALU1 ++S 4000,6000,4000,7000,400,b,UP,CALU1 ++S 1400,4700,1400,6400,200,*,DOWN,POLY ++S 2000,4000,2000,6000,400,c,DOWN,CALU1 ++S 2000,4000,2000,6100,400,*,DOWN,ALU1 ++S 2000,4000,3000,4000,600,*,RIGHT,ALU1 ++S 3000,5000,3000,6000,400,b,UP,CALU1 ++S 3000,4900,3000,6000,400,*,UP,ALU1 ++S 3000,6000,4000,6000,600,*,RIGHT,ALU1 ++S 4000,3000,4000,5000,400,a,DOWN,CALU1 ++S 3800,1300,3800,1600,200,*,UP,POLY ++S 3800,1700,3800,3700,200,6,UP,NTRANS ++S 3000,1300,3000,1600,200,*,UP,POLY ++S 3000,1700,3000,3700,200,5,UP,NTRANS ++S 2200,1300,2200,1600,200,*,UP,POLY ++S 2200,1700,2200,3700,200,4,UP,NTRANS ++S 1800,1900,1800,3500,400,*,UP,NDIF ++S 2600,1900,2600,3500,600,n2,UP,NDIF ++S 3400,1900,3400,3500,600,n1,DOWN,NDIF ++S 4400,1900,4400,3500,600,*,UP,NDIF ++S 4400,700,4400,2100,400,*,DOWN,ALU1 ++S 1000,2000,2100,2000,400,*,RIGHT,ALU1 ++S 1000,2000,1000,7000,400,*,DOWN,ALU1 ++S 1000,2000,1000,7000,400,z,DOWN,CALU1 ++S 1900,3000,4000,3000,400,*,RIGHT,ALU1 ++S 4000,3000,4000,5100,400,*,DOWN,ALU1 ++S 1900,2900,4000,2900,400,*,RIGHT,ALU1 ++S 2200,3700,2200,4300,200,*,UP,POLY ++S 3800,3700,3800,6400,200,*,UP,POLY ++S 3000,3700,3000,5600,200,*,UP,POLY ++S 2600,5600,2600,6400,200,*,DOWN,POLY ++S 1400,4600,1800,4600,200,*,LEFT,POLY ++S 1000,1900,2100,1900,400,*,RIGHT,ALU1 ++V 2000,9300,CONT_BODY_N,* ++V 1000,9300,CONT_BODY_N,* ++V 2000,700,CONT_BODY_P,* ++V 1000,700,CONT_BODY_P,* ++V 3200,8000,CONT_DIF_P,* ++V 3200,7000,CONT_DIF_P,* ++V 4400,8000,CONT_DIF_P,* ++V 2000,8000,CONT_DIF_P,* ++V 800,7000,CONT_DIF_P,* ++V 3000,5800,CONT_POLY,* ++V 4400,2000,CONT_DIF_N,* ++V 1600,2000,CONT_DIF_N,* ++V 4000,4400,CONT_POLY,* ++V 2000,4400,CONT_POLY,* ++EOF +diff --git a/alliance/src/cells/src/msxlib/nd3_x1.vbe b/alliance/src/cells/src/msxlib/nd3_x1.vbe +new file mode 100644 +index 0000000..4ed7287 +--- /dev/null ++++ b/alliance/src/cells/src/msxlib/nd3_x1.vbe +@@ -0,0 +1,38 @@ ++ENTITY nd3_x1 IS ++GENERIC ( ++ CONSTANT area : NATURAL := 5000; ++ CONSTANT cin_a : NATURAL := 5; ++ CONSTANT cin_b : NATURAL := 5; ++ CONSTANT cin_c : NATURAL := 5; ++ CONSTANT rdown_a_z : NATURAL := 2540; ++ CONSTANT rdown_b_z : NATURAL := 2540; ++ CONSTANT rdown_c_z : NATURAL := 2540; ++ CONSTANT rup_a_z : NATURAL := 2960; ++ CONSTANT rup_b_z : NATURAL := 2960; ++ CONSTANT rup_c_z : NATURAL := 2960; ++ CONSTANT tphl_a_z : NATURAL := 45; ++ CONSTANT tphl_b_z : NATURAL := 44; ++ CONSTANT tphl_c_z : NATURAL := 41; ++ CONSTANT tplh_c_z : NATURAL := 52; ++ CONSTANT tplh_b_z : NATURAL := 59; ++ CONSTANT tplh_a_z : NATURAL := 67; ++ CONSTANT transistors : NATURAL := 6 ++); ++PORT ( ++ a : in BIT; ++ b : in BIT; ++ c : in BIT; ++ z : out BIT; ++ vdd : in BIT; ++ vss : in BIT ++); ++END nd3_x1; ++ ++ARCHITECTURE behaviour_data_flow OF nd3_x1 IS ++ ++BEGIN ++ ASSERT ((vdd and not (vss)) = '1') ++ REPORT "power supply is missing on nd3_x1" ++ SEVERITY WARNING; ++ z <= not (((a and b) and c)) after 1000 ps; ++END; +diff --git a/alliance/src/cells/src/msxlib/nd3_x2.ap b/alliance/src/cells/src/msxlib/nd3_x2.ap +new file mode 100644 +index 0000000..56de21a +--- /dev/null ++++ b/alliance/src/cells/src/msxlib/nd3_x2.ap +@@ -0,0 +1,100 @@ ++V ALLIANCE : 6 ++H nd3_x2,P, 8/ 8/2014,100 ++A 0,0,5000,10000 ++R 3000,8000,ref_ref,z_80 ++R 3000,7000,ref_ref,z_70 ++R 2000,7000,ref_ref,z_70 ++R 2000,5000,ref_ref,c_50 ++R 4000,5000,ref_ref,a_50 ++R 3000,6000,ref_ref,b_60 ++R 3000,4000,ref_ref,c_40 ++R 1000,7000,ref_ref,z_70 ++R 1000,6000,ref_ref,z_60 ++R 1000,5000,ref_ref,z_50 ++R 1000,4000,ref_ref,z_40 ++R 4000,3000,ref_ref,a_30 ++R 4000,4000,ref_ref,a_40 ++R 1000,3000,ref_ref,z_30 ++R 2000,4000,ref_ref,c_40 ++R 3000,3000,ref_ref,a_30 ++R 4000,6000,ref_ref,b_60 ++R 4000,7000,ref_ref,b_70 ++R 2000,6000,ref_ref,c_60 ++R 1000,2000,ref_ref,z_20 ++R 2000,3000,ref_ref,a_30 ++R 3000,5000,ref_ref,b_50 ++S 2000,3000,2000,3000,400,a,LEFT,CALU1 ++S 3000,3000,3000,3000,400,a,LEFT,CALU1 ++S 3000,4000,3000,4000,400,c,LEFT,CALU1 ++S 2000,7000,2000,7000,400,z,LEFT,CALU1 ++S 3000,3900,3000,5600,200,*,UP,POLY ++S 3800,3900,3800,6100,200,*,DOWN,POLY ++S 2600,5300,2600,6100,200,*,DOWN,POLY ++S 1400,4700,1400,6100,200,*,DOWN,POLY ++S 3000,7000,3000,8000,400,z,UP,CALU1 ++S 3100,7000,3100,8100,600,*,DOWN,ALU1 ++S 1000,2000,1000,7000,400,z,DOWN,CALU1 ++S 900,6300,900,7300,600,*,UP,ALU1 ++S 800,6500,800,7300,600,*,UP,PDIF ++S 1800,800,1800,3700,400,*,UP,NDIF ++S 4400,800,4400,3700,600,*,UP,NDIF ++S 0,600,5000,600,1200,vss,RIGHT,CALU1 ++S 0,5000,5000,5000,10000,nd3_x2,LEFT,TALU8 ++S 0,2200,5000,2200,5200,*,LEFT,PWELL ++S 0,7600,5000,7600,5600,*,LEFT,NWELL ++S 0,9400,5000,9400,1200,vdd,RIGHT,CALU1 ++S 3800,300,3800,600,200,*,UP,POLY ++S 3000,300,3000,600,200,*,UP,POLY ++S 2200,300,2200,600,200,*,UP,POLY ++S 1400,4700,1800,4700,200,*,LEFT,POLY ++S 3400,800,3400,3700,600,n1,DOWN,NDIF ++S 2600,800,2600,3700,600,n2,UP,NDIF ++S 4400,700,4400,2100,400,*,DOWN,ALU1 ++S 2000,4000,3000,4000,600,*,RIGHT,ALU1 ++S 4000,3000,4000,5100,400,*,DOWN,ALU1 ++S 4000,3000,4000,5000,400,a,DOWN,CALU1 ++S 4000,6000,4000,7100,400,*,UP,ALU1 ++S 3000,6000,4000,6000,400,*,LEFT,ALU1 ++S 3000,5900,4000,5900,400,*,LEFT,ALU1 ++S 2000,4000,2000,6000,400,c,DOWN,CALU1 ++S 2000,4000,2000,6100,400,*,DOWN,ALU1 ++S 1000,2000,1600,2000,600,*,RIGHT,ALU1 ++S 1900,2900,4000,2900,400,*,LEFT,ALU1 ++S 1900,3000,4000,3000,400,*,LEFT,ALU1 ++S 3000,5000,3000,6000,600,*,UP,ALU1 ++S 3000,5000,3000,6000,400,b,DOWN,CALU1 ++S 1000,7000,3200,7000,400,*,LEFT,ALU1 ++S 1000,2000,1000,7000,400,*,DOWN,ALU1 ++S 2600,9400,2600,9700,200,*,DOWN,POLY ++S 1400,9400,1400,9700,200,*,DOWN,POLY ++S 3800,9400,3800,9700,200,*,DOWN,POLY ++S 2000,7900,2000,9300,400,*,DOWN,ALU1 ++S 4400,7900,4400,9300,400,*,DOWN,ALU1 ++S 1000,6900,3200,6900,400,*,LEFT,ALU1 ++S 1000,6300,1000,9200,400,*,UP,PDIF ++S 2000,6300,2000,9200,1000,*,DOWN,PDIF ++S 3200,6300,3200,9200,400,*,UP,PDIF ++S 4400,6300,4400,9200,600,*,DOWN,PDIF ++S 3800,6100,3800,9400,200,1a,DOWN,PTRANS ++S 2600,6100,2600,9400,200,1b,DOWN,PTRANS ++S 1400,6100,1400,9400,200,1z,DOWN,PTRANS ++S 3800,600,3800,3900,200,2a,UP,NTRANS ++S 3000,600,3000,3900,200,2b,UP,NTRANS ++S 2200,600,2200,3900,200,2c,UP,NTRANS ++S 4000,6000,4000,7000,400,b,UP,CALU1 ++V 700,700,CONT_BODY_P,* ++V 800,7200,CONT_DIF_P,* ++V 800,6400,CONT_DIF_P,* ++V 4000,5000,CONT_POLY,* ++V 1600,2000,CONT_DIF_N,* ++V 2000,4500,CONT_POLY,* ++V 4400,1000,CONT_DIF_N,* ++V 4400,2000,CONT_DIF_N,* ++V 3200,7000,CONT_DIF_P,* ++V 3200,8000,CONT_DIF_P,* ++V 2000,8000,CONT_DIF_P,* ++V 4400,8000,CONT_DIF_P,* ++V 4400,9000,CONT_DIF_P,* ++V 2000,9000,CONT_DIF_P,* ++V 3000,5500,CONT_POLY,* ++EOF +diff --git a/alliance/src/cells/src/msxlib/nd3_x2.vbe b/alliance/src/cells/src/msxlib/nd3_x2.vbe +new file mode 100644 +index 0000000..f23d898 +--- /dev/null ++++ b/alliance/src/cells/src/msxlib/nd3_x2.vbe +@@ -0,0 +1,38 @@ ++ENTITY nd3_x2 IS ++GENERIC ( ++ CONSTANT area : NATURAL := 5000; ++ CONSTANT cin_a : NATURAL := 7; ++ CONSTANT cin_b : NATURAL := 7; ++ CONSTANT cin_c : NATURAL := 7; ++ CONSTANT rdown_a_z : NATURAL := 1540; ++ CONSTANT rdown_b_z : NATURAL := 1540; ++ CONSTANT rdown_c_z : NATURAL := 1540; ++ CONSTANT rup_a_z : NATURAL := 1800; ++ CONSTANT rup_b_z : NATURAL := 1790; ++ CONSTANT rup_c_z : NATURAL := 1800; ++ CONSTANT tphl_a_z : NATURAL := 43; ++ CONSTANT tphl_b_z : NATURAL := 42; ++ CONSTANT tphl_c_z : NATURAL := 39; ++ CONSTANT tplh_c_z : NATURAL := 50; ++ CONSTANT tplh_b_z : NATURAL := 58; ++ CONSTANT tplh_a_z : NATURAL := 64; ++ CONSTANT transistors : NATURAL := 6 ++); ++PORT ( ++ a : in BIT; ++ b : in BIT; ++ c : in BIT; ++ z : out BIT; ++ vdd : in BIT; ++ vss : in BIT ++); ++END nd3_x2; ++ ++ARCHITECTURE behaviour_data_flow OF nd3_x2 IS ++ ++BEGIN ++ ASSERT ((vdd and not (vss)) = '1') ++ REPORT "power supply is missing on nd3_x2" ++ SEVERITY WARNING; ++ z <= not (((a and b) and c)) after 1000 ps; ++END; +diff --git a/alliance/src/cells/src/msxlib/nd3_x4.ap b/alliance/src/cells/src/msxlib/nd3_x4.ap +new file mode 100644 +index 0000000..1c3f183 +--- /dev/null ++++ b/alliance/src/cells/src/msxlib/nd3_x4.ap +@@ -0,0 +1,166 @@ ++V ALLIANCE : 6 ++H nd3_x4,P, 8/ 8/2014,100 ++A 0,0,9000,10000 ++R 7000,7000,ref_ref,z_70 ++R 2000,8000,ref_ref,z_80 ++R 3000,7000,ref_ref,z_70 ++R 2000,7000,ref_ref,z_70 ++R 2000,5000,ref_ref,c_50 ++R 4000,5000,ref_ref,a_50 ++R 3000,6000,ref_ref,b_60 ++R 1000,6000,ref_ref,z_60 ++R 1000,5000,ref_ref,z_50 ++R 1000,4000,ref_ref,z_40 ++R 4000,7000,ref_ref,z_70 ++R 5000,7000,ref_ref,z_70 ++R 6000,7000,ref_ref,z_70 ++R 7000,5000,ref_ref,c_50 ++R 5000,5000,ref_ref,a_50 ++R 4000,6000,ref_ref,b_60 ++R 5000,6000,ref_ref,b_60 ++R 7000,6000,ref_ref,c_60 ++R 6000,3000,ref_ref,c_30 ++R 6000,5000,ref_ref,b_50 ++R 3000,5000,ref_ref,b_50 ++R 2000,6000,ref_ref,z_60 ++R 2000,4000,ref_ref,c_40 ++R 7000,4000,ref_ref,c_40 ++R 6000,6000,ref_ref,b_60 ++R 1000,3000,ref_ref,z_30 ++R 7000,3000,ref_ref,c_30 ++R 1000,2000,ref_ref,z_20 ++R 2000,2000,ref_ref,z_20 ++R 3000,2000,ref_ref,z_20 ++R 4000,2000,ref_ref,z_20 ++R 5000,3000,ref_ref,c_30 ++R 4000,3000,ref_ref,c_30 ++R 3000,3000,ref_ref,c_30 ++R 2000,3000,ref_ref,c_30 ++R 3000,4000,ref_ref,b_40 ++R 5000,4000,ref_ref,a_40 ++S 1000,6000,2000,6000,600,*,RIGHT,ALU1 ++S 6000,3000,6000,3000,400,c,LEFT,CALU1 ++S 5000,3000,5000,3000,400,c,LEFT,CALU1 ++S 4000,3000,4000,3000,400,c,LEFT,CALU1 ++S 3000,3000,3000,3000,400,c,LEFT,CALU1 ++S 4000,5000,4000,5000,400,a,LEFT,CALU1 ++S 5000,6000,5000,6000,400,b,LEFT,CALU1 ++S 4000,6000,4000,6000,400,b,LEFT,CALU1 ++S 8000,6900,8000,9300,400,*,DOWN,ALU1 ++S 800,6900,800,9300,400,*,DOWN,ALU1 ++S 3200,7900,3200,9300,400,*,DOWN,ALU1 ++S 5600,7900,5600,9300,400,*,DOWN,ALU1 ++S 2000,7000,7100,7000,400,*,LEFT,ALU1 ++S 6800,7000,6800,8100,400,*,DOWN,ALU1 ++S 7000,7000,7000,7000,400,z,LEFT,CALU1 ++S 6000,7000,6000,7000,400,z,LEFT,CALU1 ++S 5000,7000,5000,7000,400,z,LEFT,CALU1 ++S 4000,7000,4000,7000,400,z,LEFT,CALU1 ++S 3000,7000,3000,7000,400,z,LEFT,CALU1 ++S 4000,2000,4000,2000,400,z,LEFT,CALU1 ++S 3000,2000,3000,2000,400,z,LEFT,CALU1 ++S 2000,2000,2000,2000,400,z,LEFT,CALU1 ++S 1000,1900,4500,1900,400,*,RIGHT,ALU1 ++S 2600,5500,2600,6000,200,*,DOWN,POLY ++S 6600,3900,6600,4400,200,*,UP,POLY ++S 1800,800,1800,3700,400,*,UP,NDIF ++S 4400,800,4400,3700,600,*,UP,NDIF ++S 3800,300,3800,600,200,*,UP,POLY ++S 3000,300,3000,600,200,*,UP,POLY ++S 2200,300,2200,600,200,*,UP,POLY ++S 3800,9200,3800,9700,200,*,DOWN,POLY ++S 2600,9200,2600,9700,200,*,DOWN,POLY ++S 1400,9200,1400,9700,200,*,DOWN,POLY ++S 1400,4700,1800,4700,200,*,LEFT,POLY ++S 5000,9200,5000,9700,200,*,DOWN,POLY ++S 6200,9200,6200,9700,200,*,DOWN,POLY ++S 7400,9200,7400,9700,200,*,DOWN,POLY ++S 0,9400,9000,9400,1200,vdd,RIGHT,CALU1 ++S 0,5000,9000,5000,10000,nd3_x4,LEFT,TALU8 ++S 0,2200,9000,2200,5200,*,LEFT,PWELL ++S 0,7600,9000,7600,5600,*,LEFT,NWELL ++S 0,600,9000,600,1200,vss,RIGHT,CALU1 ++S 1600,800,1600,3700,800,*,UP,NDIF ++S 3800,5000,5000,5000,600,*,RIGHT,POLY ++S 5000,600,5000,3900,200,10,UP,NTRANS ++S 5800,600,5800,3900,200,11,UP,NTRANS ++S 6600,600,6600,3900,200,12,UP,NTRANS ++S 3800,600,3800,3900,200,09,UP,NTRANS ++S 3000,600,3000,3900,200,08,UP,NTRANS ++S 2200,600,2200,3900,200,07,UP,NTRANS ++S 2600,800,2600,3700,600,n1,UP,NDIF ++S 3400,800,3400,3700,600,n2,DOWN,NDIF ++S 5400,800,5400,3700,600,n4,DOWN,NDIF ++S 6200,800,6200,3700,600,n3,DOWN,NDIF ++S 4400,7000,4400,8100,400,*,DOWN,ALU1 ++S 2000,6000,2000,8000,400,z,UP,CALU1 ++S 2000,6000,2000,8100,400,*,DOWN,ALU1 ++S 1400,6000,1400,9300,200,01,DOWN,PTRANS ++S 800,6200,800,9100,800,*,UP,PDIF ++S 2600,6000,2600,9300,200,02,DOWN,PTRANS ++S 2000,6200,2000,9100,1000,*,DOWN,PDIF ++S 3200,6200,3200,9100,400,*,UP,PDIF ++S 3800,6000,3800,9300,200,03,DOWN,PTRANS ++S 4400,6200,4400,9100,400,*,UP,PDIF ++S 5000,6000,5000,9300,200,04,DOWN,PTRANS ++S 5600,6200,5600,9100,400,*,UP,PDIF ++S 6200,6000,6200,9300,200,05,DOWN,PTRANS ++S 7400,6000,7400,9300,200,06,DOWN,PTRANS ++S 6800,6200,6800,9100,400,*,UP,PDIF ++S 8000,6200,8000,9100,800,*,UP,PDIF ++S 1400,4700,1400,6000,200,*,DOWN,POLY ++S 7400,4300,7400,6000,200,*,DOWN,POLY ++S 5800,3900,5800,5600,200,*,UP,POLY ++S 5000,3900,5000,6000,200,*,DOWN,POLY ++S 3800,3900,3800,6000,200,*,DOWN,POLY ++S 3000,3900,3000,5600,200,*,UP,POLY ++S 6000,5000,6000,6000,600,*,UP,ALU1 ++S 3000,6000,6000,6000,400,*,RIGHT,ALU1 ++S 6000,5000,6000,6000,400,b,DOWN,CALU1 ++S 7200,700,7200,2100,400,*,DOWN,ALU1 ++S 7000,3000,7000,6100,400,*,UP,ALU1 ++S 7000,3000,7000,6000,400,c,DOWN,CALU1 ++S 7100,3000,7100,6100,400,*,UP,ALU1 ++S 1000,2000,1000,6000,400,*,DOWN,ALU1 ++S 1000,2000,1000,6000,400,z,DOWN,CALU1 ++S 2000,3000,2000,5000,400,c,DOWN,CALU1 ++S 2000,3000,2000,5000,600,*,DOWN,ALU1 ++S 2000,3000,7000,3000,400,*,RIGHT,ALU1 ++S 1000,2000,4500,2000,400,*,RIGHT,ALU1 ++S 3000,4000,3000,6000,400,b,UP,CALU1 ++S 4000,5000,5000,5000,600,*,RIGHT,ALU1 ++S 5000,4000,5000,5000,400,a,DOWN,CALU1 ++S 5000,3900,5000,5000,400,*,UP,ALU1 ++S 2900,3900,2900,6000,400,*,DOWN,ALU1 ++S 3000,3900,3000,6000,400,*,DOWN,ALU1 ++S 5000,300,5000,600,200,*,UP,POLY ++S 5800,300,5800,600,200,*,UP,POLY ++S 6600,300,6600,600,200,*,UP,POLY ++S 7200,800,7200,3700,600,*,UP,NDIF ++V 8300,700,CONT_BODY_P,* ++V 800,7000,CONT_DIF_P,* ++V 800,8000,CONT_DIF_P,* ++V 3200,8000,CONT_DIF_P,* ++V 5600,8000,CONT_DIF_P,* ++V 8000,8000,CONT_DIF_P,* ++V 8000,7000,CONT_DIF_P,* ++V 2000,4500,CONT_POLY,* ++V 4400,5000,CONT_POLY,* ++V 6800,8000,CONT_DIF_P,* ++V 2000,8000,CONT_DIF_P,* ++V 4400,7000,CONT_DIF_P,* ++V 2000,7000,CONT_DIF_P,* ++V 4400,8000,CONT_DIF_P,* ++V 6800,7000,CONT_DIF_P,* ++V 4400,2000,CONT_DIF_N,* ++V 7000,4500,CONT_POLY,* ++V 3000,5400,CONT_POLY,* ++V 6000,5400,CONT_POLY,* ++V 8000,9000,CONT_DIF_P,* ++V 5600,9000,CONT_DIF_P,* ++V 3200,9000,CONT_DIF_P,* ++V 800,9000,CONT_DIF_P,* ++V 7200,2000,CONT_DIF_N,* ++V 7200,1000,CONT_DIF_N,* ++V 1600,1000,CONT_DIF_N,* ++EOF +diff --git a/alliance/src/cells/src/msxlib/nd3_x4.vbe b/alliance/src/cells/src/msxlib/nd3_x4.vbe +new file mode 100644 +index 0000000..a46b93f +--- /dev/null ++++ b/alliance/src/cells/src/msxlib/nd3_x4.vbe +@@ -0,0 +1,38 @@ ++ENTITY nd3_x4 IS ++GENERIC ( ++ CONSTANT area : NATURAL := 9000; ++ CONSTANT cin_a : NATURAL := 13; ++ CONSTANT cin_b : NATURAL := 15; ++ CONSTANT cin_c : NATURAL := 15; ++ CONSTANT rdown_a_z : NATURAL := 770; ++ CONSTANT rdown_b_z : NATURAL := 770; ++ CONSTANT rdown_c_z : NATURAL := 770; ++ CONSTANT rup_a_z : NATURAL := 900; ++ CONSTANT rup_b_z : NATURAL := 900; ++ CONSTANT rup_c_z : NATURAL := 900; ++ CONSTANT tphl_a_z : NATURAL := 37; ++ CONSTANT tphl_b_z : NATURAL := 41; ++ CONSTANT tphl_c_z : NATURAL := 42; ++ CONSTANT tplh_c_z : NATURAL := 63; ++ CONSTANT tplh_b_z : NATURAL := 56; ++ CONSTANT tplh_a_z : NATURAL := 48; ++ CONSTANT transistors : NATURAL := 12 ++); ++PORT ( ++ a : in BIT; ++ b : in BIT; ++ c : in BIT; ++ z : out BIT; ++ vdd : in BIT; ++ vss : in BIT ++); ++END nd3_x4; ++ ++ARCHITECTURE behaviour_data_flow OF nd3_x4 IS ++ ++BEGIN ++ ASSERT ((vdd and not (vss)) = '1') ++ REPORT "power supply is missing on nd3_x4" ++ SEVERITY WARNING; ++ z <= not (((a and b) and c)) after 1000 ps; ++END; +diff --git a/alliance/src/cells/src/msxlib/nd4_x05.ap b/alliance/src/cells/src/msxlib/nd4_x05.ap +new file mode 100644 +index 0000000..ff25b3e +--- /dev/null ++++ b/alliance/src/cells/src/msxlib/nd4_x05.ap +@@ -0,0 +1,122 @@ ++V ALLIANCE : 6 ++H nd4_x05,P, 8/ 8/2014,100 ++A 0,0,6000,10000 ++R 5000,5000,ref_ref,b_50 ++R 4000,2000,ref_ref,a_20 ++R 4000,3000,ref_ref,a_30 ++R 5000,6000,ref_ref,b_60 ++R 1000,3000,ref_ref,z_30 ++R 3000,5000,ref_ref,c_50 ++R 2000,4000,ref_ref,d_40 ++R 1000,7000,ref_ref,z_70 ++R 2000,7000,ref_ref,z_70 ++R 1000,5000,ref_ref,z_50 ++R 4000,7000,ref_ref,z_70 ++R 1000,6000,ref_ref,z_60 ++R 2000,5000,ref_ref,d_50 ++R 3000,6000,ref_ref,c_60 ++R 2000,6000,ref_ref,c_60 ++R 4000,6000,ref_ref,b_60 ++R 1000,4000,ref_ref,z_40 ++R 3000,7000,ref_ref,z_70 ++R 5000,7000,ref_ref,b_70 ++R 5000,4000,ref_ref,a_40 ++R 3000,3000,ref_ref,d_30 ++R 1000,2000,ref_ref,z_20 ++R 2000,2000,ref_ref,z_20 ++R 2000,3000,ref_ref,d_30 ++R 3000,4000,ref_ref,c_40 ++R 4000,4000,ref_ref,a_40 ++S 1100,9300,1900,9300,600,*,LEFT,NTIE ++S 1100,700,1900,700,600,*,RIGHT,PTIE ++S 5000,4900,5000,7100,400,*,UP,ALU1 ++S 5000,5000,5000,7000,400,b,UP,CALU1 ++S 4800,4200,4800,6900,200,*,DOWN,POLY ++S 4600,3300,4600,4200,200,*,UP,POLY ++S 3900,5900,5000,5900,400,*,RIGHT,ALU1 ++S 5200,1800,5200,3100,800,*,UP,NDIF ++S 4600,1200,4600,1600,200,*,DOWN,POLY ++S 3800,1200,3800,1600,200,*,DOWN,POLY ++S 3000,1200,3000,1600,200,*,DOWN,POLY ++S 2200,1200,2200,1600,200,*,DOWN,POLY ++S 2200,3300,2200,4600,200,*,UP,POLY ++S 3000,3300,3000,6200,200,*,UP,POLY ++S 3800,3300,3800,5700,200,*,UP,POLY ++S 1800,1800,1800,3100,400,*,UP,NDIF ++S 3400,1800,3400,3100,600,n2,UP,NDIF ++S 4600,1600,4600,3300,200,8,DOWN,NTRANS ++S 3800,1600,3800,3300,200,7,DOWN,NTRANS ++S 4200,1800,4200,3100,600,n1,UP,NDIF ++S 3000,1600,3000,3300,200,6,DOWN,NTRANS ++S 2200,1600,2200,3300,200,5,DOWN,NTRANS ++S 2600,1800,2600,3100,600,n3,UP,NDIF ++S 5400,7900,5400,9300,400,*,UP,ALU1 ++S 3000,7900,3000,9300,400,*,UP,ALU1 ++S 600,7900,600,9300,400,*,UP,ALU1 ++S 0,9400,6000,9400,1200,vdd,RIGHT,CALU1 ++S 3600,5800,3600,6900,200,*,DOWN,POLY ++S 2400,5800,2400,6900,200,*,DOWN,POLY ++S 1200,5200,1200,6900,200,*,DOWN,POLY ++S 1000,7000,4200,7000,400,*,LEFT,ALU1 ++S 1000,7100,4200,7100,400,*,LEFT,ALU1 ++S 1900,6100,3000,6100,400,*,LEFT,ALU1 ++S 1900,6000,3000,6000,400,*,LEFT,ALU1 ++S 600,7100,600,8100,600,*,DOWN,PDIF ++S 5300,7100,5300,8100,800,*,DOWN,PDIF ++S 3000,7100,3000,8100,600,*,DOWN,PDIF ++S 4200,7100,4200,8100,1000,*,UP,PDIF ++S 4800,6900,4800,8300,200,4,UP,PTRANS ++S 3600,6900,3600,8300,200,3,UP,PTRANS ++S 2400,6900,2400,8300,200,2,UP,PTRANS ++S 1800,7100,1800,8100,1000,*,DOWN,PDIF ++S 1200,6900,1200,8300,200,1,UP,PTRANS ++S 4800,8400,4800,8700,200,*,DOWN,POLY ++S 3600,8400,3600,8700,200,*,DOWN,POLY ++S 2400,8400,2400,8700,200,*,DOWN,POLY ++S 1200,8400,1200,8700,200,*,DOWN,POLY ++S 0,5000,6000,5000,10000,nd4_x05,LEFT,TALU8 ++S 0,2200,6000,2200,5200,*,LEFT,PWELL ++S 0,7600,6000,7600,5600,*,LEFT,NWELL ++S 0,600,6000,600,1200,vss,RIGHT,CALU1 ++S 1200,5200,1800,5200,200,*,RIGHT,POLY ++S 3900,6000,5000,6000,400,*,RIGHT,ALU1 ++S 1000,1900,2100,1900,400,*,RIGHT,ALU1 ++S 1000,2000,2100,2000,400,*,RIGHT,ALU1 ++S 1000,2000,1000,7000,400,*,DOWN,ALU1 ++S 1000,2000,1000,7000,400,z,DOWN,CALU1 ++S 2000,2000,2000,2000,400,z,LEFT,CALU1 ++S 2000,3000,3000,3000,600,*,LEFT,ALU1 ++S 2000,3000,2000,5000,400,d,DOWN,CALU1 ++S 2000,3000,2000,5100,400,*,DOWN,ALU1 ++S 3000,3000,3000,3000,400,d,LEFT,CALU1 ++S 3000,4000,3000,6000,400,c,DOWN,CALU1 ++S 3000,3900,3000,6000,400,*,DOWN,ALU1 ++S 4000,4000,5000,4000,600,*,RIGHT,ALU1 ++S 4000,1900,4000,4000,400,*,DOWN,ALU1 ++S 4000,2000,4000,4000,400,a,DOWN,CALU1 ++S 5000,4000,5000,4000,400,a,LEFT,CALU1 ++S 5200,700,5200,3100,400,*,UP,ALU1 ++S 2000,6000,2000,6000,400,c,LEFT,CALU1 ++S 4000,6000,4000,6000,400,b,LEFT,CALU1 ++S 2000,7000,2000,7000,400,z,LEFT,CALU1 ++S 3000,7000,3000,7000,400,z,LEFT,CALU1 ++S 4000,7000,4000,7000,400,z,LEFT,CALU1 ++S 1800,7000,1800,7500,400,*,DOWN,ALU1 ++S 4200,7000,4200,7500,400,*,DOWN,ALU1 ++V 2000,9300,CONT_BODY_N,* ++V 1000,9300,CONT_BODY_N,* ++V 2000,700,CONT_BODY_P,* ++V 1000,700,CONT_BODY_P,* ++V 2000,5000,CONT_POLY,* ++V 4000,6000,CONT_POLY,* ++V 5200,2000,CONT_DIF_N,* ++V 2700,6000,CONT_POLY,* ++V 3000,8000,CONT_DIF_P,* ++V 600,8000,CONT_DIF_P,* ++V 5400,8000,CONT_DIF_P,* ++V 1600,1900,CONT_DIF_N,* ++V 4600,4000,CONT_POLY,* ++V 5200,3000,CONT_DIF_N,* ++V 1800,7400,CONT_DIF_P,* ++V 4200,7400,CONT_DIF_P,* ++EOF +diff --git a/alliance/src/cells/src/msxlib/nd4_x05.vbe b/alliance/src/cells/src/msxlib/nd4_x05.vbe +new file mode 100644 +index 0000000..49ad07a +--- /dev/null ++++ b/alliance/src/cells/src/msxlib/nd4_x05.vbe +@@ -0,0 +1,44 @@ ++ENTITY nd4_x05 IS ++GENERIC ( ++ CONSTANT area : NATURAL := 6000; ++ CONSTANT cin_a : NATURAL := 4; ++ CONSTANT cin_b : NATURAL := 4; ++ CONSTANT cin_c : NATURAL := 4; ++ CONSTANT cin_d : NATURAL := 4; ++ CONSTANT rdown_a_z : NATURAL := 3830; ++ CONSTANT rdown_b_z : NATURAL := 3830; ++ CONSTANT rdown_c_z : NATURAL := 3840; ++ CONSTANT rdown_d_z : NATURAL := 3830; ++ CONSTANT rup_a_z : NATURAL := 4270; ++ CONSTANT rup_b_z : NATURAL := 4250; ++ CONSTANT rup_c_z : NATURAL := 4240; ++ CONSTANT rup_d_z : NATURAL := 4250; ++ CONSTANT tphl_a_z : NATURAL := 59; ++ CONSTANT tphl_b_z : NATURAL := 56; ++ CONSTANT tphl_c_z : NATURAL := 51; ++ CONSTANT tphl_d_z : NATURAL := 44; ++ CONSTANT tplh_d_z : NATURAL := 58; ++ CONSTANT tplh_c_z : NATURAL := 68; ++ CONSTANT tplh_b_z : NATURAL := 76; ++ CONSTANT tplh_a_z : NATURAL := 84; ++ CONSTANT transistors : NATURAL := 8 ++); ++PORT ( ++ a : in BIT; ++ b : in BIT; ++ c : in BIT; ++ d : in BIT; ++ z : out BIT; ++ vdd : in BIT; ++ vss : in BIT ++); ++END nd4_x05; ++ ++ARCHITECTURE behaviour_data_flow OF nd4_x05 IS ++ ++BEGIN ++ ASSERT ((vdd and not (vss)) = '1') ++ REPORT "power supply is missing on nd4_x05" ++ SEVERITY WARNING; ++ z <= not ((((a and b) and c) and d)) after 1000 ps; ++END; +diff --git a/alliance/src/cells/src/msxlib/nd4_x1.ap b/alliance/src/cells/src/msxlib/nd4_x1.ap +new file mode 100644 +index 0000000..43c34b5 +--- /dev/null ++++ b/alliance/src/cells/src/msxlib/nd4_x1.ap +@@ -0,0 +1,123 @@ ++V ALLIANCE : 6 ++H nd4_x1,P, 8/ 8/2014,100 ++A 0,0,6000,10000 ++R 2000,8000,ref_ref,z_80 ++R 2000,7000,ref_ref,z_70 ++R 1000,5000,ref_ref,z_50 ++R 4000,7000,ref_ref,z_70 ++R 4000,8000,ref_ref,z_80 ++R 1000,6000,ref_ref,z_60 ++R 2000,5000,ref_ref,d_50 ++R 3000,6000,ref_ref,c_60 ++R 2000,6000,ref_ref,c_60 ++R 4000,6000,ref_ref,b_60 ++R 1000,4000,ref_ref,z_40 ++R 3000,7000,ref_ref,z_70 ++R 5000,7000,ref_ref,b_70 ++R 5000,4000,ref_ref,a_40 ++R 5000,3000,ref_ref,a_30 ++R 3000,3000,ref_ref,d_30 ++R 1000,7000,ref_ref,z_70 ++R 1000,3000,ref_ref,z_30 ++R 5000,5000,ref_ref,a_50 ++R 4000,3000,ref_ref,a_30 ++R 4000,5000,ref_ref,b_50 ++R 2000,4000,ref_ref,d_40 ++R 3000,5000,ref_ref,c_50 ++R 1000,2000,ref_ref,z_20 ++R 2000,2000,ref_ref,z_20 ++R 2000,3000,ref_ref,d_30 ++R 3000,4000,ref_ref,c_40 ++R 5000,6000,ref_ref,b_60 ++S 2200,700,2200,3900,200,2d,DOWN,NTRANS ++S 3000,700,3000,3900,200,2c,DOWN,NTRANS ++S 3800,700,3800,3900,200,2b,DOWN,NTRANS ++S 4600,700,4600,3900,200,2a,DOWN,NTRANS ++S 3600,6600,3600,9300,200,1b,UP,PTRANS ++S 4800,6600,4800,9300,200,1a,UP,PTRANS ++S 0,9400,6000,9400,1200,vdd,RIGHT,CALU1 ++S 0,5000,6000,5000,10000,nd4_x1,LEFT,TALU8 ++S 0,2200,6000,2200,5200,*,LEFT,PWELL ++S 0,7600,6000,7600,5600,*,LEFT,NWELL ++S 0,600,6000,600,1200,vss,RIGHT,CALU1 ++S 4200,900,4200,3700,600,n1,UP,NDIF ++S 3400,900,3400,3700,600,n2,UP,NDIF ++S 2600,900,2600,3700,600,n3,UP,NDIF ++S 1800,900,1800,3700,400,*,UP,NDIF ++S 3800,4100,3800,5700,200,*,UP,POLY ++S 2200,3900,2200,4600,200,*,UP,POLY ++S 4200,6800,4200,9100,1000,*,UP,PDIF ++S 5300,6800,5300,9100,800,*,DOWN,PDIF ++S 3000,7900,3000,9300,400,*,UP,ALU1 ++S 5400,7900,5400,9300,400,*,UP,ALU1 ++S 600,7900,600,9300,400,*,UP,ALU1 ++S 2000,7000,2000,8000,400,z,UP,CALU1 ++S 4000,7000,4000,8000,400,z,UP,CALU1 ++S 1900,7000,1900,8100,600,*,DOWN,ALU1 ++S 4100,7000,4100,8100,600,*,DOWN,ALU1 ++S 1000,7000,4000,7000,400,*,LEFT,ALU1 ++S 1000,7100,4000,7100,400,*,LEFT,ALU1 ++S 5000,6000,5000,7000,400,b,UP,CALU1 ++S 5000,6000,5000,7100,400,*,UP,ALU1 ++S 4000,6000,5000,6000,600,*,RIGHT,ALU1 ++S 3900,3000,5000,3000,400,*,RIGHT,ALU1 ++S 5000,3000,5000,5000,400,a,DOWN,CALU1 ++S 4600,3800,4600,5200,200,*,UP,POLY ++S 5000,2900,5000,5100,400,*,DOWN,ALU1 ++S 3900,2900,5000,2900,400,*,RIGHT,ALU1 ++S 4000,5000,4000,6000,400,b,DOWN,CALU1 ++S 4000,4900,4000,6000,400,*,DOWN,ALU1 ++S 1900,6000,3000,6000,400,*,LEFT,ALU1 ++S 1900,6100,3000,6100,400,*,LEFT,ALU1 ++S 5200,900,5200,3700,800,*,UP,NDIF ++S 2200,300,2200,700,200,*,DOWN,POLY ++S 3000,300,3000,700,200,*,DOWN,POLY ++S 3800,300,3800,700,200,*,DOWN,POLY ++S 4600,300,4600,700,200,*,DOWN,POLY ++S 1000,2000,2100,2000,400,*,RIGHT,ALU1 ++S 1000,1900,2100,1900,400,*,RIGHT,ALU1 ++S 1000,2000,1000,7000,400,z,DOWN,CALU1 ++S 1000,2000,1000,7000,400,*,DOWN,ALU1 ++S 2000,2000,2000,2000,400,z,LEFT,CALU1 ++S 2000,3000,3000,3000,600,*,LEFT,ALU1 ++S 2000,3000,2000,5000,400,d,DOWN,CALU1 ++S 2000,3000,2000,5100,400,*,DOWN,ALU1 ++S 3000,3000,3000,3000,400,d,LEFT,CALU1 ++S 4000,3000,4000,3000,400,a,LEFT,CALU1 ++S 3000,4000,3000,6000,400,c,DOWN,CALU1 ++S 3000,3900,3000,6000,400,*,DOWN,ALU1 ++S 2000,6000,2000,6000,400,c,LEFT,CALU1 ++S 3000,7000,3000,7000,400,z,LEFT,CALU1 ++S 5200,700,5200,2100,400,*,UP,ALU1 ++S 1200,4700,1800,4700,200,*,RIGHT,POLY ++S 1800,5900,1800,8200,1000,*,DOWN,PDIF ++S 1200,5700,1200,8400,200,1z,UP,PTRANS ++S 2400,5700,2400,8400,200,1c,UP,PTRANS ++S 700,5900,700,8200,800,*,DOWN,PDIF ++S 3000,5900,3000,9100,600,*,DOWN,PDIF ++S 1200,8400,1200,8800,200,*,DOWN,POLY ++S 2400,8400,2400,8800,200,*,DOWN,POLY ++S 3600,9300,3600,9700,200,*,DOWN,POLY ++S 4800,9300,4800,9700,200,*,DOWN,POLY ++S 1200,4700,1200,5700,200,*,DOWN,POLY ++S 4800,5300,4800,6600,200,*,DOWN,POLY ++S 2400,5300,2800,5300,200,*,LEFT,POLY ++S 3600,6100,3600,6600,200,*,DOWN,POLY ++S 3000,3900,3000,4900,200,*,UP,POLY ++V 700,700,CONT_BODY_P,* ++V 1800,8000,CONT_DIF_P,* ++V 1800,7000,CONT_DIF_P,* ++V 4200,8000,CONT_DIF_P,* ++V 4000,6000,CONT_POLY,* ++V 5200,2000,CONT_DIF_N,* ++V 1600,2000,CONT_DIF_N,* ++V 5200,1000,CONT_DIF_N,* ++V 5400,9000,CONT_DIF_P,* ++V 3000,9000,CONT_DIF_P,* ++V 3000,8000,CONT_DIF_P,* ++V 600,8000,CONT_DIF_P,* ++V 5400,8000,CONT_DIF_P,* ++V 5000,5000,CONT_POLY,* ++V 2000,4500,CONT_POLY,* ++V 3000,5100,CONT_POLY,* ++EOF +diff --git a/alliance/src/cells/src/msxlib/nd4_x1.vbe b/alliance/src/cells/src/msxlib/nd4_x1.vbe +new file mode 100644 +index 0000000..64c5e05 +--- /dev/null ++++ b/alliance/src/cells/src/msxlib/nd4_x1.vbe +@@ -0,0 +1,44 @@ ++ENTITY nd4_x1 IS ++GENERIC ( ++ CONSTANT area : NATURAL := 6000; ++ CONSTANT cin_a : NATURAL := 7; ++ CONSTANT cin_b : NATURAL := 7; ++ CONSTANT cin_c : NATURAL := 7; ++ CONSTANT cin_d : NATURAL := 6; ++ CONSTANT rdown_a_z : NATURAL := 2040; ++ CONSTANT rdown_b_z : NATURAL := 2040; ++ CONSTANT rdown_c_z : NATURAL := 2040; ++ CONSTANT rdown_d_z : NATURAL := 2030; ++ CONSTANT rup_a_z : NATURAL := 2210; ++ CONSTANT rup_b_z : NATURAL := 2200; ++ CONSTANT rup_c_z : NATURAL := 2200; ++ CONSTANT rup_d_z : NATURAL := 2200; ++ CONSTANT tphl_a_z : NATURAL := 56; ++ CONSTANT tphl_b_z : NATURAL := 53; ++ CONSTANT tphl_c_z : NATURAL := 49; ++ CONSTANT tphl_d_z : NATURAL := 42; ++ CONSTANT tplh_d_z : NATURAL := 55; ++ CONSTANT tplh_c_z : NATURAL := 64; ++ CONSTANT tplh_b_z : NATURAL := 73; ++ CONSTANT tplh_a_z : NATURAL := 80; ++ CONSTANT transistors : NATURAL := 8 ++); ++PORT ( ++ a : in BIT; ++ b : in BIT; ++ c : in BIT; ++ d : in BIT; ++ z : out BIT; ++ vdd : in BIT; ++ vss : in BIT ++); ++END nd4_x1; ++ ++ARCHITECTURE behaviour_data_flow OF nd4_x1 IS ++ ++BEGIN ++ ASSERT ((vdd and not (vss)) = '1') ++ REPORT "power supply is missing on nd4_x1" ++ SEVERITY WARNING; ++ z <= not ((((a and b) and c) and d)) after 1000 ps; ++END; +diff --git a/alliance/src/cells/src/msxlib/nd4_x2.ap b/alliance/src/cells/src/msxlib/nd4_x2.ap +new file mode 100644 +index 0000000..e54fc17 +--- /dev/null ++++ b/alliance/src/cells/src/msxlib/nd4_x2.ap +@@ -0,0 +1,167 @@ ++V ALLIANCE : 6 ++H nd4_x2,P, 8/ 8/2014,100 ++A 0,0,9000,10000 ++R 2000,6000,ref_ref,z_60 ++R 2000,7000,ref_ref,z_70 ++R 1000,3000,ref_ref,z_30 ++R 4000,5000,ref_ref,c_50 ++R 3000,5000,ref_ref,b_50 ++R 7000,7000,ref_ref,b_70 ++R 6000,7000,ref_ref,b_70 ++R 5000,7000,ref_ref,b_70 ++R 3000,8000,ref_ref,z_80 ++R 4000,7000,ref_ref,b_70 ++R 2000,8000,ref_ref,z_80 ++R 1000,5000,ref_ref,z_50 ++R 4000,8000,ref_ref,z_80 ++R 1000,6000,ref_ref,z_60 ++R 2000,5000,ref_ref,a_50 ++R 3000,6000,ref_ref,b_60 ++R 4000,6000,ref_ref,c_60 ++R 1000,4000,ref_ref,z_40 ++R 1000,2000,ref_ref,z_20 ++R 2000,2000,ref_ref,z_20 ++R 3000,2000,ref_ref,z_20 ++R 4000,2000,ref_ref,z_20 ++R 5000,2000,ref_ref,z_20 ++R 5000,5000,ref_ref,d_50 ++R 6000,5000,ref_ref,d_50 ++R 4000,4000,ref_ref,c_40 ++R 5000,4000,ref_ref,c_40 ++R 6000,4000,ref_ref,c_40 ++R 8000,4000,ref_ref,a_40 ++R 8000,3000,ref_ref,a_30 ++R 7000,3000,ref_ref,a_30 ++R 6000,3000,ref_ref,a_30 ++R 5000,3000,ref_ref,a_30 ++R 4000,3000,ref_ref,a_30 ++R 3000,3000,ref_ref,a_30 ++R 2000,3000,ref_ref,a_30 ++R 2000,4000,ref_ref,a_40 ++R 3000,7000,ref_ref,b_70 ++R 7000,6000,ref_ref,d_60 ++R 7000,5000,ref_ref,d_50 ++R 7000,4000,ref_ref,d_50 ++S 900,6900,900,9300,400,*,DOWN,ALU1 ++S 1000,2000,1000,6000,400,z,DOWN,CALU1 ++S 1000,2000,1000,6100,400,*,DOWN,ALU1 ++S 2000,6000,2000,8000,400,z,DOWN,CALU1 ++S 2000,5900,2000,8000,600,*,UP,ALU1 ++S 1000,6000,2000,6000,600,*,RIGHT,ALU1 ++S 7800,300,7800,700,200,*,UP,POLY ++S 7000,300,7000,700,200,*,UP,POLY ++S 6200,300,6200,700,200,*,UP,POLY ++S 5400,300,5400,700,200,*,UP,POLY ++S 4200,300,4200,700,200,*,UP,POLY ++S 3400,300,3400,700,200,*,UP,POLY ++S 2600,300,2600,700,200,*,UP,POLY ++S 1800,300,1800,700,200,*,UP,POLY ++S 2000,8000,4600,8000,400,*,LEFT,ALU1 ++S 5800,5700,5800,9200,600,*,DOWN,PDIF ++S 5700,7900,5700,9300,400,*,DOWN,ALU1 ++S 5400,3000,5400,4900,200,*,DOWN,POLY ++S 3300,5700,3300,9200,1000,*,DOWN,PDIF ++S 3900,4300,3900,5500,200,*,DOWN,POLY ++S 5100,9400,5100,9700,200,*,DOWN,POLY ++S 3900,9400,3900,9700,200,*,DOWN,POLY ++S 5100,5500,5100,9400,200,04,UP,PTRANS ++S 4500,5700,4500,9200,1000,*,UP,PDIF ++S 3900,5500,3900,9400,200,03,UP,PTRANS ++S 2700,9400,2700,9700,200,*,DOWN,POLY ++S 1500,9400,1500,9700,200,*,DOWN,POLY ++S 1500,4700,1500,5500,200,*,DOWN,POLY ++S 1800,3000,1800,4900,200,*,UP,POLY ++S 2700,3900,2700,5500,200,*,UP,POLY ++S 800,5700,800,9200,600,*,DOWN,PDIF ++S 1500,5500,1500,9400,200,01,UP,PTRANS ++S 2700,5500,2700,9400,200,02,UP,PTRANS ++S 2100,5700,2100,9200,1000,*,DOWN,PDIF ++S 4000,8000,4000,8000,400,z,LEFT,CALU1 ++S 3000,8000,3000,8000,400,z,LEFT,CALU1 ++S 4000,7000,4000,7000,400,b,LEFT,CALU1 ++S 5000,7000,5000,7000,400,b,LEFT,CALU1 ++S 6000,7000,6000,7000,400,b,LEFT,CALU1 ++S 6000,5000,6000,5000,400,d,LEFT,CALU1 ++S 6000,4000,6000,4000,400,c,LEFT,CALU1 ++S 5000,4000,5000,4000,400,c,LEFT,CALU1 ++S 7000,3000,7000,3000,400,a,LEFT,CALU1 ++S 6000,3000,6000,3000,400,a,LEFT,CALU1 ++S 5000,3000,5000,3000,400,a,LEFT,CALU1 ++S 4000,3000,4000,3000,400,a,LEFT,CALU1 ++S 3000,3000,3000,3000,400,a,LEFT,CALU1 ++S 5000,2000,5000,2000,400,z,LEFT,CALU1 ++S 4000,2000,4000,2000,400,z,LEFT,CALU1 ++S 3000,2000,3000,2000,400,z,LEFT,CALU1 ++S 2000,2000,2000,2000,400,z,LEFT,CALU1 ++S 0,600,9000,600,1200,vss,RIGHT,CALU1 ++S 0,5000,9000,5000,10000,nd4_x2,LEFT,TALU8 ++S 0,2200,9000,2200,5200,*,LEFT,PWELL ++S 0,7600,9000,7600,5600,*,LEFT,NWELL ++S 0,9400,9000,9400,1200,vdd,RIGHT,CALU1 ++S 1800,700,1800,3000,200,09,DOWN,NTRANS ++S 2200,900,2200,2800,600,n3,UP,NDIF ++S 2600,700,2600,3000,200,10,DOWN,NTRANS ++S 3000,900,3000,2800,600,n2,UP,NDIF ++S 3400,700,3400,3000,200,11,DOWN,NTRANS ++S 3800,900,3800,2800,600,n1,UP,NDIF ++S 4200,700,4200,3000,200,12,DOWN,NTRANS ++S 4700,900,4700,2800,800,*,UP,NDIF ++S 5400,700,5400,3000,200,13,DOWN,NTRANS ++S 6600,900,6600,2800,600,n5,UP,NDIF ++S 7000,700,7000,3000,200,15,DOWN,NTRANS ++S 6200,700,6200,3000,200,14,DOWN,NTRANS ++S 5800,900,5800,2800,600,n4,UP,NDIF ++S 7400,900,7400,2800,600,n6,UP,NDIF ++S 7800,700,7800,3000,200,16,DOWN,NTRANS ++S 8400,900,8400,2800,600,*,UP,NDIF ++S 4200,3400,5400,3400,200,*,RIGHT,POLY ++S 3400,3000,3400,4000,200,*,UP,POLY ++S 3400,4000,3800,4000,200,*,RIGHT,POLY ++S 6200,3000,6200,3900,200,*,UP,POLY ++S 4000,4000,4000,6000,400,c,UP,CALU1 ++S 4000,4000,4000,6000,600,*,DOWN,ALU1 ++S 3900,4000,6200,4000,600,*,RIGHT,ALU1 ++S 7800,3000,7800,4200,200,*,UP,POLY ++S 2000,3000,8000,3000,400,*,RIGHT,ALU1 ++S 8000,3000,8000,4000,400,a,DOWN,CALU1 ++S 8000,3000,8000,4000,600,*,DOWN,ALU1 ++S 2600,3000,2600,4000,200,*,UP,POLY ++S 3000,5000,3000,7000,400,b,DOWN,CALU1 ++S 3000,4900,3000,7000,600,*,UP,ALU1 ++S 1000,2000,5100,2000,400,*,RIGHT,ALU1 ++S 1000,1900,5100,1900,400,*,RIGHT,ALU1 ++S 1200,900,1200,2800,800,*,UP,NDIF ++S 2000,3000,2000,5000,400,a,DOWN,CALU1 ++S 2000,3000,2000,5100,400,*,DOWN,ALU1 ++S 1900,3000,1900,5100,400,*,DOWN,ALU1 ++S 7000,3000,7000,6800,200,*,UP,POLY ++S 3000,7000,7100,7000,400,*,RIGHT,ALU1 ++S 7000,4000,7000,6000,400,d,UP,CALU1 ++S 7000,3900,7000,6100,400,*,UP,ALU1 ++S 5000,5000,7000,5000,600,*,RIGHT,ALU1 ++S 7000,7000,7000,7000,400,b,LEFT,CALU1 ++S 5000,5000,5000,5000,400,d,LEFT,CALU1 ++S 8400,700,8400,2100,400,*,DOWN,ALU1 ++V 7900,9300,CONT_BODY_N,* ++V 900,7000,CONT_DIF_P,* ++V 2100,6000,CONT_DIF_P,* ++V 6800,7000,CONT_POLY,* ++V 900,8000,CONT_DIF_P,* ++V 2100,7000,CONT_DIF_P,* ++V 5700,9000,CONT_DIF_P,* ++V 5700,8000,CONT_DIF_P,* ++V 5200,4900,CONT_POLY,* ++V 3300,9000,CONT_DIF_P,* ++V 4100,4200,CONT_POLY,* ++V 4500,8000,CONT_DIF_P,* ++V 2100,8000,CONT_DIF_P,* ++V 900,9000,CONT_DIF_P,* ++V 1900,4900,CONT_POLY,* ++V 1200,1000,CONT_DIF_N,* ++V 4800,2000,CONT_DIF_N,* ++V 8400,2000,CONT_DIF_N,* ++V 8400,1000,CONT_DIF_N,* ++V 3000,4900,CONT_POLY,* ++V 6200,4000,CONT_POLY,* ++V 8000,4000,CONT_POLY,* ++EOF +diff --git a/alliance/src/cells/src/msxlib/nd4_x2.vbe b/alliance/src/cells/src/msxlib/nd4_x2.vbe +new file mode 100644 +index 0000000..0a511a2 +--- /dev/null ++++ b/alliance/src/cells/src/msxlib/nd4_x2.vbe +@@ -0,0 +1,44 @@ ++ENTITY nd4_x2 IS ++GENERIC ( ++ CONSTANT area : NATURAL := 9000; ++ CONSTANT cin_a : NATURAL := 10; ++ CONSTANT cin_b : NATURAL := 10; ++ CONSTANT cin_c : NATURAL := 10; ++ CONSTANT cin_d : NATURAL := 9; ++ CONSTANT rdown_a_z : NATURAL := 1420; ++ CONSTANT rdown_b_z : NATURAL := 1420; ++ CONSTANT rdown_c_z : NATURAL := 1420; ++ CONSTANT rdown_d_z : NATURAL := 1410; ++ CONSTANT rup_a_z : NATURAL := 1530; ++ CONSTANT rup_b_z : NATURAL := 1520; ++ CONSTANT rup_c_z : NATURAL := 1520; ++ CONSTANT rup_d_z : NATURAL := 1520; ++ CONSTANT tphl_a_z : NATURAL := 56; ++ CONSTANT tphl_b_z : NATURAL := 53; ++ CONSTANT tphl_c_z : NATURAL := 48; ++ CONSTANT tphl_d_z : NATURAL := 40; ++ CONSTANT tplh_d_z : NATURAL := 53; ++ CONSTANT tplh_c_z : NATURAL := 63; ++ CONSTANT tplh_b_z : NATURAL := 72; ++ CONSTANT tplh_a_z : NATURAL := 79; ++ CONSTANT transistors : NATURAL := 12 ++); ++PORT ( ++ a : in BIT; ++ b : in BIT; ++ c : in BIT; ++ d : in BIT; ++ z : out BIT; ++ vdd : in BIT; ++ vss : in BIT ++); ++END nd4_x2; ++ ++ARCHITECTURE behaviour_data_flow OF nd4_x2 IS ++ ++BEGIN ++ ASSERT ((vdd and not (vss)) = '1') ++ REPORT "power supply is missing on nd4_x2" ++ SEVERITY WARNING; ++ z <= not ((((a and b) and c) and d)) after 1000 ps; ++END; +diff --git a/alliance/src/cells/src/msxlib/nd4_x3.ap b/alliance/src/cells/src/msxlib/nd4_x3.ap +new file mode 100644 +index 0000000..6dda1c9 +--- /dev/null ++++ b/alliance/src/cells/src/msxlib/nd4_x3.ap +@@ -0,0 +1,215 @@ ++V ALLIANCE : 6 ++H nd4_x3,P, 8/ 8/2014,100 ++A 0,0,11000,10000 ++R 1000,3000,ref_ref,z_30 ++R 9000,4000,ref_ref,a_40 ++R 4000,5000,ref_ref,c_50 ++R 3000,5000,ref_ref,b_50 ++R 2000,7000,ref_ref,a_70 ++R 2000,6000,ref_ref,a_60 ++R 1000,7000,ref_ref,z_70 ++R 8000,4000,ref_ref,a_40 ++R 7000,4000,ref_ref,a_40 ++R 6000,4000,ref_ref,a_40 ++R 5000,4000,ref_ref,a_40 ++R 4000,4000,ref_ref,a_40 ++R 3000,4000,ref_ref,a_40 ++R 7000,7000,ref_ref,b_70 ++R 6000,7000,ref_ref,b_70 ++R 5000,7000,ref_ref,b_70 ++R 5000,3000,ref_ref,z_30 ++R 4000,3000,ref_ref,z_30 ++R 3000,3000,ref_ref,z_30 ++R 8000,8000,ref_ref,z_80 ++R 7000,8000,ref_ref,z_80 ++R 6000,8000,ref_ref,z_80 ++R 5000,8000,ref_ref,z_80 ++R 3000,8000,ref_ref,z_80 ++R 4000,7000,ref_ref,b_70 ++R 7000,6000,ref_ref,c_60 ++R 6000,6000,ref_ref,c_60 ++R 6000,5000,ref_ref,d_50 ++R 2000,8000,ref_ref,z_80 ++R 1000,5000,ref_ref,z_50 ++R 4000,8000,ref_ref,z_80 ++R 1000,6000,ref_ref,z_60 ++R 2000,5000,ref_ref,a_50 ++R 3000,6000,ref_ref,b_60 ++R 5000,5000,ref_ref,d_50 ++R 4000,6000,ref_ref,c_60 ++R 5000,6000,ref_ref,c_60 ++R 1000,4000,ref_ref,z_40 ++R 2000,3000,ref_ref,z_30 ++R 8000,7000,ref_ref,b_70 ++R 3000,7000,ref_ref,b_70 ++R 10000,4000,ref_ref,a_40 ++R 5000,2000,ref_ref,z_20 ++R 1000,8000,ref_ref,z_80 ++R 2000,4000,ref_ref,a_40 ++R 9000,8000,ref_ref,z_80 ++R 10000,5000,ref_ref,a_50 ++R 9000,5000,ref_ref,b_50 ++R 7000,5000,ref_ref,d_50 ++R 9000,6000,ref_ref,b_60 ++R 8000,6000,ref_ref,d_60 ++S 9100,9300,10300,9300,600,*,RIGHT,NTIE ++S 900,2900,900,8000,400,*,DOWN,ALU1 ++S 1000,2900,1000,8000,400,*,DOWN,ALU1 ++S 8000,8000,8000,8000,400,z,LEFT,CALU1 ++S 7000,8000,7000,8000,400,z,LEFT,CALU1 ++S 6000,8000,6000,8000,400,z,LEFT,CALU1 ++S 5000,8000,5000,8000,400,z,LEFT,CALU1 ++S 4000,8000,4000,8000,400,z,LEFT,CALU1 ++S 3000,8000,3000,8000,400,z,LEFT,CALU1 ++S 2000,8000,2000,8000,400,z,LEFT,CALU1 ++S 7000,7000,7000,7000,400,b,LEFT,CALU1 ++S 6000,7000,6000,7000,400,b,LEFT,CALU1 ++S 5000,7000,5000,7000,400,b,LEFT,CALU1 ++S 4000,7000,4000,7000,400,b,LEFT,CALU1 ++S 5000,6000,5000,6000,400,c,LEFT,CALU1 ++S 7000,6000,7000,6000,400,c,LEFT,CALU1 ++S 6000,6000,6000,6000,400,c,LEFT,CALU1 ++S 6000,5000,6000,5000,400,d,LEFT,CALU1 ++S 5000,5000,5000,5000,400,d,LEFT,CALU1 ++S 7200,5800,7200,6700,200,*,DOWN,POLY ++S 6000,4800,6000,6700,200,*,DOWN,POLY ++S 9000,4000,9000,4000,400,a,LEFT,CALU1 ++S 8000,4000,8000,4000,400,a,LEFT,CALU1 ++S 7000,4000,7000,4000,400,a,LEFT,CALU1 ++S 6000,4000,6000,4000,400,a,LEFT,CALU1 ++S 5000,4000,5000,4000,400,a,LEFT,CALU1 ++S 4000,4000,4000,4000,400,a,LEFT,CALU1 ++S 3000,4000,3000,4000,400,a,LEFT,CALU1 ++S 2000,3000,2000,3000,400,z,LEFT,CALU1 ++S 3000,3000,3000,3000,400,z,LEFT,CALU1 ++S 4000,3000,4000,3000,400,z,LEFT,CALU1 ++S 5000,2000,5000,3000,400,z,DOWN,CALU1 ++S 0,600,11000,600,1200,vss,RIGHT,CALU1 ++S 0,5000,11000,5000,10000,nd4_x3,LEFT,TALU8 ++S 0,2200,11000,2200,5200,*,LEFT,PWELL ++S 0,7600,11000,7600,5600,*,LEFT,NWELL ++S 4800,5000,6000,5000,600,*,RIGHT,POLY ++S 1200,4600,1800,4600,200,*,RIGHT,POLY ++S 4000,6000,7100,6000,400,*,RIGHT,ALU1 ++S 4000,5000,4000,6000,400,c,DOWN,CALU1 ++S 4000,5000,4000,6000,600,*,DOWN,ALU1 ++S 3000,5000,3000,7000,400,b,DOWN,CALU1 ++S 3000,5000,3000,7000,600,*,UP,ALU1 ++S 2400,5200,2700,5200,200,*,RIGHT,POLY ++S 0,9400,11000,9400,1200,vdd,RIGHT,CALU1 ++S 600,6900,600,9100,600,*,DOWN,PDIF ++S 1200,6700,1200,9300,200,01,UP,PTRANS ++S 2400,6700,2400,9300,200,02,UP,PTRANS ++S 1800,6900,1800,9100,1000,*,DOWN,PDIF ++S 3000,6900,3000,9100,1000,*,DOWN,PDIF ++S 3600,6700,3600,9300,200,03,UP,PTRANS ++S 4200,6900,4200,9100,1000,*,UP,PDIF ++S 4800,6700,4800,9300,200,04,UP,PTRANS ++S 5400,6900,5400,9100,600,*,DOWN,PDIF ++S 6000,6700,6000,9300,200,05,UP,PTRANS ++S 6600,6900,6600,9100,1000,*,DOWN,PDIF ++S 7200,6700,7200,9300,200,06,UP,PTRANS ++S 9000,6000,9000,8200,1000,*,DOWN,PDIF ++S 8400,5800,8400,8400,200,07,UP,PTRANS ++S 9600,5800,9600,8400,200,08,UP,PTRANS ++S 10200,6000,10200,8200,600,*,DOWN,PDIF ++S 7800,6000,7800,9100,600,*,DOWN,PDIF ++S 9600,8400,9600,8800,200,*,DOWN,POLY ++S 8400,8400,8400,8800,200,*,DOWN,POLY ++S 7200,9300,7200,9700,200,*,DOWN,POLY ++S 9600,4200,9600,5800,200,*,DOWN,POLY ++S 2000,4000,10100,4000,400,*,RIGHT,ALU1 ++S 6000,9300,6000,9700,200,*,DOWN,POLY ++S 2200,700,2200,3800,200,09,DOWN,NTRANS ++S 1600,700,1600,2100,400,*,DOWN,ALU1 ++S 2200,300,2200,700,200,*,UP,POLY ++S 3000,300,3000,700,200,*,UP,POLY ++S 3800,300,3800,700,200,*,UP,POLY ++S 4600,300,4600,700,200,*,UP,POLY ++S 5800,300,5800,700,200,*,UP,POLY ++S 6600,300,6600,700,200,*,UP,POLY ++S 7400,300,7400,700,200,*,UP,POLY ++S 8200,300,8200,700,200,*,UP,POLY ++S 2600,900,2600,3600,600,n3,UP,NDIF ++S 3000,700,3000,3800,200,10,DOWN,NTRANS ++S 3400,900,3400,3600,600,n2,UP,NDIF ++S 3800,700,3800,3800,200,11,DOWN,NTRANS ++S 4200,900,4200,3600,600,n1,UP,NDIF ++S 4600,700,4600,3800,200,12,DOWN,NTRANS ++S 5100,900,5100,3600,800,*,UP,NDIF ++S 5800,700,5800,3800,200,13,DOWN,NTRANS ++S 6200,900,6200,3600,600,n4,UP,NDIF ++S 6600,700,6600,3800,200,14,DOWN,NTRANS ++S 7000,900,7000,3600,600,n5,UP,NDIF ++S 7400,700,7400,3800,200,15,DOWN,NTRANS ++S 7800,900,7800,3600,600,n6,UP,NDIF ++S 8200,700,8200,3800,200,16,DOWN,NTRANS ++S 3000,3800,3000,5000,200,*,UP,POLY ++S 1200,4600,1200,6700,200,*,DOWN,POLY ++S 2400,5200,2400,6700,200,*,DOWN,POLY ++S 3600,5800,3600,6700,200,*,DOWN,POLY ++S 3800,3800,3800,5700,200,*,UP,POLY ++S 4800,4800,4800,6700,200,*,DOWN,POLY ++S 4600,3800,4600,5200,200,*,UP,POLY ++S 5800,3800,5800,4800,200,*,UP,POLY ++S 6600,4100,6600,5700,200,*,UP,POLY ++S 8200,4200,9700,4200,200,*,RIGHT,POLY ++S 5100,1900,5100,3000,600,*,DOWN,ALU1 ++S 1600,900,1600,3600,800,*,UP,NDIF ++S 1000,3000,5000,3000,400,*,RIGHT,ALU1 ++S 1000,2900,5000,2900,400,*,RIGHT,ALU1 ++S 8800,700,8800,2100,400,*,DOWN,ALU1 ++S 8800,900,8800,3600,600,*,UP,NDIF ++S 1000,3000,1000,8000,400,z,DOWN,CALU1 ++S 2000,4000,2000,7100,400,*,DOWN,ALU1 ++S 2000,4000,2000,7000,400,a,DOWN,CALU1 ++S 1900,4000,1900,7100,400,*,DOWN,ALU1 ++S 1200,9300,1200,9700,200,*,DOWN,POLY ++S 2400,9300,2400,9700,200,*,DOWN,POLY ++S 3600,9300,3600,9700,200,*,DOWN,POLY ++S 4800,9300,4800,9700,200,*,DOWN,POLY ++S 10200,6900,10200,9300,400,*,UP,ALU1 ++S 10000,4000,10000,5000,600,*,UP,ALU1 ++S 10000,4000,10000,5000,400,a,DOWN,CALU1 ++S 10000,600,10000,3400,600,*,UP,PTIE ++S 1000,8000,9100,8000,400,*,LEFT,ALU1 ++S 7000,5000,7000,5000,400,d,LEFT,CALU1 ++S 3000,7000,9000,7000,400,*,RIGHT,ALU1 ++S 8000,7000,8000,7000,400,b,LEFT,CALU1 ++S 8900,4900,8900,7000,600,*,DOWN,ALU1 ++S 8400,4900,8400,5800,200,*,DOWN,POLY ++S 8400,5100,8800,5100,600,*,LEFT,POLY ++S 7400,4900,8400,4900,200,*,RIGHT,POLY ++S 7400,3800,7400,4900,200,*,DOWN,POLY ++S 9000,5000,9000,6000,400,b,DOWN,CALU1 ++S 4900,5000,8000,5000,400,*,RIGHT,ALU1 ++S 8000,6000,8000,6000,400,d,LEFT,CALU1 ++S 8000,5000,8000,6100,400,*,UP,ALU1 ++S 9000,8000,9000,8000,400,z,LEFT,CALU1 ++V 10300,9300,CONT_BODY_N,* ++V 9000,9300,CONT_BODY_N,* ++V 7800,9000,CONT_DIF_P,* ++V 6600,8000,CONT_DIF_P,* ++V 6800,6000,CONT_POLY,* ++V 5400,5000,CONT_POLY,* ++V 1800,8000,CONT_DIF_P,* ++V 4200,8000,CONT_DIF_P,* ++V 4000,6000,CONT_POLY,* ++V 10200,8000,CONT_DIF_P,* ++V 2000,4400,CONT_POLY,* ++V 3000,5000,CONT_POLY,* ++V 600,9000,CONT_DIF_P,* ++V 3000,9000,CONT_DIF_P,* ++V 5400,9000,CONT_DIF_P,* ++V 1600,2000,CONT_DIF_N,* ++V 1600,1000,CONT_DIF_N,* ++V 5200,2000,CONT_DIF_N,* ++V 5200,3000,CONT_DIF_N,* ++V 8800,2000,CONT_DIF_N,* ++V 8800,1000,CONT_DIF_N,* ++V 10000,600,CONT_BODY_P,* ++V 9000,8000,CONT_DIF_P,* ++V 10200,7000,CONT_DIF_P,* ++V 9900,4400,CONT_POLY,* ++V 8800,5100,CONT_POLY,* ++EOF +diff --git a/alliance/src/cells/src/msxlib/nd4_x3.vbe b/alliance/src/cells/src/msxlib/nd4_x3.vbe +new file mode 100644 +index 0000000..97aaf28 +--- /dev/null ++++ b/alliance/src/cells/src/msxlib/nd4_x3.vbe +@@ -0,0 +1,44 @@ ++ENTITY nd4_x3 IS ++GENERIC ( ++ CONSTANT area : NATURAL := 11000; ++ CONSTANT cin_a : NATURAL := 14; ++ CONSTANT cin_b : NATURAL := 14; ++ CONSTANT cin_c : NATURAL := 13; ++ CONSTANT cin_d : NATURAL := 12; ++ CONSTANT rdown_a_z : NATURAL := 1050; ++ CONSTANT rdown_b_z : NATURAL := 1050; ++ CONSTANT rdown_c_z : NATURAL := 1050; ++ CONSTANT rdown_d_z : NATURAL := 1050; ++ CONSTANT rup_a_z : NATURAL := 1150; ++ CONSTANT rup_b_z : NATURAL := 1140; ++ CONSTANT rup_c_z : NATURAL := 1140; ++ CONSTANT rup_d_z : NATURAL := 1140; ++ CONSTANT tphl_a_z : NATURAL := 56; ++ CONSTANT tphl_b_z : NATURAL := 53; ++ CONSTANT tphl_c_z : NATURAL := 48; ++ CONSTANT tphl_d_z : NATURAL := 41; ++ CONSTANT tplh_d_z : NATURAL := 54; ++ CONSTANT tplh_c_z : NATURAL := 63; ++ CONSTANT tplh_b_z : NATURAL := 73; ++ CONSTANT tplh_a_z : NATURAL := 80; ++ CONSTANT transistors : NATURAL := 16 ++); ++PORT ( ++ a : in BIT; ++ b : in BIT; ++ c : in BIT; ++ d : in BIT; ++ z : out BIT; ++ vdd : in BIT; ++ vss : in BIT ++); ++END nd4_x3; ++ ++ARCHITECTURE behaviour_data_flow OF nd4_x3 IS ++ ++BEGIN ++ ASSERT ((vdd and not (vss)) = '1') ++ REPORT "power supply is missing on nd4_x3" ++ SEVERITY WARNING; ++ z <= not ((((a and b) and c) and d)) after 1000 ps; ++END; +diff --git a/alliance/src/cells/src/msxlib/nr2_x05.ap b/alliance/src/cells/src/msxlib/nr2_x05.ap +new file mode 100644 +index 0000000..2ba4146 +--- /dev/null ++++ b/alliance/src/cells/src/msxlib/nr2_x05.ap +@@ -0,0 +1,70 @@ ++V ALLIANCE : 6 ++H nr2_x05,P, 8/ 8/2014,100 ++A 0,0,4000,10000 ++R 2000,4000,ref_ref,b_40 ++R 1000,3000,ref_ref,z_30 ++R 3000,5000,ref_ref,a_50 ++R 1000,6000,ref_ref,z_60 ++R 1000,5000,ref_ref,z_50 ++R 1000,4000,ref_ref,z_40 ++R 3000,4000,ref_ref,b_40 ++R 2000,3000,ref_ref,z_30 ++R 3000,3000,ref_ref,b_30 ++R 2000,2000,ref_ref,z_20 ++R 2000,5000,ref_ref,a_60 ++R 2000,6000,ref_ref,a_60 ++S 1100,700,1900,700,600,*,LEFT,PTIE ++S 1100,9300,1900,9300,600,*,RIGHT,NTIE ++S 0,600,4000,600,1200,vss,RIGHT,CALU1 ++S 0,9400,4000,9400,1200,vdd,RIGHT,CALU1 ++S 0,5000,4000,5000,10000,nr2_x05,LEFT,TALU8 ++S 0,2200,4000,2200,5200,*,LEFT,PWELL ++S 0,7600,4000,7600,5600,*,LEFT,NWELL ++S 1600,5600,1600,7800,200,1,UP,PTRANS ++S 2400,5600,2400,7800,200,2,UP,PTRANS ++S 2000,5800,2000,7600,600,n1,UP,PDIF ++S 1200,5800,1200,7600,400,*,UP,PDIF ++S 1400,1700,1400,2300,200,3,DOWN,NTRANS ++S 1400,1300,1400,1700,200,*,UP,POLY ++S 800,700,800,2100,400,*,DOWN,ALU1 ++S 2000,1900,2000,2100,1000,*,UP,NDIF ++S 2600,1300,2600,1700,200,*,UP,POLY ++S 2600,1700,2600,2300,200,4,DOWN,NTRANS ++S 2000,2000,2000,3000,400,z,DOWN,CALU1 ++S 1000,3000,2000,3000,600,*,RIGHT,ALU1 ++S 1800,4000,3000,4000,600,*,LEFT,ALU1 ++S 2600,2300,2600,5200,200,*,UP,POLY ++S 1600,3800,1600,5600,200,*,DOWN,POLY ++S 1400,2300,1400,4200,200,*,UP,POLY ++S 2000,5000,3000,5000,600,*,LEFT,ALU1 ++S 2000,4000,2000,4000,400,b,LEFT,CALU1 ++S 1000,3000,1000,6000,400,z,DOWN,CALU1 ++S 3000,5000,3000,5000,400,a,LEFT,CALU1 ++S 3000,5900,3000,9300,400,*,UP,ALU1 ++S 3100,5800,3100,7600,600,*,DOWN,PDIF ++S 2400,7800,2400,8200,200,*,DOWN,POLY ++S 1600,7800,1600,8200,200,*,DOWN,POLY ++S 2000,4900,2000,6100,400,*,UP,ALU1 ++S 2000,5000,2000,6000,400,a,UP,CALU1 ++S 1000,6000,1000,6600,600,*,DOWN,PDIF ++S 3000,3000,3000,4000,400,b,DOWN,CALU1 ++S 3000,2900,3000,4000,400,*,DOWN,ALU1 ++S 3200,1900,3200,2100,600,*,UP,NDIF ++S 3200,700,3200,2100,400,*,DOWN,ALU1 ++S 2000,1900,2000,3100,400,*,DOWN,ALU1 ++S 1000,2900,1000,6800,400,*,DOWN,ALU1 ++S 1400,4000,2000,4000,600,*,LEFT,POLY ++V 2000,700,CONT_BODY_P,* ++V 1000,700,CONT_BODY_P,* ++V 2000,9300,CONT_BODY_N,* ++V 1000,9300,CONT_BODY_N,* ++V 1000,5900,CONT_DIF_P,* ++V 2000,2000,CONT_DIF_N,* ++V 800,2000,CONT_DIF_N,* ++V 1800,4000,CONT_POLY,* ++V 2600,5000,CONT_POLY,* ++V 3000,7000,CONT_DIF_P,* ++V 3000,6000,CONT_DIF_P,* ++V 1000,6700,CONT_DIF_P,* ++V 3200,2000,CONT_DIF_N,* ++EOF +diff --git a/alliance/src/cells/src/msxlib/nr2_x05.vbe b/alliance/src/cells/src/msxlib/nr2_x05.vbe +new file mode 100644 +index 0000000..41e5133 +--- /dev/null ++++ b/alliance/src/cells/src/msxlib/nr2_x05.vbe +@@ -0,0 +1,32 @@ ++ENTITY nr2_x05 IS ++GENERIC ( ++ CONSTANT area : NATURAL := 4000; ++ CONSTANT cin_a : NATURAL := 3; ++ CONSTANT cin_b : NATURAL := 3; ++ CONSTANT rdown_a_z : NATURAL := 3820; ++ CONSTANT rdown_b_z : NATURAL := 3810; ++ CONSTANT rup_a_z : NATURAL := 5280; ++ CONSTANT rup_b_z : NATURAL := 5280; ++ CONSTANT tplh_a_z : NATURAL := 55; ++ CONSTANT tplh_b_z : NATURAL := 45; ++ CONSTANT tphl_b_z : NATURAL := 44; ++ CONSTANT tphl_a_z : NATURAL := 53; ++ CONSTANT transistors : NATURAL := 4 ++); ++PORT ( ++ a : in BIT; ++ b : in BIT; ++ z : out BIT; ++ vdd : in BIT; ++ vss : in BIT ++); ++END nr2_x05; ++ ++ARCHITECTURE behaviour_data_flow OF nr2_x05 IS ++ ++BEGIN ++ ASSERT ((vdd and not (vss)) = '1') ++ REPORT "power supply is missing on nr2_x05" ++ SEVERITY WARNING; ++ z <= not ((a or b)) after 900 ps; ++END; +diff --git a/alliance/src/cells/src/msxlib/nr2_x1.ap b/alliance/src/cells/src/msxlib/nr2_x1.ap +new file mode 100644 +index 0000000..edd6c77 +--- /dev/null ++++ b/alliance/src/cells/src/msxlib/nr2_x1.ap +@@ -0,0 +1,73 @@ ++V ALLIANCE : 6 ++H nr2_x1,P, 8/ 8/2014,100 ++A 0,0,4000,10000 ++R 2000,6000,ref_ref,a_60 ++R 1000,3000,ref_ref,z_30 ++R 2000,4000,ref_ref,b_40 ++R 1000,7000,ref_ref,z_70 ++R 3000,6000,ref_ref,a_60 ++R 2000,3000,ref_ref,z_30 ++R 3000,4000,ref_ref,b_40 ++R 1000,4000,ref_ref,z_40 ++R 1000,5000,ref_ref,z_50 ++R 1000,6000,ref_ref,z_60 ++R 2000,5000,ref_ref,b_50 ++R 3000,5000,ref_ref,a_50 ++R 2000,2000,ref_ref,z_20 ++R 3000,7000,ref_ref,a_70 ++S 1100,700,1900,700,600,*,LEFT,PTIE ++S 2000,3900,2000,5100,400,*,UP,ALU1 ++S 1000,2900,1000,7000,400,*,DOWN,ALU1 ++S 1400,4000,2000,4000,600,*,LEFT,POLY ++S 3000,4000,3000,4000,400,b,LEFT,CALU1 ++S 2000,6000,2000,6000,400,a,LEFT,CALU1 ++S 2400,5100,2600,5100,200,*,RIGHT,POLY ++S 2000,4000,2000,5000,400,b,DOWN,CALU1 ++S 1200,5700,1200,9200,400,*,UP,PDIF ++S 3100,5700,3100,9200,600,*,DOWN,PDIF ++S 3000,7900,3000,9300,400,*,UP,ALU1 ++S 2400,9400,2400,9700,200,*,DOWN,POLY ++S 2000,5700,2000,9200,600,n1,UP,PDIF ++S 2400,5500,2400,9400,200,2,UP,PTRANS ++S 1600,9400,1600,9700,200,*,DOWN,POLY ++S 1600,5500,1600,9400,200,1,UP,PTRANS ++S 0,5000,4000,5000,10000,nr2_x1,LEFT,TALU8 ++S 0,2200,4000,2200,5200,*,LEFT,PWELL ++S 0,7600,4000,7600,5600,*,LEFT,NWELL ++S 0,9400,4000,9400,1200,vdd,RIGHT,CALU1 ++S 0,600,4000,600,1200,vss,RIGHT,CALU1 ++S 1400,1300,1400,1700,200,*,UP,POLY ++S 1400,1700,1400,2800,200,3,DOWN,NTRANS ++S 2600,1300,2600,1700,200,*,UP,POLY ++S 2600,1700,2600,2800,200,4,DOWN,NTRANS ++S 2000,1900,2000,2600,1000,*,UP,NDIF ++S 3200,700,3200,2100,400,*,DOWN,ALU1 ++S 3300,1900,3300,2600,600,*,UP,NDIF ++S 1600,3800,1600,5500,200,*,DOWN,POLY ++S 1800,4000,3000,4000,600,*,RIGHT,ALU1 ++S 1000,3000,2000,3000,600,*,RIGHT,ALU1 ++S 2000,2000,2000,3000,400,z,DOWN,CALU1 ++S 2000,1900,2000,3000,400,*,UP,ALU1 ++S 1000,5900,1000,6500,600,*,DOWN,PDIF ++S 1000,3000,1000,7000,400,z,DOWN,CALU1 ++S 1000,7000,1000,7100,400,*,UP,ALU1 ++S 2600,2800,2600,5100,200,*,UP,POLY ++S 2400,5000,2400,5500,200,*,DOWN,POLY ++S 1400,2800,1400,4200,200,*,UP,POLY ++S 800,700,800,2100,400,*,DOWN,ALU1 ++S 700,1900,700,2600,600,*,UP,NDIF ++S 3000,4900,3000,7000,600,*,UP,ALU1 ++S 3000,5000,3000,7000,400,a,UP,CALU1 ++S 1900,6000,3100,6000,400,*,LEFT,ALU1 ++V 2000,700,CONT_BODY_P,* ++V 1000,700,CONT_BODY_P,* ++V 2000,2500,CONT_DIF_N,* ++V 3000,9000,CONT_DIF_P,* ++V 3000,8000,CONT_DIF_P,* ++V 3000,4900,CONT_POLY,* ++V 3200,2000,CONT_DIF_N,* ++V 1800,4000,CONT_POLY,* ++V 1000,5800,CONT_DIF_P,* ++V 1000,6600,CONT_DIF_P,* ++V 800,2000,CONT_DIF_N,* ++EOF +diff --git a/alliance/src/cells/src/msxlib/nr2_x1.vbe b/alliance/src/cells/src/msxlib/nr2_x1.vbe +new file mode 100644 +index 0000000..dd781df +--- /dev/null ++++ b/alliance/src/cells/src/msxlib/nr2_x1.vbe +@@ -0,0 +1,32 @@ ++ENTITY nr2_x1 IS ++GENERIC ( ++ CONSTANT area : NATURAL := 4000; ++ CONSTANT cin_a : NATURAL := 6; ++ CONSTANT cin_b : NATURAL := 5; ++ CONSTANT rdown_a_z : NATURAL := 2080; ++ CONSTANT rdown_b_z : NATURAL := 2080; ++ CONSTANT rup_a_z : NATURAL := 2980; ++ CONSTANT rup_b_z : NATURAL := 2980; ++ CONSTANT tplh_a_z : NATURAL := 53; ++ CONSTANT tplh_b_z : NATURAL := 44; ++ CONSTANT tphl_b_z : NATURAL := 42; ++ CONSTANT tphl_a_z : NATURAL := 50; ++ CONSTANT transistors : NATURAL := 4 ++); ++PORT ( ++ a : in BIT; ++ b : in BIT; ++ z : out BIT; ++ vdd : in BIT; ++ vss : in BIT ++); ++END nr2_x1; ++ ++ARCHITECTURE behaviour_data_flow OF nr2_x1 IS ++ ++BEGIN ++ ASSERT ((vdd and not (vss)) = '1') ++ REPORT "power supply is missing on nr2_x1" ++ SEVERITY WARNING; ++ z <= not ((a or b)) after 900 ps; ++END; +diff --git a/alliance/src/cells/src/msxlib/nr2_x2.ap b/alliance/src/cells/src/msxlib/nr2_x2.ap +new file mode 100644 +index 0000000..9563816 +--- /dev/null ++++ b/alliance/src/cells/src/msxlib/nr2_x2.ap +@@ -0,0 +1,92 @@ ++V ALLIANCE : 6 ++H nr2_x2,P, 8/ 8/2014,100 ++A 0,0,6000,10000 ++R 4000,4000,ref_ref,a_40 ++R 3000,4000,ref_ref,a_40 ++R 2000,4000,ref_ref,a_40 ++R 2000,5000,ref_ref,a_50 ++R 3000,5000,ref_ref,b_50 ++R 4000,5000,ref_ref,b_50 ++R 4000,6000,ref_ref,b_60 ++R 1000,6000,ref_ref,z_60 ++R 2000,2000,ref_ref,z_20 ++R 2000,3000,ref_ref,z_30 ++R 1000,4000,ref_ref,z_40 ++R 1000,5000,ref_ref,z_50 ++R 1000,3000,ref_ref,z_30 ++R 3000,7000,ref_ref,z_70 ++R 2000,6000,ref_ref,z_60 ++R 3000,6000,ref_ref,z_60 ++S 2000,4000,2000,5000,400,a,DOWN,CALU1 ++S 3000,4000,3000,4000,400,a,LEFT,CALU1 ++S 3000,5000,3000,5000,400,b,LEFT,CALU1 ++S 4400,3800,4400,5500,200,*,DOWN,POLY ++S 2800,3400,2800,4700,200,*,UP,POLY ++S 1600,3400,1600,5500,200,*,DOWN,POLY ++S 1600,900,1600,1300,200,*,UP,POLY ++S 2800,900,2800,1300,200,*,UP,POLY ++S 1000,1500,1000,3200,800,*,UP,NDIF ++S 3500,1500,3500,3200,600,*,DOWN,NDIF ++S 2800,1300,2800,3400,200,6,DOWN,NTRANS ++S 1600,1300,1600,3400,200,5,DOWN,NTRANS ++S 2200,1500,2200,3200,1000,*,UP,NDIF ++S 5000,5700,5000,9200,800,*,DOWN,PDIF ++S 1000,5700,1000,9200,800,*,DOWN,PDIF ++S 2400,5100,3600,5100,200,*,LEFT,POLY ++S 4400,5500,4400,9400,200,4,UP,PTRANS ++S 4000,5800,4000,9200,600,n2,DOWN,PDIF ++S 3000,5700,3000,9200,1000,*,DOWN,PDIF ++S 2400,5500,2400,9400,200,2,UP,PTRANS ++S 2000,5700,2000,9200,600,n1,UP,PDIF ++S 1600,5500,1600,9400,200,1,UP,PTRANS ++S 3600,5500,3600,9400,200,3,UP,PTRANS ++S 4400,9400,4400,9700,200,*,DOWN,POLY ++S 3600,9400,3600,9700,200,*,DOWN,POLY ++S 2400,9400,2400,9700,200,*,DOWN,POLY ++S 1600,9400,1600,9700,200,*,DOWN,POLY ++S 0,600,6000,600,1200,vss,RIGHT,CALU1 ++S 0,5000,6000,5000,10000,nr2_x2,LEFT,TALU8 ++S 0,2200,6000,2200,5200,*,LEFT,PWELL ++S 0,7600,6000,7600,5600,*,LEFT,NWELL ++S 0,9400,6000,9400,1200,vdd,RIGHT,CALU1 ++S 2000,2000,2000,3000,400,z,DOWN,CALU1 ++S 1000,3000,2200,3000,600,*,RIGHT,ALU1 ++S 1000,700,1000,2100,400,*,DOWN,ALU1 ++S 2000,4000,2000,5100,400,*,UP,ALU1 ++S 1900,4000,1900,5100,400,*,UP,ALU1 ++S 2900,5000,4000,5000,600,*,LEFT,ALU1 ++S 4000,4900,4000,6100,400,*,UP,ALU1 ++S 4000,5000,4000,6000,400,b,UP,CALU1 ++S 1900,4000,4100,4000,400,*,LEFT,ALU1 ++S 3800,4000,4400,4000,600,*,RIGHT,POLY ++S 3000,6000,3000,7000,400,z,UP,CALU1 ++S 3000,6000,3000,7000,600,*,UP,ALU1 ++S 1000,6100,3000,6100,400,*,RIGHT,ALU1 ++S 1000,6000,3000,6000,400,*,RIGHT,ALU1 ++S 2000,6000,2000,6000,400,z,LEFT,CALU1 ++S 1000,3000,1000,6000,400,z,DOWN,CALU1 ++S 1000,2900,1000,6100,400,*,DOWN,ALU1 ++S 2100,1900,2100,3100,600,*,DOWN,ALU1 ++S 3400,700,3400,3100,400,*,DOWN,ALU1 ++S 4000,4000,4000,4000,400,a,LEFT,CALU1 ++S 5000,6900,5000,9300,400,*,UP,ALU1 ++S 1000,6900,1000,9300,400,*,UP,ALU1 ++S 5000,600,5000,3500,600,*,UP,PTIE ++V 5000,700,CONT_BODY_P,* ++V 2000,4000,CONT_POLY,* ++V 4000,4000,CONT_POLY,* ++V 3000,7000,CONT_DIF_P,* ++V 1000,8000,CONT_DIF_P,* ++V 5000,8000,CONT_DIF_P,* ++V 5000,9000,CONT_DIF_P,* ++V 1000,9000,CONT_DIF_P,* ++V 2200,3000,CONT_DIF_N,* ++V 3000,4900,CONT_POLY,* ++V 2200,2000,CONT_DIF_N,* ++V 1000,2000,CONT_DIF_N,* ++V 3400,2000,CONT_DIF_N,* ++V 3000,6000,CONT_DIF_P,* ++V 3400,3000,CONT_DIF_N,* ++V 1000,7000,CONT_DIF_P,* ++V 5000,7000,CONT_DIF_P,* ++EOF +diff --git a/alliance/src/cells/src/msxlib/nr2_x2.vbe b/alliance/src/cells/src/msxlib/nr2_x2.vbe +new file mode 100644 +index 0000000..ddb1eaa +--- /dev/null ++++ b/alliance/src/cells/src/msxlib/nr2_x2.vbe +@@ -0,0 +1,32 @@ ++ENTITY nr2_x2 IS ++GENERIC ( ++ CONSTANT area : NATURAL := 6000; ++ CONSTANT cin_a : NATURAL := 11; ++ CONSTANT cin_b : NATURAL := 10; ++ CONSTANT rdown_a_z : NATURAL := 1090; ++ CONSTANT rdown_b_z : NATURAL := 1090; ++ CONSTANT rup_a_z : NATURAL := 1490; ++ CONSTANT rup_b_z : NATURAL := 1490; ++ CONSTANT tplh_a_z : NATURAL := 51; ++ CONSTANT tplh_b_z : NATURAL := 41; ++ CONSTANT tphl_b_z : NATURAL := 40; ++ CONSTANT tphl_a_z : NATURAL := 50; ++ CONSTANT transistors : NATURAL := 6 ++); ++PORT ( ++ a : in BIT; ++ b : in BIT; ++ z : out BIT; ++ vdd : in BIT; ++ vss : in BIT ++); ++END nr2_x2; ++ ++ARCHITECTURE behaviour_data_flow OF nr2_x2 IS ++ ++BEGIN ++ ASSERT ((vdd and not (vss)) = '1') ++ REPORT "power supply is missing on nr2_x2" ++ SEVERITY WARNING; ++ z <= not ((a or b)) after 900 ps; ++END; +diff --git a/alliance/src/cells/src/msxlib/nr2a_x05.ap b/alliance/src/cells/src/msxlib/nr2a_x05.ap +new file mode 100644 +index 0000000..b63165e +--- /dev/null ++++ b/alliance/src/cells/src/msxlib/nr2a_x05.ap +@@ -0,0 +1,91 @@ ++V ALLIANCE : 6 ++H nr2a_x05,P, 8/ 8/2014,100 ++A 0,0,5000,10000 ++R 2000,7000,ref_ref,a_70 ++R 2000,2000,ref_ref,z_20 ++R 3000,5000,ref_ref,a_50 ++R 2000,5000,ref_ref,b_50 ++R 1000,6000,ref_ref,z_60 ++R 1000,5000,ref_ref,z_50 ++R 1000,4000,ref_ref,z_40 ++R 3000,6000,ref_ref,a_60 ++R 3000,3000,ref_ref,b_30 ++R 1000,7000,ref_ref,z_70 ++R 2000,4000,ref_ref,b_40 ++R 1000,3000,ref_ref,z_30 ++R 2000,6000,ref_ref,a_60 ++R 1000,2000,ref_ref,z_20 ++R 2000,3000,ref_ref,b_30 ++S 1100,9300,1900,9300,600,*,RIGHT,NTIE ++S 2100,700,2900,700,600,*,LEFT,PTIE ++S 3200,5800,3200,7600,600,*,DOWN,PDIF ++S 2600,2300,2600,5100,200,*,UP,POLY ++S 1400,2300,1400,4200,200,*,UP,POLY ++S 1400,1700,1400,2300,200,4z,DOWN,NTRANS ++S 800,900,800,2100,600,*,UP,NDIF ++S 700,900,700,2100,600,*,UP,NDIF ++S 2600,1700,2600,2300,200,3z,DOWN,NTRANS ++S 2000,1900,2000,2100,1000,*,UP,NDIF ++S 3800,2600,3800,5500,200,*,UP,POLY ++S 3300,1900,3300,2400,600,*,UP,NDIF ++S 3800,1700,3800,2600,200,2a,DOWN,NTRANS ++S 4200,1900,4200,2400,400,*,UP,NDIF ++S 3800,7300,3800,7700,200,*,DOWN,POLY ++S 1600,7800,1600,8100,200,*,DOWN,POLY ++S 2400,7800,2400,8100,200,*,DOWN,POLY ++S 1000,6000,1000,6600,600,*,DOWN,PDIF ++S 4400,6000,4400,6600,600,*,UP,PDIF ++S 1200,5800,1200,7600,400,*,UP,PDIF ++S 1600,5600,1600,7800,200,2z,UP,PTRANS ++S 2000,5800,2000,7600,600,n1,UP,PDIF ++S 2400,5600,2400,7800,200,1z,UP,PTRANS ++S 4200,5800,4200,7100,400,*,DOWN,PDIF ++S 3800,5600,3800,7300,200,1a,UP,PTRANS ++S 2400,5000,2400,5500,200,*,DOWN,POLY ++S 1000,7000,1000,7100,400,*,UP,ALU1 ++S 3200,700,3200,2100,400,*,DOWN,ALU1 ++S 2600,1300,2600,1700,200,*,UP,POLY ++S 1400,1300,1400,1700,200,*,UP,POLY ++S 1600,3900,1600,5500,200,*,DOWN,POLY ++S 1800,4100,2000,4100,600,*,RIGHT,ALU1 ++S 2000,6000,2000,7000,400,a,DOWN,CALU1 ++S 3000,5000,3000,6000,400,a,UP,CALU1 ++S 2000,5900,2000,7100,400,*,UP,ALU1 ++S 3000,6900,3000,9300,400,*,UP,ALU1 ++S 1000,2000,2000,2000,600,*,RIGHT,ALU1 ++S 1000,2000,1000,7000,400,*,DOWN,ALU1 ++S 1000,2000,1000,7000,400,z,DOWN,CALU1 ++S 2000,2000,2000,2000,400,z,LEFT,CALU1 ++S 2000,3000,2000,5100,400,*,UP,ALU1 ++S 2000,3000,2000,5000,400,b,DOWN,CALU1 ++S 3000,3000,3000,3000,400,b,LEFT,CALU1 ++S 2000,2900,3100,2900,400,*,RIGHT,ALU1 ++S 2000,3000,3100,3000,400,*,RIGHT,ALU1 ++S 2800,3900,4400,3900,400,*,RIGHT,ALU1 ++S 3000,4900,3000,6100,400,*,UP,ALU1 ++S 2000,6000,3000,6000,600,*,LEFT,ALU1 ++S 3000,4900,3600,4900,400,*,LEFT,ALU1 ++S 0,5000,5000,5000,10000,nr2a_x05,LEFT,TALU8 ++S 0,2200,5000,2200,5200,*,LEFT,PWELL ++S 0,7600,5000,7600,5600,*,LEFT,NWELL ++S 0,9400,5000,9400,1200,vdd,RIGHT,CALU1 ++S 0,600,5000,600,1200,vss,RIGHT,CALU1 ++S 3800,1300,3800,1700,200,*,UP,POLY ++S 4400,2200,4400,6800,400,*,UP,ALU1 ++V 2000,9300,CONT_BODY_N,* ++V 1000,9300,CONT_BODY_N,* ++V 3000,700,CONT_BODY_P,* ++V 2000,700,CONT_BODY_P,* ++V 4400,5900,CONT_DIF_P,an ++V 4400,2300,CONT_DIF_N,an ++V 1000,6700,CONT_DIF_P,* ++V 1000,5900,CONT_DIF_P,* ++V 4400,6700,CONT_DIF_P,an ++V 3200,2000,CONT_DIF_N,* ++V 2000,2000,CONT_DIF_N,* ++V 3500,4900,CONT_POLY,* ++V 3000,7000,CONT_DIF_P,* ++V 800,1000,CONT_DIF_N,* ++V 2900,3900,CONT_POLY,an ++V 1800,4000,CONT_POLY,* ++EOF +diff --git a/alliance/src/cells/src/msxlib/nr2a_x05.vbe b/alliance/src/cells/src/msxlib/nr2a_x05.vbe +new file mode 100644 +index 0000000..8e51c8d +--- /dev/null ++++ b/alliance/src/cells/src/msxlib/nr2a_x05.vbe +@@ -0,0 +1,32 @@ ++ENTITY nr2a_x05 IS ++GENERIC ( ++ CONSTANT area : NATURAL := 5000; ++ CONSTANT cin_b : NATURAL := 3; ++ CONSTANT cin_a : NATURAL := 4; ++ CONSTANT rdown_b_z : NATURAL := 3810; ++ CONSTANT rdown_a_z : NATURAL := 3820; ++ CONSTANT rup_b_z : NATURAL := 5280; ++ CONSTANT rup_a_z : NATURAL := 5270; ++ CONSTANT tplh_b_z : NATURAL := 46; ++ CONSTANT tphl_b_z : NATURAL := 45; ++ CONSTANT tphh_a_z : NATURAL := 78; ++ CONSTANT tpll_a_z : NATURAL := 93; ++ CONSTANT transistors : NATURAL := 6 ++); ++PORT ( ++ b : in BIT; ++ a : in BIT; ++ z : out BIT; ++ vdd : in BIT; ++ vss : in BIT ++); ++END nr2a_x05; ++ ++ARCHITECTURE behaviour_data_flow OF nr2a_x05 IS ++ ++BEGIN ++ ASSERT ((vdd and not (vss)) = '1') ++ REPORT "power supply is missing on nr2a_x05" ++ SEVERITY WARNING; ++ z <= (not (b) and a) after 1000 ps; ++END; +diff --git a/alliance/src/cells/src/msxlib/nr2a_x1.ap b/alliance/src/cells/src/msxlib/nr2a_x1.ap +new file mode 100644 +index 0000000..169e377 +--- /dev/null ++++ b/alliance/src/cells/src/msxlib/nr2a_x1.ap +@@ -0,0 +1,91 @@ ++V ALLIANCE : 6 ++H nr2a_x1,P, 8/ 8/2014,100 ++A 0,0,5000,10000 ++R 2000,7000,ref_ref,a_70 ++R 2000,2000,ref_ref,z_20 ++R 3000,5000,ref_ref,a_50 ++R 2000,5000,ref_ref,b_50 ++R 1000,6000,ref_ref,z_60 ++R 1000,5000,ref_ref,z_50 ++R 1000,4000,ref_ref,z_40 ++R 3000,6000,ref_ref,a_60 ++R 3000,3000,ref_ref,b_30 ++R 1000,7000,ref_ref,z_70 ++R 2000,4000,ref_ref,b_40 ++R 1000,3000,ref_ref,z_30 ++R 2000,6000,ref_ref,a_60 ++R 1000,2000,ref_ref,z_20 ++R 2000,3000,ref_ref,b_30 ++S 2100,700,2900,700,600,*,LEFT,PTIE ++S 2400,5000,2400,5500,200,*,DOWN,POLY ++S 2600,2800,2600,5100,200,*,UP,POLY ++S 1000,7000,1000,7100,400,*,UP,ALU1 ++S 1000,5900,1000,6500,600,*,DOWN,PDIF ++S 3300,1900,3300,2600,600,*,UP,NDIF ++S 3200,700,3200,2100,400,*,DOWN,ALU1 ++S 2000,1900,2000,2600,1000,*,UP,NDIF ++S 2600,1300,2600,1700,200,*,UP,POLY ++S 1400,1300,1400,1700,200,*,UP,POLY ++S 1600,9400,1600,9700,200,*,DOWN,POLY ++S 2000,5700,2000,9200,600,n1,UP,PDIF ++S 2400,9400,2400,9700,200,*,DOWN,POLY ++S 1200,5700,1200,9200,400,*,UP,PDIF ++S 4400,2400,4400,6700,400,*,UP,ALU1 ++S 3800,2800,3800,5500,200,*,UP,POLY ++S 1600,3900,1600,5500,200,*,DOWN,POLY ++S 1800,4100,2000,4100,600,*,RIGHT,ALU1 ++S 2000,6000,2000,7000,400,a,DOWN,CALU1 ++S 3000,5000,3000,6000,400,a,UP,CALU1 ++S 2000,5900,2000,7100,400,*,UP,ALU1 ++S 3000,6900,3000,9300,400,*,UP,ALU1 ++S 700,900,700,2600,600,*,UP,NDIF ++S 800,900,800,2600,600,*,UP,NDIF ++S 1000,2000,2000,2000,600,*,RIGHT,ALU1 ++S 1000,2000,1000,7000,400,*,DOWN,ALU1 ++S 1000,2000,1000,7000,400,z,DOWN,CALU1 ++S 2000,2000,2000,2000,400,z,LEFT,CALU1 ++S 2000,3000,2000,5100,400,*,UP,ALU1 ++S 2000,3000,2000,5000,400,b,DOWN,CALU1 ++S 3000,3000,3000,3000,400,b,LEFT,CALU1 ++S 2000,2900,3100,2900,400,*,RIGHT,ALU1 ++S 2000,3000,3100,3000,400,*,RIGHT,ALU1 ++S 2800,3900,4400,3900,400,*,RIGHT,ALU1 ++S 4400,5900,4400,6500,600,*,UP,PDIF ++S 4200,1900,4200,2600,400,*,UP,NDIF ++S 4200,5700,4200,7500,400,*,DOWN,PDIF ++S 3800,7700,3800,8100,200,*,DOWN,POLY ++S 3000,4900,3000,6100,400,*,UP,ALU1 ++S 2000,6000,3000,6000,600,*,LEFT,ALU1 ++S 3000,4900,3600,4900,400,*,LEFT,ALU1 ++S 0,5000,5000,5000,10000,nr2a_x1,LEFT,TALU8 ++S 0,2200,5000,2200,5200,*,LEFT,PWELL ++S 0,7600,5000,7600,5600,*,LEFT,NWELL ++S 0,9400,5000,9400,1200,vdd,RIGHT,CALU1 ++S 0,600,5000,600,1200,vss,RIGHT,CALU1 ++S 3800,5500,3800,7700,200,1a,UP,PTRANS ++S 3800,1700,3800,2800,200,2a,DOWN,NTRANS ++S 2400,5500,2400,9400,200,1z,UP,PTRANS ++S 1600,5500,1600,9400,200,2z,UP,PTRANS ++S 2600,1700,2600,2800,200,3z,DOWN,NTRANS ++S 1400,1700,1400,2800,200,4z,DOWN,NTRANS ++S 3800,1300,3800,1700,200,*,UP,POLY ++S 3200,5700,3200,9200,600,*,DOWN,PDIF ++S 1400,2800,1400,4200,200,*,UP,POLY ++V 3000,700,CONT_BODY_P,* ++V 2000,700,CONT_BODY_P,* ++V 4300,9300,CONT_BODY_N,* ++V 1000,6600,CONT_DIF_P,* ++V 1000,5800,CONT_DIF_P,* ++V 3200,2000,CONT_DIF_N,* ++V 2000,2000,CONT_DIF_N,* ++V 3000,8000,CONT_DIF_P,* ++V 3000,9000,CONT_DIF_P,* ++V 4400,5800,CONT_DIF_P,* ++V 3500,4900,CONT_POLY,* ++V 3000,7000,CONT_DIF_P,* ++V 800,1000,CONT_DIF_N,* ++V 4400,6600,CONT_DIF_P,an ++V 4400,2500,CONT_DIF_N,an ++V 2900,3900,CONT_POLY,an ++V 1800,4000,CONT_POLY,* ++EOF +diff --git a/alliance/src/cells/src/msxlib/nr2a_x1.vbe b/alliance/src/cells/src/msxlib/nr2a_x1.vbe +new file mode 100644 +index 0000000..4a7dc13 +--- /dev/null ++++ b/alliance/src/cells/src/msxlib/nr2a_x1.vbe +@@ -0,0 +1,32 @@ ++ENTITY nr2a_x1 IS ++GENERIC ( ++ CONSTANT area : NATURAL := 5000; ++ CONSTANT cin_b : NATURAL := 5; ++ CONSTANT cin_a : NATURAL := 4; ++ CONSTANT rdown_b_z : NATURAL := 2080; ++ CONSTANT rdown_a_z : NATURAL := 2080; ++ CONSTANT rup_b_z : NATURAL := 2980; ++ CONSTANT rup_a_z : NATURAL := 2980; ++ CONSTANT tplh_b_z : NATURAL := 44; ++ CONSTANT tphl_b_z : NATURAL := 42; ++ CONSTANT tphh_a_z : NATURAL := 82; ++ CONSTANT tpll_a_z : NATURAL := 95; ++ CONSTANT transistors : NATURAL := 6 ++); ++PORT ( ++ b : in BIT; ++ a : in BIT; ++ z : out BIT; ++ vdd : in BIT; ++ vss : in BIT ++); ++END nr2a_x1; ++ ++ARCHITECTURE behaviour_data_flow OF nr2a_x1 IS ++ ++BEGIN ++ ASSERT ((vdd and not (vss)) = '1') ++ REPORT "power supply is missing on nr2a_x1" ++ SEVERITY WARNING; ++ z <= (not (b) and a) after 1000 ps; ++END; +diff --git a/alliance/src/cells/src/msxlib/nr3_x05.ap b/alliance/src/cells/src/msxlib/nr3_x05.ap +new file mode 100644 +index 0000000..e081561 +--- /dev/null ++++ b/alliance/src/cells/src/msxlib/nr3_x05.ap +@@ -0,0 +1,96 @@ ++V ALLIANCE : 6 ++H nr3_x05,P, 8/ 8/2014,100 ++A 0,0,5000,10000 ++R 4000,6000,ref_ref,a_60 ++R 1000,6000,ref_ref,z_60 ++R 1000,5000,ref_ref,z_50 ++R 1000,4000,ref_ref,z_40 ++R 3000,4000,ref_ref,b_40 ++R 4000,5000,ref_ref,a_50 ++R 1000,3000,ref_ref,z_30 ++R 3000,5000,ref_ref,b_50 ++R 2000,4000,ref_ref,c_40 ++R 2000,3000,ref_ref,c_30 ++R 3000,3000,ref_ref,c_30 ++R 4000,3000,ref_ref,c_30 ++R 1000,2000,ref_ref,z_20 ++R 2000,2000,ref_ref,z_20 ++R 3000,2000,ref_ref,z_20 ++R 1000,7000,ref_ref,z_70 ++R 3000,6000,ref_ref,a_60 ++R 4000,4000,ref_ref,b_40 ++S 3600,700,4200,700,600,*,LEFT,PTIE ++S 2800,2800,2800,4400,200,*,UP,POLY ++S 2600,2400,2600,2900,200,*,UP,POLY ++S 1400,2400,1400,3900,200,*,UP,POLY ++S 1600,3500,1600,5500,200,*,DOWN,POLY ++S 2400,4500,2800,4500,200,*,LEFT,POLY ++S 2000,2000,2000,2000,400,z,LEFT,CALU1 ++S 3000,2000,3000,2000,400,z,LEFT,CALU1 ++S 4000,3000,4000,3000,400,c,LEFT,CALU1 ++S 3000,3000,3000,3000,400,c,LEFT,CALU1 ++S 1000,5700,1000,6700,600,*,UP,PDIF ++S 0,600,5000,600,1200,vss,RIGHT,CALU1 ++S 0,9400,5000,9400,1200,vdd,RIGHT,CALU1 ++S 0,5000,5000,5000,10000,nr3_x05,LEFT,TALU8 ++S 0,2200,5000,2200,5200,*,LEFT,PWELL ++S 0,7600,5000,7600,5600,*,LEFT,NWELL ++S 1200,5700,1200,9200,400,*,UP,PDIF ++S 1600,5500,1600,9400,200,1,UP,PTRANS ++S 1600,9400,1600,9700,200,*,DOWN,POLY ++S 2400,5500,2400,9400,200,2,UP,PTRANS ++S 2000,5700,2000,9200,600,n2,DOWN,PDIF ++S 2400,9400,2400,9700,200,*,DOWN,POLY ++S 3200,5500,3200,9400,200,3,UP,PTRANS ++S 2800,5700,2800,9200,600,n1,DOWN,PDIF ++S 3200,9400,3200,9700,200,*,DOWN,POLY ++S 3800,5700,3800,9200,800,*,DOWN,PDIF ++S 3200,5100,3800,5100,200,*,RIGHT,POLY ++S 2400,4500,2400,5500,200,*,UP,POLY ++S 1400,1600,1400,2400,200,4,DOWN,NTRANS ++S 2600,1600,2600,2400,200,5,DOWN,NTRANS ++S 3800,1600,3800,2400,200,6,DOWN,NTRANS ++S 2000,900,2000,2200,600,*,UP,NDIF ++S 900,1800,900,2200,800,*,DOWN,NDIF ++S 3200,1800,3200,2200,1000,*,UP,NDIF ++S 700,2000,3300,2000,400,*,RIGHT,ALU1 ++S 4400,700,4400,2100,400,*,DOWN,ALU1 ++S 4400,1800,4400,2200,600,*,UP,NDIF ++S 3800,2400,3800,4600,200,*,UP,POLY ++S 2000,3000,4100,3000,400,*,LEFT,ALU1 ++S 2000,2900,4100,2900,400,*,LEFT,ALU1 ++S 1000,2000,1000,7000,400,z,DOWN,CALU1 ++S 1000,2000,1000,7100,400,*,DOWN,ALU1 ++S 1400,1200,1400,1600,200,*,DOWN,POLY ++S 2600,1200,2600,1600,200,*,DOWN,POLY ++S 3800,1200,3800,1600,200,*,DOWN,POLY ++S 2600,2800,2800,2800,200,*,RIGHT,POLY ++S 2600,2900,2800,2900,200,*,RIGHT,POLY ++S 2000,3000,2000,4000,400,c,UP,CALU1 ++S 3000,3900,3000,5100,400,*,DOWN,ALU1 ++S 3000,4000,3000,5000,400,b,UP,CALU1 ++S 2900,6000,4000,6000,400,*,RIGHT,ALU1 ++S 2900,6100,4000,6100,400,*,RIGHT,ALU1 ++S 3000,6000,3000,6000,400,a,LEFT,CALU1 ++S 4000,4800,4000,6100,400,*,UP,ALU1 ++S 4000,5000,4000,6000,400,a,UP,CALU1 ++S 4000,4000,4000,4000,400,b,LEFT,CALU1 ++S 3000,3900,4100,3900,400,*,RIGHT,ALU1 ++S 3000,4000,4100,4000,400,*,RIGHT,ALU1 ++S 2000,2900,2000,4100,400,*,DOWN,ALU1 ++S 3800,6900,3800,9300,400,*,UP,ALU1 ++V 4200,700,CONT_BODY_P,* ++V 3500,700,CONT_BODY_P,* ++V 2000,3700,CONT_POLY,* ++V 3000,4300,CONT_POLY,* ++V 1000,6600,CONT_DIF_P,* ++V 4400,2000,CONT_DIF_N,* ++V 4000,4900,CONT_POLY,* ++V 3200,2000,CONT_DIF_N,* ++V 800,2000,CONT_DIF_N,* ++V 2000,1000,CONT_DIF_N,* ++V 1000,5800,CONT_DIF_P,* ++V 3800,8000,CONT_DIF_P,* ++V 3800,9000,CONT_DIF_P,* ++V 3800,7000,CONT_DIF_P,* ++EOF +diff --git a/alliance/src/cells/src/msxlib/nr3_x05.vbe b/alliance/src/cells/src/msxlib/nr3_x05.vbe +new file mode 100644 +index 0000000..7d04efe +--- /dev/null ++++ b/alliance/src/cells/src/msxlib/nr3_x05.vbe +@@ -0,0 +1,38 @@ ++ENTITY nr3_x05 IS ++GENERIC ( ++ CONSTANT area : NATURAL := 5000; ++ CONSTANT cin_b : NATURAL := 5; ++ CONSTANT cin_c : NATURAL := 5; ++ CONSTANT cin_a : NATURAL := 5; ++ CONSTANT rdown_b_z : NATURAL := 2890; ++ CONSTANT rdown_c_z : NATURAL := 2880; ++ CONSTANT rdown_a_z : NATURAL := 2940; ++ CONSTANT rup_b_z : NATURAL := 4480; ++ CONSTANT rup_c_z : NATURAL := 4480; ++ CONSTANT rup_a_z : NATURAL := 4480; ++ CONSTANT tplh_a_z : NATURAL := 80; ++ CONSTANT tphl_c_z : NATURAL := 49; ++ CONSTANT tplh_c_z : NATURAL := 50; ++ CONSTANT tplh_b_z : NATURAL := 71; ++ CONSTANT tphl_b_z : NATURAL := 62; ++ CONSTANT tphl_a_z : NATURAL := 70; ++ CONSTANT transistors : NATURAL := 6 ++); ++PORT ( ++ b : in BIT; ++ c : in BIT; ++ a : in BIT; ++ z : out BIT; ++ vdd : in BIT; ++ vss : in BIT ++); ++END nr3_x05; ++ ++ARCHITECTURE behaviour_data_flow OF nr3_x05 IS ++ ++BEGIN ++ ASSERT ((vdd and not (vss)) = '1') ++ REPORT "power supply is missing on nr3_x05" ++ SEVERITY WARNING; ++ z <= not (((b or c) or a)) after 1000 ps; ++END; +diff --git a/alliance/src/cells/src/msxlib/nr3_x1.ap b/alliance/src/cells/src/msxlib/nr3_x1.ap +new file mode 100644 +index 0000000..5804880 +--- /dev/null ++++ b/alliance/src/cells/src/msxlib/nr3_x1.ap +@@ -0,0 +1,127 @@ ++V ALLIANCE : 6 ++H nr3_x1,P, 9/ 8/2014,100 ++A 0,0,7000,10000 ++R 3000,2000,ref_ref,z_20 ++R 2000,2000,ref_ref,z_20 ++R 1000,2000,ref_ref,z_20 ++R 1000,3000,ref_ref,z_30 ++R 3000,7000,ref_ref,z_70 ++R 2000,4000,ref_ref,a_40 ++R 2000,3000,ref_ref,a_30 ++R 6000,5000,ref_ref,a_50 ++R 2000,5000,ref_ref,a_50 ++R 2000,7000,ref_ref,z_70 ++R 1000,6000,ref_ref,z_60 ++R 1000,5000,ref_ref,z_50 ++R 1000,4000,ref_ref,z_40 ++R 3000,4000,ref_ref,b_40 ++R 3000,6000,ref_ref,a_60 ++R 4000,6000,ref_ref,a_60 ++R 5000,6000,ref_ref,a_60 ++R 6000,6000,ref_ref,a_60 ++R 5000,5000,ref_ref,b_50 ++R 4000,5000,ref_ref,b_50 ++R 3000,5000,ref_ref,b_50 ++R 3000,3000,ref_ref,b_30 ++R 1000,7000,ref_ref,z_70 ++R 2000,6000,ref_ref,a_60 ++R 6000,3000,ref_ref,c_30 ++R 6000,2000,ref_ref,c_20 ++R 6000,4000,ref_ref,c_40 ++R 5000,3000,ref_ref,c_30 ++R 4000,3000,ref_ref,c_30 ++S 3000,7000,3000,7000,400,z,LEFT,CALU1 ++S 2000,7000,2000,7000,400,z,LEFT,CALU1 ++S 2000,2000,2000,2000,400,z,LEFT,CALU1 ++S 3000,2000,3000,2000,400,z,LEFT,CALU1 ++S 3000,6000,3000,6000,400,a,LEFT,CALU1 ++S 4000,6000,4000,6000,400,a,LEFT,CALU1 ++S 5000,6000,5000,6000,400,a,LEFT,CALU1 ++S 5000,5000,5000,5000,400,b,LEFT,CALU1 ++S 4000,5000,4000,5000,400,b,LEFT,CALU1 ++S 800,5700,800,9200,800,*,DOWN,PDIF ++S 2000,2900,2000,3100,400,*,DOWN,ALU1 ++S 4000,4900,4000,5000,600,*,UP,ALU1 ++S 5400,5700,5400,9200,600,n3,DOWN,PDIF ++S 4600,5700,4600,9200,600,n4,DOWN,PDIF ++S 1800,5700,1800,9200,600,n1,DOWN,PDIF ++S 2600,5700,2600,9200,600,n2,DOWN,PDIF ++S 5800,5500,5800,9400,200,6,UP,PTRANS ++S 5000,5500,5000,9400,200,5,UP,PTRANS ++S 4200,5500,4200,9400,200,4,UP,PTRANS ++S 6300,5700,6300,9200,800,*,DOWN,PDIF ++S 5800,9400,5800,9700,200,*,DOWN,POLY ++S 5000,9400,5000,9700,200,*,DOWN,POLY ++S 4200,9400,4200,9700,200,*,DOWN,POLY ++S 1400,9400,1400,9700,200,*,DOWN,POLY ++S 2200,4500,2600,4500,200,*,LEFT,POLY ++S 3500,5700,3500,9200,800,*,DOWN,PDIF ++S 3000,5500,3000,9400,200,3,UP,PTRANS ++S 1400,5500,1400,9400,200,1,UP,PTRANS ++S 2200,5500,2200,9400,200,2,UP,PTRANS ++S 0,600,7000,600,1200,vss,RIGHT,CALU1 ++S 0,5000,7000,5000,10000,nr3_x1,LEFT,TALU8 ++S 0,2200,7000,2200,5200,*,LEFT,PWELL ++S 0,7600,7000,7600,5600,*,LEFT,NWELL ++S 0,9400,7000,9400,1200,vdd,RIGHT,CALU1 ++S 3000,9400,3000,9700,200,*,DOWN,POLY ++S 2200,9400,2200,9700,200,*,DOWN,POLY ++S 3000,3000,3000,5000,400,b,UP,CALU1 ++S 3000,2900,3000,5100,400,*,UP,ALU1 ++S 3000,5100,4200,5100,200,*,RIGHT,POLY ++S 3000,5000,5100,5000,600,*,RIGHT,ALU1 ++S 1400,3800,1400,5500,200,*,UP,POLY ++S 2200,4500,2200,5500,200,*,UP,POLY ++S 2000,3000,2000,6000,400,a,UP,CALU1 ++S 2000,4100,2000,6000,400,*,UP,ALU1 ++S 2000,6000,6000,6000,400,*,LEFT,ALU1 ++S 6000,5000,6000,6000,400,a,UP,CALU1 ++S 1000,2000,1000,7000,400,z,DOWN,CALU1 ++S 1000,2000,1000,7000,400,*,DOWN,ALU1 ++S 3600,7000,3600,8100,400,*,UP,ALU1 ++S 800,7900,800,9300,400,*,UP,ALU1 ++S 6400,7900,6400,9300,400,*,UP,ALU1 ++S 1900,2900,1900,6000,400,*,UP,ALU1 ++S 1400,3800,1800,3800,200,*,RIGHT,POLY ++S 1000,2000,3700,2000,400,*,RIGHT,ALU1 ++S 1000,1900,3700,1900,400,*,RIGHT,ALU1 ++S 6000,4900,6000,6000,600,*,UP,ALU1 ++S 1400,900,1400,2000,400,*,DOWN,NDIF ++S 1800,700,1800,2200,200,7,DOWN,NTRANS ++S 1800,300,1800,700,200,*,UP,POLY ++S 1800,2200,1800,3600,200,*,UP,POLY ++S 3600,900,3600,2000,1000,*,UP,NDIF ++S 4200,700,4200,2200,200,9,DOWN,NTRANS ++S 3000,700,3000,2200,200,8,DOWN,NTRANS ++S 2400,900,2400,2000,600,*,UP,NDIF ++S 4900,900,4900,2000,600,*,UP,NDIF ++S 4200,2200,4200,5100,200,*,UP,POLY ++S 3000,2200,3000,4500,200,*,UP,POLY ++S 1000,7100,3600,7100,400,*,RIGHT,ALU1 ++S 1000,7000,3600,7000,400,*,RIGHT,ALU1 ++S 6000,2000,6000,4000,400,c,UP,CALU1 ++S 4000,3000,4000,3000,400,c,LEFT,CALU1 ++S 5000,3000,5000,3000,400,c,LEFT,CALU1 ++S 4000,3000,6000,3000,600,*,RIGHT,ALU1 ++S 4200,300,4200,700,200,*,UP,POLY ++S 3000,300,3000,700,200,*,UP,POLY ++S 4800,700,4800,1900,400,*,UP,ALU1 ++S 6000,1900,6000,4100,400,*,UP,ALU1 ++V 6200,700,CONT_BODY_P,* ++V 3600,7100,CONT_DIF_P,* ++V 6000,4900,CONT_POLY,* ++V 3600,8000,CONT_DIF_P,* ++V 3000,4300,CONT_POLY,* ++V 5000,4900,CONT_POLY,* ++V 2000,3600,CONT_POLY,* ++V 800,8000,CONT_DIF_P,* ++V 6400,8000,CONT_DIF_P,* ++V 800,9000,CONT_DIF_P,* ++V 6400,9000,CONT_DIF_P,* ++V 4800,1000,CONT_DIF_N,* ++V 2400,1000,CONT_DIF_N,* ++V 1200,1900,CONT_DIF_N,* ++V 3600,1900,CONT_DIF_N,* ++V 4000,3000,CONT_POLY,* ++V 4800,1800,CONT_DIF_N,* ++EOF +diff --git a/alliance/src/cells/src/msxlib/nr3_x1.vbe b/alliance/src/cells/src/msxlib/nr3_x1.vbe +new file mode 100644 +index 0000000..d4c2e89 +--- /dev/null ++++ b/alliance/src/cells/src/msxlib/nr3_x1.vbe +@@ -0,0 +1,38 @@ ++ENTITY nr3_x1 IS ++GENERIC ( ++ CONSTANT area : NATURAL := 7000; ++ CONSTANT cin_b : NATURAL := 10; ++ CONSTANT cin_c : NATURAL := 9; ++ CONSTANT cin_a : NATURAL := 11; ++ CONSTANT rdown_b_z : NATURAL := 1540; ++ CONSTANT rdown_c_z : NATURAL := 1540; ++ CONSTANT rdown_a_z : NATURAL := 1570; ++ CONSTANT rup_b_z : NATURAL := 2240; ++ CONSTANT rup_c_z : NATURAL := 2230; ++ CONSTANT rup_a_z : NATURAL := 2240; ++ CONSTANT tplh_a_z : NATURAL := 78; ++ CONSTANT tphl_c_z : NATURAL := 47; ++ CONSTANT tplh_c_z : NATURAL := 45; ++ CONSTANT tplh_b_z : NATURAL := 67; ++ CONSTANT tphl_b_z : NATURAL := 62; ++ CONSTANT tphl_a_z : NATURAL := 71; ++ CONSTANT transistors : NATURAL := 9 ++); ++PORT ( ++ b : in BIT; ++ c : in BIT; ++ a : in BIT; ++ z : out BIT; ++ vdd : in BIT; ++ vss : in BIT ++); ++END nr3_x1; ++ ++ARCHITECTURE behaviour_data_flow OF nr3_x1 IS ++ ++BEGIN ++ ASSERT ((vdd and not (vss)) = '1') ++ REPORT "power supply is missing on nr3_x1" ++ SEVERITY WARNING; ++ z <= not (((b or c) or a)) after 1000 ps; ++END; +diff --git a/alliance/src/cells/src/msxlib/nr4_x05.ap b/alliance/src/cells/src/msxlib/nr4_x05.ap +new file mode 100644 +index 0000000..af0a64d +--- /dev/null ++++ b/alliance/src/cells/src/msxlib/nr4_x05.ap +@@ -0,0 +1,118 @@ ++V ALLIANCE : 6 ++H nr4_x05,P, 9/ 8/2014,100 ++A 0,0,6000,10000 ++R 3000,5000,ref_ref,d_50 ++R 1000,6000,ref_ref,z_60 ++R 3000,6000,ref_ref,d_60 ++R 5000,7000,ref_ref,a_70 ++R 5000,6000,ref_ref,a_60 ++R 5000,4000,ref_ref,b_40 ++R 2000,4000,ref_ref,d_40 ++R 4000,5000,ref_ref,c_50 ++R 3000,3000,ref_ref,c_30 ++R 2000,7000,ref_ref,z_70 ++R 4000,2000,ref_ref,z_20 ++R 3000,2000,ref_ref,z_20 ++R 2000,2000,ref_ref,z_20 ++R 4000,3000,ref_ref,b_30 ++R 5000,5000,ref_ref,a_50 ++R 1000,3000,ref_ref,z_30 ++R 1000,4000,ref_ref,z_40 ++R 4000,4000,ref_ref,c_40 ++R 2000,6000,ref_ref,z_60 ++R 1000,5000,ref_ref,z_50 ++R 5000,3000,ref_ref,b_30 ++R 3000,4000,ref_ref,c_40 ++R 2000,5000,ref_ref,d_50 ++R 1000,2000,ref_ref,z_20 ++R 4000,7000,ref_ref,a_70 ++S 4300,700,5100,700,600,*,RIGHT,PTIE ++S 4800,4900,5000,4900,600,*,RIGHT,POLY ++S 2200,5100,2400,5100,200,*,LEFT,POLY ++S 1000,6000,2000,6000,600,*,LEFT,ALU1 ++S 3900,3000,5000,3000,400,*,RIGHT,ALU1 ++S 5000,5000,5000,7000,400,a,UP,CALU1 ++S 4800,9400,4800,9700,200,*,DOWN,POLY ++S 4000,9400,4000,9700,200,*,DOWN,POLY ++S 3200,9400,3200,9700,200,*,DOWN,POLY ++S 2400,9400,2400,9700,200,*,DOWN,POLY ++S 1800,1900,1800,2100,1000,*,UP,NDIF ++S 3000,900,3000,2100,600,*,UP,NDIF ++S 4200,1900,4200,2100,1000,*,UP,NDIF ++S 600,900,600,2100,600,*,UP,NDIF ++S 0,5000,6000,5000,10000,nr4_x05,LEFT,TALU8 ++S 0,2200,6000,2200,5200,*,LEFT,PWELL ++S 0,7600,6000,7600,5600,*,LEFT,NWELL ++S 0,600,6000,600,1200,vss,RIGHT,CALU1 ++S 0,9400,6000,9400,1200,vdd,RIGHT,CALU1 ++S 2400,3800,2800,3800,200,*,LEFT,POLY ++S 1200,1300,1200,1900,200,*,UP,POLY ++S 2400,1300,2400,1900,200,*,UP,POLY ++S 3600,1300,3600,1900,200,*,UP,POLY ++S 4800,1300,4800,1900,200,*,UP,POLY ++S 1200,1700,1200,2300,200,5,DOWN,NTRANS ++S 2400,1700,2400,2300,200,6,DOWN,NTRANS ++S 3600,1700,3600,2300,200,7,DOWN,NTRANS ++S 4800,1700,4800,2300,200,8,DOWN,NTRANS ++S 1200,4700,2000,4700,200,*,LEFT,POLY ++S 2400,5500,2400,9400,200,1,UP,PTRANS ++S 2800,5700,2800,9200,600,n3,UP,PDIF ++S 3200,5500,3200,9400,200,2,UP,PTRANS ++S 3600,5700,3600,9200,600,n2,UP,PDIF ++S 4000,5500,4000,9400,200,3,UP,PTRANS ++S 4800,5500,4800,9400,200,4,UP,PTRANS ++S 4400,5700,4400,9200,600,n1,UP,PDIF ++S 5400,5700,5400,9200,600,*,DOWN,PDIF ++S 5400,7900,5400,9300,400,*,DOWN,ALU1 ++S 1800,5900,1800,7100,600,*,UP,PDIF ++S 2000,5700,2000,9200,400,*,DOWN,PDIF ++S 5000,4900,5000,7000,600,*,DOWN,ALU1 ++S 5000,3000,5000,4100,400,*,UP,ALU1 ++S 5000,3000,5000,4000,400,b,UP,CALU1 ++S 3900,2900,5000,2900,400,*,RIGHT,ALU1 ++S 3000,3000,3000,4000,400,c,DOWN,CALU1 ++S 3000,2900,3000,4000,400,*,DOWN,ALU1 ++S 3000,4000,4000,4000,600,*,RIGHT,ALU1 ++S 4000,4000,4000,5000,400,c,UP,CALU1 ++S 4000,4000,4000,5100,400,*,UP,ALU1 ++S 2000,5000,3000,5000,600,*,RIGHT,ALU1 ++S 2000,3900,2000,4600,400,*,DOWN,ALU1 ++S 3000,5000,3000,6100,400,*,UP,ALU1 ++S 3000,5000,3000,6000,400,d,UP,CALU1 ++S 3200,4000,3200,5500,200,*,DOWN,POLY ++S 4000,3200,4000,5500,200,*,DOWN,POLY ++S 3600,2300,3600,3200,200,*,UP,POLY ++S 4800,2300,4800,5500,200,*,DOWN,POLY ++S 2400,2300,2400,3800,200,*,DOWN,POLY ++S 1200,2300,1200,4700,200,*,DOWN,POLY ++S 1000,2000,1000,6000,400,z,DOWN,CALU1 ++S 1000,2000,1000,6000,400,*,DOWN,ALU1 ++S 1000,2000,4300,2000,400,*,RIGHT,ALU1 ++S 5400,700,5400,2100,400,*,DOWN,ALU1 ++S 1000,1900,4300,1900,400,*,RIGHT,ALU1 ++S 3900,7000,5000,7000,400,*,RIGHT,ALU1 ++S 1900,5900,1900,7100,600,*,DOWN,ALU1 ++S 2000,2000,2000,2000,400,z,LEFT,CALU1 ++S 3000,2000,3000,2000,400,z,LEFT,CALU1 ++S 4000,2000,4000,2000,400,z,LEFT,CALU1 ++S 2000,6000,2000,7000,400,z,UP,CALU1 ++S 2000,4000,2000,5000,400,d,DOWN,CALU1 ++S 4000,3000,4000,3000,400,b,LEFT,CALU1 ++S 4000,7000,4000,7000,400,a,LEFT,CALU1 ++V 700,9300,CONT_BODY_N,* ++V 5200,700,CONT_BODY_P,* ++V 4200,700,CONT_BODY_P,* ++V 4000,3000,CONT_POLY,* ++V 600,1000,CONT_DIF_N,* ++V 3000,1000,CONT_DIF_N,* ++V 1800,2000,CONT_DIF_N,* ++V 4200,2000,CONT_DIF_N,* ++V 1800,7000,CONT_DIF_P,* ++V 1800,6000,CONT_DIF_P,* ++V 3200,4000,CONT_POLY,* ++V 5400,8000,CONT_DIF_P,* ++V 5400,9000,CONT_DIF_P,* ++V 5000,4900,CONT_POLY,* ++V 2200,4900,CONT_POLY,* ++V 5400,2000,CONT_DIF_N,* ++EOF +diff --git a/alliance/src/cells/src/msxlib/nr4_x05.vbe b/alliance/src/cells/src/msxlib/nr4_x05.vbe +new file mode 100644 +index 0000000..d7f5ce1 +--- /dev/null ++++ b/alliance/src/cells/src/msxlib/nr4_x05.vbe +@@ -0,0 +1,44 @@ ++ENTITY nr4_x05 IS ++GENERIC ( ++ CONSTANT area : NATURAL := 6000; ++ CONSTANT cin_c : NATURAL := 5; ++ CONSTANT cin_d : NATURAL := 5; ++ CONSTANT cin_b : NATURAL := 5; ++ CONSTANT cin_a : NATURAL := 5; ++ CONSTANT rdown_c_z : NATURAL := 3840; ++ CONSTANT rdown_d_z : NATURAL := 3840; ++ CONSTANT rdown_b_z : NATURAL := 3910; ++ CONSTANT rdown_a_z : NATURAL := 4010; ++ CONSTANT rup_c_z : NATURAL := 5980; ++ CONSTANT rup_d_z : NATURAL := 5980; ++ CONSTANT rup_b_z : NATURAL := 5980; ++ CONSTANT rup_a_z : NATURAL := 5980; ++ CONSTANT tphl_d_z : NATURAL := 58; ++ CONSTANT tplh_a_z : NATURAL := 117; ++ CONSTANT tplh_d_z : NATURAL := 52; ++ CONSTANT tphl_c_z : NATURAL := 77; ++ CONSTANT tplh_b_z : NATURAL := 107; ++ CONSTANT tplh_c_z : NATURAL := 86; ++ CONSTANT tphl_b_z : NATURAL := 90; ++ CONSTANT tphl_a_z : NATURAL := 97; ++ CONSTANT transistors : NATURAL := 8 ++); ++PORT ( ++ c : in BIT; ++ d : in BIT; ++ b : in BIT; ++ a : in BIT; ++ z : out BIT; ++ vdd : in BIT; ++ vss : in BIT ++); ++END nr4_x05; ++ ++ARCHITECTURE behaviour_data_flow OF nr4_x05 IS ++ ++BEGIN ++ ASSERT ((vdd and not (vss)) = '1') ++ REPORT "power supply is missing on nr4_x05" ++ SEVERITY WARNING; ++ z <= not ((((c or d) or b) or a)) after 1100 ps; ++END; +diff --git a/alliance/src/cells/src/msxlib/nr4_x1.ap b/alliance/src/cells/src/msxlib/nr4_x1.ap +new file mode 100644 +index 0000000..583cb7d +--- /dev/null ++++ b/alliance/src/cells/src/msxlib/nr4_x1.ap +@@ -0,0 +1,170 @@ ++V ALLIANCE : 6 ++H nr4_x1,P, 9/ 8/2014,100 ++A 0,0,9000,10000 ++R 7000,5000,ref_ref,d_50 ++R 7000,7000,ref_ref,d_70 ++R 7000,6000,ref_ref,d_60 ++R 2000,2000,ref_ref,z_20 ++R 7000,4000,ref_ref,b_40 ++R 7000,3000,ref_ref,b_30 ++R 5000,5000,ref_ref,a_50 ++R 3000,6000,ref_ref,a_60 ++R 3000,5000,ref_ref,a_50 ++R 5000,7000,ref_ref,z_70 ++R 4000,7000,ref_ref,z_70 ++R 3000,7000,ref_ref,z_70 ++R 2000,7000,ref_ref,z_70 ++R 2000,6000,ref_ref,z_60 ++R 7000,8000,ref_ref,d_80 ++R 6000,8000,ref_ref,d_80 ++R 5000,8000,ref_ref,d_80 ++R 4000,8000,ref_ref,d_80 ++R 3000,8000,ref_ref,d_80 ++R 2000,8000,ref_ref,d_80 ++R 1000,8000,ref_ref,d_80 ++R 1000,7000,ref_ref,d_70 ++R 4000,3000,ref_ref,b_30 ++R 3000,3000,ref_ref,b_30 ++R 4000,5000,ref_ref,a_50 ++R 6000,4000,ref_ref,c_40 ++R 6000,3000,ref_ref,b_30 ++R 1000,5000,ref_ref,d_50 ++R 4000,2000,ref_ref,z_20 ++R 3000,2000,ref_ref,z_20 ++R 4000,4000,ref_ref,c_40 ++R 5000,3000,ref_ref,b_30 ++R 5000,4000,ref_ref,c_40 ++R 2000,4000,ref_ref,z_40 ++R 2000,3000,ref_ref,z_30 ++R 2000,5000,ref_ref,z_50 ++R 1000,6000,ref_ref,d_60 ++R 8000,5000,ref_ref,d_50 ++R 3000,4000,ref_ref,a_40 ++R 6000,5000,ref_ref,c_50 ++R 6000,6000,ref_ref,c_60 ++R 7000,2000,ref_ref,b_20 ++R 5000,6000,ref_ref,z_60 ++S 7100,700,7900,700,600,*,RIGHT,PTIE ++S 7100,4900,7100,8000,400,*,UP,ALU1 ++S 7000,4900,7000,8000,400,*,UP,ALU1 ++S 900,4800,900,8000,400,*,DOWN,ALU1 ++S 8400,6900,8400,9300,400,*,DOWN,ALU1 ++S 7000,4900,8100,4900,400,*,RIGHT,ALU1 ++S 7000,5000,8100,5000,400,*,RIGHT,ALU1 ++S 1000,8000,7000,8000,400,*,LEFT,ALU1 ++S 5000,900,5000,1300,200,*,UP,POLY ++S 3800,900,3800,1300,200,*,UP,POLY ++S 2000,1900,4500,1900,400,*,RIGHT,ALU1 ++S 2000,2000,4500,2000,400,*,RIGHT,ALU1 ++S 2000,2000,2000,7000,400,*,DOWN,ALU1 ++S 2000,2000,2000,7000,400,z,DOWN,CALU1 ++S 7000,1900,7000,4100,400,*,DOWN,ALU1 ++S 7000,2000,7000,4000,400,b,DOWN,CALU1 ++S 5000,2400,5000,5100,200,*,UP,POLY ++S 4200,5100,5400,5100,200,*,RIGHT,POLY ++S 3900,4000,6000,4000,400,*,LEFT,ALU1 ++S 3900,3900,6000,3900,400,*,LEFT,ALU1 ++S 5000,1300,5000,2400,200,12,DOWN,NTRANS ++S 4400,1500,4400,2200,1000,*,UP,NDIF ++S 3800,2400,3800,3900,200,*,UP,POLY ++S 3800,1300,3800,2400,200,11,DOWN,NTRANS ++S 3200,900,3200,2200,600,*,UP,NDIF ++S 2600,900,2600,1300,200,*,UP,POLY ++S 1400,900,1400,1300,200,*,UP,POLY ++S 2600,2400,2600,5500,200,*,DOWN,POLY ++S 2600,1300,2600,2400,200,10,DOWN,NTRANS ++S 2000,1500,2000,2200,1000,*,UP,NDIF ++S 1400,1300,1400,2400,200,9,DOWN,NTRANS ++S 7000,3200,7000,5500,200,*,DOWN,POLY ++S 6200,4200,6200,5500,200,*,DOWN,POLY ++S 6000,4000,6000,6000,400,c,UP,CALU1 ++S 6000,4000,6000,6100,400,*,UP,ALU1 ++S 3000,3900,3000,6100,400,*,DOWN,ALU1 ++S 3000,4000,3000,6000,400,a,DOWN,CALU1 ++S 3400,4100,3400,5500,200,*,DOWN,POLY ++S 3400,4100,4200,4100,200,*,RIGHT,POLY ++S 1000,4800,1000,8000,400,*,DOWN,ALU1 ++S 1000,5000,1000,8000,400,d,UP,CALU1 ++S 1200,5700,1200,9200,600,*,UP,PDIF ++S 8400,5700,8400,9200,600,*,DOWN,PDIF ++S 7800,5500,7800,9400,200,08,UP,PTRANS ++S 7400,5700,7400,9200,600,n4,UP,PDIF ++S 7000,5500,7000,9400,200,07,UP,PTRANS ++S 6600,5700,6600,9200,600,n5,UP,PDIF ++S 6200,5500,6200,9400,200,06,UP,PTRANS ++S 5800,5700,5800,9200,600,n6,UP,PDIF ++S 4800,5700,4800,9200,600,*,DOWN,PDIF ++S 5400,5500,5400,9400,200,05,UP,PTRANS ++S 4200,5500,4200,9400,200,04,UP,PTRANS ++S 3800,5700,3800,9200,600,n3,UP,PDIF ++S 3400,5500,3400,9400,200,03,UP,PTRANS ++S 3000,5700,3000,9200,600,n2,UP,PDIF ++S 2600,5500,2600,9400,200,02,UP,PTRANS ++S 2200,5700,2200,9200,600,n1,UP,PDIF ++S 1800,5500,1800,9400,200,01,UP,PTRANS ++S 0,5000,9000,5000,10000,nr4_x1,LEFT,TALU8 ++S 0,2200,9000,2200,5200,*,LEFT,PWELL ++S 0,7600,9000,7600,5600,*,LEFT,NWELL ++S 0,9400,9000,9400,1200,vdd,RIGHT,CALU1 ++S 0,600,9000,600,1200,vss,RIGHT,CALU1 ++S 4200,9400,4200,9700,200,*,DOWN,POLY ++S 3400,9400,3400,9700,200,*,DOWN,POLY ++S 2600,9400,2600,9700,200,*,DOWN,POLY ++S 1800,9400,1800,9700,200,*,DOWN,POLY ++S 5400,9400,5400,9700,200,*,DOWN,POLY ++S 6200,9400,6200,9700,200,*,DOWN,POLY ++S 7000,9400,7000,9700,200,*,DOWN,POLY ++S 7800,9400,7800,9700,200,*,DOWN,POLY ++S 2900,3000,7000,3000,400,*,RIGHT,ALU1 ++S 800,700,800,2100,400,*,DOWN,ALU1 ++S 700,1500,700,2200,600,*,UP,NDIF ++S 5600,700,5600,2100,400,*,DOWN,ALU1 ++S 5700,1500,5700,2200,600,*,UP,NDIF ++S 2000,7000,5000,7000,400,*,LEFT,ALU1 ++S 2000,7100,5000,7100,400,*,LEFT,ALU1 ++S 4900,5900,4900,7000,600,*,UP,ALU1 ++S 2000,8000,2000,8000,400,d,LEFT,CALU1 ++S 3000,8000,3000,8000,400,d,LEFT,CALU1 ++S 4000,8000,4000,8000,400,d,LEFT,CALU1 ++S 5000,8000,5000,8000,400,d,LEFT,CALU1 ++S 6000,8000,6000,8000,400,d,LEFT,CALU1 ++S 8000,5000,8000,5000,400,d,LEFT,CALU1 ++S 7000,5000,7000,8000,400,d,DOWN,CALU1 ++S 1400,2400,1400,5100,200,*,DOWN,POLY ++S 1400,5100,1800,5100,200,*,LEFT,POLY ++S 3000,7000,3000,7000,400,z,LEFT,CALU1 ++S 4000,7000,4000,7000,400,z,LEFT,CALU1 ++S 4000,2000,4000,2000,400,z,LEFT,CALU1 ++S 3000,2000,3000,2000,400,z,LEFT,CALU1 ++S 5000,6000,5000,7000,400,z,DOWN,CALU1 ++S 6000,3000,6000,3000,400,b,LEFT,CALU1 ++S 5000,3000,5000,3000,400,b,LEFT,CALU1 ++S 4000,3000,4000,3000,400,b,LEFT,CALU1 ++S 3000,3000,3000,3000,400,b,LEFT,CALU1 ++S 4000,4000,4000,4000,400,c,LEFT,CALU1 ++S 5000,4000,5000,4000,400,c,LEFT,CALU1 ++S 4000,5000,4000,5000,400,a,LEFT,CALU1 ++S 5000,5000,5000,5000,400,a,LEFT,CALU1 ++S 3000,4900,5100,4900,400,*,RIGHT,ALU1 ++S 3000,5000,5100,5000,400,*,RIGHT,ALU1 ++V 8000,700,CONT_BODY_P,* ++V 7000,700,CONT_BODY_P,* ++V 8400,7000,CONT_DIF_P,* ++V 8400,8000,CONT_DIF_P,* ++V 4800,6000,CONT_DIF_P,* ++V 4800,4900,CONT_POLY,* ++V 6000,4000,CONT_POLY,* ++V 4400,2000,CONT_DIF_N,* ++V 4000,3900,CONT_POLY,* ++V 3200,1000,CONT_DIF_N,* ++V 3000,3000,CONT_POLY,* ++V 2000,2000,CONT_DIF_N,* ++V 4800,7000,CONT_DIF_P,* ++V 8400,9000,CONT_DIF_P,* ++V 1200,9000,CONT_DIF_P,* ++V 1000,4900,CONT_POLY,* ++V 8000,4900,CONT_POLY,* ++V 6800,3000,CONT_POLY,* ++V 800,2000,CONT_DIF_N,* ++V 5600,2000,CONT_DIF_N,* ++EOF +diff --git a/alliance/src/cells/src/msxlib/nr4_x1.vbe b/alliance/src/cells/src/msxlib/nr4_x1.vbe +new file mode 100644 +index 0000000..126605b +--- /dev/null ++++ b/alliance/src/cells/src/msxlib/nr4_x1.vbe +@@ -0,0 +1,44 @@ ++ENTITY nr4_x1 IS ++GENERIC ( ++ CONSTANT area : NATURAL := 9000; ++ CONSTANT cin_c : NATURAL := 9; ++ CONSTANT cin_d : NATURAL := 11; ++ CONSTANT cin_b : NATURAL := 10; ++ CONSTANT cin_a : NATURAL := 9; ++ CONSTANT rdown_c_z : NATURAL := 2100; ++ CONSTANT rdown_d_z : NATURAL := 2180; ++ CONSTANT rdown_b_z : NATURAL := 2130; ++ CONSTANT rdown_a_z : NATURAL := 2100; ++ CONSTANT rup_c_z : NATURAL := 2990; ++ CONSTANT rup_d_z : NATURAL := 3000; ++ CONSTANT rup_b_z : NATURAL := 2990; ++ CONSTANT rup_a_z : NATURAL := 2990; ++ CONSTANT tphl_d_z : NATURAL := 102; ++ CONSTANT tplh_a_z : NATURAL := 46; ++ CONSTANT tplh_d_z : NATURAL := 112; ++ CONSTANT tphl_c_z : NATURAL := 78; ++ CONSTANT tplh_b_z : NATURAL := 102; ++ CONSTANT tplh_c_z : NATURAL := 80; ++ CONSTANT tphl_b_z : NATURAL := 92; ++ CONSTANT tphl_a_z : NATURAL := 57; ++ CONSTANT transistors : NATURAL := 12 ++); ++PORT ( ++ c : in BIT; ++ d : in BIT; ++ b : in BIT; ++ a : in BIT; ++ z : out BIT; ++ vdd : in BIT; ++ vss : in BIT ++); ++END nr4_x1; ++ ++ARCHITECTURE behaviour_data_flow OF nr4_x1 IS ++ ++BEGIN ++ ASSERT ((vdd and not (vss)) = '1') ++ REPORT "power supply is missing on nr4_x1" ++ SEVERITY WARNING; ++ z <= not ((((c or d) or b) or a)) after 1100 ps; ++END; +diff --git a/alliance/src/cells/src/msxlib/oai21_x05.ap b/alliance/src/cells/src/msxlib/oai21_x05.ap +new file mode 100644 +index 0000000..62ae640 +--- /dev/null ++++ b/alliance/src/cells/src/msxlib/oai21_x05.ap +@@ -0,0 +1,96 @@ ++V ALLIANCE : 6 ++H oai21_x05,P, 9/ 8/2014,100 ++A 0,0,5000,10000 ++R 1000,2000,ref_ref,z_20 ++R 3000,7000,ref_ref,a1_70 ++R 3000,4000,ref_ref,a2_40 ++R 2000,3000,ref_ref,b_30 ++R 3000,3000,ref_ref,b_30 ++R 2000,4000,ref_ref,b_40 ++R 4000,5000,ref_ref,a1_50 ++R 3000,5000,ref_ref,a2_50 ++R 1000,3000,ref_ref,z_30 ++R 2000,5000,ref_ref,b_50 ++R 1000,4000,ref_ref,z_40 ++R 1000,5000,ref_ref,z_50 ++R 1000,6000,ref_ref,z_60 ++R 4000,4000,ref_ref,a2_40 ++R 3000,6000,ref_ref,a2_60 ++R 4000,6000,ref_ref,a1_60 ++R 4000,7000,ref_ref,a1_70 ++R 2000,6000,ref_ref,z_60 ++R 2000,7000,ref_ref,z_70 ++S 1100,9300,1900,9300,600,*,RIGHT,NTIE ++S 1100,700,1900,700,600,*,RIGHT,PTIE ++S 4000,7900,4000,9300,400,*,UP,ALU1 ++S 800,6900,800,9300,400,*,UP,ALU1 ++S 3800,1300,3800,1700,200,*,DOWN,POLY ++S 2600,1300,2600,1700,200,*,DOWN,POLY ++S 1400,1300,1400,1700,200,*,DOWN,POLY ++S 3800,2700,3800,4800,200,*,UP,POLY ++S 2900,7100,4000,7100,400,*,LEFT,ALU1 ++S 2900,7000,4000,7000,400,*,LEFT,ALU1 ++S 2000,3000,2000,5000,400,b,DOWN,CALU1 ++S 2000,2900,2000,5100,400,*,DOWN,ALU1 ++S 2000,2900,3100,2900,400,*,RIGHT,ALU1 ++S 2000,3000,3100,3000,400,*,RIGHT,ALU1 ++S 0,9400,5000,9400,1200,vdd,RIGHT,CALU1 ++S 0,5000,5000,5000,10000,oai21_x05,LEFT,TALU8 ++S 0,2200,5000,2200,5200,*,LEFT,PWELL ++S 0,7600,5000,7600,5600,*,LEFT,NWELL ++S 0,600,5000,600,1200,vss,RIGHT,CALU1 ++S 1900,2000,4500,2000,400,*,RIGHT,ALU1 ++S 700,2000,1000,2000,600,*,RIGHT,ALU1 ++S 1800,1900,1800,2500,400,*,DOWN,NDIF ++S 1400,1700,1400,2700,200,6,UP,NTRANS ++S 1000,1900,1000,2500,400,*,UP,NDIF ++S 2000,1900,2000,2500,1000,*,DOWN,NDIF ++S 2600,1700,2600,2700,200,5,UP,NTRANS ++S 4200,1900,4200,2500,400,*,UP,NDIF ++S 3800,1700,3800,2700,200,4,UP,NTRANS ++S 3200,900,3200,2500,600,*,UP,NDIF ++S 3000,4000,4100,4000,400,*,RIGHT,ALU1 ++S 4000,5000,4000,7000,400,a1,UP,CALU1 ++S 3000,3900,4100,3900,400,*,RIGHT,ALU1 ++S 3000,4000,3000,6000,400,a2,DOWN,CALU1 ++S 3000,4000,3000,6100,400,*,UP,ALU1 ++S 1000,2000,1000,6000,400,z,DOWN,CALU1 ++S 1000,2000,1000,6000,400,*,DOWN,ALU1 ++S 1400,7300,1400,7700,200,*,DOWN,POLY ++S 1400,6100,1400,7300,200,3,DOWN,PTRANS ++S 2000,6300,2000,7100,600,*,UP,PDIF ++S 800,6300,800,7100,600,*,DOWN,PDIF ++S 1000,6000,2000,6000,600,*,RIGHT,ALU1 ++S 2000,6000,2000,7100,400,*,UP,ALU1 ++S 3400,6100,3400,8400,200,1,DOWN,PTRANS ++S 3000,6300,3000,8200,400,n1,UP,PDIF ++S 2600,6100,2600,8400,200,2,DOWN,PTRANS ++S 2200,6300,2200,8200,400,*,DOWN,PDIF ++S 4000,6300,4000,8200,600,*,DOWN,PDIF ++S 3400,8400,3400,8800,200,*,DOWN,POLY ++S 2600,8400,2600,8800,200,*,DOWN,POLY ++S 1400,2700,1400,6100,200,*,UP,POLY ++S 2600,2700,2600,6100,200,*,UP,POLY ++S 2000,6000,2000,7000,400,z,UP,CALU1 ++S 3400,5200,3800,5200,200,*,RIGHT,POLY ++S 3400,5200,3400,6100,200,*,DOWN,POLY ++S 4000,4900,4000,7000,400,*,UP,ALU1 ++S 1800,5000,2000,5000,600,*,RIGHT,ALU1 ++S 3000,3000,3000,3000,400,b,LEFT,CALU1 ++S 4000,4000,4000,4000,400,a2,LEFT,CALU1 ++S 3000,7000,3000,7000,400,a1,LEFT,CALU1 ++V 2000,9300,CONT_BODY_N,* ++V 1000,9300,CONT_BODY_N,* ++V 2000,700,CONT_BODY_P,* ++V 1000,700,CONT_BODY_P,* ++V 4000,8000,CONT_DIF_P,* ++V 800,7000,CONT_DIF_P,* ++V 3200,1000,CONT_DIF_N,* ++V 4400,2000,CONT_DIF_N,n2 ++V 2000,2000,CONT_DIF_N,n2 ++V 800,2000,CONT_DIF_N,* ++V 2000,7000,CONT_DIF_P,* ++V 4000,5000,CONT_POLY,* ++V 3000,4000,CONT_POLY,* ++V 1800,5000,CONT_POLY,* ++EOF +diff --git a/alliance/src/cells/src/msxlib/oai21_x05.vbe b/alliance/src/cells/src/msxlib/oai21_x05.vbe +new file mode 100644 +index 0000000..ec2c4e0 +--- /dev/null ++++ b/alliance/src/cells/src/msxlib/oai21_x05.vbe +@@ -0,0 +1,38 @@ ++ENTITY oai21_x05 IS ++GENERIC ( ++ CONSTANT area : NATURAL := 5000; ++ CONSTANT cin_a1 : NATURAL := 4; ++ CONSTANT cin_a2 : NATURAL := 4; ++ CONSTANT cin_b : NATURAL := 3; ++ CONSTANT rdown_a1_z : NATURAL := 3700; ++ CONSTANT rdown_a2_z : NATURAL := 3700; ++ CONSTANT rdown_b_z : NATURAL := 3420; ++ CONSTANT rup_a1_z : NATURAL := 5060; ++ CONSTANT rup_a2_z : NATURAL := 5060; ++ CONSTANT rup_b_z : NATURAL := 4960; ++ CONSTANT tphl_b_z : NATURAL := 42; ++ CONSTANT tphl_a2_z : NATURAL := 47; ++ CONSTANT tplh_a1_z : NATURAL := 72; ++ CONSTANT tplh_b_z : NATURAL := 50; ++ CONSTANT tplh_a2_z : NATURAL := 62; ++ CONSTANT tphl_a1_z : NATURAL := 57; ++ CONSTANT transistors : NATURAL := 6 ++); ++PORT ( ++ a1 : in BIT; ++ a2 : in BIT; ++ b : in BIT; ++ z : out BIT; ++ vdd : in BIT; ++ vss : in BIT ++); ++END oai21_x05; ++ ++ARCHITECTURE behaviour_data_flow OF oai21_x05 IS ++ ++BEGIN ++ ASSERT ((vdd and not (vss)) = '1') ++ REPORT "power supply is missing on oai21_x05" ++ SEVERITY WARNING; ++ z <= not (((a1 or a2) and b)) after 900 ps; ++END; +diff --git a/alliance/src/cells/src/msxlib/oai21_x1.ap b/alliance/src/cells/src/msxlib/oai21_x1.ap +new file mode 100644 +index 0000000..4cd76d4 +--- /dev/null ++++ b/alliance/src/cells/src/msxlib/oai21_x1.ap +@@ -0,0 +1,100 @@ ++V ALLIANCE : 6 ++H oai21_x1,P, 9/ 8/2014,100 ++A 0,0,5000,10000 ++R 1000,2000,ref_ref,z_20 ++R 4000,4000,ref_ref,a2_40 ++R 3000,4000,ref_ref,a2_40 ++R 4000,6000,ref_ref,a1_60 ++R 4000,7000,ref_ref,a1_70 ++R 3000,7000,ref_ref,a1_70 ++R 2000,6000,ref_ref,z_60 ++R 2000,7000,ref_ref,z_70 ++R 2000,3000,ref_ref,b_30 ++R 3000,3000,ref_ref,b_30 ++R 2000,4000,ref_ref,b_40 ++R 3000,6000,ref_ref,a2_60 ++R 4000,5000,ref_ref,a1_50 ++R 3000,5000,ref_ref,a2_50 ++R 1000,3000,ref_ref,z_30 ++R 2000,5000,ref_ref,b_50 ++R 1000,4000,ref_ref,z_40 ++R 1000,5000,ref_ref,z_50 ++R 1000,6000,ref_ref,z_60 ++S 1100,700,1900,700,600,*,RIGHT,PTIE ++S 1800,4000,2000,4000,600,*,RIGHT,ALU1 ++S 3800,3300,3800,4800,200,*,UP,POLY ++S 2600,3300,2600,5500,200,*,UP,POLY ++S 1400,3300,1400,5500,200,*,UP,POLY ++S 1000,1800,1000,3100,400,*,UP,NDIF ++S 800,2300,800,2900,600,*,UP,NDIF ++S 3200,900,3200,3100,600,*,UP,NDIF ++S 3800,1600,3800,3300,200,4,UP,NTRANS ++S 4200,1800,4200,3100,400,*,UP,NDIF ++S 1400,1600,1400,3300,200,6,UP,NTRANS ++S 2600,1600,2600,3300,200,5,UP,NTRANS ++S 2000,1800,2000,3100,600,*,DOWN,NDIF ++S 1400,1200,1400,1600,200,*,UP,POLY ++S 2600,1200,2600,1600,200,*,UP,POLY ++S 3800,1200,3800,1600,200,*,UP,POLY ++S 4400,2300,4400,2900,600,*,UP,NDIF ++S 4400,2000,4400,3100,400,*,UP,ALU1 ++S 1900,2000,4400,2000,400,*,RIGHT,ALU1 ++S 3000,3000,3000,3000,400,b,LEFT,CALU1 ++S 4000,4000,4000,4000,400,a2,LEFT,CALU1 ++S 3000,7000,3000,7000,400,a1,LEFT,CALU1 ++S 1000,2000,1000,6000,400,*,DOWN,ALU1 ++S 1000,2000,1000,6000,400,z,DOWN,CALU1 ++S 3400,5100,3900,5100,200,*,RIGHT,POLY ++S 3400,5100,3400,5500,200,*,DOWN,POLY ++S 3000,4000,3000,6100,400,*,UP,ALU1 ++S 3000,3900,4100,3900,400,*,RIGHT,ALU1 ++S 3000,4000,4100,4000,400,*,RIGHT,ALU1 ++S 3000,4000,3000,6000,400,a2,DOWN,CALU1 ++S 2900,7100,4000,7100,400,*,RIGHT,ALU1 ++S 4000,4800,4000,7000,400,*,UP,ALU1 ++S 4000,5000,4000,7000,400,a1,UP,CALU1 ++S 2900,7000,4000,7000,400,*,RIGHT,ALU1 ++S 800,5700,800,7300,600,*,DOWN,PDIF ++S 800,6900,800,9300,400,*,UP,ALU1 ++S 1000,6000,2000,6000,600,*,RIGHT,ALU1 ++S 2000,6000,2000,7100,400,*,UP,ALU1 ++S 2000,6000,2000,7000,400,z,UP,CALU1 ++S 1400,7500,1400,7900,200,*,DOWN,POLY ++S 4000,7900,4000,9300,400,*,UP,ALU1 ++S 2000,5700,2000,7300,1000,*,UP,PDIF ++S 1400,5500,1400,7500,200,3,DOWN,PTRANS ++S 2000,2900,3100,2900,400,*,RIGHT,ALU1 ++S 2000,3000,2000,5100,400,*,DOWN,ALU1 ++S 2000,3000,3100,3000,400,*,RIGHT,ALU1 ++S 2000,3000,2000,5000,400,b,DOWN,CALU1 ++S 0,9400,5000,9400,1200,vdd,RIGHT,CALU1 ++S 0,5000,5000,5000,10000,oai21_x1,LEFT,TALU8 ++S 0,2200,5000,2200,5200,*,LEFT,PWELL ++S 0,7600,5000,7600,5600,*,LEFT,NWELL ++S 0,600,5000,600,1200,vss,RIGHT,CALU1 ++S 3100,5700,3100,9200,400,n1,UP,PDIF ++S 3400,5500,3400,9400,200,1,DOWN,PTRANS ++S 2600,5500,2600,9400,200,2,DOWN,PTRANS ++S 2200,5700,2200,9200,400,*,DOWN,PDIF ++S 4000,5700,4000,9200,600,*,DOWN,PDIF ++S 3400,9400,3400,9700,200,*,DOWN,POLY ++S 2600,9400,2600,9700,200,*,DOWN,POLY ++S 900,1900,900,3100,600,*,DOWN,ALU1 ++V 1000,9300,CONT_BODY_N,* ++V 2000,700,CONT_BODY_P,* ++V 1000,700,CONT_BODY_P,* ++V 1800,4000,CONT_POLY,* ++V 3000,4000,CONT_POLY,* ++V 800,2200,CONT_DIF_N,* ++V 800,3000,CONT_DIF_N,* ++V 2000,2000,CONT_DIF_N,n2 ++V 4400,2200,CONT_DIF_N,n2 ++V 4400,3000,CONT_DIF_N,n2 ++V 800,7000,CONT_DIF_P,* ++V 2000,6800,CONT_DIF_P,* ++V 2000,6000,CONT_DIF_P,* ++V 4000,9000,CONT_DIF_P,* ++V 4000,8000,CONT_DIF_P,* ++V 3200,1000,CONT_DIF_N,* ++V 4000,4900,CONT_POLY,* ++EOF +diff --git a/alliance/src/cells/src/msxlib/oai21_x1.vbe b/alliance/src/cells/src/msxlib/oai21_x1.vbe +new file mode 100644 +index 0000000..5ab3443 +--- /dev/null ++++ b/alliance/src/cells/src/msxlib/oai21_x1.vbe +@@ -0,0 +1,38 @@ ++ENTITY oai21_x1 IS ++GENERIC ( ++ CONSTANT area : NATURAL := 5000; ++ CONSTANT cin_a1 : NATURAL := 6; ++ CONSTANT cin_a2 : NATURAL := 6; ++ CONSTANT cin_b : NATURAL := 4; ++ CONSTANT rdown_a1_z : NATURAL := 2170; ++ CONSTANT rdown_a2_z : NATURAL := 2170; ++ CONSTANT rdown_b_z : NATURAL := 2010; ++ CONSTANT rup_a1_z : NATURAL := 2980; ++ CONSTANT rup_a2_z : NATURAL := 2980; ++ CONSTANT rup_b_z : NATURAL := 2970; ++ CONSTANT tphl_b_z : NATURAL := 41; ++ CONSTANT tphl_a2_z : NATURAL := 45; ++ CONSTANT tplh_a1_z : NATURAL := 69; ++ CONSTANT tplh_b_z : NATURAL := 49; ++ CONSTANT tplh_a2_z : NATURAL := 60; ++ CONSTANT tphl_a1_z : NATURAL := 55; ++ CONSTANT transistors : NATURAL := 6 ++); ++PORT ( ++ a1 : in BIT; ++ a2 : in BIT; ++ b : in BIT; ++ z : out BIT; ++ vdd : in BIT; ++ vss : in BIT ++); ++END oai21_x1; ++ ++ARCHITECTURE behaviour_data_flow OF oai21_x1 IS ++ ++BEGIN ++ ASSERT ((vdd and not (vss)) = '1') ++ REPORT "power supply is missing on oai21_x1" ++ SEVERITY WARNING; ++ z <= not (((a1 or a2) and b)) after 900 ps; ++END; +diff --git a/alliance/src/cells/src/msxlib/oai21_x2.ap b/alliance/src/cells/src/msxlib/oai21_x2.ap +new file mode 100644 +index 0000000..3fbf730 +--- /dev/null ++++ b/alliance/src/cells/src/msxlib/oai21_x2.ap +@@ -0,0 +1,123 @@ ++V ALLIANCE : 6 ++H oai21_x2,P, 9/ 8/2014,100 ++A 0,0,7000,10000 ++R 6000,4000,ref_ref,a1_40 ++R 6000,6000,ref_ref,a1_60 ++R 2000,4000,ref_ref,b_40 ++R 5000,4000,ref_ref,a1_40 ++R 5000,7000,ref_ref,a2_70 ++R 4000,8000,ref_ref,z_80 ++R 4000,7000,ref_ref,z_70 ++R 3000,7000,ref_ref,z_70 ++R 2000,7000,ref_ref,z_70 ++R 5000,6000,ref_ref,a2_60 ++R 6000,5000,ref_ref,a1_50 ++R 4000,5000,ref_ref,a2_50 ++R 4000,4000,ref_ref,a1_40 ++R 1000,7000,ref_ref,z_70 ++R 1000,6000,ref_ref,z_60 ++R 1000,5000,ref_ref,z_50 ++R 1000,4000,ref_ref,z_40 ++R 2000,5000,ref_ref,b_50 ++R 1000,3000,ref_ref,z_30 ++R 4000,6000,ref_ref,a2_60 ++R 3000,4000,ref_ref,a1_40 ++R 2000,6000,ref_ref,b_60 ++R 3000,6000,ref_ref,b_60 ++S 5100,700,5900,700,600,*,RIGHT,PTIE ++S 5600,4800,5600,5600,200,*,DOWN,POLY ++S 5000,4000,5000,4000,400,a1,LEFT,CALU1 ++S 6100,4000,6100,6100,400,*,UP,ALU1 ++S 2900,4000,6000,4000,400,*,RIGHT,ALU1 ++S 6000,4000,6000,6000,400,a1,UP,CALU1 ++S 6000,4000,6000,6100,400,*,UP,ALU1 ++S 4000,4000,4000,4000,400,a1,LEFT,CALU1 ++S 3000,4000,3000,4000,400,a1,LEFT,CALU1 ++S 3000,6000,3000,6000,400,b,LEFT,CALU1 ++S 4000,7000,4000,8000,400,z,UP,CALU1 ++S 3000,7000,3000,7000,400,z,LEFT,CALU1 ++S 2000,7000,2000,7000,400,z,LEFT,CALU1 ++S 5600,9400,5600,9700,200,*,DOWN,POLY ++S 4800,9400,4800,9700,200,*,DOWN,POLY ++S 3600,9400,3600,9700,200,*,DOWN,POLY ++S 2800,9400,2800,9700,200,*,DOWN,POLY ++S 1600,9400,1600,9700,200,*,DOWN,POLY ++S 1600,300,1600,700,200,*,UP,POLY ++S 1600,5600,1600,9400,200,5,DOWN,PTRANS ++S 1200,5800,1200,9200,400,*,UP,PDIF ++S 2200,5800,2200,9200,600,*,DOWN,PDIF ++S 0,600,7000,600,1200,vss,RIGHT,CALU1 ++S 0,5000,7000,5000,10000,oai21_x2,LEFT,TALU8 ++S 0,2200,7000,2200,5200,*,LEFT,PWELL ++S 0,7600,7000,7600,5600,*,LEFT,NWELL ++S 0,9400,7000,9400,1200,vdd,RIGHT,CALU1 ++S 2200,7900,2200,9300,400,*,DOWN,ALU1 ++S 6200,7900,6200,9300,400,*,DOWN,ALU1 ++S 1000,6000,1000,6800,600,*,UP,PDIF ++S 1000,7000,4000,7000,600,*,RIGHT,ALU1 ++S 4100,6900,4100,8100,600,*,UP,ALU1 ++S 4000,6000,5000,6000,600,*,RIGHT,ALU1 ++S 4000,5000,4000,6000,400,a2,DOWN,CALU1 ++S 4000,4900,4000,6000,400,*,UP,ALU1 ++S 5000,6000,5000,7000,400,a2,UP,CALU1 ++S 5000,6000,5000,7100,400,*,UP,ALU1 ++S 1000,3000,1000,7000,400,z,DOWN,CALU1 ++S 3200,5800,3200,9200,600,n2,DOWN,PDIF ++S 3600,5600,3600,9400,200,4,DOWN,PTRANS ++S 2800,5600,2800,9400,200,3,DOWN,PTRANS ++S 4800,5600,4800,9400,200,2,DOWN,PTRANS ++S 4200,5800,4200,9200,1000,*,UP,PDIF ++S 6200,5800,6200,9200,800,*,DOWN,PDIF ++S 5600,5600,5600,9400,200,1,DOWN,PTRANS ++S 5200,5800,5200,9200,600,n1,UP,PDIF ++S 3600,5200,4800,5200,200,*,RIGHT,POLY ++S 2800,300,2800,700,200,*,UP,POLY ++S 1200,800,1200,3600,400,*,UP,NDIF ++S 1000,2600,1000,3400,600,*,UP,NDIF ++S 2200,800,2200,3600,600,*,UP,NDIF ++S 3400,800,3400,3600,600,*,UP,NDIF ++S 5200,2200,5200,3800,200,6,UP,NTRANS ++S 4600,2400,4600,3600,600,*,UP,NDIF ++S 4000,1800,4000,2200,200,*,UP,POLY ++S 5200,1800,5200,2200,200,*,UP,POLY ++S 5800,700,5800,3100,400,*,DOWN,ALU1 ++S 5900,2400,5900,3600,600,*,UP,NDIF ++S 2000,6000,3100,6000,400,*,RIGHT,ALU1 ++S 2000,6100,3100,6100,400,*,RIGHT,ALU1 ++S 2000,4000,2000,6000,400,b,DOWN,CALU1 ++S 2000,3900,2000,6000,400,*,DOWN,ALU1 ++S 3000,4000,3000,4500,600,*,UP,ALU1 ++S 2200,3000,4700,3000,400,*,RIGHT,ALU1 ++S 2200,2000,2200,3000,600,*,DOWN,ALU1 ++S 4000,4200,5200,4200,200,*,LEFT,POLY ++S 3400,700,3400,2100,400,*,UP,ALU1 ++S 4100,4200,4100,4800,400,*,DOWN,POLY ++S 4000,2200,4000,3800,200,7,UP,NTRANS ++S 2800,600,2800,3800,200,8,UP,NTRANS ++S 1600,600,1600,3800,200,9,UP,NTRANS ++S 1600,3800,1600,5300,200,*,UP,POLY ++S 2800,4400,2800,5600,200,*,UP,POLY ++S 1000,2600,1000,7000,400,*,DOWN,ALU1 ++V 6000,700,CONT_BODY_P,* ++V 5000,700,CONT_BODY_P,* ++V 6000,5000,CONT_POLY,* ++V 4200,8000,CONT_DIF_P,* ++V 2200,2000,CONT_DIF_N,n3 ++V 2200,9000,CONT_DIF_P,* ++V 6200,9000,CONT_DIF_P,* ++V 2200,8000,CONT_DIF_P,* ++V 6200,8000,CONT_DIF_P,* ++V 1000,5900,CONT_DIF_P,* ++V 1000,6700,CONT_DIF_P,* ++V 4200,7000,CONT_DIF_P,* ++V 4000,5000,CONT_POLY,* ++V 3400,1000,CONT_DIF_N,* ++V 1000,3500,CONT_DIF_N,* ++V 1000,2700,CONT_DIF_N,* ++V 4600,3000,CONT_DIF_N,n3 ++V 5800,3000,CONT_DIF_N,* ++V 3000,4400,CONT_POLY,* ++V 2000,5000,CONT_POLY,* ++V 2200,3000,CONT_DIF_N,n3 ++V 3400,2000,CONT_DIF_N,* ++EOF +diff --git a/alliance/src/cells/src/msxlib/oai21_x2.vbe b/alliance/src/cells/src/msxlib/oai21_x2.vbe +new file mode 100644 +index 0000000..a55d6ec +--- /dev/null ++++ b/alliance/src/cells/src/msxlib/oai21_x2.vbe +@@ -0,0 +1,38 @@ ++ENTITY oai21_x2 IS ++GENERIC ( ++ CONSTANT area : NATURAL := 7000; ++ CONSTANT cin_a1 : NATURAL := 12; ++ CONSTANT cin_a2 : NATURAL := 11; ++ CONSTANT cin_b : NATURAL := 8; ++ CONSTANT rdown_a1_z : NATURAL := 1150; ++ CONSTANT rdown_a2_z : NATURAL := 1150; ++ CONSTANT rdown_b_z : NATURAL := 1060; ++ CONSTANT rup_a1_z : NATURAL := 1530; ++ CONSTANT rup_a2_z : NATURAL := 1530; ++ CONSTANT rup_b_z : NATURAL := 1560; ++ CONSTANT tphl_b_z : NATURAL := 41; ++ CONSTANT tphl_a2_z : NATURAL := 44; ++ CONSTANT tplh_a1_z : NATURAL := 66; ++ CONSTANT tplh_b_z : NATURAL := 48; ++ CONSTANT tplh_a2_z : NATURAL := 57; ++ CONSTANT tphl_a1_z : NATURAL := 54; ++ CONSTANT transistors : NATURAL := 8 ++); ++PORT ( ++ a1 : in BIT; ++ a2 : in BIT; ++ b : in BIT; ++ z : out BIT; ++ vdd : in BIT; ++ vss : in BIT ++); ++END oai21_x2; ++ ++ARCHITECTURE behaviour_data_flow OF oai21_x2 IS ++ ++BEGIN ++ ASSERT ((vdd and not (vss)) = '1') ++ REPORT "power supply is missing on oai21_x2" ++ SEVERITY WARNING; ++ z <= not (((a1 or a2) and b)) after 900 ps; ++END; +diff --git a/alliance/src/cells/src/msxlib/oai22_x05.ap b/alliance/src/cells/src/msxlib/oai22_x05.ap +new file mode 100644 +index 0000000..81b196c +--- /dev/null ++++ b/alliance/src/cells/src/msxlib/oai22_x05.ap +@@ -0,0 +1,124 @@ ++V ALLIANCE : 6 ++H oai22_x05,P, 9/ 8/2014,100 ++A 0,0,6000,10000 ++R 5000,4000,ref_ref,a2_40 ++R 2000,4000,ref_ref,z_40 ++R 3000,4000,ref_ref,b2_40 ++R 4000,4000,ref_ref,b2_40 ++R 2000,5000,ref_ref,b1_50 ++R 2000,6000,ref_ref,b1_60 ++R 3000,7000,ref_ref,b1_70 ++R 3000,5000,ref_ref,b2_50 ++R 4000,5000,ref_ref,a2_50 ++R 5000,6000,ref_ref,a1_60 ++R 4000,7000,ref_ref,a1_70 ++R 1000,4000,ref_ref,z_40 ++R 1000,5000,ref_ref,z_50 ++R 1000,6000,ref_ref,z_60 ++R 1000,7000,ref_ref,z_70 ++R 3000,8000,ref_ref,z_80 ++R 2000,8000,ref_ref,z_80 ++R 2000,3000,ref_ref,z_30 ++R 5000,7000,ref_ref,a1_70 ++R 4000,8000,ref_ref,a1_80 ++R 4000,6000,ref_ref,a2_60 ++R 5000,5000,ref_ref,a2_50 ++R 1000,8000,ref_ref,z_80 ++R 2000,7000,ref_ref,b1_70 ++R 3000,6000,ref_ref,b2_60 ++S 4100,9300,4900,9300,600,*,RIGHT,NTIE ++S 1100,700,1900,700,600,*,RIGHT,PTIE ++S 5000,4000,5000,5000,400,a2,DOWN,CALU1 ++S 3000,4000,4000,4000,600,*,RIGHT,ALU1 ++S 1000,4000,2000,4000,600,*,RIGHT,ALU1 ++S 0,9400,6000,9400,1200,vdd,RIGHT,CALU1 ++S 0,600,6000,600,1200,vss,RIGHT,CALU1 ++S 0,5000,6000,5000,10000,oai22_x05,LEFT,TALU8 ++S 0,2200,6000,2200,5200,*,LEFT,PWELL ++S 0,7600,6000,7600,5600,*,LEFT,NWELL ++S 5200,7900,5200,9300,400,*,UP,ALU1 ++S 4600,6500,4600,8500,200,1,DOWN,PTRANS ++S 3800,6500,3800,8500,200,2,DOWN,PTRANS ++S 4200,6700,4200,8300,600,n1,UP,PDIF ++S 3200,6700,3200,8300,1000,*,UP,PDIF ++S 2600,6500,2600,8500,200,4,DOWN,PTRANS ++S 1800,6500,1800,8500,200,3,DOWN,PTRANS ++S 2200,6700,2200,8300,600,n2,UP,PDIF ++S 4000,7000,4000,8000,400,a1,UP,CALU1 ++S 4000,7000,4000,8100,400,*,UP,ALU1 ++S 4000,7000,5000,7000,600,*,RIGHT,ALU1 ++S 5000,6000,5000,7000,400,a1,UP,CALU1 ++S 5000,5800,5000,7000,400,*,UP,ALU1 ++S 5000,3900,5000,5000,400,*,DOWN,ALU1 ++S 4000,5000,5000,5000,400,*,RIGHT,ALU1 ++S 5100,3900,5100,5000,400,*,DOWN,ALU1 ++S 4000,5000,4000,6000,400,a2,UP,CALU1 ++S 4000,5000,4000,6100,400,*,UP,ALU1 ++S 4000,4900,5000,4900,400,*,RIGHT,ALU1 ++S 4600,6000,4600,6500,200,*,DOWN,POLY ++S 5200,2900,5200,3400,400,*,DOWN,NDIF ++S 4800,2700,4800,3600,200,5,UP,NTRANS ++S 3000,2900,3000,3400,1000,*,UP,NDIF ++S 3600,2700,3600,3600,200,6,UP,NTRANS ++S 1800,2900,1800,3400,1000,*,UP,NDIF ++S 2400,2700,2400,3600,200,8,UP,NTRANS ++S 1200,2700,1200,3600,200,7,UP,NTRANS ++S 800,2900,800,3400,400,*,DOWN,NDIF ++S 1800,5300,1800,6500,200,*,DOWN,POLY ++S 4800,3600,4800,5600,200,*,UP,POLY ++S 3800,4000,3800,6500,200,*,DOWN,POLY ++S 3600,3600,3600,4100,200,*,UP,POLY ++S 2400,3600,2400,4000,200,*,UP,POLY ++S 2400,4000,2800,4000,200,*,RIGHT,POLY ++S 1200,3600,1200,4800,200,*,UP,POLY ++S 1200,4800,1800,4800,200,*,RIGHT,POLY ++S 2600,8500,2600,8900,200,*,DOWN,POLY ++S 2000,3000,2000,4000,400,z,UP,CALU1 ++S 1900,2900,1900,4000,600,*,UP,ALU1 ++S 600,2000,600,3100,400,*,UP,ALU1 ++S 4800,2300,4800,2700,200,*,UP,POLY ++S 3600,2300,3600,2700,200,*,UP,POLY ++S 2400,2300,2400,2700,200,*,UP,POLY ++S 1200,2300,1200,2700,200,*,UP,POLY ++S 1800,8500,1800,8900,200,*,DOWN,POLY ++S 1000,8000,3200,8000,600,*,RIGHT,ALU1 ++S 1000,4000,1000,8000,400,z,DOWN,CALU1 ++S 1000,4400,1000,8000,400,*,DOWN,ALU1 ++S 2000,7000,3000,7000,600,*,RIGHT,ALU1 ++S 2000,4900,2000,7000,400,*,UP,ALU1 ++S 2000,5000,2000,7000,400,b1,UP,CALU1 ++S 2800,4000,2800,6100,200,*,DOWN,POLY ++S 2600,6000,2600,6500,200,*,DOWN,POLY ++S 2000,8000,2000,8000,400,z,LEFT,CALU1 ++S 3000,8000,3000,8000,400,z,LEFT,CALU1 ++S 3000,7000,3000,7000,400,b1,LEFT,CALU1 ++S 3000,4000,3000,6100,400,*,DOWN,ALU1 ++S 3000,4000,3000,6000,400,b2,DOWN,CALU1 ++S 4000,4000,4000,4000,400,b2,LEFT,CALU1 ++S 3800,8500,3800,8800,200,*,DOWN,POLY ++S 4600,8500,4600,8800,200,*,DOWN,POLY ++S 600,2000,2900,2000,400,*,RIGHT,ALU1 ++S 2900,2000,2900,3000,400,*,DOWN,ALU1 ++S 2900,3000,5500,3000,400,*,RIGHT,ALU1 ++S 4200,1800,4200,3400,600,*,UP,NDIF ++S 4200,700,4200,2100,400,*,DOWN,ALU1 ++S 1200,6700,1200,9100,600,*,DOWN,PDIF ++S 1100,6700,1100,9100,600,*,DOWN,PDIF ++S 5300,6700,5300,8300,600,*,DOWN,PDIF ++V 4000,9300,CONT_BODY_N,* ++V 5000,9300,CONT_BODY_N,* ++V 2000,700,CONT_BODY_P,* ++V 1000,700,CONT_BODY_P,* ++V 1800,3000,CONT_DIF_N,* ++V 3200,8000,CONT_DIF_P,* ++V 5200,8000,CONT_DIF_P,* ++V 5000,5900,CONT_POLY,* ++V 4000,5000,CONT_POLY,* ++V 5400,3000,CONT_DIF_N,n3 ++V 3000,3000,CONT_DIF_N,n3 ++V 600,3000,CONT_DIF_N,n3 ++V 3000,5000,CONT_POLY,* ++V 2000,5000,CONT_POLY,* ++V 1200,9000,CONT_DIF_P,* ++V 4200,2000,CONT_DIF_N,* ++EOF +diff --git a/alliance/src/cells/src/msxlib/oai22_x05.vbe b/alliance/src/cells/src/msxlib/oai22_x05.vbe +new file mode 100644 +index 0000000..0dfc79e +--- /dev/null ++++ b/alliance/src/cells/src/msxlib/oai22_x05.vbe +@@ -0,0 +1,44 @@ ++ENTITY oai22_x05 IS ++GENERIC ( ++ CONSTANT area : NATURAL := 6000; ++ CONSTANT cin_b1 : NATURAL := 4; ++ CONSTANT cin_b2 : NATURAL := 4; ++ CONSTANT cin_a1 : NATURAL := 4; ++ CONSTANT cin_a2 : NATURAL := 4; ++ CONSTANT rdown_b1_z : NATURAL := 3810; ++ CONSTANT rdown_b2_z : NATURAL := 3800; ++ CONSTANT rdown_a1_z : NATURAL := 3760; ++ CONSTANT rdown_a2_z : NATURAL := 3760; ++ CONSTANT rup_b1_z : NATURAL := 5850; ++ CONSTANT rup_b2_z : NATURAL := 5830; ++ CONSTANT rup_a1_z : NATURAL := 5840; ++ CONSTANT rup_a2_z : NATURAL := 5840; ++ CONSTANT tphl_a2_z : NATURAL := 58; ++ CONSTANT tphl_b2_z : NATURAL := 49; ++ CONSTANT tplh_b1_z : NATURAL := 68; ++ CONSTANT tphl_a1_z : NATURAL := 67; ++ CONSTANT tplh_b2_z : NATURAL := 57; ++ CONSTANT tphl_b1_z : NATURAL := 59; ++ CONSTANT tplh_a1_z : NATURAL := 87; ++ CONSTANT tplh_a2_z : NATURAL := 77; ++ CONSTANT transistors : NATURAL := 8 ++); ++PORT ( ++ b1 : in BIT; ++ b2 : in BIT; ++ a1 : in BIT; ++ a2 : in BIT; ++ z : out BIT; ++ vdd : in BIT; ++ vss : in BIT ++); ++END oai22_x05; ++ ++ARCHITECTURE behaviour_data_flow OF oai22_x05 IS ++ ++BEGIN ++ ASSERT ((vdd and not (vss)) = '1') ++ REPORT "power supply is missing on oai22_x05" ++ SEVERITY WARNING; ++ z <= not (((b1 or b2) and (a1 or a2))) after 1000 ps; ++END; +diff --git a/alliance/src/cells/src/msxlib/oai22_x1.ap b/alliance/src/cells/src/msxlib/oai22_x1.ap +new file mode 100644 +index 0000000..e80a678 +--- /dev/null ++++ b/alliance/src/cells/src/msxlib/oai22_x1.ap +@@ -0,0 +1,121 @@ ++V ALLIANCE : 6 ++H oai22_x1,P, 9/ 8/2014,100 ++A 0,0,6000,10000 ++R 1000,3000,ref_ref,z_30 ++R 3000,3000,ref_ref,b2_30 ++R 3000,7000,ref_ref,z_70 ++R 2000,7000,ref_ref,z_70 ++R 5000,4000,ref_ref,a2_40 ++R 5000,7000,ref_ref,a1_70 ++R 2000,4000,ref_ref,b1_40 ++R 2000,5000,ref_ref,b1_50 ++R 2000,6000,ref_ref,b1_60 ++R 4000,3000,ref_ref,b2_30 ++R 3000,4000,ref_ref,b2_40 ++R 3000,5000,ref_ref,b2_50 ++R 4000,4000,ref_ref,a2_40 ++R 4000,5000,ref_ref,a2_50 ++R 5000,5000,ref_ref,a1_50 ++R 5000,6000,ref_ref,a1_60 ++R 4000,7000,ref_ref,a1_70 ++R 1000,4000,ref_ref,z_40 ++R 1000,5000,ref_ref,z_50 ++R 1000,6000,ref_ref,z_60 ++R 1000,7000,ref_ref,z_70 ++R 3000,8000,ref_ref,z_80 ++R 2000,3000,ref_ref,z_30 ++R 4000,6000,ref_ref,a2_60 ++R 3000,6000,ref_ref,b1_60 ++S 1100,700,1900,700,600,*,RIGHT,PTIE ++S 1000,2900,2100,2900,400,*,RIGHT,ALU1 ++S 1000,7000,3200,7000,600,*,RIGHT,ALU1 ++S 4000,7000,5000,7000,600,*,RIGHT,ALU1 ++S 1000,3000,2100,3000,400,*,RIGHT,ALU1 ++S 1200,4700,1500,4700,200,*,RIGHT,POLY ++S 1800,4900,2000,4900,600,*,RIGHT,ALU1 ++S 2000,3900,2000,6000,400,*,UP,ALU1 ++S 3000,3000,3000,5100,400,*,DOWN,ALU1 ++S 3000,3000,3000,5000,400,b2,DOWN,CALU1 ++S 3000,2900,4100,2900,400,*,RIGHT,ALU1 ++S 2600,3800,2600,5500,200,*,DOWN,POLY ++S 3600,3400,3600,3900,200,*,UP,POLY ++S 3000,3000,4100,3000,400,*,RIGHT,ALU1 ++S 1200,7900,1200,9300,400,*,UP,ALU1 ++S 3000,7000,3000,8000,400,z,UP,CALU1 ++S 3100,7000,3100,8100,600,*,UP,ALU1 ++S 1000,3000,1000,7000,400,*,DOWN,ALU1 ++S 1000,3000,1000,7000,400,z,DOWN,CALU1 ++S 2000,6100,3100,6100,400,*,RIGHT,ALU1 ++S 2000,4000,2000,6000,400,b1,UP,CALU1 ++S 2000,6000,3100,6000,400,*,RIGHT,ALU1 ++S 3800,4200,3800,5500,200,*,DOWN,POLY ++S 4800,3400,4800,4700,200,*,UP,POLY ++S 5000,4800,5000,7000,400,*,UP,ALU1 ++S 5000,5000,5000,7000,400,a1,UP,CALU1 ++S 5200,7900,5200,9300,400,*,UP,ALU1 ++S 4600,9400,4600,9700,200,*,DOWN,POLY ++S 3800,9400,3800,9700,200,*,DOWN,POLY ++S 2600,9400,2600,9700,200,*,DOWN,POLY ++S 1800,9400,1800,9700,200,*,DOWN,POLY ++S 5300,5700,5300,9200,600,*,DOWN,PDIF ++S 4200,5700,4200,9200,600,n1,UP,PDIF ++S 4600,5500,4600,9400,200,1,DOWN,PTRANS ++S 3800,5500,3800,9400,200,2,DOWN,PTRANS ++S 3200,5700,3200,9200,1000,*,UP,PDIF ++S 2200,5700,2200,9200,600,n2,UP,PDIF ++S 2600,5500,2600,9400,200,4,DOWN,PTRANS ++S 1800,5500,1800,9400,200,3,DOWN,PTRANS ++S 1100,5700,1100,9200,600,*,DOWN,PDIF ++S 2400,1700,2400,3400,200,8,UP,NTRANS ++S 1200,1700,1200,3400,200,7,UP,NTRANS ++S 3600,1700,3600,3400,200,6,UP,NTRANS ++S 4800,1700,4800,3400,200,5,UP,NTRANS ++S 4200,900,4200,3200,600,*,UP,NDIF ++S 5200,1900,5200,3200,400,*,DOWN,NDIF ++S 800,1900,800,3200,400,*,DOWN,NDIF ++S 500,2000,5500,2000,400,*,RIGHT,ALU1 ++S 0,9400,6000,9400,1200,vdd,RIGHT,CALU1 ++S 0,600,6000,600,1200,vss,RIGHT,CALU1 ++S 0,5000,6000,5000,10000,oai22_x1,LEFT,TALU8 ++S 0,2200,6000,2200,5200,*,LEFT,PWELL ++S 0,7600,6000,7600,5600,*,LEFT,NWELL ++S 1200,1300,1200,1700,200,*,UP,POLY ++S 2400,1300,2400,1700,200,*,UP,POLY ++S 3600,1300,3600,1700,200,*,UP,POLY ++S 4800,1300,4800,1700,200,*,UP,POLY ++S 1800,1900,1800,3200,1000,*,UP,NDIF ++S 3000,1900,3000,3200,1000,*,UP,NDIF ++S 4000,4000,4000,6100,400,*,UP,ALU1 ++S 3900,4000,3900,6100,400,*,UP,ALU1 ++S 4000,4000,4000,6000,400,a2,DOWN,CALU1 ++S 4000,4000,5100,4000,400,*,RIGHT,ALU1 ++S 5000,4000,5000,4000,400,a2,LEFT,CALU1 ++S 5400,2100,5400,2700,600,*,UP,NDIF ++S 5400,2000,5400,2800,600,*,UP,ALU1 ++S 4000,7000,4000,7000,400,a1,LEFT,CALU1 ++S 4000,3000,4000,3000,400,b2,LEFT,CALU1 ++S 3000,6000,3000,6000,400,b1,LEFT,CALU1 ++S 2000,7000,2000,7000,400,z,LEFT,CALU1 ++S 2000,3000,2000,3000,400,z,LEFT,CALU1 ++S 2400,3400,2400,3900,200,*,UP,POLY ++S 4600,5000,4600,5500,200,*,DOWN,POLY ++S 1200,3400,1200,4700,200,*,UP,POLY ++V 2000,700,CONT_BODY_P,* ++V 1000,700,CONT_BODY_P,* ++V 3200,7000,CONT_DIF_P,* ++V 3000,4900,CONT_POLY,* ++V 1200,8000,CONT_DIF_P,* ++V 5200,8000,CONT_DIF_P,* ++V 1800,4900,CONT_POLY,* ++V 5000,4900,CONT_POLY,* ++V 5200,9000,CONT_DIF_P,* ++V 1200,9000,CONT_DIF_P,* ++V 4200,1000,CONT_DIF_N,* ++V 600,2000,CONT_DIF_N,n3 ++V 3000,2000,CONT_DIF_N,n3 ++V 5400,2000,CONT_DIF_N,n3 ++V 1800,3000,CONT_DIF_N,* ++V 3200,8000,CONT_DIF_P,* ++V 5400,2800,CONT_DIF_N,n3 ++V 4000,4000,CONT_POLY,* ++EOF +diff --git a/alliance/src/cells/src/msxlib/oai22_x1.vbe b/alliance/src/cells/src/msxlib/oai22_x1.vbe +new file mode 100644 +index 0000000..1975abc +--- /dev/null ++++ b/alliance/src/cells/src/msxlib/oai22_x1.vbe +@@ -0,0 +1,44 @@ ++ENTITY oai22_x1 IS ++GENERIC ( ++ CONSTANT area : NATURAL := 6000; ++ CONSTANT cin_b1 : NATURAL := 7; ++ CONSTANT cin_b2 : NATURAL := 6; ++ CONSTANT cin_a1 : NATURAL := 6; ++ CONSTANT cin_a2 : NATURAL := 6; ++ CONSTANT rdown_b1_z : NATURAL := 2010; ++ CONSTANT rdown_b2_z : NATURAL := 2010; ++ CONSTANT rdown_a1_z : NATURAL := 1990; ++ CONSTANT rdown_a2_z : NATURAL := 1990; ++ CONSTANT rup_b1_z : NATURAL := 2990; ++ CONSTANT rup_b2_z : NATURAL := 2990; ++ CONSTANT rup_a1_z : NATURAL := 2990; ++ CONSTANT rup_a2_z : NATURAL := 2990; ++ CONSTANT tphl_a2_z : NATURAL := 55; ++ CONSTANT tphl_b2_z : NATURAL := 48; ++ CONSTANT tplh_b1_z : NATURAL := 63; ++ CONSTANT tphl_a1_z : NATURAL := 64; ++ CONSTANT tplh_b2_z : NATURAL := 53; ++ CONSTANT tphl_b1_z : NATURAL := 57; ++ CONSTANT tplh_a1_z : NATURAL := 80; ++ CONSTANT tplh_a2_z : NATURAL := 70; ++ CONSTANT transistors : NATURAL := 8 ++); ++PORT ( ++ b1 : in BIT; ++ b2 : in BIT; ++ a1 : in BIT; ++ a2 : in BIT; ++ z : out BIT; ++ vdd : in BIT; ++ vss : in BIT ++); ++END oai22_x1; ++ ++ARCHITECTURE behaviour_data_flow OF oai22_x1 IS ++ ++BEGIN ++ ASSERT ((vdd and not (vss)) = '1') ++ REPORT "power supply is missing on oai22_x1" ++ SEVERITY WARNING; ++ z <= not (((b1 or b2) and (a1 or a2))) after 1000 ps; ++END; +diff --git a/alliance/src/cells/src/msxlib/oai22_x2.ap b/alliance/src/cells/src/msxlib/oai22_x2.ap +new file mode 100644 +index 0000000..e51c32a +--- /dev/null ++++ b/alliance/src/cells/src/msxlib/oai22_x2.ap +@@ -0,0 +1,167 @@ ++V ALLIANCE : 6 ++H oai22_x2,P, 9/ 8/2014,100 ++A 0,0,10000,10000 ++R 6000,4000,ref_ref,a2_40 ++R 8000,4000,ref_ref,a1_40 ++R 8000,7000,ref_ref,a2_70 ++R 8000,6000,ref_ref,a2_60 ++R 4000,4000,ref_ref,b2_40 ++R 3000,5000,ref_ref,b2_50 ++R 3000,6000,ref_ref,b1_60 ++R 4000,5000,ref_ref,b1_50 ++R 2000,5000,ref_ref,b1_50 ++R 2000,4000,ref_ref,b1_40 ++R 9000,4000,ref_ref,a1_40 ++R 9000,5000,ref_ref,a1_50 ++R 6000,5000,ref_ref,a1_50 ++R 8000,5000,ref_ref,a2_50 ++R 7000,4000,ref_ref,a2_40 ++R 4000,3000,ref_ref,z_30 ++R 3000,3000,ref_ref,z_30 ++R 2000,3000,ref_ref,z_30 ++R 6000,7000,ref_ref,z_70 ++R 3000,8000,ref_ref,z_80 ++R 3000,7000,ref_ref,z_70 ++R 2000,7000,ref_ref,z_70 ++R 1000,6000,ref_ref,z_60 ++R 1000,5000,ref_ref,z_50 ++R 1000,4000,ref_ref,z_40 ++R 4000,7000,ref_ref,z_70 ++R 5000,7000,ref_ref,z_70 ++R 5000,3000,ref_ref,b2_30 ++R 7000,7000,ref_ref,z_70 ++R 1000,7000,ref_ref,z_70 ++R 1000,3000,ref_ref,z_30 ++R 2000,6000,ref_ref,b1_60 ++R 4000,6000,ref_ref,b1_60 ++R 3000,4000,ref_ref,b2_40 ++R 5000,4000,ref_ref,b2_40 ++R 7000,5000,ref_ref,a2_50 ++R 9000,6000,ref_ref,a1_60 ++R 7000,6000,ref_ref,z_60 ++S 8500,700,9300,700,600,*,RIGHT,PTIE ++S 6000,7000,6000,7000,400,z,LEFT,CALU1 ++S 5000,7000,5000,7000,400,z,LEFT,CALU1 ++S 4000,7000,4000,7000,400,z,LEFT,CALU1 ++S 2000,7000,2000,7000,400,z,LEFT,CALU1 ++S 4000,3000,4000,3000,400,z,LEFT,CALU1 ++S 3000,3000,3000,3000,400,z,LEFT,CALU1 ++S 2000,3000,2000,3000,400,z,LEFT,CALU1 ++S 3000,6000,3000,6000,400,b1,LEFT,CALU1 ++S 4000,4000,4000,4000,400,b2,LEFT,CALU1 ++S 7400,2300,7400,2900,600,*,UP,NDIF ++S 7400,2000,7400,3100,400,*,UP,ALU1 ++S 2500,2000,7400,2000,400,*,RIGHT,ALU1 ++S 7000,4000,7000,4000,400,a1,LEFT,CALU1 ++S 8000,4000,8000,4000,400,a1,LEFT,CALU1 ++S 7000,5000,7000,5000,400,a2,LEFT,CALU1 ++S 8000,5000,8000,7100,400,*,DOWN,ALU1 ++S 6000,4000,6000,5100,600,*,UP,ALU1 ++S 6000,4000,6000,5000,400,a1,UP,CALU1 ++S 8000,5000,8000,7000,400,a2,DOWN,CALU1 ++S 6000,4000,9000,4000,400,*,RIGHT,ALU1 ++S 0,600,10000,600,1200,vss,RIGHT,CALU1 ++S 0,5000,10000,5000,10000,oai22_x2,LEFT,TALU8 ++S 0,2200,10000,2200,5200,*,LEFT,PWELL ++S 0,7600,10000,7600,5600,*,LEFT,NWELL ++S 0,9400,10000,9400,1200,vdd,RIGHT,CALU1 ++S 2000,5800,2000,9100,600,n2a,UP,PDIF ++S 4000,5800,4000,9100,600,n2b,UP,PDIF ++S 6000,5800,6000,9100,600,n1a,UP,PDIF ++S 8000,5800,8000,9100,600,n1b,UP,PDIF ++S 3200,600,3200,3900,200,8,UP,NTRANS ++S 4400,600,4400,3900,200,7,UP,NTRANS ++S 6800,600,6800,3900,200,6,UP,NTRANS ++S 5600,600,5600,3900,200,5,UP,NTRANS ++S 7000,5800,7000,9100,1000,*,UP,PDIF ++S 5000,5800,5000,9100,1000,*,UP,PDIF ++S 3000,5800,3000,9100,1000,*,UP,PDIF ++S 900,5800,900,9100,600,*,DOWN,PDIF ++S 9100,5800,9100,9100,600,*,DOWN,PDIF ++S 3000,4000,3000,5000,400,b2,UP,CALU1 ++S 3200,300,3200,600,200,*,UP,POLY ++S 4400,300,4400,600,200,*,UP,POLY ++S 5600,300,5600,600,200,*,UP,POLY ++S 6800,300,6800,600,200,*,UP,POLY ++S 7200,800,7200,3700,400,*,UP,NDIF ++S 6200,800,6200,3700,1000,*,UP,NDIF ++S 5000,800,5000,3700,1000,*,UP,NDIF ++S 3800,800,3800,3700,1000,*,UP,NDIF ++S 2800,800,2800,3700,400,*,UP,NDIF ++S 1000,3000,1000,7000,400,z,DOWN,CALU1 ++S 1000,3000,1000,7000,400,*,DOWN,ALU1 ++S 5500,5000,6000,5000,600,*,LEFT,ALU1 ++S 2000,6000,4000,6000,400,*,RIGHT,ALU1 ++S 2400,5200,3600,5200,200,*,RIGHT,POLY ++S 8400,5200,8600,5200,200,*,RIGHT,POLY ++S 6400,5200,7600,5200,200,*,RIGHT,POLY ++S 8400,5600,8400,9300,200,1b,DOWN,PTRANS ++S 7600,5600,7600,9300,200,2b,DOWN,PTRANS ++S 6400,5600,6400,9300,200,2a,DOWN,PTRANS ++S 5600,5600,5600,9300,200,1a,DOWN,PTRANS ++S 4400,5600,4400,9300,200,3b,DOWN,PTRANS ++S 2400,5600,2400,9300,200,4a,DOWN,PTRANS ++S 1600,5600,1600,9300,200,3a,DOWN,PTRANS ++S 3600,5600,3600,9300,200,4b,DOWN,PTRANS ++S 3000,7000,3000,8100,400,*,UP,ALU1 ++S 3000,7000,3000,8000,400,z,UP,CALU1 ++S 900,3000,900,7000,400,*,DOWN,ALU1 ++S 1000,7000,7000,7000,400,*,RIGHT,ALU1 ++S 1000,3000,4100,3000,400,*,RIGHT,ALU1 ++S 2000,3900,2000,6000,400,*,DOWN,ALU1 ++S 2000,4000,2000,6000,400,b1,UP,CALU1 ++S 4000,5400,4000,6000,400,*,DOWN,ALU1 ++S 4000,5000,4000,6000,400,b1,UP,CALU1 ++S 2000,6100,4000,6100,400,*,RIGHT,ALU1 ++S 4000,5000,4500,5000,600,*,RIGHT,ALU1 ++S 3000,4000,5000,4000,400,*,RIGHT,ALU1 ++S 3000,4000,3000,5000,600,*,DOWN,ALU1 ++S 1600,4500,1600,5600,200,*,DOWN,POLY ++S 5000,3000,5000,4000,400,b2,DOWN,CALU1 ++S 5000,3000,5000,4000,600,*,DOWN,ALU1 ++S 9000,4000,9000,6000,400,a1,UP,CALU1 ++S 7000,5000,8000,5000,600,*,RIGHT,ALU1 ++S 8400,9300,8400,9700,200,*,DOWN,POLY ++S 7600,9300,7600,9700,200,*,DOWN,POLY ++S 6400,9300,6400,9700,200,*,DOWN,POLY ++S 5600,9300,5600,9700,200,*,DOWN,POLY ++S 4400,9300,4400,9700,200,*,DOWN,POLY ++S 3600,9300,3600,9700,200,*,DOWN,POLY ++S 2400,9300,2400,9700,200,*,DOWN,POLY ++S 1600,9300,1600,9700,200,*,DOWN,POLY ++S 3200,3900,3200,4600,200,*,UP,POLY ++S 4400,3900,4400,4600,200,*,UP,POLY ++S 5600,3900,5600,4600,200,*,UP,POLY ++S 6800,3900,6800,5200,200,*,UP,POLY ++S 9000,4000,9000,6000,600,*,UP,ALU1 ++S 7000,6000,7000,7000,400,z,UP,CALU1 ++S 7000,6000,7000,7000,600,*,UP,ALU1 ++S 1000,7900,1000,9300,400,*,UP,ALU1 ++S 5000,7900,5000,9300,400,*,UP,ALU1 ++S 9000,6900,9000,9300,400,*,UP,ALU1 ++V 9300,700,CONT_BODY_P,* ++V 8400,700,CONT_BODY_P,* ++V 7400,2200,CONT_DIF_N,n3 ++V 7400,3000,CONT_DIF_N,n3 ++V 7000,5000,CONT_POLY,* ++V 6200,1000,CONT_DIF_N,* ++V 5000,2000,CONT_DIF_N,n3 ++V 2600,2000,CONT_DIF_N,n3 ++V 3800,3000,CONT_DIF_N,* ++V 3000,5000,CONT_POLY,* ++V 9000,5000,CONT_POLY,* ++V 5600,5000,CONT_POLY,* ++V 1000,8000,CONT_DIF_P,* ++V 9000,8000,CONT_DIF_P,* ++V 5000,8000,CONT_DIF_P,* ++V 3000,8000,CONT_DIF_P,* ++V 3000,7000,CONT_DIF_P,* ++V 1000,9000,CONT_DIF_P,* ++V 5000,9000,CONT_DIF_P,* ++V 2000,4400,CONT_POLY,* ++V 9000,9000,CONT_DIF_P,* ++V 7000,7000,CONT_DIF_P,* ++V 4400,5000,CONT_POLY,* ++V 7000,6000,CONT_DIF_P,* ++V 9000,7000,CONT_DIF_P,* ++EOF +diff --git a/alliance/src/cells/src/msxlib/oai22_x2.vbe b/alliance/src/cells/src/msxlib/oai22_x2.vbe +new file mode 100644 +index 0000000..4e3796b +--- /dev/null ++++ b/alliance/src/cells/src/msxlib/oai22_x2.vbe +@@ -0,0 +1,44 @@ ++ENTITY oai22_x2 IS ++GENERIC ( ++ CONSTANT area : NATURAL := 10000; ++ CONSTANT cin_b1 : NATURAL := 12; ++ CONSTANT cin_b2 : NATURAL := 11; ++ CONSTANT cin_a1 : NATURAL := 12; ++ CONSTANT cin_a2 : NATURAL := 11; ++ CONSTANT rdown_b1_z : NATURAL := 1040; ++ CONSTANT rdown_b2_z : NATURAL := 1030; ++ CONSTANT rdown_a1_z : NATURAL := 1020; ++ CONSTANT rdown_a2_z : NATURAL := 1020; ++ CONSTANT rup_b1_z : NATURAL := 1580; ++ CONSTANT rup_b2_z : NATURAL := 1570; ++ CONSTANT rup_a1_z : NATURAL := 1570; ++ CONSTANT rup_a2_z : NATURAL := 1570; ++ CONSTANT tphl_a2_z : NATURAL := 53; ++ CONSTANT tphl_b2_z : NATURAL := 47; ++ CONSTANT tplh_b1_z : NATURAL := 62; ++ CONSTANT tphl_a1_z : NATURAL := 62; ++ CONSTANT tplh_b2_z : NATURAL := 52; ++ CONSTANT tphl_b1_z : NATURAL := 56; ++ CONSTANT tplh_a1_z : NATURAL := 78; ++ CONSTANT tplh_a2_z : NATURAL := 69; ++ CONSTANT transistors : NATURAL := 12 ++); ++PORT ( ++ b1 : in BIT; ++ b2 : in BIT; ++ a1 : in BIT; ++ a2 : in BIT; ++ z : out BIT; ++ vdd : in BIT; ++ vss : in BIT ++); ++END oai22_x2; ++ ++ARCHITECTURE behaviour_data_flow OF oai22_x2 IS ++ ++BEGIN ++ ASSERT ((vdd and not (vss)) = '1') ++ REPORT "power supply is missing on oai22_x2" ++ SEVERITY WARNING; ++ z <= not (((b1 or b2) and (a1 or a2))) after 1000 ps; ++END; +diff --git a/alliance/src/cells/src/msxlib/oan21_x1.ap b/alliance/src/cells/src/msxlib/oan21_x1.ap +new file mode 100644 +index 0000000..ae856ff +--- /dev/null ++++ b/alliance/src/cells/src/msxlib/oan21_x1.ap +@@ -0,0 +1,117 @@ ++V ALLIANCE : 6 ++H oan21_x1,P, 9/ 8/2014,100 ++A 0,0,7000,10000 ++R 5000,6000,ref_ref,a2_60 ++R 6000,5000,ref_ref,a1_50 ++R 5000,5000,ref_ref,a2_50 ++R 4000,5000,ref_ref,b_50 ++R 6000,6000,ref_ref,a1_60 ++R 6000,7000,ref_ref,a1_70 ++R 5000,7000,ref_ref,a1_70 ++R 4000,3000,ref_ref,b_30 ++R 5000,3000,ref_ref,b_30 ++R 4000,4000,ref_ref,b_40 ++R 6000,4000,ref_ref,a2_40 ++R 5000,4000,ref_ref,a2_40 ++R 1000,6000,ref_ref,z_60 ++R 2000,6000,ref_ref,z_60 ++R 2000,5000,ref_ref,z_50 ++R 2000,4000,ref_ref,z_40 ++R 2000,3000,ref_ref,z_30 ++S 1100,9300,1900,9300,600,*,RIGHT,NTIE ++S 1100,700,1900,700,600,*,RIGHT,PTIE ++S 6000,7900,6000,9300,400,*,UP,ALU1 ++S 4000,2900,5100,2900,400,*,RIGHT,ALU1 ++S 4000,3000,4000,5100,400,*,DOWN,ALU1 ++S 4000,3000,5100,3000,400,*,RIGHT,ALU1 ++S 4000,3000,4000,5000,400,b,DOWN,CALU1 ++S 5000,4000,5000,6000,400,a2,DOWN,CALU1 ++S 4900,7100,6000,7100,400,*,RIGHT,ALU1 ++S 6000,4800,6000,7000,400,*,UP,ALU1 ++S 6000,5000,6000,7000,400,a1,UP,CALU1 ++S 4900,7000,6000,7000,400,*,RIGHT,ALU1 ++S 2800,6900,2800,9300,400,*,UP,ALU1 ++S 5000,3000,5000,3000,400,b,LEFT,CALU1 ++S 6000,4000,6000,4000,400,a2,LEFT,CALU1 ++S 5000,7000,5000,7000,400,a1,LEFT,CALU1 ++S 5000,4000,5000,6100,400,*,UP,ALU1 ++S 5000,3900,6100,3900,400,*,RIGHT,ALU1 ++S 5000,4000,6100,4000,400,*,RIGHT,ALU1 ++S 5400,5100,5900,5100,200,*,RIGHT,POLY ++S 5400,5100,5400,5500,200,*,DOWN,POLY ++S 0,600,7000,600,1200,vss,RIGHT,CALU1 ++S 0,9400,7000,9400,1200,vdd,RIGHT,CALU1 ++S 0,5000,7000,5000,10000,oan21_x1,LEFT,TALU8 ++S 0,2200,7000,2200,5200,*,LEFT,PWELL ++S 0,7600,7000,7600,5600,*,LEFT,NWELL ++S 4600,3800,4600,5500,200,*,UP,POLY ++S 600,700,600,3100,400,*,DOWN,ALU1 ++S 1600,6100,1600,6700,600,*,DOWN,PDIF ++S 1000,6000,2000,6000,600,*,LEFT,ALU1 ++S 1600,5900,1600,6900,400,*,DOWN,ALU1 ++S 3400,4700,3400,5500,200,*,UP,POLY ++S 3900,4800,3900,5100,600,*,DOWN,ALU1 ++S 2800,3900,3000,3900,600,*,RIGHT,ALU1 ++S 2000,3000,2000,6000,400,z,UP,CALU1 ++S 1000,6000,1000,6000,400,z,LEFT,CALU1 ++S 5400,8300,5400,8700,200,*,DOWN,POLY ++S 4600,8300,4600,8700,200,*,DOWN,POLY ++S 5100,5900,5100,8100,400,n1,UP,PDIF ++S 5400,5700,5400,8300,200,1,DOWN,PTRANS ++S 4600,5700,4600,8300,200,2,DOWN,PTRANS ++S 6000,5900,6000,8100,600,*,DOWN,PDIF ++S 4200,5900,4200,8100,400,*,DOWN,PDIF ++S 4000,5900,4000,6900,1000,*,UP,PDIF ++S 3400,5700,3400,7100,200,3,DOWN,PTRANS ++S 4000,6000,4000,6900,400,*,UP,ALU1 ++S 3000,5900,4000,5900,400,*,RIGHT,ALU1 ++S 3400,7100,3400,7500,200,*,DOWN,POLY ++S 4200,1900,4200,2700,600,*,DOWN,NDIF ++S 4800,1700,4800,2900,200,5,UP,NTRANS ++S 5800,1700,5800,2900,200,4,UP,NTRANS ++S 3200,1900,3200,2700,400,*,UP,NDIF ++S 3600,1700,3600,2900,200,6,UP,NTRANS ++S 3000,2500,3000,5900,400,*,DOWN,ALU1 ++S 4100,2000,6500,2000,400,*,RIGHT,ALU1 ++S 6200,1900,6200,2700,400,*,UP,NDIF ++S 5800,2900,5800,4800,200,*,UP,POLY ++S 4800,2900,4800,4000,200,*,UP,POLY ++S 3600,2900,3600,4800,200,*,UP,POLY ++S 3600,1300,3600,1700,200,*,UP,POLY ++S 4800,1300,4800,1700,200,*,UP,POLY ++S 5800,1300,5800,1700,200,*,UP,POLY ++S 5300,600,5300,2700,400,*,UP,NDIF ++S 2200,5700,2200,7700,200,2,DOWN,PTRANS ++S 2800,5900,2800,7500,600,*,DOWN,PDIF ++S 1800,5900,1800,7500,400,*,UP,PDIF ++S 2200,7700,2200,8100,200,*,DOWN,POLY ++S 1200,2300,1200,3300,200,6,UP,NTRANS ++S 1600,2500,1600,3100,400,*,UP,NDIF ++S 1200,1900,1200,2300,200,*,UP,POLY ++S 600,2500,600,3100,600,*,UP,NDIF ++S 1200,3700,2800,3700,200,*,LEFT,POLY ++S 2200,3700,2200,5500,200,*,DOWN,POLY ++S 2200,3900,2800,3900,600,*,LEFT,POLY ++S 2000,2900,2000,6000,400,*,UP,ALU1 ++S 1900,2900,1900,3400,600,*,UP,ALU1 ++V 2000,9300,CONT_BODY_N,* ++V 1000,9300,CONT_BODY_N,* ++V 2000,700,CONT_BODY_P,* ++V 1000,700,CONT_BODY_P,* ++V 5000,4000,CONT_POLY,* ++V 6000,4900,CONT_POLY,* ++V 2800,7000,CONT_DIF_P,* ++V 6000,8000,CONT_DIF_P,* ++V 4200,2000,CONT_DIF_N,n2 ++V 600,3000,CONT_DIF_N,* ++V 1600,6000,CONT_DIF_P,* ++V 1600,6800,CONT_DIF_P,* ++V 3800,4900,CONT_POLY,* ++V 2800,3900,CONT_POLY,zn ++V 4000,6000,CONT_DIF_P,zn ++V 4000,6800,CONT_DIF_P,zn ++V 3000,2600,CONT_DIF_N,zn ++V 6400,2000,CONT_DIF_N,n2 ++V 5400,700,CONT_DIF_N,* ++V 1800,3000,CONT_DIF_N,* ++EOF +diff --git a/alliance/src/cells/src/msxlib/oan21_x1.vbe b/alliance/src/cells/src/msxlib/oan21_x1.vbe +new file mode 100644 +index 0000000..543780b +--- /dev/null ++++ b/alliance/src/cells/src/msxlib/oan21_x1.vbe +@@ -0,0 +1,38 @@ ++ENTITY oan21_x1 IS ++GENERIC ( ++ CONSTANT area : NATURAL := 7000; ++ CONSTANT cin_a1 : NATURAL := 5; ++ CONSTANT cin_a2 : NATURAL := 5; ++ CONSTANT cin_b : NATURAL := 4; ++ CONSTANT rdown_a1_z : NATURAL := 2310; ++ CONSTANT rdown_a2_z : NATURAL := 2310; ++ CONSTANT rdown_b_z : NATURAL := 2300; ++ CONSTANT rup_a1_z : NATURAL := 2970; ++ CONSTANT rup_a2_z : NATURAL := 2960; ++ CONSTANT rup_b_z : NATURAL := 2960; ++ CONSTANT tphh_b_z : NATURAL := 77; ++ CONSTANT tpll_b_z : NATURAL := 100; ++ CONSTANT tpll_a1_z : NATURAL := 125; ++ CONSTANT tphh_a2_z : NATURAL := 83; ++ CONSTANT tpll_a2_z : NATURAL := 116; ++ CONSTANT tphh_a1_z : NATURAL := 95; ++ CONSTANT transistors : NATURAL := 8 ++); ++PORT ( ++ a1 : in BIT; ++ a2 : in BIT; ++ b : in BIT; ++ z : out BIT; ++ vdd : in BIT; ++ vss : in BIT ++); ++END oan21_x1; ++ ++ARCHITECTURE behaviour_data_flow OF oan21_x1 IS ++ ++BEGIN ++ ASSERT ((vdd and not (vss)) = '1') ++ REPORT "power supply is missing on oan21_x1" ++ SEVERITY WARNING; ++ z <= ((a1 or a2) and b) after 1200 ps; ++END; +diff --git a/alliance/src/cells/src/msxlib/oan21_x2.ap b/alliance/src/cells/src/msxlib/oan21_x2.ap +new file mode 100644 +index 0000000..9016472 +--- /dev/null ++++ b/alliance/src/cells/src/msxlib/oan21_x2.ap +@@ -0,0 +1,126 @@ ++V ALLIANCE : 6 ++H oan21_x2,P, 9/ 8/2014,100 ++A 0,0,7000,10000 ++R 5000,6000,ref_ref,a2_60 ++R 6000,5000,ref_ref,a1_50 ++R 5000,5000,ref_ref,a2_50 ++R 4000,5000,ref_ref,b_50 ++R 6000,6000,ref_ref,a1_60 ++R 6000,7000,ref_ref,a1_70 ++R 5000,7000,ref_ref,a1_70 ++R 4000,3000,ref_ref,b_30 ++R 5000,3000,ref_ref,b_30 ++R 4000,4000,ref_ref,b_40 ++R 6000,4000,ref_ref,a2_40 ++R 5000,4000,ref_ref,a2_40 ++R 1000,6000,ref_ref,z_60 ++R 2000,6000,ref_ref,z_60 ++R 2000,5000,ref_ref,z_50 ++R 2000,4000,ref_ref,z_40 ++R 2000,3000,ref_ref,z_30 ++S 1100,700,1900,700,600,*,RIGHT,PTIE ++S 6000,7900,6000,9300,400,*,UP,ALU1 ++S 4000,2900,5100,2900,400,*,RIGHT,ALU1 ++S 4000,3000,4000,5100,400,*,DOWN,ALU1 ++S 4000,3000,5100,3000,400,*,RIGHT,ALU1 ++S 4000,3000,4000,5000,400,b,DOWN,CALU1 ++S 5000,4000,5000,6000,400,a2,DOWN,CALU1 ++S 4900,7100,6000,7100,400,*,RIGHT,ALU1 ++S 6000,4800,6000,7000,400,*,UP,ALU1 ++S 6000,5000,6000,7000,400,a1,UP,CALU1 ++S 4900,7000,6000,7000,400,*,RIGHT,ALU1 ++S 2800,6900,2800,9300,400,*,UP,ALU1 ++S 5000,3000,5000,3000,400,b,LEFT,CALU1 ++S 6000,4000,6000,4000,400,a2,LEFT,CALU1 ++S 5000,7000,5000,7000,400,a1,LEFT,CALU1 ++S 5000,4000,5000,6100,400,*,UP,ALU1 ++S 5000,3900,6100,3900,400,*,RIGHT,ALU1 ++S 5000,4000,6100,4000,400,*,RIGHT,ALU1 ++S 6400,2000,6400,3100,400,*,UP,ALU1 ++S 5400,5100,5900,5100,200,*,RIGHT,POLY ++S 5400,5100,5400,5500,200,*,DOWN,POLY ++S 3400,7500,3400,7900,200,*,DOWN,POLY ++S 5800,1200,5800,1600,200,*,UP,POLY ++S 5800,3300,5800,4800,200,*,UP,POLY ++S 6200,1800,6200,3100,400,*,UP,NDIF ++S 6400,2300,6400,2900,600,*,UP,NDIF ++S 5800,1600,5800,3300,200,4,UP,NTRANS ++S 4000,5700,4000,7300,1000,*,UP,PDIF ++S 3400,5500,3400,7500,200,3,DOWN,PTRANS ++S 0,600,7000,600,1200,vss,RIGHT,CALU1 ++S 0,9400,7000,9400,1200,vdd,RIGHT,CALU1 ++S 0,5000,7000,5000,10000,oan21_x2,LEFT,TALU8 ++S 0,2200,7000,2200,5200,*,LEFT,PWELL ++S 0,7600,7000,7600,5600,*,LEFT,NWELL ++S 4600,5500,4600,9300,200,2,DOWN,PTRANS ++S 5400,5500,5400,9300,200,1,DOWN,PTRANS ++S 5100,5700,5100,9100,400,n1,UP,PDIF ++S 4200,5700,4200,9100,400,*,DOWN,PDIF ++S 6000,5700,6000,9100,600,*,DOWN,PDIF ++S 5400,9300,5400,9700,200,*,DOWN,POLY ++S 4600,9300,4600,9700,200,*,DOWN,POLY ++S 5300,500,5300,3100,400,*,UP,NDIF ++S 4800,1600,4800,3300,200,5,UP,NTRANS ++S 4800,1200,4800,1600,200,*,UP,POLY ++S 4200,1800,4200,3100,600,*,DOWN,NDIF ++S 3600,1600,3600,3300,200,6,UP,NTRANS ++S 3600,1200,3600,1600,200,*,UP,POLY ++S 3000,2300,3000,2900,600,*,UP,NDIF ++S 3200,1800,3200,3100,400,*,UP,NDIF ++S 4600,3800,4600,5500,200,*,UP,POLY ++S 4800,3300,4800,4000,200,*,UP,POLY ++S 1200,1700,1200,3600,200,6,UP,NTRANS ++S 600,700,600,3100,400,*,DOWN,ALU1 ++S 600,1900,600,3400,600,*,UP,NDIF ++S 1600,1900,1600,3400,400,*,UP,NDIF ++S 1200,1200,1200,1600,200,*,UP,POLY ++S 2200,5500,2200,9300,200,2,DOWN,PTRANS ++S 1600,6100,1600,6700,600,*,DOWN,PDIF ++S 1800,5700,1800,9100,400,*,UP,PDIF ++S 2800,5700,2800,9100,600,*,DOWN,PDIF ++S 1000,6000,2000,6000,600,*,LEFT,ALU1 ++S 1600,5900,1600,6900,400,*,DOWN,ALU1 ++S 3600,3300,3600,4800,200,*,UP,POLY ++S 3400,4700,3400,5500,200,*,UP,POLY ++S 3900,4800,3900,5100,600,*,DOWN,ALU1 ++S 2800,3900,3000,3900,600,*,RIGHT,ALU1 ++S 3000,6000,4000,6000,400,*,RIGHT,ALU1 ++S 4000,6000,4000,7100,400,*,UP,ALU1 ++S 1200,4100,2800,4100,200,*,LEFT,POLY ++S 1200,3600,1200,4100,200,*,DOWN,POLY ++S 2200,4100,2200,5500,200,*,DOWN,POLY ++S 3000,2100,3000,6000,400,*,DOWN,ALU1 ++S 2000,3000,2000,6000,400,z,UP,CALU1 ++S 1000,6000,1000,6000,400,z,LEFT,CALU1 ++S 2200,9300,2200,9700,200,*,DOWN,POLY ++S 4100,2000,6400,2000,400,*,RIGHT,ALU1 ++S 1800,2600,1800,3200,600,*,DOWN,NDIF ++S 2000,2400,2000,6000,400,*,UP,ALU1 ++S 1900,2400,1900,3400,600,*,UP,ALU1 ++V 2000,700,CONT_BODY_P,* ++V 1000,700,CONT_BODY_P,* ++V 700,9300,CONT_BODY_N,* ++V 5000,4000,CONT_POLY,* ++V 6000,4900,CONT_POLY,* ++V 6400,2200,CONT_DIF_N,n2 ++V 6400,3000,CONT_DIF_N,n2 ++V 2800,7000,CONT_DIF_P,* ++V 6000,9000,CONT_DIF_P,* ++V 6000,8000,CONT_DIF_P,* ++V 5400,600,CONT_DIF_N,* ++V 4200,2000,CONT_DIF_N,n2 ++V 600,2000,CONT_DIF_N,* ++V 1800,3300,CONT_DIF_N,* ++V 600,3000,CONT_DIF_N,* ++V 1600,6000,CONT_DIF_P,* ++V 1600,6800,CONT_DIF_P,* ++V 2800,8000,CONT_DIF_P,* ++V 2800,9000,CONT_DIF_P,* ++V 3800,4900,CONT_POLY,* ++V 4000,7000,CONT_DIF_P,zn ++V 4000,6200,CONT_DIF_P,zn ++V 2800,3900,CONT_POLY,zn ++V 3000,3000,CONT_DIF_N,zn ++V 3000,2200,CONT_DIF_N,zn ++V 1800,2500,CONT_DIF_N,* ++EOF +diff --git a/alliance/src/cells/src/msxlib/oan21_x2.vbe b/alliance/src/cells/src/msxlib/oan21_x2.vbe +new file mode 100644 +index 0000000..b05bce2 +--- /dev/null ++++ b/alliance/src/cells/src/msxlib/oan21_x2.vbe +@@ -0,0 +1,38 @@ ++ENTITY oan21_x2 IS ++GENERIC ( ++ CONSTANT area : NATURAL := 7000; ++ CONSTANT cin_a1 : NATURAL := 6; ++ CONSTANT cin_a2 : NATURAL := 7; ++ CONSTANT cin_b : NATURAL := 5; ++ CONSTANT rdown_a1_z : NATURAL := 1220; ++ CONSTANT rdown_a2_z : NATURAL := 1220; ++ CONSTANT rdown_b_z : NATURAL := 1210; ++ CONSTANT rup_a1_z : NATURAL := 1560; ++ CONSTANT rup_a2_z : NATURAL := 1560; ++ CONSTANT rup_b_z : NATURAL := 1560; ++ CONSTANT tphh_b_z : NATURAL := 80; ++ CONSTANT tpll_b_z : NATURAL := 103; ++ CONSTANT tpll_a1_z : NATURAL := 126; ++ CONSTANT tphh_a2_z : NATURAL := 85; ++ CONSTANT tpll_a2_z : NATURAL := 117; ++ CONSTANT tphh_a1_z : NATURAL := 98; ++ CONSTANT transistors : NATURAL := 8 ++); ++PORT ( ++ a1 : in BIT; ++ a2 : in BIT; ++ b : in BIT; ++ z : out BIT; ++ vdd : in BIT; ++ vss : in BIT ++); ++END oan21_x2; ++ ++ARCHITECTURE behaviour_data_flow OF oan21_x2 IS ++ ++BEGIN ++ ASSERT ((vdd and not (vss)) = '1') ++ REPORT "power supply is missing on oan21_x2" ++ SEVERITY WARNING; ++ z <= ((a1 or a2) and b) after 1200 ps; ++END; +diff --git a/alliance/src/cells/src/msxlib/oan22_x1.ap b/alliance/src/cells/src/msxlib/oan22_x1.ap +new file mode 100644 +index 0000000..36f6622 +--- /dev/null ++++ b/alliance/src/cells/src/msxlib/oan22_x1.ap +@@ -0,0 +1,137 @@ ++V ALLIANCE : 6 ++H oan22_x1,P, 9/ 8/2014,100 ++A 0,0,8000,10000 ++R 1000,4000,ref_ref,z_40 ++R 2000,3000,ref_ref,z_30 ++R 2000,4000,ref_ref,z_40 ++R 2000,5000,ref_ref,z_50 ++R 2000,6000,ref_ref,z_60 ++R 2000,7000,ref_ref,z_70 ++R 5000,6000,ref_ref,b1_60 ++R 6000,7000,ref_ref,a1_70 ++R 6000,6000,ref_ref,a2_60 ++R 4000,6000,ref_ref,b1_60 ++R 6000,3000,ref_ref,b2_30 ++R 5000,4000,ref_ref,b2_40 ++R 5000,5000,ref_ref,b2_50 ++R 6000,4000,ref_ref,a2_40 ++R 6000,5000,ref_ref,a2_50 ++R 7000,5000,ref_ref,a1_50 ++R 7000,6000,ref_ref,a1_60 ++R 5000,3000,ref_ref,b2_30 ++R 7000,4000,ref_ref,a2_40 ++R 7000,7000,ref_ref,a1_70 ++R 4000,4000,ref_ref,b1_40 ++R 4000,5000,ref_ref,b1_50 ++R 2000,8000,ref_ref,z_80 ++S 1100,9300,1900,9300,600,*,RIGHT,NTIE ++S 1100,700,1900,700,600,*,RIGHT,PTIE ++S 2000,6700,2000,7300,600,*,UP,PDIF ++S 6300,700,6300,2800,400,*,UP,NDIF ++S 6800,1400,6800,1800,200,*,UP,POLY ++S 5800,1400,5800,1800,200,*,UP,POLY ++S 4600,1400,4600,1800,200,*,UP,POLY ++S 3400,1400,3400,1800,200,*,UP,POLY ++S 3400,3000,3400,3900,200,*,UP,POLY ++S 4600,3000,4600,5500,200,*,DOWN,POLY ++S 6800,3000,6800,4700,200,*,UP,POLY ++S 5800,3000,5800,5500,200,*,DOWN,POLY ++S 7400,1900,7400,2100,600,*,UP,ALU1 ++S 2800,1900,2800,2100,600,*,UP,ALU1 ++S 5200,1900,5200,2100,600,*,DOWN,ALU1 ++S 4000,2700,4000,3000,600,*,UP,ALU1 ++S 7200,2000,7200,2800,400,*,DOWN,NDIF ++S 6800,1800,6800,3000,200,5,UP,NTRANS ++S 5800,1800,5800,3000,200,6,UP,NTRANS ++S 5200,2000,5200,2800,1000,*,UP,NDIF ++S 3000,2000,3000,2800,400,*,DOWN,NDIF ++S 4600,1800,4600,3000,200,8,UP,NTRANS ++S 3400,1800,3400,3000,200,7,UP,NTRANS ++S 4000,2000,4000,2800,1000,*,UP,NDIF ++S 2800,1900,7400,1900,400,*,RIGHT,ALU1 ++S 1300,3700,1300,4700,200,*,DOWN,POLY ++S 1300,2300,1300,2700,200,*,UP,POLY ++S 600,2900,600,3500,600,*,UP,NDIF ++S 1300,2700,1300,3700,200,2z,UP,NTRANS ++S 1700,2900,1700,3500,400,*,UP,NDIF ++S 2600,4900,2600,6300,200,*,DOWN,POLY ++S 6600,8300,6600,8700,200,*,DOWN,POLY ++S 5800,8300,5800,8700,200,*,DOWN,POLY ++S 4600,8300,4600,8700,200,*,DOWN,POLY ++S 3800,8300,3800,8700,200,*,DOWN,POLY ++S 2600,8300,2600,8700,200,*,DOWN,POLY ++S 3200,5900,3200,8100,600,*,DOWN,PDIF ++S 2200,6500,2200,8100,400,*,DOWN,PDIF ++S 2600,6300,2600,8300,200,1z,DOWN,PTRANS ++S 4200,5900,4200,8100,600,n2,UP,PDIF ++S 3800,5700,3800,8300,200,3,DOWN,PTRANS ++S 6200,5900,6200,8100,600,n1,UP,PDIF ++S 6600,5700,6600,8300,200,1,DOWN,PTRANS ++S 7300,5900,7300,8100,600,*,DOWN,PDIF ++S 4600,5700,4600,8300,200,4,DOWN,PTRANS ++S 5200,5900,5200,8100,1000,*,UP,PDIF ++S 5800,5700,5800,8300,200,2,DOWN,PTRANS ++S 3000,3000,3000,7000,400,*,DOWN,ALU1 ++S 3000,7000,5200,7000,400,*,RIGHT,ALU1 ++S 5200,7000,5200,8100,400,*,UP,ALU1 ++S 2800,4900,3000,4900,600,*,RIGHT,ALU1 ++S 1300,4700,2800,4700,200,*,LEFT,POLY ++S 900,4000,2000,4000,400,*,LEFT,ALU1 ++S 1000,4000,1000,4000,400,z,LEFT,CALU1 ++S 1900,2900,1900,4000,400,*,DOWN,ALU1 ++S 3800,4000,4000,4000,600,*,RIGHT,ALU1 ++S 3800,4000,3800,5500,200,*,DOWN,POLY ++S 700,700,700,3100,400,*,DOWN,ALU1 ++S 0,5000,8000,5000,10000,oan22_x1,LEFT,TALU8 ++S 0,2200,8000,2200,5200,*,LEFT,PWELL ++S 0,7600,8000,7600,5600,*,LEFT,NWELL ++S 0,9400,8000,9400,1200,vdd,RIGHT,CALU1 ++S 0,600,8000,600,1200,vss,RIGHT,CALU1 ++S 6600,5000,6600,5500,200,*,DOWN,POLY ++S 5000,6000,5000,6000,400,b1,LEFT,CALU1 ++S 6000,4000,6000,6100,400,*,UP,ALU1 ++S 5900,4000,5900,6100,400,*,UP,ALU1 ++S 6000,4000,6000,6000,400,a2,DOWN,CALU1 ++S 6000,4000,7100,4000,400,*,RIGHT,ALU1 ++S 7000,4000,7000,4000,400,a2,LEFT,CALU1 ++S 6000,7000,6000,7000,400,a1,LEFT,CALU1 ++S 6000,3000,6000,3000,400,b2,LEFT,CALU1 ++S 4000,4000,4000,6000,400,b1,UP,CALU1 ++S 4000,6000,5100,6000,400,*,RIGHT,ALU1 ++S 7000,4800,7000,7000,400,*,UP,ALU1 ++S 7000,5000,7000,7000,400,a1,UP,CALU1 ++S 7200,7900,7200,9300,400,*,UP,ALU1 ++S 5000,2900,6100,2900,400,*,RIGHT,ALU1 ++S 5000,3000,6100,3000,400,*,RIGHT,ALU1 ++S 3200,7900,3200,9300,400,*,UP,ALU1 ++S 4000,6100,5100,6100,400,*,RIGHT,ALU1 ++S 6000,7000,7000,7000,600,*,RIGHT,ALU1 ++S 3000,3000,4100,3000,400,*,RIGHT,ALU1 ++S 4000,3900,4000,6000,400,*,UP,ALU1 ++S 5000,3000,5000,5100,400,*,DOWN,ALU1 ++S 5000,3000,5000,5000,400,b2,DOWN,CALU1 ++S 2000,3000,2000,8000,400,z,DOWN,CALU1 ++S 2000,2900,2000,8100,400,*,DOWN,ALU1 ++V 2000,9300,CONT_BODY_N,* ++V 1000,9300,CONT_BODY_N,* ++V 2000,700,CONT_BODY_P,* ++V 1000,700,CONT_BODY_P,* ++V 2000,7400,CONT_DIF_P,* ++V 6400,800,CONT_DIF_N,* ++V 7400,2100,CONT_DIF_N,n3 ++V 5200,2100,CONT_DIF_N,n3 ++V 2800,2100,CONT_DIF_N,n3 ++V 4000,2700,CONT_DIF_N,zn ++V 1900,3400,CONT_DIF_N,* ++V 5200,7200,CONT_DIF_P,zn ++V 5200,8000,CONT_DIF_P,zn ++V 2800,4900,CONT_POLY,zn ++V 2000,6600,CONT_DIF_P,* ++V 3800,4000,CONT_POLY,* ++V 700,3000,CONT_DIF_N,* ++V 3200,8000,CONT_DIF_P,* ++V 7200,8000,CONT_DIF_P,* ++V 5000,4900,CONT_POLY,* ++V 7000,4900,CONT_POLY,* ++V 6000,4000,CONT_POLY,* ++EOF +diff --git a/alliance/src/cells/src/msxlib/oan22_x1.vbe b/alliance/src/cells/src/msxlib/oan22_x1.vbe +new file mode 100644 +index 0000000..6c4adb3 +--- /dev/null ++++ b/alliance/src/cells/src/msxlib/oan22_x1.vbe +@@ -0,0 +1,44 @@ ++ENTITY oan22_x1 IS ++GENERIC ( ++ CONSTANT area : NATURAL := 8000; ++ CONSTANT cin_b1 : NATURAL := 5; ++ CONSTANT cin_b2 : NATURAL := 5; ++ CONSTANT cin_a2 : NATURAL := 5; ++ CONSTANT cin_a1 : NATURAL := 5; ++ CONSTANT rdown_b1_z : NATURAL := 2320; ++ CONSTANT rdown_b2_z : NATURAL := 2320; ++ CONSTANT rdown_a2_z : NATURAL := 2340; ++ CONSTANT rdown_a1_z : NATURAL := 2340; ++ CONSTANT rup_b1_z : NATURAL := 2970; ++ CONSTANT rup_b2_z : NATURAL := 2960; ++ CONSTANT rup_a2_z : NATURAL := 2960; ++ CONSTANT rup_a1_z : NATURAL := 2970; ++ CONSTANT tphh_a2_z : NATURAL := 96; ++ CONSTANT tpll_b1_z : NATURAL := 122; ++ CONSTANT tphh_a1_z : NATURAL := 107; ++ CONSTANT tphh_b2_z : NATURAL := 87; ++ CONSTANT tpll_a1_z : NATURAL := 146; ++ CONSTANT tpll_b2_z : NATURAL := 112; ++ CONSTANT tphh_b1_z : NATURAL := 99; ++ CONSTANT tpll_a2_z : NATURAL := 136; ++ CONSTANT transistors : NATURAL := 10 ++); ++PORT ( ++ b1 : in BIT; ++ b2 : in BIT; ++ a2 : in BIT; ++ a1 : in BIT; ++ z : out BIT; ++ vdd : in BIT; ++ vss : in BIT ++); ++END oan22_x1; ++ ++ARCHITECTURE behaviour_data_flow OF oan22_x1 IS ++ ++BEGIN ++ ASSERT ((vdd and not (vss)) = '1') ++ REPORT "power supply is missing on oan22_x1" ++ SEVERITY WARNING; ++ z <= ((b1 or b2) and (a2 or a1)) after 1200 ps; ++END; +diff --git a/alliance/src/cells/src/msxlib/oan22_x2.ap b/alliance/src/cells/src/msxlib/oan22_x2.ap +new file mode 100644 +index 0000000..5ba3758 +--- /dev/null ++++ b/alliance/src/cells/src/msxlib/oan22_x2.ap +@@ -0,0 +1,136 @@ ++V ALLIANCE : 6 ++H oan22_x2,P, 9/ 8/2014,100 ++A 0,0,8000,10000 ++R 1000,4000,ref_ref,z_40 ++R 2000,3000,ref_ref,z_30 ++R 2000,4000,ref_ref,z_40 ++R 2000,5000,ref_ref,z_50 ++R 2000,6000,ref_ref,z_60 ++R 2000,7000,ref_ref,z_70 ++R 5000,6000,ref_ref,b1_60 ++R 6000,7000,ref_ref,a1_70 ++R 6000,6000,ref_ref,a2_60 ++R 4000,6000,ref_ref,b1_60 ++R 6000,3000,ref_ref,b2_30 ++R 5000,4000,ref_ref,b2_40 ++R 5000,5000,ref_ref,b2_50 ++R 6000,4000,ref_ref,a2_40 ++R 6000,5000,ref_ref,a2_50 ++R 7000,5000,ref_ref,a1_50 ++R 7000,6000,ref_ref,a1_60 ++R 5000,3000,ref_ref,b2_30 ++R 7000,4000,ref_ref,a2_40 ++R 7000,7000,ref_ref,a1_70 ++R 4000,4000,ref_ref,b1_40 ++R 4000,5000,ref_ref,b1_50 ++R 2000,8000,ref_ref,z_80 ++S 1100,700,1900,700,600,*,RIGHT,PTIE ++S 2600,9400,2600,9700,200,*,DOWN,POLY ++S 3000,3000,3000,7000,400,*,DOWN,ALU1 ++S 3000,7000,5200,7000,400,*,RIGHT,ALU1 ++S 2600,5500,2600,9400,200,1z,DOWN,PTRANS ++S 5200,7000,5200,8100,400,*,UP,ALU1 ++S 2800,4900,3000,4900,600,*,RIGHT,ALU1 ++S 1300,3600,1300,4700,200,*,DOWN,POLY ++S 1300,4700,2800,4700,200,*,LEFT,POLY ++S 3400,3400,3400,3900,200,*,UP,POLY ++S 900,4000,2000,4000,400,*,LEFT,ALU1 ++S 1000,4000,1000,4000,400,z,LEFT,CALU1 ++S 1900,2900,1900,4000,400,*,DOWN,ALU1 ++S 2000,5900,2000,6500,600,*,DOWN,PDIF ++S 2200,5700,2200,9200,400,*,DOWN,PDIF ++S 3800,4000,4000,4000,600,*,RIGHT,ALU1 ++S 3800,4000,3800,5500,200,*,DOWN,POLY ++S 700,700,700,3100,400,*,DOWN,ALU1 ++S 600,1900,600,3400,600,*,UP,NDIF ++S 1700,1900,1700,3400,400,*,UP,NDIF ++S 1300,1700,1300,3600,200,2z,UP,NTRANS ++S 1300,1300,1300,1700,200,*,UP,POLY ++S 2700,2000,7500,2000,400,*,RIGHT,ALU1 ++S 3000,1900,3000,3200,400,*,DOWN,NDIF ++S 3400,1300,3400,1700,200,*,UP,POLY ++S 3400,1700,3400,3400,200,7,UP,NTRANS ++S 4000,1900,4000,3200,1000,*,UP,NDIF ++S 4600,3400,4600,5500,200,*,DOWN,POLY ++S 4600,1300,4600,1700,200,*,UP,POLY ++S 4600,1700,4600,3400,200,8,UP,NTRANS ++S 5200,1900,5200,3200,1000,*,UP,NDIF ++S 5800,1300,5800,1700,200,*,UP,POLY ++S 5800,1700,5800,3400,200,6,UP,NTRANS ++S 6300,600,6300,3200,400,*,UP,NDIF ++S 0,5000,8000,5000,10000,oan22_x2,LEFT,TALU8 ++S 0,2200,8000,2200,5200,*,LEFT,PWELL ++S 0,7600,8000,7600,5600,*,LEFT,NWELL ++S 0,9400,8000,9400,1200,vdd,RIGHT,CALU1 ++S 0,600,8000,600,1200,vss,RIGHT,CALU1 ++S 3100,5700,3100,9200,600,*,DOWN,PDIF ++S 7300,5700,7300,9200,600,*,DOWN,PDIF ++S 6200,5700,6200,9200,600,n1,UP,PDIF ++S 6600,5500,6600,9400,200,1,DOWN,PTRANS ++S 5800,5500,5800,9400,200,2,DOWN,PTRANS ++S 5200,5700,5200,9200,1000,*,UP,PDIF ++S 4200,5700,4200,9200,600,n2,UP,PDIF ++S 4600,5500,4600,9400,200,4,DOWN,PTRANS ++S 3800,5500,3800,9400,200,3,DOWN,PTRANS ++S 6800,1700,6800,3400,200,5,UP,NTRANS ++S 7200,1900,7200,3200,400,*,DOWN,NDIF ++S 7400,2100,7400,2700,600,*,UP,NDIF ++S 6800,1300,6800,1700,200,*,UP,POLY ++S 6600,5000,6600,5500,200,*,DOWN,POLY ++S 3800,9400,3800,9700,200,*,DOWN,POLY ++S 5800,4200,5800,5500,200,*,DOWN,POLY ++S 6800,3400,6800,4700,200,*,UP,POLY ++S 6600,9400,6600,9700,200,*,DOWN,POLY ++S 5800,9400,5800,9700,200,*,DOWN,POLY ++S 4600,9400,4600,9700,200,*,DOWN,POLY ++S 5000,6000,5000,6000,400,b1,LEFT,CALU1 ++S 6000,4000,6000,6100,400,*,UP,ALU1 ++S 5900,4000,5900,6100,400,*,UP,ALU1 ++S 6000,4000,6000,6000,400,a2,DOWN,CALU1 ++S 6000,4000,7100,4000,400,*,RIGHT,ALU1 ++S 7000,4000,7000,4000,400,a2,LEFT,CALU1 ++S 7400,2000,7400,2800,600,*,UP,ALU1 ++S 6000,7000,6000,7000,400,a1,LEFT,CALU1 ++S 6000,3000,6000,3000,400,b2,LEFT,CALU1 ++S 4000,4000,4000,6000,400,b1,UP,CALU1 ++S 4000,6000,5100,6000,400,*,RIGHT,ALU1 ++S 7000,4800,7000,7000,400,*,UP,ALU1 ++S 7000,5000,7000,7000,400,a1,UP,CALU1 ++S 7200,7900,7200,9300,400,*,UP,ALU1 ++S 5000,2900,6100,2900,400,*,RIGHT,ALU1 ++S 5000,3000,6100,3000,400,*,RIGHT,ALU1 ++S 3200,7900,3200,9300,400,*,UP,ALU1 ++S 4000,6100,5100,6100,400,*,RIGHT,ALU1 ++S 6000,7000,7000,7000,600,*,RIGHT,ALU1 ++S 3000,3000,4100,3000,400,*,RIGHT,ALU1 ++S 4000,3900,4000,6000,400,*,UP,ALU1 ++S 5000,3000,5000,5100,400,*,DOWN,ALU1 ++S 5000,3000,5000,5000,400,b2,DOWN,CALU1 ++S 2000,3000,2000,8000,400,z,DOWN,CALU1 ++S 2000,2900,2000,8100,400,*,DOWN,ALU1 ++V 1000,9300,CONT_BODY_N,* ++V 2100,700,CONT_BODY_P,* ++V 1000,700,CONT_BODY_P,* ++V 5200,7200,CONT_DIF_P,zn ++V 5200,8000,CONT_DIF_P,zn ++V 4000,3000,CONT_DIF_N,zn ++V 2800,4900,CONT_POLY,zn ++V 2000,6600,CONT_DIF_P,* ++V 2000,5800,CONT_DIF_P,* ++V 3800,4000,CONT_POLY,* ++V 1900,3300,CONT_DIF_N,* ++V 700,2000,CONT_DIF_N,* ++V 700,3000,CONT_DIF_N,* ++V 2800,2000,CONT_DIF_N,n3 ++V 5200,2000,CONT_DIF_N,n3 ++V 6400,700,CONT_DIF_N,* ++V 3200,8000,CONT_DIF_P,* ++V 7200,8000,CONT_DIF_P,* ++V 7200,9000,CONT_DIF_P,* ++V 3200,9000,CONT_DIF_P,* ++V 7400,2000,CONT_DIF_N,n3 ++V 7400,2800,CONT_DIF_N,n3 ++V 5000,4900,CONT_POLY,* ++V 7000,4900,CONT_POLY,* ++V 6000,4000,CONT_POLY,* ++EOF +diff --git a/alliance/src/cells/src/msxlib/oan22_x2.vbe b/alliance/src/cells/src/msxlib/oan22_x2.vbe +new file mode 100644 +index 0000000..f3d6f6e +--- /dev/null ++++ b/alliance/src/cells/src/msxlib/oan22_x2.vbe +@@ -0,0 +1,44 @@ ++ENTITY oan22_x2 IS ++GENERIC ( ++ CONSTANT area : NATURAL := 8000; ++ CONSTANT cin_b1 : NATURAL := 7; ++ CONSTANT cin_b2 : NATURAL := 7; ++ CONSTANT cin_a2 : NATURAL := 7; ++ CONSTANT cin_a1 : NATURAL := 7; ++ CONSTANT rdown_b1_z : NATURAL := 1220; ++ CONSTANT rdown_b2_z : NATURAL := 1220; ++ CONSTANT rdown_a2_z : NATURAL := 1230; ++ CONSTANT rdown_a1_z : NATURAL := 1230; ++ CONSTANT rup_b1_z : NATURAL := 1520; ++ CONSTANT rup_b2_z : NATURAL := 1520; ++ CONSTANT rup_a2_z : NATURAL := 1520; ++ CONSTANT rup_a1_z : NATURAL := 1520; ++ CONSTANT tphh_a2_z : NATURAL := 97; ++ CONSTANT tpll_b1_z : NATURAL := 122; ++ CONSTANT tphh_a1_z : NATURAL := 109; ++ CONSTANT tphh_b2_z : NATURAL := 89; ++ CONSTANT tpll_a1_z : NATURAL := 143; ++ CONSTANT tpll_b2_z : NATURAL := 112; ++ CONSTANT tphh_b1_z : NATURAL := 101; ++ CONSTANT tpll_a2_z : NATURAL := 134; ++ CONSTANT transistors : NATURAL := 10 ++); ++PORT ( ++ b1 : in BIT; ++ b2 : in BIT; ++ a2 : in BIT; ++ a1 : in BIT; ++ z : out BIT; ++ vdd : in BIT; ++ vss : in BIT ++); ++END oan22_x2; ++ ++ARCHITECTURE behaviour_data_flow OF oan22_x2 IS ++ ++BEGIN ++ ASSERT ((vdd and not (vss)) = '1') ++ REPORT "power supply is missing on oan22_x2" ++ SEVERITY WARNING; ++ z <= ((b1 or b2) and (a2 or a1)) after 1200 ps; ++END; +diff --git a/alliance/src/cells/src/msxlib/or2_x1.ap b/alliance/src/cells/src/msxlib/or2_x1.ap +new file mode 100644 +index 0000000..80412bf +--- /dev/null ++++ b/alliance/src/cells/src/msxlib/or2_x1.ap +@@ -0,0 +1,93 @@ ++V ALLIANCE : 6 ++H or2_x1,P, 9/ 8/2014,100 ++A 0,0,5000,10000 ++R 4000,6000,ref_ref,b_60 ++R 4000,5000,ref_ref,b_50 ++R 3000,5000,ref_ref,a_50 ++R 3000,4000,ref_ref,a_40 ++R 4000,4000,ref_ref,a_40 ++R 1000,6000,ref_ref,z_60 ++R 1000,5000,ref_ref,z_50 ++R 1000,4000,ref_ref,z_40 ++R 1000,3000,ref_ref,z_30 ++R 1000,2000,ref_ref,z_20 ++R 2000,2000,ref_ref,z_20 ++R 1000,7000,ref_ref,z_70 ++R 3000,6000,ref_ref,b_60 ++S 3500,9300,4300,9300,600,*,RIGHT,NTIE ++S 3500,700,4300,700,600,*,RIGHT,PTIE ++S 800,3100,1000,3100,600,*,RIGHT,ALU1 ++S 1000,1900,2100,1900,400,*,RIGHT,ALU1 ++S 1000,2000,2100,2000,400,*,RIGHT,ALU1 ++S 1000,2600,1000,3200,400,*,DOWN,NDIF ++S 1400,2000,1400,2400,200,*,DOWN,POLY ++S 1400,2400,1400,3400,200,2z,DOWN,NTRANS ++S 2600,3400,2600,3900,200,*,UP,POLY ++S 3600,5100,3600,5600,200,*,DOWN,POLY ++S 2000,2000,2000,2000,400,z,LEFT,CALU1 ++S 4000,4000,4000,4000,400,a,LEFT,CALU1 ++S 2600,2700,2600,3400,200,2a,DOWN,NTRANS ++S 3800,2700,3800,3400,200,2b,DOWN,NTRANS ++S 1600,5600,1600,7600,200,1z,UP,PTRANS ++S 2800,5600,2800,8300,200,1a,UP,PTRANS ++S 3600,5600,3600,8300,200,1b,UP,PTRANS ++S 2000,900,2000,3200,600,*,UP,NDIF ++S 4400,700,4400,3100,400,*,DOWN,ALU1 ++S 2000,3000,3300,3000,400,*,LEFT,ALU1 ++S 2800,4400,2800,5600,200,*,UP,POLY ++S 2600,2300,2600,2700,200,*,DOWN,POLY ++S 3800,2300,3800,2700,200,*,DOWN,POLY ++S 4400,2900,4400,3200,600,*,UP,NDIF ++S 3200,2900,3200,3200,1000,*,UP,NDIF ++S 4000,5800,4000,8100,400,*,UP,PDIF ++S 3600,8300,3600,8700,200,*,DOWN,POLY ++S 2800,8300,2800,8700,200,*,DOWN,POLY ++S 1600,7600,1600,8000,200,*,DOWN,POLY ++S 1200,5800,1200,7400,400,*,UP,PDIF ++S 3200,5800,3200,8100,600,n1,DOWN,PDIF ++S 3000,3900,4100,3900,400,*,RIGHT,ALU1 ++S 3000,4000,4100,4000,400,*,RIGHT,ALU1 ++S 1000,5800,1000,6600,600,*,UP,PDIF ++S 0,600,5000,600,1200,vss,RIGHT,CALU1 ++S 0,9400,5000,9400,1200,vdd,RIGHT,CALU1 ++S 0,5000,5000,5000,10000,or2_x1,LEFT,TALU8 ++S 0,2200,5000,2200,5200,*,LEFT,PWELL ++S 0,7600,5000,7600,5600,*,LEFT,NWELL ++S 1000,2000,1000,7000,400,z,DOWN,CALU1 ++S 3800,3400,3800,4800,200,*,UP,POLY ++S 1000,1900,1000,7100,400,*,DOWN,ALU1 ++S 1600,4800,1600,5600,200,*,DOWN,POLY ++S 1400,3400,1400,5200,200,*,UP,POLY ++S 1400,5000,2200,5000,600,*,LEFT,POLY ++S 2600,3800,3000,3800,200,*,RIGHT,POLY ++S 3600,5200,4000,5200,200,*,RIGHT,POLY ++S 3000,4000,3000,5000,400,a,UP,CALU1 ++S 3000,3900,3000,5100,400,*,DOWN,ALU1 ++S 2900,6000,4000,6000,400,*,RIGHT,ALU1 ++S 2900,6100,4000,6100,400,*,RIGHT,ALU1 ++S 3000,6000,3000,6000,400,b,LEFT,CALU1 ++S 4000,5000,4000,6000,400,b,UP,CALU1 ++S 4000,4900,4000,6100,400,*,UP,ALU1 ++S 4200,7300,4200,7900,600,*,DOWN,PDIF ++S 2000,7000,4200,7000,400,*,LEFT,ALU1 ++S 4200,7000,4200,8100,400,*,UP,ALU1 ++S 2000,3000,2000,7000,400,*,UP,ALU1 ++S 2200,7900,2200,9300,400,*,UP,ALU1 ++S 2200,5800,2200,8100,600,n2,DOWN,PDIF ++V 4300,9300,CONT_BODY_N,* ++V 3400,9300,CONT_BODY_N,* ++V 4300,700,CONT_BODY_P,* ++V 3400,700,CONT_BODY_P,* ++V 800,3100,CONT_DIF_N,* ++V 3200,3000,CONT_DIF_N,zn ++V 3000,4000,CONT_POLY,* ++V 4400,3000,CONT_DIF_N,* ++V 1000,6700,CONT_DIF_P,* ++V 1000,5900,CONT_DIF_P,* ++V 4000,5000,CONT_POLY,* ++V 2000,1000,CONT_DIF_N,* ++V 2000,5000,CONT_POLY,zn ++V 4200,8000,CONT_DIF_P,zn ++V 4200,7200,CONT_DIF_P,zn ++V 2200,8000,CONT_DIF_P,* ++EOF +diff --git a/alliance/src/cells/src/msxlib/or2_x1.vbe b/alliance/src/cells/src/msxlib/or2_x1.vbe +new file mode 100644 +index 0000000..2147c77 +--- /dev/null ++++ b/alliance/src/cells/src/msxlib/or2_x1.vbe +@@ -0,0 +1,32 @@ ++ENTITY or2_x1 IS ++GENERIC ( ++ CONSTANT area : NATURAL := 5000; ++ CONSTANT cin_a : NATURAL := 4; ++ CONSTANT cin_b : NATURAL := 4; ++ CONSTANT rdown_a_z : NATURAL := 2300; ++ CONSTANT rdown_b_z : NATURAL := 2300; ++ CONSTANT rup_a_z : NATURAL := 2970; ++ CONSTANT rup_b_z : NATURAL := 2960; ++ CONSTANT tpll_a_z : NATURAL := 102; ++ CONSTANT tphh_b_z : NATURAL := 80; ++ CONSTANT tpll_b_z : NATURAL := 93; ++ CONSTANT tphh_a_z : NATURAL := 93; ++ CONSTANT transistors : NATURAL := 6 ++); ++PORT ( ++ a : in BIT; ++ b : in BIT; ++ z : out BIT; ++ vdd : in BIT; ++ vss : in BIT ++); ++END or2_x1; ++ ++ARCHITECTURE behaviour_data_flow OF or2_x1 IS ++ ++BEGIN ++ ASSERT ((vdd and not (vss)) = '1') ++ REPORT "power supply is missing on or2_x1" ++ SEVERITY WARNING; ++ z <= (a or b) after 1100 ps; ++END; +diff --git a/alliance/src/cells/src/msxlib/or3_x1.ap b/alliance/src/cells/src/msxlib/or3_x1.ap +new file mode 100644 +index 0000000..aeca76b +--- /dev/null ++++ b/alliance/src/cells/src/msxlib/or3_x1.ap +@@ -0,0 +1,106 @@ ++V ALLIANCE : 6 ++H or3_x1,P, 9/ 8/2014,100 ++A 0,0,6000,10000 ++R 4000,3000,ref_ref,c_30 ++R 5000,3000,ref_ref,c_30 ++R 5000,5000,ref_ref,c_50 ++R 5000,4000,ref_ref,c_40 ++R 1000,7000,ref_ref,z_70 ++R 2000,2000,ref_ref,z_20 ++R 1000,2000,ref_ref,z_20 ++R 1000,3000,ref_ref,z_30 ++R 1000,4000,ref_ref,z_40 ++R 1000,5000,ref_ref,z_50 ++R 1000,6000,ref_ref,z_60 ++R 4000,4000,ref_ref,a_40 ++R 3000,4000,ref_ref,a_40 ++R 3000,5000,ref_ref,a_50 ++R 3000,6000,ref_ref,a_60 ++R 4000,5000,ref_ref,b_50 ++R 4000,6000,ref_ref,b_60 ++R 4000,7000,ref_ref,b_70 ++R 3000,7000,ref_ref,b_70 ++S 5400,6900,5400,8000,400,*,DOWN,ALU1 ++S 2000,8000,5400,8000,400,*,LEFT,ALU1 ++S 5400,7100,5400,7700,600,*,UP,PDIF ++S 3000,7000,3000,7000,400,b,LEFT,CALU1 ++S 4000,3000,4000,3000,400,c,LEFT,CALU1 ++S 4000,4000,4000,4000,400,a,LEFT,CALU1 ++S 2000,2000,2000,2000,400,z,LEFT,CALU1 ++S 3600,2400,3600,2900,200,*,UP,POLY ++S 3200,9300,3200,9700,200,*,DOWN,POLY ++S 4000,9300,4000,9700,200,*,DOWN,POLY ++S 4800,9300,4800,9700,200,*,DOWN,POLY ++S 1800,900,1800,2500,600,*,UP,NDIF ++S 3900,2900,5000,2900,400,*,RIGHT,ALU1 ++S 5000,3000,5000,5100,400,*,UP,ALU1 ++S 3900,3000,5000,3000,400,*,RIGHT,ALU1 ++S 5000,3000,5000,5000,400,c,UP,CALU1 ++S 3000,2000,5500,2000,400,*,RIGHT,ALU1 ++S 3000,2000,3000,3000,400,*,DOWN,ALU1 ++S 2000,3000,3000,3000,400,*,LEFT,ALU1 ++S 2800,2800,2800,4500,200,*,UP,POLY ++S 2400,2800,2800,2800,200,*,RIGHT,POLY ++S 3800,2800,3800,4800,200,*,DOWN,POLY ++S 4800,2400,4800,5600,200,*,DOWN,POLY ++S 2400,1300,2400,1700,200,*,DOWN,POLY ++S 3600,1300,3600,1700,200,*,DOWN,POLY ++S 4800,1300,4800,1700,200,*,DOWN,POLY ++S 4200,900,4200,2200,600,*,UP,NDIF ++S 4800,1700,4800,2400,200,2c,DOWN,NTRANS ++S 5400,1900,5400,2200,600,*,UP,NDIF ++S 2400,1700,2400,2400,200,2a,DOWN,NTRANS ++S 3600,1700,3600,2400,200,2b,DOWN,NTRANS ++S 3000,1900,3000,2200,1000,*,UP,NDIF ++S 5200,5800,5200,9100,400,*,UP,PDIF ++S 3200,5600,3200,9300,200,1a,UP,PTRANS ++S 3600,5800,3600,9100,600,n1,DOWN,PDIF ++S 4800,5600,4800,9300,200,1c,UP,PTRANS ++S 4000,5600,4000,9300,200,1b,UP,PTRANS ++S 4400,5800,4400,9100,600,n2,DOWN,PDIF ++S 1200,4400,1600,4400,200,*,RIGHT,POLY ++S 2400,5800,2400,9100,1000,n2,DOWN,PDIF ++S 3200,4400,3200,5600,200,*,UP,POLY ++S 0,9400,6000,9400,1200,vdd,RIGHT,CALU1 ++S 0,5000,6000,5000,10000,or3_x1,LEFT,TALU8 ++S 0,2200,6000,2200,5200,*,LEFT,PWELL ++S 0,7600,6000,7600,5600,*,LEFT,NWELL ++S 1000,2000,1000,7000,400,z,DOWN,CALU1 ++S 2900,7100,4000,7100,400,*,RIGHT,ALU1 ++S 2900,7000,4000,7000,400,*,RIGHT,ALU1 ++S 1000,5800,1000,6600,600,*,UP,PDIF ++S 3000,4000,4100,4000,400,*,RIGHT,ALU1 ++S 3000,3900,4100,3900,400,*,RIGHT,ALU1 ++S 3000,4000,3000,6100,400,*,DOWN,ALU1 ++S 4000,4900,4000,7100,400,*,UP,ALU1 ++S 1000,2000,1000,7100,400,*,DOWN,ALU1 ++S 2000,3000,2000,8000,400,*,UP,ALU1 ++S 1200,5800,1200,7400,400,*,UP,PDIF ++S 1600,7600,1600,8000,200,*,DOWN,POLY ++S 1600,4400,1600,5600,200,*,DOWN,POLY ++S 4000,5000,4000,7000,400,b,UP,CALU1 ++S 3000,4000,3000,6000,400,a,UP,CALU1 ++S 1600,5600,1600,7600,200,1z,UP,PTRANS ++S 0,600,6000,600,1200,vss,RIGHT,CALU1 ++S 800,1900,800,2500,400,*,DOWN,NDIF ++S 1200,1700,1200,2700,200,2z,DOWN,NTRANS ++S 1200,1300,1200,1700,200,*,DOWN,POLY ++S 1200,2700,1200,4400,200,*,UP,POLY ++S 500,2000,2100,2000,400,*,RIGHT,ALU1 ++V 1000,9300,CONT_BODY_N,* ++V 3000,700,CONT_BODY_P,* ++V 5400,7800,CONT_DIF_P,zn ++V 5400,7000,CONT_DIF_P,zn ++V 5000,3000,CONT_POLY,* ++V 4200,1000,CONT_DIF_N,* ++V 5400,2000,CONT_DIF_N,zn ++V 2400,9000,CONT_DIF_P,* ++V 3000,4600,CONT_POLY,* ++V 4000,5000,CONT_POLY,* ++V 1000,5900,CONT_DIF_P,* ++V 1000,6700,CONT_DIF_P,* ++V 2000,4600,CONT_POLY,zn ++V 600,2000,CONT_DIF_N,* ++V 1800,1000,CONT_DIF_N,* ++V 3000,2100,CONT_DIF_N,zn ++EOF +diff --git a/alliance/src/cells/src/msxlib/or3_x1.vbe b/alliance/src/cells/src/msxlib/or3_x1.vbe +new file mode 100644 +index 0000000..4c2892b +--- /dev/null ++++ b/alliance/src/cells/src/msxlib/or3_x1.vbe +@@ -0,0 +1,38 @@ ++ENTITY or3_x1 IS ++GENERIC ( ++ CONSTANT area : NATURAL := 6000; ++ CONSTANT cin_a : NATURAL := 5; ++ CONSTANT cin_b : NATURAL := 5; ++ CONSTANT cin_c : NATURAL := 5; ++ CONSTANT rdown_a_z : NATURAL := 2330; ++ CONSTANT rdown_b_z : NATURAL := 2330; ++ CONSTANT rdown_c_z : NATURAL := 2330; ++ CONSTANT rup_a_z : NATURAL := 2990; ++ CONSTANT rup_b_z : NATURAL := 2970; ++ CONSTANT rup_c_z : NATURAL := 2960; ++ CONSTANT tphh_c_z : NATURAL := 93; ++ CONSTANT tpll_a_z : NATURAL := 143; ++ CONSTANT tphh_b_z : NATURAL := 112; ++ CONSTANT tpll_b_z : NATURAL := 134; ++ CONSTANT tphh_a_z : NATURAL := 125; ++ CONSTANT tpll_c_z : NATURAL := 111; ++ CONSTANT transistors : NATURAL := 8 ++); ++PORT ( ++ a : in BIT; ++ b : in BIT; ++ c : in BIT; ++ z : out BIT; ++ vdd : in BIT; ++ vss : in BIT ++); ++END or3_x1; ++ ++ARCHITECTURE behaviour_data_flow OF or3_x1 IS ++ ++BEGIN ++ ASSERT ((vdd and not (vss)) = '1') ++ REPORT "power supply is missing on or3_x1" ++ SEVERITY WARNING; ++ z <= ((a or b) or c) after 1100 ps; ++END; +diff --git a/alliance/src/cells/src/msxlib/or4_x1.ap b/alliance/src/cells/src/msxlib/or4_x1.ap +new file mode 100644 +index 0000000..4748a86 +--- /dev/null ++++ b/alliance/src/cells/src/msxlib/or4_x1.ap +@@ -0,0 +1,124 @@ ++V ALLIANCE : 6 ++H or4_x1,P, 9/ 8/2014,100 ++A 0,0,7000,10000 ++R 5000,7000,ref_ref,d_70 ++R 6000,7000,ref_ref,d_70 ++R 6000,6000,ref_ref,d_60 ++R 6000,4000,ref_ref,c_40 ++R 3000,7000,ref_ref,b_70 ++R 5000,5000,ref_ref,c_50 ++R 5000,4000,ref_ref,c_40 ++R 1000,7000,ref_ref,z_70 ++R 2000,2000,ref_ref,z_20 ++R 1000,2000,ref_ref,z_20 ++R 1000,3000,ref_ref,z_30 ++R 1000,4000,ref_ref,z_40 ++R 1000,5000,ref_ref,z_50 ++R 1000,6000,ref_ref,z_60 ++R 4000,4000,ref_ref,a_40 ++R 3000,4000,ref_ref,a_40 ++R 3000,5000,ref_ref,a_50 ++R 3000,6000,ref_ref,a_60 ++R 4000,5000,ref_ref,b_50 ++R 4000,6000,ref_ref,b_60 ++R 4000,7000,ref_ref,b_70 ++R 6000,5000,ref_ref,d_50 ++R 5000,6000,ref_ref,c_60 ++S 5100,700,5900,700,600,*,RIGHT,PTIE ++S 5600,9400,5600,9700,200,*,DOWN,POLY ++S 4800,9400,4800,9700,200,*,DOWN,POLY ++S 4000,9400,4000,9700,200,*,DOWN,POLY ++S 3200,9400,3200,9700,200,*,DOWN,POLY ++S 3600,3300,3600,3800,200,*,UP,POLY ++S 4800,3900,4800,5500,200,*,DOWN,POLY ++S 3200,4400,3200,5500,200,*,UP,POLY ++S 3800,3700,3800,4700,200,*,DOWN,POLY ++S 500,3000,1000,3000,400,*,RIGHT,ALU1 ++S 0,9400,7000,9400,1200,vdd,RIGHT,CALU1 ++S 0,5000,7000,5000,10000,or4_x1,LEFT,TALU8 ++S 0,2200,7000,2200,5200,*,LEFT,PWELL ++S 0,7600,7000,7600,5600,*,LEFT,NWELL ++S 0,600,7000,600,1200,vss,RIGHT,CALU1 ++S 6400,700,6400,3100,400,*,DOWN,ALU1 ++S 6000,4800,6000,7000,400,*,DOWN,ALU1 ++S 5000,4000,5000,6100,400,*,UP,ALU1 ++S 4900,7100,6000,7100,400,*,LEFT,ALU1 ++S 4900,7000,6000,7000,400,*,LEFT,ALU1 ++S 6000,5000,6000,7000,400,d,DOWN,CALU1 ++S 4600,3300,4600,3900,200,*,UP,POLY ++S 5000,3900,6100,3900,400,*,RIGHT,ALU1 ++S 5600,5000,5600,5500,200,*,DOWN,POLY ++S 5000,4000,6100,4000,400,*,RIGHT,ALU1 ++S 2900,7000,4000,7000,400,*,RIGHT,ALU1 ++S 2900,7100,4000,7100,400,*,RIGHT,ALU1 ++S 2000,3000,5300,3000,400,*,LEFT,ALU1 ++S 4000,700,4000,1900,400,*,DOWN,ALU1 ++S 5800,3300,5800,4700,200,*,UP,POLY ++S 5800,2300,5800,2700,200,*,DOWN,POLY ++S 5800,2700,5800,3300,200,2d,DOWN,NTRANS ++S 4600,2700,4600,3300,200,2c,DOWN,NTRANS ++S 4600,2300,4600,2700,200,*,DOWN,POLY ++S 4100,1700,4100,3100,400,*,UP,NDIF ++S 3600,2400,3600,2700,200,*,DOWN,POLY ++S 2400,3700,2800,3700,200,*,RIGHT,POLY ++S 2800,3700,2800,4500,200,*,UP,POLY ++S 2400,2300,2400,2700,200,*,DOWN,POLY ++S 3600,2700,3600,3300,200,2b,DOWN,NTRANS ++S 2400,2700,2400,3300,200,2a,DOWN,NTRANS ++S 1800,900,1800,3100,600,*,UP,NDIF ++S 1600,4400,1600,5500,200,*,DOWN,POLY ++S 1200,4400,1600,4400,200,*,RIGHT,POLY ++S 1200,3300,1200,4400,200,*,UP,POLY ++S 1200,1900,1200,2300,200,*,DOWN,POLY ++S 1200,2300,1200,3300,200,2z,DOWN,NTRANS ++S 800,2500,800,3100,400,*,DOWN,NDIF ++S 1000,1900,2100,1900,400,*,RIGHT,ALU1 ++S 1000,2000,2100,2000,400,*,RIGHT,ALU1 ++S 1000,2000,1000,7000,400,z,DOWN,CALU1 ++S 3000,4000,4100,4000,400,*,RIGHT,ALU1 ++S 3000,3900,4100,3900,400,*,RIGHT,ALU1 ++S 3000,4000,3000,6100,400,*,DOWN,ALU1 ++S 1000,2000,1000,7100,400,*,DOWN,ALU1 ++S 2000,3000,2000,8000,400,*,UP,ALU1 ++S 4000,5000,4000,7000,400,b,UP,CALU1 ++S 3000,4000,3000,6000,400,a,UP,CALU1 ++S 2000,8000,6300,8000,400,*,LEFT,ALU1 ++S 4000,4800,4000,7100,400,*,UP,ALU1 ++S 1000,5700,1000,6500,600,*,UP,PDIF ++S 1200,5700,1200,7300,400,*,UP,PDIF ++S 1600,5500,1600,7500,200,1z,UP,PTRANS ++S 1600,7500,1600,7900,200,*,DOWN,POLY ++S 2400,5700,2400,9200,1000,n2,DOWN,PDIF ++S 3200,5500,3200,9400,200,1a,UP,PTRANS ++S 3600,5700,3600,9200,600,n1,DOWN,PDIF ++S 4000,5500,4000,9400,200,1b,UP,PTRANS ++S 4400,5700,4400,9200,600,n2,DOWN,PDIF ++S 4800,5500,4800,9400,200,1c,UP,PTRANS ++S 5600,5500,5600,9400,200,1d,UP,PTRANS ++S 5200,5700,5200,9200,600,n2,DOWN,PDIF ++S 6000,5700,6000,9200,400,n3,UP,PDIF ++S 5000,4000,5000,6000,400,c,UP,CALU1 ++S 4000,4000,4000,4000,400,a,LEFT,CALU1 ++S 5000,7000,5000,7000,400,d,LEFT,CALU1 ++S 6000,4000,6000,4000,400,c,LEFT,CALU1 ++S 2000,2000,2000,2000,400,z,LEFT,CALU1 ++S 3000,7000,3000,7000,400,b,LEFT,CALU1 ++V 1000,9300,CONT_BODY_N,* ++V 6000,700,CONT_BODY_P,* ++V 5000,700,CONT_BODY_P,* ++V 6400,3000,CONT_DIF_N,* ++V 5000,4000,CONT_POLY,* ++V 5200,3000,CONT_DIF_N,zn ++V 4000,1800,CONT_DIF_N,* ++V 3000,3000,CONT_DIF_N,zn ++V 1800,1000,CONT_DIF_N,* ++V 600,3000,CONT_DIF_N,* ++V 2400,9000,CONT_DIF_P,* ++V 3000,4600,CONT_POLY,* ++V 1000,6700,CONT_DIF_P,* ++V 2000,4600,CONT_POLY,zn ++V 6200,8000,CONT_DIF_P,zn ++V 4000,4900,CONT_POLY,* ++V 1000,5800,CONT_DIF_P,* ++V 6000,4900,CONT_POLY,* ++EOF +diff --git a/alliance/src/cells/src/msxlib/or4_x1.vbe b/alliance/src/cells/src/msxlib/or4_x1.vbe +new file mode 100644 +index 0000000..7c861e3 +--- /dev/null ++++ b/alliance/src/cells/src/msxlib/or4_x1.vbe +@@ -0,0 +1,44 @@ ++ENTITY or4_x1 IS ++GENERIC ( ++ CONSTANT area : NATURAL := 8000; ++ CONSTANT cin_b : NATURAL := 5; ++ CONSTANT cin_c : NATURAL := 5; ++ CONSTANT cin_a : NATURAL := 5; ++ CONSTANT cin_d : NATURAL := 5; ++ CONSTANT rdown_b_z : NATURAL := 2400; ++ CONSTANT rdown_c_z : NATURAL := 2400; ++ CONSTANT rdown_a_z : NATURAL := 2400; ++ CONSTANT rdown_d_z : NATURAL := 2400; ++ CONSTANT rup_b_z : NATURAL := 2990; ++ CONSTANT rup_c_z : NATURAL := 2970; ++ CONSTANT rup_a_z : NATURAL := 3020; ++ CONSTANT rup_d_z : NATURAL := 2970; ++ CONSTANT tphh_d_z : NATURAL := 103; ++ CONSTANT tphh_c_z : NATURAL := 127; ++ CONSTANT tphh_b_z : NATURAL := 145; ++ CONSTANT tpll_a_z : NATURAL := 191; ++ CONSTANT tphh_a_z : NATURAL := 157; ++ CONSTANT tpll_b_z : NATURAL := 181; ++ CONSTANT tpll_d_z : NATURAL := 125; ++ CONSTANT tpll_c_z : NATURAL := 159; ++ CONSTANT transistors : NATURAL := 10 ++); ++PORT ( ++ b : in BIT; ++ c : in BIT; ++ a : in BIT; ++ d : in BIT; ++ z : out BIT; ++ vdd : in BIT; ++ vss : in BIT ++); ++END or4_x1; ++ ++ARCHITECTURE behaviour_data_flow OF or4_x1 IS ++ ++BEGIN ++ ASSERT ((vdd and not (vss)) = '1') ++ REPORT "power supply is missing on or4_x1" ++ SEVERITY WARNING; ++ z <= (((b or c) or a) or d) after 1200 ps; ++END; +diff --git a/alliance/src/cells/src/msxlib/powmid_x0.ap b/alliance/src/cells/src/msxlib/powmid_x0.ap +new file mode 100644 +index 0000000..ce2c8fd +--- /dev/null ++++ b/alliance/src/cells/src/msxlib/powmid_x0.ap +@@ -0,0 +1,23 @@ ++V ALLIANCE : 6 ++H powmid_x0,P, 4/ 1/2008,100 ++A 0,0,7000,10000 ++S 0,7600,7000,7600,5600,*,LEFT,NWELL ++S 0,2200,7000,2200,5200,*,LEFT,PWELL ++S 0,5000,7000,5000,10000,powmid_x0,LEFT,TALU8 ++S 1000,600,6000,600,1200,vss,RIGHT,CALU2 ++S 900,500,6100,500,1400,*,RIGHT,ALU2 ++S 0,500,7000,500,1400,*,RIGHT,ALU1 ++S 900,9500,6100,9500,1400,*,RIGHT,ALU2 ++S 1000,9400,6000,9400,1200,vdd,RIGHT,CALU2 ++S 0,9500,7000,9500,1400,*,RIGHT,ALU1 ++S 5000,0,5000,10000,2400,vss,DOWN,CALU3 ++S 2000,0,2000,10000,2400,vdd,DOWN,CALU3 ++S 0,9400,7000,9400,1200,vdd,RIGHT,CALU1 ++S 0,600,7000,600,1200,vss,RIGHT,CALU1 ++S 5000,0,5000,10000,2400,*,UP,ALU3 ++S 2000,0,2000,10000,2400,*,UP,ALU3 ++B 2000,500,2300,1200,CONT_VIA,* ++B 5000,500,2300,1200,CONT_VIA2,* ++B 5000,9500,2300,1200,CONT_VIA,* ++B 2000,9500,2300,1200,CONT_VIA2,* ++EOF +diff --git a/alliance/src/cells/src/msxlib/powmid_x0.vbe b/alliance/src/cells/src/msxlib/powmid_x0.vbe +new file mode 100644 +index 0000000..3d677ef +--- /dev/null ++++ b/alliance/src/cells/src/msxlib/powmid_x0.vbe +@@ -0,0 +1,18 @@ ++ENTITY powmid_x0 IS ++GENERIC ( ++ CONSTANT area : NATURAL := 7000; ++ CONSTANT transistors : NATURAL := 0 ++); ++PORT ( ++ vdd : in BIT; ++ vss : in BIT ++); ++END powmid_x0; ++ ++ARCHITECTURE behaviour_data_flow OF powmid_x0 IS ++ ++BEGIN ++ ASSERT (vdd and not (vss)) ++ REPORT "power supply is missing on powmid_x0" ++ SEVERITY WARNING; ++END; +diff --git a/alliance/src/cells/src/msxlib/rowend_x0.ap b/alliance/src/cells/src/msxlib/rowend_x0.ap +new file mode 100644 +index 0000000..8ebdfe4 +--- /dev/null ++++ b/alliance/src/cells/src/msxlib/rowend_x0.ap +@@ -0,0 +1,9 @@ ++V ALLIANCE : 6 ++H rowend_x0,P,17/ 6/2004,100 ++A 0,0,1000,10000 ++S 0,9400,1000,9400,1200,vdd,RIGHT,CALU1 ++S 0,600,1000,600,1200,vss,RIGHT,CALU1 ++S 0,7600,1000,7600,5600,*,LEFT,NWELL ++S 0,2200,1000,2200,5200,*,LEFT,PWELL ++S 0,5000,1000,5000,10000,rowend_x0,LEFT,TALU8 ++EOF +diff --git a/alliance/src/cells/src/msxlib/rowend_x0.vbe b/alliance/src/cells/src/msxlib/rowend_x0.vbe +new file mode 100644 +index 0000000..bb2015f +--- /dev/null ++++ b/alliance/src/cells/src/msxlib/rowend_x0.vbe +@@ -0,0 +1,18 @@ ++ENTITY rowend_x0 IS ++GENERIC ( ++ CONSTANT area : NATURAL := 1000; ++ CONSTANT transistors : NATURAL := 0 ++); ++PORT ( ++ vdd : in BIT; ++ vss : in BIT ++); ++END rowend_x0; ++ ++ARCHITECTURE behaviour_data_flow OF rowend_x0 IS ++ ++BEGIN ++ ASSERT (vdd and not (vss)) ++ REPORT "power supply is missing on rowend_x0" ++ SEVERITY WARNING; ++END; +diff --git a/alliance/src/cells/src/msxlib/sff1_x4.ap b/alliance/src/cells/src/msxlib/sff1_x4.ap +new file mode 100644 +index 0000000..7f03573 +--- /dev/null ++++ b/alliance/src/cells/src/msxlib/sff1_x4.ap +@@ -0,0 +1,234 @@ ++V ALLIANCE : 6 ++H sff1_x4,P,14/ 8/2014,100 ++A 0,0,18000,10000 ++R 16000,4000,ref_ref,q_40 ++R 2000,8000,ref_ref,ck_80 ++R 2000,7000,ref_ref,ck_70 ++R 2000,6000,ref_ref,ck_60 ++R 2000,5000,ref_ref,ck_50 ++R 2000,4000,ref_ref,ck_40 ++R 2000,3000,ref_ref,ck_30 ++R 2000,2000,ref_ref,ck_20 ++R 5000,7000,ref_ref,i_70 ++R 5000,6000,ref_ref,i_60 ++R 5000,5000,ref_ref,i_50 ++R 5000,4000,ref_ref,i_40 ++R 5000,3000,ref_ref,i_30 ++R 6000,2000,ref_ref,i_20 ++R 16000,8000,ref_ref,q_80 ++R 16000,7000,ref_ref,q_70 ++R 16000,6000,ref_ref,q_60 ++R 16000,5000,ref_ref,q_50 ++R 16000,3000,ref_ref,q_30 ++R 16000,2000,ref_ref,q_20 ++R 6000,8000,ref_ref,i_80 ++R 15000,5000,ref_ref,q_50 ++R 15000,3000,ref_ref,q_30 ++S 9600,7500,9600,9400,200,*,DOWN,PTRANS ++S 10000,7700,10000,9200,600,*,DOWN,PDIF ++S 12800,700,13600,700,600,*,RIGHT,PTIE ++S 6800,700,7600,700,600,*,RIGHT,PTIE ++S 3200,700,4000,700,600,*,RIGHT,PTIE ++S 14600,4000,16800,4000,600,sff_s,RIGHT,POLY ++S 13800,4000,14900,4000,400,*,RIGHT,ALU1 ++S 14400,4800,14400,7200,200,*,UP,POLY ++S 4100,2000,4100,8000,400,*,DOWN,ALU1 ++S 5100,8000,6100,8000,400,*,RIGHT,ALU1 ++S 5100,2000,6100,2000,400,*,RIGHT,ALU1 ++S 5100,2000,5100,8000,400,*,DOWN,ALU1 ++S 600,6900,600,8100,400,*,DOWN,ALU1 ++S 3000,1900,3000,7100,400,*,DOWN,ALU1 ++S 9900,7000,11400,7000,400,*,LEFT,ALU1 ++S 11400,1900,11400,8100,400,y,DOWN,ALU1 ++S 14700,3000,16200,3000,400,*,RIGHT,ALU1 ++S 14700,5000,16200,5000,400,*,RIGHT,ALU1 ++S 15000,900,15000,2100,400,*,DOWN,ALU1 ++S 17400,900,17400,2100,400,*,DOWN,ALU1 ++S 15000,5900,15000,9100,400,*,DOWN,ALU1 ++S 17400,5900,17400,9100,400,*,DOWN,ALU1 ++S 9000,3000,10500,3000,400,*,LEFT,ALU1 ++S 7700,2000,9000,2000,400,*,RIGHT,ALU1 ++S 9900,2000,11400,2000,400,*,RIGHT,ALU1 ++S 12600,4000,12600,7000,400,*,DOWN,ALU1 ++S 9000,6000,10500,6000,400,*,RIGHT,ALU1 ++S 0,9400,18000,9400,1200,vdd,RIGHT,CALU1 ++S 0,600,18000,600,1200,vss,RIGHT,CALU1 ++S 13200,2800,13200,5000,200,*,DOWN,POLY ++S 15600,2800,15600,5200,200,*,DOWN,POLY ++S 14400,3000,15000,3000,600,*,RIGHT,POLY ++S 14400,5000,15000,5000,600,*,RIGHT,POLY ++S 16800,2800,16800,5200,200,*,DOWN,POLY ++S 12000,2800,12000,4000,200,*,DOWN,POLY ++S 10800,1800,10800,3000,200,*,UP,POLY ++S 10800,6000,10800,7200,200,*,DOWN,POLY ++S 12000,5000,12000,7200,200,*,DOWN,POLY ++S 8400,2800,8400,4000,200,*,DOWN,POLY ++S 11200,7700,11200,9200,600,*,DOWN,PDIF ++S 10800,7500,10800,9400,200,*,UP,PTRANS ++S 16200,5700,16200,9200,600,*,DOWN,PDIF ++S 16800,5500,16800,9400,200,*,DOWN,PTRANS ++S 17400,5700,17400,9200,600,*,DOWN,PDIF ++S 15600,5500,15600,9400,200,*,DOWN,PTRANS ++S 15000,5700,15000,9200,600,*,DOWN,PDIF ++S 6000,7500,6000,9400,200,*,DOWN,PTRANS ++S 10800,600,10800,1500,200,*,UP,NTRANS ++S 11400,800,11400,1300,600,*,DOWN,NDIF ++S 11400,800,11400,2300,600,*,DOWN,NDIF ++S 16200,800,16200,2300,600,*,DOWN,NDIF ++S 16800,600,16800,2500,200,*,UP,NTRANS ++S 17400,800,17400,2300,600,*,DOWN,NDIF ++S 15600,600,15600,2500,200,*,UP,NTRANS ++S 9000,800,9000,2300,600,*,DOWN,NDIF ++S 0,5000,18000,5000,10000,sff1_x4,RIGHT,TALU8 ++S 0,2200,18000,2200,5200,*,RIGHT,PWELL ++S 0,7600,18000,7600,5600,*,RIGHT,NWELL ++S 1200,6600,1200,8600,200,*,DOWN,PTRANS ++S 600,6800,600,8400,600,*,UP,PDIF ++S 1800,6800,1800,9100,600,*,UP,PDIF ++S 7000,2900,7000,5100,400,*,DOWN,ALU1 ++S 1200,6000,1800,6000,600,*,RIGHT,POLY ++S 12000,4000,12600,4000,600,*,RIGHT,POLY ++S 7800,4000,8400,4000,600,*,RIGHT,POLY ++S 10200,6000,10800,6000,600,*,RIGHT,POLY ++S 12600,7000,13200,7000,600,*,RIGHT,POLY ++S 9600,7000,10200,7000,600,*,RIGHT,POLY ++S 10200,3000,10800,3000,600,*,RIGHT,POLY ++S 9600,2000,10200,2000,600,*,RIGHT,POLY ++S 4000,6000,6000,6000,200,*,RIGHT,POLY ++S 3000,1700,3000,2300,600,*,DOWN,NDIF ++S 2400,1500,2400,2500,200,*,UP,NTRANS ++S 600,1900,600,7100,400,*,DOWN,ALU1 ++S 2400,2800,2400,6200,200,*,DOWN,POLY ++S 1200,3000,1800,3000,600,*,RIGHT,POLY ++S 600,5000,13200,5000,200,nckr,RIGHT,POLY ++S 3200,4000,12000,4000,200,ckr,RIGHT,POLY ++S 6900,6000,8000,6000,400,*,RIGHT,ALU1 ++S 7800,6800,7800,8400,600,*,UP,PDIF ++S 8400,5000,8400,6200,200,*,DOWN,POLY ++S 8000,3900,8000,6000,400,*,UP,ALU1 ++S 9000,6700,9000,9200,600,*,UP,PDIF ++S 6000,6200,6000,7200,200,*,UP,POLY ++S 6000,2900,6000,6100,400,u,DOWN,ALU1 ++S 7700,7000,9000,7000,400,*,RIGHT,ALU1 ++S 13800,2000,13800,8000,400,*,DOWN,ALU1 ++S 9000,2000,9000,7000,400,sff_m,DOWN,ALU1 ++S 6600,6800,6600,9200,600,*,UP,PDIF ++S 7200,6600,7200,8600,200,*,DOWN,PTRANS ++S 8400,1500,8400,2500,200,*,UP,NTRANS ++S 12000,1500,12000,2500,200,*,UP,NTRANS ++S 12000,7500,12000,9400,200,*,DOWN,PTRANS ++S 14400,7500,14400,9400,200,*,DOWN,PTRANS ++S 13200,1500,13200,2500,200,*,UP,NTRANS ++S 12600,1700,12600,2300,600,*,DOWN,NDIF ++S 12500,2000,13800,2000,400,*,RIGHT,ALU1 ++S 12500,8000,13800,8000,400,*,RIGHT,ALU1 ++S 16000,2000,16000,8000,400,q,DOWN,CALU1 ++S 2000,2000,2000,8000,400,ck,DOWN,CALU1 ++S 2000,1900,2000,8100,400,*,DOWN,ALU1 ++S 1500,6000,2000,6000,400,*,RIGHT,ALU1 ++S 1500,3000,2000,3000,400,*,RIGHT,ALU1 ++S 5000,3000,5000,7000,400,i,DOWN,CALU1 ++S 6000,8000,6000,8000,400,i,LEFT,CALU1 ++S 6000,2000,6000,2000,400,i,LEFT,CALU1 ++S 16000,1900,16000,8100,400,*,DOWN,ALU1 ++S 5000,2900,5000,7100,400,*,DOWN,ALU1 ++S 4100,8000,4300,8000,400,*,RIGHT,ALU1 ++S 4100,2000,4300,2000,400,*,RIGHT,ALU1 ++S 3900,6000,4100,6000,400,*,RIGHT,ALU1 ++S 3100,4000,3300,4000,400,*,RIGHT,ALU1 ++S 16100,8000,16300,8000,400,*,RIGHT,ALU1 ++S 16100,7000,16300,7000,400,*,RIGHT,ALU1 ++S 16100,6000,16300,6000,400,*,RIGHT,ALU1 ++S 16100,2000,16300,2000,400,*,RIGHT,ALU1 ++S 12700,7000,12900,7000,400,*,RIGHT,ALU1 ++S 12300,4000,12500,4000,400,*,RIGHT,ALU1 ++S 15000,5000,15000,5000,400,q,LEFT,CALU1 ++S 15000,3000,15000,3000,400,q,LEFT,CALU1 ++S 2400,6600,2400,8600,200,*,DOWN,PTRANS ++S 3000,6800,3000,8400,600,*,UP,PDIF ++S 8400,6600,8400,8600,200,*,DOWN,PTRANS ++S 14400,1500,14400,2500,200,*,UP,NTRANS ++S 15000,800,15000,2300,600,*,DOWN,NDIF ++S 13800,1700,13800,2300,600,*,DOWN,NDIF ++S 9600,600,9600,1500,200,*,UP,NTRANS ++S 10200,800,10200,1300,600,*,DOWN,NDIF ++S 1800,1000,1800,2300,600,*,DOWN,NDIF ++S 1200,1500,1200,2500,200,*,UP,NTRANS ++S 600,1700,600,2300,600,*,DOWN,NDIF ++S 4800,7500,4800,9400,200,*,DOWN,PTRANS ++S 5400,7700,5400,9200,600,*,UP,PDIF ++S 4200,7700,4200,9200,600,*,UP,PDIF ++S 13200,7500,13200,9400,200,*,DOWN,PTRANS ++S 12600,7700,12600,9200,600,*,DOWN,PDIF ++S 13800,7700,13800,9200,600,*,UP,PDIF ++S 7200,1500,7200,2500,200,*,UP,NTRANS ++S 7800,1700,7800,2300,600,*,DOWN,NDIF ++S 6600,1700,6600,2300,600,*,DOWN,NDIF ++S 6000,1500,6000,2500,200,*,UP,NTRANS ++S 5400,900,5400,2300,600,*,DOWN,NDIF ++S 4800,1500,4800,2500,200,*,UP,NTRANS ++S 4200,1700,4200,2300,600,*,DOWN,NDIF ++V 13800,700,CONT_BODY_P,* ++V 12600,700,CONT_BODY_P,* ++V 7800,700,CONT_BODY_P,* ++V 6600,700,CONT_BODY_P,* ++V 4200,700,CONT_BODY_P,* ++V 3000,700,CONT_BODY_P,* ++V 14800,4000,CONT_POLY,* ++V 600,8000,CONT_DIF_P,* ++V 3000,7000,CONT_DIF_P,* ++V 10000,7000,CONT_POLY,* ++V 14800,5000,CONT_POLY,* ++V 14800,3000,CONT_POLY,* ++V 10400,3000,CONT_POLY,* ++V 12400,4000,CONT_POLY,* ++V 10400,6000,CONT_POLY,* ++V 8000,4000,CONT_POLY,* ++V 10000,2000,CONT_POLY,* ++V 12800,7000,CONT_POLY,* ++V 12600,8000,CONT_DIF_P,* ++V 10200,9000,CONT_DIF_P,* ++V 11400,8000,CONT_DIF_P,* ++V 17400,6000,CONT_DIF_P,* ++V 16200,6000,CONT_DIF_P,* ++V 15000,6000,CONT_DIF_P,* ++V 15000,7000,CONT_DIF_P,* ++V 15000,8000,CONT_DIF_P,* ++V 17400,9000,CONT_DIF_P,* ++V 15000,9000,CONT_DIF_P,* ++V 17400,8000,CONT_DIF_P,* ++V 17400,7000,CONT_DIF_P,* ++V 5400,9000,CONT_DIF_P,* ++V 12600,2000,CONT_DIF_N,* ++V 10200,1000,CONT_DIF_N,* ++V 7800,2000,CONT_DIF_N,* ++V 11400,2000,CONT_DIF_N,* ++V 17400,1000,CONT_DIF_N,* ++V 15000,1000,CONT_DIF_N,* ++V 17400,2000,CONT_DIF_N,* ++V 15000,2000,CONT_DIF_N,* ++V 16200,2000,CONT_DIF_N,* ++V 5400,1000,CONT_DIF_N,* ++V 4200,2000,CONT_DIF_N,* ++V 1800,1000,CONT_DIF_N,* ++V 600,7000,CONT_DIF_P,* ++V 1800,9000,CONT_DIF_P,* ++V 1600,6000,CONT_POLY,* ++V 600,5000,CONT_POLY,* ++V 3200,4000,CONT_POLY,* ++V 4000,6000,CONT_POLY,* ++V 5000,7000,CONT_POLY,* ++V 5000,3000,CONT_POLY,* ++V 6000,3000,CONT_POLY,* ++V 6000,6000,CONT_POLY,* ++V 7000,5000,CONT_POLY,* ++V 7000,3000,CONT_POLY,* ++V 600,2000,CONT_DIF_N,* ++V 3000,2000,CONT_DIF_N,* ++V 1600,3000,CONT_POLY,* ++V 16200,8000,CONT_DIF_P,* ++V 16200,7000,CONT_DIF_P,* ++V 4200,8000,CONT_DIF_P,* ++V 7000,6000,CONT_POLY,* ++V 7800,7000,CONT_DIF_P,* ++EOF +diff --git a/alliance/src/cells/src/msxlib/sff1_x4.vbe b/alliance/src/cells/src/msxlib/sff1_x4.vbe +new file mode 100644 +index 0000000..4756bfd +--- /dev/null ++++ b/alliance/src/cells/src/msxlib/sff1_x4.vbe +@@ -0,0 +1,39 @@ ++ENTITY sff1_x4 IS ++GENERIC ( ++ CONSTANT area : NATURAL := 4500; ++ CONSTANT cin_ck : NATURAL := 8; ++ CONSTANT cin_i : NATURAL := 8; ++ CONSTANT rdown_ck_q : NATURAL := 800; ++ CONSTANT rup_ck_q : NATURAL := 890; ++ CONSTANT taf_ck_q : NATURAL := 500; ++ CONSTANT tar_ck_q : NATURAL := 500; ++ CONSTANT thf_i_ck : NATURAL := 0; ++ CONSTANT thr_i_ck : NATURAL := 0; ++ CONSTANT tsf_i_ck : NATURAL := 585; ++ CONSTANT tsr_i_ck : NATURAL := 476; ++ CONSTANT transistors : NATURAL := 26 ++); ++PORT ( ++ ck : in BIT; ++ i : in BIT; ++ q : out BIT; ++ vdd : in BIT; ++ vss : in BIT ++); ++END sff1_x4; ++ ++ARCHITECTURE VBE OF sff1_x4 IS ++ SIGNAL sff_m : REG_BIT REGISTER; ++ ++BEGIN ++ ASSERT (vdd and not (vss)) ++ REPORT "power supply is missing on sff1_x4" ++ SEVERITY WARNING; ++ ++ label0 : BLOCK ((ck and not (ck'STABLE)) = '1') ++ BEGIN ++ sff_m <= GUARDED i; ++ END BLOCK label0; ++ ++ q <= sff_m after 1700 ps; ++END; +diff --git a/alliance/src/cells/src/msxlib/sff2_x4.ap b/alliance/src/cells/src/msxlib/sff2_x4.ap +new file mode 100644 +index 0000000..1cc235b +--- /dev/null ++++ b/alliance/src/cells/src/msxlib/sff2_x4.ap +@@ -0,0 +1,276 @@ ++V ALLIANCE : 6 ++H sff2_x4,P,14/ 8/2014,100 ++A 0,0,24000,10000 ++R 9000,2000,ref_ref,ck_20 ++R 9000,7000,ref_ref,ck_70 ++R 9000,6000,ref_ref,ck_60 ++R 9000,5000,ref_ref,ck_50 ++R 9000,4000,ref_ref,ck_40 ++R 9000,3000,ref_ref,ck_30 ++R 2000,3000,ref_ref,i0_30 ++R 2000,4000,ref_ref,i0_40 ++R 2000,5000,ref_ref,i0_50 ++R 2000,7000,ref_ref,i0_70 ++R 2000,6000,ref_ref,i0_60 ++R 2000,8000,ref_ref,i0_80 ++R 6000,2000,ref_ref,i1_20 ++R 6000,3000,ref_ref,i1_30 ++R 6000,4000,ref_ref,i1_40 ++R 6000,5000,ref_ref,i1_50 ++R 6000,6000,ref_ref,i1_60 ++R 6000,7000,ref_ref,i1_70 ++R 3000,5000,ref_ref,cmd_50 ++R 3000,6000,ref_ref,cmd_60 ++R 3000,7000,ref_ref,cmd_70 ++R 3000,8000,ref_ref,cmd_80 ++R 22000,2000,ref_ref,q_20 ++R 22000,3000,ref_ref,q_30 ++R 22000,5000,ref_ref,q_50 ++R 22000,6000,ref_ref,q_60 ++R 22000,7000,ref_ref,q_70 ++R 22000,8000,ref_ref,q_80 ++R 22000,4000,ref_ref,q_40 ++R 21000,5000,ref_ref,q_50 ++R 21000,3000,ref_ref,q_30 ++S 3200,9300,4800,9300,600,*,RIGHT,NTIE ++S 18800,700,19600,700,600,*,RIGHT,PTIE ++S 12800,700,13600,700,600,*,RIGHT,PTIE ++S 3200,700,4800,700,600,*,RIGHT,PTIE ++S 22000,1900,22000,8100,400,*,DOWN,ALU1 ++S 20400,1500,20400,2400,200,*,UP,NTRANS ++S 19200,1500,19200,2500,200,*,UP,NTRANS ++S 20400,7500,20400,9400,200,*,DOWN,PTRANS ++S 19200,7600,19200,9400,200,*,DOWN,PTRANS ++S 18000,7500,18000,9400,200,*,DOWN,PTRANS ++S 18000,1500,18000,2500,200,*,UP,NTRANS ++S 15600,600,15600,1400,200,*,UP,NTRANS ++S 14400,1500,14400,2500,200,*,UP,NTRANS ++S 15600,7600,15600,9400,200,*,DOWN,PTRANS ++S 14400,6500,14400,8500,200,*,DOWN,PTRANS ++S 13200,6600,13200,8600,200,*,DOWN,PTRANS ++S 13200,1500,13200,2400,200,*,UP,NTRANS ++S 0,5000,24000,5000,10000,sff2_x4,RIGHT,TALU8 ++S 0,2200,24000,2200,5200,*,RIGHT,PWELL ++S 0,7600,24000,7600,5600,*,RIGHT,NWELL ++S 1800,900,1800,2200,600,*,UP,NDIF ++S 600,1700,600,2300,600,*,UP,NDIF ++S 1200,1500,1200,2500,200,*,UP,NTRANS ++S 2400,1500,2400,2400,200,*,UP,NTRANS ++S 5000,1500,5000,2400,200,*,UP,NTRANS ++S 3800,1700,3800,2200,600,*,UP,NDIF ++S 3200,1500,3200,2400,200,*,UP,NTRANS ++S 6400,900,6400,2200,600,*,UP,NDIF ++S 5800,1500,5800,2400,200,*,UP,NTRANS ++S 4200,1700,4200,3100,1000,*,DOWN,NDIF ++S 9600,1500,9600,2500,200,*,UP,NTRANS ++S 9000,900,9000,2200,600,*,DOWN,NDIF ++S 7800,1600,7800,2200,600,*,DOWN,NDIF ++S 8400,1400,8400,2400,200,*,UP,NTRANS ++S 10200,1700,10200,2300,600,*,DOWN,NDIF ++S 16200,800,16200,1200,600,*,DOWN,NDIF ++S 17400,800,17400,1300,600,*,DOWN,NDIF ++S 16800,600,16800,1500,200,*,UP,NTRANS ++S 23400,800,23400,2300,600,*,DOWN,NDIF ++S 22800,600,22800,2500,200,*,UP,NTRANS ++S 22200,800,22200,2300,600,*,DOWN,NDIF ++S 21000,800,21000,2200,600,*,DOWN,NDIF ++S 17400,800,17400,2300,600,*,DOWN,NDIF ++S 18600,1700,18600,2300,600,*,DOWN,NDIF ++S 21600,600,21600,2500,200,*,UP,NTRANS ++S 19800,1700,19800,2200,600,*,DOWN,NDIF ++S 11400,900,11400,2200,600,*,DOWN,NDIF ++S 12000,1500,12000,2400,200,*,UP,NTRANS ++S 12600,1700,12600,2200,600,*,DOWN,NDIF ++S 15000,800,15000,2300,600,*,DOWN,NDIF ++S 13800,1700,13800,2200,600,*,DOWN,NDIF ++S 2400,6600,2400,8500,200,*,DOWN,PTRANS ++S 1800,6800,1800,9100,600,*,DOWN,PDIF ++S 600,6700,600,8300,600,*,DOWN,PDIF ++S 1200,6500,1200,8500,200,*,DOWN,PTRANS ++S 5800,6600,5800,8500,200,*,DOWN,PTRANS ++S 4000,6800,4000,8300,1000,*,DOWN,PDIF ++S 3200,6600,3200,8500,200,*,DOWN,PTRANS ++S 6400,6800,6400,9100,600,*,DOWN,PDIF ++S 5000,6600,5000,8500,200,*,DOWN,PTRANS ++S 10200,6700,10200,8300,600,*,UP,PDIF ++S 9600,6500,9600,8500,200,*,DOWN,PTRANS ++S 8400,6600,8400,8600,200,*,DOWN,PTRANS ++S 7800,6800,7800,8400,600,*,UP,PDIF ++S 16000,7800,16000,9200,600,*,DOWN,PDIF ++S 18600,7800,18600,9200,600,*,DOWN,PDIF ++S 17200,7700,17200,9200,600,*,DOWN,PDIF ++S 9000,6800,9000,9100,600,*,UP,PDIF ++S 23400,5700,23400,9200,600,*,DOWN,PDIF ++S 22800,5500,22800,9400,200,*,DOWN,PTRANS ++S 22200,5700,22200,9200,600,*,DOWN,PDIF ++S 16800,7500,16800,9400,200,*,UP,PTRANS ++S 19800,7800,19800,9200,600,*,UP,PDIF ++S 12000,7600,12000,9400,200,*,DOWN,PTRANS ++S 21000,5700,21000,9200,600,*,DOWN,PDIF ++S 21600,5500,21600,9400,200,*,DOWN,PTRANS ++S 15000,6700,15000,9200,600,*,UP,PDIF ++S 13800,6800,13800,8400,600,*,UP,PDIF ++S 12600,6800,12600,9200,600,*,UP,PDIF ++S 11400,7800,11400,9200,600,*,UP,PDIF ++S 15600,2000,16200,2000,600,*,RIGHT,POLY ++S 16800,1800,16800,3000,200,*,UP,POLY ++S 1200,5000,5000,5000,200,*,RIGHT,POLY ++S 1200,2800,1200,6200,200,*,DOWN,POLY ++S 1800,3000,2400,3000,600,*,RIGHT,POLY ++S 1800,6000,2400,6000,600,*,RIGHT,POLY ++S 5000,2800,5000,5000,200,*,DOWN,POLY ++S 3200,2800,3200,4000,200,*,DOWN,POLY ++S 3200,5000,3200,6200,200,*,DOWN,POLY ++S 8400,6000,9000,6000,600,*,RIGHT,POLY ++S 10200,4000,18000,4000,200,ckr,RIGHT,POLY ++S 7800,5000,19200,5000,200,nckr,RIGHT,POLY ++S 20400,5000,21000,5000,600,*,RIGHT,POLY ++S 20400,3000,21000,3000,600,*,RIGHT,POLY ++S 21600,2800,21600,5200,200,*,DOWN,POLY ++S 19200,2800,19200,5000,200,*,DOWN,POLY ++S 9600,2800,9600,6200,200,*,DOWN,POLY ++S 8400,3000,9000,3000,600,*,RIGHT,POLY ++S 13800,4000,14400,4000,600,*,RIGHT,POLY ++S 18000,4000,18600,4000,600,*,RIGHT,POLY ++S 14400,2800,14400,4000,200,*,DOWN,POLY ++S 18000,5000,18000,7200,200,*,DOWN,POLY ++S 16800,6000,16800,7200,200,*,DOWN,POLY ++S 18000,2800,18000,4000,200,*,DOWN,POLY ++S 22800,2800,22800,5200,200,*,DOWN,POLY ++S 14400,5000,14400,6200,200,*,DOWN,POLY ++S 16200,3000,16800,3000,600,*,RIGHT,POLY ++S 15600,7000,16200,7000,600,*,RIGHT,POLY ++S 18600,7000,19200,7000,600,*,RIGHT,POLY ++S 16200,6000,16800,6000,600,*,RIGHT,POLY ++S 0,600,24000,600,1200,vss,RIGHT,CALU1 ++S 600,2000,5000,2000,400,*,RIGHT,ALU1 ++S 600,1900,600,7100,400,*,DOWN,ALU1 ++S 9000,1900,9000,7100,400,*,DOWN,ALU1 ++S 10200,1900,10200,7100,400,*,DOWN,ALU1 ++S 5000,2000,5000,6100,400,*,DOWN,ALU1 ++S 3000,2000,3000,4100,400,*,UP,ALU1 ++S 17400,1900,17400,8100,400,y,DOWN,ALU1 ++S 6000,1900,6000,7100,400,*,DOWN,ALU1 ++S 7800,1900,7800,7100,400,*,DOWN,ALU1 ++S 15900,2000,17400,2000,400,*,RIGHT,ALU1 ++S 13700,2000,15000,2000,400,*,RIGHT,ALU1 ++S 18500,2000,19800,2000,400,*,RIGHT,ALU1 ++S 23400,900,23400,2100,400,*,DOWN,ALU1 ++S 21000,900,21000,2100,400,*,DOWN,ALU1 ++S 0,9400,24000,9400,1200,vdd,RIGHT,CALU1 ++S 2000,2900,2000,8100,400,*,DOWN,ALU1 ++S 4000,8000,12000,8000,400,*,RIGHT,ALU1 ++S 3000,4900,3000,8100,400,*,DOWN,ALU1 ++S 4000,2900,4000,8000,400,*,DOWN,ALU1 ++S 15900,7000,17400,7000,400,*,LEFT,ALU1 ++S 23400,5900,23400,9100,400,*,DOWN,ALU1 ++S 21000,5900,21000,9100,400,*,DOWN,ALU1 ++S 20700,5000,22200,5000,400,*,RIGHT,ALU1 ++S 20700,3000,22200,3000,400,*,RIGHT,ALU1 ++S 15000,6000,16500,6000,400,*,RIGHT,ALU1 ++S 18600,4000,18600,7000,400,*,DOWN,ALU1 ++S 15000,3000,16500,3000,400,*,LEFT,ALU1 ++S 18500,8000,19800,8000,400,*,RIGHT,ALU1 ++S 13700,7000,15000,7000,400,*,RIGHT,ALU1 ++S 12000,2900,12000,8000,400,u,DOWN,ALU1 ++S 14000,3900,14000,6000,400,*,UP,ALU1 ++S 12900,6000,14000,6000,400,*,RIGHT,ALU1 ++S 13000,2900,13000,5100,400,*,DOWN,ALU1 ++S 15000,2000,15000,7000,400,sff_m,DOWN,ALU1 ++S 19800,2000,19800,8000,400,sff_s,DOWN,ALU1 ++S 20400,4800,20400,7200,200,*,DOWN,POLY ++S 19800,4000,20900,4000,400,*,RIGHT,ALU1 ++S 20800,4000,22800,4000,600,*,RIGHT,POLY ++S 9000,2000,9000,7000,400,ck,DOWN,CALU1 ++S 2000,3000,2000,8000,400,i0,DOWN,CALU1 ++S 6000,2000,6000,7000,400,i1,DOWN,CALU1 ++S 3000,5000,3000,8000,400,cmd,DOWN,CALU1 ++S 22000,2000,22000,8000,400,q,DOWN,CALU1 ++S 8700,6000,8900,6000,400,*,RIGHT,ALU1 ++S 8700,3000,8900,3000,400,*,RIGHT,ALU1 ++S 7900,5000,8100,5000,400,*,RIGHT,ALU1 ++S 22100,8000,22300,8000,400,*,RIGHT,ALU1 ++S 22100,7000,22300,7000,400,*,RIGHT,ALU1 ++S 22100,6000,22300,6000,400,*,RIGHT,ALU1 ++S 22100,2000,22300,2000,400,*,RIGHT,ALU1 ++S 18700,7000,18900,7000,400,*,RIGHT,ALU1 ++S 18300,4000,18500,4000,400,*,RIGHT,ALU1 ++S 11700,7000,11900,7000,400,*,RIGHT,ALU1 ++S 10300,4000,10500,4000,400,*,RIGHT,ALU1 ++S 21000,5000,21000,5000,400,q,LEFT,CALU1 ++S 21000,3000,21000,3000,400,q,LEFT,CALU1 ++V 5000,9300,CONT_BODY_N,* ++V 3000,9300,CONT_BODY_N,* ++V 19800,700,CONT_BODY_P,* ++V 18600,700,CONT_BODY_P,* ++V 13800,700,CONT_BODY_P,* ++V 12600,700,CONT_BODY_P,* ++V 5000,700,CONT_BODY_P,* ++V 3000,700,CONT_BODY_P,* ++V 8000,5000,CONT_POLY,* ++V 1800,1000,CONT_DIF_N,* ++V 600,2000,CONT_DIF_N,* ++V 6400,1000,CONT_DIF_N,* ++V 18600,2000,CONT_DIF_N,* ++V 10200,2000,CONT_DIF_N,* ++V 9000,1000,CONT_DIF_N,* ++V 7800,2000,CONT_DIF_N,* ++V 22200,2000,CONT_DIF_N,* ++V 21000,2000,CONT_DIF_N,* ++V 23400,2000,CONT_DIF_N,* ++V 21000,1000,CONT_DIF_N,* ++V 23400,1000,CONT_DIF_N,* ++V 17400,2000,CONT_DIF_N,* ++V 13800,2000,CONT_DIF_N,* ++V 16200,1000,CONT_DIF_N,* ++V 11400,1000,CONT_DIF_N,* ++V 4000,3000,CONT_DIF_N,* ++V 1800,9000,CONT_DIF_P,* ++V 600,7000,CONT_DIF_P,* ++V 7800,7000,CONT_DIF_P,* ++V 10200,7000,CONT_DIF_P,* ++V 6400,9000,CONT_DIF_P,* ++V 21000,6000,CONT_DIF_P,* ++V 22200,6000,CONT_DIF_P,* ++V 23400,6000,CONT_DIF_P,* ++V 17400,8000,CONT_DIF_P,* ++V 16200,9000,CONT_DIF_P,* ++V 18600,8000,CONT_DIF_P,* ++V 9000,9000,CONT_DIF_P,* ++V 4000,7000,CONT_DIF_P,* ++V 22200,8000,CONT_DIF_P,* ++V 11400,9000,CONT_DIF_P,* ++V 23400,7000,CONT_DIF_P,* ++V 23400,8000,CONT_DIF_P,* ++V 21000,9000,CONT_DIF_P,* ++V 23400,9000,CONT_DIF_P,* ++V 21000,8000,CONT_DIF_P,* ++V 21000,7000,CONT_DIF_P,* ++V 13800,7000,CONT_DIF_P,* ++V 22200,7000,CONT_DIF_P,* ++V 16000,2000,CONT_POLY,* ++V 2000,3000,CONT_POLY,* ++V 2000,6000,CONT_POLY,* ++V 5000,6000,CONT_POLY,* ++V 3000,5000,CONT_POLY,* ++V 3000,4000,CONT_POLY,* ++V 16000,7000,CONT_POLY,* ++V 8800,3000,CONT_POLY,* ++V 8800,6000,CONT_POLY,* ++V 6000,3000,CONT_POLY,* ++V 10400,4000,CONT_POLY,* ++V 11800,7000,CONT_POLY,* ++V 18800,7000,CONT_POLY,* ++V 14000,4000,CONT_POLY,* ++V 16400,6000,CONT_POLY,* ++V 18400,4000,CONT_POLY,* ++V 16400,3000,CONT_POLY,* ++V 20800,3000,CONT_POLY,* ++V 20800,5000,CONT_POLY,* ++V 13000,6000,CONT_POLY,* ++V 13000,3000,CONT_POLY,* ++V 13000,5000,CONT_POLY,* ++V 12000,3000,CONT_POLY,* ++V 6000,6000,CONT_POLY,* ++V 20800,4000,CONT_POLY,* ++EOF +diff --git a/alliance/src/cells/src/msxlib/sff2_x4.vbe b/alliance/src/cells/src/msxlib/sff2_x4.vbe +new file mode 100644 +index 0000000..59eaa64 +--- /dev/null ++++ b/alliance/src/cells/src/msxlib/sff2_x4.vbe +@@ -0,0 +1,51 @@ ++ENTITY sff2_x4 IS ++GENERIC ( ++ CONSTANT area : NATURAL := 6000; ++ CONSTANT cin_ck : NATURAL := 8; ++ CONSTANT cin_cmd : NATURAL := 16; ++ CONSTANT cin_i0 : NATURAL := 8; ++ CONSTANT cin_i1 : NATURAL := 7; ++ CONSTANT rdown_ck_q : NATURAL := 800; ++ CONSTANT rup_ck_q : NATURAL := 890; ++ CONSTANT taf_ck_q : NATURAL := 500; ++ CONSTANT tar_ck_q : NATURAL := 500; ++ CONSTANT thf_cmd_ck : NATURAL := 0; ++ CONSTANT thf_i0_ck : NATURAL := 0; ++ CONSTANT thf_i1_ck : NATURAL := 0; ++ CONSTANT thr_cmd_ck : NATURAL := 0; ++ CONSTANT thr_i0_ck : NATURAL := 0; ++ CONSTANT thr_i1_ck : NATURAL := 0; ++ CONSTANT tsf_cmd_ck : NATURAL := 833; ++ CONSTANT tsf_i0_ck : NATURAL := 764; ++ CONSTANT tsf_i1_ck : NATURAL := 764; ++ CONSTANT tsr_cmd_ck : NATURAL := 770; ++ CONSTANT tsr_i0_ck : NATURAL := 666; ++ CONSTANT tsr_i1_ck : NATURAL := 666; ++ CONSTANT transistors : NATURAL := 34 ++); ++PORT ( ++ ck : in BIT; ++ cmd : in BIT; ++ i0 : in BIT; ++ i1 : in BIT; ++ q : out BIT; ++ vdd : in BIT; ++ vss : in BIT ++); ++END sff2_x4; ++ ++ARCHITECTURE VBE OF sff2_x4 IS ++ SIGNAL sff_m : REG_BIT REGISTER; ++ ++BEGIN ++ ASSERT (vdd and not (vss)) ++ REPORT "power supply is missing on sff2_x4" ++ SEVERITY WARNING; ++ ++ label0 : BLOCK ((ck and not (ck'STABLE)) = '1') ++ BEGIN ++ sff_m <= GUARDED ((i1 and cmd) or (i0 and not (cmd))); ++ END BLOCK label0; ++ ++ q <= sff_m after 2000 ps; ++END; +diff --git a/alliance/src/cells/src/msxlib/sff3_x4.ap b/alliance/src/cells/src/msxlib/sff3_x4.ap +new file mode 100644 +index 0000000..7f7d585 +--- /dev/null ++++ b/alliance/src/cells/src/msxlib/sff3_x4.ap +@@ -0,0 +1,358 @@ ++V ALLIANCE : 6 ++H sff3_x4,P,14/ 8/2014,100 ++A 0,0,28000,10000 ++R 9000,5000,ref_ref,i0_50 ++R 8000,6000,ref_ref,i0_60 ++R 8000,4000,ref_ref,i0_40 ++R 7000,6000,ref_ref,cmd0_60 ++R 7000,5000,ref_ref,cmd0_50 ++R 7000,4000,ref_ref,cmd0_40 ++R 5000,5000,ref_ref,i1_50 ++R 3000,5000,ref_ref,i2_50 ++R 1000,7000,ref_ref,cmd1_70 ++R 1000,6000,ref_ref,cmd1_60 ++R 1000,5000,ref_ref,cmd1_50 ++R 1000,4000,ref_ref,cmd1_40 ++R 1000,3000,ref_ref,cmd1_30 ++R 26000,7000,ref_ref,q_70 ++R 26000,8000,ref_ref,q_80 ++R 26000,4000,ref_ref,q_40 ++R 26000,3000,ref_ref,q_30 ++R 26000,5000,ref_ref,q_50 ++R 26000,6000,ref_ref,q_60 ++R 26000,2000,ref_ref,q_20 ++R 12000,4000,ref_ref,ck_40 ++R 12000,3000,ref_ref,ck_30 ++R 12000,5000,ref_ref,ck_50 ++R 12000,6000,ref_ref,ck_60 ++R 12000,7000,ref_ref,ck_70 ++R 12000,2000,ref_ref,ck_20 ++R 25000,5000,ref_ref,q_50 ++R 25000,3000,ref_ref,q_30 ++S 16600,9300,17800,9300,600,*,RIGHT,NTIE ++S 12800,9300,14200,9300,600,*,RIGHT,NTIE ++S 22800,700,23600,700,600,*,RIGHT,PTIE ++S 16800,700,17600,700,600,*,RIGHT,PTIE ++S 12800,700,14200,700,600,*,RIGHT,PTIE ++S 8800,6000,9200,6000,600,*,RIGHT,POLY ++S 8800,4000,9200,4000,600,*,RIGHT,POLY ++S 3600,7000,4000,7000,600,*,RIGHT,POLY ++S 3600,3000,4000,3000,600,*,RIGHT,POLY ++S 26000,1900,26000,8100,400,*,DOWN,ALU1 ++S 8000,4000,8000,4000,400,i0,LEFT,CALU1 ++S 8000,6000,8000,6000,400,i0,LEFT,CALU1 ++S 9000,5000,9000,5000,400,i0,LEFT,CALU1 ++S 7000,4000,7000,6000,400,cmd0,DOWN,CALU1 ++S 5000,5000,5000,5000,400,i1,LEFT,CALU1 ++S 3000,5000,3000,5000,400,i2,LEFT,CALU1 ++S 1000,3000,1000,7000,400,cmd1,DOWN,CALU1 ++S 26000,2000,26000,8000,400,q,DOWN,CALU1 ++S 12000,2000,12000,7000,400,ck,DOWN,CALU1 ++S 7000,5000,7900,5000,400,*,RIGHT,ALU1 ++S 9800,3000,9800,3500,400,*,DOWN,ALU1 ++S 7900,6000,8800,6000,400,*,RIGHT,ALU1 ++S 7900,4000,8800,4000,400,*,RIGHT,ALU1 ++S 7000,3900,7000,6100,400,*,DOWN,ALU1 ++S 8800,3900,8800,6100,400,*,UP,ALU1 ++S 1000,7900,1000,9100,400,*,UP,ALU1 ++S 2100,2000,6700,2000,400,*,RIGHT,ALU1 ++S 7000,3000,7000,7200,200,*,UP,POLY ++S 7000,7200,7200,7200,200,*,RIGHT,POLY ++S 8800,6000,9200,6000,200,*,RIGHT,POLY ++S 9200,6000,9200,7200,200,*,UP,POLY ++S 8000,3800,8000,6600,200,*,DOWN,POLY ++S 9000,4000,9200,4000,200,*,RIGHT,POLY ++S 9200,2200,9200,4000,200,*,DOWN,POLY ++S 8400,2200,8400,3000,200,*,UP,POLY ++S 10400,4000,10400,5200,200,*,DOWN,POLY ++S 8000,7200,8400,7200,200,*,LEFT,POLY ++S 8000,6600,8000,7200,200,*,UP,POLY ++S 6000,2600,6000,7200,200,*,DOWN,POLY ++S 7200,2200,7600,2200,200,*,RIGHT,POLY ++S 6600,3000,6800,3000,200,*,LEFT,POLY ++S 8000,5000,10400,5000,200,*,RIGHT,POLY ++S 7600,2200,7600,3800,200,*,DOWN,POLY ++S 7600,3800,8000,3800,200,*,LEFT,POLY ++S 4000,4000,4000,7200,200,*,DOWN,POLY ++S 1000,5000,1600,5000,600,*,RIGHT,POLY ++S 3600,3000,4000,3000,200,*,RIGHT,POLY ++S 5200,6000,5200,7200,200,*,UP,POLY ++S 5200,2600,5200,4000,200,*,UP,POLY ++S 4000,2600,4000,3000,200,*,DOWN,POLY ++S 2800,2600,2800,7200,200,*,DOWN,POLY ++S 5000,5000,6000,5000,200,*,RIGHT,POLY ++S 4000,4000,5200,4000,200,*,RIGHT,POLY ++S 9800,3100,9800,3300,600,*,DOWN,NDIF ++S 10400,2900,10400,3700,200,*,DOWN,NTRANS ++S 6600,800,6600,2100,600,*,DOWN,NDIF ++S 9200,700,9200,1900,200,*,UP,NTRANS ++S 9800,1100,9800,1900,600,*,UP,NDIF ++S 7200,600,7200,1800,200,*,UP,NTRANS ++S 7800,800,7800,1600,400,*,DOWN,NDIF ++S 8400,700,8400,1900,200,*,UP,NTRANS ++S 4000,1100,4000,2300,200,*,UP,NTRANS ++S 5200,1100,5200,2300,200,*,UP,NTRANS ++S 6000,1100,6000,2300,200,*,UP,NTRANS ++S 2800,1100,2800,2300,200,*,UP,NTRANS ++S 2200,1300,2200,1900,600,*,DOWN,NDIF ++S 3400,1300,3400,2100,400,*,DOWN,NDIF ++S 4600,1300,4600,3100,600,*,UP,NDIF ++S 9800,7800,9800,9200,600,*,UP,PDIF ++S 7800,7800,7800,9200,400,*,UP,PDIF ++S 9200,7600,9200,9400,200,*,UP,PTRANS ++S 6600,7800,6600,9200,400,*,UP,PDIF ++S 9800,5700,9800,6700,600,*,UP,PDIF ++S 10400,5500,10400,6900,200,*,UP,PTRANS ++S 8400,7600,8400,9400,200,*,UP,PTRANS ++S 7200,7600,7200,9400,200,*,UP,PTRANS ++S 6000,7500,6000,9400,200,*,UP,PTRANS ++S 5200,7500,5200,9400,200,*,UP,PTRANS ++S 2200,5800,2200,6800,600,*,UP,PDIF ++S 1600,5600,1600,7000,200,*,UP,PTRANS ++S 1000,5800,1000,7900,600,*,UP,PDIF ++S 4000,7600,4000,9400,200,*,UP,PTRANS ++S 4600,7100,4600,9200,600,*,UP,PDIF ++S 3400,7800,3400,9200,400,*,DOWN,PDIF ++S 2800,7500,2800,9400,200,*,UP,PTRANS ++S 2200,7700,2200,9200,600,*,UP,PDIF ++S 27400,5900,27400,9100,400,*,DOWN,ALU1 ++S 25000,5900,25000,9100,400,*,DOWN,ALU1 ++S 27400,900,27400,2100,400,*,DOWN,ALU1 ++S 25000,900,25000,2100,400,*,DOWN,ALU1 ++S 24400,5000,25000,5000,600,*,RIGHT,POLY ++S 24400,3000,25000,3000,600,*,RIGHT,POLY ++S 25600,2800,25600,5200,200,*,DOWN,POLY ++S 23200,2800,23200,5000,200,*,DOWN,POLY ++S 17800,4000,18400,4000,600,*,RIGHT,POLY ++S 22000,4000,22600,4000,600,*,RIGHT,POLY ++S 18400,2800,18400,4000,200,*,DOWN,POLY ++S 22000,5000,22000,7200,200,*,DOWN,POLY ++S 20800,6000,20800,7200,200,*,DOWN,POLY ++S 22000,2800,22000,4000,200,*,DOWN,POLY ++S 20200,3000,20800,3000,600,*,RIGHT,POLY ++S 19600,7000,20200,7000,600,*,RIGHT,POLY ++S 22600,7000,23200,7000,600,*,RIGHT,POLY ++S 20200,6000,20800,6000,600,*,RIGHT,POLY ++S 24400,4800,24400,7200,200,*,DOWN,POLY ++S 24800,4000,26800,4000,600,*,RIGHT,POLY ++S 26800,2800,26800,5200,200,*,DOWN,POLY ++S 18400,5000,18400,6200,200,*,DOWN,POLY ++S 14200,6200,14800,6200,200,*,RIGHT,POLY ++S 14200,2800,14800,2800,200,*,RIGHT,POLY ++S 14200,2800,14200,6200,200,*,DOWN,POLY ++S 15000,4000,22000,4000,200,ckr,RIGHT,POLY ++S 19600,2000,20200,2000,600,*,RIGHT,POLY ++S 20800,1800,20800,3000,200,*,UP,POLY ++S 17200,1500,17200,2400,200,*,UP,NTRANS ++S 24400,1500,24400,2400,200,*,UP,NTRANS ++S 23200,1500,23200,2500,200,*,UP,NTRANS ++S 22000,1500,22000,2500,200,*,UP,NTRANS ++S 19600,600,19600,1400,200,*,UP,NTRANS ++S 18400,1500,18400,2500,200,*,UP,NTRANS ++S 21400,800,21400,1300,600,*,DOWN,NDIF ++S 20800,600,20800,1500,200,*,UP,NTRANS ++S 25000,800,25000,2200,600,*,DOWN,NDIF ++S 21400,800,21400,2300,600,*,DOWN,NDIF ++S 22600,1700,22600,2300,600,*,DOWN,NDIF ++S 25600,600,25600,2500,200,*,UP,NTRANS ++S 14200,1700,14200,2200,600,*,DOWN,NDIF ++S 20200,800,20200,1200,600,*,DOWN,NDIF ++S 16600,1700,16600,2200,600,*,DOWN,NDIF ++S 19000,800,19000,2300,600,*,DOWN,NDIF ++S 17800,1700,17800,2200,600,*,DOWN,NDIF ++S 27400,800,27400,2300,600,*,DOWN,NDIF ++S 26800,600,26800,2500,200,*,UP,NTRANS ++S 26200,800,26200,2300,600,*,DOWN,NDIF ++S 23800,1700,23800,2200,600,*,DOWN,NDIF ++S 15400,900,15400,2200,600,*,DOWN,NDIF ++S 16000,1500,16000,2400,200,*,UP,NTRANS ++S 14800,1500,14800,2400,200,*,UP,NTRANS ++S 22000,7500,22000,9400,200,*,DOWN,PTRANS ++S 19600,7600,19600,9400,200,*,DOWN,PTRANS ++S 18400,6500,18400,8500,200,*,DOWN,PTRANS ++S 24400,7500,24400,9400,200,*,DOWN,PTRANS ++S 23200,7600,23200,9400,200,*,DOWN,PTRANS ++S 27400,5700,27400,9200,600,*,DOWN,PDIF ++S 26800,5500,26800,9400,200,*,DOWN,PTRANS ++S 26200,5700,26200,9200,600,*,DOWN,PDIF ++S 20800,7500,20800,9400,200,*,UP,PTRANS ++S 14200,6800,14200,8300,600,*,UP,PDIF ++S 17200,6600,17200,8500,200,*,DOWN,PTRANS ++S 19000,6700,19000,9200,600,*,UP,PDIF ++S 17800,6800,17800,8300,600,*,UP,PDIF ++S 20000,7800,20000,9200,600,*,DOWN,PDIF ++S 22600,7800,22600,9200,600,*,DOWN,PDIF ++S 21200,7700,21200,9200,600,*,DOWN,PDIF ++S 23800,7800,23800,9200,600,*,UP,PDIF ++S 25000,5700,25000,9200,600,*,DOWN,PDIF ++S 25600,5500,25600,9400,200,*,DOWN,PTRANS ++S 16600,6800,16600,8300,600,*,UP,PDIF ++S 15400,6800,15400,9100,600,*,UP,PDIF ++S 16000,6600,16000,8500,200,*,DOWN,PTRANS ++S 14800,6600,14800,8500,200,*,DOWN,PTRANS ++S 0,5000,28000,5000,10000,sff3_x4,RIGHT,TALU8 ++S 0,2200,28000,2200,5200,*,RIGHT,PWELL ++S 0,7600,28000,7600,5600,*,RIGHT,NWELL ++S 0,9400,28000,9400,1200,vdd,RIGHT,CALU1 ++S 0,600,28000,600,1200,vss,RIGHT,CALU1 ++S 12200,2800,12200,6200,200,*,DOWN,POLY ++S 12200,6500,12200,8500,200,*,DOWN,PTRANS ++S 12200,1500,12200,2500,200,*,UP,NTRANS ++S 12800,1700,12800,2300,600,*,DOWN,NDIF ++S 12800,6700,12800,8300,600,*,UP,PDIF ++S 11200,5700,11200,9100,1000,*,DOWN,PDIF ++S 11200,900,11200,3500,1000,*,DOWN,NDIF ++S 13000,6700,13000,8300,600,*,UP,PDIF ++S 13000,1700,13000,2300,600,*,DOWN,NDIF ++S 13200,5000,23200,5000,200,nckr,RIGHT,POLY ++S 1000,700,1000,2100,400,*,DOWN,ALU1 ++S 2200,3100,2200,3500,600,*,UP,NDIF ++S 1600,2900,1600,3700,200,*,DOWN,NTRANS ++S 1000,1900,1000,3500,600,*,DOWN,NDIF ++S 1600,4000,1600,5200,200,*,DOWN,POLY ++S 2200,3000,3700,3000,400,*,LEFT,ALU1 ++S 4100,5000,5100,5000,400,*,LEFT,ALU1 ++S 3000,4300,3000,5100,400,*,DOWN,ALU1 ++S 2000,3200,2000,6000,400,*,UP,ALU1 ++S 2100,6000,5100,6000,400,*,LEFT,ALU1 ++S 4500,3000,5600,3000,400,*,RIGHT,ALU1 ++S 5600,3000,5600,4000,400,*,UP,ALU1 ++S 5600,4000,6000,4000,400,*,RIGHT,ALU1 ++S 6000,4000,6000,6900,400,*,UP,ALU1 ++S 1000,7000,3700,7000,400,*,LEFT,ALU1 ++S 2100,8000,6700,8000,400,*,RIGHT,ALU1 ++S 4500,7000,11000,7000,400,*,RIGHT,ALU1 ++S 6700,3000,9800,3000,400,*,RIGHT,ALU1 ++S 10000,3400,10000,6000,400,*,DOWN,ALU1 ++S 9800,7100,9800,8100,400,*,DOWN,ALU1 ++S 9800,8000,16000,8000,400,*,RIGHT,ALU1 ++S 11000,2000,11000,7000,400,*,DOWN,ALU1 ++S 9700,2000,11000,2000,400,*,RIGHT,ALU1 ++S 13000,1900,13000,7100,400,*,DOWN,ALU1 ++S 14200,6900,15000,6900,400,*,LEFT,ALU1 ++S 15000,2100,15000,6900,400,*,UP,ALU1 ++S 14200,2100,15000,2100,400,*,RIGHT,ALU1 ++S 16000,2900,16000,8000,400,u,DOWN,ALU1 ++S 17000,3000,17000,5100,400,*,DOWN,ALU1 ++S 19000,2000,19000,7000,400,sff_m,DOWN,ALU1 ++S 17700,7000,19000,7000,400,*,RIGHT,ALU1 ++S 19100,6000,20500,6000,400,*,RIGHT,ALU1 ++S 19100,3000,20500,3000,400,*,LEFT,ALU1 ++S 17700,2000,19000,2000,400,*,RIGHT,ALU1 ++S 19900,2000,21400,2000,400,*,RIGHT,ALU1 ++S 21400,1900,21400,8100,400,y,DOWN,ALU1 ++S 19900,7000,21300,7000,400,*,LEFT,ALU1 ++S 22600,4000,22600,7000,400,*,DOWN,ALU1 ++S 23800,2000,23800,8000,400,sff_s,DOWN,ALU1 ++S 22500,8000,23800,8000,400,*,RIGHT,ALU1 ++S 23900,4000,24900,4000,400,*,RIGHT,ALU1 ++S 22500,2000,23800,2000,400,*,RIGHT,ALU1 ++S 24700,3000,26100,3000,400,*,RIGHT,ALU1 ++S 24700,5000,26100,5000,400,*,RIGHT,ALU1 ++S 17100,6000,18000,6000,400,*,RIGHT,ALU1 ++S 18000,3900,18000,6000,400,*,UP,ALU1 ++S 8900,5000,9100,5000,400,*,LEFT,ALU1 ++S 1000,2900,1000,7100,400,*,DOWN,ALU1 ++S 12000,1900,12000,7100,400,*,DOWN,ALU1 ++S 9700,6000,9900,6000,400,*,RIGHT,ALU1 ++S 2100,3200,2300,3200,400,*,RIGHT,ALU1 ++S 26100,8000,26300,8000,400,*,RIGHT,ALU1 ++S 26100,7000,26300,7000,400,*,RIGHT,ALU1 ++S 26100,6000,26300,6000,400,*,RIGHT,ALU1 ++S 26100,2000,26300,2000,400,*,RIGHT,ALU1 ++S 22700,7000,22900,7000,400,*,RIGHT,ALU1 ++S 22300,4000,22500,4000,400,*,RIGHT,ALU1 ++S 17100,3000,17300,3000,400,*,RIGHT,ALU1 ++S 14100,7000,14300,7000,400,*,RIGHT,ALU1 ++S 14100,2000,14300,2000,400,*,RIGHT,ALU1 ++S 13100,5000,13300,5000,400,*,RIGHT,ALU1 ++S 25000,5000,25000,5000,400,q,LEFT,CALU1 ++S 25000,3000,25000,3000,400,q,LEFT,CALU1 ++V 17800,9300,CONT_BODY_N,* ++V 16600,9300,CONT_BODY_N,* ++V 14200,9300,CONT_BODY_N,* ++V 12800,9300,CONT_BODY_N,* ++V 23800,700,CONT_BODY_P,* ++V 22600,700,CONT_BODY_P,* ++V 17800,700,CONT_BODY_P,* ++V 16600,700,CONT_BODY_P,* ++V 14200,700,CONT_BODY_P,* ++V 12800,700,CONT_BODY_P,* ++V 11000,9000,CONT_DIF_P,* ++V 8800,6000,CONT_POLY,* ++V 8800,4000,CONT_POLY,* ++V 7800,5000,CONT_POLY,* ++V 8400,3000,CONT_POLY,* ++V 6800,3000,CONT_POLY,* ++V 5000,6000,CONT_POLY,* ++V 3000,5000,CONT_POLY,* ++V 5000,5000,CONT_POLY,* ++V 1000,5000,CONT_POLY,* ++V 3600,3000,CONT_POLY,* ++V 3600,7000,CONT_POLY,* ++V 9800,3400,CONT_DIF_N,* ++V 4600,3000,CONT_DIF_N,* ++V 6600,2000,CONT_DIF_N,* ++V 7800,1000,CONT_DIF_N,* ++V 9800,2000,CONT_DIF_N,* ++V 11000,1000,CONT_DIF_N,* ++V 1000,2000,CONT_DIF_N,* ++V 2200,2000,CONT_DIF_N,* ++V 6600,8000,CONT_DIF_P,* ++V 7800,9000,CONT_DIF_P,* ++V 9800,8000,CONT_DIF_P,* ++V 9800,6000,CONT_DIF_P,* ++V 4600,7000,CONT_DIF_P,* ++V 2200,8000,CONT_DIF_P,* ++V 2200,6000,CONT_DIF_P,* ++V 1000,8000,CONT_DIF_P,* ++V 20000,7000,CONT_POLY,* ++V 22800,7000,CONT_POLY,* ++V 18000,4000,CONT_POLY,* ++V 20400,6000,CONT_POLY,* ++V 22400,4000,CONT_POLY,* ++V 20400,3000,CONT_POLY,* ++V 24800,3000,CONT_POLY,* ++V 24800,5000,CONT_POLY,* ++V 17000,5000,CONT_POLY,* ++V 24800,4000,CONT_POLY,* ++V 15000,4000,CONT_POLY,* ++V 17200,6000,CONT_POLY,* ++V 16000,6000,CONT_POLY,* ++V 17200,3000,CONT_POLY,* ++V 16000,3000,CONT_POLY,* ++V 20000,2000,CONT_POLY,* ++V 14200,2000,CONT_DIF_N,* ++V 26200,2000,CONT_DIF_N,* ++V 25000,2000,CONT_DIF_N,* ++V 27400,2000,CONT_DIF_N,* ++V 25000,1000,CONT_DIF_N,* ++V 27400,1000,CONT_DIF_N,* ++V 21400,2000,CONT_DIF_N,* ++V 17800,2000,CONT_DIF_N,* ++V 22600,2000,CONT_DIF_N,* ++V 20200,1000,CONT_DIF_N,* ++V 15400,1000,CONT_DIF_N,* ++V 25000,6000,CONT_DIF_P,* ++V 26200,6000,CONT_DIF_P,* ++V 27400,6000,CONT_DIF_P,* ++V 21400,8000,CONT_DIF_P,* ++V 20200,9000,CONT_DIF_P,* ++V 26200,8000,CONT_DIF_P,* ++V 27400,7000,CONT_DIF_P,* ++V 27400,8000,CONT_DIF_P,* ++V 25000,9000,CONT_DIF_P,* ++V 14200,7000,CONT_DIF_P,* ++V 27400,9000,CONT_DIF_P,* ++V 25000,8000,CONT_DIF_P,* ++V 25000,7000,CONT_DIF_P,* ++V 17800,7000,CONT_DIF_P,* ++V 26200,7000,CONT_DIF_P,* ++V 22600,8000,CONT_DIF_P,* ++V 15400,9200,CONT_DIF_P,* ++V 12000,5000,CONT_POLY,* ++V 13200,5000,CONT_POLY,* ++V 13000,2000,CONT_DIF_N,* ++V 13000,7000,CONT_DIF_P,* ++V 2200,3200,CONT_DIF_N,* ++EOF +diff --git a/alliance/src/cells/src/msxlib/sff3_x4.vbe b/alliance/src/cells/src/msxlib/sff3_x4.vbe +new file mode 100644 +index 0000000..a1953ab +--- /dev/null ++++ b/alliance/src/cells/src/msxlib/sff3_x4.vbe +@@ -0,0 +1,65 @@ ++ENTITY sff3_x4 IS ++GENERIC ( ++ CONSTANT area : NATURAL := 7000; ++ CONSTANT cin_ck : NATURAL := 8; ++ CONSTANT cin_cmd0 : NATURAL := 15; ++ CONSTANT cin_cmd1 : NATURAL := 15; ++ CONSTANT cin_i0 : NATURAL := 9; ++ CONSTANT cin_i1 : NATURAL := 8; ++ CONSTANT cin_i2 : NATURAL := 8; ++ CONSTANT rdown_ck_q : NATURAL := 890; ++ CONSTANT rup_ck_q : NATURAL := 810; ++ CONSTANT taf_ck_q : NATURAL := 600; ++ CONSTANT tar_ck_q : NATURAL := 600; ++ CONSTANT thf_ck_q : NATURAL := 0; ++ CONSTANT thf_cmd0_ck : NATURAL := 0; ++ CONSTANT thf_cmd1_ck : NATURAL := 0; ++ CONSTANT thf_i0_ck : NATURAL := 0; ++ CONSTANT thf_i1_ck : NATURAL := 0; ++ CONSTANT thf_i2_ck : NATURAL := 0; ++ CONSTANT thr_ck_q : NATURAL := 0; ++ CONSTANT thr_cmd0_ck : NATURAL := 0; ++ CONSTANT thr_cmd1_ck : NATURAL := 0; ++ CONSTANT thr_i0_ck : NATURAL := 0; ++ CONSTANT thr_i1_ck : NATURAL := 0; ++ CONSTANT thr_i2_ck : NATURAL := 0; ++ CONSTANT tsf_cmd0_ck : NATURAL := 1200; ++ CONSTANT tsf_cmd1_ck : NATURAL := 1200; ++ CONSTANT tsf_i0_ck : NATURAL := 1200; ++ CONSTANT tsf_i1_ck : NATURAL := 1200; ++ CONSTANT tsf_i2_ck : NATURAL := 1200; ++ CONSTANT tsr_cmd0_ck : NATURAL := 1100; ++ CONSTANT tsr_cmd1_ck : NATURAL := 1100; ++ CONSTANT tsr_i0_ck : NATURAL := 850; ++ CONSTANT tsr_i1_ck : NATURAL := 950; ++ CONSTANT tsr_i2_ck : NATURAL := 950; ++ CONSTANT transistors : NATURAL := 42 ++); ++PORT ( ++ ck : in BIT; ++ cmd0 : in BIT; ++ cmd1 : in BIT; ++ i0 : in BIT; ++ i1 : in BIT; ++ i2 : in BIT; ++ q : out BIT; ++ vdd : in BIT; ++ vss : in BIT ++); ++END sff3_x4; ++ ++ARCHITECTURE behaviour_data_flow OF sff3_x4 IS ++ SIGNAL sff_m : REG_BIT REGISTER; ++ ++BEGIN ++ ASSERT (vdd and not (vss)) ++ REPORT "power supply is missing on sff3_x4" ++ SEVERITY WARNING; ++ ++ label0 : BLOCK ((ck and not (ck'STABLE)) = '1') ++ BEGIN ++ sff_m <= GUARDED ((not (cmd0) and i0) or (cmd0 and ((cmd1 and i1) or (not (cmd1) and i2)))); ++ END BLOCK label0; ++ ++ q <= sff_m after 2400 ps; ++END; +diff --git a/alliance/src/cells/src/msxlib/tie_x0.ap b/alliance/src/cells/src/msxlib/tie_x0.ap +new file mode 100644 +index 0000000..250d3cf +--- /dev/null ++++ b/alliance/src/cells/src/msxlib/tie_x0.ap +@@ -0,0 +1,15 @@ ++V ALLIANCE : 6 ++H tie_x0,P, 9/ 8/2014,100 ++A 0,0,2000,10000 ++S 1000,5700,1000,9500,1200,*,UP,NTIE ++S 1000,500,1000,3700,1200,*,DOWN,PTIE ++S 0,600,2000,600,1200,vss,RIGHT,CALU1 ++S 0,5000,2000,5000,10000,tie_x0,LEFT,TALU8 ++S 0,2200,2000,2200,5200,*,LEFT,PWELL ++S 0,7600,2000,7600,5600,*,LEFT,NWELL ++S 0,9400,2000,9400,1200,vdd,RIGHT,CALU1 ++V 1300,700,CONT_BODY_P,* ++V 700,700,CONT_BODY_P,* ++V 1300,9300,CONT_BODY_N,* ++V 700,9300,CONT_BODY_N,* ++EOF +diff --git a/alliance/src/cells/src/msxlib/tie_x0.vbe b/alliance/src/cells/src/msxlib/tie_x0.vbe +new file mode 100644 +index 0000000..fa318aa +--- /dev/null ++++ b/alliance/src/cells/src/msxlib/tie_x0.vbe +@@ -0,0 +1,18 @@ ++ENTITY tie_x0 IS ++GENERIC ( ++ CONSTANT area : NATURAL := 2000; ++ CONSTANT transistors : NATURAL := 0 ++); ++PORT ( ++ vdd : in BIT; ++ vss : in BIT ++); ++END tie_x0; ++ ++ARCHITECTURE behaviour_data_flow OF tie_x0 IS ++ ++BEGIN ++ ASSERT (vdd and not (vss)) ++ REPORT "power supply is missing on tie_x0" ++ SEVERITY WARNING; ++END; +diff --git a/alliance/src/cells/src/msxlib/vddtie.ap b/alliance/src/cells/src/msxlib/vddtie.ap +new file mode 100644 +index 0000000..18a1269 +--- /dev/null ++++ b/alliance/src/cells/src/msxlib/vddtie.ap +@@ -0,0 +1,53 @@ ++V ALLIANCE : 6 ++H vddtie,P, 9/ 8/2014,100 ++A 0,0,3000,10000 ++R 2000,2000,ref_ref,z_20 ++R 2000,3000,ref_ref,z_30 ++R 2000,4000,ref_ref,z_40 ++R 2000,5000,ref_ref,z_50 ++R 2000,6000,ref_ref,z_60 ++R 2000,7000,ref_ref,z_70 ++R 2000,8000,ref_ref,z_80 ++R 1000,6000,ref_ref,z_60 ++S 600,9300,2400,9300,600,*,RIGHT,NTIE ++S 600,700,2400,700,600,*,RIGHT,PTIE ++S 2000,1900,2000,8100,400,*,DOWN,ALU1 ++S 1400,8500,1400,8800,200,*,UP,POLY ++S 700,5700,700,8300,600,*,UP,PDIF ++S 1400,5500,1400,8500,200,1,UP,PTRANS ++S 2100,5700,2100,8300,600,*,UP,PDIF ++S 1400,1600,1400,3900,200,2,DOWN,NTRANS ++S 1400,1200,1400,1600,200,*,DOWN,POLY ++S 2100,1800,2100,3700,600,*,DOWN,NDIF ++S 700,1800,700,3700,600,*,UP,NDIF ++S 800,4700,1400,4700,600,*,RIGHT,POLY ++S 800,700,800,4800,400,*,DOWN,ALU1 ++S 1400,3900,1400,5500,200,*,DOWN,POLY ++S 2000,2000,2000,8000,400,z,DOWN,CALU1 ++S 0,9400,3000,9400,1200,vdd,RIGHT,CALU1 ++S 0,600,3000,600,1200,vss,RIGHT,CALU1 ++S 0,5000,3000,5000,10000,vddtie,LEFT,TALU8 ++S 0,2200,3000,2200,5200,*,LEFT,PWELL ++S 0,7600,3000,7600,5600,*,LEFT,NWELL ++S 800,6000,2000,6000,400,*,LEFT,ALU1 ++S 800,7300,800,9300,400,*,UP,ALU1 ++S 1000,6000,1000,6000,400,z,LEFT,CALU1 ++V 2300,9300,CONT_BODY_N,* ++V 1500,9300,CONT_BODY_N,* ++V 700,9300,CONT_BODY_N,* ++V 2300,700,CONT_BODY_P,* ++V 1500,700,CONT_BODY_P,* ++V 700,700,CONT_BODY_P,* ++V 800,2000,CONT_DIF_N,* ++V 800,2800,CONT_DIF_N,* ++V 800,3600,CONT_DIF_N,* ++V 800,7400,CONT_DIF_P,* ++V 800,8200,CONT_DIF_P,* ++V 2000,2000,CONT_DIF_N,* ++V 800,4700,CONT_POLY,* ++V 2000,2800,CONT_DIF_N,* ++V 2000,3600,CONT_DIF_N,* ++V 2000,7400,CONT_DIF_P,* ++V 2000,6600,CONT_DIF_P,* ++V 2000,5800,CONT_DIF_P,* ++EOF +diff --git a/alliance/src/cells/src/msxlib/vddtie.vbe b/alliance/src/cells/src/msxlib/vddtie.vbe +new file mode 100644 +index 0000000..bf325ef +--- /dev/null ++++ b/alliance/src/cells/src/msxlib/vddtie.vbe +@@ -0,0 +1,20 @@ ++ENTITY vddtie IS ++GENERIC ( ++ CONSTANT area : NATURAL := 3000; ++ CONSTANT transistors : NATURAL := 0 ++); ++PORT ( ++ z : out BIT; ++ vdd : in BIT; ++ vss : in BIT ++); ++END vddtie; ++ ++ARCHITECTURE behaviour_data_flow OF vddtie IS ++ ++BEGIN ++ ASSERT (vdd and not (vss)) ++ REPORT "power supply is missing on vddtie" ++ SEVERITY WARNING; ++ z <= '1'; ++END; +diff --git a/alliance/src/cells/src/msxlib/vfeed1.ap b/alliance/src/cells/src/msxlib/vfeed1.ap +new file mode 100644 +index 0000000..ab4bca1 +--- /dev/null ++++ b/alliance/src/cells/src/msxlib/vfeed1.ap +@@ -0,0 +1,9 @@ ++V ALLIANCE : 6 ++H vfeed1,P,16/ 6/2004,100 ++A 0,0,1000,10000 ++S 0,7600,1000,7600,5600,*,LEFT,NWELL ++S 0,2200,1000,2200,5200,*,LEFT,PWELL ++S 0,5000,1000,5000,10000,vfeed1,LEFT,TALU8 ++S 0,600,1000,600,1200,vss,RIGHT,CALU1 ++S 0,9400,1000,9400,1200,vdd,RIGHT,CALU1 ++EOF +diff --git a/alliance/src/cells/src/msxlib/vfeed1.vbe b/alliance/src/cells/src/msxlib/vfeed1.vbe +new file mode 100644 +index 0000000..5f0117f +--- /dev/null ++++ b/alliance/src/cells/src/msxlib/vfeed1.vbe +@@ -0,0 +1,18 @@ ++ENTITY vfeed1 IS ++GENERIC ( ++ CONSTANT area : NATURAL := 1000; ++ CONSTANT transistors : NATURAL := 0 ++); ++PORT ( ++ vdd : in BIT; ++ vss : in BIT ++); ++END vfeed1; ++ ++ARCHITECTURE behaviour_data_flow OF vfeed1 IS ++ ++BEGIN ++ ASSERT (vdd and not (vss)) ++ REPORT "power supply is missing on vfeed1" ++ SEVERITY WARNING; ++END; +diff --git a/alliance/src/cells/src/msxlib/vfeed2.ap b/alliance/src/cells/src/msxlib/vfeed2.ap +new file mode 100644 +index 0000000..578a4f4 +--- /dev/null ++++ b/alliance/src/cells/src/msxlib/vfeed2.ap +@@ -0,0 +1,15 @@ ++V ALLIANCE : 6 ++H vfeed2,P, 9/ 8/2014,100 ++A 0,0,2000,10000 ++S 1000,5700,1000,9500,1400,*,UP,NTIE ++S 1000,500,1000,3700,1400,*,DOWN,PTIE ++S 0,600,2000,600,1200,vss,RIGHT,CALU1 ++S 0,5000,2000,5000,10000,vfeed2,LEFT,TALU8 ++S 0,2200,2000,2200,5200,*,LEFT,PWELL ++S 0,7600,2000,7600,5600,*,LEFT,NWELL ++S 0,9400,2000,9400,1200,vdd,RIGHT,CALU1 ++V 1300,700,CONT_BODY_P,* ++V 700,700,CONT_BODY_P,* ++V 1300,9300,CONT_BODY_N,* ++V 700,9300,CONT_BODY_N,* ++EOF +diff --git a/alliance/src/cells/src/msxlib/vfeed2.vbe b/alliance/src/cells/src/msxlib/vfeed2.vbe +new file mode 100644 +index 0000000..4ad9833 +--- /dev/null ++++ b/alliance/src/cells/src/msxlib/vfeed2.vbe +@@ -0,0 +1,18 @@ ++ENTITY vfeed2 IS ++GENERIC ( ++ CONSTANT area : NATURAL := 2000; ++ CONSTANT transistors : NATURAL := 0 ++); ++PORT ( ++ vdd : in BIT; ++ vss : in BIT ++); ++END vfeed2; ++ ++ARCHITECTURE behaviour_data_flow OF vfeed2 IS ++ ++BEGIN ++ ASSERT (vdd and not (vss)) ++ REPORT "power supply is missing on vfeed2" ++ SEVERITY WARNING; ++END; +diff --git a/alliance/src/cells/src/msxlib/vfeed3.ap b/alliance/src/cells/src/msxlib/vfeed3.ap +new file mode 100644 +index 0000000..d0a4d80 +--- /dev/null ++++ b/alliance/src/cells/src/msxlib/vfeed3.ap +@@ -0,0 +1,17 @@ ++V ALLIANCE : 6 ++H vfeed3,P, 9/ 8/2014,100 ++A 0,0,3000,10000 ++S 0,5000,3000,5000,10000,vfeed3,LEFT,TALU8 ++S 0,2200,3000,2200,5200,*,LEFT,PWELL ++S 0,7600,3000,7600,5600,*,LEFT,NWELL ++S 0,600,3000,600,1200,vss,RIGHT,CALU1 ++S 0,9400,3000,9400,1200,vdd,RIGHT,CALU1 ++S 1500,5700,1500,9500,2400,*,UP,NTIE ++S 1500,500,1500,3700,2400,*,DOWN,PTIE ++V 2300,700,CONT_BODY_P,* ++V 1500,700,CONT_BODY_P,* ++V 700,700,CONT_BODY_P,* ++V 700,9300,CONT_BODY_N,* ++V 2300,9300,CONT_BODY_N,* ++V 1500,9300,CONT_BODY_N,* ++EOF +diff --git a/alliance/src/cells/src/msxlib/vfeed3.vbe b/alliance/src/cells/src/msxlib/vfeed3.vbe +new file mode 100644 +index 0000000..ca6ce9f +--- /dev/null ++++ b/alliance/src/cells/src/msxlib/vfeed3.vbe +@@ -0,0 +1,18 @@ ++ENTITY vfeed3 IS ++GENERIC ( ++ CONSTANT area : NATURAL := 3000; ++ CONSTANT transistors : NATURAL := 0 ++); ++PORT ( ++ vdd : in BIT; ++ vss : in BIT ++); ++END vfeed3; ++ ++ARCHITECTURE behaviour_data_flow OF vfeed3 IS ++ ++BEGIN ++ ASSERT (vdd and not (vss)) ++ REPORT "power supply is missing on vfeed3" ++ SEVERITY WARNING; ++END; +diff --git a/alliance/src/cells/src/msxlib/vfeed4.ap b/alliance/src/cells/src/msxlib/vfeed4.ap +new file mode 100644 +index 0000000..eab369c +--- /dev/null ++++ b/alliance/src/cells/src/msxlib/vfeed4.ap +@@ -0,0 +1,19 @@ ++V ALLIANCE : 6 ++H vfeed4,P, 9/ 8/2014,100 ++A 0,0,4000,10000 ++S 0,5000,4000,5000,10000,vfeed4,LEFT,TALU8 ++S 0,2200,4000,2200,5200,*,LEFT,PWELL ++S 0,7600,4000,7600,5600,*,LEFT,NWELL ++S 0,9400,4000,9400,1200,vdd,RIGHT,CALU1 ++S 0,600,4000,600,1200,vss,RIGHT,CALU1 ++S 2000,5700,2000,9500,3400,*,UP,NTIE ++S 2000,500,2000,3700,3400,*,DOWN,PTIE ++V 3300,700,CONT_BODY_P,* ++V 3300,9300,CONT_BODY_N,* ++V 2400,9300,CONT_BODY_N,* ++V 1500,9300,CONT_BODY_N,* ++V 700,9300,CONT_BODY_N,* ++V 2500,700,CONT_BODY_P,* ++V 1500,700,CONT_BODY_P,* ++V 700,700,CONT_BODY_P,* ++EOF +diff --git a/alliance/src/cells/src/msxlib/vfeed4.vbe b/alliance/src/cells/src/msxlib/vfeed4.vbe +new file mode 100644 +index 0000000..436550b +--- /dev/null ++++ b/alliance/src/cells/src/msxlib/vfeed4.vbe +@@ -0,0 +1,18 @@ ++ENTITY vfeed4 IS ++GENERIC ( ++ CONSTANT area : NATURAL := 4000; ++ CONSTANT transistors : NATURAL := 0 ++); ++PORT ( ++ vdd : in BIT; ++ vss : in BIT ++); ++END vfeed4; ++ ++ARCHITECTURE behaviour_data_flow OF vfeed4 IS ++ ++BEGIN ++ ASSERT (vdd and not (vss)) ++ REPORT "power supply is missing on vfeed4" ++ SEVERITY WARNING; ++END; +diff --git a/alliance/src/cells/src/msxlib/vfeed5.ap b/alliance/src/cells/src/msxlib/vfeed5.ap +new file mode 100644 +index 0000000..fdafd35 +--- /dev/null ++++ b/alliance/src/cells/src/msxlib/vfeed5.ap +@@ -0,0 +1,21 @@ ++V ALLIANCE : 6 ++H vfeed5,P, 9/ 8/2014,100 ++A 0,0,5000,10000 ++S 0,5000,5000,5000,10000,vfeed5,LEFT,TALU8 ++S 0,2200,5000,2200,5200,*,LEFT,PWELL ++S 0,7600,5000,7600,5600,*,LEFT,NWELL ++S 0,600,5000,600,1200,vss,RIGHT,CALU1 ++S 0,9400,5000,9400,1200,vdd,RIGHT,CALU1 ++S 2500,5700,2500,9500,4400,*,UP,NTIE ++S 2500,500,2500,3700,4400,*,DOWN,PTIE ++V 3500,9300,CONT_BODY_N,* ++V 2500,9300,CONT_BODY_N,* ++V 1500,9300,CONT_BODY_N,* ++V 4300,9300,CONT_BODY_N,* ++V 700,9300,CONT_BODY_N,* ++V 2500,700,CONT_BODY_P,* ++V 3500,700,CONT_BODY_P,* ++V 4300,700,CONT_BODY_P,* ++V 1500,700,CONT_BODY_P,* ++V 700,700,CONT_BODY_P,* ++EOF +diff --git a/alliance/src/cells/src/msxlib/vfeed5.vbe b/alliance/src/cells/src/msxlib/vfeed5.vbe +new file mode 100644 +index 0000000..57242e7 +--- /dev/null ++++ b/alliance/src/cells/src/msxlib/vfeed5.vbe +@@ -0,0 +1,18 @@ ++ENTITY vfeed5 IS ++GENERIC ( ++ CONSTANT area : NATURAL := 5000; ++ CONSTANT transistors : NATURAL := 0 ++); ++PORT ( ++ vdd : in BIT; ++ vss : in BIT ++); ++END vfeed5; ++ ++ARCHITECTURE behaviour_data_flow OF vfeed5 IS ++ ++BEGIN ++ ASSERT (vdd and not (vss)) ++ REPORT "power supply is missing on vfeed5" ++ SEVERITY WARNING; ++END; +diff --git a/alliance/src/cells/src/msxlib/vfeed6.ap b/alliance/src/cells/src/msxlib/vfeed6.ap +new file mode 100644 +index 0000000..5ea319b +--- /dev/null ++++ b/alliance/src/cells/src/msxlib/vfeed6.ap +@@ -0,0 +1,23 @@ ++V ALLIANCE : 6 ++H vfeed6,P, 9/ 8/2014,100 ++A 0,0,6000,10000 ++S 0,5000,6000,5000,10000,vfeed6,LEFT,TALU8 ++S 0,2200,6000,2200,5200,*,LEFT,PWELL ++S 0,7600,6000,7600,5600,*,LEFT,NWELL ++S 0,600,6000,600,1200,vss,RIGHT,CALU1 ++S 0,9400,6000,9400,1200,vdd,RIGHT,CALU1 ++S 3000,500,3000,3700,5400,*,DOWN,PTIE ++S 3000,5700,3000,9500,5400,*,UP,NTIE ++V 1500,700,CONT_BODY_P,* ++V 2500,700,CONT_BODY_P,* ++V 3500,700,CONT_BODY_P,* ++V 4500,700,CONT_BODY_P,* ++V 5300,700,CONT_BODY_P,* ++V 700,700,CONT_BODY_P,* ++V 1500,9300,CONT_BODY_N,* ++V 2500,9300,CONT_BODY_N,* ++V 3500,9300,CONT_BODY_N,* ++V 4500,9300,CONT_BODY_N,* ++V 5300,9300,CONT_BODY_N,* ++V 700,9300,CONT_BODY_N,* ++EOF +diff --git a/alliance/src/cells/src/msxlib/vfeed6.vbe b/alliance/src/cells/src/msxlib/vfeed6.vbe +new file mode 100644 +index 0000000..a603a3a +--- /dev/null ++++ b/alliance/src/cells/src/msxlib/vfeed6.vbe +@@ -0,0 +1,18 @@ ++ENTITY vfeed6 IS ++GENERIC ( ++ CONSTANT area : NATURAL := 6000; ++ CONSTANT transistors : NATURAL := 0 ++); ++PORT ( ++ vdd : in BIT; ++ vss : in BIT ++); ++END vfeed6; ++ ++ARCHITECTURE behaviour_data_flow OF vfeed6 IS ++ ++BEGIN ++ ASSERT (vdd and not (vss)) ++ REPORT "power supply is missing on vfeed6" ++ SEVERITY WARNING; ++END; +diff --git a/alliance/src/cells/src/msxlib/vfeed7.ap b/alliance/src/cells/src/msxlib/vfeed7.ap +new file mode 100644 +index 0000000..d01c623 +--- /dev/null ++++ b/alliance/src/cells/src/msxlib/vfeed7.ap +@@ -0,0 +1,25 @@ ++V ALLIANCE : 6 ++H vfeed7,P, 9/ 8/2014,100 ++A 0,0,7000,10000 ++S 0,5000,7000,5000,10000,vfeed7,LEFT,TALU8 ++S 0,2200,7000,2200,5200,*,LEFT,PWELL ++S 0,7600,7000,7600,5600,*,LEFT,NWELL ++S 0,600,7000,600,1200,vss,RIGHT,CALU1 ++S 0,9400,7000,9400,1200,vdd,RIGHT,CALU1 ++S 3500,5700,3500,9500,6400,*,UP,NTIE ++S 3500,500,3500,3700,6400,*,DOWN,PTIE ++V 1500,700,CONT_BODY_P,* ++V 2500,700,CONT_BODY_P,* ++V 3500,700,CONT_BODY_P,* ++V 4500,700,CONT_BODY_P,* ++V 5500,700,CONT_BODY_P,* ++V 6300,700,CONT_BODY_P,* ++V 700,700,CONT_BODY_P,* ++V 1500,9300,CONT_BODY_N,* ++V 2500,9300,CONT_BODY_N,* ++V 3500,9300,CONT_BODY_N,* ++V 4500,9300,CONT_BODY_N,* ++V 5500,9300,CONT_BODY_N,* ++V 6300,9300,CONT_BODY_N,* ++V 700,9300,CONT_BODY_N,* ++EOF +diff --git a/alliance/src/cells/src/msxlib/vfeed7.vbe b/alliance/src/cells/src/msxlib/vfeed7.vbe +new file mode 100644 +index 0000000..94fa2ee +--- /dev/null ++++ b/alliance/src/cells/src/msxlib/vfeed7.vbe +@@ -0,0 +1,18 @@ ++ENTITY vfeed7 IS ++GENERIC ( ++ CONSTANT area : NATURAL := 7000; ++ CONSTANT transistors : NATURAL := 0 ++); ++PORT ( ++ vdd : in BIT; ++ vss : in BIT ++); ++END vfeed7; ++ ++ARCHITECTURE behaviour_data_flow OF vfeed7 IS ++ ++BEGIN ++ ASSERT (vdd and not (vss)) ++ REPORT "power supply is missing on vfeed7" ++ SEVERITY WARNING; ++END; +diff --git a/alliance/src/cells/src/msxlib/vfeed8.ap b/alliance/src/cells/src/msxlib/vfeed8.ap +new file mode 100644 +index 0000000..d4f75bd +--- /dev/null ++++ b/alliance/src/cells/src/msxlib/vfeed8.ap +@@ -0,0 +1,27 @@ ++V ALLIANCE : 6 ++H vfeed8,P, 9/ 8/2014,100 ++A 0,0,8000,10000 ++S 0,5000,8000,5000,10000,vfeed8,LEFT,TALU8 ++S 0,2200,8000,2200,5200,*,LEFT,PWELL ++S 0,7600,8000,7600,5600,*,LEFT,NWELL ++S 0,600,8000,600,1200,vss,RIGHT,CALU1 ++S 0,9400,8000,9400,1200,vdd,RIGHT,CALU1 ++S 4000,500,4000,3700,7400,*,DOWN,PTIE ++S 4000,5700,4000,9500,7400,*,UP,NTIE ++V 1500,9300,CONT_BODY_N,* ++V 2500,9300,CONT_BODY_N,* ++V 3500,9300,CONT_BODY_N,* ++V 4500,9300,CONT_BODY_N,* ++V 5500,9300,CONT_BODY_N,* ++V 6500,9300,CONT_BODY_N,* ++V 6500,700,CONT_BODY_P,* ++V 5500,700,CONT_BODY_P,* ++V 4500,700,CONT_BODY_P,* ++V 3500,700,CONT_BODY_P,* ++V 2500,700,CONT_BODY_P,* ++V 1500,700,CONT_BODY_P,* ++V 700,700,CONT_BODY_P,* ++V 7300,700,CONT_BODY_P,* ++V 7300,9300,CONT_BODY_N,* ++V 700,9300,CONT_BODY_N,* ++EOF +diff --git a/alliance/src/cells/src/msxlib/vfeed8.vbe b/alliance/src/cells/src/msxlib/vfeed8.vbe +new file mode 100644 +index 0000000..01c51c3 +--- /dev/null ++++ b/alliance/src/cells/src/msxlib/vfeed8.vbe +@@ -0,0 +1,18 @@ ++ENTITY vfeed8 IS ++GENERIC ( ++ CONSTANT area : NATURAL := 8000; ++ CONSTANT transistors : NATURAL := 0 ++); ++PORT ( ++ vdd : in BIT; ++ vss : in BIT ++); ++END vfeed8; ++ ++ARCHITECTURE behaviour_data_flow OF vfeed8 IS ++ ++BEGIN ++ ASSERT (vdd and not (vss)) ++ REPORT "power supply is missing on vfeed8" ++ SEVERITY WARNING; ++END; +diff --git a/alliance/src/cells/src/msxlib/vsstie.ap b/alliance/src/cells/src/msxlib/vsstie.ap +new file mode 100644 +index 0000000..2dd552a +--- /dev/null ++++ b/alliance/src/cells/src/msxlib/vsstie.ap +@@ -0,0 +1,54 @@ ++V ALLIANCE : 6 ++H vsstie,P,17/ 8/2004,100 ++A 0,0,3000,10000 ++R 2000,8000,ref_ref,z_80 ++R 2000,7000,ref_ref,z_70 ++R 2000,6000,ref_ref,z_60 ++R 2000,5000,ref_ref,z_50 ++R 2000,4000,ref_ref,z_40 ++R 2000,3000,ref_ref,z_30 ++R 2000,2000,ref_ref,z_20 ++R 1000,4000,ref_ref,z_40 ++S 0,7600,3000,7600,5600,*,LEFT,NWELL ++S 0,2200,3000,2200,5200,*,LEFT,PWELL ++S 0,5000,3000,5000,10000,vsstie,LEFT,TALU8 ++S 0,600,3000,600,1200,vss,RIGHT,CALU1 ++S 0,9400,3000,9400,1200,vdd,RIGHT,CALU1 ++S 2000,2000,2000,8000,400,z,DOWN,CALU1 ++S 1400,3900,1400,5500,200,*,DOWN,POLY ++S 700,1800,700,3700,600,*,UP,NDIF ++S 2100,1800,2100,3700,600,*,DOWN,NDIF ++S 1400,1200,1400,1600,200,*,DOWN,POLY ++S 1400,1600,1400,3900,200,2,DOWN,NTRANS ++S 600,600,2400,600,600,*,RIGHT,PTIE ++S 600,9400,2400,9400,600,*,RIGHT,NTIE ++S 2100,5700,2100,8300,600,*,UP,PDIF ++S 1400,5500,1400,8500,200,1,UP,PTRANS ++S 700,5700,700,8300,600,*,UP,PDIF ++S 1400,8500,1400,8800,200,*,UP,POLY ++S 2000,1900,2000,8100,400,*,DOWN,ALU1 ++S 800,700,800,2900,400,*,DOWN,ALU1 ++S 800,4800,800,9300,400,*,UP,ALU1 ++S 800,4900,1400,4900,600,*,RIGHT,POLY ++S 1000,4000,1000,4000,400,z,LEFT,CALU1 ++S 800,4000,2000,4000,400,*,LEFT,ALU1 ++V 2000,5800,CONT_DIF_P,* ++V 2000,6600,CONT_DIF_P,* ++V 2000,7400,CONT_DIF_P,* ++V 2000,3600,CONT_DIF_N,* ++V 2000,2800,CONT_DIF_N,* ++V 2000,2000,CONT_DIF_N,* ++V 700,600,CONT_BODY_P,* ++V 1500,600,CONT_BODY_P,* ++V 2300,600,CONT_BODY_P,* ++V 700,9400,CONT_BODY_N,* ++V 1500,9400,CONT_BODY_N,* ++V 2300,9400,CONT_BODY_N,* ++V 800,8200,CONT_DIF_P,* ++V 800,7400,CONT_DIF_P,* ++V 800,6600,CONT_DIF_P,* ++V 800,5800,CONT_DIF_P,* ++V 800,2800,CONT_DIF_N,* ++V 800,2000,CONT_DIF_N,* ++V 800,4900,CONT_POLY,* ++EOF +diff --git a/alliance/src/cells/src/msxlib/vsstie.vbe b/alliance/src/cells/src/msxlib/vsstie.vbe +new file mode 100644 +index 0000000..9f430c7 +--- /dev/null ++++ b/alliance/src/cells/src/msxlib/vsstie.vbe +@@ -0,0 +1,20 @@ ++ENTITY vsstie IS ++GENERIC ( ++ CONSTANT area : NATURAL := 3000; ++ CONSTANT transistors : NATURAL := 0 ++); ++PORT ( ++ z : out BIT; ++ vdd : in BIT; ++ vss : in BIT ++); ++END vsstie; ++ ++ARCHITECTURE behaviour_data_flow OF vsstie IS ++ ++BEGIN ++ ASSERT (vdd and not (vss)) ++ REPORT "power supply is missing on vsstie" ++ SEVERITY WARNING; ++ z <= '0'; ++END; +diff --git a/alliance/src/cells/src/msxlib/xaoi21_x05.ap b/alliance/src/cells/src/msxlib/xaoi21_x05.ap +new file mode 100644 +index 0000000..aa036e2 +--- /dev/null ++++ b/alliance/src/cells/src/msxlib/xaoi21_x05.ap +@@ -0,0 +1,142 @@ ++V ALLIANCE : 6 ++H xaoi21_x05,P, 9/ 8/2014,100 ++A 0,0,8000,10000 ++R 4000,8000,ref_ref,b_80 ++R 5000,8000,ref_ref,b_80 ++R 6000,8000,ref_ref,b_80 ++R 6000,7000,ref_ref,b_70 ++R 5000,2000,ref_ref,z_20 ++R 5000,3000,ref_ref,z_30 ++R 5000,4000,ref_ref,z_40 ++R 4000,4000,ref_ref,z_40 ++R 4000,5000,ref_ref,z_50 ++R 4000,6000,ref_ref,z_60 ++R 2000,6000,ref_ref,a2_60 ++R 3000,6000,ref_ref,a2_60 ++R 3000,5000,ref_ref,a2_50 ++R 3000,4000,ref_ref,a2_40 ++R 4000,3000,ref_ref,a1_30 ++R 3000,3000,ref_ref,a1_30 ++R 2000,3000,ref_ref,a1_30 ++R 2000,4000,ref_ref,a1_40 ++R 2000,5000,ref_ref,a1_50 ++S 1100,9300,1900,9300,600,*,RIGHT,NTIE ++S 3100,700,3900,700,600,*,RIGHT,PTIE ++S 6000,1900,6000,5100,400,*,UP,ALU1 ++S 5000,8000,5000,8000,400,b,LEFT,CALU1 ++S 4000,8000,4000,8000,400,b,LEFT,CALU1 ++S 6000,7000,6000,8000,400,b,DOWN,CALU1 ++S 6000,6900,6600,6900,400,*,RIGHT,ALU1 ++S 3300,8000,6000,8000,400,*,LEFT,ALU1 ++S 3300,8100,6000,8100,400,*,LEFT,ALU1 ++S 6600,5900,6600,6900,400,*,UP,ALU1 ++S 6000,6900,6000,8100,400,*,DOWN,ALU1 ++S 5000,6000,5000,7000,400,*,UP,ALU1 ++S 5000,6000,5700,6000,400,*,LEFT,ALU1 ++S 700,7000,5000,7000,400,*,RIGHT,ALU1 ++S 3600,5100,3600,5500,200,*,DOWN,POLY ++S 2200,1300,2200,1700,200,*,DOWN,POLY ++S 3000,1300,3000,1700,200,*,DOWN,POLY ++S 4200,1300,4200,1700,200,*,DOWN,POLY ++S 5400,1300,5400,1700,200,*,DOWN,POLY ++S 6600,1300,6600,1700,200,*,DOWN,POLY ++S 6800,8700,6800,9100,200,*,UP,POLY ++S 5600,8700,5600,9100,200,*,UP,POLY ++S 4800,8700,4800,9100,200,*,UP,POLY ++S 2400,7500,2400,7900,200,*,UP,POLY ++S 1200,7500,1200,7900,200,*,UP,POLY ++S 1800,7900,1800,9300,400,*,UP,ALU1 ++S 7400,5100,7400,7900,400,*,DOWN,ALU1 ++S 6000,5100,7400,5100,400,*,LEFT,ALU1 ++S 5000,5000,6000,5000,600,*,RIGHT,ALU1 ++S 4000,5700,4000,7300,400,*,UP,PDIF ++S 4200,5900,4200,7300,600,*,UP,PDIF ++S 7200,6900,7200,8500,400,*,DOWN,PDIF ++S 4400,6900,4400,8500,400,*,DOWN,PDIF ++S 800,5700,800,7300,400,*,DOWN,PDIF ++S 6200,6900,6200,9100,600,*,DOWN,PDIF ++S 7200,700,7200,2100,400,*,DOWN,ALU1 ++S 7200,1900,7200,2400,600,*,UP,NDIF ++S 7300,1900,7300,2400,600,*,UP,NDIF ++S 6600,2600,6600,6000,200,*,UP,POLY ++S 6000,1900,6000,2400,600,*,UP,NDIF ++S 4000,4000,4000,6000,400,z,UP,CALU1 ++S 5000,2000,5000,4000,400,z,UP,CALU1 ++S 4000,4000,5000,4000,600,*,RIGHT,ALU1 ++S 4900,1900,4900,4000,600,*,DOWN,ALU1 ++S 3000,5700,3000,7300,600,*,DOWN,PDIF ++S 1800,5700,1800,8100,600,*,DOWN,PDIF ++S 600,5900,600,6500,600,*,UP,PDIF ++S 2000,6000,2000,6000,400,a2,LEFT,CALU1 ++S 3000,4000,3000,6000,400,a2,UP,CALU1 ++S 2000,6000,3000,6000,600,*,LEFT,ALU1 ++S 2000,2900,2000,5100,400,*,UP,ALU1 ++S 3000,3000,3000,3000,400,a1,LEFT,CALU1 ++S 4000,3000,4000,3000,400,a1,LEFT,CALU1 ++S 2000,3000,2000,5000,400,a1,DOWN,CALU1 ++S 2400,4500,2400,5500,200,*,DOWN,POLY ++S 3000,4000,3000,4300,200,*,DOWN,POLY ++S 2400,4500,3000,4500,200,*,RIGHT,POLY ++S 2000,3000,4000,3000,600,*,LEFT,ALU1 ++S 3000,3900,3000,6100,400,*,UP,ALU1 ++S 5800,3000,5800,6000,200,*,DOWN,POLY ++S 5400,3000,5800,3000,200,*,RIGHT,POLY ++S 4100,4000,4100,6100,600,*,DOWN,ALU1 ++S 600,2000,600,7000,400,*,DOWN,ALU1 ++S 600,2000,3700,2000,400,*,RIGHT,ALU1 ++S 7400,7100,7400,7700,600,*,UP,PDIF ++S 0,9400,8000,9400,1200,vdd,RIGHT,CALU1 ++S 0,5000,8000,5000,10000,xaoi21_x05,LEFT,TALU8 ++S 0,2200,8000,2200,5200,*,LEFT,PWELL ++S 0,7600,8000,7600,5600,*,LEFT,NWELL ++S 0,600,8000,600,1200,vss,RIGHT,CALU1 ++S 6800,6000,6800,6700,200,*,DOWN,POLY ++S 5600,6000,5600,6700,200,*,DOWN,POLY ++S 5100,6900,5100,8500,400,n1,DOWN,PDIF ++S 4200,4500,4800,4500,200,*,RIGHT,POLY ++S 4800,4500,4800,6700,200,*,DOWN,POLY ++S 4200,2900,4200,4500,200,*,UP,POLY ++S 3600,1900,3600,2700,600,*,UP,NDIF ++S 3000,2900,3000,4000,200,*,UP,POLY ++S 2600,1900,2600,2700,400,n2,UP,NDIF ++S 1500,900,1500,2700,600,*,UP,NDIF ++S 1600,900,1600,2700,600,*,UP,NDIF ++S 1200,3700,2200,3700,200,*,RIGHT,POLY ++S 1200,3700,1200,5500,200,*,DOWN,POLY ++S 4600,1900,4600,2700,400,*,UP,NDIF ++S 4800,1900,4800,2400,600,*,UP,NDIF ++S 6800,6700,6800,8700,200,1b,DOWN,PTRANS ++S 1200,5500,1200,7500,200,1a,DOWN,PTRANS ++S 2200,1700,2200,2900,200,2a,UP,NTRANS ++S 2400,5500,2400,7500,200,3a,DOWN,PTRANS ++S 3000,1700,3000,2900,200,4a,UP,NTRANS ++S 3600,5500,3600,7500,200,2b,DOWN,PTRANS ++S 6600,1700,6600,2600,200,3b,UP,NTRANS ++S 4800,6700,4800,8700,200,2z,DOWN,PTRANS ++S 5600,6700,5600,8700,200,1z,DOWN,PTRANS ++S 5400,1700,5400,2600,200,3z,UP,NTRANS ++S 4200,1700,4200,2900,200,4z,UP,NTRANS ++V 2000,9300,CONT_BODY_N,* ++V 1000,9300,CONT_BODY_N,* ++V 4000,700,CONT_BODY_P,* ++V 3000,700,CONT_BODY_P,* ++V 6000,2000,CONT_DIF_N,bn ++V 4800,2000,CONT_DIF_N,* ++V 5000,5000,CONT_POLY,bn ++V 7200,2000,CONT_DIF_N,* ++V 3000,4300,CONT_POLY,* ++V 3600,2000,CONT_DIF_N,an ++V 6600,6000,CONT_POLY,* ++V 5600,6000,CONT_POLY,an ++V 1600,1000,CONT_DIF_N,* ++V 600,6600,CONT_DIF_P,an ++V 600,5800,CONT_DIF_P,an ++V 1800,8000,CONT_DIF_P,* ++V 3000,7000,CONT_DIF_P,an ++V 4200,6000,CONT_DIF_P,* ++V 3400,8100,CONT_POLY,* ++V 7400,7000,CONT_DIF_P,bn ++V 7400,7800,CONT_DIF_P,bn ++V 6200,9000,CONT_DIF_P,* ++V 2000,3500,CONT_POLY,* ++EOF +diff --git a/alliance/src/cells/src/msxlib/xaoi21_x05.vbe b/alliance/src/cells/src/msxlib/xaoi21_x05.vbe +new file mode 100644 +index 0000000..a74687d +--- /dev/null ++++ b/alliance/src/cells/src/msxlib/xaoi21_x05.vbe +@@ -0,0 +1,44 @@ ++ENTITY xaoi21_x05 IS ++GENERIC ( ++ CONSTANT area : NATURAL := 8000; ++ CONSTANT cin_b : NATURAL := 6; ++ CONSTANT cin_a1 : NATURAL := 5; ++ CONSTANT cin_a2 : NATURAL := 4; ++ CONSTANT rdown_b_z : NATURAL := 3960; ++ CONSTANT rdown_a1_z : NATURAL := 3890; ++ CONSTANT rdown_a2_z : NATURAL := 3890; ++ CONSTANT rup_b_z : NATURAL := 3690; ++ CONSTANT rup_a1_z : NATURAL := 4780; ++ CONSTANT rup_a2_z : NATURAL := 4770; ++ CONSTANT tphl_a1_z : NATURAL := 83; ++ CONSTANT tphl_a2_z : NATURAL := 84; ++ CONSTANT tphl_b_z : NATURAL := 68; ++ CONSTANT tplh_b_z : NATURAL := 42; ++ CONSTANT tplh_a1_z : NATURAL := 88; ++ CONSTANT tplh_a2_z : NATURAL := 83; ++ CONSTANT tphh_b_z : NATURAL := 87; ++ CONSTANT tpll_b_z : NATURAL := 66; ++ CONSTANT tphh_a1_z : NATURAL := 120; ++ CONSTANT tphh_a2_z : NATURAL := 121; ++ CONSTANT tpll_a1_z : NATURAL := 118; ++ CONSTANT tpll_a2_z : NATURAL := 111; ++ CONSTANT transistors : NATURAL := 11 ++); ++PORT ( ++ b : in BIT; ++ a1 : in BIT; ++ a2 : in BIT; ++ z : out BIT; ++ vdd : in BIT; ++ vss : in BIT ++); ++END xaoi21_x05; ++ ++ARCHITECTURE behaviour_data_flow OF xaoi21_x05 IS ++ ++BEGIN ++ ASSERT ((vdd and not (vss)) = '1') ++ REPORT "power supply is missing on xaoi21_x05" ++ SEVERITY WARNING; ++ z <= not ((b xor (a1 and a2))) after 1100 ps; ++END; +diff --git a/alliance/src/cells/src/msxlib/xaoi21_x1.ap b/alliance/src/cells/src/msxlib/xaoi21_x1.ap +new file mode 100644 +index 0000000..8d1d5ea +--- /dev/null ++++ b/alliance/src/cells/src/msxlib/xaoi21_x1.ap +@@ -0,0 +1,146 @@ ++V ALLIANCE : 6 ++H xaoi21_x1,P, 9/ 8/2014,100 ++A 0,0,9000,10000 ++R 2000,5000,ref_ref,a1_50 ++R 2000,4000,ref_ref,a1_40 ++R 2000,3000,ref_ref,a1_30 ++R 3000,3000,ref_ref,a1_30 ++R 4000,3000,ref_ref,a1_30 ++R 3000,4000,ref_ref,a2_40 ++R 3000,5000,ref_ref,a2_50 ++R 3000,6000,ref_ref,a2_60 ++R 2000,6000,ref_ref,a2_60 ++R 7000,7000,ref_ref,b_70 ++R 7000,8000,ref_ref,b_80 ++R 6000,8000,ref_ref,b_80 ++R 5000,8000,ref_ref,b_80 ++R 4000,8000,ref_ref,b_80 ++R 5000,6000,ref_ref,z_60 ++R 5000,5000,ref_ref,z_50 ++R 5000,4000,ref_ref,z_40 ++R 5000,3000,ref_ref,z_30 ++R 5000,2000,ref_ref,z_20 ++R 7000,6000,ref_ref,b_60 ++R 4000,5000,ref_ref,z_50 ++S 600,2000,3700,2000,400,*,RIGHT,ALU1 ++S 600,2000,600,7000,400,*,DOWN,ALU1 ++S 3000,3900,3000,6100,400,*,UP,ALU1 ++S 2000,3000,4000,3000,600,*,LEFT,ALU1 ++S 2400,4500,3000,4500,200,*,RIGHT,POLY ++S 3000,4000,3000,4300,200,*,DOWN,POLY ++S 2400,4500,2400,5500,200,*,DOWN,POLY ++S 2000,3000,2000,5000,400,a1,DOWN,CALU1 ++S 4000,3000,4000,3000,400,a1,LEFT,CALU1 ++S 3000,3000,3000,3000,400,a1,LEFT,CALU1 ++S 2000,2900,2000,5100,400,*,UP,ALU1 ++S 2000,6000,3000,6000,600,*,LEFT,ALU1 ++S 3000,4000,3000,6000,400,a2,UP,CALU1 ++S 2000,6000,2000,6000,400,a2,LEFT,CALU1 ++S 0,9400,9000,9400,1200,vdd,RIGHT,CALU1 ++S 6000,8000,6000,8000,400,b,LEFT,CALU1 ++S 5000,8000,5000,8000,400,b,LEFT,CALU1 ++S 0,5000,9000,5000,10000,xaoi21_x1,LEFT,TALU8 ++S 0,2200,9000,2200,5200,*,LEFT,PWELL ++S 0,7600,9000,7600,5600,*,LEFT,NWELL ++S 600,7900,600,9300,400,*,UP,ALU1 ++S 4600,5100,4600,5500,200,*,DOWN,POLY ++S 3400,8000,7000,8000,400,*,LEFT,ALU1 ++S 4000,8000,4000,8000,400,b,LEFT,CALU1 ++S 4600,5500,4600,9300,200,2b,DOWN,PTRANS ++S 3700,8000,3700,9700,200,*,UP,POLY ++S 3700,9700,4600,9700,200,*,RIGHT,POLY ++S 4200,5700,4200,9100,400,*,UP,PDIF ++S 2400,9300,2400,9700,200,*,UP,POLY ++S 1200,9300,1200,9700,200,*,UP,POLY ++S 2400,5500,2400,9300,200,3a,DOWN,PTRANS ++S 2800,5700,2800,9100,400,*,DOWN,PDIF ++S 1200,5500,1200,9300,200,1a,DOWN,PTRANS ++S 1800,5700,1800,9100,600,*,DOWN,PDIF ++S 600,5700,600,9100,600,*,DOWN,PDIF ++S 1800,7000,1800,7900,400,*,UP,ALU1 ++S 600,7000,6000,7000,400,*,RIGHT,ALU1 ++S 5800,9300,5800,9700,200,*,UP,POLY ++S 6600,9300,6600,9700,200,*,UP,POLY ++S 7800,9300,7800,9700,200,*,UP,POLY ++S 8200,6900,8200,9100,400,*,DOWN,PDIF ++S 5000,2000,5000,6000,400,z,UP,CALU1 ++S 6600,5500,6600,9300,200,1z,DOWN,PTRANS ++S 5800,5500,5800,9300,200,2z,DOWN,PTRANS ++S 7200,5700,7200,9100,600,*,DOWN,PDIF ++S 7800,5500,7800,9300,200,1b,DOWN,PTRANS ++S 8400,5900,8400,6500,600,*,UP,PDIF ++S 7000,6000,7000,8000,400,b,DOWN,CALU1 ++S 6000,4900,6000,7000,400,*,UP,ALU1 ++S 8400,3900,8400,6700,400,*,DOWN,ALU1 ++S 7000,6000,7600,6000,400,*,RIGHT,ALU1 ++S 7000,6000,7000,8000,600,*,DOWN,ALU1 ++S 7600,4800,7600,6000,400,*,UP,ALU1 ++S 0,600,9000,600,1200,vss,RIGHT,CALU1 ++S 5000,1900,5000,6100,400,*,DOWN,ALU1 ++S 5000,6000,5200,6000,600,*,LEFT,ALU1 ++S 4800,2000,5000,2000,600,*,RIGHT,ALU1 ++S 6700,3900,8400,3900,400,*,LEFT,ALU1 ++S 5800,4100,5800,5500,200,*,DOWN,POLY ++S 4200,4100,6400,4100,200,*,RIGHT,POLY ++S 5800,3200,5800,4900,400,*,UP,ALU1 ++S 5800,4900,6700,4900,400,*,LEFT,ALU1 ++S 6600,700,6600,2400,200,3b,UP,NTRANS ++S 5400,700,5400,2400,200,3z,UP,NTRANS ++S 4600,900,4600,2900,400,*,UP,NDIF ++S 4200,700,4200,3100,200,4z,UP,NTRANS ++S 2600,900,2600,2900,400,n2,UP,NDIF ++S 2200,700,2200,3100,200,2a,UP,NTRANS ++S 3000,700,3000,3100,200,4a,UP,NTRANS ++S 1600,900,1600,2900,600,*,UP,NDIF ++S 1500,900,1500,2900,600,*,UP,NDIF ++S 3600,900,3600,2900,600,*,UP,NDIF ++S 4800,900,4800,2200,600,*,UP,NDIF ++S 6000,900,6000,2200,600,*,UP,NDIF ++S 7200,900,7200,2200,600,*,UP,NDIF ++S 6600,2800,7600,2800,200,*,RIGHT,POLY ++S 7600,2800,7600,5000,200,*,UP,POLY ++S 5200,5700,5200,9100,600,*,UP,PDIF ++S 4000,6300,4000,6900,600,*,DOWN,PDIF ++S 4000,6100,4000,7000,400,*,UP,ALU1 ++S 4000,5000,4000,5000,400,z,LEFT,CALU1 ++S 3900,5000,5000,5000,400,*,RIGHT,ALU1 ++S 1200,3900,2200,3900,200,*,RIGHT,POLY ++S 1200,3900,1200,5500,200,*,DOWN,POLY ++S 3000,3100,3000,4000,200,*,UP,POLY ++S 4200,3100,4200,4100,200,*,UP,POLY ++S 5400,2400,5400,3500,200,*,UP,POLY ++S 2200,300,2200,700,200,*,DOWN,POLY ++S 3000,300,3000,700,200,*,DOWN,POLY ++S 4200,300,4200,700,200,*,DOWN,POLY ++S 5400,300,5400,700,200,*,DOWN,POLY ++S 6600,300,6600,700,200,*,DOWN,POLY ++S 6600,2000,6600,3900,400,*,UP,ALU1 ++S 5900,2000,6600,2000,400,*,RIGHT,ALU1 ++S 7400,700,7400,2100,400,*,UP,ALU1 ++S 7500,1800,7500,2200,600,*,DOWN,NDIF ++V 8300,700,CONT_BODY_P,* ++V 1600,1000,CONT_DIF_N,* ++V 3600,2000,CONT_DIF_N,an ++V 3000,4300,CONT_POLY,* ++V 7200,9000,CONT_DIF_P,* ++V 600,8000,CONT_DIF_P,* ++V 1800,7000,CONT_DIF_P,an ++V 5200,6000,CONT_DIF_P,* ++V 4000,7000,CONT_DIF_P,an ++V 3000,9000,CONT_DIF_P,* ++V 3500,8000,CONT_POLY,* ++V 600,9000,CONT_DIF_P,* ++V 1800,7800,CONT_DIF_P,an ++V 4800,2000,CONT_DIF_N,* ++V 8400,5800,CONT_DIF_P,bn ++V 8400,6600,CONT_DIF_P,bn ++V 6600,4900,CONT_POLY,an ++V 7600,4900,CONT_POLY,* ++V 5800,3300,CONT_POLY,an ++V 6000,2000,CONT_DIF_N,bn ++V 7200,1000,CONT_DIF_N,* ++V 6800,3900,CONT_POLY,bn ++V 4000,6200,CONT_DIF_P,an ++V 2000,3700,CONT_POLY,* ++V 7400,2000,CONT_DIF_N,* ++EOF +diff --git a/alliance/src/cells/src/msxlib/xaoi21_x1.vbe b/alliance/src/cells/src/msxlib/xaoi21_x1.vbe +new file mode 100644 +index 0000000..2c54cf0 +--- /dev/null ++++ b/alliance/src/cells/src/msxlib/xaoi21_x1.vbe +@@ -0,0 +1,44 @@ ++ENTITY xaoi21_x1 IS ++GENERIC ( ++ CONSTANT area : NATURAL := 9000; ++ CONSTANT cin_b : NATURAL := 11; ++ CONSTANT cin_a1 : NATURAL := 8; ++ CONSTANT cin_a2 : NATURAL := 8; ++ CONSTANT rdown_b_z : NATURAL := 2070; ++ CONSTANT rdown_a1_z : NATURAL := 2010; ++ CONSTANT rdown_a2_z : NATURAL := 2010; ++ CONSTANT rup_b_z : NATURAL := 1940; ++ CONSTANT rup_a1_z : NATURAL := 2500; ++ CONSTANT rup_a2_z : NATURAL := 2500; ++ CONSTANT tphl_a1_z : NATURAL := 74; ++ CONSTANT tphl_a2_z : NATURAL := 75; ++ CONSTANT tphl_b_z : NATURAL := 63; ++ CONSTANT tplh_b_z : NATURAL := 39; ++ CONSTANT tplh_a1_z : NATURAL := 82; ++ CONSTANT tplh_a2_z : NATURAL := 77; ++ CONSTANT tphh_b_z : NATURAL := 79; ++ CONSTANT tpll_b_z : NATURAL := 60; ++ CONSTANT tphh_a1_z : NATURAL := 110; ++ CONSTANT tphh_a2_z : NATURAL := 111; ++ CONSTANT tpll_a1_z : NATURAL := 112; ++ CONSTANT tpll_a2_z : NATURAL := 105; ++ CONSTANT transistors : NATURAL := 11 ++); ++PORT ( ++ b : in BIT; ++ a1 : in BIT; ++ a2 : in BIT; ++ z : out BIT; ++ vdd : in BIT; ++ vss : in BIT ++); ++END xaoi21_x1; ++ ++ARCHITECTURE behaviour_data_flow OF xaoi21_x1 IS ++ ++BEGIN ++ ASSERT ((vdd and not (vss)) = '1') ++ REPORT "power supply is missing on xaoi21_x1" ++ SEVERITY WARNING; ++ z <= not ((b xor (a1 and a2))) after 1100 ps; ++END; +diff --git a/alliance/src/cells/src/msxlib/xaon21_x05.ap b/alliance/src/cells/src/msxlib/xaon21_x05.ap +new file mode 100644 +index 0000000..8b813d0 +--- /dev/null ++++ b/alliance/src/cells/src/msxlib/xaon21_x05.ap +@@ -0,0 +1,131 @@ ++V ALLIANCE : 6 ++H xaon21_x05,P, 9/ 8/2014,100 ++A 0,0,8000,10000 ++R 1000,3000,ref_ref,a1_30 ++R 1000,4000,ref_ref,a1_40 ++R 3000,3000,ref_ref,z_30 ++R 2000,3000,ref_ref,a1_30 ++R 3000,6000,ref_ref,a2_60 ++R 4000,4000,ref_ref,z_40 ++R 4000,5000,ref_ref,z_50 ++R 4000,6000,ref_ref,z_60 ++R 4000,3000,ref_ref,z_30 ++R 6000,2000,ref_ref,b_20 ++R 6000,3000,ref_ref,b_30 ++R 6000,4000,ref_ref,b_40 ++R 2000,6000,ref_ref,a2_60 ++R 3000,5000,ref_ref,a2_50 ++R 3000,4000,ref_ref,a2_40 ++R 7000,2000,ref_ref,b_20 ++R 1000,2000,ref_ref,a1_20 ++S 1100,9300,1900,9300,600,*,RIGHT,NTIE ++S 3200,400,6800,400,200,*,RIGHT,POLY ++S 1200,2900,1200,5200,200,*,UP,POLY ++S 1000,3000,2000,3000,600,*,LEFT,ALU1 ++S 2000,3000,2000,3000,400,a1,LEFT,CALU1 ++S 2000,2900,2000,4300,200,*,UP,POLY ++S 2600,1900,2600,2700,600,*,UP,NDIF ++S 2500,2000,5200,2000,400,*,LEFT,ALU1 ++S 1600,1900,1600,2700,400,n2,UP,NDIF ++S 1200,1700,1200,2900,200,09,UP,NTRANS ++S 1200,1300,1200,1700,200,*,DOWN,POLY ++S 2000,1700,2000,2900,200,10,UP,NTRANS ++S 2000,1300,2000,1700,200,*,DOWN,POLY ++S 3000,3000,3000,3000,400,z,LEFT,CALU1 ++S 3000,3000,4000,3000,600,*,RIGHT,ALU1 ++S 6800,400,6800,2800,200,*,UP,POLY ++S 6600,4900,7400,4900,400,*,RIGHT,ALU1 ++S 3200,400,3200,1700,200,*,DOWN,POLY ++S 2000,4300,2800,4300,200,*,RIGHT,POLY ++S 4000,3000,4000,6000,400,z,DOWN,CALU1 ++S 2800,4300,2800,5000,200,*,UP,POLY ++S 2000,6000,2000,6000,400,a2,LEFT,CALU1 ++S 3000,3900,3000,6100,400,*,UP,ALU1 ++S 3000,4000,3000,6000,400,a2,DOWN,CALU1 ++S 2000,6000,3000,6000,600,*,LEFT,ALU1 ++S 6000,1900,6000,4100,400,*,DOWN,ALU1 ++S 6000,2000,6000,4000,400,b,DOWN,CALU1 ++S 0,600,8000,600,1200,vss,RIGHT,CALU1 ++S 0,9400,8000,9400,1200,vdd,RIGHT,CALU1 ++S 0,5000,8000,5000,10000,xaon21_x05,LEFT,TALU8 ++S 0,2200,8000,2200,5200,*,LEFT,PWELL ++S 0,7600,8000,7600,5600,*,LEFT,NWELL ++S 7000,2000,7000,2000,400,b,LEFT,CALU1 ++S 6000,2000,7000,2000,600,*,LEFT,ALU1 ++S 4700,2500,4700,3000,400,n1,UP,NDIF ++S 5200,2300,5200,3200,200,07,UP,NTRANS ++S 4400,2300,4400,3200,200,06,UP,NTRANS ++S 3600,2500,3600,3000,600,*,UP,NDIF ++S 3600,2200,3600,3000,400,*,DOWN,NDIF ++S 3200,2000,3200,3200,200,08,UP,NTRANS ++S 2800,2200,2800,3000,400,*,DOWN,NDIF ++S 3200,3200,3200,3600,200,*,UP,POLY ++S 4400,1900,4400,2300,200,*,DOWN,POLY ++S 5200,1900,5200,2300,200,*,DOWN,POLY ++S 7200,2900,7200,3400,400,*,UP,NDIF ++S 6800,2700,6800,3600,200,11,UP,NTRANS ++S 6100,900,6100,3400,800,*,UP,NDIF ++S 7400,3200,7400,4900,400,*,UP,ALU1 ++S 6800,4000,7500,4000,200,*,RIGHT,POLY ++S 5200,5400,5800,5400,400,*,RIGHT,ALU1 ++S 5200,2000,5200,5400,400,*,UP,ALU1 ++S 5500,6000,5500,8000,200,04,DOWN,PTRANS ++S 4300,6000,4300,8000,200,03,DOWN,PTRANS ++S 4900,6200,4900,7800,600,*,UP,PDIF ++S 4400,3300,4400,4600,200,*,UP,POLY ++S 4300,4600,4300,6000,200,*,DOWN,POLY ++S 4300,4600,6900,4600,200,*,LEFT,POLY ++S 4000,6300,5000,6300,400,*,LEFT,ALU1 ++S 4000,2900,4000,6300,400,*,DOWN,ALU1 ++S 3200,7100,5800,7100,400,*,LEFT,ALU1 ++S 3200,6900,3200,7100,400,*,UP,ALU1 ++S 5800,5400,5800,7100,400,*,UP,ALU1 ++S 5900,6200,5900,7800,400,*,UP,PDIF ++S 5500,8000,5500,8400,200,*,UP,POLY ++S 4300,8000,4300,8400,200,*,UP,POLY ++S 6000,7900,6600,7900,400,*,LEFT,ALU1 ++S 6600,4900,6600,7900,400,*,DOWN,ALU1 ++S 6200,6400,6200,8000,600,*,DOWN,PDIF ++S 7500,4000,7500,5800,200,*,DOWN,POLY ++S 7400,6400,7400,8000,600,*,DOWN,PDIF ++S 7400,6700,7400,9300,400,*,UP,ALU1 ++S 6700,8200,6700,8600,200,*,UP,POLY ++S 6700,6200,6700,8200,200,05,DOWN,PTRANS ++S 6700,5800,7500,5800,200,*,RIGHT,POLY ++S 3800,6200,3800,7800,600,*,UP,PDIF ++S 2300,7700,2300,9300,600,*,UP,ALU1 ++S 2500,6200,2500,7800,600,*,UP,PDIF ++S 1700,6000,1700,8000,200,01,DOWN,PTRANS ++S 1300,6200,1300,7800,400,*,UP,PDIF ++S 1700,8000,1700,8400,200,*,UP,POLY ++S 1700,5200,1700,6100,200,*,DOWN,POLY ++S 1200,5200,1700,5200,200,*,RIGHT,POLY ++S 600,900,600,2700,600,*,UP,NDIF ++S 1000,2000,1000,4000,400,a1,DOWN,CALU1 ++S 1000,1900,1000,4100,400,*,DOWN,ALU1 ++S 3100,8000,3100,8400,200,*,UP,POLY ++S 3100,6000,3100,8000,200,02,DOWN,PTRANS ++S 3100,4800,3100,6100,200,*,DOWN,POLY ++S 1000,6900,3200,6900,400,*,LEFT,ALU1 ++V 2000,9300,CONT_BODY_N,* ++V 1000,9300,CONT_BODY_N,* ++V 2000,700,CONT_BODY_P,* ++V 1000,3500,CONT_POLY,* ++V 2600,2000,CONT_DIF_N,an ++V 6700,4900,CONT_POLY,bn ++V 6100,1000,CONT_DIF_N,* ++V 7000,2000,CONT_POLY,* ++V 3000,5000,CONT_POLY,* ++V 5200,3800,CONT_POLY,an ++V 3800,2900,CONT_DIF_N,* ++V 7400,3300,CONT_DIF_N,bn ++V 4900,6300,CONT_DIF_P,* ++V 6100,7900,CONT_DIF_P,bn ++V 7400,6800,CONT_DIF_P,* ++V 7400,7800,CONT_DIF_P,* ++V 5300,5400,CONT_POLY,an ++V 2300,7700,CONT_DIF_P,* ++V 1100,6900,CONT_DIF_P,an ++V 600,1000,CONT_DIF_N,* ++V 3700,7100,CONT_DIF_P,an ++EOF +diff --git a/alliance/src/cells/src/msxlib/xaon21_x05.vbe b/alliance/src/cells/src/msxlib/xaon21_x05.vbe +new file mode 100644 +index 0000000..a437136 +--- /dev/null ++++ b/alliance/src/cells/src/msxlib/xaon21_x05.vbe +@@ -0,0 +1,44 @@ ++ENTITY xaon21_x05 IS ++GENERIC ( ++ CONSTANT area : NATURAL := 8000; ++ CONSTANT cin_b : NATURAL := 5; ++ CONSTANT cin_a1 : NATURAL := 4; ++ CONSTANT cin_a2 : NATURAL := 4; ++ CONSTANT rdown_b_z : NATURAL := 3870; ++ CONSTANT rdown_a1_z : NATURAL := 3870; ++ CONSTANT rdown_a2_z : NATURAL := 3870; ++ CONSTANT rup_b_z : NATURAL := 3790; ++ CONSTANT rup_a1_z : NATURAL := 4790; ++ CONSTANT rup_a2_z : NATURAL := 4780; ++ CONSTANT tplh_a1_z : NATURAL := 82; ++ CONSTANT tplh_a2_z : NATURAL := 78; ++ CONSTANT tphl_b_z : NATURAL := 29; ++ CONSTANT tplh_b_z : NATURAL := 88; ++ CONSTANT tphh_b_z : NATURAL := 55; ++ CONSTANT tphl_a1_z : NATURAL := 76; ++ CONSTANT tphl_a2_z : NATURAL := 78; ++ CONSTANT tpll_a1_z : NATURAL := 111; ++ CONSTANT tpll_a2_z : NATURAL := 105; ++ CONSTANT tpll_b_z : NATURAL := 88; ++ CONSTANT tphh_a1_z : NATURAL := 113; ++ CONSTANT tphh_a2_z : NATURAL := 114; ++ CONSTANT transistors : NATURAL := 11 ++); ++PORT ( ++ b : in BIT; ++ a1 : in BIT; ++ a2 : in BIT; ++ z : out BIT; ++ vdd : in BIT; ++ vss : in BIT ++); ++END xaon21_x05; ++ ++ARCHITECTURE behaviour_data_flow OF xaon21_x05 IS ++ ++BEGIN ++ ASSERT ((vdd and not (vss)) = '1') ++ REPORT "power supply is missing on xaon21_x05" ++ SEVERITY WARNING; ++ z <= (b xor (a1 and a2)) after 1000 ps; ++END; +diff --git a/alliance/src/cells/src/msxlib/xaon21_x1.ap b/alliance/src/cells/src/msxlib/xaon21_x1.ap +new file mode 100644 +index 0000000..ec6bccd +--- /dev/null ++++ b/alliance/src/cells/src/msxlib/xaon21_x1.ap +@@ -0,0 +1,130 @@ ++V ALLIANCE : 6 ++H xaon21_x1,P, 9/ 8/2014,100 ++A 0,0,8000,10000 ++R 4000,4000,ref_ref,z_40 ++R 4000,5000,ref_ref,z_50 ++R 3000,7000,ref_ref,a2_70 ++R 2000,7000,ref_ref,a2_70 ++R 2000,5000,ref_ref,a2_50 ++R 1000,5000,ref_ref,a1_50 ++R 1000,3000,ref_ref,a1_30 ++R 1000,4000,ref_ref,a1_40 ++R 3000,3000,ref_ref,z_30 ++R 2000,3000,ref_ref,a1_30 ++R 4000,6000,ref_ref,z_60 ++R 4000,3000,ref_ref,z_30 ++R 2000,6000,ref_ref,a2_60 ++R 7000,5000,ref_ref,b_50 ++R 3000,5000,ref_ref,b_50 ++R 7000,6000,ref_ref,b_60 ++R 3000,4000,ref_ref,b_40 ++S 6800,3800,6800,5200,200,*,DOWN,POLY ++S 6800,300,6800,2100,200,*,UP,POLY ++S 6100,1400,6100,3600,800,*,UP,NDIF ++S 7400,2600,7400,4000,400,*,UP,ALU1 ++S 7400,2800,7400,3400,600,*,UP,NDIF ++S 7200,2300,7200,3600,400,*,UP,NDIF ++S 6800,2100,6800,3800,200,11,UP,NTRANS ++S 3200,300,3200,1200,200,*,DOWN,POLY ++S 1200,3600,1200,5200,200,*,UP,POLY ++S 6000,9400,6000,9700,200,*,DOWN,POLY ++S 4800,9400,4800,9700,200,*,DOWN,POLY ++S 3600,9400,3600,9700,200,*,DOWN,POLY ++S 2400,9400,2400,9700,200,*,DOWN,POLY ++S 1200,9400,1200,9700,200,*,DOWN,POLY ++S 6000,700,6000,3100,400,*,DOWN,ALU1 ++S 600,7100,600,7700,600,*,UP,PDIF ++S 600,8000,4200,8000,400,*,LEFT,ALU1 ++S 600,6900,600,8000,400,*,UP,ALU1 ++S 6800,5800,6800,9200,800,*,DOWN,PDIF ++S 6800,6900,6800,9300,400,*,UP,ALU1 ++S 6000,4000,6000,8000,400,*,DOWN,ALU1 ++S 6000,4000,7400,4000,400,*,LEFT,ALU1 ++S 3800,1400,3800,3000,600,*,DOWN,NDIF ++S 1200,800,1200,1200,200,*,DOWN,POLY ++S 2000,800,2000,1200,200,*,DOWN,POLY ++S 2000,3600,2000,4600,200,*,UP,POLY ++S 5200,900,5200,1200,200,*,DOWN,POLY ++S 4400,900,4400,1200,200,*,DOWN,POLY ++S 7000,4900,7000,6100,400,*,DOWN,ALU1 ++S 3000,3900,3000,5100,400,*,DOWN,ALU1 ++S 2400,5100,2400,5600,200,*,DOWN,POLY ++S 4000,6000,4200,6000,600,*,LEFT,ALU1 ++S 3000,3000,3000,3000,400,z,LEFT,CALU1 ++S 4000,3000,4000,6000,400,z,DOWN,CALU1 ++S 4000,2900,4000,6100,400,*,DOWN,ALU1 ++S 600,1400,600,3400,600,*,UP,NDIF ++S 1200,1200,1200,3600,200,09,UP,NTRANS ++S 1600,1400,1600,3400,400,n2,UP,NDIF ++S 2800,2000,2800,3400,400,*,DOWN,NDIF ++S 3600,1400,3600,3400,400,*,UP,NDIF ++S 3200,1200,3200,3600,200,08,UP,NTRANS ++S 2000,1200,2000,3600,200,10,UP,NTRANS ++S 2600,1400,2600,3400,600,*,UP,NDIF ++S 2500,2000,5000,2000,400,*,LEFT,ALU1 ++S 5000,3400,5200,3400,600,*,RIGHT,ALU1 ++S 4200,7000,5000,7000,400,*,LEFT,ALU1 ++S 5000,2000,5000,7000,400,*,UP,ALU1 ++S 6000,5200,6800,5200,200,*,RIGHT,POLY ++S 5300,8000,6000,8000,400,*,LEFT,ALU1 ++S 3600,5200,4000,5200,200,*,RIGHT,POLY ++S 4800,5600,4800,9400,200,04,DOWN,PTRANS ++S 5400,5800,5400,9200,600,*,DOWN,PDIF ++S 6000,5600,6000,9400,200,05,DOWN,PTRANS ++S 2400,5600,2400,9400,200,02,DOWN,PTRANS ++S 3000,5800,3000,9200,600,*,UP,PDIF ++S 3600,5600,3600,9400,200,03,DOWN,PTRANS ++S 4000,4200,6000,4200,200,*,RIGHT,POLY ++S 4000,4200,4000,5200,200,*,DOWN,POLY ++S 4200,7000,4200,8000,400,*,UP,ALU1 ++S 4000,5800,4000,9200,600,*,UP,PDIF ++S 1700,5800,1700,9200,600,*,UP,PDIF ++S 4400,2800,4400,4200,200,*,UP,POLY ++S 3000,7000,3000,7000,400,a2,LEFT,CALU1 ++S 2000,7000,3000,7000,600,*,LEFT,ALU1 ++S 2000,4900,2000,7100,400,*,UP,ALU1 ++S 2000,5000,2000,7000,400,a2,DOWN,CALU1 ++S 1200,5600,1200,9400,200,01,DOWN,PTRANS ++S 800,5800,800,9200,400,*,UP,PDIF ++S 4400,1200,4400,2800,200,06,UP,NTRANS ++S 5200,1200,5200,2800,200,07,UP,NTRANS ++S 4700,1400,4700,2600,400,n1,UP,NDIF ++S 3200,300,6800,300,200,*,RIGHT,POLY ++S 1000,3000,2000,3000,600,*,LEFT,ALU1 ++S 1000,3000,1000,5000,400,a1,DOWN,CALU1 ++S 1000,2900,1000,5100,400,*,DOWN,ALU1 ++S 2000,3000,2000,3000,400,a1,LEFT,CALU1 ++S 600,700,600,2100,400,*,DOWN,ALU1 ++S 3000,3000,4000,3000,600,*,RIGHT,ALU1 ++S 0,600,8000,600,1200,vss,RIGHT,CALU1 ++S 0,9400,8000,9400,1200,vdd,RIGHT,CALU1 ++S 0,5000,8000,5000,10000,xaon21_x1,LEFT,TALU8 ++S 0,2200,8000,2200,5200,*,LEFT,PWELL ++S 0,7600,8000,7600,5600,*,LEFT,NWELL ++S 7000,5000,7000,6000,400,b,DOWN,CALU1 ++S 3000,4000,3000,5000,400,b,UP,CALU1 ++V 7300,700,CONT_BODY_P,* ++V 7400,2700,CONT_DIF_N,bn ++V 7400,3500,CONT_DIF_N,bn ++V 6000,3000,CONT_DIF_N,* ++V 6000,2000,CONT_DIF_N,* ++V 600,7800,CONT_DIF_P,an ++V 600,7000,CONT_DIF_P,an ++V 6800,9000,CONT_DIF_P,* ++V 6800,8000,CONT_DIF_P,* ++V 6800,7000,CONT_DIF_P,* ++V 3800,2900,CONT_DIF_N,* ++V 7000,5000,CONT_POLY,* ++V 3000,4200,CONT_POLY,* ++V 5000,5000,CONT_POLY,an ++V 6000,4400,CONT_POLY,bn ++V 5400,8000,CONT_DIF_P,bn ++V 4200,6000,CONT_DIF_P,* ++V 1800,9000,CONT_DIF_P,* ++V 3000,8000,CONT_DIF_P,an ++V 2000,5000,CONT_POLY,* ++V 1000,5000,CONT_POLY,* ++V 5200,3400,CONT_POLY,an ++V 600,2000,CONT_DIF_N,* ++V 2600,2000,CONT_DIF_N,an ++EOF +diff --git a/alliance/src/cells/src/msxlib/xaon21_x1.vbe b/alliance/src/cells/src/msxlib/xaon21_x1.vbe +new file mode 100644 +index 0000000..79f01d2 +--- /dev/null ++++ b/alliance/src/cells/src/msxlib/xaon21_x1.vbe +@@ -0,0 +1,44 @@ ++ENTITY xaon21_x1 IS ++GENERIC ( ++ CONSTANT area : NATURAL := 8000; ++ CONSTANT cin_b : NATURAL := 10; ++ CONSTANT cin_a1 : NATURAL := 7; ++ CONSTANT cin_a2 : NATURAL := 8; ++ CONSTANT rdown_b_z : NATURAL := 2130; ++ CONSTANT rdown_a1_z : NATURAL := 2060; ++ CONSTANT rdown_a2_z : NATURAL := 2060; ++ CONSTANT rup_b_z : NATURAL := 1980; ++ CONSTANT rup_a1_z : NATURAL := 2500; ++ CONSTANT rup_a2_z : NATURAL := 2500; ++ CONSTANT tplh_a1_z : NATURAL := 78; ++ CONSTANT tplh_a2_z : NATURAL := 73; ++ CONSTANT tphl_b_z : NATURAL := 27; ++ CONSTANT tplh_b_z : NATURAL := 82; ++ CONSTANT tphh_b_z : NATURAL := 51; ++ CONSTANT tphl_a1_z : NATURAL := 69; ++ CONSTANT tphl_a2_z : NATURAL := 70; ++ CONSTANT tpll_a1_z : NATURAL := 105; ++ CONSTANT tpll_a2_z : NATURAL := 99; ++ CONSTANT tpll_b_z : NATURAL := 83; ++ CONSTANT tphh_a1_z : NATURAL := 100; ++ CONSTANT tphh_a2_z : NATURAL := 101; ++ CONSTANT transistors : NATURAL := 11 ++); ++PORT ( ++ b : in BIT; ++ a1 : in BIT; ++ a2 : in BIT; ++ z : out BIT; ++ vdd : in BIT; ++ vss : in BIT ++); ++END xaon21_x1; ++ ++ARCHITECTURE behaviour_data_flow OF xaon21_x1 IS ++ ++BEGIN ++ ASSERT ((vdd and not (vss)) = '1') ++ REPORT "power supply is missing on xaon21_x1" ++ SEVERITY WARNING; ++ z <= (b xor (a1 and a2)) after 1000 ps; ++END; +diff --git a/alliance/src/cells/src/msxlib/xaon22_x05.ap b/alliance/src/cells/src/msxlib/xaon22_x05.ap +new file mode 100644 +index 0000000..f014b42 +--- /dev/null ++++ b/alliance/src/cells/src/msxlib/xaon22_x05.ap +@@ -0,0 +1,164 @@ ++V ALLIANCE : 6 ++H xaon22_x05,P, 9/ 8/2014,100 ++A 0,0,10000,10000 ++R 2000,4000,ref_ref,a1_40 ++R 8000,7000,ref_ref,b1_70 ++R 8000,6000,ref_ref,b1_60 ++R 8000,4000,ref_ref,b2_40 ++R 8000,3000,ref_ref,b2_30 ++R 8000,2000,ref_ref,b2_20 ++R 5000,3000,ref_ref,z_30 ++R 3000,4000,ref_ref,a2_40 ++R 3000,5000,ref_ref,a2_50 ++R 2000,6000,ref_ref,a2_60 ++R 4000,3000,ref_ref,z_30 ++R 4000,6000,ref_ref,z_60 ++R 4000,5000,ref_ref,z_50 ++R 4000,4000,ref_ref,z_40 ++R 3000,6000,ref_ref,a2_60 ++R 1000,4000,ref_ref,a1_40 ++R 1000,3000,ref_ref,a1_30 ++R 1000,5000,ref_ref,a1_50 ++R 7000,6000,ref_ref,b1_60 ++R 8000,5000,ref_ref,b1_50 ++R 9000,2000,ref_ref,b2_20 ++S 1100,9300,1900,9300,600,*,RIGHT,NTIE ++S 1100,700,1900,700,600,*,RIGHT,PTIE ++S 7000,6000,8000,6000,600,*,RIGHT,ALU1 ++S 8000,4900,8000,7100,400,*,UP,ALU1 ++S 6200,4800,6200,8000,400,*,UP,ALU1 ++S 1600,1900,1600,3100,400,n2,UP,NDIF ++S 2600,2000,6000,2000,400,*,LEFT,ALU1 ++S 2600,2000,2600,3100,400,*,DOWN,ALU1 ++S 2000,4000,2000,4000,400,a1,LEFT,CALU1 ++S 1000,4000,2000,4000,600,*,LEFT,ALU1 ++S 5200,2400,5200,3300,200,6z,UP,NTRANS ++S 6000,2400,6000,3300,200,5z,UP,NTRANS ++S 4000,1700,4000,3300,200,4z,UP,NTRANS ++S 3200,1700,3200,3300,200,3z,UP,NTRANS ++S 8600,1700,8600,3300,200,4b,UP,NTRANS ++S 7800,1700,7800,3300,200,3b,UP,NTRANS ++S 2000,1700,2000,3300,200,4a,UP,NTRANS ++S 1200,1700,1200,3300,200,3a,UP,NTRANS ++S 5600,2600,5600,3100,400,n1,UP,NDIF ++S 6800,1900,6800,3100,1000,*,UP,NDIF ++S 9000,1900,9000,3100,400,*,UP,NDIF ++S 3200,700,8600,700,200,*,RIGHT,POLY ++S 8600,3300,8600,4000,200,*,UP,POLY ++S 8600,700,8600,1700,200,*,DOWN,POLY ++S 2000,3300,2000,4600,200,*,UP,POLY ++S 2000,4600,2800,4600,200,*,RIGHT,POLY ++S 1200,3300,1200,5200,200,*,UP,POLY ++S 2000,1300,2000,1700,200,*,DOWN,POLY ++S 1200,1300,1200,1700,200,*,DOWN,POLY ++S 3200,700,3200,1700,200,*,DOWN,POLY ++S 4400,1900,4400,3100,400,*,DOWN,NDIF ++S 600,1900,600,3100,600,*,UP,NDIF ++S 2600,1900,2600,3100,600,*,UP,NDIF ++S 3200,3300,3200,3700,200,*,UP,POLY ++S 4000,3300,4000,3700,200,*,UP,POLY ++S 5200,2000,5200,2400,200,*,DOWN,POLY ++S 6000,2000,6000,2400,200,*,DOWN,POLY ++S 4000,1300,7800,1300,200,*,RIGHT,POLY ++S 7800,3300,7800,5500,200,*,UP,POLY ++S 7000,700,7000,3100,400,*,DOWN,ALU1 ++S 8000,2000,8000,4000,400,b2,DOWN,CALU1 ++S 4000,3000,5000,3000,600,*,RIGHT,ALU1 ++S 5000,3000,5000,3000,400,z,LEFT,CALU1 ++S 5200,3300,5200,4700,200,*,UP,POLY ++S 4400,2600,4400,3100,600,*,UP,NDIF ++S 0,9400,10000,9400,1200,vdd,RIGHT,CALU1 ++S 0,5000,10000,5000,10000,xaon22_x05,LEFT,TALU8 ++S 0,2200,10000,2200,5200,*,LEFT,PWELL ++S 0,7600,10000,7600,5600,*,LEFT,NWELL ++S 0,600,10000,600,1200,vss,RIGHT,CALU1 ++S 2000,6000,3000,6000,600,*,LEFT,ALU1 ++S 3000,4000,3000,6000,400,a2,DOWN,CALU1 ++S 3000,3900,3000,6100,400,*,UP,ALU1 ++S 2000,6000,2000,6000,400,a2,LEFT,CALU1 ++S 4000,3000,4000,6000,400,z,DOWN,CALU1 ++S 600,700,600,2100,400,*,DOWN,ALU1 ++S 2800,2300,2800,3100,400,*,DOWN,NDIF ++S 1000,2900,1000,5100,400,*,DOWN,ALU1 ++S 1000,3000,1000,5000,400,a1,DOWN,CALU1 ++S 6000,2000,6000,4000,400,*,UP,ALU1 ++S 2200,7700,2200,9300,400,*,UP,ALU1 ++S 1200,5200,1600,5200,200,*,RIGHT,POLY ++S 5400,4000,6000,4000,400,*,RIGHT,ALU1 ++S 6800,5800,8000,5800,200,*,LEFT,POLY ++S 8000,1900,8000,4000,400,*,DOWN,ALU1 ++S 6800,6200,6800,8200,200,1b,DOWN,PTRANS ++S 7000,6000,7000,6000,400,b1,LEFT,CALU1 ++S 8000,5000,8000,7000,400,b1,UP,CALU1 ++S 6200,8000,9400,8000,400,*,RIGHT,ALU1 ++S 7800,6400,7800,9100,1400,*,DOWN,PDIF ++S 8800,6200,8800,8200,200,2b,DOWN,PTRANS ++S 9200,6400,9200,8000,400,*,DOWN,PDIF ++S 9400,6600,9400,7200,600,*,UP,PDIF ++S 9000,2000,9000,2000,400,b2,LEFT,CALU1 ++S 8000,4000,8600,4000,600,*,LEFT,ALU1 ++S 8000,2000,9000,2000,600,*,RIGHT,ALU1 ++S 9400,2900,9400,8000,400,*,UP,ALU1 ++S 9100,3000,9400,3000,600,*,RIGHT,ALU1 ++S 8800,4000,8800,6200,200,*,UP,POLY ++S 8800,8200,8800,8600,200,*,UP,POLY ++S 6800,8200,6800,8600,200,*,UP,POLY ++S 4000,4700,6400,4700,200,*,LEFT,POLY ++S 4000,6500,4600,6500,600,*,LEFT,ALU1 ++S 5200,6200,5200,8200,200,2z,DOWN,PTRANS ++S 4600,6400,4600,8000,600,*,UP,PDIF ++S 4000,6200,4000,8200,200,1z,DOWN,PTRANS ++S 4000,2900,4000,6600,400,*,DOWN,ALU1 ++S 5400,4000,5400,7500,400,*,DOWN,ALU1 ++S 6000,6400,6000,8000,600,*,UP,PDIF ++S 5200,8200,5200,8600,200,*,UP,POLY ++S 4000,8200,4000,8600,200,*,UP,POLY ++S 5200,5500,5200,6200,200,*,DOWN,POLY ++S 4900,5500,5400,5500,400,*,LEFT,ALU1 ++S 2800,6200,2800,8200,200,2a,DOWN,PTRANS ++S 3400,6400,3400,8000,600,*,UP,PDIF ++S 2200,6400,2200,8000,600,*,UP,PDIF ++S 1600,6200,1600,8200,200,1a,DOWN,PTRANS ++S 1200,6400,1200,8000,400,*,UP,PDIF ++S 3000,6900,3000,7500,400,*,UP,ALU1 ++S 3000,7500,5400,7500,400,*,LEFT,ALU1 ++S 1000,6900,3000,6900,400,*,LEFT,ALU1 ++S 2800,8200,2800,8600,200,*,UP,POLY ++S 1600,8200,1600,8600,200,*,UP,POLY ++S 1600,5200,1600,6200,200,*,DOWN,POLY ++S 2800,4800,2800,6200,200,*,DOWN,POLY ++S 4000,4700,4000,6200,200,*,UP,POLY ++S 1000,7200,1000,7800,600,*,UP,PDIF ++S 1000,6900,1000,8000,400,*,UP,ALU1 ++S 3600,1900,3600,3100,400,n3,UP,NDIF ++S 8200,1900,8200,3100,400,n4,UP,NDIF ++V 2000,9300,CONT_BODY_N,* ++V 1000,9300,CONT_BODY_N,* ++V 2000,700,CONT_BODY_P,* ++V 1000,700,CONT_BODY_P,* ++V 6200,4900,CONT_POLY,bn ++V 6200,7300,CONT_DIF_P,bn ++V 6200,6500,CONT_DIF_P,bn ++V 8200,9000,CONT_DIF_P,* ++V 7400,9000,CONT_DIF_P,* ++V 2600,2200,CONT_DIF_N,an ++V 2600,3000,CONT_DIF_N,an ++V 9200,3000,CONT_DIF_N,bn ++V 3000,4800,CONT_POLY,* ++V 1000,5000,CONT_POLY,* ++V 7000,2000,CONT_DIF_N,* ++V 8600,4000,CONT_POLY,* ++V 7000,3000,CONT_DIF_N,* ++V 6000,3900,CONT_POLY,an ++V 4600,3000,CONT_DIF_N,* ++V 600,2000,CONT_DIF_N,* ++V 2200,7800,CONT_DIF_P,* ++V 8000,5600,CONT_POLY,* ++V 9400,6500,CONT_DIF_P,bn ++V 9400,7300,CONT_DIF_P,bn ++V 4600,6500,CONT_DIF_P,* ++V 5000,5500,CONT_POLY,an ++V 3400,7500,CONT_DIF_P,an ++V 1000,7900,CONT_DIF_P,an ++V 1000,7100,CONT_DIF_P,an ++EOF +diff --git a/alliance/src/cells/src/msxlib/xaon22_x05.vbe b/alliance/src/cells/src/msxlib/xaon22_x05.vbe +new file mode 100644 +index 0000000..94984ef +--- /dev/null ++++ b/alliance/src/cells/src/msxlib/xaon22_x05.vbe +@@ -0,0 +1,52 @@ ++ENTITY xaon22_x05 IS ++GENERIC ( ++ CONSTANT area : NATURAL := 10000; ++ CONSTANT cin_b1 : NATURAL := 7; ++ CONSTANT cin_b2 : NATURAL := 7; ++ CONSTANT cin_a1 : NATURAL := 5; ++ CONSTANT cin_a2 : NATURAL := 5; ++ CONSTANT rdown_b1_z : NATURAL := 3810; ++ CONSTANT rdown_b2_z : NATURAL := 3830; ++ CONSTANT rdown_a1_z : NATURAL := 3880; ++ CONSTANT rdown_a2_z : NATURAL := 3870; ++ CONSTANT rup_b1_z : NATURAL := 3950; ++ CONSTANT rup_b2_z : NATURAL := 3980; ++ CONSTANT rup_a1_z : NATURAL := 5000; ++ CONSTANT rup_a2_z : NATURAL := 4990; ++ CONSTANT tplh_a1_z : NATURAL := 100; ++ CONSTANT tplh_a2_z : NATURAL := 94; ++ CONSTANT tphl_b1_z : NATURAL := 34; ++ CONSTANT tphl_b2_z : NATURAL := 36; ++ CONSTANT tplh_b1_z : NATURAL := 115; ++ CONSTANT tplh_b2_z : NATURAL := 118; ++ CONSTANT tphh_b1_z : NATURAL := 61; ++ CONSTANT tphh_b2_z : NATURAL := 67; ++ CONSTANT tphl_a1_z : NATURAL := 75; ++ CONSTANT tphl_a2_z : NATURAL := 77; ++ CONSTANT tpll_a1_z : NATURAL := 121; ++ CONSTANT tpll_a2_z : NATURAL := 114; ++ CONSTANT tpll_b1_z : NATURAL := 111; ++ CONSTANT tpll_b2_z : NATURAL := 107; ++ CONSTANT tphh_a1_z : NATURAL := 107; ++ CONSTANT tphh_a2_z : NATURAL := 107; ++ CONSTANT transistors : NATURAL := 14 ++); ++PORT ( ++ b1 : in BIT; ++ b2 : in BIT; ++ a1 : in BIT; ++ a2 : in BIT; ++ z : out BIT; ++ vdd : in BIT; ++ vss : in BIT ++); ++END xaon22_x05; ++ ++ARCHITECTURE behaviour_data_flow OF xaon22_x05 IS ++ ++BEGIN ++ ASSERT ((vdd and not (vss)) = '1') ++ REPORT "power supply is missing on xaon22_x05" ++ SEVERITY WARNING; ++ z <= ((b1 and b2) xor (a1 and a2)) after 1000 ps; ++END; +diff --git a/alliance/src/cells/src/msxlib/xaon22_x1.ap b/alliance/src/cells/src/msxlib/xaon22_x1.ap +new file mode 100644 +index 0000000..5f59fce +--- /dev/null ++++ b/alliance/src/cells/src/msxlib/xaon22_x1.ap +@@ -0,0 +1,166 @@ ++V ALLIANCE : 6 ++H xaon22_x1,P,21/10/2004,100 ++A 0,0,10000,10000 ++R 8000,7000,ref_ref,b1_70 ++R 8000,6000,ref_ref,b1_60 ++R 8000,4000,ref_ref,b2_40 ++R 8000,3000,ref_ref,b2_30 ++R 8000,2000,ref_ref,b2_20 ++R 5000,3000,ref_ref,z_30 ++R 3000,4000,ref_ref,a2_40 ++R 3000,5000,ref_ref,a2_50 ++R 2000,6000,ref_ref,a2_60 ++R 4000,3000,ref_ref,z_30 ++R 4000,6000,ref_ref,z_60 ++R 4000,5000,ref_ref,z_50 ++R 4000,4000,ref_ref,z_40 ++R 3000,6000,ref_ref,a2_60 ++R 1000,4000,ref_ref,a1_40 ++R 1000,3000,ref_ref,a1_30 ++R 9000,2000,ref_ref,b2_20 ++R 4000,7000,ref_ref,z_70 ++R 2000,5000,ref_ref,a1_50 ++R 1000,5000,ref_ref,a1_50 ++R 8000,5000,ref_ref,b1_50 ++R 7000,7000,ref_ref,b1_70 ++S 4000,3000,4000,7000,400,z,DOWN,CALU1 ++S 4200,1500,4200,3400,400,n3,UP,NDIF ++S 8000,2000,8000,4000,400,b2,DOWN,CALU1 ++S 5000,3000,5000,3000,400,z,LEFT,CALU1 ++S 0,9400,10000,9400,1200,vdd,RIGHT,CALU1 ++S 0,7600,10000,7600,5600,*,LEFT,NWELL ++S 0,2200,10000,2200,5200,*,LEFT,PWELL ++S 0,5000,10000,5000,10000,xaon22_x1,LEFT,TALU8 ++S 0,600,10000,600,1200,vss,RIGHT,CALU1 ++S 2000,6000,3000,6000,600,*,LEFT,ALU1 ++S 3000,4000,3000,6000,400,a2,DOWN,CALU1 ++S 3000,3900,3000,6100,400,*,UP,ALU1 ++S 2000,6000,2000,6000,400,a2,LEFT,CALU1 ++S 8000,5000,8000,7000,400,b1,UP,CALU1 ++S 6200,8000,9400,8000,400,*,RIGHT,ALU1 ++S 9000,2000,9000,2000,400,b2,LEFT,CALU1 ++S 8000,2000,9000,2000,600,*,RIGHT,ALU1 ++S 5200,5500,5200,6200,200,*,DOWN,POLY ++S 1000,6900,3000,6900,400,*,LEFT,ALU1 ++S 7200,700,7200,3100,400,*,DOWN,ALU1 ++S 6600,1500,6600,1900,200,*,DOWN,POLY ++S 5800,1500,5800,1900,200,*,DOWN,POLY ++S 4600,900,7800,900,200,*,RIGHT,POLY ++S 3800,300,3800,1300,200,*,DOWN,POLY ++S 3800,300,8600,300,200,*,RIGHT,POLY ++S 3000,8000,5400,8000,400,*,LEFT,ALU1 ++S 3000,6900,3000,8000,400,*,UP,ALU1 ++S 4000,7000,4600,7000,600,*,LEFT,ALU1 ++S 4000,2900,4000,7100,400,*,DOWN,ALU1 ++S 3000,800,3000,3700,400,*,DOWN,NDIF ++S 2600,600,2600,3900,200,4a,UP,NTRANS ++S 3200,2000,3200,3100,400,*,DOWN,ALU1 ++S 3200,2000,6000,2000,400,*,LEFT,ALU1 ++S 2200,800,2200,3700,400,n2,UP,NDIF ++S 1800,600,1800,3900,200,3a,UP,NTRANS ++S 1200,700,1200,2100,400,*,DOWN,ALU1 ++S 1100,800,1100,3700,600,*,UP,NDIF ++S 1800,3900,1800,5200,200,*,UP,POLY ++S 2600,3900,2600,4700,200,*,UP,POLY ++S 1000,5000,2000,5000,600,*,LEFT,ALU1 ++S 2000,5000,2000,5000,400,a1,LEFT,CALU1 ++S 1000,2900,1000,5100,400,*,DOWN,ALU1 ++S 1000,3000,1000,5000,400,a1,DOWN,CALU1 ++S 4000,3000,5200,3000,600,*,RIGHT,ALU1 ++S 2800,5900,2800,9400,200,2a,DOWN,PTRANS ++S 3400,6100,3400,9200,600,*,UP,PDIF ++S 4000,5900,4000,9400,200,1z,DOWN,PTRANS ++S 2200,6100,2200,9200,600,*,UP,PDIF ++S 1600,5900,1600,9400,200,1a,DOWN,PTRANS ++S 1200,6100,1200,9200,400,*,UP,PDIF ++S 6000,6100,6000,9200,600,*,UP,PDIF ++S 5200,5900,5200,9400,200,2z,DOWN,PTRANS ++S 4600,6100,4600,9200,600,*,UP,PDIF ++S 6800,5900,6800,9400,200,1b,DOWN,PTRANS ++S 7800,6100,7800,9200,1400,*,DOWN,PDIF ++S 8800,5900,8800,9400,200,2b,DOWN,PTRANS ++S 4000,4500,5800,4500,200,*,LEFT,POLY ++S 5900,5300,6200,5300,400,*,LEFT,ALU1 ++S 6200,5300,6200,8000,400,*,UP,ALU1 ++S 5400,6100,5400,8000,400,*,DOWN,ALU1 ++S 2200,7900,2200,9300,400,*,UP,ALU1 ++S 4000,4500,4000,5900,200,*,UP,POLY ++S 1600,5200,1600,5900,200,*,DOWN,POLY ++S 2800,4800,2800,5900,200,*,DOWN,POLY ++S 4600,3600,4600,3900,200,*,UP,POLY ++S 3800,3600,3800,3900,200,*,UP,POLY ++S 4600,1300,4600,3600,200,4z,UP,NTRANS ++S 3800,1300,3800,3600,200,3z,UP,NTRANS ++S 3200,1500,3200,3400,600,*,UP,NDIF ++S 5000,1500,5000,3400,400,*,DOWN,NDIF ++S 5200,2000,5200,3400,600,*,DOWN,NDIF ++S 5800,1800,5800,3600,200,6z,UP,NTRANS ++S 6600,1800,6600,3600,200,5z,UP,NTRANS ++S 6200,2000,6200,3400,400,n1,UP,NDIF ++S 5400,2000,5400,3400,400,*,DOWN,NDIF ++S 5800,3600,5800,5100,200,*,UP,POLY ++S 5000,4200,5000,6100,400,*,DOWN,ALU1 ++S 6000,2000,6000,4200,400,*,UP,ALU1 ++S 5000,4200,6700,4200,400,*,LEFT,ALU1 ++S 9200,6100,9200,9200,400,*,DOWN,PDIF ++S 9100,3300,9600,3300,400,*,LEFT,ALU1 ++S 7000,7000,7000,7000,400,b1,LEFT,CALU1 ++S 7000,7000,8000,7000,600,*,RIGHT,ALU1 ++S 8800,4200,8800,5900,200,*,UP,POLY ++S 1800,300,1800,600,200,*,DOWN,POLY ++S 2600,300,2600,600,200,*,DOWN,POLY ++S 1600,9400,1600,9700,200,*,UP,POLY ++S 2800,9400,2800,9700,200,*,UP,POLY ++S 4000,9400,4000,9700,200,*,UP,POLY ++S 5200,9400,5200,9700,200,*,UP,POLY ++S 6800,9400,6800,9700,200,*,UP,POLY ++S 8800,9400,8800,9700,200,*,UP,POLY ++S 1000,7300,1000,7900,600,*,UP,PDIF ++S 1000,6900,1000,8100,400,*,UP,ALU1 ++S 8200,1500,8200,3400,400,n4,UP,NDIF ++S 9000,1500,9000,3400,400,*,UP,NDIF ++S 8600,1300,8600,3600,200,4b,UP,NTRANS ++S 7400,1500,7400,3400,400,*,DOWN,NDIF ++S 7800,1300,7800,3600,200,3b,UP,NTRANS ++S 7200,1500,7200,3400,600,*,UP,NDIF ++S 7800,900,7800,1300,200,*,DOWN,POLY ++S 8600,300,8600,1300,200,*,DOWN,POLY ++S 7800,3600,7800,4900,200,*,UP,POLY ++S 8000,5000,8000,7100,600,*,UP,ALU1 ++S 6800,5200,7600,5200,200,*,RIGHT,POLY ++S 6800,5200,6800,5900,200,*,DOWN,POLY ++S 7500,5000,8100,5000,400,*,RIGHT,ALU1 ++S 8000,4200,8700,4200,400,*,LEFT,ALU1 ++S 8000,1900,8000,4200,400,*,DOWN,ALU1 ++S 9400,6300,9400,6900,600,*,UP,PDIF ++S 9600,3300,9600,6100,400,*,DOWN,ALU1 ++S 9400,6100,9400,8000,400,*,UP,ALU1 ++V 7400,9000,CONT_DIF_P,* ++V 8200,9000,CONT_DIF_P,* ++V 7200,3000,CONT_DIF_N,* ++V 5200,3000,CONT_DIF_N,* ++V 3400,8000,CONT_DIF_P,an ++V 4600,7000,CONT_DIF_P,* ++V 3200,3000,CONT_DIF_N,an ++V 3200,2200,CONT_DIF_N,an ++V 1200,2000,CONT_DIF_N,* ++V 1200,1000,CONT_DIF_N,* ++V 3000,4500,CONT_POLY,* ++V 1600,5000,CONT_POLY,* ++V 6200,7800,CONT_DIF_P,bn ++V 6200,7000,CONT_DIF_P,bn ++V 6200,6200,CONT_DIF_P,bn ++V 5000,5300,CONT_POLY,an ++V 6000,5300,CONT_POLY,bn ++V 2200,8000,CONT_DIF_P,* ++V 2200,9000,CONT_DIF_P,* ++V 6600,4200,CONT_POLY,an ++V 9200,3300,CONT_DIF_N,bn ++V 1000,8000,CONT_DIF_P,an ++V 1000,7200,CONT_DIF_P,an ++V 7600,5000,CONT_POLY,* ++V 8600,4200,CONT_POLY,* ++V 7200,2000,CONT_DIF_N,* ++V 9400,6200,CONT_DIF_P,bn ++V 9400,7000,CONT_DIF_P,bn ++EOF +diff --git a/alliance/src/cells/src/msxlib/xaon22_x1.vbe b/alliance/src/cells/src/msxlib/xaon22_x1.vbe +new file mode 100644 +index 0000000..fb62fa3 +--- /dev/null ++++ b/alliance/src/cells/src/msxlib/xaon22_x1.vbe +@@ -0,0 +1,52 @@ ++ENTITY xaon22_x1 IS ++GENERIC ( ++ CONSTANT area : NATURAL := 10000; ++ CONSTANT cin_b1 : NATURAL := 10; ++ CONSTANT cin_b2 : NATURAL := 10; ++ CONSTANT cin_a1 : NATURAL := 8; ++ CONSTANT cin_a2 : NATURAL := 8; ++ CONSTANT rdown_b1_z : NATURAL := 1960; ++ CONSTANT rdown_b2_z : NATURAL := 1970; ++ CONSTANT rdown_a1_z : NATURAL := 1970; ++ CONSTANT rdown_a2_z : NATURAL := 1970; ++ CONSTANT rup_b1_z : NATURAL := 2330; ++ CONSTANT rup_b2_z : NATURAL := 2350; ++ CONSTANT rup_a1_z : NATURAL := 2880; ++ CONSTANT rup_a2_z : NATURAL := 2870; ++ CONSTANT tplh_a1_z : NATURAL := 98; ++ CONSTANT tplh_a2_z : NATURAL := 89; ++ CONSTANT tphl_b1_z : NATURAL := 37; ++ CONSTANT tphl_b2_z : NATURAL := 39; ++ CONSTANT tplh_b1_z : NATURAL := 103; ++ CONSTANT tplh_b2_z : NATURAL := 106; ++ CONSTANT tphh_b1_z : NATURAL := 66; ++ CONSTANT tphh_b2_z : NATURAL := 71; ++ CONSTANT tphl_a1_z : NATURAL := 65; ++ CONSTANT tphl_a2_z : NATURAL := 66; ++ CONSTANT tpll_a1_z : NATURAL := 113; ++ CONSTANT tpll_a2_z : NATURAL := 104; ++ CONSTANT tpll_b1_z : NATURAL := 100; ++ CONSTANT tpll_b2_z : NATURAL := 96; ++ CONSTANT tphh_a1_z : NATURAL := 94; ++ CONSTANT tphh_a2_z : NATURAL := 94; ++ CONSTANT transistors : NATURAL := 14 ++); ++PORT ( ++ b1 : in BIT; ++ b2 : in BIT; ++ a1 : in BIT; ++ a2 : in BIT; ++ z : out BIT; ++ vdd : in BIT; ++ vss : in BIT ++); ++END xaon22_x1; ++ ++ARCHITECTURE behaviour_data_flow OF xaon22_x1 IS ++ ++BEGIN ++ ASSERT ((vdd and not (vss)) = '1') ++ REPORT "power supply is missing on xaon22_x1" ++ SEVERITY WARNING; ++ z <= ((b1 and b2) xor (a1 and a2)) after 1000 ps; ++END; +diff --git a/alliance/src/cells/src/msxlib/xnr2_x05.ap b/alliance/src/cells/src/msxlib/xnr2_x05.ap +new file mode 100644 +index 0000000..d4efc72 +--- /dev/null ++++ b/alliance/src/cells/src/msxlib/xnr2_x05.ap +@@ -0,0 +1,120 @@ ++V ALLIANCE : 6 ++H xnr2_x05,P, 9/ 8/2014,100 ++A 0,0,7000,10000 ++R 2000,7000,ref_ref,z_70 ++R 5000,7000,ref_ref,b_70 ++R 5000,8000,ref_ref,b_80 ++R 4000,6000,ref_ref,b_60 ++R 5000,6000,ref_ref,b_60 ++R 2000,8000,ref_ref,z_80 ++R 5000,3000,ref_ref,a_30 ++R 3000,8000,ref_ref,z_80 ++R 1000,6000,ref_ref,z_60 ++R 1000,5000,ref_ref,z_50 ++R 1000,4000,ref_ref,z_40 ++R 1000,7000,ref_ref,z_70 ++R 2000,3000,ref_ref,z_30 ++R 2000,4000,ref_ref,z_40 ++R 5000,4000,ref_ref,a_40 ++R 5000,2000,ref_ref,a_20 ++R 6000,2000,ref_ref,a_20 ++S 1100,9300,1900,9300,600,*,RIGHT,NTIE ++S 1100,700,1900,700,600,*,RIGHT,PTIE ++S 2200,8500,2200,8800,200,*,UP,POLY ++S 1400,8500,1400,8800,200,*,UP,POLY ++S 800,7900,800,9300,400,*,UP,ALU1 ++S 800,6700,800,8300,600,*,DOWN,PDIF ++S 700,6700,700,8300,600,*,DOWN,PDIF ++S 0,9400,7000,9400,1200,vdd,RIGHT,CALU1 ++S 2000,7000,2000,8000,400,*,DOWN,ALU1 ++S 1000,7000,2000,7000,600,*,RIGHT,ALU1 ++S 2000,8100,3100,8100,400,*,LEFT,ALU1 ++S 2000,8000,3100,8000,400,*,LEFT,ALU1 ++S 1000,4000,1000,7000,400,*,UP,ALU1 ++S 1000,4000,1000,7000,400,z,UP,CALU1 ++S 2000,7000,2000,8000,400,z,DOWN,CALU1 ++S 5000,6000,5000,8000,400,b,UP,CALU1 ++S 4000,7000,4000,8100,400,*,UP,ALU1 ++S 4700,900,4700,3100,1600,*,UP,NDIF ++S 0,5000,7000,5000,10000,xnr2_x05,LEFT,TALU8 ++S 0,2200,7000,2200,5200,*,LEFT,PWELL ++S 0,7600,7000,7600,5600,*,LEFT,NWELL ++S 0,600,7000,600,1200,vss,RIGHT,CALU1 ++S 6200,2600,6200,3100,400,*,UP,NDIF ++S 5800,2400,5800,3300,200,9,UP,NTRANS ++S 3000,2600,3000,3100,600,*,UP,NDIF ++S 2400,2400,2400,3300,200,7,UP,NTRANS ++S 3600,2400,3600,3300,200,8,UP,NTRANS ++S 3600,2000,3600,2400,200,*,DOWN,POLY ++S 5800,2000,5800,2400,200,*,DOWN,POLY ++S 1800,2600,1800,3100,600,*,UP,NDIF ++S 1200,2400,1200,3300,200,6,UP,NTRANS ++S 800,2600,800,3100,400,*,DOWN,NDIF ++S 1000,4000,2000,4000,600,*,LEFT,ALU1 ++S 2000,3000,2000,4000,400,z,DOWN,CALU1 ++S 1900,2900,1900,4100,600,*,DOWN,ALU1 ++S 600,2000,600,2800,400,*,DOWN,ALU1 ++S 1200,2000,1200,2400,200,*,DOWN,POLY ++S 2400,2000,2400,2400,200,*,DOWN,POLY ++S 3000,2900,3000,7000,400,*,UP,ALU1 ++S 3000,7000,4000,7000,400,*,LEFT,ALU1 ++S 3800,5900,5500,5900,600,*,RIGHT,ALU1 ++S 2200,6100,2600,6100,200,*,RIGHT,POLY ++S 2600,3700,2600,6100,200,*,DOWN,POLY ++S 5800,3300,5800,6500,200,*,DOWN,POLY ++S 6200,6700,6200,8300,400,*,DOWN,PDIF ++S 5800,6500,5800,8500,200,5,DOWN,PTRANS ++S 4600,6500,4600,8500,200,4,DOWN,PTRANS ++S 4000,6700,4000,8300,600,*,UP,PDIF ++S 3400,6500,3400,8500,200,3,DOWN,PTRANS ++S 2200,6500,2200,8500,200,2,DOWN,PTRANS ++S 2800,6700,2800,8300,600,*,UP,PDIF ++S 1400,6500,1400,8500,200,1,DOWN,PTRANS ++S 1700,6700,1700,8300,400,n1,UP,PDIF ++S 5200,6700,5200,9100,600,*,UP,PDIF ++S 3400,8500,3400,8900,200,*,UP,POLY ++S 4600,8500,4600,8900,200,*,UP,POLY ++S 5800,8500,5800,8900,200,*,UP,POLY ++S 5000,6000,5000,8100,400,*,UP,ALU1 ++S 4000,6000,4000,6000,400,b,LEFT,CALU1 ++S 3000,8000,3000,8000,400,z,LEFT,CALU1 ++S 2400,3300,2400,3800,200,*,UP,POLY ++S 3400,5700,3400,6500,200,*,DOWN,POLY ++S 6000,2000,6000,2000,400,a,LEFT,CALU1 ++S 5000,2000,6100,2000,400,*,RIGHT,ALU1 ++S 5000,2000,5000,4000,600,*,DOWN,ALU1 ++S 5000,2000,5000,4000,400,a,DOWN,CALU1 ++S 600,2000,3800,2000,400,*,RIGHT,ALU1 ++S 4600,3700,4600,6500,200,*,DOWN,POLY ++S 3600,3700,4600,3700,200,*,LEFT,POLY ++S 2800,5000,3700,5000,200,*,LEFT,POLY ++S 3800,4900,6400,4900,400,*,RIGHT,ALU1 ++S 3800,2000,3800,4900,400,*,UP,ALU1 ++S 6400,6900,6400,7500,600,*,UP,PDIF ++S 6400,2900,6400,7700,400,*,UP,ALU1 ++S 1800,5000,3000,5000,600,*,LEFT,ALU1 ++S 1400,4800,1400,6500,200,*,DOWN,POLY ++S 1200,3300,1200,4900,200,*,UP,POLY ++V 2000,9300,CONT_BODY_N,* ++V 1000,9300,CONT_BODY_N,* ++V 2000,700,CONT_BODY_P,* ++V 1000,700,CONT_BODY_P,* ++V 800,8000,CONT_DIF_P,* ++V 4000,8000,CONT_DIF_P,an ++V 4200,1000,CONT_DIF_N,* ++V 5200,9000,CONT_DIF_P,* ++V 5200,1000,CONT_DIF_N,* ++V 3000,3000,CONT_DIF_N,an ++V 6400,3000,CONT_DIF_N,bn ++V 2800,8000,CONT_DIF_P,* ++V 1800,3000,CONT_DIF_N,* ++V 600,2700,CONT_DIF_N,bn ++V 3800,5900,CONT_POLY,* ++V 5400,5900,CONT_POLY,* ++V 6400,6800,CONT_DIF_P,bn ++V 4000,7200,CONT_DIF_P,an ++V 5000,3900,CONT_POLY,* ++V 3800,4800,CONT_POLY,bn ++V 6400,7600,CONT_DIF_P,bn ++V 1800,5000,CONT_POLY,an ++EOF +diff --git a/alliance/src/cells/src/msxlib/xnr2_x05.vbe b/alliance/src/cells/src/msxlib/xnr2_x05.vbe +new file mode 100644 +index 0000000..283bce3 +--- /dev/null ++++ b/alliance/src/cells/src/msxlib/xnr2_x05.vbe +@@ -0,0 +1,36 @@ ++ENTITY xnr2_x05 IS ++GENERIC ( ++ CONSTANT area : NATURAL := 7000; ++ CONSTANT cin_b : NATURAL := 6; ++ CONSTANT cin_a : NATURAL := 4; ++ CONSTANT rdown_b_z : NATURAL := 3580; ++ CONSTANT rdown_a_z : NATURAL := 3690; ++ CONSTANT rup_b_z : NATURAL := 4620; ++ CONSTANT rup_a_z : NATURAL := 4840; ++ CONSTANT tphl_a_z : NATURAL := 67; ++ CONSTANT tphl_b_z : NATURAL := 72; ++ CONSTANT tplh_b_z : NATURAL := 42; ++ CONSTANT tplh_a_z : NATURAL := 72; ++ CONSTANT tphh_b_z : NATURAL := 86; ++ CONSTANT tpll_b_z : NATURAL := 70; ++ CONSTANT tphh_a_z : NATURAL := 101; ++ CONSTANT tpll_a_z : NATURAL := 97; ++ CONSTANT transistors : NATURAL := 9 ++); ++PORT ( ++ b : in BIT; ++ a : in BIT; ++ z : out BIT; ++ vdd : in BIT; ++ vss : in BIT ++); ++END xnr2_x05; ++ ++ARCHITECTURE behaviour_data_flow OF xnr2_x05 IS ++ ++BEGIN ++ ASSERT ((vdd and not (vss)) = '1') ++ REPORT "power supply is missing on xnr2_x05" ++ SEVERITY WARNING; ++ z <= not ((b xor a)) after 1100 ps; ++END; +diff --git a/alliance/src/cells/src/msxlib/xnr2_x1.ap b/alliance/src/cells/src/msxlib/xnr2_x1.ap +new file mode 100644 +index 0000000..b9d72a3 +--- /dev/null ++++ b/alliance/src/cells/src/msxlib/xnr2_x1.ap +@@ -0,0 +1,114 @@ ++V ALLIANCE : 6 ++H xnr2_x1,P, 9/ 8/2014,100 ++A 0,0,7000,10000 ++R 1000,8000,ref_ref,z_80 ++R 2000,8000,ref_ref,z_80 ++R 4000,3000,ref_ref,a_30 ++R 5000,5000,ref_ref,b_50 ++R 4000,5000,ref_ref,b_50 ++R 4000,4000,ref_ref,b_40 ++R 5000,4000,ref_ref,a_40 ++R 5000,3000,ref_ref,a_30 ++R 3000,8000,ref_ref,z_80 ++R 1000,6000,ref_ref,z_60 ++R 1000,5000,ref_ref,z_50 ++R 1000,4000,ref_ref,z_40 ++R 1000,3000,ref_ref,z_30 ++R 1000,7000,ref_ref,z_70 ++S 1100,700,1900,700,600,*,RIGHT,PTIE ++S 1000,8000,3100,8000,400,*,LEFT,ALU1 ++S 1000,8100,3100,8100,400,*,LEFT,ALU1 ++S 1400,9400,1400,9700,200,*,UP,POLY ++S 2200,9400,2200,9700,200,*,UP,POLY ++S 3400,9400,3400,9700,200,*,UP,POLY ++S 4600,9400,4600,9700,200,*,UP,POLY ++S 5800,9400,5800,9700,200,*,UP,POLY ++S 5800,1300,5800,1700,200,*,DOWN,POLY ++S 2400,1300,2400,1700,200,*,DOWN,POLY ++S 3600,1300,3600,1700,200,*,DOWN,POLY ++S 1200,1300,1200,1700,200,*,DOWN,POLY ++S 6200,5900,6200,9200,400,*,DOWN,PDIF ++S 700,5900,700,9200,600,*,DOWN,PDIF ++S 5200,5900,5200,9200,600,*,UP,PDIF ++S 4000,5900,4000,9200,600,*,UP,PDIF ++S 2800,5900,2800,9200,600,*,UP,PDIF ++S 1700,5900,1700,9200,400,n1,UP,PDIF ++S 5200,6900,5200,9300,400,*,UP,ALU1 ++S 2000,7000,4000,7000,400,*,LEFT,ALU1 ++S 4000,7000,4000,8100,400,*,UP,ALU1 ++S 6400,2000,6400,6900,400,*,UP,ALU1 ++S 2800,4400,2800,6000,400,*,DOWN,ALU1 ++S 2800,6000,6400,6000,400,*,LEFT,ALU1 ++S 6400,6100,6400,6700,600,*,UP,PDIF ++S 1800,4500,2000,4500,600,*,LEFT,ALU1 ++S 3000,2900,3000,3600,400,*,UP,ALU1 ++S 2000,3600,2000,7000,400,*,UP,ALU1 ++S 4700,900,4700,3100,1600,*,UP,NDIF ++S 800,1900,800,3100,400,*,DOWN,NDIF ++S 6200,1900,6200,3100,400,*,UP,NDIF ++S 3000,1900,3000,3100,600,*,UP,NDIF ++S 1800,1900,1800,3100,600,*,UP,NDIF ++S 5000,3000,5000,4000,600,*,DOWN,ALU1 ++S 3900,3000,5000,3000,400,*,RIGHT,ALU1 ++S 4000,4000,4000,5000,400,b,UP,CALU1 ++S 5000,3000,5000,4000,400,a,DOWN,CALU1 ++S 3400,5300,4000,5300,200,*,RIGHT,POLY ++S 2000,3600,3000,3600,400,*,LEFT,ALU1 ++S 1000,2800,1900,2800,400,*,LEFT,ALU1 ++S 500,2000,6400,2000,400,*,RIGHT,ALU1 ++S 1200,1700,1200,3300,200,6,UP,NTRANS ++S 2400,1700,2400,3300,200,7,UP,NTRANS ++S 3600,1700,3600,3300,200,8,UP,NTRANS ++S 5800,5700,5800,9400,200,5,DOWN,PTRANS ++S 1000,3000,1000,8000,400,*,UP,ALU1 ++S 1000,3000,1000,8000,400,z,UP,CALU1 ++S 0,5000,7000,5000,10000,xnr2_x1,LEFT,TALU8 ++S 0,2200,7000,2200,5200,*,LEFT,PWELL ++S 0,7600,7000,7600,5600,*,LEFT,NWELL ++S 0,9400,7000,9400,1200,vdd,RIGHT,CALU1 ++S 0,600,7000,600,1200,vss,RIGHT,CALU1 ++S 1400,4500,2000,4500,600,*,LEFT,POLY ++S 5800,3300,5800,5700,200,*,DOWN,POLY ++S 3600,3700,4600,3700,200,*,LEFT,POLY ++S 2600,3700,2600,5300,200,*,DOWN,POLY ++S 4600,3700,4600,5700,200,*,DOWN,POLY ++S 4600,5700,4600,9400,200,4,DOWN,PTRANS ++S 3400,5700,3400,9400,200,3,DOWN,PTRANS ++S 1400,5700,1400,9400,200,1,DOWN,PTRANS ++S 2200,5700,2200,9400,200,2,DOWN,PTRANS ++S 2200,5300,2600,5300,200,*,RIGHT,POLY ++S 1400,4300,1400,5700,200,*,DOWN,POLY ++S 2400,3700,2600,3700,200,*,LEFT,POLY ++S 5800,1700,5800,3300,200,9,UP,NTRANS ++S 4000,3000,4000,3000,400,a,LEFT,CALU1 ++S 5000,5000,5000,5000,400,b,LEFT,CALU1 ++S 1200,3300,1200,4400,200,*,UP,POLY ++S 2000,8000,2000,8000,400,z,LEFT,CALU1 ++S 3000,8000,3000,8000,400,z,LEFT,CALU1 ++S 6400,2300,6400,2900,600,*,UP,NDIF ++S 3900,3900,3900,5000,600,*,UP,ALU1 ++S 3800,5000,5500,5000,400,*,RIGHT,ALU1 ++V 2000,700,CONT_BODY_P,* ++V 1000,700,CONT_BODY_P,* ++V 5200,7000,CONT_DIF_P,* ++V 5200,8000,CONT_DIF_P,* ++V 4000,8000,CONT_DIF_P,an ++V 6400,6800,CONT_DIF_P,bn ++V 4200,1000,CONT_DIF_N,* ++V 2800,4500,CONT_POLY,bn ++V 1800,2800,CONT_DIF_N,* ++V 600,2000,CONT_DIF_N,bn ++V 6400,6000,CONT_DIF_P,bn ++V 5200,9000,CONT_DIF_P,* ++V 5200,1000,CONT_DIF_N,* ++V 3000,3000,CONT_DIF_N,an ++V 1800,4500,CONT_POLY,an ++V 6400,3000,CONT_DIF_N,bn ++V 5000,3900,CONT_POLY,* ++V 2800,8000,CONT_DIF_P,* ++V 800,9000,CONT_DIF_P,* ++V 5400,5000,CONT_POLY,* ++V 4000,7200,CONT_DIF_P,an ++V 6400,2200,CONT_DIF_N,bn ++V 3800,4900,CONT_POLY,* ++EOF +diff --git a/alliance/src/cells/src/msxlib/xnr2_x1.vbe b/alliance/src/cells/src/msxlib/xnr2_x1.vbe +new file mode 100644 +index 0000000..55a219f +--- /dev/null ++++ b/alliance/src/cells/src/msxlib/xnr2_x1.vbe +@@ -0,0 +1,36 @@ ++ENTITY xnr2_x1 IS ++GENERIC ( ++ CONSTANT area : NATURAL := 7000; ++ CONSTANT cin_b : NATURAL := 10; ++ CONSTANT cin_a : NATURAL := 7; ++ CONSTANT rdown_b_z : NATURAL := 2020; ++ CONSTANT rdown_a_z : NATURAL := 2060; ++ CONSTANT rup_b_z : NATURAL := 2510; ++ CONSTANT rup_a_z : NATURAL := 2620; ++ CONSTANT tphl_a_z : NATURAL := 66; ++ CONSTANT tphl_b_z : NATURAL := 67; ++ CONSTANT tplh_b_z : NATURAL := 38; ++ CONSTANT tplh_a_z : NATURAL := 69; ++ CONSTANT tphh_b_z : NATURAL := 80; ++ CONSTANT tpll_b_z : NATURAL := 65; ++ CONSTANT tphh_a_z : NATURAL := 96; ++ CONSTANT tpll_a_z : NATURAL := 93; ++ CONSTANT transistors : NATURAL := 9 ++); ++PORT ( ++ b : in BIT; ++ a : in BIT; ++ z : out BIT; ++ vdd : in BIT; ++ vss : in BIT ++); ++END xnr2_x1; ++ ++ARCHITECTURE behaviour_data_flow OF xnr2_x1 IS ++ ++BEGIN ++ ASSERT ((vdd and not (vss)) = '1') ++ REPORT "power supply is missing on xnr2_x1" ++ SEVERITY WARNING; ++ z <= not ((b xor a)) after 1100 ps; ++END; +diff --git a/alliance/src/cells/src/msxlib/xor2_x05.ap b/alliance/src/cells/src/msxlib/xor2_x05.ap +new file mode 100644 +index 0000000..fb2b7d1 +--- /dev/null ++++ b/alliance/src/cells/src/msxlib/xor2_x05.ap +@@ -0,0 +1,122 @@ ++V ALLIANCE : 6 ++H xor2_x05,P, 9/ 8/2014,100 ++A 0,0,7000,10000 ++R 6000,7000,ref_ref,b_70 ++R 5000,6000,ref_ref,b_60 ++R 5000,4000,ref_ref,a_40 ++R 5000,3000,ref_ref,a_30 ++R 1000,6000,ref_ref,z_60 ++R 1000,5000,ref_ref,z_50 ++R 1000,4000,ref_ref,z_40 ++R 1000,3000,ref_ref,z_30 ++R 1000,7000,ref_ref,z_70 ++R 2000,7000,ref_ref,z_70 ++R 5000,2000,ref_ref,a_20 ++R 2000,2000,ref_ref,z_20 ++R 3000,2000,ref_ref,z_20 ++R 5000,7000,ref_ref,b_70 ++R 6000,8000,ref_ref,b_80 ++R 4000,4000,ref_ref,a_40 ++R 2000,3000,ref_ref,z_30 ++S 1100,9300,1900,9300,600,*,RIGHT,NTIE ++S 1200,700,1900,700,600,*,RIGHT,PTIE ++S 6400,1900,6400,5900,400,bn,DOWN,ALU1 ++S 4700,6500,4700,9100,1600,*,UP,PDIF ++S 5800,2600,5800,5500,200,*,UP,POLY ++S 6000,7000,6000,8000,400,b,UP,CALU1 ++S 5000,6000,5000,7000,400,b,DOWN,CALU1 ++S 5000,5900,5000,7000,400,*,DOWN,ALU1 ++S 6200,5700,6200,7300,400,*,UP,PDIF ++S 5800,5500,5800,7500,200,4,DOWN,PTRANS ++S 0,5000,7000,5000,10000,xor2_x05,LEFT,TALU8 ++S 0,2200,7000,2200,5200,*,LEFT,PWELL ++S 0,7600,7000,7600,5600,*,LEFT,NWELL ++S 0,9400,7000,9400,1200,vdd,RIGHT,CALU1 ++S 0,600,7000,600,1200,vss,RIGHT,CALU1 ++S 5000,2000,5000,4000,400,a,UP,CALU1 ++S 1000,7000,2100,7000,400,*,LEFT,ALU1 ++S 1200,6300,1200,8300,200,1,DOWN,PTRANS ++S 1800,6500,1800,8100,800,*,UP,PDIF ++S 2400,6300,2400,8300,200,2,DOWN,PTRANS ++S 1200,8300,1200,8700,200,*,UP,POLY ++S 2400,8300,2400,8700,200,*,UP,POLY ++S 3600,6300,3600,8300,200,3,DOWN,PTRANS ++S 3000,6500,3000,8100,600,*,UP,PDIF ++S 1000,7100,2100,7100,400,*,LEFT,ALU1 ++S 800,6500,800,7800,400,*,UP,PDIF ++S 3600,8300,3600,8700,200,*,UP,POLY ++S 3400,400,5800,400,200,*,RIGHT,POLY ++S 4000,1900,4000,3000,400,an,DOWN,ALU1 ++S 5000,1900,5000,4000,400,*,DOWN,ALU1 ++S 3900,4000,5000,4000,400,*,LEFT,ALU1 ++S 3900,4100,5000,4100,400,*,LEFT,ALU1 ++S 6200,1900,6200,2400,400,*,UP,NDIF ++S 5800,1700,5800,2600,200,9,UP,NTRANS ++S 4000,1900,4000,2400,1000,*,DOWN,NDIF ++S 4600,1700,4600,2600,200,8,UP,NTRANS ++S 3400,1700,3400,2600,200,7,UP,NTRANS ++S 2800,1900,2800,2400,1000,*,DOWN,NDIF ++S 2200,1700,2200,2600,200,6,UP,NTRANS ++S 1800,1900,1800,2400,600,n1,UP,NDIF ++S 1400,1700,1400,2600,200,5,UP,NTRANS ++S 3400,2600,3400,3000,200,*,UP,POLY ++S 2200,1300,2200,1700,200,*,UP,POLY ++S 1400,1300,1400,1700,200,*,UP,POLY ++S 3400,400,3400,1700,200,*,DOWN,POLY ++S 4600,1300,4600,1700,200,*,UP,POLY ++S 5800,600,5800,1700,200,*,UP,POLY ++S 5200,900,5200,2400,600,*,UP,NDIF ++S 2200,3000,2600,3000,200,*,LEFT,POLY ++S 3000,3000,4000,3000,400,*,RIGHT,ALU1 ++S 1000,3000,2000,3000,600,*,RIGHT,ALU1 ++S 2000,2000,2000,3000,400,*,DOWN,ALU1 ++S 2000,1900,3100,1900,400,*,RIGHT,ALU1 ++S 2000,2000,3100,2000,400,*,RIGHT,ALU1 ++S 1000,3000,1000,7000,400,*,DOWN,ALU1 ++S 1000,3000,1000,7000,400,z,DOWN,CALU1 ++S 2000,2000,2000,3000,400,z,DOWN,CALU1 ++S 3000,2000,3000,2000,400,z,LEFT,CALU1 ++S 4000,4000,4000,4000,400,a,LEFT,CALU1 ++S 700,1900,700,2400,600,*,UP,NDIF ++S 800,700,800,2100,400,*,DOWN,ALU1 ++S 3600,5900,3600,6300,200,*,UP,POLY ++S 3000,3000,3000,7100,400,*,UP,ALU1 ++S 4900,6500,4900,8100,1200,*,DOWN,PDIF ++S 2000,7000,2000,7000,400,z,LEFT,CALU1 ++S 5200,7900,5200,9300,400,*,UP,ALU1 ++S 6100,6900,6100,8100,600,*,UP,ALU1 ++S 5000,7000,6200,7000,600,*,RIGHT,ALU1 ++S 5800,7500,5800,8300,200,*,UP,POLY ++S 2600,3000,2600,5300,200,*,DOWN,POLY ++S 2400,5300,3800,5300,200,*,LEFT,POLY ++S 2400,5200,2400,6300,200,*,DOWN,POLY ++S 1800,4400,3000,4400,600,*,RIGHT,ALU1 ++S 1400,2600,1400,4600,200,*,UP,POLY ++S 1200,4500,1200,6300,200,*,DOWN,POLY ++S 4600,2600,4600,5900,200,*,UP,POLY ++S 3600,5900,4600,5900,200,*,LEFT,POLY ++S 3800,5000,3800,8000,400,*,DOWN,ALU1 ++S 3800,5000,6400,5000,400,*,LEFT,ALU1 ++S 500,8000,3800,8000,400,*,RIGHT,ALU1 ++S 5300,5700,5300,7300,600,*,UP,PDIF ++V 2000,9300,CONT_BODY_N,* ++V 1000,9300,CONT_BODY_N,* ++V 2000,700,CONT_BODY_P,* ++V 1100,700,CONT_BODY_P,* ++V 6400,5800,CONT_DIF_P,bn ++V 4800,4000,CONT_POLY,* ++V 1800,7000,CONT_DIF_P,* ++V 600,8000,CONT_DIF_P,bn ++V 3000,7000,CONT_DIF_P,an ++V 5200,1000,CONT_DIF_N,* ++V 2800,2000,CONT_DIF_N,* ++V 4000,2000,CONT_DIF_N,an ++V 4200,9000,CONT_DIF_P,* ++V 6400,2000,CONT_DIF_N,bn ++V 800,2000,CONT_DIF_N,* ++V 5200,8000,CONT_DIF_P,* ++V 5200,9000,CONT_DIF_P,* ++V 6100,8100,CONT_POLY,* ++V 1800,4400,CONT_POLY,an ++V 3800,5100,CONT_POLY,bn ++EOF +diff --git a/alliance/src/cells/src/msxlib/xor2_x05.vbe b/alliance/src/cells/src/msxlib/xor2_x05.vbe +new file mode 100644 +index 0000000..9bb09a8 +--- /dev/null ++++ b/alliance/src/cells/src/msxlib/xor2_x05.vbe +@@ -0,0 +1,36 @@ ++ENTITY xor2_x05 IS ++GENERIC ( ++ CONSTANT area : NATURAL := 7000; ++ CONSTANT cin_b : NATURAL := 5; ++ CONSTANT cin_a : NATURAL := 4; ++ CONSTANT rdown_b_z : NATURAL := 3520; ++ CONSTANT rdown_a_z : NATURAL := 3620; ++ CONSTANT rup_b_z : NATURAL := 4790; ++ CONSTANT rup_a_z : NATURAL := 4890; ++ CONSTANT tplh_a_z : NATURAL := 69; ++ CONSTANT tphl_b_z : NATURAL := 35; ++ CONSTANT tplh_b_z : NATURAL := 89; ++ CONSTANT tphh_b_z : NATURAL := 64; ++ CONSTANT tphl_a_z : NATURAL := 65; ++ CONSTANT tpll_a_z : NATURAL := 93; ++ CONSTANT tpll_b_z : NATURAL := 94; ++ CONSTANT tphh_a_z : NATURAL := 91; ++ CONSTANT transistors : NATURAL := 9 ++); ++PORT ( ++ b : in BIT; ++ a : in BIT; ++ z : out BIT; ++ vdd : in BIT; ++ vss : in BIT ++); ++END xor2_x05; ++ ++ARCHITECTURE behaviour_data_flow OF xor2_x05 IS ++ ++BEGIN ++ ASSERT ((vdd and not (vss)) = '1') ++ REPORT "power supply is missing on xor2_x05" ++ SEVERITY WARNING; ++ z <= (b xor a) after 1000 ps; ++END; +diff --git a/alliance/src/cells/src/msxlib/xor2_x1.ap b/alliance/src/cells/src/msxlib/xor2_x1.ap +new file mode 100644 +index 0000000..05b2324 +--- /dev/null ++++ b/alliance/src/cells/src/msxlib/xor2_x1.ap +@@ -0,0 +1,120 @@ ++V ALLIANCE : 6 ++H xor2_x1,P, 9/ 8/2014,100 ++A 0,0,7000,10000 ++R 5000,2000,ref_ref,a_20 ++R 5000,6000,ref_ref,b_60 ++R 5000,4000,ref_ref,a_40 ++R 5000,3000,ref_ref,a_30 ++R 1000,6000,ref_ref,z_60 ++R 1000,5000,ref_ref,z_50 ++R 1000,4000,ref_ref,z_40 ++R 1000,3000,ref_ref,z_30 ++R 1000,7000,ref_ref,z_70 ++R 2000,7000,ref_ref,z_70 ++R 1000,2000,ref_ref,z_20 ++R 2000,2000,ref_ref,z_20 ++R 5000,7000,ref_ref,b_70 ++R 4000,4000,ref_ref,a_40 ++R 3000,2000,ref_ref,z_20 ++R 6000,8000,ref_ref,b_80 ++R 6000,7000,ref_ref,b_70 ++S 6400,2000,6400,5000,400,*,UP,ALU1 ++S 2000,7000,2000,7000,400,z,LEFT,CALU1 ++S 3000,2000,3000,2000,400,z,LEFT,CALU1 ++S 2000,2000,2000,2000,400,z,LEFT,CALU1 ++S 4000,4000,4000,4000,400,a,LEFT,CALU1 ++S 2000,6000,3000,6000,400,*,LEFT,ALU1 ++S 0,5000,7000,5000,10000,xor2_x1,LEFT,TALU8 ++S 0,2200,7000,2200,5200,*,LEFT,PWELL ++S 0,7600,7000,7600,5600,*,LEFT,NWELL ++S 0,9400,7000,9400,1200,vdd,RIGHT,CALU1 ++S 0,600,7000,600,1200,vss,RIGHT,CALU1 ++S 5000,2000,5000,4000,400,a,UP,CALU1 ++S 1000,7000,2100,7000,400,*,RIGHT,ALU1 ++S 1000,7100,2100,7100,400,*,RIGHT,ALU1 ++S 1000,2000,1000,7000,400,*,DOWN,ALU1 ++S 1000,2000,1000,7000,400,z,DOWN,CALU1 ++S 4000,1900,4000,3000,400,an,DOWN,ALU1 ++S 2000,3000,2000,6000,400,*,UP,ALU1 ++S 2000,3000,4000,3000,400,*,RIGHT,ALU1 ++S 3400,400,5600,400,200,*,RIGHT,POLY ++S 1200,9400,1200,9700,200,*,DOWN,POLY ++S 2400,9400,2400,9700,200,*,DOWN,POLY ++S 3600,9400,3600,9700,200,*,DOWN,POLY ++S 3000,6000,3000,7100,400,*,DOWN,ALU1 ++S 3900,4000,5000,4000,400,*,LEFT,ALU1 ++S 3900,4100,5000,4100,400,*,LEFT,ALU1 ++S 1000,2000,3000,2000,600,*,RIGHT,ALU1 ++S 3000,5000,6400,5000,400,*,RIGHT,ALU1 ++S 5200,9400,5200,9700,200,*,DOWN,POLY ++S 5000,6000,5000,7000,400,b,UP,CALU1 ++S 5000,5900,5000,7000,400,*,DOWN,ALU1 ++S 6000,7000,6000,8000,400,b,UP,CALU1 ++S 5000,7000,6500,7000,600,*,RIGHT,ALU1 ++S 5000,1900,5000,4000,400,*,DOWN,ALU1 ++S 4600,7900,4600,9300,400,*,UP,ALU1 ++S 3800,5000,3800,8000,400,*,UP,ALU1 ++S 500,8000,3800,8000,400,*,RIGHT,ALU1 ++S 6000,7000,6000,8100,400,*,UP,ALU1 ++S 6200,1700,6200,2900,400,*,UP,NDIF ++S 1400,1200,1400,1500,200,*,UP,POLY ++S 2200,1200,2200,1500,200,*,UP,POLY ++S 3400,400,3400,1500,200,*,DOWN,POLY ++S 4600,1100,4600,1500,200,*,UP,POLY ++S 5800,400,5800,1500,200,*,UP,POLY ++S 700,900,700,3000,600,*,UP,NDIF ++S 800,900,800,3000,600,*,UP,NDIF ++S 1800,1700,1800,3000,600,n1,UP,NDIF ++S 1400,1500,1400,3200,200,5,UP,NTRANS ++S 2200,1500,2200,3200,200,6,UP,NTRANS ++S 2200,3600,2800,3600,200,*,LEFT,POLY ++S 3400,3200,3400,3600,200,*,UP,POLY ++S 1500,4400,2000,4400,600,*,LEFT,POLY ++S 4000,1700,4000,3000,1000,*,DOWN,NDIF ++S 4600,1500,4600,3200,200,8,UP,NTRANS ++S 3400,1500,3400,3200,200,7,UP,NTRANS ++S 2800,1700,2800,3000,1000,*,DOWN,NDIF ++S 5200,900,5200,3000,600,*,UP,NDIF ++S 5800,1500,5800,3200,200,9,UP,NTRANS ++S 2400,5200,2800,5200,200,*,RIGHT,POLY ++S 1400,3200,1400,4600,200,*,UP,POLY ++S 1200,4500,1200,5700,200,*,UP,POLY ++S 2400,5600,2400,9400,200,2,DOWN,PTRANS ++S 3600,5600,3600,9400,200,3,DOWN,PTRANS ++S 3000,5800,3000,9200,600,*,UP,PDIF ++S 800,5800,800,9200,400,*,UP,PDIF ++S 1200,5600,1200,9400,200,1,DOWN,PTRANS ++S 1800,5800,1800,9200,1000,*,UP,PDIF ++S 4400,5800,4400,9200,800,*,DOWN,PDIF ++S 5200,5600,5200,9400,200,4,DOWN,PTRANS ++S 5600,5800,5600,9200,400,*,UP,PDIF ++S 5800,5000,5800,6000,400,*,DOWN,ALU1 ++S 5800,3200,5800,5200,200,*,UP,POLY ++S 2800,3600,2800,5200,200,*,DOWN,POLY ++S 5200,5200,6600,5200,200,*,LEFT,POLY ++S 6600,5200,6600,6800,200,*,DOWN,POLY ++S 6400,2200,6400,2800,600,*,DOWN,NDIF ++S 3000,4300,3000,5000,400,*,DOWN,ALU1 ++S 4600,3200,4600,4000,200,*,DOWN,POLY ++S 4200,4000,4200,5200,200,*,UP,POLY ++S 3600,5200,4200,5200,200,*,LEFT,POLY ++V 2000,700,CONT_BODY_P,* ++V 3000,6200,CONT_DIF_P,an ++V 600,8000,CONT_DIF_P,bn ++V 1800,7000,CONT_DIF_P,* ++V 5200,1000,CONT_DIF_N,* ++V 4000,2000,CONT_DIF_N,an ++V 2800,2000,CONT_DIF_N,* ++V 3000,7000,CONT_DIF_P,an ++V 6400,7000,CONT_POLY,* ++V 4600,9000,CONT_DIF_P,* ++V 4600,8000,CONT_DIF_P,* ++V 800,1000,CONT_DIF_N,* ++V 4000,2800,CONT_DIF_N,an ++V 3000,4400,CONT_POLY,bn ++V 2000,4400,CONT_POLY,an ++V 6400,2900,CONT_DIF_N,bn ++V 5800,5900,CONT_DIF_P,bn ++V 6400,2100,CONT_DIF_N,bn ++V 4400,4000,CONT_POLY,* ++EOF +diff --git a/alliance/src/cells/src/msxlib/xor2_x1.vbe b/alliance/src/cells/src/msxlib/xor2_x1.vbe +new file mode 100644 +index 0000000..82248ab +--- /dev/null ++++ b/alliance/src/cells/src/msxlib/xor2_x1.vbe +@@ -0,0 +1,36 @@ ++ENTITY xor2_x1 IS ++GENERIC ( ++ CONSTANT area : NATURAL := 7000; ++ CONSTANT cin_b : NATURAL := 9; ++ CONSTANT cin_a : NATURAL := 7; ++ CONSTANT rdown_b_z : NATURAL := 1860; ++ CONSTANT rdown_a_z : NATURAL := 1910; ++ CONSTANT rup_b_z : NATURAL := 2530; ++ CONSTANT rup_a_z : NATURAL := 2570; ++ CONSTANT tplh_a_z : NATURAL := 65; ++ CONSTANT tphl_b_z : NATURAL := 33; ++ CONSTANT tplh_b_z : NATURAL := 82; ++ CONSTANT tphh_b_z : NATURAL := 59; ++ CONSTANT tphl_a_z : NATURAL := 62; ++ CONSTANT tpll_a_z : NATURAL := 88; ++ CONSTANT tpll_b_z : NATURAL := 87; ++ CONSTANT tphh_a_z : NATURAL := 86; ++ CONSTANT transistors : NATURAL := 9 ++); ++PORT ( ++ b : in BIT; ++ a : in BIT; ++ z : out BIT; ++ vdd : in BIT; ++ vss : in BIT ++); ++END xor2_x1; ++ ++ARCHITECTURE behaviour_data_flow OF xor2_x1 IS ++ ++BEGIN ++ ASSERT ((vdd and not (vss)) = '1') ++ REPORT "power supply is missing on xor2_x1" ++ SEVERITY WARNING; ++ z <= (b xor a) after 1000 ps; ++END; +diff --git a/alliance/src/cells/src/pxlib/CATAL b/alliance/src/cells/src/pxlib/CATAL +index 1c60cc6..f0f8a4d 100644 +--- a/alliance/src/cells/src/pxlib/CATAL ++++ b/alliance/src/cells/src/pxlib/CATAL +@@ -11,3 +11,16 @@ pvsseck_px C + pvsse_px C + pvssick_px C + pvssi_px C ++pck_sp C ++piot_sp C ++pi_sp C ++po_sp C ++pot_sp C ++pvddeck_sp C ++pvdde_sp C ++pvddick_sp C ++pvddi_sp C ++pvsseck_sp C ++pvsse_sp C ++pvssick_sp C ++pvssi_sp C +diff --git a/alliance/src/cells/src/pxlib/Makefile.am b/alliance/src/cells/src/pxlib/Makefile.am +index f286c75..3a2ed65 100644 +--- a/alliance/src/cells/src/pxlib/Makefile.am ++++ b/alliance/src/cells/src/pxlib/Makefile.am +@@ -29,7 +29,33 @@ pxlib_DATA=CATAL \ + pvssick_px.ap \ + pvssick_px.vbe \ + pvssi_px.ap \ +- pvssi_px.vbe ++ pvssi_px.vbe \ ++ pck_sp.ap \ ++ pck_sp.vbe \ ++ piot_sp.ap \ ++ piot_sp.vbe \ ++ pi_sp.ap \ ++ pi_sp.vbe \ ++ po_sp.ap \ ++ po_sp.vbe \ ++ pot_sp.ap \ ++ pot_sp.vbe \ ++ pvddeck_sp.ap \ ++ pvddeck_sp.vbe \ ++ pvdde_sp.ap \ ++ pvdde_sp.vbe \ ++ pvddick_sp.ap \ ++ pvddick_sp.vbe \ ++ pvddi_sp.ap \ ++ pvddi_sp.vbe \ ++ pvsseck_sp.ap \ ++ pvsseck_sp.vbe \ ++ pvsse_sp.ap \ ++ pvsse_sp.vbe \ ++ pvssick_sp.ap \ ++ pvssick_sp.vbe \ ++ pvssi_sp.ap \ ++ pvssi_sp.vbe + + EXTRA_DIST=$(pxlib_DATA) + +diff --git a/alliance/src/cells/src/pxlib/pck_sp.ap b/alliance/src/cells/src/pxlib/pck_sp.ap +new file mode 100644 +index 0000000..6bc30b2 +--- /dev/null ++++ b/alliance/src/cells/src/pxlib/pck_sp.ap +@@ -0,0 +1,55 @@ ++V ALLIANCE : 6 ++H pck_sp,P, 4/ 9/2014,100 ++A 0,0,20000,40000 ++C 20000,2000,500,ck,3,EAST,ALU3 ++C 0,2000,500,ck,2,WEST,ALU3 ++C 20000,5000,1200,vddi,1,EAST,ALU3 ++C 20000,3500,1200,vssi,1,EAST,ALU3 ++C 20000,17000,1200,vdde,5,EAST,ALU3 ++C 20000,14000,1200,vdde,3,EAST,ALU3 ++C 20000,11000,1200,vdde,1,EAST,ALU3 ++C 20000,9500,1200,vsse,1,EAST,ALU3 ++C 20000,12500,1200,vsse,3,EAST,ALU3 ++C 20000,15500,1200,vsse,5,EAST,ALU3 ++C 20000,18500,1200,vsse,7,EAST,ALU3 ++C 0,17000,1200,vdde,4,WEST,ALU3 ++C 0,14000,1200,vdde,2,WEST,ALU3 ++C 0,11000,1200,vdde,0,WEST,ALU3 ++C 0,9500,1200,vsse,0,WEST,ALU3 ++C 0,5000,1200,vddi,0,WEST,ALU3 ++C 0,3500,1200,vssi,0,WEST,ALU3 ++C 0,12500,1200,vsse,2,WEST,ALU3 ++C 0,15500,1200,vsse,4,WEST,ALU3 ++C 0,18500,1200,vsse,6,WEST,ALU3 ++C 20000,8000,1200,vddi,3,EAST,ALU3 ++C 20000,6500,1200,vssi,3,EAST,ALU3 ++C 0,6500,1200,vssi,2,WEST,ALU3 ++C 0,8000,1200,vddi,2,WEST,ALU3 ++C 10000,40000,100,pad,0,NORTH,ALU1 ++S 0,6500,400,6500,1200,*,RIGHT,ALU3 ++S 0,5000,400,5000,1200,*,RIGHT,ALU3 ++S 0,3500,400,3500,1200,*,RIGHT,ALU3 ++S 0,2000,400,2000,500,*,RIGHT,ALU3 ++S 0,18500,400,18500,1200,*,RIGHT,ALU3 ++S 0,17000,400,17000,1200,*,RIGHT,ALU3 ++S 0,12500,400,12500,1200,*,RIGHT,ALU3 ++S 0,15500,400,15500,1200,*,RIGHT,ALU3 ++S 0,14000,400,14000,1200,*,RIGHT,ALU3 ++S 0,11000,400,11000,1200,*,RIGHT,ALU3 ++S 0,9500,400,9500,1200,*,RIGHT,ALU3 ++S 0,8000,400,8000,1200,*,RIGHT,ALU3 ++S 19600,2000,20000,2000,500,*,RIGHT,ALU3 ++S 19600,3500,20000,3500,1200,*,RIGHT,ALU3 ++S 19600,5000,20000,5000,1200,*,RIGHT,ALU3 ++S 19600,6500,20000,6500,1200,*,RIGHT,ALU3 ++S 19600,8000,20000,8000,1200,*,RIGHT,ALU3 ++S 19600,9500,20000,9500,1200,*,RIGHT,ALU3 ++S 19600,11000,20000,11000,1200,*,RIGHT,ALU3 ++S 19600,12500,20000,12500,1200,*,RIGHT,ALU3 ++S 19600,14000,20000,14000,1200,*,RIGHT,ALU3 ++S 19600,15500,20000,15500,1200,*,RIGHT,ALU3 ++S 19600,17000,20000,17000,1200,*,RIGHT,ALU3 ++S 19600,18500,20000,18500,1200,*,RIGHT,ALU3 ++S 10000,30000,10000,40000,100,*,DOWN,ALU1 ++I 0,0,pck_px,a,NOSYM ++EOF +diff --git a/alliance/src/cells/src/pxlib/pck_sp.vbe b/alliance/src/cells/src/pxlib/pck_sp.vbe +new file mode 100644 +index 0000000..a0cc38b +--- /dev/null ++++ b/alliance/src/cells/src/pxlib/pck_sp.vbe +@@ -0,0 +1,29 @@ ++ENTITY pck_sp IS ++ GENERIC ( ++ CONSTANT area : NATURAL := 80000; ++ CONSTANT cin_pad : NATURAL := 1326; ++ CONSTANT tpll_pad : NATURAL := 1443; ++ CONSTANT rdown_pad : NATURAL := 58; ++ CONSTANT tphh_pad : NATURAL := 228; ++ CONSTANT rup_pad : NATURAL := 68 ++ ); ++ PORT ( ++ pad : in BIT; ++ ck : out BIT; ++ vdde : in BIT; ++ vddi : in BIT; ++ vsse : in BIT; ++ vssi : in BIT ++ ); ++END pck_sp; ++ ++ ++ARCHITECTURE behaviour_data_flow OF pck_sp IS ++ ++BEGIN ++ ck <= pad; ++ ++ ASSERT ((((vddi and vdde) and not (vssi)) and not (vsse)) = '1') ++ REPORT "power supply is missing on pck_sp" ++ SEVERITY WARNING; ++END; +diff --git a/alliance/src/cells/src/pxlib/pi_sp.ap b/alliance/src/cells/src/pxlib/pi_sp.ap +new file mode 100644 +index 0000000..712c9e8 +--- /dev/null ++++ b/alliance/src/cells/src/pxlib/pi_sp.ap +@@ -0,0 +1,58 @@ ++V ALLIANCE : 6 ++H pi_sp,P, 4/ 9/2014,100 ++A 0,0,20000,40000 ++C 10000,40000,100,pad,0,NORTH,ALU1 ++C 4000,0,200,t,0,SOUTH,ALU1 ++C 4000,0,200,t,1,SOUTH,ALU2 ++C 0,8000,1200,vddi,6,WEST,ALU3 ++C 0,6500,1200,vssi,6,WEST,ALU3 ++C 20000,6500,1200,vssi,7,EAST,ALU3 ++C 20000,8000,1200,vddi,7,EAST,ALU3 ++C 0,18500,1200,vsse,6,WEST,ALU3 ++C 0,15500,1200,vsse,4,WEST,ALU3 ++C 0,12500,1200,vsse,2,WEST,ALU3 ++C 0,3500,1200,vssi,4,WEST,ALU3 ++C 0,5000,1200,vddi,4,WEST,ALU3 ++C 0,9500,1200,vsse,0,WEST,ALU3 ++C 0,11000,1200,vdde,0,WEST,ALU3 ++C 0,14000,1200,vdde,2,WEST,ALU3 ++C 0,17000,1200,vdde,4,WEST,ALU3 ++C 20000,18500,1200,vsse,7,EAST,ALU3 ++C 20000,15500,1200,vsse,5,EAST,ALU3 ++C 20000,12500,1200,vsse,3,EAST,ALU3 ++C 20000,9500,1200,vsse,1,EAST,ALU3 ++C 20000,11000,1200,vdde,1,EAST,ALU3 ++C 20000,14000,1200,vdde,3,EAST,ALU3 ++C 20000,17000,1200,vdde,5,EAST,ALU3 ++C 20000,3500,1200,vssi,5,EAST,ALU3 ++C 20000,5000,1200,vddi,5,EAST,ALU3 ++C 0,2000,500,ck,0,WEST,ALU3 ++C 20000,2000,500,ck,1,EAST,ALU3 ++S 10000,30000,10000,40000,100,*,DOWN,ALU1 ++S 19600,18500,20000,18500,1200,*,RIGHT,ALU3 ++S 19600,17000,20000,17000,1200,*,RIGHT,ALU3 ++S 19600,15500,20000,15500,1200,*,RIGHT,ALU3 ++S 19600,14000,20000,14000,1200,*,RIGHT,ALU3 ++S 19600,12500,20000,12500,1200,*,RIGHT,ALU3 ++S 19600,11000,20000,11000,1200,*,RIGHT,ALU3 ++S 19600,9500,20000,9500,1200,*,RIGHT,ALU3 ++S 19600,8000,20000,8000,1200,*,RIGHT,ALU3 ++S 19600,6500,20000,6500,1200,*,RIGHT,ALU3 ++S 19600,5000,20000,5000,1200,*,RIGHT,ALU3 ++S 19600,3500,20000,3500,1200,*,RIGHT,ALU3 ++S 19600,2000,20000,2000,500,*,RIGHT,ALU3 ++S 0,8000,400,8000,1200,*,RIGHT,ALU3 ++S 0,9500,400,9500,1200,*,RIGHT,ALU3 ++S 0,11000,400,11000,1200,*,RIGHT,ALU3 ++S 0,14000,400,14000,1200,*,RIGHT,ALU3 ++S 0,15500,400,15500,1200,*,RIGHT,ALU3 ++S 0,12500,400,12500,1200,*,RIGHT,ALU3 ++S 0,17000,400,17000,1200,*,RIGHT,ALU3 ++S 0,18500,400,18500,1200,*,RIGHT,ALU3 ++S 0,2000,400,2000,500,*,RIGHT,ALU3 ++S 0,3500,400,3500,1200,*,RIGHT,ALU3 ++S 0,5000,400,5000,1200,*,RIGHT,ALU3 ++S 0,6500,400,6500,1200,*,RIGHT,ALU3 ++I 0,0,pi_px,a,NOSYM ++V 4000,0,CONT_VIA,* ++EOF +diff --git a/alliance/src/cells/src/pxlib/pi_sp.vbe b/alliance/src/cells/src/pxlib/pi_sp.vbe +new file mode 100644 +index 0000000..44119b8 +--- /dev/null ++++ b/alliance/src/cells/src/pxlib/pi_sp.vbe +@@ -0,0 +1,30 @@ ++ENTITY pi_sp IS ++ GENERIC ( ++ CONSTANT area : NATURAL := 80000; ++ CONSTANT cin_pad : NATURAL := 654; ++ CONSTANT tpll_pad : NATURAL := 1487; ++ CONSTANT rdown_pad : NATURAL := 234; ++ CONSTANT tphh_pad : NATURAL := 233; ++ CONSTANT rup_pad : NATURAL := 273 ++ ); ++ PORT ( ++ pad : in BIT; ++ t : out BIT; ++ ck : in BIT; ++ vdde : in BIT; ++ vddi : in BIT; ++ vsse : in BIT; ++ vssi : in BIT ++ ); ++END pi_sp; ++ ++ ++ARCHITECTURE behaviour_data_flow OF pi_sp IS ++ ++BEGIN ++ t <= pad; ++ ++ ASSERT ((((vddi and vdde) and not (vssi)) and not (vsse)) = '1') ++ REPORT "power supply is missing on pi_sp" ++ SEVERITY WARNING; ++END; +diff --git a/alliance/src/cells/src/pxlib/piot_sp.ap b/alliance/src/cells/src/pxlib/piot_sp.ap +new file mode 100644 +index 0000000..12d6bdf +--- /dev/null ++++ b/alliance/src/cells/src/pxlib/piot_sp.ap +@@ -0,0 +1,64 @@ ++V ALLIANCE : 6 ++H piot_sp,P, 5/ 9/2014,100 ++A 0,0,20000,40000 ++C 10000,40000,100,pad,2,NORTH,ALU1 ++C 4000,0,200,t,0,SOUTH,ALU1 ++C 4000,0,200,t,1,SOUTH,ALU2 ++C 14000,0,200,i,0,SOUTH,ALU1 ++C 14000,0,200,i,1,SOUTH,ALU2 ++C 0,8000,1200,vddi,2,WEST,ALU3 ++C 0,6500,1200,vssi,2,WEST,ALU3 ++C 20000,6500,1200,vssi,3,EAST,ALU3 ++C 20000,8000,1200,vddi,3,EAST,ALU3 ++C 0,18500,1200,vsse,6,WEST,ALU3 ++C 0,15500,1200,vsse,4,WEST,ALU3 ++C 0,12500,1200,vsse,2,WEST,ALU3 ++C 0,3500,1200,vssi,0,WEST,ALU3 ++C 0,5000,1200,vddi,0,WEST,ALU3 ++C 0,9500,1200,vsse,0,WEST,ALU3 ++C 0,11000,1200,vdde,0,WEST,ALU3 ++C 0,14000,1200,vdde,2,WEST,ALU3 ++C 0,17000,1200,vdde,4,WEST,ALU3 ++C 20000,18500,1200,vsse,7,EAST,ALU3 ++C 20000,15500,1200,vsse,5,EAST,ALU3 ++C 20000,12500,1200,vsse,3,EAST,ALU3 ++C 20000,9500,1200,vsse,1,EAST,ALU3 ++C 20000,11000,1200,vdde,1,EAST,ALU3 ++C 20000,14000,1200,vdde,3,EAST,ALU3 ++C 20000,17000,1200,vdde,5,EAST,ALU3 ++C 20000,3500,1200,vssi,1,EAST,ALU3 ++C 20000,5000,1200,vddi,1,EAST,ALU3 ++C 0,2000,500,ck,0,WEST,ALU3 ++C 20000,2000,500,ck,1,EAST,ALU3 ++C 15000,0,200,b,1,SOUTH,ALU2 ++C 15000,0,200,b,0,SOUTH,ALU1 ++S 10000,30000,10000,40000,100,*,DOWN,ALU1 ++S 19600,18500,20000,18500,1200,*,RIGHT,ALU3 ++S 19600,17000,20000,17000,1200,*,RIGHT,ALU3 ++S 19600,15500,20000,15500,1200,*,RIGHT,ALU3 ++S 19600,14000,20000,14000,1200,*,RIGHT,ALU3 ++S 19600,12500,20000,12500,1200,*,RIGHT,ALU3 ++S 19600,11000,20000,11000,1200,*,RIGHT,ALU3 ++S 19600,9500,20000,9500,1200,*,RIGHT,ALU3 ++S 19600,8000,20000,8000,1200,*,RIGHT,ALU3 ++S 19600,6500,20000,6500,1200,*,RIGHT,ALU3 ++S 19600,5000,20000,5000,1200,*,RIGHT,ALU3 ++S 19600,3500,20000,3500,1200,*,RIGHT,ALU3 ++S 19600,2000,20000,2000,500,*,RIGHT,ALU3 ++S 0,8000,400,8000,1200,*,RIGHT,ALU3 ++S 0,9500,400,9500,1200,*,RIGHT,ALU3 ++S 0,11000,400,11000,1200,*,RIGHT,ALU3 ++S 0,14000,400,14000,1200,*,RIGHT,ALU3 ++S 0,15500,400,15500,1200,*,RIGHT,ALU3 ++S 0,12500,400,12500,1200,*,RIGHT,ALU3 ++S 0,17000,400,17000,1200,*,RIGHT,ALU3 ++S 0,18500,400,18500,1200,*,RIGHT,ALU3 ++S 0,2000,400,2000,500,*,RIGHT,ALU3 ++S 0,3500,400,3500,1200,*,RIGHT,ALU3 ++S 0,5000,400,5000,1200,*,RIGHT,ALU3 ++S 0,6500,400,6500,1200,*,RIGHT,ALU3 ++I 0,0,piot_px,a,NOSYM ++V 4000,0,CONT_VIA,* ++V 14000,0,CONT_VIA,* ++V 15000,0,CONT_VIA,b ++EOF +diff --git a/alliance/src/cells/src/pxlib/piot_sp.vbe b/alliance/src/cells/src/pxlib/piot_sp.vbe +new file mode 100644 +index 0000000..ceac775 +--- /dev/null ++++ b/alliance/src/cells/src/pxlib/piot_sp.vbe +@@ -0,0 +1,44 @@ ++ENTITY piot_sp IS ++ GENERIC ( ++ CONSTANT area : NATURAL := 80000; ++ CONSTANT rup : NATURAL := 402; ++ CONSTANT rdown : NATURAL := 0 ++ ); ++ PORT ( ++ i : in BIT; ++ b : in BIT; ++ t : out BIT; ++ pad : inout MUX_BIT BUS; ++ ck : in BIT; ++ vdde : in BIT; ++ vddi : in BIT; ++ vsse : in BIT; ++ vssi : in BIT ++ ); ++END piot_sp; ++ ++ARCHITECTURE behaviour_data_flow OF piot_sp IS ++ SIGNAL b1 : BIT; ++ SIGNAL b2 : BIT; ++ SIGNAL b3 : BIT; ++ SIGNAL b4 : BIT; ++ SIGNAL b5 : BIT; ++ SIGNAL b6 : BIT; ++ ++BEGIN ++ b6 <= b5; ++ b5 <= b4; ++ b4 <= b3; ++ b3 <= b2; ++ b2 <= b1; ++ b1 <= b; ++ label0 : BLOCK (b6 = '1') ++ BEGIN ++ pad <= GUARDED i; ++ END BLOCK label0; ++ t <= pad; ++ ++ ASSERT ((((vddi and vdde) and not (vssi)) and not (vsse)) = '1') ++ REPORT "power supply is missing on piot_sp" ++ SEVERITY WARNING; ++END; +diff --git a/alliance/src/cells/src/pxlib/po_sp.ap b/alliance/src/cells/src/pxlib/po_sp.ap +new file mode 100644 +index 0000000..914038a +--- /dev/null ++++ b/alliance/src/cells/src/pxlib/po_sp.ap +@@ -0,0 +1,58 @@ ++V ALLIANCE : 6 ++H po_sp,P, 4/ 9/2014,100 ++A 0,0,20000,40000 ++C 10000,40000,100,pad,0,NORTH,ALU1 ++C 14000,0,200,i,0,SOUTH,ALU1 ++C 14000,0,200,i,1,SOUTH,ALU2 ++C 0,8000,1200,vddi,6,WEST,ALU3 ++C 0,6500,1200,vssi,6,WEST,ALU3 ++C 20000,6500,1200,vssi,7,EAST,ALU3 ++C 20000,8000,1200,vddi,7,EAST,ALU3 ++C 0,18500,1200,vsse,6,WEST,ALU3 ++C 0,15500,1200,vsse,4,WEST,ALU3 ++C 0,12500,1200,vsse,2,WEST,ALU3 ++C 0,3500,1200,vssi,4,WEST,ALU3 ++C 0,5000,1200,vddi,4,WEST,ALU3 ++C 0,9500,1200,vsse,0,WEST,ALU3 ++C 0,11000,1200,vdde,0,WEST,ALU3 ++C 0,14000,1200,vdde,2,WEST,ALU3 ++C 0,17000,1200,vdde,4,WEST,ALU3 ++C 20000,18500,1200,vsse,7,EAST,ALU3 ++C 20000,15500,1200,vsse,5,EAST,ALU3 ++C 20000,12500,1200,vsse,3,EAST,ALU3 ++C 20000,9500,1200,vsse,1,EAST,ALU3 ++C 20000,11000,1200,vdde,1,EAST,ALU3 ++C 20000,14000,1200,vdde,3,EAST,ALU3 ++C 20000,17000,1200,vdde,5,EAST,ALU3 ++C 20000,3500,1200,vssi,5,EAST,ALU3 ++C 20000,5000,1200,vddi,5,EAST,ALU3 ++C 0,2000,500,ck,0,WEST,ALU3 ++C 20000,2000,500,ck,1,EAST,ALU3 ++S 10000,30000,10000,40000,100,*,DOWN,ALU1 ++S 19600,18500,20000,18500,1200,*,RIGHT,ALU3 ++S 19600,17000,20000,17000,1200,*,RIGHT,ALU3 ++S 19600,15500,20000,15500,1200,*,RIGHT,ALU3 ++S 19600,14000,20000,14000,1200,*,RIGHT,ALU3 ++S 19600,12500,20000,12500,1200,*,RIGHT,ALU3 ++S 19600,11000,20000,11000,1200,*,RIGHT,ALU3 ++S 19600,9500,20000,9500,1200,*,RIGHT,ALU3 ++S 19600,8000,20000,8000,1200,*,RIGHT,ALU3 ++S 19600,6500,20000,6500,1200,*,RIGHT,ALU3 ++S 19600,5000,20000,5000,1200,*,RIGHT,ALU3 ++S 19600,3500,20000,3500,1200,*,RIGHT,ALU3 ++S 19600,2000,20000,2000,500,*,RIGHT,ALU3 ++S 0,8000,400,8000,1200,*,RIGHT,ALU3 ++S 0,9500,400,9500,1200,*,RIGHT,ALU3 ++S 0,11000,400,11000,1200,*,RIGHT,ALU3 ++S 0,14000,400,14000,1200,*,RIGHT,ALU3 ++S 0,15500,400,15500,1200,*,RIGHT,ALU3 ++S 0,12500,400,12500,1200,*,RIGHT,ALU3 ++S 0,17000,400,17000,1200,*,RIGHT,ALU3 ++S 0,18500,400,18500,1200,*,RIGHT,ALU3 ++S 0,2000,400,2000,500,*,RIGHT,ALU3 ++S 0,3500,400,3500,1200,*,RIGHT,ALU3 ++S 0,5000,400,5000,1200,*,RIGHT,ALU3 ++S 0,6500,400,6500,1200,*,RIGHT,ALU3 ++I 0,0,po_px,a,NOSYM ++V 14000,0,CONT_VIA,* ++EOF +diff --git a/alliance/src/cells/src/pxlib/po_sp.vbe b/alliance/src/cells/src/pxlib/po_sp.vbe +new file mode 100644 +index 0000000..6d9d9d7 +--- /dev/null ++++ b/alliance/src/cells/src/pxlib/po_sp.vbe +@@ -0,0 +1,29 @@ ++ENTITY po_sp IS ++ GENERIC ( ++ CONSTANT area : NATURAL := 80000; ++ CONSTANT cin_i : NATURAL := 191; ++ CONSTANT tpll_i : NATURAL := 2176; ++ CONSTANT rdown_i : NATURAL := 15; ++ CONSTANT tphh_i : NATURAL := 2032; ++ CONSTANT rup_i : NATURAL := 16 ++ ); ++ PORT ( ++ i : in BIT; ++ pad : out BIT; ++ ck : in BIT; ++ vdde : in BIT; ++ vddi : in BIT; ++ vsse : in BIT; ++ vssi : in BIT ++ ); ++END po_sp; ++ ++ARCHITECTURE behaviour_data_flow OF po_sp IS ++ ++BEGIN ++ pad <= i; ++ ++ ASSERT ((((vddi and vdde) and not (vssi)) and not (vsse)) = '1') ++ REPORT "power supply is missing on po_sp" ++ SEVERITY WARNING; ++END; +diff --git a/alliance/src/cells/src/pxlib/pot_sp.ap b/alliance/src/cells/src/pxlib/pot_sp.ap +new file mode 100644 +index 0000000..918c64f +--- /dev/null ++++ b/alliance/src/cells/src/pxlib/pot_sp.ap +@@ -0,0 +1,61 @@ ++V ALLIANCE : 6 ++H pot_sp,P, 4/ 9/2014,100 ++A 0,0,20000,40000 ++C 10000,40000,100,pad,0,NORTH,ALU1 ++C 14000,0,200,i,0,SOUTH,ALU1 ++C 14000,0,200,i,1,SOUTH,ALU2 ++C 0,8000,1200,vddi,6,WEST,ALU3 ++C 0,6500,1200,vssi,6,WEST,ALU3 ++C 20000,6500,1200,vssi,7,EAST,ALU3 ++C 20000,8000,1200,vddi,7,EAST,ALU3 ++C 0,18500,1200,vsse,6,WEST,ALU3 ++C 0,15500,1200,vsse,4,WEST,ALU3 ++C 0,12500,1200,vsse,2,WEST,ALU3 ++C 0,3500,1200,vssi,4,WEST,ALU3 ++C 0,5000,1200,vddi,4,WEST,ALU3 ++C 0,9500,1200,vsse,0,WEST,ALU3 ++C 0,11000,1200,vdde,0,WEST,ALU3 ++C 0,14000,1200,vdde,2,WEST,ALU3 ++C 0,17000,1200,vdde,4,WEST,ALU3 ++C 20000,18500,1200,vsse,7,EAST,ALU3 ++C 20000,15500,1200,vsse,5,EAST,ALU3 ++C 20000,12500,1200,vsse,3,EAST,ALU3 ++C 20000,9500,1200,vsse,1,EAST,ALU3 ++C 20000,11000,1200,vdde,1,EAST,ALU3 ++C 20000,14000,1200,vdde,3,EAST,ALU3 ++C 20000,17000,1200,vdde,5,EAST,ALU3 ++C 20000,3500,1200,vssi,5,EAST,ALU3 ++C 20000,5000,1200,vddi,5,EAST,ALU3 ++C 0,2000,500,ck,0,WEST,ALU3 ++C 20000,2000,500,ck,1,EAST,ALU3 ++C 15000,0,200,b,1,SOUTH,ALU2 ++C 15000,0,200,b,0,SOUTH,ALU1 ++S 10000,30000,10000,40000,100,*,DOWN,ALU1 ++S 19600,18500,20000,18500,1200,*,RIGHT,ALU3 ++S 19600,17000,20000,17000,1200,*,RIGHT,ALU3 ++S 19600,15500,20000,15500,1200,*,RIGHT,ALU3 ++S 19600,14000,20000,14000,1200,*,RIGHT,ALU3 ++S 19600,12500,20000,12500,1200,*,RIGHT,ALU3 ++S 19600,11000,20000,11000,1200,*,RIGHT,ALU3 ++S 19600,9500,20000,9500,1200,*,RIGHT,ALU3 ++S 19600,8000,20000,8000,1200,*,RIGHT,ALU3 ++S 19600,6500,20000,6500,1200,*,RIGHT,ALU3 ++S 19600,5000,20000,5000,1200,*,RIGHT,ALU3 ++S 19600,3500,20000,3500,1200,*,RIGHT,ALU3 ++S 19600,2000,20000,2000,500,*,RIGHT,ALU3 ++S 0,8000,400,8000,1200,*,RIGHT,ALU3 ++S 0,9500,400,9500,1200,*,RIGHT,ALU3 ++S 0,11000,400,11000,1200,*,RIGHT,ALU3 ++S 0,14000,400,14000,1200,*,RIGHT,ALU3 ++S 0,15500,400,15500,1200,*,RIGHT,ALU3 ++S 0,12500,400,12500,1200,*,RIGHT,ALU3 ++S 0,17000,400,17000,1200,*,RIGHT,ALU3 ++S 0,18500,400,18500,1200,*,RIGHT,ALU3 ++S 0,2000,400,2000,500,*,RIGHT,ALU3 ++S 0,3500,400,3500,1200,*,RIGHT,ALU3 ++S 0,5000,400,5000,1200,*,RIGHT,ALU3 ++S 0,6500,400,6500,1200,*,RIGHT,ALU3 ++I 0,0,pot_px,a,NOSYM ++V 14000,0,CONT_VIA,* ++V 15000,0,CONT_VIA,b ++EOF +diff --git a/alliance/src/cells/src/pxlib/pot_sp.vbe b/alliance/src/cells/src/pxlib/pot_sp.vbe +new file mode 100644 +index 0000000..fc54a73 +--- /dev/null ++++ b/alliance/src/cells/src/pxlib/pot_sp.vbe +@@ -0,0 +1,42 @@ ++ENTITY pot_sp IS ++ GENERIC ( ++ CONSTANT area : NATURAL := 80000; ++ CONSTANT rup : NATURAL := 684404; ++ CONSTANT rdown : NATURAL := 24 ++ ); ++ PORT ( ++ i : in BIT; ++ b : in BIT; ++ pad : out MUX_BIT BUS; ++ ck : in BIT; ++ vdde : in BIT; ++ vddi : in BIT; ++ vsse : in BIT; ++ vssi : in BIT ++ ); ++END pot_sp; ++ ++ARCHITECTURE behaviour_data_flow OF pot_sp IS ++ SIGNAL b1 : BIT; ++ SIGNAL b2 : BIT; ++ SIGNAL b3 : BIT; ++ SIGNAL b4 : BIT; ++ SIGNAL b5 : BIT; ++ SIGNAL b6 : BIT; ++ ++BEGIN ++ b6 <= b5; ++ b5 <= b4; ++ b4 <= b3; ++ b3 <= b2; ++ b2 <= b1; ++ b1 <= b; ++ label0 : BLOCK (b6 = '1') ++ BEGIN ++ pad <= GUARDED i; ++ END BLOCK label0; ++ ++ ASSERT ((((vddi and vdde) and not (vssi)) and not (vsse)) = '1') ++ REPORT "power supply is missing on pot_sp" ++ SEVERITY WARNING; ++END; +diff --git a/alliance/src/cells/src/pxlib/pvdde_sp.ap b/alliance/src/cells/src/pxlib/pvdde_sp.ap +new file mode 100644 +index 0000000..e3e5973 +--- /dev/null ++++ b/alliance/src/cells/src/pxlib/pvdde_sp.ap +@@ -0,0 +1,55 @@ ++V ALLIANCE : 6 ++H pvdde_sp,P, 4/ 9/2014,100 ++A 0,0,20000,40000 ++C 10000,40000,100,vdde,6,NORTH,ALU1 ++C 0,8000,1200,vddi,6,WEST,ALU3 ++C 0,6500,1200,vssi,6,WEST,ALU3 ++C 20000,6500,1200,vssi,7,EAST,ALU3 ++C 20000,8000,1200,vddi,7,EAST,ALU3 ++C 0,18500,1200,vsse,6,WEST,ALU3 ++C 0,15500,1200,vsse,4,WEST,ALU3 ++C 0,12500,1200,vsse,2,WEST,ALU3 ++C 0,3500,1200,vssi,4,WEST,ALU3 ++C 0,5000,1200,vddi,4,WEST,ALU3 ++C 0,9500,1200,vsse,0,WEST,ALU3 ++C 0,11000,1200,vdde,0,WEST,ALU3 ++C 0,14000,1200,vdde,2,WEST,ALU3 ++C 0,17000,1200,vdde,4,WEST,ALU3 ++C 20000,18500,1200,vsse,7,EAST,ALU3 ++C 20000,15500,1200,vsse,5,EAST,ALU3 ++C 20000,12500,1200,vsse,3,EAST,ALU3 ++C 20000,9500,1200,vsse,1,EAST,ALU3 ++C 20000,11000,1200,vdde,1,EAST,ALU3 ++C 20000,14000,1200,vdde,3,EAST,ALU3 ++C 20000,17000,1200,vdde,5,EAST,ALU3 ++C 20000,3500,1200,vssi,5,EAST,ALU3 ++C 20000,5000,1200,vddi,5,EAST,ALU3 ++C 0,2000,500,ck,0,WEST,ALU3 ++C 20000,2000,500,ck,1,EAST,ALU3 ++S 10000,30000,10000,40000,100,*,DOWN,ALU1 ++S 19600,18500,20000,18500,1200,*,RIGHT,ALU3 ++S 19600,17000,20000,17000,1200,*,RIGHT,ALU3 ++S 19600,15500,20000,15500,1200,*,RIGHT,ALU3 ++S 19600,14000,20000,14000,1200,*,RIGHT,ALU3 ++S 19600,12500,20000,12500,1200,*,RIGHT,ALU3 ++S 19600,11000,20000,11000,1200,*,RIGHT,ALU3 ++S 19600,9500,20000,9500,1200,*,RIGHT,ALU3 ++S 19600,8000,20000,8000,1200,*,RIGHT,ALU3 ++S 19600,6500,20000,6500,1200,*,RIGHT,ALU3 ++S 19600,5000,20000,5000,1200,*,RIGHT,ALU3 ++S 19600,3500,20000,3500,1200,*,RIGHT,ALU3 ++S 19600,2000,20000,2000,500,*,RIGHT,ALU3 ++S 0,8000,400,8000,1200,*,RIGHT,ALU3 ++S 0,9500,400,9500,1200,*,RIGHT,ALU3 ++S 0,11000,400,11000,1200,*,RIGHT,ALU3 ++S 0,14000,400,14000,1200,*,RIGHT,ALU3 ++S 0,15500,400,15500,1200,*,RIGHT,ALU3 ++S 0,12500,400,12500,1200,*,RIGHT,ALU3 ++S 0,17000,400,17000,1200,*,RIGHT,ALU3 ++S 0,18500,400,18500,1200,*,RIGHT,ALU3 ++S 0,2000,400,2000,500,*,RIGHT,ALU3 ++S 0,3500,400,3500,1200,*,RIGHT,ALU3 ++S 0,5000,400,5000,1200,*,RIGHT,ALU3 ++S 0,6500,400,6500,1200,*,RIGHT,ALU3 ++I 0,0,pvdde_px,a,NOSYM ++EOF +diff --git a/alliance/src/cells/src/pxlib/pvdde_sp.vbe b/alliance/src/cells/src/pxlib/pvdde_sp.vbe +new file mode 100644 +index 0000000..a22d525 +--- /dev/null ++++ b/alliance/src/cells/src/pxlib/pvdde_sp.vbe +@@ -0,0 +1,20 @@ ++ENTITY pvdde_sp IS ++ GENERIC ( ++ CONSTANT area : NATURAL := 80000 ++ ); ++ PORT ( ++ ck : in BIT; ++ vdde : in BIT; ++ vddi : in BIT; ++ vsse : in BIT; ++ vssi : in BIT ++ ); ++END pvdde_sp; ++ ++ARCHITECTURE behaviour_data_flow OF pvdde_sp IS ++ ++BEGIN ++ ASSERT ((((not (vssi) and not (vsse)) and vddi) and vdde) = '1') ++ REPORT "power supply is missing on pvdde_sp" ++ SEVERITY WARNING; ++END; +diff --git a/alliance/src/cells/src/pxlib/pvddeck_px.ap b/alliance/src/cells/src/pxlib/pvddeck_px.ap +index ab2760c..f221151 100644 +--- a/alliance/src/cells/src/pxlib/pvddeck_px.ap ++++ b/alliance/src/cells/src/pxlib/pvddeck_px.ap +@@ -88,8 +88,10 @@ S 4900,5100,6700,5100,300,40onymous_,RIGHT,POLY + S 5500,3000,8500,3000,6000,2nonymous_,RIGHT,TALU2 + S 13000,3700,13000,4100,200,123nymous_,UP,ALU1 + S 4300,4900,4300,5400,100,65onymous_,UP,POLY +-S 9500,0,9500,1000,1200,cko,UP,CALU5 +-S 9500,0,9500,1000,1200,cko,UP,CALU4 ++S 9500,0,9500,1000,1200,cko,UP,ALU5 ++S 9500,0,9500,1000,1200,cko,UP,ALU4 ++S 9500,-450,9500,200,1200,cko,UP,CALU5 ++S 9500,-450,9500,200,1200,cko,UP,CALU4 + S 3500,100,3500,1500,200,22onymous_,UP,TALU5 + S 13600,5600,13600,7000,200,97onymous_,UP,ALU1 + S 14800,5600,14800,7500,300,110nymous_,UP,PDIF +diff --git a/alliance/src/cells/src/pxlib/pvddeck_sp.ap b/alliance/src/cells/src/pxlib/pvddeck_sp.ap +new file mode 100644 +index 0000000..0157fd1 +--- /dev/null ++++ b/alliance/src/cells/src/pxlib/pvddeck_sp.ap +@@ -0,0 +1,59 @@ ++V ALLIANCE : 6 ++H pvddeck_sp,P, 4/ 9/2014,100 ++A 0,0,20000,40000 ++C 20000,2000,500,ck,5,EAST,ALU3 ++C 0,2000,500,ck,4,WEST,ALU3 ++C 20000,5000,1200,vddi,1,EAST,ALU3 ++C 20000,3500,1200,vssi,1,EAST,ALU3 ++C 20000,17000,1200,vdde,5,EAST,ALU3 ++C 20000,14000,1200,vdde,3,EAST,ALU3 ++C 20000,11000,1200,vdde,1,EAST,ALU3 ++C 20000,9500,1200,vsse,1,EAST,ALU3 ++C 20000,12500,1200,vsse,3,EAST,ALU3 ++C 20000,15500,1200,vsse,5,EAST,ALU3 ++C 20000,18500,1200,vsse,7,EAST,ALU3 ++C 0,17000,1200,vdde,4,WEST,ALU3 ++C 0,14000,1200,vdde,2,WEST,ALU3 ++C 0,11000,1200,vdde,0,WEST,ALU3 ++C 0,9500,1200,vsse,0,WEST,ALU3 ++C 0,5000,1200,vddi,0,WEST,ALU3 ++C 0,3500,1200,vssi,0,WEST,ALU3 ++C 0,12500,1200,vsse,2,WEST,ALU3 ++C 0,15500,1200,vsse,4,WEST,ALU3 ++C 0,18500,1200,vsse,6,WEST,ALU3 ++C 20000,8000,1200,vddi,3,EAST,ALU3 ++C 20000,6500,1200,vssi,3,EAST,ALU3 ++C 0,6500,1200,vssi,2,WEST,ALU3 ++C 0,8000,1200,vddi,2,WEST,ALU3 ++C 10000,40000,100,vdde,6,NORTH,ALU1 ++C 9500,0,200,cko,1,SOUTH,ALU2 ++C 9500,0,200,cko,0,SOUTH,ALU1 ++S 5800,700,14200,700,800,cko,RIGHT,ALU2 ++S 0,6500,400,6500,1200,*,RIGHT,ALU3 ++S 0,5000,400,5000,1200,*,RIGHT,ALU3 ++S 0,3500,400,3500,1200,*,RIGHT,ALU3 ++S 0,2000,400,2000,500,*,RIGHT,ALU3 ++S 0,18500,400,18500,1200,*,RIGHT,ALU3 ++S 0,17000,400,17000,1200,*,RIGHT,ALU3 ++S 0,12500,400,12500,1200,*,RIGHT,ALU3 ++S 0,15500,400,15500,1200,*,RIGHT,ALU3 ++S 0,14000,400,14000,1200,*,RIGHT,ALU3 ++S 0,11000,400,11000,1200,*,RIGHT,ALU3 ++S 0,9500,400,9500,1200,*,RIGHT,ALU3 ++S 0,8000,400,8000,1200,*,RIGHT,ALU3 ++S 19600,2000,20000,2000,500,*,RIGHT,ALU3 ++S 19600,3500,20000,3500,1200,*,RIGHT,ALU3 ++S 19600,5000,20000,5000,1200,*,RIGHT,ALU3 ++S 19600,6500,20000,6500,1200,*,RIGHT,ALU3 ++S 19600,8000,20000,8000,1200,*,RIGHT,ALU3 ++S 19600,9500,20000,9500,1200,*,RIGHT,ALU3 ++S 19600,11000,20000,11000,1200,*,RIGHT,ALU3 ++S 19600,12500,20000,12500,1200,*,RIGHT,ALU3 ++S 19600,14000,20000,14000,1200,*,RIGHT,ALU3 ++S 19600,15500,20000,15500,1200,*,RIGHT,ALU3 ++S 19600,17000,20000,17000,1200,*,RIGHT,ALU3 ++S 19600,18500,20000,18500,1200,*,RIGHT,ALU3 ++S 10000,30000,10000,40000,100,*,DOWN,ALU1 ++I 0,0,pvddeck_px,a,NOSYM ++B 9500,500,1200,1200,CONT_VIA,* ++EOF +diff --git a/alliance/src/cells/src/pxlib/pvddeck_sp.vbe b/alliance/src/cells/src/pxlib/pvddeck_sp.vbe +new file mode 100644 +index 0000000..298d1aa +--- /dev/null ++++ b/alliance/src/cells/src/pxlib/pvddeck_sp.vbe +@@ -0,0 +1,31 @@ ++ENTITY pvddeck_sp IS ++ GENERIC ( ++ CONSTANT area : NATURAL := 80000; ++ CONSTANT cin_ck : NATURAL := 127; ++ CONSTANT tpll_ck : NATURAL := 1055; ++ CONSTANT rdown_ck : NATURAL := 126; ++ CONSTANT tphh_ck : NATURAL := 963; ++ CONSTANT rup_ck : NATURAL := 183 ++ ); ++ PORT ( ++ cko : out WOR_BIT BUS; ++ ck : in BIT; ++ vdde : in BIT; ++ vddi : in BIT; ++ vsse : in BIT; ++ vssi : in BIT ++ ); ++END pvddeck_sp; ++ ++ARCHITECTURE behaviour_data_flow OF pvddeck_sp IS ++ ++BEGIN ++ label0 : BLOCK ('1' = '1') ++ BEGIN ++ cko <= GUARDED ck; ++ END BLOCK label0; ++ ++ ASSERT ((((not (vssi) and not (vsse)) and vddi) and vdde) = '1') ++ REPORT "power supply is missing on pvddeck_sp" ++ SEVERITY WARNING; ++END; +diff --git a/alliance/src/cells/src/pxlib/pvddi_sp.ap b/alliance/src/cells/src/pxlib/pvddi_sp.ap +new file mode 100644 +index 0000000..2d1d104 +--- /dev/null ++++ b/alliance/src/cells/src/pxlib/pvddi_sp.ap +@@ -0,0 +1,61 @@ ++V ALLIANCE : 6 ++H pvddi_sp,P, 4/ 9/2014,100 ++A 0,0,20000,40000 ++C 10000,0,5200,vddi,10,SOUTH,ALU2 ++C 10000,0,5200,vddi,8,SOUTH,ALU1 ++S 10000,0,10000,8500,5200,*,UP,ALU2 ++B 10000,1100,5200,2400,CONT_VIA,* ++C 20000,2000,500,ck,1,EAST,ALU3 ++C 0,2000,500,ck,0,WEST,ALU3 ++C 20000,5000,1200,vddi,14,EAST,ALU3 ++C 20000,3500,1200,vssi,1,EAST,ALU3 ++C 20000,17000,1200,vdde,5,EAST,ALU3 ++C 20000,14000,1200,vdde,3,EAST,ALU3 ++C 20000,11000,1200,vdde,1,EAST,ALU3 ++C 20000,9500,1200,vsse,1,EAST,ALU3 ++C 20000,12500,1200,vsse,3,EAST,ALU3 ++C 20000,15500,1200,vsse,5,EAST,ALU3 ++C 20000,18500,1200,vsse,7,EAST,ALU3 ++C 0,17000,1200,vdde,4,WEST,ALU3 ++C 0,14000,1200,vdde,2,WEST,ALU3 ++C 0,11000,1200,vdde,0,WEST,ALU3 ++C 0,9500,1200,vsse,0,WEST,ALU3 ++C 0,5000,1200,vddi,13,WEST,ALU3 ++C 0,3500,1200,vssi,0,WEST,ALU3 ++C 0,12500,1200,vsse,2,WEST,ALU3 ++C 0,15500,1200,vsse,4,WEST,ALU3 ++C 0,18500,1200,vsse,6,WEST,ALU3 ++C 20000,8000,1200,vddi,16,EAST,ALU3 ++C 20000,6500,1200,vssi,3,EAST,ALU3 ++C 0,6500,1200,vssi,2,WEST,ALU3 ++C 0,8000,1200,vddi,15,WEST,ALU3 ++C 10000,40000,100,vddi,17,NORTH,ALU1 ++S 0,6500,400,6500,1200,*,RIGHT,ALU3 ++S 0,5000,400,5000,1200,*,RIGHT,ALU3 ++S 0,3500,400,3500,1200,*,RIGHT,ALU3 ++S 0,2000,400,2000,500,*,RIGHT,ALU3 ++S 0,18500,400,18500,1200,*,RIGHT,ALU3 ++S 0,17000,400,17000,1200,*,RIGHT,ALU3 ++S 0,12500,400,12500,1200,*,RIGHT,ALU3 ++S 0,15500,400,15500,1200,*,RIGHT,ALU3 ++S 0,14000,400,14000,1200,*,RIGHT,ALU3 ++S 0,11000,400,11000,1200,*,RIGHT,ALU3 ++S 0,9500,400,9500,1200,*,RIGHT,ALU3 ++S 0,8000,400,8000,1200,*,RIGHT,ALU3 ++S 19600,2000,20000,2000,500,*,RIGHT,ALU3 ++S 19600,3500,20000,3500,1200,*,RIGHT,ALU3 ++S 19600,5000,20000,5000,1200,*,RIGHT,ALU3 ++S 19600,6500,20000,6500,1200,*,RIGHT,ALU3 ++S 19600,8000,20000,8000,1200,*,RIGHT,ALU3 ++S 19600,9500,20000,9500,1200,*,RIGHT,ALU3 ++S 19600,11000,20000,11000,1200,*,RIGHT,ALU3 ++S 19600,12500,20000,12500,1200,*,RIGHT,ALU3 ++S 19600,14000,20000,14000,1200,*,RIGHT,ALU3 ++S 19600,15500,20000,15500,1200,*,RIGHT,ALU3 ++S 19600,17000,20000,17000,1200,*,RIGHT,ALU3 ++S 19600,18500,20000,18500,1200,*,RIGHT,ALU3 ++S 10000,30000,10000,40000,100,*,DOWN,ALU1 ++S 10000,0,10000,8500,5200,*,UP,ALU2 ++B 10000,1100,5200,2400,CONT_VIA,* ++I 0,0,pvddi_px,a,NOSYM ++EOF +diff --git a/alliance/src/cells/src/pxlib/pvddi_sp.vbe b/alliance/src/cells/src/pxlib/pvddi_sp.vbe +new file mode 100644 +index 0000000..a000348 +--- /dev/null ++++ b/alliance/src/cells/src/pxlib/pvddi_sp.vbe +@@ -0,0 +1,20 @@ ++ENTITY pvddi_sp IS ++ GENERIC ( ++ CONSTANT area : NATURAL := 80000 ++ ); ++ PORT ( ++ ck : in BIT; ++ vdde : in BIT; ++ vddi : in BIT; ++ vsse : in BIT; ++ vssi : in BIT ++ ); ++END pvddi_sp; ++ ++ARCHITECTURE behaviour_data_flow OF pvddi_sp IS ++ ++BEGIN ++ ASSERT ((((vddi and vdde) and not (vssi)) and not (vsse)) = '1') ++ REPORT "power supply is missing on pvddi_sp" ++ SEVERITY WARNING; ++END; +diff --git a/alliance/src/cells/src/pxlib/pvddick_px.ap b/alliance/src/cells/src/pxlib/pvddick_px.ap +index 0cfbd82..e2549ab 100644 +--- a/alliance/src/cells/src/pxlib/pvddick_px.ap ++++ b/alliance/src/cells/src/pxlib/pvddick_px.ap +@@ -91,8 +91,10 @@ S 13900,5400,13900,7700,100,32onymous_,UP,PTRANS + S 18500,3000,20000,3000,6000,121nymous_,RIGHT,TALU4 + S 7000,3700,7000,4100,200,63onymous_,UP,ALU1 + S 14200,6100,14200,7500,200,6nonymous_,UP,ALU1 +-S 9500,0,9500,1000,1200,cko,UP,CALU4 +-S 9500,0,9500,1000,1200,cko,UP,CALU5 ++S 9500,0,9500,1000,1200,cko,UP,ALU4 ++S 9500,0,9500,1000,1200,cko,UP,ALU5 ++S 9500,-450,9500,200,1200,cko,UP,CALU5 ++S 9500,-450,9500,200,1200,cko,UP,CALU4 + S 15400,5600,15400,7500,300,19onymous_,UP,PDIF + S 6400,5600,6400,7000,200,89onymous_,UP,ALU1 + S 5200,4200,5200,4600,200,102nymous_,UP,ALU1 +diff --git a/alliance/src/cells/src/pxlib/pvddick_sp.ap b/alliance/src/cells/src/pxlib/pvddick_sp.ap +new file mode 100644 +index 0000000..65566d0 +--- /dev/null ++++ b/alliance/src/cells/src/pxlib/pvddick_sp.ap +@@ -0,0 +1,70 @@ ++V ALLIANCE : 6 ++H pvddick_sp,P, 5/ 9/2014,100 ++A 0,0,20000,40000 ++C 6500,0,200,cko,4,SOUTH,ALU2 ++C 5500,0,200,cko,0,SOUTH,ALU2 ++C 10000,40000,100,vddi,6,NORTH,ALU1 ++C 0,8000,1200,vddi,4,WEST,ALU3 ++C 0,6500,1200,vssi,2,WEST,ALU3 ++C 20000,6500,1200,vssi,3,EAST,ALU3 ++C 20000,8000,1200,vddi,5,EAST,ALU3 ++C 0,18500,1200,vsse,6,WEST,ALU3 ++C 0,15500,1200,vsse,4,WEST,ALU3 ++C 0,12500,1200,vsse,2,WEST,ALU3 ++C 0,3500,1200,vssi,0,WEST,ALU3 ++C 0,5000,1200,vddi,2,WEST,ALU3 ++C 0,9500,1200,vsse,0,WEST,ALU3 ++C 0,11000,1200,vdde,0,WEST,ALU3 ++C 0,14000,1200,vdde,2,WEST,ALU3 ++C 0,17000,1200,vdde,4,WEST,ALU3 ++C 20000,18500,1200,vsse,7,EAST,ALU3 ++C 20000,15500,1200,vsse,5,EAST,ALU3 ++C 20000,12500,1200,vsse,3,EAST,ALU3 ++C 20000,9500,1200,vsse,1,EAST,ALU3 ++C 20000,11000,1200,vdde,1,EAST,ALU3 ++C 20000,14000,1200,vdde,3,EAST,ALU3 ++C 20000,17000,1200,vdde,5,EAST,ALU3 ++C 20000,3500,1200,vssi,1,EAST,ALU3 ++C 20000,5000,1200,vddi,3,EAST,ALU3 ++C 0,2000,500,ck,0,WEST,ALU3 ++C 20000,2000,500,ck,1,EAST,ALU3 ++C 10000,0,5200,vddi,0,SOUTH,ALU1 ++C 10000,0,5200,vddi,1,SOUTH,ALU2 ++S 6500,0,6500,1000,200,*,DOWN,ALU2 ++S 5500,500,5500,1000,200,*,UP,ALU2 ++S 5500,0,5500,500,200,*,DOWN,ALU2 ++S 5500,1000,5700,1000,200,*,LEFT,ALU3 ++S 5500,500,5700,500,200,*,LEFT,ALU3 ++S 6000,0,6000,1000,1200,cko,DOWN,ALU3 ++S 10000,30000,10000,40000,100,*,DOWN,ALU1 ++S 19600,18500,20000,18500,1200,*,RIGHT,ALU3 ++S 19600,17000,20000,17000,1200,*,RIGHT,ALU3 ++S 19600,15500,20000,15500,1200,*,RIGHT,ALU3 ++S 19600,14000,20000,14000,1200,*,RIGHT,ALU3 ++S 19600,12500,20000,12500,1200,*,RIGHT,ALU3 ++S 19600,11000,20000,11000,1200,*,RIGHT,ALU3 ++S 19600,9500,20000,9500,1200,*,RIGHT,ALU3 ++S 19600,8000,20000,8000,1200,*,RIGHT,ALU3 ++S 19600,6500,20000,6500,1200,*,RIGHT,ALU3 ++S 19600,5000,20000,5000,1200,*,RIGHT,ALU3 ++S 19600,3500,20000,3500,1200,*,RIGHT,ALU3 ++S 19600,2000,20000,2000,500,*,RIGHT,ALU3 ++S 0,8000,400,8000,1200,*,RIGHT,ALU3 ++S 0,9500,400,9500,1200,*,RIGHT,ALU3 ++S 0,11000,400,11000,1200,*,RIGHT,ALU3 ++S 0,14000,400,14000,1200,*,RIGHT,ALU3 ++S 0,15500,400,15500,1200,*,RIGHT,ALU3 ++S 0,12500,400,12500,1200,*,RIGHT,ALU3 ++S 0,17000,400,17000,1200,*,RIGHT,ALU3 ++S 0,18500,400,18500,1200,*,RIGHT,ALU3 ++S 0,2000,400,2000,500,*,RIGHT,ALU3 ++S 0,3500,400,3500,1200,*,RIGHT,ALU3 ++S 0,5000,400,5000,1200,*,RIGHT,ALU3 ++S 0,6500,400,6500,1200,*,RIGHT,ALU3 ++S 5800,1000,14200,1000,200,*,RIGHT,ALU3 ++S 5800,500,14200,500,200,*,RIGHT,ALU3 ++S 10000,0,10000,8500,5200,*,UP,ALU2 ++I 0,0,pvddick_px,a,NOSYM ++B 6000,500,1200,1200,CONT_VIA,* ++B 10000,1100,5200,2400,CONT_VIA,* ++EOF +diff --git a/alliance/src/cells/src/pxlib/pvddick_sp.vbe b/alliance/src/cells/src/pxlib/pvddick_sp.vbe +new file mode 100644 +index 0000000..954ac35 +--- /dev/null ++++ b/alliance/src/cells/src/pxlib/pvddick_sp.vbe +@@ -0,0 +1,31 @@ ++ENTITY pvddick_sp IS ++ GENERIC ( ++ CONSTANT area : NATURAL := 80000; ++ CONSTANT cin_ck : NATURAL := 127; ++ CONSTANT tpll_ck : NATURAL := 1235; ++ CONSTANT rdown_ck : NATURAL := 253; ++ CONSTANT tphh_ck : NATURAL := 1109; ++ CONSTANT rup_ck : NATURAL := 311 ++ ); ++ PORT ( ++ cko : out WOR_BIT BUS; ++ ck : in BIT; ++ vdde : in BIT; ++ vddi : in BIT; ++ vsse : in BIT; ++ vssi : in BIT ++ ); ++END pvddick_sp; ++ ++ARCHITECTURE behaviour_data_flow OF pvddick_sp IS ++ ++BEGIN ++ label0 : BLOCK ('1' = '1') ++ BEGIN ++ cko <= GUARDED ck; ++ END BLOCK label0; ++ ++ ASSERT ((((vddi and vdde) and not (vssi)) and not (vsse)) = '1') ++ REPORT "power supply is missing on pvddick_sp" ++ SEVERITY WARNING; ++END; +diff --git a/alliance/src/cells/src/pxlib/pvsse_sp.ap b/alliance/src/cells/src/pxlib/pvsse_sp.ap +new file mode 100644 +index 0000000..a669894 +--- /dev/null ++++ b/alliance/src/cells/src/pxlib/pvsse_sp.ap +@@ -0,0 +1,55 @@ ++V ALLIANCE : 6 ++H pvsse_sp,P, 4/ 9/2014,100 ++A 0,0,20000,40000 ++C 10000,40000,100,vsse,8,NORTH,ALU1 ++C 0,8000,1200,vddi,6,WEST,ALU3 ++C 0,6500,1200,vssi,6,WEST,ALU3 ++C 20000,6500,1200,vssi,7,EAST,ALU3 ++C 20000,8000,1200,vddi,7,EAST,ALU3 ++C 0,18500,1200,vsse,6,WEST,ALU3 ++C 0,15500,1200,vsse,4,WEST,ALU3 ++C 0,12500,1200,vsse,2,WEST,ALU3 ++C 0,3500,1200,vssi,4,WEST,ALU3 ++C 0,5000,1200,vddi,4,WEST,ALU3 ++C 0,9500,1200,vsse,0,WEST,ALU3 ++C 0,11000,1200,vdde,0,WEST,ALU3 ++C 0,14000,1200,vdde,2,WEST,ALU3 ++C 0,17000,1200,vdde,4,WEST,ALU3 ++C 20000,18500,1200,vsse,7,EAST,ALU3 ++C 20000,15500,1200,vsse,5,EAST,ALU3 ++C 20000,12500,1200,vsse,3,EAST,ALU3 ++C 20000,9500,1200,vsse,1,EAST,ALU3 ++C 20000,11000,1200,vdde,1,EAST,ALU3 ++C 20000,14000,1200,vdde,3,EAST,ALU3 ++C 20000,17000,1200,vdde,5,EAST,ALU3 ++C 20000,3500,1200,vssi,5,EAST,ALU3 ++C 20000,5000,1200,vddi,5,EAST,ALU3 ++C 0,2000,500,ck,0,WEST,ALU3 ++C 20000,2000,500,ck,1,EAST,ALU3 ++S 10000,30000,10000,40000,100,*,DOWN,ALU1 ++S 19600,18500,20000,18500,1200,*,RIGHT,ALU3 ++S 19600,17000,20000,17000,1200,*,RIGHT,ALU3 ++S 19600,15500,20000,15500,1200,*,RIGHT,ALU3 ++S 19600,14000,20000,14000,1200,*,RIGHT,ALU3 ++S 19600,12500,20000,12500,1200,*,RIGHT,ALU3 ++S 19600,11000,20000,11000,1200,*,RIGHT,ALU3 ++S 19600,9500,20000,9500,1200,*,RIGHT,ALU3 ++S 19600,8000,20000,8000,1200,*,RIGHT,ALU3 ++S 19600,6500,20000,6500,1200,*,RIGHT,ALU3 ++S 19600,5000,20000,5000,1200,*,RIGHT,ALU3 ++S 19600,3500,20000,3500,1200,*,RIGHT,ALU3 ++S 19600,2000,20000,2000,500,*,RIGHT,ALU3 ++S 0,8000,400,8000,1200,*,RIGHT,ALU3 ++S 0,9500,400,9500,1200,*,RIGHT,ALU3 ++S 0,11000,400,11000,1200,*,RIGHT,ALU3 ++S 0,14000,400,14000,1200,*,RIGHT,ALU3 ++S 0,15500,400,15500,1200,*,RIGHT,ALU3 ++S 0,12500,400,12500,1200,*,RIGHT,ALU3 ++S 0,17000,400,17000,1200,*,RIGHT,ALU3 ++S 0,18500,400,18500,1200,*,RIGHT,ALU3 ++S 0,2000,400,2000,500,*,RIGHT,ALU3 ++S 0,3500,400,3500,1200,*,RIGHT,ALU3 ++S 0,5000,400,5000,1200,*,RIGHT,ALU3 ++S 0,6500,400,6500,1200,*,RIGHT,ALU3 ++I 0,0,pvsse_px,a,NOSYM ++EOF +diff --git a/alliance/src/cells/src/pxlib/pvsse_sp.vbe b/alliance/src/cells/src/pxlib/pvsse_sp.vbe +new file mode 100644 +index 0000000..b6445e9 +--- /dev/null ++++ b/alliance/src/cells/src/pxlib/pvsse_sp.vbe +@@ -0,0 +1,20 @@ ++ENTITY pvsse_sp IS ++ GENERIC ( ++ CONSTANT area : NATURAL := 80000 ++ ); ++ PORT ( ++ ck : in BIT; ++ vdde : in BIT; ++ vddi : in BIT; ++ vsse : in BIT; ++ vssi : in BIT ++ ); ++END pvsse_sp; ++ ++ARCHITECTURE behaviour_data_flow OF pvsse_sp IS ++ ++BEGIN ++ ASSERT ((((vddi and vdde) and not (vssi)) and not (vsse)) = '1') ++ REPORT "power supply is missing on pvsse_sp" ++ SEVERITY WARNING; ++END; +diff --git a/alliance/src/cells/src/pxlib/pvsseck_px.ap b/alliance/src/cells/src/pxlib/pvsseck_px.ap +index 85af7b6..40f1818 100644 +--- a/alliance/src/cells/src/pxlib/pvsseck_px.ap ++++ b/alliance/src/cells/src/pxlib/pvsseck_px.ap +@@ -90,8 +90,10 @@ S 4300,4900,4300,5400,100,40onymous_,UP,POLY + S 5800,5600,5800,7500,300,27onymous_,UP,PDIF + S 13900,5400,13900,7700,100,77onymous_,UP,PTRANS + S 6700,4900,6700,5400,100,14onymous_,UP,POLY +-S 9500,0,9500,1000,1200,cko,UP,CALU5 +-S 9500,0,9500,1000,1200,cko,UP,CALU4 ++S 9500,0,9500,1000,1200,cko,UP,ALU5 ++S 9500,0,9500,1000,1200,cko,UP,ALU4 ++S 9500,-450,9500,200,1200,cko,UP,CALU5 ++S 9500,-450,9500,200,1200,cko,UP,CALU4 + S 15400,3700,15400,4600,200,97onymous_,UP,ALU1 + S 13600,5100,16000,5100,200,71onymous_,RIGHT,ALU1 + S 5800,500,5800,5600,200,52onymous_,UP,ALU2 +diff --git a/alliance/src/cells/src/pxlib/pvsseck_sp.ap b/alliance/src/cells/src/pxlib/pvsseck_sp.ap +new file mode 100644 +index 0000000..0bc0abb +--- /dev/null ++++ b/alliance/src/cells/src/pxlib/pvsseck_sp.ap +@@ -0,0 +1,59 @@ ++V ALLIANCE : 6 ++H pvsseck_sp,P, 4/ 9/2014,100 ++A 0,0,20000,40000 ++C 10000,40000,100,vsse,8,NORTH,ALU1 ++C 0,8000,1200,vddi,6,WEST,ALU3 ++C 0,6500,1200,vssi,6,WEST,ALU3 ++C 20000,6500,1200,vssi,7,EAST,ALU3 ++C 20000,8000,1200,vddi,7,EAST,ALU3 ++C 0,18500,1200,vsse,6,WEST,ALU3 ++C 0,15500,1200,vsse,4,WEST,ALU3 ++C 0,12500,1200,vsse,2,WEST,ALU3 ++C 0,3500,1200,vssi,4,WEST,ALU3 ++C 0,5000,1200,vddi,4,WEST,ALU3 ++C 0,9500,1200,vsse,0,WEST,ALU3 ++C 0,11000,1200,vdde,0,WEST,ALU3 ++C 0,14000,1200,vdde,2,WEST,ALU3 ++C 0,17000,1200,vdde,4,WEST,ALU3 ++C 20000,18500,1200,vsse,7,EAST,ALU3 ++C 20000,15500,1200,vsse,5,EAST,ALU3 ++C 20000,12500,1200,vsse,3,EAST,ALU3 ++C 20000,9500,1200,vsse,1,EAST,ALU3 ++C 20000,11000,1200,vdde,1,EAST,ALU3 ++C 20000,14000,1200,vdde,3,EAST,ALU3 ++C 20000,17000,1200,vdde,5,EAST,ALU3 ++C 20000,3500,1200,vssi,5,EAST,ALU3 ++C 20000,5000,1200,vddi,5,EAST,ALU3 ++C 0,2000,500,ck,2,WEST,ALU3 ++C 20000,2000,500,ck,3,EAST,ALU3 ++C 9500,0,200,cko,1,SOUTH,ALU2 ++C 9500,0,200,cko,0,SOUTH,ALU1 ++S 10000,30000,10000,40000,100,*,DOWN,ALU1 ++S 19600,18500,20000,18500,1200,*,RIGHT,ALU3 ++S 19600,17000,20000,17000,1200,*,RIGHT,ALU3 ++S 19600,15500,20000,15500,1200,*,RIGHT,ALU3 ++S 19600,14000,20000,14000,1200,*,RIGHT,ALU3 ++S 19600,12500,20000,12500,1200,*,RIGHT,ALU3 ++S 19600,11000,20000,11000,1200,*,RIGHT,ALU3 ++S 19600,9500,20000,9500,1200,*,RIGHT,ALU3 ++S 19600,8000,20000,8000,1200,*,RIGHT,ALU3 ++S 19600,6500,20000,6500,1200,*,RIGHT,ALU3 ++S 19600,5000,20000,5000,1200,*,RIGHT,ALU3 ++S 19600,3500,20000,3500,1200,*,RIGHT,ALU3 ++S 19600,2000,20000,2000,500,*,RIGHT,ALU3 ++S 0,8000,400,8000,1200,*,RIGHT,ALU3 ++S 0,9500,400,9500,1200,*,RIGHT,ALU3 ++S 0,11000,400,11000,1200,*,RIGHT,ALU3 ++S 0,14000,400,14000,1200,*,RIGHT,ALU3 ++S 0,15500,400,15500,1200,*,RIGHT,ALU3 ++S 0,12500,400,12500,1200,*,RIGHT,ALU3 ++S 0,17000,400,17000,1200,*,RIGHT,ALU3 ++S 0,18500,400,18500,1200,*,RIGHT,ALU3 ++S 0,2000,400,2000,500,*,RIGHT,ALU3 ++S 0,3500,400,3500,1200,*,RIGHT,ALU3 ++S 0,5000,400,5000,1200,*,RIGHT,ALU3 ++S 0,6500,400,6500,1200,*,RIGHT,ALU3 ++S 5800,700,14200,700,800,cko,RIGHT,ALU2 ++I 0,0,pvsseck_px,a,NOSYM ++B 9500,500,1200,1200,CONT_VIA,* ++EOF +diff --git a/alliance/src/cells/src/pxlib/pvsseck_sp.vbe b/alliance/src/cells/src/pxlib/pvsseck_sp.vbe +new file mode 100644 +index 0000000..c044150 +--- /dev/null ++++ b/alliance/src/cells/src/pxlib/pvsseck_sp.vbe +@@ -0,0 +1,31 @@ ++ENTITY pvsseck_sp IS ++ GENERIC ( ++ CONSTANT area : NATURAL := 80000; ++ CONSTANT cin_ck : NATURAL := 127; ++ CONSTANT tpll_ck : NATURAL := 1055; ++ CONSTANT rdown_ck : NATURAL := 126; ++ CONSTANT tphh_ck : NATURAL := 963; ++ CONSTANT rup_ck : NATURAL := 183 ++ ); ++ PORT ( ++ cko : out WOR_BIT BUS; ++ ck : in BIT; ++ vdde : in BIT; ++ vddi : in BIT; ++ vsse : in BIT; ++ vssi : in BIT ++ ); ++END pvsseck_sp; ++ ++ARCHITECTURE behaviour_data_flow OF pvsseck_sp IS ++ ++BEGIN ++ label0 : BLOCK ('1' = '1') ++ BEGIN ++ cko <= GUARDED ck; ++ END BLOCK label0; ++ ++ ASSERT ((((vddi and vdde) and not (vssi)) and not (vsse)) = '1') ++ REPORT "power supply is missing on pvsseck_sp" ++ SEVERITY WARNING; ++END; +diff --git a/alliance/src/cells/src/pxlib/pvssi_sp.ap b/alliance/src/cells/src/pxlib/pvssi_sp.ap +new file mode 100644 +index 0000000..ba2b620 +--- /dev/null ++++ b/alliance/src/cells/src/pxlib/pvssi_sp.ap +@@ -0,0 +1,59 @@ ++V ALLIANCE : 6 ++H pvssi_sp,P, 4/ 9/2014,100 ++A 0,0,20000,40000 ++C 10000,0,5200,vssi,10,SOUTH,ALU2 ++C 10000,0,5200,vssi,8,SOUTH,ALU1 ++C 20000,2000,500,ck,1,EAST,ALU3 ++C 0,2000,500,ck,0,WEST,ALU3 ++C 20000,5000,1200,vddi,1,EAST,ALU3 ++C 20000,3500,1200,vssi,5,EAST,ALU3 ++C 20000,17000,1200,vdde,5,EAST,ALU3 ++C 20000,14000,1200,vdde,3,EAST,ALU3 ++C 20000,11000,1200,vdde,1,EAST,ALU3 ++C 20000,9500,1200,vsse,1,EAST,ALU3 ++C 20000,12500,1200,vsse,3,EAST,ALU3 ++C 20000,15500,1200,vsse,5,EAST,ALU3 ++C 20000,18500,1200,vsse,7,EAST,ALU3 ++C 0,17000,1200,vdde,4,WEST,ALU3 ++C 0,14000,1200,vdde,2,WEST,ALU3 ++C 0,11000,1200,vdde,0,WEST,ALU3 ++C 0,9500,1200,vsse,0,WEST,ALU3 ++C 0,5000,1200,vddi,0,WEST,ALU3 ++C 0,3500,1200,vssi,4,WEST,ALU3 ++C 0,12500,1200,vsse,2,WEST,ALU3 ++C 0,15500,1200,vsse,4,WEST,ALU3 ++C 0,18500,1200,vsse,6,WEST,ALU3 ++C 20000,8000,1200,vddi,3,EAST,ALU3 ++C 20000,6500,1200,vssi,7,EAST,ALU3 ++C 0,6500,1200,vssi,6,WEST,ALU3 ++C 0,8000,1200,vddi,2,WEST,ALU3 ++C 10000,40000,100,vssi,8,NORTH,ALU1 ++S 0,6500,400,6500,1200,*,RIGHT,ALU3 ++S 0,5000,400,5000,1200,*,RIGHT,ALU3 ++S 0,3500,400,3500,1200,*,RIGHT,ALU3 ++S 0,2000,400,2000,500,*,RIGHT,ALU3 ++S 0,18500,400,18500,1200,*,RIGHT,ALU3 ++S 0,17000,400,17000,1200,*,RIGHT,ALU3 ++S 0,12500,400,12500,1200,*,RIGHT,ALU3 ++S 0,15500,400,15500,1200,*,RIGHT,ALU3 ++S 0,14000,400,14000,1200,*,RIGHT,ALU3 ++S 0,11000,400,11000,1200,*,RIGHT,ALU3 ++S 0,9500,400,9500,1200,*,RIGHT,ALU3 ++S 0,8000,400,8000,1200,*,RIGHT,ALU3 ++S 19600,2000,20000,2000,500,*,RIGHT,ALU3 ++S 19600,3500,20000,3500,1200,*,RIGHT,ALU3 ++S 19600,5000,20000,5000,1200,*,RIGHT,ALU3 ++S 19600,6500,20000,6500,1200,*,RIGHT,ALU3 ++S 19600,8000,20000,8000,1200,*,RIGHT,ALU3 ++S 19600,9500,20000,9500,1200,*,RIGHT,ALU3 ++S 19600,11000,20000,11000,1200,*,RIGHT,ALU3 ++S 19600,12500,20000,12500,1200,*,RIGHT,ALU3 ++S 19600,14000,20000,14000,1200,*,RIGHT,ALU3 ++S 19600,15500,20000,15500,1200,*,RIGHT,ALU3 ++S 19600,17000,20000,17000,1200,*,RIGHT,ALU3 ++S 19600,18500,20000,18500,1200,*,RIGHT,ALU3 ++S 10000,30000,10000,40000,100,*,DOWN,ALU1 ++I 0,0,pvssi_px,a,NOSYM ++B 10000,1100,5200,2400,CONT_VIA,* ++S 10000,0,10000,8500,5200,*,UP,ALU2 ++EOF +diff --git a/alliance/src/cells/src/pxlib/pvssi_sp.vbe b/alliance/src/cells/src/pxlib/pvssi_sp.vbe +new file mode 100644 +index 0000000..17bed49 +--- /dev/null ++++ b/alliance/src/cells/src/pxlib/pvssi_sp.vbe +@@ -0,0 +1,20 @@ ++ENTITY pvssi_sp IS ++ GENERIC ( ++ CONSTANT area : NATURAL := 80000 ++ ); ++ PORT ( ++ ck : in BIT; ++ vdde : in BIT; ++ vddi : in BIT; ++ vsse : in BIT; ++ vssi : in BIT ++ ); ++END pvssi_sp; ++ ++ARCHITECTURE behaviour_data_flow OF pvssi_sp IS ++ ++BEGIN ++ ASSERT ((((vddi and vdde) and not (vssi)) and not (vsse)) = '1') ++ REPORT "power supply is missing on pvssi_sp" ++ SEVERITY WARNING; ++END; +diff --git a/alliance/src/cells/src/pxlib/pvssick_px.ap b/alliance/src/cells/src/pxlib/pvssick_px.ap +index f8d408d..ed19770 100644 +--- a/alliance/src/cells/src/pxlib/pvssick_px.ap ++++ b/alliance/src/cells/src/pxlib/pvssick_px.ap +@@ -90,8 +90,10 @@ S 14200,6100,14200,7500,200,8nonymous_,UP,ALU1 + S 15400,5600,15400,7500,300,21onymous_,UP,PDIF + S 4600,5600,4600,7500,300,71onymous_,UP,PDIF + S 14800,4200,14800,4600,200,52onymous_,UP,ALU1 +-S 9500,0,9500,1000,1200,cko,UP,CALU4 +-S 9500,0,9500,1000,1200,cko,UP,CALU5 ++S 9500,0,9500,1000,1200,cko,UP,ALU4 ++S 9500,0,9500,1000,1200,cko,UP,ALU5 ++S 9500,-450,9500,200,1200,cko,UP,CALU5 ++S 9500,-450,9500,200,1200,cko,UP,CALU4 + S 7000,5600,7000,7500,300,97onymous_,UP,PDIF + S 16500,3000,16500,3000,6000,128nymous_,RIGHT,TALU2 + S 5800,6100,5800,7500,200,58onymous_,UP,ALU1 +diff --git a/alliance/src/cells/src/pxlib/pvssick_sp.ap b/alliance/src/cells/src/pxlib/pvssick_sp.ap +new file mode 100644 +index 0000000..ab70336 +--- /dev/null ++++ b/alliance/src/cells/src/pxlib/pvssick_sp.ap +@@ -0,0 +1,73 @@ ++V ALLIANCE : 6 ++H pvssick_sp,P,10/ 9/2014,100 ++A 0,0,20000,40000 ++C 6400,0,100,cko,3,SOUTH,ALU1 ++C 6400,0,200,cko,4,SOUTH,ALU2 ++C 20000,2000,500,ck,1,EAST,ALU3 ++C 0,2000,500,ck,0,WEST,ALU3 ++C 20000,5000,1200,vddi,1,EAST,ALU3 ++C 20000,3500,1200,vssi,3,EAST,ALU3 ++C 20000,17000,1200,vdde,5,EAST,ALU3 ++C 20000,14000,1200,vdde,3,EAST,ALU3 ++C 20000,11000,1200,vdde,1,EAST,ALU3 ++C 20000,9500,1200,vsse,1,EAST,ALU3 ++C 20000,12500,1200,vsse,3,EAST,ALU3 ++C 20000,15500,1200,vsse,5,EAST,ALU3 ++C 20000,18500,1200,vsse,7,EAST,ALU3 ++C 0,17000,1200,vdde,4,WEST,ALU3 ++C 0,14000,1200,vdde,2,WEST,ALU3 ++C 0,11000,1200,vdde,0,WEST,ALU3 ++C 0,9500,1200,vsse,0,WEST,ALU3 ++C 0,5000,1200,vddi,0,WEST,ALU3 ++C 0,3500,1200,vssi,2,WEST,ALU3 ++C 0,12500,1200,vsse,2,WEST,ALU3 ++C 0,15500,1200,vsse,4,WEST,ALU3 ++C 0,18500,1200,vsse,6,WEST,ALU3 ++C 20000,8000,1200,vddi,3,EAST,ALU3 ++C 20000,6500,1200,vssi,5,EAST,ALU3 ++C 0,6500,1200,vssi,4,WEST,ALU3 ++C 0,8000,1200,vddi,2,WEST,ALU3 ++C 10000,40000,100,vssi,6,NORTH,ALU1 ++C 10000,0,5200,vssi,0,SOUTH,ALU1 ++C 10000,0,5200,vssi,1,SOUTH,ALU2 ++C 5800,0,200,cko,2,SOUTH,ALU2 ++C 5800,0,200,cko,0,SOUTH,ALU1 ++C 5800,0,100,cko,1,SOUTH,ALU1 ++S 6400,0,6400,1000,200,*,UP,ALU2 ++S 5800,500,14200,500,200,*,RIGHT,ALU3 ++S 5800,1000,14200,1000,200,*,RIGHT,ALU3 ++S 0,6500,400,6500,1200,*,RIGHT,ALU3 ++S 0,5000,400,5000,1200,*,RIGHT,ALU3 ++S 0,3500,400,3500,1200,*,RIGHT,ALU3 ++S 0,2000,400,2000,500,*,RIGHT,ALU3 ++S 0,18500,400,18500,1200,*,RIGHT,ALU3 ++S 0,17000,400,17000,1200,*,RIGHT,ALU3 ++S 0,12500,400,12500,1200,*,RIGHT,ALU3 ++S 0,15500,400,15500,1200,*,RIGHT,ALU3 ++S 0,14000,400,14000,1200,*,RIGHT,ALU3 ++S 0,11000,400,11000,1200,*,RIGHT,ALU3 ++S 0,9500,400,9500,1200,*,RIGHT,ALU3 ++S 0,8000,400,8000,1200,*,RIGHT,ALU3 ++S 19600,2000,20000,2000,500,*,RIGHT,ALU3 ++S 19600,3500,20000,3500,1200,*,RIGHT,ALU3 ++S 19600,5000,20000,5000,1200,*,RIGHT,ALU3 ++S 19600,6500,20000,6500,1200,*,RIGHT,ALU3 ++S 19600,8000,20000,8000,1200,*,RIGHT,ALU3 ++S 19600,9500,20000,9500,1200,*,RIGHT,ALU3 ++S 19600,11000,20000,11000,1200,*,RIGHT,ALU3 ++S 19600,12500,20000,12500,1200,*,RIGHT,ALU3 ++S 19600,14000,20000,14000,1200,*,RIGHT,ALU3 ++S 19600,15500,20000,15500,1200,*,RIGHT,ALU3 ++S 19600,17000,20000,17000,1200,*,RIGHT,ALU3 ++S 19600,18500,20000,18500,1200,*,RIGHT,ALU3 ++S 10000,30000,10000,40000,100,*,DOWN,ALU1 ++S 10000,0,10000,8500,5200,*,UP,ALU2 ++S 6000,0,6000,1000,1200,cko,DOWN,ALU3 ++S 5800,0,5800,1000,200,*,UP,ALU2 ++I 0,0,pvssick_px,a,NOSYM ++V 6400,0,CONT_VIA,* ++B 10000,1100,5200,2400,CONT_VIA,* ++V 5800,500,CONT_VIA2,* ++V 5800,1000,CONT_VIA2,* ++V 5800,0,CONT_VIA,* ++EOF +diff --git a/alliance/src/cells/src/pxlib/pvssick_sp.vbe b/alliance/src/cells/src/pxlib/pvssick_sp.vbe +new file mode 100644 +index 0000000..569407c +--- /dev/null ++++ b/alliance/src/cells/src/pxlib/pvssick_sp.vbe +@@ -0,0 +1,32 @@ ++ENTITY pvssick_sp IS ++ GENERIC ( ++ CONSTANT area : NATURAL := 80000; ++ CONSTANT cin_ck : NATURAL := 127; ++ CONSTANT tpll_ck : NATURAL := 1235; ++ CONSTANT rdown_ck : NATURAL := 253; ++ CONSTANT tphh_ck : NATURAL := 1109; ++ CONSTANT rup_ck : NATURAL := 311 ++ ); ++ PORT ( ++ cko : out WOR_BIT BUS; ++ ck : in BIT; ++ vdde : in BIT; ++ vddi : in BIT; ++ vsse : in BIT; ++ vssi : in BIT ++ ); ++END pvssick_sp; ++ ++ARCHITECTURE behaviour_data_flow OF pvssick_sp IS ++ ++BEGIN ++ ++ label0 : BLOCK ('1' = '1') ++ BEGIN ++ cko <= GUARDED ck; ++ END BLOCK label0; ++ ++ ASSERT ((((vddi and vdde) and not (vssi)) and not (vsse)) = '1') ++ REPORT "power supply is missing on pvssick_sp" ++ SEVERITY WARNING; ++END; +diff --git a/alliance/src/distrib/etc/alc_env.csh.in b/alliance/src/distrib/etc/alc_env.csh.in +index 18a1802..cea6941 100644 +--- a/alliance/src/distrib/etc/alc_env.csh.in ++++ b/alliance/src/distrib/etc/alc_env.csh.in +@@ -53,7 +53,7 @@ + setenv MBK_CATA_LIB "${MBK_CATA_LIB}:${CELLS_TOP}/romlib" + setenv MBK_CATA_LIB "${MBK_CATA_LIB}:${CELLS_TOP}/ramlib" + setenv MBK_CATA_LIB "${MBK_CATA_LIB}:${CELLS_TOP}/pxlib" +- setenv MBK_CATA_LIB "${MBK_CATA_LIB}:${CELLS_TOP}/padlib" ++#setenv MBK_CATA_LIB "${MBK_CATA_LIB}:${CELLS_TOP}/padlib" + setenv MBK_TARGET_LIB "${CELLS_TOP}/sxlib" + setenv MBK_C4_LIB ./cellsC4 + +@@ -93,9 +93,9 @@ + endif + + if ( $?MANPATH ) then +- setenv MANPATH "${MANPATH}:${ALLIANCE_TOP}/man" ++ setenv MANPATH "${MANPATH}:${ALLIANCE_TOP}/share/man" + else +- setenv MANPATH ":${ALLIANCE_TOP}/man:`manpath`" ++ setenv MANPATH ":${ALLIANCE_TOP}/share/man:`manpath`" + endif + endif + +diff --git a/alliance/src/distrib/etc/alc_env.sh.in b/alliance/src/distrib/etc/alc_env.sh.in +index ee283b7..a4115f2 100644 +--- a/alliance/src/distrib/etc/alc_env.sh.in ++++ b/alliance/src/distrib/etc/alc_env.sh.in +@@ -55,7 +55,7 @@ + MBK_CATA_LIB=$MBK_CATA_LIB:$CELLS_TOP/ramlib + MBK_CATA_LIB=$MBK_CATA_LIB:$CELLS_TOP/romlib + MBK_CATA_LIB=$MBK_CATA_LIB:$CELLS_TOP/pxlib +- MBK_CATA_LIB=$MBK_CATA_LIB:$CELLS_TOP/padlib ++ #MBK_CATA_LIB=$MBK_CATA_LIB:$CELLS_TOP/padlib + export MBK_CATA_LIB + + MBK_TARGET_LIB=$CELLS_TOP/sxlib; export MBK_TARGET_LIB +@@ -92,9 +92,9 @@ + #fi + + if [ -z "${MANPATH}" ]; then +- MANPATH=:$ALLIANCE_TOP/man:$(manpath) ++ MANPATH=:$ALLIANCE_TOP/share/man:$(manpath) + else +- MANPATH=$MANPATH:$ALLIANCE_TOP/man ++ MANPATH=$MANPATH:$ALLIANCE_TOP/share/man + fi + export MANPATH + fi +diff --git a/alliance/src/documentation/alliance-examples/etc/techno-035.rds b/alliance/src/documentation/alliance-examples/etc/techno-035.rds +index 8c78141..746fd27 100644 +--- a/alliance/src/documentation/alliance-examples/etc/techno-035.rds ++++ b/alliance/src/documentation/alliance-examples/etc/techno-035.rds +@@ -415,3 +415,37 @@ CONT_TURN3 RDS_ALU8 .0 ALL + + END + ++##------------------------------------------------------------------- ++# TABLE MBK_WIRESETTING : ++##------------------------------------------------------------------- ++# ++# This table is used by ocp, nero & ring. It supplies *symbolic* ++# information about the routing grid, the cell gauge and the power ++# wires. ++ ++TABLE MBK_WIRESETTING ++ ++ X_GRID 5 ++ Y_GRID 5 ++ Y_SLICE 50 ++ WIDTH_VDD 6 ++ WIDTH_VSS 6 ++ TRACK_WIDTH_ALU8 0 ++ TRACK_WIDTH_ALU7 2 ++ TRACK_WIDTH_ALU6 2 ++ TRACK_WIDTH_ALU5 2 ++ TRACK_WIDTH_ALU4 2 ++ TRACK_WIDTH_ALU3 2 ++ TRACK_WIDTH_ALU2 2 ++ TRACK_WIDTH_ALU1 2 ++ TRACK_SPACING_ALU8 0 ++ TRACK_SPACING_ALU7 8 ++ TRACK_SPACING_ALU6 8 ++ TRACK_SPACING_ALU5 3 ++ TRACK_SPACING_ALU4 3 ++ TRACK_SPACING_ALU3 3 ++ TRACK_SPACING_ALU2 3 ++ TRACK_SPACING_ALU1 3 ++ ++END ++ +diff --git a/alliance/src/documentation/alliance-examples/etc/techno-symb.rds b/alliance/src/documentation/alliance-examples/etc/techno-symb.rds +index 38bb0ce..2d890b8 100644 +--- a/alliance/src/documentation/alliance-examples/etc/techno-symb.rds ++++ b/alliance/src/documentation/alliance-examples/etc/techno-symb.rds +@@ -422,6 +422,40 @@ TABLE S2R_MINIMUM_LAYER_WIDTH + END + + ##------------------------------------------------------------------- ++# TABLE MBK_WIRESETTING : ++##------------------------------------------------------------------- ++# ++# This table is used by ocp, nero & ring. It supplies *symbolic* ++# information about the routing grid, the cell gauge and the power ++# wires. ++ ++TABLE MBK_WIRESETTING ++ ++ X_GRID 5 ++ Y_GRID 5 ++ Y_SLICE 50 ++ WIDTH_VDD 6 ++ WIDTH_VSS 6 ++ TRACK_WIDTH_ALU8 0 ++ TRACK_WIDTH_ALU7 2 ++ TRACK_WIDTH_ALU6 2 ++ TRACK_WIDTH_ALU5 2 ++ TRACK_WIDTH_ALU4 2 ++ TRACK_WIDTH_ALU3 2 ++ TRACK_WIDTH_ALU2 2 ++ TRACK_WIDTH_ALU1 2 ++ TRACK_SPACING_ALU8 0 ++ TRACK_SPACING_ALU7 8 ++ TRACK_SPACING_ALU6 8 ++ TRACK_SPACING_ALU5 3 ++ TRACK_SPACING_ALU4 3 ++ TRACK_SPACING_ALU3 3 ++ TRACK_SPACING_ALU2 3 ++ TRACK_SPACING_ALU1 3 ++ ++END ++ ++##------------------------------------------------------------------- + # TABLE CIF_LAYER : + ##------------------------------------------------------------------- + +diff --git a/alliance/src/genlib/man3/GENLIB_GET_REF_X.3 b/alliance/src/genlib/man3/GENLIB_GET_REF_X.3 +index e274b98..e64064e 100644 +--- a/alliance/src/genlib/man3/GENLIB_GET_REF_X.3 ++++ b/alliance/src/genlib/man3/GENLIB_GET_REF_X.3 +@@ -27,7 +27,7 @@ Name of the instance in the which the reference is to be searched for + .TP + \fIrefname\fP + Name of the reference +-SH DESCRIPTION ++.SH DESCRIPTION + \fBGET_REF_X\fP looks for + the reference, \fIrefname\fP, in the instance called \fIinsname\fP. + .SH RETURN VALUE +diff --git a/alliance/src/mbk/src/alc_pars_p.c b/alliance/src/mbk/src/alc_pars_p.c +index f65c6cb..a5212b7 100644 +--- a/alliance/src/mbk/src/alc_pars_p.c ++++ b/alliance/src/mbk/src/alc_pars_p.c +@@ -63,28 +63,28 @@ + #define MAXLBUFFER 256 + #define MAXLBUFF 256 + +-#define EVAL -2 +-#define EVER -3 +-#define EOPEN -4 +-#define ECLOSE -5 +-#define ESETUP -6 +-#define ELAYER -7 +-#define EOPGEO -8 +-#define ESYNTAX -9 +-#define EORIENT -10 +-#define EHEADER -11 +-#define EMISSEOF -12 +-#define ETYPESEG -13 +-#define ETYPEVIA -14 +-#define ENAMETRS -15 +-#define ENBFIELDS -16 +-#define EFILENAME -17 +-#define EFILETYPE -18 +-#define EBOUNDBOX -19 +-#define EABUTMBOX -20 +-#define EALLOCFIG -21 +-#define ECOMPONENT -22 +-#define ETRANSORIENT -23 ++#define EVAL 2 ++#define EVER 3 ++#define EOPEN 4 ++#define ECLOSE 5 ++#define ESETUP 6 ++#define ELAYER 7 ++#define EOPGEO 8 ++#define ESYNTAX 9 ++#define EORIENT 10 ++#define EHEADER 11 ++#define EMISSEOF 12 ++#define ETYPESEG 13 ++#define ETYPEVIA 14 ++#define ENAMETRS 15 ++#define ENBFIELDS 16 ++#define EFILENAME 17 ++#define EFILETYPE 18 ++#define EBOUNDBOX 19 ++#define EABUTMBOX 20 ++#define EALLOCFIG 21 ++#define ECOMPONENT 22 ++#define ETRANSORIENT 23 + + + #define mc_nexttoken(p_head,p_next,error_code) \ +@@ -1125,10 +1125,10 @@ static void alc_printerror(error_code) + fprintf( stderr, "ptfig not allocated"); break; + case ECOMPONENT : + fprintf( stderr, "invalid component"); break; +- default : fprintf( stderr, "unknow error"); ++ default : fprintf( stderr, "unknow error code %ld", error_code ); + } + fprintf( stderr, "\n( line %ld parsing %s )\n",parser.curr_line, +- parser.file_name ); EXIT( 1); ++ parser.file_name ); EXIT( 1); + } + + +diff --git a/alliance/src/mbk/src/mbk_util.c b/alliance/src/mbk/src/mbk_util.c +index 88ccfde..cc04f5b 100644 +--- a/alliance/src/mbk/src/mbk_util.c ++++ b/alliance/src/mbk/src/mbk_util.c +@@ -90,6 +90,15 @@ long MBK_TRACK_SPACING_ALU5 = 8; + long MBK_TRACK_SPACING_ALU6 = 8; + long MBK_TRACK_SPACING_ALU7 = 8; + long MBK_TRACK_SPACING_ALU8 = 0; ++unsigned long RING_WMIN_ALU1 = 2; ++unsigned long RING_WMIN_ALU2 = 2; ++unsigned long RING_DMIN_ALU1_ALU1 = 3; ++unsigned long RING_DMIN_ALU2_ALU2 = 3; ++unsigned long RING_WVIA_ALU1 = 2; ++unsigned long RING_WVIA_ALU2 = 3; ++unsigned long RING_EXTENSION_ALU2 = 1; ++unsigned long RING_BV_VIA_VIA = 4; ++unsigned long RING_WALIM = 60; + char PARSER_INFO[100] = "nothing yet"; /* version number, and so on */ + char *VDD = NULL; /* user name for power high */ + char *VSS = NULL; /* user name for power ground */ +@@ -302,6 +311,43 @@ static char MBK_RAND_SEED[] = { 0x62, + if (str != NULL) + MBK_TRACK_SPACING_ALU8 = (long)atoi(str); + ++ str = mbkgetenv("RING_WMIN_ALU1"); ++ if (str != NULL) ++ RING_WMIN_ALU1 = (long)atoi(str); ++ ++ str = mbkgetenv("RING_WMIN_ALU2"); ++ if (str != NULL) ++ RING_WMIN_ALU2 = (long)atoi(str); ++ ++ str = mbkgetenv("RING_DMIN_ALU1_ALU1"); ++ if (str != NULL) ++ RING_DMIN_ALU1_ALU1 = (long)atoi(str); ++ ++ str = mbkgetenv("RING_DMIN_ALU2_ALU2"); ++ if (str != NULL) ++ RING_DMIN_ALU2_ALU2 = (long)atoi(str); ++ ++ str = mbkgetenv("RING_WVIA_ALU1"); ++ if (str != NULL) ++ RING_WVIA_ALU1 = (long)atoi(str); ++ ++ str = mbkgetenv("RING_WVIA_ALU2"); ++ if (str != NULL) ++ RING_WVIA_ALU2 = (long)atoi(str); ++ ++ str = mbkgetenv("RING_EXTENSION_ALU2"); ++ if (str != NULL) ++ RING_EXTENSION_ALU2 = (long)atoi(str); ++ ++ str = mbkgetenv("RING_BV_VIA_VIA"); ++ if (str != NULL) ++ RING_BV_VIA_VIA = (long)atoi(str); ++ ++ str = mbkgetenv("RING_WALIM"); ++ if (str != NULL) ++ RING_WALIM = (long)atoi(str); ++ ++ + srand((unsigned int) MBK_RAND_SEED); + + str = mbkgetenv("MBK_IN_LO"); +diff --git a/alliance/src/mbk/src/mut.h b/alliance/src/mbk/src/mut.h +index 9e87261..11c2914 100644 +--- a/alliance/src/mbk/src/mut.h ++++ b/alliance/src/mbk/src/mut.h +@@ -211,6 +211,17 @@ extern long MBK_TRACK_SPACING_ALU5; + extern long MBK_TRACK_SPACING_ALU6; + extern long MBK_TRACK_SPACING_ALU7; + extern long MBK_TRACK_SPACING_ALU8; ++ ++extern unsigned long RING_WMIN_ALU1; ++extern unsigned long RING_WMIN_ALU2; ++extern unsigned long RING_DMIN_ALU1_ALU1; ++extern unsigned long RING_DMIN_ALU2_ALU2; ++extern unsigned long RING_WVIA_ALU1; ++extern unsigned long RING_WVIA_ALU2; ++extern unsigned long RING_EXTENSION_ALU2; ++extern unsigned long RING_BV_VIA_VIA; ++extern unsigned long RING_WALIM; ++ + extern char PARSER_INFO[]; /* version number, and so on */ + extern char *VDD; /* user name for power high */ + extern char *VSS; /* user name for power ground */ +diff --git a/alliance/src/nero/src/UDefs.h b/alliance/src/nero/src/UDefs.h +index f756e26..042e705 100644 +--- a/alliance/src/nero/src/UDefs.h ++++ b/alliance/src/nero/src/UDefs.h +@@ -38,7 +38,7 @@ + # include + # include + +-# include ++//# include + + + +diff --git a/alliance/src/nero/src/UOpts.cpp b/alliance/src/nero/src/UOpts.cpp +index 8fb4fd8..a369fd6 100644 +--- a/alliance/src/nero/src/UOpts.cpp ++++ b/alliance/src/nero/src/UOpts.cpp +@@ -16,12 +16,10 @@ + + + +-# include "unistd.h" ++# include + # include "UDefs.h" + + +- +- + // +----------------------------------------------------------------+ + // | Methods Definitions | + // +----------------------------------------------------------------+ +@@ -119,7 +117,7 @@ void COpts::getopts (int argc, char *argv[]) throw (except_done) + extern char *optarg; + int key; + long key_index; +- string key_string; ++ string key_string; + const char *short_format; + + +@@ -127,9 +125,9 @@ void COpts::getopts (int argc, char *argv[]) throw (except_done) + + short_format = tShort.c_str(); + +- // Loop over getopt. ++// Loop over getopt. + while (true) { +- key = getopt (argc, argv, short_format); ++ key = ::getopt (argc, argv, short_format); + + if (key == -1) break; + +diff --git a/alliance/src/nero/src/nero.cpp b/alliance/src/nero/src/nero.cpp +index d59566d..7a70240 100644 +--- a/alliance/src/nero/src/nero.cpp ++++ b/alliance/src/nero/src/nero.cpp +@@ -17,6 +17,11 @@ + + + # include "RDefs.h" ++# ifdef __CYGWIN__ ++extern "C" { ++ int getopt ( int argc, char * const argv[], const char *optstring ); ++} ++# endif + + + +diff --git a/alliance/src/ocp/src/placer/PCon.cpp b/alliance/src/ocp/src/placer/PCon.cpp +index e236e98..d69a635 100644 +--- a/alliance/src/ocp/src/placer/PCon.cpp ++++ b/alliance/src/ocp/src/placer/PCon.cpp +@@ -60,7 +60,7 @@ PCon::Save(struct phfig *physicalfig, const double dx, const double dy) const { + , (int)(GetPosX() * PITCH + dx) + , (int)(GetPosY() * PITCH + dy) + , _orient==NORTH || _orient == SOUTH ? ALU2 : ALU3 +- , (_orient==NORTH || _orient == SOUTH ? 2 : 1) * (PITCH/MBK_X_GRID)); ++ , (_orient==NORTH || _orient == SOUTH ? MBK_TRACK_WIDTH_ALU2:MBK_TRACK_WIDTH_ALU3)*SCALE_X); + } else { + #if 0 + addphcon(physicalfig, +@@ -89,7 +89,7 @@ PCon::RingSave(struct phfig *physicalfig, const double dx, const double dy) cons + (int)(GetPosX() * PITCH + dx), + (int)(GetPosY() * PITCH + dy), + ALU2, +- 2 * (PITCH/MBK_X_GRID)); ++ MBK_TRACK_WIDTH_ALU2*SCALE_X); + } + + ostream& +diff --git a/alliance/src/ocp/src/placer/iocscan.l b/alliance/src/ocp/src/placer/iocscan.l +index db95f60..3279e05 100644 +--- a/alliance/src/ocp/src/placer/iocscan.l ++++ b/alliance/src/ocp/src/placer/iocscan.l +@@ -1,6 +1,7 @@ + + %option noinput + %option nounput ++%option yylineno + + /* This file is part of the Alliance Project. + Copyright (C) Laboratoire LIP6 - Departement ASIM +diff --git a/alliance/src/rds/etc/Makefile.am b/alliance/src/rds/etc/Makefile.am +index ab78e4e..d5cca76 100644 +--- a/alliance/src/rds/etc/Makefile.am ++++ b/alliance/src/rds/etc/Makefile.am +@@ -1,8 +1,7 @@ +-# $Id: Makefile.am,v 1.5 2002/05/08 21:07:26 jpc Exp $ + + etcdir=$(prefix)/etc + +-etc_DATA=cmos.rds ++etc_DATA=cmos.rds scn6m_deep_09.rds + + EXTRA_DIST=$(etc_DATA) + +diff --git a/alliance/src/rds/etc/cmos.rds b/alliance/src/rds/etc/cmos.rds +index d1a6bed..b597366 100644 +--- a/alliance/src/rds/etc/cmos.rds ++++ b/alliance/src/rds/etc/cmos.rds +@@ -396,6 +396,42 @@ TABLE S2R_MINIMUM_LAYER_WIDTH + END + + ##------------------------------------------------------------------- ++# TABLE MBK_WIRESETTING : ++##------------------------------------------------------------------- ++# ++# This table is used by ocp, nero & ring. It supplies *symbolic* ++# information about the routing grid, the cell gauge and the power ++# wires. ++ ++ ++TABLE MBK_WIRESETTING ++ ++ X_GRID 5 ++ Y_GRID 5 ++ Y_SLICE 50 ++ WIDTH_VDD 6 ++ WIDTH_VSS 6 ++ TRACK_WIDTH_ALU8 0 ++ TRACK_WIDTH_ALU7 2 ++ TRACK_WIDTH_ALU6 2 ++ TRACK_WIDTH_ALU5 2 ++ TRACK_WIDTH_ALU4 2 ++ TRACK_WIDTH_ALU3 2 ++ TRACK_WIDTH_ALU2 2 ++ TRACK_WIDTH_ALU1 2 ++ TRACK_SPACING_ALU8 0 ++ TRACK_SPACING_ALU7 8 ++ TRACK_SPACING_ALU6 8 ++ TRACK_SPACING_ALU5 3 ++ TRACK_SPACING_ALU4 3 ++ TRACK_SPACING_ALU3 3 ++ TRACK_SPACING_ALU2 3 ++ TRACK_SPACING_ALU1 3 ++ ++END ++ ++ ++##------------------------------------------------------------------- + # TABLE CIF_LAYER : + ##------------------------------------------------------------------- + +diff --git a/alliance/src/rds/etc/scn6m_deep_09.rds b/alliance/src/rds/etc/scn6m_deep_09.rds +new file mode 100644 +index 0000000..86b2ac8 +--- /dev/null ++++ b/alliance/src/rds/etc/scn6m_deep_09.rds +@@ -0,0 +1,2134 @@ ++ ++# ================================================================== ++# COPYRIGHT IS UNCERTAIN YET. ++# ++# This file is a derived from the Alliance cmos.rds, adapted by ++# Graham Petley for 0.13um and finally to MOSIS scn6m_deep by ++# Naohiko Shimizu. It is a 2lambdas rules. ++# ++# To be used with the msxlib and mpxlib libraries (the leading 'm' ++# standing for MOSIS). ++# ++# The design rules are listed (i) the 0.13um generic rule set; ++# (ii) the vsclib 2um rules scaled by the value of lambda (0.055); ++# (iii) the MOSIS SCMOS and (iv) DEEP rules scaled by 0.06; ++# (v) the vsclib 2um rules. ++#------------------------------------+-----+-----+-----+-----+-----+ ++# DESIGN RULES | notes ++#------------------------------------+-----+-----+-----+-----+-----+ ++# 0.13 vsclib MOSIS DEEP 2um ++#------------------------------------+-----+-----+-----+-----+-----+ ++# 1.1 NWELL width 0.64 0.99 0.60 0.72 18.0 ++# 1.1 PWELL width 0.64 0.99 0.60 0.72 18.0 ++# 1.3 NWELL space 0.64 0.99 0.36 0.36 18.0 ++# 1.3 PWELL space 0.64 0.99 0.36 0.36 18.0 ++#------------------------------------+-----+-----+-----+-----+-----+ ++# 2.1a PDIF/NDIF width 0.20 0.22 0.18 0.18 4.0 ++# 2.1b PTIE/NTIE width 0.20 0.22 0.18 0.18 4.0 ++# 2.2a PDIF space 0.20 0.22 0.18 0.18 4.0 ++# 2.2a NDIF space 0.20 0.22 0.18 0.18 4.0 ++# 2.2b PTIE space 0.20 0.22 0.18 0.18 4.0 ++# 2.2b NTIE space 0.20 0.22 0.18 0.18 4.0 ++# 2.3a NWELL to NDIF space 0.32 0.33 0.30 0.36 6.0 ++# 2.3b NWELL overlap of PDIF 0.32 0.33 0.30 0.36 6.0 ++# 2.4a NWELL to PTIE space 0.24 0.275 0.18 0.18 5.0 ++# 2.4b NWELL overlap of NTIE 0.24 0.275 0.18 0.18 5.0 ++# 2.5 NDIF to PTIE space 0.20 0.22 0.24 0.24 4.0 ++# 2.5 PDIF to NTIE space 0.20 0.22 0.24 0.24 4.0 ++# 2.8a PDIF to NDIF space 0.64 0.66 0.60 0.72 12.0 ++# 2.8b PDIF to PTIE space 0.54 0.55 0.48 0.54 11.0 ++# 2.8b NTIE to NDIF space 0.54 0.55 0.48 0.54 11.0 ++# 2.8c NTIE to PTIE space 0.44 0.44 0.36 0.36 10.0 ++#------------------------------------+-----+-----+-----+-----+-----+ ++# 3.1 POLY width 0.12 0.11 0.12 0.12 2.0 ++# 3.2 POLY space over field 0.20 0.22 0.12 0.18 4.0 ++# 3.2a POLY space over diffusion 0.24 0.275 0.12 0.24 5.0 ++# 3.3 POLY overlap of transistor 0.18 0.22 0.12 0.15 4.0 ++# 3.4 Source/drain width 0.26 0.275 0.18 0.24 5.0 ++# 3.5 PDIF or NDIF to POLY space 0.10 0.11 0.06 0.06 2.0 ++# 3.5a POLY to CHANNEL space 0.10 0.165 0.06 0.06 3.0 ++#------------------------------------+-----+-----+-----+-----+-----+ ++# 4.1 SELECT to CHANNEL space 0.28 0.275 0.18 0.18 5.0 ++# 4.2a SELECT overlap of PDIF or NDIF 0.18 0.165 0.12 0.12 3.0 ++# 4.2b SELECT overlap of PTIE or NTIE 0.04 0.055 0.12 0.12 1.0 ++# 4.4 SELECT width 0.24 0.22 0.12 0.24 4.0 ++#------------------------------------+-----+-----+-----+-----+-----+ ++# 5.1 Exact POLY CONTACT size 0.16 0.11 0.12 0.12 2.0 ++# 5.2 POLY overlap of CONTACT 0.08 0.11 0.09 0.09 2.0 ++# 5.3 CONTACT space 0.20 0.275 0.12 0.24 5.0 ++# 5.4 POLY CONTACT to CHANNEL space 0.16 0.165 0.12 0.12 3.0 ++#------------------------------------+-----+-----+-----+-----+-----+ ++# 6.1 Exact PDIF or NDIF CONTACT size .16 0.11 0.12 0.12 2.0 ++# 6.1 Exact PTIE or NTIE CONTACT size .16 0.11 0.12 0.12 2.0 ++# 6.2a PDIF or NDIF overlap of CONTACT .08 0.11 0.09 0.09 2.0 ++# 6.2b PTIE or NTIE overlap of CONTACT .08 0.11 0.09 0.09 2.0 ++# 6.3 CONTACT space 0.20 0.275 0.12 0.24 5.0 ++# 6.4 PDIF CONTACT to CHANNEL space 0.12 0.165 0.12 0.12 3.0 ++# 6.4 NDIF CONTACT to CHANNEL space 0.12 0.165 0.12 0.12 3.0 ++# 6.4a PTIE CONTACT to CHANNEL space 0.40 0.44 0.39 0.39 8.0 ++# 6.4a NTIE CONTACT to CHANNEL space 0.40 0.44 0.39 0.39 8.0 ++#------------------------------------+-----+-----+-----+-----+-----+ ++# 7.1 Metal-1 width 0.18 0.22 0.18 0.18 4.0 ++# 7.2 Metal-1 space 0.18 0.165 0.12 0.18 3.0 ++# 7.3a Metal-1 side overlap of CONTACT .01 0.055 0.06 0.06 1.0 1 ++# 7.3b Metal-1 end overlap of CONTACT 0.06 0.11 0.06 0.06 2.0 ++#------------------------------------+-----+-----+-----+-----+-----+ ++# 8.1 VIA1 width 0.20 0.11 0.12 0.18 2.0 ++# 8.2 VIA1 space 0.24 0.33 0.18 0.18 6.0 ++# 8.3a Metal-1 side overlap of VIA1 0.01 0.055 0.06 0.06 1.0 1 ++# 8.3b Metal-1 end overlap of VIA1 0.06 0.11 0.06 0.06 2.0 2 ++#------------------------------------+-----+-----+-----+-----+-----+ ++# 9.x=Metal-2 15.x=Metal-3 22.x=Metal-4 26.x=Metal-5 ++#------------------------------------+-----+-----+-----+-----+-----+ ++# 9.1 Metal-2 width 0.22 0.22 0.18 0.18 4.0 ++# 9.2 Metal-2 space 0.22 0.22 0.18 0.24 4.0 ++# 9.3a Metal-2 side overlap of VIA1 0.01 0.055 0.06 0.06 1.0 1 ++# 9.3b Metal-2 end overlap of VIA1 0.06 0.11 0.06 0.06 2.0 2 ++#------------------------------------+-----+-----+-----+-----+-----+ ++# 14.x=VIA2 21.x=VIA3 25.x=VIA4 ++#------------------------------------+-----+-----+-----+-----+-----+ ++# 14.1 VIA2 width 0.20 0.11 0.12 0.18 2.0 ++# 14.2 VIA2 space 0.24 0.33 0.18 0.18 6.0 ++# 14.3a Metal-2 side overlap of VIA2 0.01 0.055 0.06 0.06 1.0 1 ++# 14.3b Metal-2 end overlap of VIA2 0.06 0.11 0.06 0.06 2.0 2 ++#------------------------------------+-----+-----+-----+-----+-----+ ++# 29.1 VIA5 width 0.40 0.22 0.18 0.24 2.0 3 ++# 29.2 VIA5 space 0.48 0.66 0.24 0.24 14.0 ++# 29.3a Metal-5 side overlap of VIA5 0.02 0.11 0.06 0.06 3.0 1 ++# 29.3b Metal-5 end overlap of VIA5 0.06 0.165 0.06 0.06 4.0 2 ++#------------------------------------+-----+-----+-----+-----+-----+ ++# 30.1 Metal-6 width 0.44 0.44 0.30 0.30 8.0 ++# 30.2 Metal-6 space 0.44 0.44 0.30 0.30 8.0 ++# 30.3a Metal-6 side overlap of VIA5 0.13 0.22 0.06 0.12 3.0 ++# 30.3b Metal-6 end overlap of VIA5 0.13 0.22 0.06 0.12 4.0 ++#------------------------------------+-----+-----+-----+-----+-----+ ++# ++#notes ++# 1. Metal overlap of CONTACT and VIA rules have been divided ++# into two. Modern technologies have one (small) side ++# overlap (1 in the drawing) and a ++# 1 larger end overlap (2 in the drawing). ++# |--| For metal-1, the vsclib uses 1.0 for (1) ++# +--------+ - and 2.0 for (2). The rule set has checks ++# |////////| | for these different values. The checks ++# |////////| | 2 for the higher metal overlap rules (934, ++# |//+--+//| + 1434, 1534, 2134, 2234, 2534, 2634, ++# |//| |//| 2934) are present. They have been ++# |//+--+//| commented (except for ALU6) in the vsc013x ++# |////////| RDS file. ++# ++# 2. The end overlap of metal over via should be 2 lambda, but ++# this isn't supported by NERO. For metal-1 the support is in the ++# cell layout. For the upper metal layers the end overlap must ++# be added by a script. Checks are made in vsc013.rds but not in ++# vsc013x.rds. ++# 3. Rules are for a 6 layer metal process. For fewer layers, ++# apply metal-6 to top metal and VIA5 to top via. ++# ++##------------------------------------------------------------------- ++# PHYSICAL_GRID : ++##------------------------------------------------------------------- ++ ++DEFINE PHYSICAL_GRID 0.005 ++ ++##------------------------------------------------------------------- ++# LAMBDA : ++##------------------------------------------------------------------- ++ ++DEFINE LAMBDA 0.09 ++ ++##------------------------------------------------------------------- ++# TABLE MBK_TO_RDS_SEGMENT : ++# ++# MBK RDS layer 1 RDS layer 2 ++# name name TRANS DLR DWR OFFSET name TRANS DLR DWR OFFSET ... ++##------------------------------------------------------------------- ++ ++TABLE MBK_TO_RDS_SEGMENT ++ ++ PWELL RDS_PWELL VW 0.36 0.0 0.0 ALL \ ++ RDS_USER6 VW 0.36 0.0 0.0 DRC ++ NWELL RDS_NWELL VW 0.36 0.0 0.0 ALL \ ++ RDS_USER3 VW 0.36 0.0 0.0 DRC ++ ++# The NIMP/PIMP layers are not visualised in ++# Graal. If you want to see the layers, change ++# the keyword in the NIMP/PIMP entry from DRC to ALL. ++# TVIA3 and TVIA4 are replicas of PIMP and NIMP ++# to ensure geometries written to CIF and GDS. ++ NDIF RDS_NDIF VW 0.18 0.0 0.0 ALL \ ++ RDS_ACTIV VW 0.18 0.0 0.0 DRC \ ++ RDS_NIMP VW 0.36 0.36 0.0 DRC \ ++ RDS_TVIA4 VW 0.36 0.36 0.0 DRC ++ PDIF RDS_PDIF VW 0.18 0.0 0.0 ALL \ ++ RDS_ACTIV VW 0.18 0.0 0.0 DRC \ ++ RDS_PIMP VW 0.36 0.36 0.0 DRC \ ++ RDS_TVIA3 VW 0.36 0.36 0.0 DRC ++ ++# RDS_NTIE EXT is for visualisation in Graal. ++# RDS_NTIE DRC makes a NIMP layer the same as RDS_NIMP. ++# The NTIE is used to make an implant layer because ++# s2r with the -i option uses NTIE to "cut" a hole in ++# the PIMP implant generated from NWELL. The real NTIE ++# layer is too small for this hole, so the layer is ++# redefined in DRC mode to give the right size hole. ++# RDS_ACTIV is the diffusion layer. ++# RDS_NIMP makes a second implant layer which is the same ++# as the RDS_NTIE. It is included so that the implant layer ++# can be seen in Graal if the DRC entry is changed to ALL. ++# RDS_TPOLY is used to write out an NTIE geometry to ++# CIF and GDS, and for design rule checks to the diffusion ++# layer. NTIE cannot be used for this because it must be ++# oversized to the implant layer. ++# s2r must be run twice to make a single correct ++# CIF or GDS file for cell fred.ap, ++# $ s2r -i fred ++# $ s2r -p fred ++# These should not be combined and must be run one after ++# the other. ++# Make sure old CIF files are removed before running s2r. ++# NTIE RDS_NTIE VW 0.495 0.54 0.0 EXT \ ++# RDS_NTIE VW 0.495 0.54 0.0 DRC \ ++# RDS_ACTIV VW 0.135 -0.09 0.0 DRC \ ++# RDS_NIMP VW 0.495 0.54 0.0 DRC \ ++# RDS_TPOLY VW 0.135 -0.09 0.0 DRC ++# PTIE RDS_PTIE VW 0.495 0.54 0.0 EXT \ ++# RDS_PTIE VW 0.495 0.54 0.0 DRC \ ++# RDS_ACTIV VW 0.135 -0.09 0.0 DRC \ ++# RDS_PIMP VW 0.495 0.54 0.0 DRC \ ++# RDS_VPOLY VW 0.135 -0.09 0.0 DRC ++ ++ NTIE RDS_NTIE VW 0.045 -0.09 0.0 EXT \ ++ RDS_NTIE VW 0.225 0.27 0.0 DRC \ ++ RDS_ACTIV VW 0.045 -0.09 0.0 DRC \ ++ RDS_NIMP VW 0.225 0.27 0.0 DRC \ ++ RDS_TPOLY VW 0.045 -0.09 0.0 DRC ++ PTIE RDS_PTIE VW 0.045 -0.09 0.0 EXT \ ++ RDS_PTIE VW 0.225 0.27 0.0 DRC \ ++ RDS_ACTIV VW 0.045 -0.09 0.0 DRC \ ++ RDS_PIMP VW 0.225 0.27 0.0 DRC \ ++ RDS_VPOLY VW 0.045 -0.09 0.0 DRC ++ ++# The GATE layer is the poly which makes the ++# transistor. It is used to measure the ENDCAP ++# value. ++ NTRANS RDS_POLY VW 0.27 0.00 0.0 ALL \ ++ RDS_GATE VW 0.27 0.00 0.0 DRC \ ++ RDS_NDIF LCW 0.0 0.27 0.0 EXT \ ++ RDS_NDIF RCW 0.0 0.27 0.0 EXT \ ++ RDS_NDIF VW 0.0 0.72 0.0 DRC \ ++ RDS_ACTIV VW 0.0 0.72 0.0 ALL \ ++ RDS_NIMP VW 0.18 1.26 0.0 DRC \ ++ RDS_NIMP VW 0.18 1.26 0.0 DRC \ ++ RDS_TVIA4 VW 0.18 1.26 0.0 DRC \ ++ RDS_TVIA4 VW 0.18 1.26 0.0 DRC ++ PTRANS RDS_POLY VW 0.27 0.00 0.0 ALL \ ++ RDS_GATE VW 0.27 0.00 0.0 DRC \ ++ RDS_PDIF LCW 0.0 0.27 0.0 EXT \ ++ RDS_PDIF RCW 0.0 0.27 0.0 EXT \ ++ RDS_PDIF VW 0.0 0.72 0.0 DRC \ ++ RDS_ACTIV VW 0.0 0.72 0.0 ALL \ ++ RDS_PIMP VW 0.18 1.26 0.0 ALL \ ++ RDS_PIMP VW 0.18 1.26 0.0 DRC \ ++ RDS_TVIA3 VW 0.18 1.26 0.0 DRC \ ++ RDS_TVIA3 VW 0.18 1.26 0.0 DRC ++ POLY RDS_POLY VW 0.09 0.00 0.0 ALL ++ ++# POLY2 layer used to define metal-1 which ++# has a 7 lambda pitch. ALU1 layer is used for ++# metal-1 which has an 8 lambda pitch ++# Layer USER0 is used to check for the end overlap of ++# 2 lambda wide metal-1 to CONT. Layer USER1 checks 4 lambda ++# wide metal-1. Their DLR is ++# metal-1_DLR + lambda + CONT_width/2 + end_overlap ++# = 0.095 + 0.055 + 0.08 + 0.06 = 0.29 ++# USER0 DWR is 0.0. ++# USER1 DWR set to size USER1 to CONT width (0.22-0.06=0.16). ++# Layer USER2 is used to check for the end overlap of ++# 4 lambda metal-1. Its DWR is ++# max(CONT+2*end_overlap,width of 4 lambda metal-1)-4 ++# = max(0.16+2*0.06,0.22)-0.22 = max(0.28,0.22)-0.22 = 0.06 ++# USER2 DLR is set to half CONT width (0.08) ++# USER4 and USER5 match USER1 and USER2 for VIA ++# POLY2 RDS_POLY2 VW 0.18 0.09 0.0 ALL \ ++# RDS_USER0 VW 0.18 0.09 0.0 DRC \ ++# RDS_USER1 VW 0.18 0.09 0.0 DRC \ ++# RDS_USER2 VW 0.18 0.09 0.0 DRC \ ++# RDS_USER4 VW 0.18 0.09 0.0 DRC \ ++# RDS_USER5 VW 0.18 0.09 0.0 DRC ++ ++ ALU1 RDS_ALU1 VW 0.18 0.09 0.0 ALL \ ++ RDS_USER0 VW 0.18 0.09 0.0 DRC \ ++ RDS_USER1 VW 0.18 0.09 0.0 DRC \ ++ RDS_USER2 VW 0.18 0.09 0.0 DRC \ ++ RDS_USER4 VW 0.18 0.09 0.0 DRC \ ++ RDS_USER5 VW 0.18 0.09 0.0 DRC ++ ++# Layers VALU2-VALU6 and TALU2-TALU6 are used to ++# check for the end overlap of the metal to via. ++ ALU2 RDS_ALU2 VW 0.135 0.00 0.0 ALL \ ++ RDS_TALU2 VW 0.135 0.00 0.0 DRC \ ++ RDS_VALU2 VW 0.135 0.00 0.0 DRC ++ ALU3 RDS_ALU3 VW 0.135 0.00 0.0 ALL \ ++ RDS_TALU3 VW 0.135 0.00 0.0 DRC \ ++ RDS_VALU3 VW 0.135 0.00 0.0 DRC ++ ALU4 RDS_ALU4 VW 0.135 0.00 0.0 ALL \ ++ RDS_TALU4 VW 0.135 0.00 0.0 DRC \ ++ RDS_VALU4 VW 0.135 0.00 0.0 DRC ++ ALU5 RDS_ALU5 VW 0.135 0.00 0.0 ALL \ ++ RDS_TALU5 VW 0.135 0.00 0.0 DRC \ ++ RDS_VALU5 VW 0.135 0.00 0.0 DRC ++ ALU6 RDS_ALU6 VW 0.225 0.00 0.0 ALL \ ++ RDS_TALU6 VW 0.225 0.00 0.0 DRC \ ++ RDS_VALU6 VW 0.225 0.00 0.0 DRC ++ ++ CALU1 RDS_ALU1 VW 0.18 0.0 0.0 ALL ++ CALU2 RDS_ALU2 VW 0.135 0.0 0.0 ALL ++ CALU3 RDS_ALU3 VW 0.135 0.0 0.0 ALL ++ CALU4 RDS_ALU4 VW 0.135 0.0 0.0 ALL ++ CALU5 RDS_ALU5 VW 0.135 0.0 0.0 ALL ++ CALU6 RDS_ALU6 VW 0.225 0.0 0.0 ALL ++ TALU1 RDS_TALU1 VW 0.18 0.0 0.0 ALL ++ TALU2 RDS_TALU2 VW 0.135 0.0 0.0 ALL ++ TALU3 RDS_TALU3 VW 0.135 0.0 0.0 ALL ++ TALU4 RDS_TALU4 VW 0.135 0.0 0.0 ALL ++ TALU5 RDS_TALU5 VW 0.135 0.0 0.0 ALL ++ TALU6 RDS_TALU6 VW 0.225 0.0 0.0 ALL ++ TALU8 RDS_TALU8 VW 0.00 0.0 0.0 ALL ++ ++END ++ ++##------------------------------------------------------------------- ++# TABLE MBK_TO_RDS_CONNECTOR : ++# ++# MBK RDS layer ++# name name DER DWR ++##------------------------------------------------------------------- ++ ++TABLE MBK_TO_RDS_CONNECTOR ++ ++ POLY RDS_POLY 0.00 0.00 ++# POLY2 RDS_POLY2 0.00 0.00 ++ ALU1 RDS_ALU1 0.00 0.00 ++ ALU2 RDS_ALU2 0.00 0.00 ++ ALU3 RDS_ALU3 0.00 0.00 ++ ALU4 RDS_ALU4 0.00 0.00 ++ ALU5 RDS_ALU5 0.00 0.00 ++ ALU6 RDS_ALU6 0.00 0.00 ++ ++END ++ ++##------------------------------------------------------------------- ++# TABLE MBK_TO_RDS_REFERENCE : ++# ++# MBK ref RDS layer ++# name name width ++##------------------------------------------------------------------- ++ ++TABLE MBK_TO_RDS_REFERENCE ++ ++ REF_REF RDS_REF 0.27 ++ REF_CON RDS_VALU1 0.27 RDS_TVIA1 0.27 RDS_TALU2 0.36 ++ ++END ++ ++##------------------------------------------------------------------- ++# TABLE MBK_TO_RDS_VIA : ++# ++# MBK via RDS layer 1 RDS layer 2 RDS layer 3 RDS layer 4 ++# name name width name width name width name width ++##------------------------------------------------------------------- ++ ++TABLE MBK_TO_RDS_VIA ++# The NIMP/PIMP layers are not visualised in Graal. If you want to ++# see the layers, change the keyword for NIMP/PIMP from DRC to ALL. ++ ++ CONT_BODY_P\ ++ RDS_PTIE 0.81 DRC\ ++ RDS_PTIE 0.45 EXT\ ++ RDS_VPOLY 0.45 DRC\ ++ RDS_CONT 0.18 ALL\ ++ RDS_ALU1 0.36 ALL\ ++ RDS_ACTIV 0.45 DRC\ ++ RDS_PIMP 0.81 DRC ++ CONT_BODY_N\ ++ RDS_NTIE 0.81 DRC\ ++ RDS_NTIE 0.45 EXT\ ++ RDS_TPOLY 0.45 DRC\ ++ RDS_CONT 0.18 ALL\ ++ RDS_ALU1 0.36 ALL\ ++ RDS_ACTIV 0.45 DRC\ ++ RDS_NIMP 0.81 DRC ++ CONT_DIF_N\ ++ RDS_NDIF 0.54 ALL\ ++ RDS_CONT 0.18 ALL\ ++ RDS_ALU1 0.36 ALL\ ++ RDS_ACTIV 0.54 DRC\ ++ RDS_NIMP 0.90 DRC\ ++ RDS_TVIA4 0.90 DRC ++ CONT_DIF_P\ ++ RDS_PDIF 0.54 ALL\ ++ RDS_CONT 0.18 ALL\ ++ RDS_ALU1 0.36 ALL\ ++ RDS_ACTIV 0.54 DRC\ ++ RDS_PIMP 0.90 DRC\ ++ RDS_TVIA3 0.90 DRC ++ CONT_POLY\ ++ RDS_POLY 0.54 ALL\ ++ RDS_CONT 0.18 ALL\ ++ RDS_ALU1 0.36 ALL ++ CONT_VIA\ ++ RDS_ALU1 0.45 ALL\ ++ RDS_VIA1 0.27 ALL\ ++ RDS_ALU2 0.45 ALL ++ CONT_VIA2\ ++ RDS_ALU2 0.45 ALL\ ++ RDS_VIA2 0.27 ALL\ ++ RDS_VALU3 0.45 ALL\ ++ RDS_TALU3 0.45 ALL\ ++ RDS_ALU3 0.45 ALL ++ CONT_VIA3\ ++ RDS_ALU3 0.45 ALL\ ++ RDS_VIA3 0.27 ALL\ ++ RDS_VALU4 0.45 ALL\ ++ RDS_TALU4 0.45 ALL\ ++ RDS_ALU4 0.45 ALL ++ CONT_VIA4\ ++ RDS_ALU4 0.45 ALL\ ++ RDS_VIA4 0.27 ALL\ ++ RDS_VALU5 0.45 ALL\ ++ RDS_TALU5 0.45 ALL\ ++ RDS_ALU5 0.45 ALL ++ CONT_VIA5\ ++ RDS_ALU5 0.63 ALL\ ++ RDS_VIA5 0.45 ALL\ ++ RDS_VALU6 0.72 ALL\ ++ RDS_TALU6 0.72 ALL\ ++ RDS_ALU6 0.72 ALL ++ C_X_N\ ++ RDS_POLY 0.36 ALL\ ++ RDS_NDIF 0.55 ALL\ ++ RDS_ACTIV 0.55 ALL ++ C_X_P\ ++ RDS_POLY 0.36 ALL\ ++ RDS_PDIF 0.55 ALL\ ++ RDS_ACTIV 0.55 ALL ++END ++ ++##------------------------------------------------------------------- ++# TABLE MBK_TO_RDS_BIGVIA_HOLE : ++# ++# MBK via RDS Hole ++# name name side step mode ++##------------------------------------------------------------------- ++ ++TABLE MBK_TO_RDS_BIGVIA_HOLE ++ ++CONT_VIA RDS_VIA1 0.27 0.27 ALL ++CONT_VIA2 RDS_VIA2 0.27 0.27 ALL ++CONT_VIA3 RDS_VIA3 0.27 0.27 ALL ++CONT_VIA4 RDS_VIA4 0.27 0.27 ALL ++CONT_VIA5 RDS_VIA5 0.36 0.36 ALL ++ ++END ++ ++##------------------------------------------------------------------- ++# TABLE MBK_TO_RDS_BIGVIA_METAL : ++# ++# MBK via RDS layer 1 ... ++# name name delta-width overlap mode ++##------------------------------------------------------------------- ++ ++TABLE MBK_TO_RDS_BIGVIA_METAL ++ ++CONT_VIA RDS_ALU1 0.0 0.09 ALL RDS_ALU2 0.0 0.09 ALL ++CONT_VIA2 RDS_ALU2 0.0 0.09 ALL RDS_ALU3 0.0 0.09 ALL ++CONT_VIA3 RDS_ALU3 0.0 0.09 ALL RDS_ALU4 0.0 0.09 ALL ++CONT_VIA4 RDS_ALU4 0.0 0.09 ALL RDS_ALU5 0.0 0.09 ALL ++CONT_VIA5 RDS_ALU5 0.0 0.09 ALL RDS_ALU6 0.0 0.18 ALL ++ ++END ++ ++##------------------------------------------------------------------- ++# TABLE MBK_TO_RDS_TURNVIA : ++# ++# MBK via RDS layer 1 ... ++# name name DWR MODE ++##------------------------------------------------------------------- ++ ++TABLE MBK_TO_RDS_TURNVIA ++ ++CONT_TURN1 RDS_ALU1 0.0 ALL ++CONT_TURN2 RDS_ALU2 0.0 ALL ++CONT_TURN3 RDS_ALU3 0.0 ALL ++CONT_TURN4 RDS_ALU4 0.0 ALL ++CONT_TURN5 RDS_ALU5 0.0 ALL ++CONT_TURN6 RDS_ALU6 0.0 ALL ++ ++END ++ ++TABLE MBK_WIRESETTING ++X_GRID 10 ++Y_GRID 10 ++Y_SLICE 100 ++WIDTH_VDD 12 ++WIDTH_VSS 12 ++TRACK_WIDTH_ALU8 0 ++TRACK_WIDTH_ALU7 4 ++TRACK_WIDTH_ALU6 4 ++TRACK_WIDTH_ALU5 4 ++TRACK_WIDTH_ALU4 3 ++TRACK_WIDTH_ALU3 3 ++TRACK_WIDTH_ALU2 3 ++TRACK_WIDTH_ALU1 3 ++TRACK_SPACING_ALU8 0 ++TRACK_SPACING_ALU7 4 ++TRACK_SPACING_ALU6 4 ++TRACK_SPACING_ALU5 4 ++TRACK_SPACING_ALU4 4 ++TRACK_SPACING_ALU3 4 ++TRACK_SPACING_ALU2 4 ++TRACK_SPACING_ALU1 3 ++WMIN_ALU1 3 ++WMIN_ALU2 3 ++DMIN_ALU1_ALU1 5 ++DMIN_ALU2_ALU2 5 ++WVIA_ALU1 5 ++WVIA_ALU2 5 ++EXTENSION_ALU2 1 ++BV_VIA_VIA 8 ++WALIM 60 ++END ++ ++ ++##------------------------------------------------------------------- ++# TABLE LYNX_GRAPH : ++# ++# RDS layer Rds layer 1 Rds layer 2 ... ++# name name name ... ++##------------------------------------------------------------------- ++ ++TABLE LYNX_GRAPH ++ ++##--------------------------- ++ ++ RDS_NDIF RDS_CONT RDS_NDIF ++ RDS_PDIF RDS_CONT RDS_PDIF ++ RDS_NTIE RDS_CONT RDS_TPOLY RDS_NTIE ++ RDS_PTIE RDS_CONT RDS_VPOLY RDS_PTIE ++ ++ RDS_POLY RDS_CONT RDS_POLY ++ RDS_CONT RDS_PDIF RDS_NDIF RDS_POLY RDS_PTIE RDS_NTIE RDS_ALU1 RDS_POLY2 RDS_CONT ++ RDS_POLY2 RDS_CONT RDS_ALU1 RDS_POLY2 ++ RDS_ALU1 RDS_CONT RDS_VIA1 RDS_POLY2 RDS_ALU1 ++ ++ RDS_VIA1 RDS_ALU1 RDS_ALU2 RDS_VIA1 ++ RDS_VIA2 RDS_ALU2 RDS_ALU3 RDS_VIA2 ++ RDS_VIA3 RDS_ALU3 RDS_ALU4 RDS_VIA3 ++ RDS_VIA4 RDS_ALU4 RDS_ALU5 RDS_VIA4 ++ RDS_VIA5 RDS_ALU5 RDS_ALU6 RDS_VIA5 ++ RDS_ALU2 RDS_VIA1 RDS_VIA2 RDS_ALU2 ++ RDS_ALU3 RDS_VIA2 RDS_VIA3 RDS_ALU3 ++ RDS_ALU4 RDS_VIA3 RDS_VIA4 RDS_ALU4 ++ RDS_ALU5 RDS_VIA4 RDS_VIA5 RDS_ALU5 ++ RDS_ALU6 RDS_VIA5 RDS_ALU6 ++ ++END ++ ++##------------------------------------------------------------------- ++# TABLE LYNX_CAPA : ++# ++# RDS layer Surface capacitance Perimetric capacitance ++# name piF / Micron^2 piF / Micron ++##------------------------------------------------------------------- ++ ++TABLE LYNX_CAPA ++# poly alu0 alu1 alu2 alu3 alu4 alu5 alu6 ++# pitch 7 14 14 16 16 16 16 36 ++ RDS_POLY 10.10E-05 10.00e-05 ++ RDS_POLY2 3.400e-05 5.300e-05 ++ RDS_ALU1 3.400e-05 5.300e-05 ++ RDS_ALU2 1.400e-05 3.600e-05 ++ RDS_ALU3 0.900e-05 2.900e-05 ++ RDS_ALU4 0.700e-05 2.400e-05 ++ RDS_ALU5 0.500e-05 2.100e-05 ++ RDS_ALU6 0.400e-05 1.900e-05 ++ ++END ++ ++##------------------------------------------------------------------- ++# TABLE LYNX_RESISTOR : ++# ++# RDS layer Surface resistor ++# name Ohm / Micron^2 ++##------------------------------------------------------------------- ++ ++TABLE LYNX_RESISTOR ++ ++ RDS_POLY 8.3 ++ RDS_POLY2 0.08 ++ RDS_ALU1 0.08 ++ RDS_ALU2 0.08 ++ RDS_ALU3 0.08 ++ RDS_ALU4 0.08 ++ RDS_ALU5 0.07 ++ RDS_ALU6 0.01 ++ ++END ++ ++##------------------------------------------------------------------- ++# TABLE LYNX_TRANSISTOR : ++# ++# MBK layer Transistor Type MBK via ++# name name name ++##------------------------------------------------------------------- ++ ++TABLE LYNX_TRANSISTOR ++ ++ NTRANS NTRANS C_X_N RDS_POLY RDS_NDIF RDS_NDIF RDS_PWELL ++ PTRANS PTRANS C_X_P RDS_POLY RDS_PDIF RDS_PDIF RDS_NWELL ++ ++END ++ ++##------------------------------------------------------------------- ++# TABLE LYNX_DIFFUSION : ++# ++# RDS layer RDS layer ++# name name ++##------------------------------------------------------------------- ++ ++TABLE LYNX_DIFFUSION ++END ++ ++##------------------------------------------------------------------- ++# TABLE LYNX_BULK_IMPLICIT : ++# ++# RDS layer Bulk type ++# name EXPLICIT/IMPLICIT ++##------------------------------------------------------------------- ++ ++TABLE LYNX_BULK_IMPLICIT ++END ++ ++ ++ ++##------------------------------------------------------------------- ++# TABLE S2R_OVERSIZE_DENOTCH : ++##------------------------------------------------------------------- ++ ++TABLE S2R_OVERSIZE_DENOTCH ++ RDS_NWELL 1.075 ++ RDS_PWELL 1.075 ++ RDS_ACTIV 0.175 ++ RDS_PDIF 0.265 ++ RDS_NDIF 0.265 ++ RDS_TPOLY 0.265 ++ RDS_VPOLY 0.265 ++ RDS_NTIE 0.265 ++ RDS_PTIE 0.265 ++# The NIMP and PIMP values are used to set the width of WELL and ++# IMPlant beyond the Abox. Values set equal to the NIMP/PIMP ++# overlap of TIE contact so that thin slivers of IMPlant are not ++# inserted between the TIE implant and well edge. ++ RDS_PIMP 0.355 ++ RDS_NIMP 0.355 ++# Denotch NIMP and PIMP with user layers allowing single implant ++# contact between two implant edges. ++# Width is (2.5+6.2a)*2+6.1=(0.20+0.08)*2+0.16=0.72. Denotch just below. ++ RDS_TVIA3 0.0 ++ RDS_TVIA4 0.0 ++ RDS_POLY 0.0 ++ RDS_POLY2 0.0 ++ RDS_ALU1 0.0 ++ RDS_ALU2 0.0 ++ RDS_ALU3 0.0 ++ RDS_ALU4 0.0 ++ RDS_ALU5 0.0 ++ RDS_ALU6 0.0 ++END ++ ++##------------------------------------------------------------------- ++# TABLE S2R_BLOC_RING_WIDTH : ++##------------------------------------------------------------------- ++ ++TABLE S2R_BLOC_RING_WIDTH ++END ++ ++##------------------------------------------------------------------- ++# TABLE S2R_MINIMUM_LAYER_WIDTH : ++##------------------------------------------------------------------- ++ ++TABLE S2R_MINIMUM_LAYER_WIDTH ++ ++ RDS_NWELL 1.08 ++ RDS_PWELL 1.08 ++ RDS_NDIF 0.27 ++ RDS_PDIF 0.27 ++ RDS_NTIE 0.27 ++ RDS_PTIE 0.27 ++ RDS_TPOLY 0.27 ++ RDS_VPOLY 0.27 ++ RDS_PIMP 0.36 ++ RDS_NIMP 0.36 ++ RDS_POLY 0.18 ++ RDS_CONT 0.18 ++ RDS_POLY2 0.27 ++ RDS_ALU1 0.27 ++ RDS_TALU1 0.27 ++ RDS_VIA1 0.27 ++ RDS_ALU2 0.27 ++ RDS_TALU2 0.27 ++ RDS_VIA2 0.27 ++ RDS_ALU3 0.27 ++ RDS_TALU3 0.27 ++ RDS_VIA3 0.27 ++ RDS_ALU4 0.27 ++ RDS_TALU4 0.27 ++ RDS_VIA4 0.27 ++ RDS_ALU5 0.27 ++ RDS_TALU5 0.27 ++ RDS_VIA5 0.27 ++ RDS_ALU6 0.44 ++ RDS_TALU6 0.44 ++ RDS_REF 0.36 ++ RDS_TALU8 3.96 ++ ++END ++ ++##------------------------------------------------------------------- ++# TABLE CIF_LAYER : ++##------------------------------------------------------------------- ++ ++TABLE CIF_LAYER ++# Layer definitions used by MOSIS ++#-------------------------------- ++ RDS_NWELL CWN ++ RDS_PWELL CWP ++ RDS_USER3 CWN ++ RDS_USER6 CWP ++ RDS_NDIF CND ++ RDS_PDIF CPD ++ RDS_TPOLY CNS ++ RDS_VPOLY CPS ++# PTIE and NTIE actually provide the implants ++# around the cutouts for CONT_BODY_N and _P. ++ RDS_PTIE CSP ++ RDS_NTIE CSN ++ RDS_ACTIV CAA ++ RDS_PIMP CSP ++ RDS_NIMP CSN ++# If using 's2r -i' then the TVIA3 and TVIA4 ++# lines should be commented. If using 's2r' ++# only then the lines should be uncommented. ++# RDS_TVIA3 CSP ++# RDS_TVIA4 CSN ++ RDS_POLY CPG ++ RDS_CONT CCC ++# RDS_POLY2 CM1 ++ RDS_ALU1 CM1 ++# RDS_TALU1 TM1 ++ RDS_VIA1 CV1 ++ RDS_ALU2 CM2 ++# RDS_TALU2 TM2 ++ RDS_VIA2 CV2 ++ RDS_ALU3 CM3 ++# RDS_TALU3 TM3 ++ RDS_VIA3 CV3 ++ RDS_ALU4 CM4 ++# RDS_TALU4 TM4 ++ RDS_VIA4 CV4 ++ RDS_ALU5 CM5 ++# RDS_TALU5 TM5 ++ RDS_VIA5 CV5 ++ RDS_ALU6 CM6 ++# RDS_TALU6 TM6 ++ RDS_REF REF ++ RDS_TALU8 AB ++ ++# Layer definitions used by Alliance ++#----------------------------------- ++# RDS_NWELL LNWELL ++# RDS_PWELL LPWELL ++# RDS_NDIF LNDIF ++# RDS_PDIF LPDIF ++# RDS_TPOLY LTPOLY ++# RDS_VPOLY LVPOLY ++# RDS_NTIE LNTIE ++# RDS_PTIE LPTIE ++# RDS_PIMP LPIMP ++# RDS_NIMP LNIMP ++# RDS_POLY LPOLY ++# RDS_POLY2 LPOLY2 ++# RDS_CONT LCONT ++# RDS_POLY2 LALU1 ++# RDS_ALU1 LALU1 ++# RDS_TALU1 LTALU1 ++# RDS_VIA1 LVIA ++# RDS_ALU2 LALU2 ++# RDS_TALU2 LTALU2 ++# RDS_VIA2 LVIA2 ++# RDS_ALU3 LALU3 ++# RDS_TALU3 LTALU3 ++# RDS_VIA3 LVIA3 ++# RDS_ALU4 LALU4 ++# RDS_TALU4 LTALU4 ++# RDS_VIA4 LVIA4 ++# RDS_ALU5 LALU5 ++# RDS_TALU5 LTALU5 ++# RDS_VIA5 LVIA5 ++# RDS_ALU6 LALU6 ++# RDS_TALU6 LTALU6 ++# RDS_REF LREF ++END ++ ++##------------------------------------------------------------------- ++# TABLE GDS_LAYER : ++##------------------------------------------------------------------- ++ ++TABLE GDS_LAYER ++# Layer definitions used by MOSIS ++#-------------------------------- ++ RDS_PWELL 41 ++ RDS_NWELL 42 ++ RDS_USER6 41 ++ RDS_USER3 42 ++ RDS_NDIF 43 ++ RDS_PDIF 43 ++ RDS_TPOLY 43 ++ RDS_VPOLY 43 ++ RDS_PTIE 44 ++ RDS_NTIE 45 ++ RDS_ACTIV 43 ++ RDS_PIMP 44 ++ RDS_NIMP 45 ++# RDS_TVIA3 44 ++# RDS_TVIA4 45 ++ RDS_POLY 46 46 ++ RDS_CONT 25 ++# RDS_POLY2 49 49 ++ RDS_ALU1 49 49 ++# RDS_TALU1 13 ++ RDS_VIA1 50 ++ RDS_ALU2 51 51 ++# RDS_TALU2 17 ++ RDS_VIA2 61 ++ RDS_ALU3 62 62 ++# RDS_TALU3 20 ++ RDS_VIA3 30 ++ RDS_ALU4 31 31 ++# RDS_TALU4 23 ++ RDS_VIA4 32 ++ RDS_ALU5 33 33 ++# RDS_TALU5 27 ++ RDS_VIA5 36 ++ RDS_ALU6 37 37 ++# RDS_TALU6 30 ++# RDS_REF 24 ++# RDS_TALU8 63 ++ ++# Layer definitions used by Alliance ++#----------------------------------- ++# RDS_NWELL 1 ++# RDS_PWELL 2 ++# RDS_NDIF 3 ++# RDS_PDIF 4 ++# RDS_NTIE 5 ++# RDS_PTIE 6 ++# RDS_POLY 7 ++# RDS_POLY2 8 ++# RDS_TPOLY 9 ++# RDS_CONT 10 ++# RDS_POLY2 11 ++# RDS_ALU1 11 ++# RDS_TALU1 13 ++# RDS_VIA1 14 ++# RDS_ALU2 16 ++# RDS_TALU2 17 ++# RDS_VIA2 18 ++# RDS_ALU3 19 ++# RDS_TALU3 20 ++# RDS_VIA3 21 ++# RDS_ALU4 22 ++# RDS_TALU4 23 ++# RDS_VIA4 25 ++# RDS_ALU5 26 ++# RDS_TALU5 27 ++# RDS_VIA5 28 ++# RDS_ALU6 29 ++# RDS_TALU6 30 ++# RDS_REF 24 ++END ++ ++##------------------------------------------------------------------- ++# TABLE S2R_POST_TREAT : ++##------------------------------------------------------------------- ++ ++TABLE S2R_POST_TREAT ++ ++ RDS_NWELL TREAT NULL ++ RDS_PWELL TREAT NULL ++ RDS_NDIF TREAT NULL ++ RDS_PDIF TREAT NULL ++ RDS_NTIE TREAT NULL ++ RDS_PTIE TREAT NULL ++ RDS_TPOLY TREAT NULL ++ RDS_VPOLY TREAT NULL ++ RDS_NIMP TREAT NULL ++ RDS_PIMP TREAT NULL ++ RDS_TVIA4 TREAT NULL ++ RDS_TVIA3 TREAT NULL ++ RDS_ACTIV TREAT NULL ++ RDS_POLY TREAT NULL ++ RDS_CONT NOTREAT NULL ++ RDS_VIA1 NOTREAT NULL ++ RDS_VIA2 NOTREAT NULL ++ RDS_VIA3 NOTREAT NULL ++ RDS_VIA4 NOTREAT NULL ++ RDS_VIA5 NOTREAT NULL ++ RDS_POLY2 TREAT NULL ++ RDS_ALU1 TREAT NULL ++ RDS_ALU2 TREAT NULL ++ RDS_ALU3 TREAT NULL ++ RDS_ALU4 TREAT NULL ++ RDS_ALU5 TREAT NULL ++ RDS_ALU6 TREAT NULL ++ RDS_TALU1 TREAT NULL ++ RDS_TALU2 TREAT NULL ++ RDS_TALU3 TREAT NULL ++ RDS_TALU4 TREAT NULL ++ RDS_TALU5 TREAT NULL ++ RDS_TALU6 TREAT NULL ++ ++# Two RDS_TALU8 rectangles are written, one with no name and ++# one with the cell name. When merged, the name is lost. ++# It is prefered to have a single rectangle with no name rather ++# than two, one of which is named. ++ RDS_TALU8 TREAT NULL ++ ++END ++ ++##------------------------------------------------------------------- ++## All layers used in the regles must be listed here first. ++## Otherwise you get an error like : ++# DRUC ERR: Undefined RDS LAYER ++##------------------------------------------------------------------- ++DRC_RULES ++ ++layer RDS_USER0 0.27; ++layer RDS_USER1 0.27; ++layer RDS_USER2 0.27; ++layer RDS_USER4 0.27; ++layer RDS_USER5 0.27; ++layer RDS_NWELL 1.08; ++layer RDS_PWELL 1.08; ++layer RDS_NTIE 0.27; ++layer RDS_PTIE 0.27; ++layer RDS_NDIF 0.27; ++layer RDS_PDIF 0.27; ++layer RDS_TPOLY 0.27; ++layer RDS_VPOLY 0.27; ++layer RDS_ACTIV 0.27; ++layer RDS_PIMP 0.45; ++layer RDS_NIMP 0.45; ++layer RDS_CONT 0.18; ++layer RDS_VIA1 0.27; ++layer RDS_VIA2 0.27; ++layer RDS_VIA3 0.27; ++layer RDS_VIA4 0.27; ++layer RDS_VIA5 0.36; ++layer RDS_POLY 0.18; ++layer RDS_GATE 0.18; ++layer RDS_ALU1 0.27; ++layer RDS_ALU2 0.27; ++layer RDS_ALU3 0.27; ++layer RDS_ALU4 0.27; ++layer RDS_ALU5 0.27; ++layer RDS_ALU6 0.45; ++ ++layer RDS_REF 0.20; ++layer RDS_TALU1 0.27; ++layer RDS_TALU2 0.27; ++layer RDS_TALU3 0.27; ++layer RDS_TALU4 0.27; ++layer RDS_TALU5 0.27; ++layer RDS_TALU6 0.45; ++layer RDS_TALU8 3.96; ++layer RDS_POLY2 0.27; ++layer RDS_VALU2 0.27; ++layer RDS_VALU3 0.27; ++layer RDS_VALU4 0.27; ++layer RDS_VALU5 0.27; ++layer RDS_VALU6 0.45; ++ ++regles ++ ++# Note : ``min'' is different from ``>=''. ++# min is applied on polygons and >= is applied on rectangles. ++# There is the same difference between max and <=. ++# >= is faster than min, but min must be used where it is ++# required to consider polygons, for example distance of ++# two objects in the same layer ++#----------------------------------------------------------- ++# Check the NWELL shapes ++#----------------------- ++caracterise RDS_NWELL ( ++ regle 110 : largeur >= 1.08 ; ++ regle 111 : longueur_inter min 1.08 ; ++ regle 130 : notch >= 1.08 ; ++); ++relation RDS_NWELL , RDS_NWELL ( ++ regle 131 : distance axiale min 0.54 ; ++); ++ ++# Check the PWELL shapes ++#----------------------- ++caracterise RDS_PWELL ( ++ regle 112 : largeur >= 1.08 ; ++ regle 113 : longueur_inter min 1.08 ; ++ regle 132 : notch >= 1.08 ; ++); ++relation RDS_PWELL , RDS_PWELL ( ++ regle 133 : distance axiale min 0.54 ; ++); ++ ++define RDS_NWELL , RDS_PWELL intersection -> BOTH_WELLS; ++ ++# Check no NWELL and PWELL overlap ++#--------------------------------- ++# Won't work with PWELL made from symbolic NWELL ++caracterise BOTH_WELLS ( ++ regle 140 : largeur max 0.0 ; ++); ++relation RDS_PWELL , RDS_NWELL ( ++ regle 141 : distance axiale min 0.0 ; ++); ++ ++undefine BOTH_WELLS; ++ ++# Check the RDS_PDIF shapes ++#-------------------------- ++caracterise RDS_PDIF ( ++ regle 210 : largeur >= 0.27 ; ++ regle 211 : longueur_inter min 0.27 ; ++ regle 220 : notch >= 0.27 ; ++); ++relation RDS_PDIF , RDS_PDIF ( ++ regle 221 : distance axiale min 0.27 ; ++); ++ ++# Check the RDS_NDIF shapes ++#-------------------------- ++caracterise RDS_NDIF ( ++ regle 212 : largeur >= 0.27 ; ++ regle 213 : longueur_inter min 0.27 ; ++ regle 222 : notch >= 0.27 ; ++); ++relation RDS_NDIF , RDS_NDIF ( ++ regle 223 : distance axiale min 0.27 ; ++); ++ ++# define PSUB and NSUB layers for easier ++# understanding of design rules ++define RDS_VPOLY , RDS_PTIE intersection -> PSUB; ++define RDS_TPOLY , RDS_NTIE intersection -> NSUB; ++ ++# Check the RDS_PTIE shapes ++#-------------------------- ++caracterise PSUB ( ++ regle 214 : largeur >= 0.27 ; ++ regle 215 : longueur_inter min 0.27 ; ++ regle 224 : notch >= 0.27 ; ++); ++relation PSUB , PSUB ( ++ regle 225 : distance axiale min 0.27 ; ++); ++ ++# Check the RDS_NTIE shapes ++#-------------------------- ++caracterise NSUB ( ++ regle 216 : largeur >= 0.27 ; ++ regle 217 : longueur_inter min 0.27 ; ++ regle 226 : notch >= 0.27 ; ++); ++relation NSUB , NSUB ( ++ regle 227 : distance axiale min 0.27 ; ++); ++ ++# Check RDS_NDIF is outside NWELL ++#-------------------------------- ++relation RDS_NDIF , RDS_NWELL ( ++ regle 230 : distance axiale >= 0.54 ; ++ regle 231 : enveloppe longueur_inter < 0.0 ; ++ regle 232 : croix longueur_inter < 0.0 ; ++ regle 233 : intersection longueur_inter < 0.0 ; ++ regle 234 : extension longueur_inter < 0.0 ; ++ regle 235 : inclusion longueur_inter < 0.0 ; ++); ++relation RDS_NWELL , RDS_NDIF ( ++ regle 236 : marge longueur_inter < 0.0 ; ++); ++ ++# Check RDS_PDIF is inside NWELL ++#------------------------------- ++relation RDS_NWELL , RDS_PDIF ( ++ regle 237 : enveloppe inferieure min 0.54 ; ++); ++ ++# Check RDS_PTIE is outside NWELL ++#-------------------------------- ++relation PSUB , RDS_NWELL ( ++ regle 240 : distance axiale >= 0.27 ; ++ regle 241 : enveloppe longueur_inter < 0.0 ; ++ regle 242 : croix longueur_inter < 0.0 ; ++ regle 243 : intersection longueur_inter < 0.0 ; ++ regle 244 : extension longueur_inter < 0.0 ; ++ regle 245 : inclusion longueur_inter < 0.0 ; ++); ++relation RDS_NWELL , PSUB ( ++ regle 246 : marge longueur_inter < 0.0 ; ++); ++ ++# Check RDS_NTIE is inside NWELL ++#------------------------------- ++relation RDS_NWELL , NSUB ( ++ regle 247 : enveloppe inferieure min 0.27 ; ++); ++ ++# Check NDIF and PDIF separation ++#------------------------------- ++relation RDS_NDIF , PSUB ( ++ regle 250 : distance axiale min 0.36 ; ++ regle 251 : intersection longueur_inter < 0.0 ; ++ regle 252 : extension longueur_inter < 0.0 ; ++ regle 253 : inclusion longueur_inter < 0.0 ; ++); ++relation RDS_PDIF , NSUB ( ++ regle 254 : distance axiale min 0.36 ; ++ regle 255 : intersection longueur_inter < 0.0 ; ++ regle 256 : extension longueur_inter < 0.0 ; ++ regle 257 : inclusion longueur_inter < 0.0 ; ++); ++ ++# Check RDS_PDIF is outside PWELL ++#--------------------------------- ++relation RDS_PDIF , RDS_PWELL ( ++ regle 260 : distance axiale >= 0.54 ; ++ regle 261 : enveloppe longueur_inter < 0.0 ; ++ regle 262 : croix longueur_inter < 0.0 ; ++ regle 263 : intersection longueur_inter < 0.0 ; ++ regle 264 : extension longueur_inter < 0.0 ; ++ regle 265 : inclusion longueur_inter < 0.0 ; ++); ++relation RDS_PWELL , RDS_PDIF ( ++ regle 266 : marge longueur_inter < 0.0 ; ++); ++ ++# Check RDS_NDIF is inside PWELL ++#------------------------------- ++relation RDS_PWELL , RDS_NDIF ( ++ regle 267 : enveloppe inferieure min 0.54 ; ++); ++ ++# Check RDS_NTIE is outside PWELL ++#-------------------------------- ++relation NSUB , RDS_PWELL ( ++ regle 270 : distance axiale >= 0.27 ; ++ regle 271 : enveloppe longueur_inter < 0.0 ; ++ regle 272 : croix longueur_inter < 0.0 ; ++ regle 273 : intersection longueur_inter < 0.0 ; ++ regle 274 : extension longueur_inter < 0.0 ; ++ regle 275 : inclusion longueur_inter < 0.0 ; ++); ++relation RDS_PWELL , NSUB ( ++ regle 276 : marge longueur_inter < 0.0 ; ++); ++ ++# Check RDS_PTIE is inside PWELL ++#------------------------------- ++relation RDS_PWELL , PSUB ( ++ regle 277 : enveloppe inferieure min 0.27 ; ++); ++ ++# Check opposite implant diffusion spacings ++#------------------------------------------ ++# These rules added to flag DRC errors even if ++# NWELL and PWELL are not visualised in Graal ++#--------------------------------------------- ++relation RDS_PDIF , RDS_NDIF ( ++# distance is nwell overlap pdif plus nwell space to ndif ++ regle 280 : distance axiale min 1.08 ; ++); ++relation RDS_PDIF , PSUB ( ++# distance is nwell overlap pdif plus nwell space to ptie ++ regle 281 : distance axiale min 0.81 ; ++); ++relation NSUB , RDS_NDIF ( ++# distance is nwell overlap ntie plus nwell space to ndif ++ regle 282 : distance axiale min 0.81 ; ++); ++# distance is nwell overlap ntie plus nwell space to ptie ++relation NSUB , PSUB ( ++ regle 283 : distance axiale min 0.54 ; ++); ++ ++define RDS_ACTIV , RDS_POLY intersection -> CHANNEL; ++ ++# Check the RDS_POLY shapes ++#-------------------------- ++caracterise RDS_POLY ( ++ regle 310 : largeur >= 0.18 ; ++ regle 311 : longueur_inter >= 0.18 ; ++ regle 320 : notch >= 0.27 ; ++); ++relation RDS_POLY , RDS_POLY ( ++ regle 321 : distance axiale min 0.27 ; ++); ++ ++# Check the CHANNEL shapes ++#-------------------------- ++caracterise CHANNEL ( ++ regle 322 : notch >= 0.27 ; ++); ++relation CHANNEL , CHANNEL ( ++ regle 323 : distance axiale min 0.27 ; ++); ++ ++# Check POLY overlap of TRANSISTOR (ENDCAP) ++#------------------------------------------ ++relation RDS_POLY , RDS_PDIF ( ++ regle 330 : croix longueur_min min 0.225 ; ++); ++relation RDS_POLY , RDS_NDIF ( ++ regle 331 : croix longueur_min min 0.225 ; ++); ++ ++# Check SOURCE/DRAIN width ++#------------------------- ++relation RDS_PDIF , RDS_GATE ( ++ regle 340 : croix longueur_min min 0.36 ; ++); ++relation RDS_NDIF , RDS_GATE ( ++ regle 341 : croix longueur_min min 0.36 ; ++); ++ ++# Check RDS_POLY separation to DIF ++#--------------------------------- ++relation RDS_POLY , RDS_PDIF ( ++ regle 350 : distance axiale min 0.09 ; ++); ++relation RDS_POLY , RDS_NDIF ( ++ regle 351 : distance axiale min 0.09 ; ++); ++relation RDS_POLY , PSUB ( ++ regle 352 : distance axiale min 0.09 ; ++); ++relation RDS_POLY , NSUB ( ++ regle 353 : distance axiale min 0.09 ; ++); ++ ++# Check RDS_POLY separation to TRANSISTOR CHANNEL ++#------------------------------------------------ ++relation RDS_POLY , CHANNEL ( ++ regle 354 : distance axiale >= 0.09 ; ++); ++ ++undefine NSUB; ++undefine PSUB; ++define RDS_POLY , CHANNEL exclusion -> FIELD_POLY; ++define RDS_PDIF , RDS_POLY intersection -> PGATE; ++ ++# Check RDS_POLY does not overlap PDIF ++#------------------------------------- ++relation PGATE , FIELD_POLY ( ++ regle 355 : inclusion longueur_inter < 0.0 ; ++); ++relation FIELD_POLY , PGATE ( ++ regle 356 : extension longueur_inter < 0.0 ; ++); ++ ++undefine PGATE; ++define RDS_NDIF , RDS_POLY intersection -> NGATE; ++ ++# Check RDS_POLY does not overlap NDIF ++#------------------------------------- ++relation NGATE , FIELD_POLY ( ++ regle 357 : inclusion longueur_inter < 0.0 ; ++); ++relation FIELD_POLY , NGATE ( ++ regle 358 : extension longueur_inter < 0.0 ; ++); ++ ++undefine NGATE; ++define RDS_PDIF , CHANNEL intersection -> PTR; ++ ++# N-select and P-select rules ++#---------------------------- ++relation PTR , RDS_NIMP ( ++ regle 410 : distance axiale min 0.27 ; ++); ++ ++undefine PTR; ++define RDS_NDIF , CHANNEL intersection -> NTR; ++ ++relation NTR , RDS_PIMP ( ++ regle 411 : distance axiale min 0.27 ; ++); ++ ++undefine NTR; ++undefine FIELD_POLY; ++define RDS_VPOLY , RDS_PTIE intersection -> PSUB; ++define RDS_TPOLY , RDS_NTIE intersection -> NSUB; ++ ++relation RDS_PIMP , RDS_PDIF ( ++ regle 420 : enveloppe inferieure min 0.18 ; ++); ++relation RDS_PIMP , PSUB ( ++ regle 421 : enveloppe inferieure min 0.18 ; ++); ++relation RDS_NIMP , RDS_NDIF ( ++ regle 422 : enveloppe inferieure min 0.18 ; ++); ++relation RDS_NIMP , NSUB ( ++ regle 423 : enveloppe inferieure min 0.18 ; ++); ++ ++undefine NSUB; ++undefine PSUB; ++define RDS_PIMP , RDS_PWELL intersection -> TIE_PIMP; ++define RDS_NIMP , RDS_NWELL intersection -> TIE_NIMP; ++ ++# Check min SELECT widths for TIE implant ++#---------------------------------------- ++caracterise TIE_PIMP ( ++ regle 440 : largeur >= 0.36 ; ++ regle 441 : longueur_inter min 0.36 ; ++); ++# This is the min NIMP width rule ++relation TIE_PIMP , TIE_PIMP ( ++ regle 444 : distance axiale min 0.36 ; ++); ++caracterise TIE_NIMP ( ++ regle 442 : largeur >= 0.36 ; ++ regle 443 : longueur_inter min 0.36 ; ++); ++# This is the min PIMP width rule ++relation TIE_NIMP , TIE_NIMP ( ++ regle 445 : distance axiale min 0.36 ; ++); ++ ++undefine TIE_NIMP; ++undefine TIE_PIMP; ++define RDS_POLY , RDS_CONT intersection -> POLY_CONT; ++ ++# Check CONT layer size, separation and overlaps ++#----------------------------------------------- ++caracterise POLY_CONT ( ++ regle 510 : largeur max 0.185 ; ++ regle 511 : largeur min 0.18 ; ++); ++relation RDS_POLY , RDS_CONT ( ++ regle 520 : enveloppe inferieure min 0.09 ; ++); ++relation RDS_CONT , RDS_CONT ( ++ regle 530 : distance axiale min 0.36 ; ++); ++ ++# Check POLY CONTACT separation from TRANSISTOR CHANNEL ++#------------------------------------------------------ ++relation CHANNEL , POLY_CONT ( ++ regle 540 : distance axiale >= 0.27 ; ++); ++ ++undefine POLY_CONT; ++define RDS_CONT , CHANNEL intersection -> BAD_CONT; ++ ++# CONTACT not allowed over TRANSISTOR ++#------------------------------------ ++caracterise BAD_CONT ( ++ regle 580 : largeur max 0.0 ; ++); ++ ++undefine BAD_CONT; ++ ++define RDS_PDIF , RDS_CONT intersection -> PDIF_CONT; ++caracterise PDIF_CONT ( ++ regle 610 : longueur max 0.185 ; ++ regle 611 : longueur_inter min 0.18 ; ++); ++# Check PDIF CONTACT separation from TRANSISTOR CHANNEL ++#------------------------------------------------------ ++relation CHANNEL , PDIF_CONT ( ++ regle 640 : distance axiale >= 0.18 ; ++); ++ ++undefine PDIF_CONT; ++define RDS_NDIF , RDS_CONT intersection -> NDIF_CONT; ++ ++caracterise NDIF_CONT ( ++ regle 612 : longueur max 0.185 ; ++ regle 613 : longueur_inter min 0.18 ; ++); ++# Check NDIF CONTACT separation from TRANSISTOR CHANNEL ++#------------------------------------------------------ ++relation CHANNEL , NDIF_CONT ( ++ regle 641 : distance axiale >= 0.18 ; ++); ++ ++undefine NDIF_CONT; ++define RDS_PTIE , RDS_CONT intersection -> PTIE_CONT; ++caracterise PTIE_CONT ( ++ regle 614 : longueur max 0.185 ; ++ regle 615 : longueur_inter min 0.18 ; ++); ++# Check PTIE CONTACT separation from TRANSISTOR CHANNEL ++#------------------------------------------------------ ++relation CHANNEL , PTIE_CONT ( ++ regle 642 : distance axiale >= 0.27 ; ++); ++ ++undefine PTIE_CONT; ++define RDS_NTIE , RDS_CONT intersection -> NTIE_CONT; ++ ++caracterise NTIE_CONT ( ++ regle 616 : longueur max 0.185 ; ++ regle 617 : longueur_inter min 0.18 ; ++); ++# Check NTIE CONTACT separation from TRANSISTOR CHANNEL ++#------------------------------------------------------ ++relation CHANNEL , NTIE_CONT ( ++ regle 643 : distance axiale >= 0.27 ; ++); ++ ++undefine NTIE_CONT; ++ ++relation RDS_PDIF , RDS_CONT ( ++ regle 620 : enveloppe inferieure min 0.09 ; ++); ++relation RDS_NDIF , RDS_CONT ( ++ regle 621 : enveloppe inferieure min 0.09 ; ++); ++relation RDS_PTIE , RDS_CONT ( ++ regle 622 : enveloppe inferieure min 0.09 ; ++); ++relation RDS_NTIE , RDS_CONT ( ++ regle 623 : enveloppe inferieure min 0.09 ; ++); ++ ++undefine CHANNEL; ++define RDS_ALU1 , RDS_POLY2 union -> ANY_ALU1; ++ ++# Check RDS_ALU1 shapes ++#---------------------- ++caracterise RDS_ALU1 ( ++ regle 710 : largeur >= 0.27 ; ++ regle 711 : longueur_inter min 0.27 ; ++); ++caracterise ANY_ALU1 ( ++ regle 720 : notch >= 0.27 ; ++); ++caracterise RDS_POLY2 ( ++ regle 712 : largeur >= 0.27 ; ++ regle 713 : longueur_inter min 0.27 ; ++ regle 721 : notch >= 0.27 ; ++); ++caracterise RDS_TALU1 ( ++ regle 714 : largeur >= 0.27 ; ++ regle 715 : longueur_inter min 0.27 ; ++ regle 722 : notch >= 0.27 ; ++); ++relation ANY_ALU1 , ANY_ALU1 ( ++ regle 723 : distance axiale min 0.27 ; ++); ++relation RDS_ALU1 , RDS_ALU1 ( ++ regle 724 : distance axiale min 0.27 ; ++); ++relation RDS_TALU1 , RDS_TALU1 ( ++ regle 725 : distance axiale min 0.27 ; ++); ++ ++# Check ALU1 side overlap of CONT ++#-------------------------------- ++relation ANY_ALU1 , RDS_CONT ( ++# Case where ALU1 overlap of CONT is positive but less than design rule ++ regle 730 : enveloppe inferieure min 0.09 ; ++); ++ ++define ANY_ALU1 , RDS_USER2 union -> WIDE_ALU1; ++define WIDE_ALU1 , RDS_USER1 intersection -> THIN_ALU1; ++undefine WIDE_ALU1; ++ ++relation THIN_ALU1 , RDS_CONT ( ++# Case where ALU1 is 2 lambda wide ++# Side overlap rule used for end overlap ++ regle 733 : croix longueur_min min 0.09 ; ++# Optional larger value of end overlap ++ regle 734 : croix longueur_min min 0.09 ; ++); ++ ++undefine THIN_ALU1; ++#define ANY_ALU1 , RDS_USER0 intersection -> THIN_ALU1; ++ ++#relation THIN_ALU1 , RDS_CONT ( ++# Case where ALU1 is 1 lambda wide ++# Side overlap rule used for end overlap ++# regle 735 : croix longueur_min min 0.01 ; ++# Optional larger value of end overlap ++# regle 736 : croix longueur_min min 0.06 ; ++#); ++ ++#undefine THIN_ALU1; ++define ANY_ALU1 , RDS_USER5 union -> WIDE_ALU1; ++define WIDE_ALU1 , RDS_USER4 intersection -> THIN_ALU1; ++ ++# Check REF size and RDS_ALU1 overlap of REF ++#------------------------------------------- ++#caracterise RDS_REF ( ++# regle 750 : largeur max 0.205 ; ++# regle 751 : largeur min 0.20 ; ++#); ++#relation RDS_REF , RDS_REF ( ++# regle 760 : distance axiale min 0.24 ; ++#); ++#relation RDS_REF , RDS_ALU1 ( ++# regle 770 : intersection longueur_inter max 0.0 ; ++#); ++#relation RDS_REF ,RDS_TALU1 ( ++# regle 772 : intersection longueur_inter max 0.0 ; ++#); ++#relation RDS_ALU1 , RDS_REF ( ++# regle 773 : enveloppe inferieure min 0.01 ; ++# regle 774 : marge longueur_inter max 0.01 ; ++#); ++#relation RDS_TALU1 , RDS_REF ( ++# regle 775 : enveloppe inferieure min 0.01 ; ++# regle 776 : marge longueur_inter max 0.01 ; ++#); ++#relation THIN_ALU1 , RDS_REF ( ++# regle 780 : croix longueur_min min 0.01 ; ++# regle 781 : croix longueur_min min 0.06 ; ++#); ++ ++# Check VIA layer size and separation ++#------------------------------------ ++caracterise RDS_VIA1 ( ++ regle 810 : largeur <= 0.275 ; ++ regle 811 : largeur >= 0.27 ; ++); ++relation RDS_VIA1 , RDS_VIA1 ( ++ regle 820 : distance axiale min 0.27 ; ++); ++ ++# Check ALU1 overlap of VIA1 ++#--------------------------- ++relation RDS_ALU1 , RDS_VIA1 ( ++# Case 1: side overlap ++# Basic side overlap checked on all sides ++ regle 830 : enveloppe inferieure min 0.09 ; ++ regle 831 : marge longueur_inter max 0.09 ; ++); ++#relation RDS_VIA1 , RDS_ALU1 ( ++# regle 832 : intersection longueur_inter max 0.0 ; ++#); ++ ++relation THIN_ALU1 , RDS_VIA1 ( ++# Case 2: end overlap ++# Side overlap rule used for end overlap ++ regle 833 : croix longueur_min min 0.09 ; ++# Optional larger value of end overlap ++ regle 834 : croix longueur_min min 0.09 ; ++); ++ ++undefine WIDE_ALU1; ++undefine THIN_ALU1; ++undefine ANY_ALU1; ++ ++# Check RDS_ALU2 shapes ++#---------------------- ++caracterise RDS_ALU2 ( ++ regle 910 : largeur >= 0.27 ; ++ regle 911 : longueur_inter min 0.27 ; ++ regle 920 : notch >= 0.36 ; ++); ++relation RDS_ALU2 , RDS_ALU2 ( ++ regle 921 : distance axiale min 0.36 ; ++); ++# Check ALU2 overlap of VIA1 ++#--------------------------- ++relation RDS_ALU2 , RDS_VIA1 ( ++# Case 1: side overlap ++# Basic side overlap checked on all sides ++ regle 930 : enveloppe inferieure min 0.09 ; ++ regle 931 : marge longueur_inter max 0.09 ; ++); ++#relation RDS_VIA1 , RDS_ALU2 ( ++# regle 932 : intersection longueur_inter max 0.0 ; ++#); ++ ++define RDS_ALU2 , RDS_TALU2 union -> WIDE_ALU2; ++define WIDE_ALU2 , RDS_VALU2 intersection -> THIN_ALU2; ++ ++relation THIN_ALU2 , RDS_VIA1 ( ++# Case 2: end overlap ++# Side overlap rule used for end overlap ++ regle 933 : croix longueur_min min 0.09 ; ++# Optional larger value of end overlap ++ regle 934 : croix longueur_min min 0.09 ; ++); ++ ++# Check VIA2 layer size and separation ++#------------------------------------- ++caracterise RDS_VIA2 ( ++ regle 1410 : largeur <= 0.275 ; ++ regle 1411 : largeur >= 0.27 ; ++); ++relation RDS_VIA2 , RDS_VIA2 ( ++ regle 1420 : distance axiale min 0.27 ; ++); ++ ++# Check ALU2 overlap of VIA2 ++#--------------------------- ++relation RDS_ALU2 , RDS_VIA2 ( ++# Case 1: side overlap ++# Basic side overlap checked on all sides ++ regle 1430 : enveloppe inferieure min 0.09 ; ++ regle 1431 : marge longueur_inter max 0.09 ; ++); ++#relation RDS_VIA2 , RDS_ALU2 ( ++# regle 1432 : intersection longueur_inter max 0.0 ; ++#); ++ ++relation THIN_ALU2 , RDS_VIA2 ( ++# Case 2: end overlap ++# Side overlap rule used for end overlap ++ regle 1433 : croix longueur_min min 0.09 ; ++# Optional larger value of end overlap ++ regle 1434 : croix longueur_min min 0.09 ; ++); ++ ++undefine WIDE_ALU2; ++undefine THIN_ALU2; ++ ++# Check RDS_ALU3 shapes ++#---------------------- ++caracterise RDS_ALU3 ( ++ regle 1510 : largeur >= 0.27 ; ++ regle 1511 : longueur_inter min 0.27 ; ++ regle 1520 : notch >= 0.36 ; ++); ++relation RDS_ALU3 , RDS_ALU3 ( ++ regle 1521 : distance axiale min 0.27 ; ++); ++# Check ALU3 overlap of VIA2 ++#--------------------------- ++relation RDS_ALU3 , RDS_VIA2 ( ++# Case 1: side overlap ++# Basic side overlap checked on all sides ++ regle 1530 : enveloppe inferieure min 0.09 ; ++ regle 1531 : marge longueur_inter max 0.09 ; ++); ++#relation RDS_VIA2 , RDS_ALU3 ( ++# regle 1532 : intersection longueur_inter max 0.0 ; ++#); ++ ++define RDS_ALU3 , RDS_TALU3 union -> WIDE_ALU3; ++define WIDE_ALU3 , RDS_VALU3 intersection -> THIN_ALU3; ++ ++relation THIN_ALU3 , RDS_VIA2 ( ++# Case 2: end overlap ++# Side overlap rule used for end overlap ++ regle 1533 : croix longueur_min min 0.09 ; ++# Optional larger value of end overlap ++ regle 1534 : croix longueur_min min 0.09 ; ++); ++ ++# Check VIA3 layer size and separation ++#------------------------------------- ++caracterise RDS_VIA3 ( ++ regle 2110 : largeur <= 0.275 ; ++ regle 2111 : largeur >= 0.27 ; ++); ++relation RDS_VIA3 , RDS_VIA3 ( ++ regle 2120 : distance axiale min 0.27 ; ++); ++ ++# Check ALU3 overlap of VIA3 ++#--------------------------- ++relation RDS_ALU3 , RDS_VIA3 ( ++# Case 1: side overlap ++# Basic side overlap checked on all sides ++ regle 2130 : enveloppe inferieure min 0.09 ; ++ regle 2131 : marge longueur_inter max 0.09 ; ++); ++#relation RDS_VIA3 , RDS_ALU3 ( ++# regle 2132 : intersection longueur_inter max 0.0 ; ++#); ++ ++relation THIN_ALU3 , RDS_VIA3 ( ++# Case 2: end overlap ++# Side overlap rule used for end overlap ++ regle 2133 : croix longueur_min min 0.09 ; ++# Optional larger value of end overlap ++ regle 2134 : croix longueur_min min 0.09 ; ++); ++ ++undefine WIDE_ALU3; ++undefine THIN_ALU3; ++ ++# Check RDS_ALU4 shapes ++#---------------------- ++caracterise RDS_ALU4 ( ++ regle 2210 : largeur >= 0.27 ; ++ regle 2211 : longueur_inter min 0.27 ; ++ regle 2220 : notch >= 0.36 ; ++); ++relation RDS_ALU4 , RDS_ALU4 ( ++ regle 2221 : distance axiale min 0.36 ; ++); ++# Check ALU4 overlap of VIA3 ++#--------------------------- ++relation RDS_ALU4 , RDS_VIA3 ( ++# Case 1: side overlap ++# Basic side overlap checked on all sides ++ regle 2230 : enveloppe inferieure min 0.09 ; ++ regle 2231 : marge longueur_inter max 0.09 ; ++); ++#relation RDS_VIA3 , RDS_ALU4 ( ++# regle 2232 : intersection longueur_inter max 0.0 ; ++#); ++ ++define RDS_ALU4 , RDS_TALU4 union -> WIDE_ALU4; ++define WIDE_ALU4 , RDS_VALU4 intersection -> THIN_ALU4; ++ ++relation THIN_ALU4 , RDS_VIA3 ( ++# Case 2: end overlap ++# Side overlap rule used for end overlap ++ regle 2233 : croix longueur_min min 0.09 ; ++# Optional larger value of end overlap ++ regle 2234 : croix longueur_min min 0.09 ; ++); ++ ++# Check VIA4 layer size and separation ++#------------------------------------- ++caracterise RDS_VIA4 ( ++ regle 2510 : largeur <= 0.275 ; ++ regle 2511 : largeur >= 0.27 ; ++); ++relation RDS_VIA4 , RDS_VIA4 ( ++ regle 2520 : distance axiale min 0.27 ; ++); ++ ++# Check ALU4 overlap of VIA4 ++#--------------------------- ++relation RDS_ALU4 , RDS_VIA4 ( ++# Case 1: side overlap ++# Basic side overlap checked on all sides ++ regle 2530 : enveloppe inferieure min 0.09 ; ++ regle 2531 : marge longueur_inter max 0.09 ; ++); ++#relation RDS_VIA4 , RDS_ALU4 ( ++# regle 2532 : intersection longueur_inter max 0.0 ; ++#); ++ ++relation THIN_ALU4 , RDS_VIA4 ( ++# Case 2: end overlap ++# Side overlap rule used for end overlap ++ regle 2533 : croix longueur_min min 0.09 ; ++# Optional larger value of end overlap ++ regle 2534 : croix longueur_min min 0.09 ; ++); ++ ++undefine WIDE_ALU4; ++undefine THIN_ALU4; ++ ++# Check RDS_ALU5 shapes ++#---------------------- ++caracterise RDS_ALU5 ( ++ regle 2610 : largeur >= 0.27 ; ++ regle 2611 : longueur_inter min 0.27 ; ++ regle 2620 : notch >= 0.36 ; ++); ++relation RDS_ALU5 , RDS_ALU5 ( ++ regle 2621 : distance axiale min 0.36 ; ++); ++# Check ALU5 overlap of VIA4 ++#--------------------------- ++relation RDS_ALU5 , RDS_VIA4 ( ++# Case 1: side overlap ++# Basic side overlap checked on all sides ++ regle 2630 : enveloppe inferieure min 0.09 ; ++ regle 2631 : marge longueur_inter max 0.09 ; ++); ++#relation RDS_VIA4 , RDS_ALU5 ( ++# regle 2632 : intersection longueur_inter max 0.0 ; ++#); ++ ++define RDS_ALU5 , RDS_TALU5 union -> WIDE_ALU5; ++define WIDE_ALU5 , RDS_VALU5 intersection -> THIN_ALU5; ++ ++relation THIN_ALU5 , RDS_VIA4 ( ++# Case 2: end overlap ++# Side overlap rule used for end overlap ++ regle 2633 : croix longueur_min min 0.09 ; ++# Optional larger value of end overlap ++ regle 2634 : croix longueur_min min 0.09 ; ++); ++ ++# VIA5 and ALU6 width and spacings ++# larger than lower layers ++#------------------------------------- ++caracterise RDS_VIA5 ( ++ regle 2910 : largeur <= 0.365 ; ++ regle 2911 : largeur >= 0.36 ; ++); ++relation RDS_VIA5 , RDS_VIA5 ( ++ regle 2920 : distance axiale min 0.36 ; ++); ++ ++# Check ALU5 overlap of VIA5 ++#--------------------------- ++relation RDS_ALU5 , RDS_VIA5 ( ++# Case 1: side overlap ++# Basic side overlap checked on all sides ++ regle 2930 : enveloppe inferieure min 0.09 ; ++ regle 2931 : marge longueur_inter max 0.09 ; ++); ++#relation RDS_VIA5 , RDS_ALU5 ( ++# regle 2932 : intersection longueur_inter max 0.0 ; ++#); ++ ++relation THIN_ALU5 , RDS_VIA5 ( ++# Case 2: end overlap ++# Side overlap rule used for end overlap ++ regle 2933 : croix longueur_min min 0.09 ; ++# Optional larger value of end overlap ++ regle 2934 : croix longueur_min min 0.09 ; ++); ++ ++undefine WIDE_ALU5; ++undefine THIN_ALU5; ++ ++# Check RDS_ALU6 shapes ++#---------------------- ++caracterise RDS_ALU6 ( ++ regle 3010 : largeur >= 0.45 ; ++ regle 3011 : longueur_inter min 0.45 ; ++ regle 3020 : notch >= 0.45 ; ++); ++relation RDS_ALU6 , RDS_ALU6 ( ++ regle 3021 : distance axiale min 0.45 ; ++); ++# Check ALU6 overlap of VIA5 ++#--------------------------- ++relation RDS_ALU6 , RDS_VIA5 ( ++# Case 1: side overlap ++# Basic side overlap checked on all sides ++ regle 3030 : enveloppe inferieure min 0.18 ; ++ regle 3031 : marge longueur_inter max 0.18 ; ++); ++#relation RDS_VIA5 , RDS_ALU6 ( ++# regle 3032 : intersection longueur_inter max 0.0 ; ++#); ++ ++define RDS_ALU6 , RDS_TALU6 union -> WIDE_ALU6; ++define WIDE_ALU6 , RDS_VALU6 intersection -> THIN_ALU6; ++ ++relation THIN_ALU6 , RDS_VIA5 ( ++# Case 2: end overlap ++# Side overlap rule used for end overlap ++ regle 3033 : croix longueur_min min 0.18 ; ++# Optional larger value of end overlap ++ regle 3034 : croix longueur_min min 0.18 ; ++); ++ ++undefine WIDE_ALU6; ++undefine THIN_ALU6; ++define RDS_VPOLY , RDS_PTIE intersection -> PSUB; ++define RDS_TPOLY , RDS_NTIE intersection -> NSUB; ++ ++# Rule only applies if an AB in TALU8 has been manually ++# drawn around the cell ++# Check all layers half design rule inside layer AB ++#-------------------------------------------------- ++# Equals 4.4/2+4.2b = 0.24/2+0.04 = 0.16 ++#relation RDS_TALU8 , PSUB ( ++# regle 5010 : enveloppe inferieure min 0.16 ; ++#); ++#relation RDS_TALU8 , NSUB ( ++# regle 5011 : enveloppe inferieure min 0.16 ; ++#); ++# Equals 2.2/2 = 0.20/2 = 0.10 ++#relation RDS_TALU8 , RDS_PDIF ( ++# regle 5020 : enveloppe inferieure min 0.10 ; ++#); ++#relation RDS_TALU8 , RDS_NDIF ( ++# regle 5021 : enveloppe inferieure min 0.10 ; ++#); ++# Equals 3.2/2 = 0.20/2 = 0.10 ++#relation RDS_TALU8 , RDS_POLY ( ++# regle 5030 : enveloppe inferieure min 0.10 ; ++#); ++# Equals 7.2/2 = 0.22/2 = 0.11 ++#relation RDS_TALU8 , RDS_ALU1 ( ++# regle 5040 : enveloppe inferieure min 0.11 ; ++#); ++# Equals 7.2/2 = 0.18/2 = 0.09 ++#relation RDS_TALU8 , RDS_POLY2 ( ++# regle 5041 : enveloppe inferieure min 0.09 ; ++#); ++#relation RDS_TALU8 , RDS_REF ( ++# regle 5050 : enveloppe inferieure min 0.12 ; ++#); ++ ++undefine NSUB; ++undefine PSUB; ++ ++fin regles ++DRC_COMMENT ++110 1.1 NWELL Width < 1.08um ( 12 lambda) ++111 1.1 NWELL Width < 1.08um ( 12 lambda) ++112 1.1 PWELL Width < 1.08um ( 12 lambda) ++113 1.1 PWELL Width < 1.08um ( 12 lambda) ++130 1.3 NWELL Notch < 0.54um ( 6 lambda) ++131 1.3 NWELL Space < 0.54um ( 6 lambda) ++132 1.3 PWELL Notch < 0.54um ( 6 lambda) ++133 1.3 PWELL Space < 0.54um ( 6 lambda) ++140 1.4 NWELL and PWELL must not overlap (misaligned NWELL?) ++141 1.4 NWELL and PWELL Space < 0um ++210 2.1a PDIF Width < 0.27um ( 3 lambda) ++211 2.1a PDIF Width < 0.27um ( 3 lambda) ++220 2.2a PDIF Notch < 0.27um ( 3 lambda) ++221 2.2a PDIF Space < 0.27um ( 3 lambda) ++212 2.1a NDIF Width < 0.27um ( 3 lambda) ++213 2.1a NDIF Width < 0.27um ( 3 lambda) ++222 2.2a NDIF Notch < 0.27um ( 3 lambda) ++223 2.2a NDIF Space < 0.27um ( 3 lambda) ++214 2.1b PTIE Width < 0.27um ( 3 lambda) ++215 2.1b PTIE Width < 0.27um ( 3 lambda) ++224 2.2b PTIE Notch < 0.27um ( 3 lambda) ++225 2.2b PTIE Space < 0.27um ( 3 lambda) ++216 2.1b NTIE Width < 0.27um ( 3 lambda) ++217 2.1b NTIE Width < 0.27um ( 3 lambda) ++226 2.2b NTIE Notch < 0.27um ( 3 lambda) ++227 2.2b NTIE Space < 0.27um ( 3 lambda) ++230 2.3a NWELL to NDIF Space < 0.54um ( 6 lambda) ++231 2.3a NDIF must not touch NWELL ++232 2.3a NDIF must not touch NWELL ++233 2.3a NDIF must not touch NWELL ++234 2.3a NDIF must not touch NWELL ++235 2.3a NDIF must not touch NWELL ++236 2.3a NDIF must not touch NWELL ++237 2.3b NWELL Overlap of PDIF < 0.54um ( 6 lambda) ++240 2.4a NWELL to PTIE Space < 0.27um (3 lambda) ++241 2.4a PTIE must not touch NWELL ++242 2.4a PTIE must not touch NWELL ++243 2.4a PTIE must not touch NWELL ++244 2.4a PTIE must not touch NWELL ++245 2.4a PTIE must not touch NWELL ++246 2.4a PTIE must not touch NWELL ++247 2.4b NWELL Overlap of NTIE < 0.27um (3 lambda) ++250 2.5 NDIF to PTIE Space < 0.36um (4 lambda) ++251 2.5 NDIF must not touch or overlap PTIE ++252 2.5 NDIF must not touch or overlap PTIE ++253 2.5 NDIF must not touch or overlap PTIE ++254 2.5 PDIF to NTIE Space < 0.36um (4 lambda) ++255 2.5 PDIF must not touch or overlap NTIE ++256 2.5 PDIF must not touch or overlap NTIE ++257 2.5 PDIF must not touch or overlap NTIE ++260 2.3b PWELL to PDIF Space < 0.54um (6 lambda) ++261 2.3b PDIF must not touch PWELL ++262 2.3b PDIF must not touch PWELL ++263 2.3b PDIF must not touch PWELL ++264 2.3b PDIF must not touch PWELL ++265 2.3b PDIF must not touch PWELL ++266 2.3b PDIF must not touch PWELL ++267 2.3a PWELL Overlap of NDIF 0.54um (6 lambda) ++270 2.4b PWELL to NTIE Space 0.27um (3 lambda) ++271 2.4b NTIE must not touch PWELL ++272 2.4b NTIE must not touch PWELL ++273 2.4b NTIE must not touch PWELL ++274 2.4b NTIE must not touch PWELL ++275 2.4b NTIE must not touch PWELL ++276 2.4b NTIE must not touch PWELL ++277 2.4a PWELL Overlap of PTIE < 0.27um (3 lambda) ++280 2.8a PDIF to NDIF Space < 1.08um (12 lambda) ++281 2.8b PDIF to PTIE Space < 0.81um (9 lambda) ++282 2.8b NTIE to NDIF Space < 0.81um (9 lambda) ++283 2.8c NTIE to PTIE Space < 0.54um (6 lambda) ++310 3.1 POLY Width < 0.18um (2 lambda) ++311 3.1 POLY Width < 0.18um (2 lambda) ++320 3.2 POLY Notch < 0.27um (3 lambda) ++321 3.2 POLY Space < 0.27um (3 lambda) ++322 3.2a CHANNEL Space < 0.36um (4 lambda) ++323 3.2a CHANNEL Space < 0.36um (4 lambda) ++330 3.3 POLY Overlap of P-TRANSISTOR < 0.225um (2.5 lambda) ++331 3.3 POLY Overlap of N-TRANSISTOR < 0.225um (2.5 lambda) ++340 3.4 P-TRANSISTOR SOURCE/DRAIN Width < 0.36um (4 lambda) ++341 3.4 N-TRANSISTOR SOURCE/DRAIN Width < 0.36um (4 lambda) ++350 3.5 PDIF to POLY Space < 0.09um (1 lambda) ++351 3.5 NDIF to POLY Space < 0.09um (1 lambda) ++352 3.5 PTIE to POLY Space < 0.09um (1 lambda) ++353 3.5 NTIE to POLY Space < 0.09um (1 lambda) ++354 3.5a POLY to GATE Space < 0.09um (1 lambda) ++355 3.5 POLY must not touch or overlap PDIF ++356 3.5 POLY must not touch or overlap PDIF ++357 3.5 POLY must not touch or overlap NDIF ++358 3.5 POLY must not touch or overlap NDIF ++410 4.1 NIMP to P-TRANSISTOR Space < 0.27um (3 lambda) ++411 4.1 PIMP to N-TRANSISTOR Space < 0.27um (3 lambda) ++420 4.2a PIMP Overlap of PDIF < 0.18um (2 lambda) ++421 4.2b PIMP Overlap of PTIE < 0.18um (2 lambda) ++422 4.2a NIMP Overlap of NDIF < 0.18um (2 lambda) ++423 4.2b NIMP Overlap of NTIE < 0.18um (2 lambda) ++440 4.4 PIMP in PWELL Width < 0.36um (4 lambda) ++441 4.4 PIMP in PWELL Width < 0.36um (4 lambda) ++442 4.4 NIMP in NWELL Width < 0.36um (4 lambda) ++443 4.4 NIMP in NWELL Width < 0.36um (4 lambda) ++444 4.4 NIMP in PWELL Width < 0.36um (4 lambda) ++445 4.4 PIMP in NWELL Width < 0.36um (4 lambda) ++510 5.1 POLY CONTACT Width > 0.18um (2 lambda) ++511 5.1 POLY CONTACT Width < 0.18um (2 lambda) ++520 5.2 POLY Overlap of CONTACT < 0.135um (1.5 lambda) ++530 5.3 CONTACT Space < 0.36um (4 lambda) ++540 5.4 POLY CONTACT to CHANNEL Space < 0.18um (2 lambda) ++580 5.8 CONTACT not allowed over TRANSISTOR ++610 6.1 PDIF CONTACT Width > 0.18um (2 lambda) ++611 6.1 PDIF CONTACT Width < 0.18um (2 lambda) ++612 6.1 NDIF CONTACT Width > 0.18um (2 lambda) ++613 6.1 NDIF CONTACT Width < 0.18um (2 lambda) ++614 6.1 PTIE CONTACT Width > 0.18um (2 lambda) ++615 6.1 PTIE CONTACT Width < 0.18um (2 lambda) ++616 6.1 NTIE CONTACT Width > 0.18um (2 lambda) ++617 6.1 NTIE CONTACT Width < 0.18um (2 lambda) ++620 6.2a PDIF Overlap of CONT < 0.135um (1.5 lambda) ++621 6.2a NDIF Overlap of CONT < 0.135um (1.5 lambda) ++622 6.2b PTIE Overlap of CONT < 0.135um (1.5 lambda) ++623 6.2b NTIE Overlap of CONT < 0.135um (1.5 lambda) ++640 6.4 PDIF CONTACT to CHANNEL Space < 0.18um (2 lambda) ++641 6.4 NDIF CONTACT to CHANNEL Space < 0.18um (2 lambda) ++642 4.1+4.2b+6.2b PTIE CONTACT to CHANNEL Space < 0.585um (6.5 lambda) ++643 4.1+4.2b+6.2b NTIE CONTACT to CHANNEL Space < 0.585um (6.5 lambda) ++710 7.1 ALU1 Width < 0.27um (3 lambda) ++711 7.1 ALU1 Width < 0.27um (3 lambda) ++720 7.2 ALU1 Notch < 0.27um (3 lambda) ++712 7.1 ALU0 Width < 0.27um (3 lambda) ++713 7.1 ALU0 Width < 0.27um (3 lambda) ++721 7.2 ALU0 Notch < 0.27um (3 lambda) ++714 7.1 TALU1 Width < 0.27um (3 lambda) ++715 7.1 TALU1 Width < 0.27um (3 lambda) ++722 7.2 TALU1 Notch < 0.27um (3 lambda) ++723 7.2 ALU0 Space < 0.27um (3 lambda) ++724 7.2 ALU1 Space < 0.27um (3 lambda) ++725 7.2 TALU1 Space < 0.27um (3 lambda) ++730 7.3a ALU1 side Overlap of CONTACT < 0.09um (1 lambda) ++731 7.3a ALU1 side Overlap of CONTACT < 0.09um (1 lambda) ++732 7.3b ALU1 end Overlap of CONTACT <= 0.09um (1 lambda) ++733 7.3b ALU1 end Overlap of CONTACT < 0.09um (small) (1 lambda) ++734 7.3b ALU1 end Overlap of CONTACT < 0.09um (big) (1 lambda) ++735 7.3b ALU1 end Overlap of CONTACT < 0.09um (small) (1 lambda) ++736 7.3b ALU1 end Overlap of CONTACT < 0.09um (big) (1 lambda) ++750 7.5 REF Width > 0.27um (3 lambda) ++751 7.5 REF Width < 0.27um (3 lambda) ++760 7.6 REF Space < 0.27um (3 lambda) ++770 7.7 ALU1 must not touch or intersect REF ++772 7.7 TALU1 must not touch or intersect REF ++773 7.7 ALU1 Overlap of REF < 0.09um (1 lambda) ++774 7.7 ALU1 Overlap of REF < 0.09um (1 lambda) ++775 7.7 TALU1 Overlap of REF < 0.09um (1 lambda) ++776 7.7 TALU1 Overlap of REF < 0.09um (1 lambda) ++780 7.8 ALU1 end Overlap of REF < 0.09um (small) (1 lambda) ++781 7.8 ALU1 end Overlap of REF < 0.09um (big) (1 lambda) ++810 8.1 VIA1 Width > 0.27um (3 lambda) ++811 8.1 VIA1 Width < 0.27um (3 lambda) ++820 8.2 VIA1 Space < 0.27um (3 lambda) ++830 8.3a ALU1 side Overlap of VIA1 < 0.09um (1 lambda) ++831 8.3a ALU1 side Overlap of VIA1 < 0.09um (1 lambda) ++832 8.3 ALU1 must not touch or intersect VIA1 ++833 8.3b ALU1 end Overlap of VIA1 < 0.09um (small) (1 lambda) ++834 8.3b ALU1 end Overlap of VIA1 < 0.09um (big) (1 lambda) ++910 9.1 ALU2 Width < 0.27um (3 lambda) ++911 9.1 ALU2 Width < 0.27um (3 lambda) ++920 9.2 ALU2 Notch < 0.36um (4 lambda) ++921 9.2 ALU2 Space < 0.36um (4 lambda) ++930 9.3a ALU2 side Overlap of VIA1 < 0.09um (1 lambda) ++931 9.3a ALU2 side Overlap of VIA1 < 0.09um (1 lambda) ++932 9.3 ALU2 must not touch or intersect VIA1 ++933 9.3b ALU2 end Overlap of VIA1 < 0.09um (small) (1 lambda) ++934 9.3b ALU2 end Overlap of VIA1 < 0.09um (big) (1 lambda) ++1410 14.1 VIA2 Width > 0.27um (3 lambda) ++1411 14.1 VIA2 Width < 0.27um (3 lambda) ++1420 14.2 VIA2 Space < 0.36um (4 lambda) ++1430 14.3a ALU2 side Overlap of VIA2 < 0.09um (1 lambda) ++1431 14.3a ALU2 side Overlap of VIA2 < 0.09um (1 lambda) ++1432 14.3 ALU2 must not touch or intersect VIA2 ++1433 14.3b ALU2 end Overlap of VIA2 < 0.09um (small) (1 lambda) ++1434 14.3b ALU2 end Overlap of VIA2 < 0.09um (big) (1 lambda) ++1510 15.1 ALU3 Width < 0.27um (3 lambda) ++1511 15.1 ALU3 Width < 0.27um (3 lambda) ++1520 15.2 ALU3 Notch < 0.36um (4 lambda) ++1521 15.2 ALU3 Space < 0.36um (4 lambda) ++1530 15.3a ALU3 side Overlap of VIA2 < 0.09um (1 lambda) ++1531 15.3a ALU3 side Overlap of VIA2 < 0.09um (1 lambda) ++1532 15.3 ALU3 must not touch or intersect VIA2 ++1533 15.3b ALU3 end Overlap of VIA2 < 0.09um (small) (1 lambda) ++1534 15.3b ALU3 end Overlap of VIA2 < 0.09um (big) (1 lambda) ++2110 21.1 VIA3 Width > 0.27um (3 lambda) ++2111 21.1 VIA3 Width < 0.27um (3 lambda) ++2120 21.2 VIA3 Space < 0.36um (4 lambda) ++2130 21.3a ALU3 side Overlap of VIA3 < 0.09um (1 lambda) ++2131 21.3a ALU3 side Overlap of VIA3 < 0.09um (1 lambda) ++2132 21.3 ALU3 must not touch or intersect VIA3 ++2133 21.3b ALU3 end Overlap of VIA3 < 0.09um (small) (1 lambda) ++2134 21.3b ALU3 end Overlap of VIA3 < 0.09um (big) (1 lambda) ++2210 22.1 ALU4 Width < 0.27um (3 lambda) ++2211 22.1 ALU4 Width < 0.27um (3 lambda) ++2220 22.2 ALU4 Notch < 0.36um (4 lambda) ++2221 22.2 ALU4 Space < 0.36um (4 lambda) ++2230 22.3a ALU4 side Overlap of VIA3 < 0.09um (1 lambda) ++2231 22.3a ALU4 side Overlap of VIA3 < 0.09um (1 lambda) ++2232 22.3 ALU4 must not touch or intersect VIA3 ++2233 22.3b ALU4 end Overlap of VIA3 < 0.09um (small) (1 lambda) ++2234 22.3b ALU4 end Overlap of VIA3 < 0.09um (big) (1 lambda) ++2510 25.1 VIA4 Width > 0.27um (3 lambda) ++2511 25.1 VIA4 Width < 0.27um (3 lambda) ++2520 25.2 VIA4 Space < 0.36um (4 lambda) ++2530 25.3a ALU4 side Overlap of VIA4 < 0.09um (1 lambda) ++2531 25.3a ALU4 side Overlap of VIA4 < 0.09um (1 lambda) ++2532 25.3 ALU4 must not touch or intersect VIA4 ++2533 25.3b ALU4 end Overlap of VIA4 < 0.09um (small) (1 lambda) ++2534 25.3b ALU4 end Overlap of VIA4 < 0.09um (big) (1 lambda) ++2610 26.1 ALU5 Width < 0.27um (3 lambda) ++2611 26.1 ALU5 Width < 0.27um (3 lambda) ++2620 26.2 ALU5 Notch < 0.36um (4 lambda) ++2621 26.2 ALU5 Space < 0.36um (4 lambda) ++2630 26.3a ALU5 side Overlap of VIA4 < 0.09um (1 lambda) ++2631 26.3a ALU5 side Overlap of VIA4 < 0.09um (1 lambda) ++2632 26.3 ALU5 must not touch or intersect VIA4 ++2633 26.3b ALU5 end Overlap of VIA4 < 0.09um (small) (1 lambda) ++2634 26.3b ALU5 end Overlap of VIA4 < 0.09um (big) (1 lambda) ++2910 29.1 VIA5 Width > 0.36um (4 lambda) ++2911 29.1 VIA5 Width < 0.36um (4 lambda) ++2920 29.2 VIA5 Space < 0.36um (4 lambda) ++2930 29.3a ALU5 side Overlap of VIA5 < 0.09um (1 lambda) ++2931 29.3a ALU5 side Overlap of VIA5 < 0.09um (1 lambda) ++2932 29.3 ALU5 must not touch or intersect VIA5 ++2933 29.3b ALU5 end Overlap of VIA5 < 0.09um (small) (1 lambda) ++2934 29.3b ALU5 end Overlap of VIA5 < 0.09um (big) (1 lambda) ++3010 30.1 ALU6 Width < 0.45um (5 lambda) ++3011 30.1 ALU6 Width < 0.45um (5 lambda) ++3020 30.2 ALU6 Notch < 0.45um (5 lambda) ++3021 30.2 ALU6 Space < 0.45um (5 lambda) ++3030 30.3a ALU6 side Overlap of VIA5 < 0.18um (2 lambda) ++3031 30.3a ALU6 side Overlap of VIA5 < 0.18um (2 lambda) ++3032 30.3 ALU6 must not touch or intersect VIA5 ++3033 30.3b ALU6 end Overlap of VIA5 < 0.18um (small) (2 lambda) ++3034 30.3b ALU6 end Overlap of VIA5 < 0.18um (big) (2 lambda) ++5010 50.1 AB Overlap of PTIE < 0.36um (4 lambda) ++5011 50.1 AB Overlap of NTIE < 0.36um (4 lambda) ++5020 50.2 AB Overlap of PDIF < 0.135um (1.5 lambda) ++5021 50.2 AB Overlap of NDIF < 0.135um (1.5 lambda) ++5030 50.3 AB Overlap of POLY < 0.135um (1.5 lambda) ++5040 50.4 AB Overlap of ALU1 < 0.135um (1.5 lambda) ++5041 50.4 AB Overlap of ALU0 < 0.135um (1.5 lambda) ++5050 50.5 AB Overlap of REF < 0.18um (2 lambda) ++END_DRC_COMMENT ++END_DRC_RULES +diff --git a/alliance/src/rds/src/rfmacces.c b/alliance/src/rds/src/rfmacces.c +index 1c87652..74879af 100644 +--- a/alliance/src/rds/src/rfmacces.c ++++ b/alliance/src/rds/src/rfmacces.c +@@ -478,8 +478,8 @@ rdsrec_list *viambkrds( Figure, Via, Lynx ) + ( ( USE == RDS_USE_DRC ) && ( ! Lynx ) ) ) + { + if ( SIDE_STEP == 0 ) break; +- if ( WSX < (SIDE_STEP << 1) ) break; +- if ( WSY < (SIDE_STEP << 1) ) break; ++ if ( WSX < SIDE+(SIDE>>1) ) break; ++ if ( WSY < SIDE+(SIDE>>1) ) break; + + X1R = Xvia + OVERLAP - ( ( WSX + DWR ) >> 1 ); + Y1R = Yvia + OVERLAP - ( ( WSY + DWR ) >> 1 ); +diff --git a/alliance/src/rds/src/rprparse.c b/alliance/src/rds/src/rprparse.c +index 2f1e97b..da68e71 100644 +--- a/alliance/src/rds/src/rprparse.c ++++ b/alliance/src/rds/src/rprparse.c +@@ -103,6 +103,10 @@ extern long MBK_X_GRID, MBK_Y_GRID, MBK_Y_SLICE, MBK_WIDTH_VSS, MBK_WIDTH_VDD, + MBK_TRACK_SPACING_ALU7, MBK_TRACK_SPACING_ALU8; + long *RDS_WIRESETTING_TABLE [ MBK_MAX_WIRESETTING ] = + { ++ &RING_BV_VIA_VIA, ++ &RING_DMIN_ALU1_ALU1, ++ &RING_DMIN_ALU2_ALU2, ++ &RING_EXTENSION_ALU2, + &MBK_TRACK_SPACING_ALU1, &MBK_TRACK_SPACING_ALU2, + &MBK_TRACK_SPACING_ALU3, &MBK_TRACK_SPACING_ALU4, + &MBK_TRACK_SPACING_ALU5, &MBK_TRACK_SPACING_ALU6, +@@ -111,9 +115,15 @@ extern long MBK_X_GRID, MBK_Y_GRID, MBK_Y_SLICE, MBK_WIDTH_VSS, MBK_WIDTH_VDD, + &MBK_TRACK_WIDTH_ALU3, &MBK_TRACK_WIDTH_ALU4, + &MBK_TRACK_WIDTH_ALU5, &MBK_TRACK_WIDTH_ALU6, + &MBK_TRACK_WIDTH_ALU7, &MBK_TRACK_WIDTH_ALU8, ++ &RING_WALIM, + &MBK_WIDTH_VDD, + &MBK_WIDTH_VSS, ++ &RING_WMIN_ALU1, ++ &RING_WMIN_ALU2, ++ &RING_WVIA_ALU1, ++ &RING_WVIA_ALU2, + &MBK_X_GRID, &MBK_Y_GRID, &MBK_Y_SLICE ++ + }; + /*------------------------------------------------------------\ + | | +@@ -412,6 +422,10 @@ extern long MBK_X_GRID, MBK_Y_GRID, MBK_Y_SLICE, MBK_WIDTH_VSS, MBK_WIDTH_VDD, + char MBK_WIRESETTING_NAME [ MBK_MAX_WIRESETTING ][ MBK_MAX_WIRESETTING_TLEN ] = + + { ++ "bv_via_via", ++ "dmin_alu1_alu1", ++ "dmin_alu2_alu2", ++ "extension_alu2", + "track_spacing_alu1", + "track_spacing_alu2", + "track_spacing_alu3", +@@ -428,8 +442,13 @@ extern long MBK_X_GRID, MBK_Y_GRID, MBK_Y_SLICE, MBK_WIDTH_VSS, MBK_WIDTH_VDD, + "track_width_alu6", + "track_width_alu7", + "track_width_alu8", ++ "walim", + "width_vdd", + "width_vss", ++ "wmin_alu1", ++ "wmin_alu2", ++ "wvia_alu1", ++ "wvia_alu2", + "x_grid", + "y_grid", + "y_slice" +diff --git a/alliance/src/rds/src/rprparse.h b/alliance/src/rds/src/rprparse.h +index 03f35e3..dfb548e 100644 +--- a/alliance/src/rds/src/rprparse.h ++++ b/alliance/src/rds/src/rprparse.h +@@ -33,7 +33,7 @@ + # define RPR_MAX_BUFFER 512 + # define RPR_MAX_KEYWORD 151 + +-# define MBK_MAX_WIRESETTING 21 ++# define MBK_MAX_WIRESETTING 30 + # define RPR_SEPARATORS_STRING " \t\n" + # define RPR_COMMENT_CHAR '#' + +diff --git a/alliance/src/ring/src/Makefile.am b/alliance/src/ring/src/Makefile.am +index e630fc7..65e1653 100644 +--- a/alliance/src/ring/src/Makefile.am ++++ b/alliance/src/ring/src/Makefile.am +@@ -11,7 +11,8 @@ bin_PROGRAMS = ring + ring_LDADD = @ALLIANCE_LIBS@ \ + -L$(top_builddir)/genlib/src \ + -L$(top_builddir)/mbk/src \ +- -lMgn -lMpu -lMlu -lMlo -lMph -lMut -lRcn ++ -L$(top_builddir)/rds/src \ ++ -lMgn -lMpu -lMlu -lMlo -lMph -lMut -lRcn -lRds + + ring_SOURCES = bigvia.c bigvia.h \ + compress.c compress.h \ +diff --git a/alliance/src/ring/src/param.c b/alliance/src/ring/src/param.c +index ecd3af1..52589e6 100644 +--- a/alliance/src/ring/src/param.c ++++ b/alliance/src/ring/src/param.c +@@ -126,11 +126,22 @@ void lecture_param(int nbarg, char** tab, char** nom_circuit_lo, + /* arguments de mbk */ + /* ---------------- */ + ++ rdsenv(); ++ loadrdsparam(); ++ + mbkenv(); /* choix de l'utilisateur mis dans des variables UNIX */ + /* on recupere (long) SCALE_X */ + +- if (mode_debug) ++ if (mode_debug) { + printf("CATALNAME is %s\n", CATAL); ++ printf("WMIN_ALU1 is %ld\n", WMIN_ALU1); ++ printf("WVIA_ALU1 is %ld\n", WVIA_ALU1); ++ printf("WMIN_ALU2 is %ld\n", WMIN_ALU2); ++ printf("WVIA_ALU2 is %ld\n", WVIA_ALU2); ++ printf("DMIN_ALU1_ALU1 is %ld\n", DMIN_ALU1_ALU1); ++ printf("DMIN_ALU2_ALU2 is %ld\n", DMIN_ALU2_ALU2); ++ printf("BV_VIA_VIA is %ld\n", BV_VIA_VIA); ++ } + + if (NULL == (f_catal = mbkfopen(CATAL, NULL, READ_TEXT))) + ringerreur(ERR_CATAL, CATAL, NULL); +diff --git a/alliance/src/ring/src/sesame.c b/alliance/src/ring/src/sesame.c +index 9b48fc2..7ac61ea 100644 +--- a/alliance/src/ring/src/sesame.c ++++ b/alliance/src/ring/src/sesame.c +@@ -51,6 +51,13 @@ + + void ringerreur(int code, void *pt_liste, void *pt_liste2) + { ++ fprintf( stderr, "WMIN_ALU1: %d\n", (int)WMIN_ALU1 ); ++ fprintf( stderr, "WMIN_ALU2: %d\n", (int)WMIN_ALU2 ); ++ fprintf( stderr, "DMIN_ALU1_ALU1: %d\n", (int)DMIN_ALU1_ALU1 ); ++ fprintf( stderr, "DMIN_ALU2_ALU2: %d\n", (int)DMIN_ALU2_ALU2 ); ++ fprintf( stderr, "WVIA_ALU1: %d\n", (int)WVIA_ALU1 ); ++ fprintf( stderr, "WVIA_ALU2: %d\n", (int)WVIA_ALU2 ); ++ + loins_list * circuit_inst, *liste_inst; + locon_list * con_lo; + chain_list * liste; +diff --git a/alliance/src/ring/src/struct.h b/alliance/src/ring/src/struct.h +index 8b46130..0d54a94 100644 +--- a/alliance/src/ring/src/struct.h ++++ b/alliance/src/ring/src/struct.h +@@ -77,19 +77,20 @@ + #define OUEST 2 + #define EST 3 + /* Nombres entiers obligatoires ! */ +-#define WMIN_ALU1 2 /* largeur minimum de l'alu1,l'alu2,dist mini alu1<->alu2 */ +-#define WMIN_ALU2 2 /* et largeur du via */ +-#define DMIN_ALU1_ALU1 3 /* dmin en a1 a1 2.5 arrondi a 3 */ +-#define DMIN_ALU2_ALU2 3 +-#define WVIA_ALU1 2 /* largeur du via pour l'alu1 */ +-#define WVIA_ALU2 3 /* largeur du via pour l'alu2 */ ++#define WMIN_ALU1 RING_WMIN_ALU1 ++#define WMIN_ALU2 RING_WMIN_ALU2 ++#define DMIN_ALU1_ALU1 RING_DMIN_ALU1_ALU1 ++#define DMIN_ALU2_ALU2 RING_DMIN_ALU2_ALU2 ++#define WVIA_ALU1 RING_WVIA_ALU1 + +-#define EXTENSION_ALU2 1 /* extension alu2 pour fignoler coin couronne */ ++#define WVIA_ALU2 RING_WVIA_ALU2 /* largeur du via pour l'alu2 */ + +-#define BV_VIA_VIA 4 /* must be even, whatever! */ ++#define EXTENSION_ALU2 RING_EXTENSION_ALU2 /* pour fignoler coin couronne */ ++ ++#define BV_VIA_VIA RING_BV_VIA_VIA /* must be even, whatever! */ + #define BV_VIASIZE WVIA_ALU2 /* design rule for equipotential vias */ + +-#define WALIM 60 /* largeur prdefinie des alim */ ++#define WALIM RING_WALIM /* largeur prdefinie des alim */ + + /*#define PISTE_DEP_ALIMPLOT 10 Nombre de piste a considerer pour une deport alim plot */ + /* code des ringerreurs traitees par ringerreur(code) */ +diff --git a/alliance/src/s2r/doc/s2r.1 b/alliance/src/s2r/doc/s2r.1 +index 8cc9e3c..18fe38d 100644 +--- a/alliance/src/s2r/doc/s2r.1 ++++ b/alliance/src/s2r/doc/s2r.1 +@@ -141,7 +141,7 @@ example below. + setenv RDS_TECHNO_NAME /labo/etc/prol15.rds + setenv RDS_IN gds + setenv RDS_OUT gds +- s2r -c na2_y ++ s2r \-c na2_y + .fi + .ft R + .RS diff --git a/0001-Remove-stray-files.patch b/0001-Remove-stray-files.patch new file mode 100644 index 0000000..20eeef7 --- /dev/null +++ b/0001-Remove-stray-files.patch @@ -0,0 +1,1475 @@ +From fad51c8b32248c47cee6ed5ace1620551ed382aa Mon Sep 17 00:00:00 2001 +From: =?UTF-8?q?Ralf=20Cors=C3=A9pius?= +Date: Sun, 28 Feb 2016 13:12:16 +0100 +Subject: [PATCH 01/10] Remove stray files. + +--- + alliance/src/elp/src/Makefile | 719 -------------------------------------- + alliance/src/genpat/src/Makefile | 729 --------------------------------------- + 2 files changed, 1448 deletions(-) + delete mode 100644 alliance/src/elp/src/Makefile + delete mode 100644 alliance/src/genpat/src/Makefile + +diff --git a/alliance/src/elp/src/Makefile b/alliance/src/elp/src/Makefile +deleted file mode 100644 +index 79ed72d..0000000 +--- a/alliance/src/elp/src/Makefile ++++ /dev/null +@@ -1,719 +0,0 @@ +-# Makefile.in generated by automake 1.8.5 from Makefile.am. +-# elp/src/Makefile. Generated from Makefile.in by configure. +- +-# Copyright (C) 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002, +-# 2003, 2004 Free Software Foundation, Inc. +-# This Makefile.in is free software; the Free Software Foundation +-# gives unlimited permission to copy and/or distribute it, +-# with or without modifications, as long as this notice is preserved. +- +-# This program is distributed in the hope that it will be useful, +-# but WITHOUT ANY WARRANTY, to the extent permitted by law; without +-# even the implied warranty of MERCHANTABILITY or FITNESS FOR A +-# PARTICULAR PURPOSE. +- +- +- +- +-SOURCES = $(libElp_la_SOURCES) +- +-srcdir = . +-top_srcdir = ../.. +- +-pkgdatadir = $(datadir)/alliance +-pkglibdir = $(libdir)/alliance +-pkgincludedir = $(includedir)/alliance +-top_builddir = ../.. +-am__cd = CDPATH="$${ZSH_VERSION+.}$(PATH_SEPARATOR)" && cd +-INSTALL = /usr/bin/install -c +-install_sh_DATA = $(install_sh) -c -m 644 +-install_sh_PROGRAM = $(install_sh) -c +-install_sh_SCRIPT = $(install_sh) -c +-INSTALL_HEADER = $(INSTALL_DATA) +-transform = $(program_transform_name) +-NORMAL_INSTALL = : +-PRE_INSTALL = : +-POST_INSTALL = : +-NORMAL_UNINSTALL = : +-PRE_UNINSTALL = : +-POST_UNINSTALL = : +-host_triplet = i686-pc-linux-gnu +-subdir = elp/src +-DIST_COMMON = $(include_HEADERS) $(srcdir)/Makefile.am \ +- $(srcdir)/Makefile.in elp_l.c elp_y.c +-ACLOCAL_M4 = $(top_srcdir)/aclocal.m4 +-am__aclocal_m4_deps = $(top_srcdir)/./alliance.m4 \ +- $(top_srcdir)/./motif.m4 $(top_srcdir)/./xpm.m4 \ +- $(top_srcdir)/configure.in +-am__configure_deps = $(am__aclocal_m4_deps) $(CONFIGURE_DEPENDENCIES) \ +- $(ACLOCAL_M4) +-mkinstalldirs = $(mkdir_p) +-CONFIG_CLEAN_FILES = +-am__installdirs = "$(DESTDIR)$(libdir)" "$(DESTDIR)$(includedir)" +-libLTLIBRARIES_INSTALL = $(INSTALL) +-LTLIBRARIES = $(lib_LTLIBRARIES) +-libElp_la_LIBADD = +-am_libElp_la_OBJECTS = elp_y.lo elp_l.lo elp.lo elperror.lo +-libElp_la_OBJECTS = $(am_libElp_la_OBJECTS) +-DEFAULT_INCLUDES = -I. -I$(srcdir) +-depcomp = $(SHELL) $(top_srcdir)/depcomp +-am__depfiles_maybe = depfiles +-DEP_FILES = ./$(DEPDIR)/elp.Plo ./$(DEPDIR)/elp_l.Plo \ +- ./$(DEPDIR)/elp_y.Plo ./$(DEPDIR)/elperror.Plo +-COMPILE = $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) \ +- $(CPPFLAGS) $(AM_CFLAGS) $(CFLAGS) +-LTCOMPILE = $(LIBTOOL) --mode=compile $(CC) $(DEFS) \ +- $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) \ +- $(AM_CFLAGS) $(CFLAGS) +-CCLD = $(CC) +-LINK = $(LIBTOOL) --mode=link $(CCLD) $(AM_CFLAGS) $(CFLAGS) \ +- $(AM_LDFLAGS) $(LDFLAGS) -o $@ +-LEXCOMPILE = $(LEX) $(LFLAGS) $(AM_LFLAGS) +-LTLEXCOMPILE = $(LIBTOOL) --mode=compile $(LEX) $(LFLAGS) $(AM_LFLAGS) +-YACCCOMPILE = $(YACC) $(YFLAGS) $(AM_YFLAGS) +-LTYACCCOMPILE = $(LIBTOOL) --mode=compile $(YACC) $(YFLAGS) \ +- $(AM_YFLAGS) +-SOURCES = $(libElp_la_SOURCES) +-DIST_SOURCES = $(libElp_la_SOURCES) +-includeHEADERS_INSTALL = $(INSTALL_HEADER) +-HEADERS = $(include_HEADERS) +-ETAGS = etags +-CTAGS = ctags +-DISTFILES = $(DIST_COMMON) $(DIST_SOURCES) $(TEXINFOS) $(EXTRA_DIST) +-ABE_DLL_VERSION = 2:1:0 +-ABL_DLL_VERSION = 1:3:0 +-ABT_DLL_VERSION = 2:1:0 +-ABV_DLL_VERSION = 2:1:0 +-ACLOCAL = ${SHELL} /dsk/l1/misc/hcl/alliance/src/missing --run aclocal-1.8 +-ALCBANNER_MAJOR_VERSION = 1 +-ALCBANNER_MINOR_VERSION = 1 +-ALCBANNER_VERSION = 1.1 +-ALLIANCE_BUILD_FALSE = # +-ALLIANCE_BUILD_TRUE = +-ALLIANCE_CFLAGS = -I/users/outil/alliance/Linux.FC2/include +-ALLIANCE_LIBS = -L/users/outil/alliance/Linux.FC2/lib +-ALLIANCE_TOP = /users/outil/alliance/Linux.FC2 +-AMDEP_FALSE = # +-AMDEP_TRUE = +-AMTAR = ${SHELL} /dsk/l1/misc/hcl/alliance/src/missing --run tar +-AR = ar +-ATTILA_MAJOR_VERSION = 0 +-ATTILA_MINOR_VERSION = 1 +-ATTILA_VERSION = 0.1 +-AUTOCONF = ${SHELL} /dsk/l1/misc/hcl/alliance/src/missing --run autoconf +-AUTOHEADER = ${SHELL} /dsk/l1/misc/hcl/alliance/src/missing --run autoheader +-AUTOMAKE = ${SHELL} /dsk/l1/misc/hcl/alliance/src/missing --run automake-1.8 +-AUT_DLL_VERSION = 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$(depcomp) \ +-# $(COMPILE) -c `$(CYGPATH_W) '$<'` +- +-.c.lo: +- if $(LTCOMPILE) -MT $@ -MD -MP -MF "$(DEPDIR)/$*.Tpo" -c -o $@ $<; \ +- then mv -f "$(DEPDIR)/$*.Tpo" "$(DEPDIR)/$*.Plo"; else rm -f "$(DEPDIR)/$*.Tpo"; exit 1; fi +-# source='$<' object='$@' libtool=yes \ +-# depfile='$(DEPDIR)/$*.Plo' tmpdepfile='$(DEPDIR)/$*.TPlo' \ +-# $(CCDEPMODE) $(depcomp) \ +-# $(LTCOMPILE) -c -o $@ $< +- +-mostlyclean-libtool: +- -rm -f *.lo +- +-clean-libtool: +- -rm -rf .libs _libs +- +-distclean-libtool: +- -rm -f libtool +-uninstall-info-am: +-install-includeHEADERS: $(include_HEADERS) +- @$(NORMAL_INSTALL) +- test -z "$(includedir)" || $(mkdir_p) "$(DESTDIR)$(includedir)" +- @list='$(include_HEADERS)'; for p in $$list; do \ +- if test -f "$$p"; then d=; else d="$(srcdir)/"; fi; \ +- f="`echo $$p | sed -e 's|^.*/||'`"; \ +- echo " $(includeHEADERS_INSTALL) '$$d$$p' '$(DESTDIR)$(includedir)/$$f'"; \ +- $(includeHEADERS_INSTALL) "$$d$$p" "$(DESTDIR)$(includedir)/$$f"; \ +- done +- +-uninstall-includeHEADERS: +- @$(NORMAL_UNINSTALL) +- @list='$(include_HEADERS)'; for p in $$list; do \ +- f="`echo $$p | sed -e 's|^.*/||'`"; \ +- echo " rm -f '$(DESTDIR)$(includedir)/$$f'"; \ +- rm -f "$(DESTDIR)$(includedir)/$$f"; \ +- done +- +-ID: $(HEADERS) $(SOURCES) $(LISP) $(TAGS_FILES) +- list='$(SOURCES) $(HEADERS) $(LISP) $(TAGS_FILES)'; \ +- unique=`for i in $$list; do \ +- if test -f "$$i"; then echo $$i; else echo $(srcdir)/$$i; fi; \ +- done | \ +- $(AWK) ' { files[$$0] = 1; } \ +- END { for (i in files) print i; }'`; \ +- mkid -fID $$unique +-tags: TAGS +- +-TAGS: $(HEADERS) $(SOURCES) $(TAGS_DEPENDENCIES) \ +- $(TAGS_FILES) $(LISP) +- tags=; \ +- here=`pwd`; \ +- list='$(SOURCES) $(HEADERS) $(LISP) $(TAGS_FILES)'; \ +- unique=`for i in $$list; do \ +- if test -f "$$i"; then echo $$i; else echo $(srcdir)/$$i; fi; \ +- done | \ +- $(AWK) ' { files[$$0] = 1; } \ +- END { for (i in files) print i; }'`; \ +- if test -z "$(ETAGS_ARGS)$$tags$$unique"; then :; else \ +- test -n "$$unique" || unique=$$empty_fix; \ +- $(ETAGS) $(ETAGSFLAGS) $(AM_ETAGSFLAGS) $(ETAGS_ARGS) \ +- $$tags $$unique; \ +- fi +-ctags: CTAGS +-CTAGS: $(HEADERS) $(SOURCES) $(TAGS_DEPENDENCIES) \ +- $(TAGS_FILES) $(LISP) +- tags=; \ +- here=`pwd`; \ +- list='$(SOURCES) $(HEADERS) $(LISP) $(TAGS_FILES)'; \ +- unique=`for i in $$list; do \ +- if test -f "$$i"; then echo $$i; else echo $(srcdir)/$$i; fi; \ +- done | \ +- $(AWK) ' { files[$$0] = 1; } \ +- END { for (i in files) print i; }'`; \ +- test -z "$(CTAGS_ARGS)$$tags$$unique" \ +- || $(CTAGS) $(CTAGSFLAGS) $(AM_CTAGSFLAGS) $(CTAGS_ARGS) \ +- $$tags $$unique +- +-GTAGS: +- here=`$(am__cd) $(top_builddir) && pwd` \ +- && cd $(top_srcdir) \ +- && gtags -i $(GTAGS_ARGS) $$here +- +-distclean-tags: +- -rm -f TAGS ID GTAGS GRTAGS GSYMS GPATH tags +- +-distdir: $(DISTFILES) +- @srcdirstrip=`echo "$(srcdir)" | sed 's|.|.|g'`; \ +- topsrcdirstrip=`echo "$(top_srcdir)" | sed 's|.|.|g'`; \ +- list='$(DISTFILES)'; for file in $$list; do \ +- case $$file in \ +- $(srcdir)/*) file=`echo "$$file" | sed "s|^$$srcdirstrip/||"`;; \ +- $(top_srcdir)/*) file=`echo "$$file" | sed "s|^$$topsrcdirstrip/|$(top_builddir)/|"`;; \ +- esac; \ +- if test -f $$file || test -d $$file; then d=.; else d=$(srcdir); fi; \ +- dir=`echo "$$file" | sed -e 's,/[^/]*$$,,'`; \ +- if test "$$dir" != "$$file" && test "$$dir" != "."; then \ +- dir="/$$dir"; \ +- $(mkdir_p) "$(distdir)$$dir"; \ +- else \ +- dir=''; \ +- fi; \ +- if test -d $$d/$$file; then \ +- if test -d $(srcdir)/$$file && test $$d != $(srcdir); then \ +- cp -pR $(srcdir)/$$file $(distdir)$$dir || exit 1; \ +- fi; \ +- cp -pR $$d/$$file $(distdir)$$dir || exit 1; \ +- else \ +- test -f $(distdir)/$$file \ +- || cp -p $$d/$$file $(distdir)/$$file \ +- || exit 1; \ +- fi; \ +- done +-check-am: all-am +-check: check-am +-all-am: Makefile $(LTLIBRARIES) $(SCRIPTS) $(HEADERS) +-installdirs: +- for dir in "$(DESTDIR)$(libdir)" "$(DESTDIR)$(bindir)" "$(DESTDIR)$(includedir)"; do \ +- test -z "$$dir" || $(mkdir_p) "$$dir"; \ +- done +-install: install-am +-install-exec: install-exec-am +-install-data: install-data-am +-uninstall: uninstall-am +- +-install-am: all-am +- @$(MAKE) $(AM_MAKEFLAGS) install-exec-am install-data-am +- +-installcheck: installcheck-am +-install-strip: +- $(MAKE) $(AM_MAKEFLAGS) INSTALL_PROGRAM="$(INSTALL_STRIP_PROGRAM)" \ +- install_sh_PROGRAM="$(INSTALL_STRIP_PROGRAM)" INSTALL_STRIP_FLAG=-s \ +- `test -z '$(STRIP)' || \ +- echo "INSTALL_PROGRAM_ENV=STRIPPROG='$(STRIP)'"` install +-mostlyclean-generic: +- +-clean-generic: +- -test -z "$(CLEANFILES)" || rm -f $(CLEANFILES) +- +-distclean-generic: +- -rm -f $(CONFIG_CLEAN_FILES) +- +-maintainer-clean-generic: +- @echo "This command is intended for maintainers to use" +- @echo "it deletes files that may require special tools to rebuild." +-clean: clean-am +- +-clean-am: clean-generic clean-libLTLIBRARIES clean-libtool \ +- mostlyclean-am +- +-distclean: distclean-am +- -rm -rf ./$(DEPDIR) +- -rm -f Makefile +-distclean-am: clean-am distclean-compile distclean-generic \ +- distclean-libtool distclean-tags +- +-dvi: dvi-am +- +-dvi-am: +- +-html: html-am +- +-info: info-am +- +-info-am: +- +-install-data-am: install-includeHEADERS +- +-install-exec-am: install-binSCRIPTS install-libLTLIBRARIES +- +-install-info: install-info-am +- +-install-man: +- +-installcheck-am: +- +-maintainer-clean: maintainer-clean-am +- -rm -rf ./$(DEPDIR) +- -rm -f Makefile +-maintainer-clean-am: distclean-am maintainer-clean-generic +- +-mostlyclean: mostlyclean-am +- +-mostlyclean-am: mostlyclean-compile mostlyclean-generic \ +- mostlyclean-libtool +- +-pdf: pdf-am +- +-pdf-am: +- +-ps: ps-am +- +-ps-am: +- +-uninstall-am: uninstall-binSCRIPTS uninstall-includeHEADERS \ +- uninstall-info-am uninstall-libLTLIBRARIES +- +-.PHONY: CTAGS GTAGS all all-am check check-am clean clean-generic \ +- clean-libLTLIBRARIES clean-libtool ctags distclean \ +- distclean-compile distclean-generic distclean-libtool \ +- distclean-tags distdir dvi dvi-am html html-am info info-am \ +- install install-am install-binSCRIPTS install-data \ +- install-data-am install-exec install-exec-am \ +- install-includeHEADERS install-info install-info-am \ +- install-libLTLIBRARIES install-man install-strip installcheck \ +- installcheck-am installdirs maintainer-clean \ +- maintainer-clean-generic mostlyclean mostlyclean-compile \ +- mostlyclean-generic mostlyclean-libtool pdf pdf-am ps ps-am \ +- tags uninstall uninstall-am uninstall-binSCRIPTS \ +- uninstall-includeHEADERS uninstall-info-am \ +- uninstall-libLTLIBRARIES +- +- +-genpat : ${srcdir}/genpat.sh +- ${SED} 's,__ALLIANCE_INSTALL_DIR__,$(ALLIANCE_INSTALL_DIR),' $< > $@ +- chmod a+x $@ +-# Tell versions [3.59,3.63) of GNU make to not export all variables. +-# Otherwise a system limit (for SysV at least) may be exceeded. +-.NOEXPORT: +-- +2.5.0 + diff --git a/0002-Update-autostuff.patch b/0002-Update-autostuff.patch new file mode 100644 index 0000000..d188265 --- /dev/null +++ b/0002-Update-autostuff.patch @@ -0,0 +1,191 @@ +From c4b1cb8e7cbf8e36282f42b9307fe46b6cc6a92f Mon Sep 17 00:00:00 2001 +From: =?UTF-8?q?Ralf=20Cors=C3=A9pius?= +Date: Sun, 28 Feb 2016 10:07:48 +0100 +Subject: [PATCH 02/10] Update autostuff + +--- + alliance/src/Makefile.am | 2 + + alliance/src/autostuff | 123 ++++++++++++++++++++++++----------------------- + 2 files changed, 66 insertions(+), 59 deletions(-) + +diff --git a/alliance/src/Makefile.am b/alliance/src/Makefile.am +index 061389e..e23b5c2 100644 +--- a/alliance/src/Makefile.am ++++ b/alliance/src/Makefile.am +@@ -1,3 +1,5 @@ ++ACLOCAL_AMFLAGS = -I. ++ + SUBDIRS = @TOOLSDIRS@ + + EXTRA_DIST = autostuff alliance.m4 motif.m4 oldgcc.m4 xpm.m4 build depcomp \ +diff --git a/alliance/src/autostuff b/alliance/src/autostuff +index 53083eb..2955c8b 100755 +--- a/alliance/src/autostuff ++++ b/alliance/src/autostuff +@@ -89,38 +89,40 @@ ordered_dirs="$ordered_dirs $dirs" + + AC_OUTPUT=`find $ordered_dirs -name Makefile.am | sed "s,\.am,,"` + +-rm -f configure.in +-echo "" >> configure.in +-echo "AC_INIT(./autostuff)" >> configure.in +-echo "AM_INIT_AUTOMAKE(alliance, 5.0)" >> configure.in +-echo "" >> configure.in +-echo "AM_PROG_LEX" >> configure.in +-echo "AM_PROG_LIBTOOL" >> configure.in +-echo "AC_CHECK_HEADERS(fcntl.h malloc.h strings.h sys/time.h unistd.h)" >> configure.in +-echo "AC_CHECK_HEADERS(strings.h unistd.h)" >> configure.in +-echo "AC_CHECK_LIB(gen, basename)" >> configure.in +-echo "AC_CHECK_LIB(iberty, basename)" >> configure.in +-echo "AC_CHECK_LIB(m, exp)" >> configure.in +-echo "AC_CHECK_LIB(m, floor)" >> configure.in +-echo "AC_CHECK_LIB(m, pow)" >> configure.in +-echo "AC_CHECK_LIB(m, sqrt)" >> configure.in +-echo "AC_CHECK_PROG(SED, sed, sed)" >> configure.in +-echo "AC_CHECK_PROGS(SED, gsed sed)" >> configure.in +-echo "AC_C_CONST" >> configure.in +-echo "AC_FUNC_VFORK" >> configure.in +-echo "AC_HEADER_STDC" >> configure.in +-echo "AC_HEADER_SYS_WAIT" >> configure.in +-echo "AC_PATH_XTRA" >> configure.in +-echo "AC_PROG_CC" >> configure.in +-echo "AC_PROG_CPP" >> configure.in +-echo "AC_PROG_CXX" >> configure.in +-echo "AC_PROG_INSTALL" >> configure.in +-echo "AC_PROG_MAKE_SET" >> configure.in +-echo "AC_PROG_LIBTOOL" >> configure.in +-echo "AC_PROG_YACC" >> configure.in +-echo "AC_TYPE_SIGNAL" >> configure.in ++rm -f configure.ac ++echo "" >> configure.ac ++echo "AC_INIT(alliance,5.0)" >> configure.ac ++echo "AC_CONFIG_SRCDIR(./autostuff)" >> configure.ac ++echo "AM_INIT_AUTOMAKE(foreign)" >> configure.ac ++echo "AC_CONFIG_MACRO_DIRS([.])" >> configure.ac ++echo "" >> configure.ac ++echo "AM_PROG_LEX" >> configure.ac ++echo "AM_PROG_LIBTOOL" >> configure.ac ++echo "AC_CHECK_HEADERS(fcntl.h malloc.h strings.h sys/time.h unistd.h)" >> configure.ac ++echo "AC_CHECK_HEADERS(strings.h unistd.h)" >> configure.ac ++echo "AC_CHECK_LIB(gen, basename)" >> configure.ac ++echo "AC_CHECK_LIB(iberty, basename)" >> configure.ac ++echo "AC_CHECK_LIB(m, exp)" >> configure.ac ++echo "AC_CHECK_LIB(m, floor)" >> configure.ac ++echo "AC_CHECK_LIB(m, pow)" >> configure.ac ++echo "AC_CHECK_LIB(m, sqrt)" >> configure.ac ++echo "AC_CHECK_PROG(SED, sed, sed)" >> configure.ac ++echo "AC_CHECK_PROGS(SED, gsed sed)" >> configure.ac ++echo "AC_C_CONST" >> configure.ac ++echo "AC_FUNC_VFORK" >> configure.ac ++echo "AC_HEADER_STDC" >> configure.ac ++echo "AC_HEADER_SYS_WAIT" >> configure.ac ++echo "AC_PATH_XTRA" >> configure.ac ++echo "AC_PROG_CC" >> configure.ac ++echo "AC_PROG_CPP" >> configure.ac ++echo "AC_PROG_CXX" >> configure.ac ++echo "AC_PROG_INSTALL" >> configure.ac ++echo "AC_PROG_MAKE_SET" >> configure.ac ++echo "AC_PROG_LIBTOOL" >> configure.ac ++echo "AC_PROG_YACC" >> configure.ac ++echo "AC_TYPE_SIGNAL" >> configure.ac + +-cat >> configure.in <<"EOF" ++cat >> configure.ac <<"EOF" + dnl + dnl Check for X stuff + dnl +@@ -283,60 +285,63 @@ LDFLAGS="$ice_save_LDFLAGS" + fi + EOF + +-echo "AM_ALLIANCE" >> configure.in +-echo "AM_CONDITIONAL([ALLIANCE_BUILD],[(exit 0)])" >> configure.in ++echo "AM_ALLIANCE" >> configure.ac ++echo "AM_CONDITIONAL([ALLIANCE_BUILD],[(exit 0)])" >> configure.ac + + find $ordered_dirs -name configure.in | while read config; do + echo "Scanning $config" +- echo "" >> configure.in +- echo "dnl Infos extracted from $config" >> configure.in ++ echo "" >> configure.ac ++ echo "dnl Infos extracted from $config" >> configure.ac + + for version_line in `grep -ah _CUR= $config`; do +- echo "$version_line" >> configure.in ++ echo "$version_line" >> configure.ac + version_name=`echo $version_line | sed 's,=.*,,'` +- echo "AC_SUBST($version_name)" >> configure.in ++ echo "AC_SUBST($version_name)" >> configure.ac + done + for version_line in `grep -ah _REV= $config`; do +- echo "$version_line" >> configure.in ++ echo "$version_line" >> configure.ac + version_name=`echo $version_line | sed 's,=.*,,'` +- echo "AC_SUBST($version_name)" >> configure.in ++ echo "AC_SUBST($version_name)" >> configure.ac + done + for version_line in `grep -ah _REL= $config`; do +- echo "$version_line" >> configure.in ++ echo "$version_line" >> configure.ac + version_name=`echo $version_line | sed 's,=.*,,'` +- echo "AC_SUBST($version_name)" >> configure.in ++ echo "AC_SUBST($version_name)" >> configure.ac + done + + for dll_line in `grep -ah _DLL_VERSION= $config`; do +- echo "$dll_line" >> configure.in ++ echo "$dll_line" >> configure.ac + dll_name=`echo $dll_line | sed 's,=.*,,'` +- echo "AC_SUBST($dll_name)" >> configure.in ++ echo "AC_SUBST($dll_name)" >> configure.ac + done + for version_line in `grep -ah _VERSION= $config | grep -v DLL`; do +- echo "$version_line" >> configure.in ++ echo "$version_line" >> configure.ac + version_name=`echo $version_line | sed 's,=.*,,'` +- echo "AC_SUBST($version_name)" >> configure.in ++ echo "AC_SUBST($version_name)" >> configure.ac + done + done + +-echo "" >> configure.in +-echo "TOOLSDIRS=\"$ordered_dirs\"" >> configure.in +-echo "AC_SUBST(TOOLSDIRS)" >> configure.in ++echo "" >> configure.ac ++echo "TOOLSDIRS=\"$ordered_dirs\"" >> configure.ac ++echo "AC_SUBST(TOOLSDIRS)" >> configure.ac + +-echo "" >> configure.in +-echo "AC_OUTPUT([" >> configure.in +-echo "Makefile" >> configure.in +-echo "distrib/etc/alc_env.sh" >> configure.in +-echo "distrib/etc/alc_env.csh" >> configure.in ++echo "" >> configure.ac ++echo "# HACK: Set to empty." >> configure.ac ++echo "AC_SUBST([ALLIANCE_LIB],[ ])" >> configure.ac ++echo "AC_SUBST([ALLIANCE_CFLAGS],[ ])" >> configure.ac ++echo "AC_SUBST([ALLIANCE_TOP],[ ])" >> configure.ac ++ ++echo "" >> configure.ac ++echo "AC_OUTPUT([" >> configure.ac ++echo "Makefile" >> configure.ac ++echo "distrib/etc/alc_env.sh" >> configure.ac ++echo "distrib/etc/alc_env.csh" >> configure.ac + for template in $AC_OUTPUT; do +- echo "$template" >> configure.in ++ echo "$template" >> configure.ac + done +-echo "])" >> configure.in ++echo "])" >> configure.ac + + +-aclocal -I . +-libtoolize --force --copy --automake +-automake --foreign --add-missing --copy +-autoconf ++autoreconf -fi + + exit 0 +-- +2.5.0 + diff --git a/0003-Consolidate-installation-dirs.patch b/0003-Consolidate-installation-dirs.patch new file mode 100644 index 0000000..26fe6ee --- /dev/null +++ b/0003-Consolidate-installation-dirs.patch @@ -0,0 +1,151 @@ +From 9397e394dfbb0162236e85d6046862fb7e9bae58 Mon Sep 17 00:00:00 2001 +From: =?UTF-8?q?Ralf=20Cors=C3=A9pius?= +Date: Mon, 29 Feb 2016 14:49:22 +0100 +Subject: [PATCH 03/10] Consolidate installation dirs + +--- + alliance/src/cells/src/dp_sxlib/Makefile.am | 2 +- + alliance/src/cells/src/mpxlib/Makefile.am | 2 +- + alliance/src/cells/src/msxlib/Makefile.am | 2 +- + alliance/src/cells/src/padlib/Makefile.am | 2 +- + alliance/src/cells/src/pxlib/Makefile.am | 2 +- + alliance/src/cells/src/ramlib/Makefile.am | 2 +- + alliance/src/cells/src/rf2lib/Makefile.am | 2 +- + alliance/src/cells/src/rflib/Makefile.am | 2 +- + alliance/src/cells/src/romlib/Makefile.am | 2 +- + alliance/src/cells/src/sxlib/Makefile.am | 14 +++++++------- + 10 files changed, 16 insertions(+), 16 deletions(-) + +diff --git a/alliance/src/cells/src/dp_sxlib/Makefile.am b/alliance/src/cells/src/dp_sxlib/Makefile.am +index 58fa1a2..5d1b32f 100644 +--- a/alliance/src/cells/src/dp_sxlib/Makefile.am ++++ b/alliance/src/cells/src/dp_sxlib/Makefile.am +@@ -1,6 +1,6 @@ + # $Id: Makefile.am,v 1.4 2002/05/08 21:07:13 jpc Exp $ + +-dp_sxlibdir=$(prefix)/cells/dp_sxlib ++dp_sxlibdir=$(pkgdatadir)/cells/dp_sxlib + + dp_sxlib_DATA=CATAL dp_dff_scan_x4.ap dp_dff_scan_x4.vbe dp_dff_scan_x4_buf.ap dp_dff_scan_x4_buf.vbe dp_dff_x4.ap dp_dff_x4.vbe dp_dff_x4_buf.ap dp_dff_x4_buf.vbe dp_mux_x2.ap dp_mux_x2.vbe dp_mux_x2_buf.ap dp_mux_x2_buf.vbe dp_mux_x4.ap dp_mux_x4.vbe dp_mux_x4_buf.ap dp_mux_x4_buf.vbe dp_nmux_x1.ap dp_nmux_x1.vbe dp_nmux_x1_buf.ap dp_nmux_x1_buf.vbe dp_nts_x2.ap dp_nts_x2.vbe dp_nts_x2_buf.ap dp_nts_x2_buf.vbe dp_rom2_buf.ap dp_rom2_buf.vbe dp_rom4_buf.ap dp_rom4_buf.vbe dp_rom4_nxr2_x4.ap dp_rom4_nxr2_x4.vbe dp_rom4_xr2_x4.ap dp_rom4_xr2_x4.vbe dp_sff_scan_x4.ap dp_sff_scan_x4.vbe dp_sff_scan_x4_buf.ap dp_sff_scan_x4_buf.vbe dp_sff_x4.ap dp_sff_x4.vbe dp_sff_x4_buf.ap dp_sff_x4_buf.vbe dp_sxlib.lef dp_ts_x4.ap dp_ts_x4.vbe dp_ts_x4_buf.ap dp_ts_x4_buf.vbe dp_ts_x8.ap dp_ts_x8.vbe dp_ts_x8_buf.ap dp_ts_x8_buf.vbe + +diff --git a/alliance/src/cells/src/mpxlib/Makefile.am b/alliance/src/cells/src/mpxlib/Makefile.am +index 9469aab..47166af 100644 +--- a/alliance/src/cells/src/mpxlib/Makefile.am ++++ b/alliance/src/cells/src/mpxlib/Makefile.am +@@ -1,5 +1,5 @@ + +-mpxlibdir=$(prefix)/cells/mpxlib ++mpxlibdir=$(pkgdatadir)/cells/mpxlib + + mpxlib_DATA=CATAL \ + pck_mpx.ap \ +diff --git a/alliance/src/cells/src/msxlib/Makefile.am b/alliance/src/cells/src/msxlib/Makefile.am +index d67fc5b..5300de0 100644 +--- a/alliance/src/cells/src/msxlib/Makefile.am ++++ b/alliance/src/cells/src/msxlib/Makefile.am +@@ -1,5 +1,5 @@ + +-msxlibdir=$(prefix)/cells/msxlib ++msxlibdir=$(pkgdatadir)/cells/msxlib + + msxlib_DATA=CATAL \ + an2_x05.ap \ +diff --git a/alliance/src/cells/src/padlib/Makefile.am b/alliance/src/cells/src/padlib/Makefile.am +index 9b14265..b28a371 100644 +--- a/alliance/src/cells/src/padlib/Makefile.am ++++ b/alliance/src/cells/src/padlib/Makefile.am +@@ -1,6 +1,6 @@ + # $Id: Makefile.am,v 1.4 2002/05/08 21:07:24 jpc Exp $ + +-padlibdir=$(prefix)/cells/padlib ++padlibdir=$(pkgdatadir)/cells/padlib + + padlib_DATA=CATAL corner_sp.ap corner_sp.vbe padreal.ap padreal.cif padsymb.db palck_sp.ap pali_sp.ap paliot_sp.ap paliotw_sp.ap palo_sp.ap palot_sp.ap palotw_sp.ap palow_sp.ap palvdde_sp.ap palvddeck_sp.ap palvddi_sp.ap palvddick_sp.ap palvsse_sp.ap palvsseck_sp.ap palvssi_sp.ap palvssick_sp.ap pck_sp.al pck_sp.ap pck_sp.vbe pi_sp.al pi_sp.ap pi_sp.vbe piot_sp.al piot_sp.ap piot_sp.vbe piotw_sp.al piotw_sp.ap piotw_sp.vbe po_sp.al po_sp.ap po_sp.vbe pot_sp.al pot_sp.ap pot_sp.vbe potw_sp.al potw_sp.ap potw_sp.vbe pow_sp.al pow_sp.ap pow_sp.vbe pvdde_sp.al pvdde_sp.ap pvdde_sp.vbe pvddeck_sp.al pvddeck_sp.ap pvddeck_sp.vbe pvddi_sp.al pvddi_sp.ap pvddi_sp.vbe pvddick_sp.al pvddick_sp.ap pvddick_sp.vbe pvsse_sp.al pvsse_sp.ap pvsse_sp.vbe pvsseck_sp.al pvsseck_sp.ap pvsseck_sp.vbe pvssi_sp.al pvssi_sp.ap pvssi_sp.vbe pvssick_sp.al pvssick_sp.ap pvssick_sp.vbe + +diff --git a/alliance/src/cells/src/pxlib/Makefile.am b/alliance/src/cells/src/pxlib/Makefile.am +index 3a2ed65..d0f631f 100644 +--- a/alliance/src/cells/src/pxlib/Makefile.am ++++ b/alliance/src/cells/src/pxlib/Makefile.am +@@ -1,6 +1,6 @@ + # $Id: Makefile.am,v 1.2 2005/11/08 10:13:51 franck Exp $ + +-pxlibdir=$(prefix)/cells/pxlib ++pxlibdir=$(pkgdatadir)/cells/pxlib + + pxlib_DATA=CATAL \ + pck_px.ap \ +diff --git a/alliance/src/cells/src/ramlib/Makefile.am b/alliance/src/cells/src/ramlib/Makefile.am +index 66febd9..63a92ff 100644 +--- a/alliance/src/cells/src/ramlib/Makefile.am ++++ b/alliance/src/cells/src/ramlib/Makefile.am +@@ -1,6 +1,6 @@ + # $Id: Makefile.am,v 1.1 2002/07/15 22:23:32 jpc Exp $ + +-ramlibdir = $(prefix)/cells/ramlib ++ramlibdir = $(pkgdatadir)/cells/ramlib + + ramlib_DATA = ramlib.lef \ + CATAL \ +diff --git a/alliance/src/cells/src/rf2lib/Makefile.am b/alliance/src/cells/src/rf2lib/Makefile.am +index fd9318a..fc80cd3 100644 +--- a/alliance/src/cells/src/rf2lib/Makefile.am ++++ b/alliance/src/cells/src/rf2lib/Makefile.am +@@ -1,6 +1,6 @@ + # $Id: Makefile.am,v 1.2 2004/09/29 21:50:28 jpc Exp $ + +-rf2libdir=$(prefix)/cells/rf2lib ++rf2libdir=$(pkgdatadir)/cells/rf2lib + + rf2lib_DATA=CATAL \ + rf2lib.lef \ +diff --git a/alliance/src/cells/src/rflib/Makefile.am b/alliance/src/cells/src/rflib/Makefile.am +index 33ee5ac..6f8ffa7 100644 +--- a/alliance/src/cells/src/rflib/Makefile.am ++++ b/alliance/src/cells/src/rflib/Makefile.am +@@ -1,6 +1,6 @@ + # $Id: Makefile.am,v 1.4 2002/05/08 21:07:24 jpc Exp $ + +-rflibdir=$(prefix)/cells/rflib ++rflibdir=$(pkgdatadir)/cells/rflib + + rflib_DATA=CATAL rf_dec_bufad0.ap rf_dec_bufad0.vbe rf_dec_bufad1.ap rf_dec_bufad1.vbe rf_dec_bufad2.ap rf_dec_bufad2.vbe rf_dec_nand2.ap rf_dec_nand2.vbe rf_dec_nand3.ap rf_dec_nand3.vbe rf_dec_nand4.ap rf_dec_nand4.vbe rf_dec_nao3.ap rf_dec_nao3.vbe rf_dec_nbuf.ap rf_dec_nbuf.vbe rf_dec_nor3.ap rf_dec_nor3.vbe rf_fifo_buf.ap rf_fifo_buf.vbe rf_fifo_clock.ap rf_fifo_clock.vbe rf_fifo_empty.ap rf_fifo_empty.vbe rf_fifo_full.ap rf_fifo_full.vbe rf_fifo_inc.ap rf_fifo_inc.vbe rf_fifo_nop.ap rf_fifo_nop.vbe rf_fifo_ok.ap rf_fifo_ok.vbe rf_fifo_orand4.ap rf_fifo_orand4.vbe rf_fifo_orand5.ap rf_fifo_orand5.vbe rf_fifo_ptreset.ap rf_fifo_ptreset.vbe rf_fifo_ptset.ap rf_fifo_ptset.vbe rf_inmux_buf_2.ap rf_inmux_buf_2.vbe rf_inmux_buf_4.ap rf_inmux_buf_4.vbe rf_inmux_mem.ap rf_inmux_mem.vbe rf_mid_buf_2.ap rf_mid_buf_2.vbe rf_mid_buf_4.ap rf_mid_buf_4.vbe rf_mid_mem.ap rf_mid_mem.vbe rf_mid_mem_r0.ap rf_mid_mem_r0.vbe rf_out_buf_2.ap rf_out_buf_2.vbe rf_out_buf_4.ap rf_out_buf_4.vbe rf_out_mem.ap rf_out_mem.vbe rflib.lef + +diff --git a/alliance/src/cells/src/romlib/Makefile.am b/alliance/src/cells/src/romlib/Makefile.am +index 578081e..b9ae364 100644 +--- a/alliance/src/cells/src/romlib/Makefile.am ++++ b/alliance/src/cells/src/romlib/Makefile.am +@@ -1,6 +1,6 @@ + # $Id: Makefile.am,v 1.2 2006/06/07 19:20:03 jpc Exp $ + +-romlibdir = $(prefix)/cells/romlib ++romlibdir = $(pkgdatadir)/cells/romlib + + romlib_DATA = romlib.lef \ + CATAL \ +diff --git a/alliance/src/cells/src/sxlib/Makefile.am b/alliance/src/cells/src/sxlib/Makefile.am +index fdadefe..ef8957c 100644 +--- a/alliance/src/cells/src/sxlib/Makefile.am ++++ b/alliance/src/cells/src/sxlib/Makefile.am +@@ -1,12 +1,12 @@ + # $Id: Makefile.am,v 1.5 2002/05/08 21:07:24 jpc Exp $ + +-sxlibvbedir=$(prefix)/cells/sxlib +-sxlibapdir=$(prefix)/cells/sxlib +-sxlibaldir=$(prefix)/cells/sxlib +-sxlibdatdir=$(prefix)/cells/sxlib +-sxlibvhddir=$(prefix)/cells/sxlib +-sxlibetcdir=$(prefix)/cells/sxlib +-sxlibsymdir=$(prefix)/cells/sxlib ++sxlibvbedir=$(pkgdatadir)/cells/sxlib ++sxlibapdir=$(pkgdatadir)/cells/sxlib ++sxlibaldir=$(pkgdatadir)/cells/sxlib ++sxlibdatdir=$(pkgdatadir)/cells/sxlib ++sxlibvhddir=$(pkgdatadir)/cells/sxlib ++sxlibetcdir=$(pkgdatadir)/cells/sxlib ++sxlibsymdir=$(pkgdatadir)/cells/sxlib + + sxlibvbe_DATA = a2_x2.vbe a2_x4.vbe a3_x2.vbe a3_x4.vbe \ + a4_x2.vbe a4_x4.vbe an12_x1.vbe an12_x4.vbe ao22_x2.vbe \ +-- +2.5.0 + diff --git a/0004-Misc-installation-dirs-fixes.patch b/0004-Misc-installation-dirs-fixes.patch new file mode 100644 index 0000000..947f9e3 --- /dev/null +++ b/0004-Misc-installation-dirs-fixes.patch @@ -0,0 +1,316 @@ +From d0a8e157bca76b7686d632e15f6360e549241dbf Mon Sep 17 00:00:00 2001 +From: =?UTF-8?q?Ralf=20Cors=C3=A9pius?= +Date: Mon, 29 Feb 2016 14:53:11 +0100 +Subject: [PATCH 04/10] Misc installation dirs fixes. + +--- + alliance/src/attila/doc/Makefile.am | 1 - + alliance/src/attila/doc/attila/Makefile.am | 5 +---- + alliance/src/attila/etc/Makefile.am | 2 +- + alliance/src/distrib/etc/Makefile.am | 4 ++-- + alliance/src/documentation/Makefile.am | 5 +---- + alliance/src/documentation/tutorials/Makefile.am | 2 +- + alliance/src/dreal/etc/Makefile.am | 2 +- + alliance/src/elp/etc/Makefile.am | 2 +- + alliance/src/genlib/doc/Makefile.am | 1 - + alliance/src/genlib/doc/genlib/Makefile.am | 2 +- + alliance/src/graal/etc/Makefile.am | 2 +- + alliance/src/mbk/etc/Makefile.am | 2 +- + alliance/src/nero/doc/Makefile.am | 1 - + alliance/src/nero/doc/nero/Makefile.am | 5 +---- + alliance/src/rds/etc/Makefile.am | 2 +- + alliance/src/scapin/etc/Makefile.am | 2 +- + alliance/src/sea/etc/Makefile.am | 2 +- + alliance/src/xfsm/etc/Makefile.am | 2 +- + alliance/src/xgra/etc/Makefile.am | 2 +- + alliance/src/xpat/etc/Makefile.am | 2 +- + alliance/src/xsch/etc/Makefile.am | 2 +- + alliance/src/xvpn/etc/Makefile.am | 2 +- + 22 files changed, 20 insertions(+), 32 deletions(-) + +diff --git a/alliance/src/attila/doc/Makefile.am b/alliance/src/attila/doc/Makefile.am +index ff3f0f1..46665bd 100644 +--- a/alliance/src/attila/doc/Makefile.am ++++ b/alliance/src/attila/doc/Makefile.am +@@ -1,7 +1,6 @@ + + SUBDIRS = attila man1 + +-pdfdir = $(prefix)/doc/pdf + pdf_DATA = attila.pdf + + EXTRA_DIST = $(pdf_DATA) \ +diff --git a/alliance/src/attila/doc/attila/Makefile.am b/alliance/src/attila/doc/attila/Makefile.am +index d342379..86e7e1e 100644 +--- a/alliance/src/attila/doc/attila/Makefile.am ++++ b/alliance/src/attila/doc/attila/Makefile.am +@@ -1,12 +1,9 @@ + + +-pkghtmldir = $(prefix)/doc/html/@PACKAGE@ ++pkghtmldir = $(htmldir)/@PACKAGE@ + pkghtml_DATA = \ + ./attila.html \ + ./ref_attila.html \ + ./man_attila.html + + EXTRA_DIST = $(pkghtml_DATA) +- +-install-data-hook: +- find $(DESTDIR)$(prefix)/doc/html/@PACKAGE@ -type f | xargs chmod g+w +diff --git a/alliance/src/attila/etc/Makefile.am b/alliance/src/attila/etc/Makefile.am +index b69a787..0902c40 100644 +--- a/alliance/src/attila/etc/Makefile.am ++++ b/alliance/src/attila/etc/Makefile.am +@@ -1,4 +1,4 @@ +-etcdir = $(prefix)/etc ++etcdir=$(sysconfdir)/alliance + + etc_DATA = attila.conf + +diff --git a/alliance/src/distrib/etc/Makefile.am b/alliance/src/distrib/etc/Makefile.am +index 39d2d29..f84b52b 100644 +--- a/alliance/src/distrib/etc/Makefile.am ++++ b/alliance/src/distrib/etc/Makefile.am +@@ -1,7 +1,7 @@ + # $Id: Makefile.am,v 1.9 2012/05/03 15:32:24 jpc Exp $ + +-etcdir=$(sysconfdir)/profile.d ++profileddir=$(sysconfdir)/profile.d + +-etc_SCRIPTS=alc_env.csh alc_env.sh ++profiled_DATA=alc_env.csh alc_env.sh + + EXTRA_DIST=alc_env.csh.in alc_env.sh.in +diff --git a/alliance/src/documentation/Makefile.am b/alliance/src/documentation/Makefile.am +index f937897..5a2c299 100644 +--- a/alliance/src/documentation/Makefile.am ++++ b/alliance/src/documentation/Makefile.am +@@ -1,9 +1,6 @@ + + SUBDIRS = tutorials + +- +-docdir = $(prefix)/doc +- + nobase_doc_DATA = overview/datapath.gif \ + overview/genview.gif \ + overview/graal.gif \ +@@ -51,7 +48,7 @@ nobase_doc_DATA = overview/datapath.gif \ + design-flow/xpat.gif \ + design-flow/xsch.gif + +-examplesdir = $(prefix)/examples ++examplesdir = $(docdir)/examples + + nobase_examples_DATA = regression.sh \ + alliance-examples/go-all.sh \ +diff --git a/alliance/src/documentation/tutorials/Makefile.am b/alliance/src/documentation/tutorials/Makefile.am +index f97c255..547c094 100644 +--- a/alliance/src/documentation/tutorials/Makefile.am ++++ b/alliance/src/documentation/tutorials/Makefile.am +@@ -1,5 +1,5 @@ + +-tutorialsdir = $(prefix)/tutorials ++tutorialsdir = $(docdir)/tutorials + + nobase_tutorials_DATA = place_and_route/src/Makefile \ + place_and_route/src/amd2901/Makefile \ +diff --git a/alliance/src/dreal/etc/Makefile.am b/alliance/src/dreal/etc/Makefile.am +index debdb76..3e3d097 100644 +--- a/alliance/src/dreal/etc/Makefile.am ++++ b/alliance/src/dreal/etc/Makefile.am +@@ -1,6 +1,6 @@ + # $Id: Makefile.am,v 1.5 2002/05/08 21:07:25 jpc Exp $ + +-etcdir=$(prefix)/etc ++etcdir=$(sysconfdir)/alliance + + etc_DATA=cmos.dreal + +diff --git a/alliance/src/elp/etc/Makefile.am b/alliance/src/elp/etc/Makefile.am +index b8ef276..c833a67 100644 +--- a/alliance/src/elp/etc/Makefile.am ++++ b/alliance/src/elp/etc/Makefile.am +@@ -1,6 +1,6 @@ + # $Id: Makefile.am,v 1.5 2002/05/08 21:07:25 jpc Exp $ + +-etcdir=$(prefix)/etc ++etcdir=$(sysconfdir)/alliance + + etc_DATA=prol.elp + +diff --git a/alliance/src/genlib/doc/Makefile.am b/alliance/src/genlib/doc/Makefile.am +index ec53916..b4e44c5 100644 +--- a/alliance/src/genlib/doc/Makefile.am ++++ b/alliance/src/genlib/doc/Makefile.am +@@ -1,7 +1,6 @@ + + SUBDIRS = genlib + +-pdfdir = $(prefix)/doc/pdf + pdf_DATA = genlib.pdf + + EXTRA_DIST = $(pdf_DATA) \ +diff --git a/alliance/src/genlib/doc/genlib/Makefile.am b/alliance/src/genlib/doc/genlib/Makefile.am +index 448eabb..b398869 100644 +--- a/alliance/src/genlib/doc/genlib/Makefile.am ++++ b/alliance/src/genlib/doc/genlib/Makefile.am +@@ -1,6 +1,6 @@ + + +-pkghtmldir = $(prefix)/doc/html/@PACKAGE@ ++pkghtmldir = $(htmldir)/@PACKAGE@ + pkghtml_DATA = \ + ./genlib.html \ + ./ref_genlib.html \ +diff --git a/alliance/src/graal/etc/Makefile.am b/alliance/src/graal/etc/Makefile.am +index 3ca5068..dfec7cb 100644 +--- a/alliance/src/graal/etc/Makefile.am ++++ b/alliance/src/graal/etc/Makefile.am +@@ -1,6 +1,6 @@ + # $Id: Makefile.am,v 1.6 2002/05/08 21:07:25 jpc Exp $ + +-etcdir=$(prefix)/etc ++etcdir=$(sysconfdir)/alliance + + etc_DATA=cmos.graal + +diff --git a/alliance/src/mbk/etc/Makefile.am b/alliance/src/mbk/etc/Makefile.am +index 2e75ab1..ba1b61d 100644 +--- a/alliance/src/mbk/etc/Makefile.am ++++ b/alliance/src/mbk/etc/Makefile.am +@@ -1,6 +1,6 @@ + # $Id: Makefile.am,v 1.4 2002/05/08 21:07:25 jpc Exp $ + +-etcdir=$(prefix)/etc ++etcdir=$(sysconfdir)/alliance + + etc_DATA=spimodel.cfg + +diff --git a/alliance/src/nero/doc/Makefile.am b/alliance/src/nero/doc/Makefile.am +index 0c33137..56d01bc 100644 +--- a/alliance/src/nero/doc/Makefile.am ++++ b/alliance/src/nero/doc/Makefile.am +@@ -1,7 +1,6 @@ + + SUBDIRS = nero man1 + +-pdfdir = $(prefix)/doc/pdf + pdf_DATA = nero.pdf + + EXTRA_DIST = $(pdf_DATA) \ +diff --git a/alliance/src/nero/doc/nero/Makefile.am b/alliance/src/nero/doc/nero/Makefile.am +index 11d58e1..8e29a17 100644 +--- a/alliance/src/nero/doc/nero/Makefile.am ++++ b/alliance/src/nero/doc/nero/Makefile.am +@@ -1,12 +1,9 @@ + + +-pkghtmldir = $(prefix)/doc/html/@PACKAGE@ ++pkghtmldir = $(htmldir)/@PACKAGE@ + pkghtml_DATA = \ + ./nero.html \ + ./ref_nero.html \ + ./man_nero.html + + EXTRA_DIST = $(pkghtml_DATA) +- +-install-data-hook: +- find $(DESTDIR)$(prefix)/doc/html/@PACKAGE@ -type f | xargs chmod g+w +diff --git a/alliance/src/rds/etc/Makefile.am b/alliance/src/rds/etc/Makefile.am +index d5cca76..fac05cd 100644 +--- a/alliance/src/rds/etc/Makefile.am ++++ b/alliance/src/rds/etc/Makefile.am +@@ -1,5 +1,5 @@ + +-etcdir=$(prefix)/etc ++etcdir=$(sysconfdir)/alliance + + etc_DATA=cmos.rds scn6m_deep_09.rds + +diff --git a/alliance/src/scapin/etc/Makefile.am b/alliance/src/scapin/etc/Makefile.am +index 9684d1f..ddb68bd 100644 +--- a/alliance/src/scapin/etc/Makefile.am ++++ b/alliance/src/scapin/etc/Makefile.am +@@ -1,6 +1,6 @@ + # $Id: Makefile.am,v 1.5 2002/05/08 21:07:26 jpc Exp $ + +-etcdir=$(prefix)/etc ++etcdir=$(sysconfdir)/alliance + + etc_DATA=sxlib.scapin + +diff --git a/alliance/src/sea/etc/Makefile.am b/alliance/src/sea/etc/Makefile.am +index d1f3aca..fab246b 100644 +--- a/alliance/src/sea/etc/Makefile.am ++++ b/alliance/src/sea/etc/Makefile.am +@@ -1,4 +1,4 @@ +-etcdir = $(prefix)/etc ++etcdir=$(sysconfdir)/alliance + + etc_DATA = se_defaults.mac cmos.lef + +diff --git a/alliance/src/xfsm/etc/Makefile.am b/alliance/src/xfsm/etc/Makefile.am +index 2b35b64..63387be 100644 +--- a/alliance/src/xfsm/etc/Makefile.am ++++ b/alliance/src/xfsm/etc/Makefile.am +@@ -1,6 +1,6 @@ + # $Id: Makefile.am,v 1.5 2002/05/08 21:07:26 jpc Exp $ + +-etcdir=$(prefix)/etc ++etcdir=$(sysconfdir)/alliance + + etc_DATA=xfsm.par + +diff --git a/alliance/src/xgra/etc/Makefile.am b/alliance/src/xgra/etc/Makefile.am +index 4c9feb5..37edcd1 100644 +--- a/alliance/src/xgra/etc/Makefile.am ++++ b/alliance/src/xgra/etc/Makefile.am +@@ -1,6 +1,6 @@ + # $Id: Makefile.am,v 1.1 2007/11/27 20:41:31 ludo Exp $ + +-etcdir=$(prefix)/etc ++etcdir=$(sysconfdir)/alliance + + etc_DATA=xgra.par + +diff --git a/alliance/src/xpat/etc/Makefile.am b/alliance/src/xpat/etc/Makefile.am +index 8f2fa0d..43175c2 100644 +--- a/alliance/src/xpat/etc/Makefile.am ++++ b/alliance/src/xpat/etc/Makefile.am +@@ -1,6 +1,6 @@ + # $Id: Makefile.am,v 1.6 2002/05/08 21:07:26 jpc Exp $ + +-etcdir=$(prefix)/etc ++etcdir=$(sysconfdir)/alliance + + etc_DATA=xpat.par + +diff --git a/alliance/src/xsch/etc/Makefile.am b/alliance/src/xsch/etc/Makefile.am +index 973ab38..2d88390 100644 +--- a/alliance/src/xsch/etc/Makefile.am ++++ b/alliance/src/xsch/etc/Makefile.am +@@ -1,6 +1,6 @@ + # $Id: Makefile.am,v 1.5 2002/05/08 21:07:26 jpc Exp $ + +-etcdir=$(prefix)/etc ++etcdir=$(sysconfdir)/alliance + + etc_DATA=xsch.par + +diff --git a/alliance/src/xvpn/etc/Makefile.am b/alliance/src/xvpn/etc/Makefile.am +index ba70004..f28560a 100644 +--- a/alliance/src/xvpn/etc/Makefile.am ++++ b/alliance/src/xvpn/etc/Makefile.am +@@ -1,6 +1,6 @@ + # $Id: Makefile.am,v 1.5 2002/05/08 21:07:26 jpc Exp $ + +-etcdir=$(prefix)/etc ++etcdir=$(sysconfdir)/alliance + + etc_DATA=xvpn.par + +-- +2.5.0 + diff --git a/0005-Use-inttypes-macros-to-print-int32_t.patch b/0005-Use-inttypes-macros-to-print-int32_t.patch new file mode 100644 index 0000000..f3c2d4b --- /dev/null +++ b/0005-Use-inttypes-macros-to-print-int32_t.patch @@ -0,0 +1,36 @@ +From 5305097fa027775bc96ae58e0e938a1ef85f1fff Mon Sep 17 00:00:00 2001 +From: =?UTF-8?q?Ralf=20Cors=C3=A9pius?= +Date: Sun, 28 Feb 2016 09:33:27 +0100 +Subject: [PATCH 05/10] Use inttypes-macros to print int32_t. + +--- + alliance/src/rds/src/gds_parse.c | 5 +++-- + 1 file changed, 3 insertions(+), 2 deletions(-) + +diff --git a/alliance/src/rds/src/gds_parse.c b/alliance/src/rds/src/gds_parse.c +index dfa2239..18e4ec6 100644 +--- a/alliance/src/rds/src/gds_parse.c ++++ b/alliance/src/rds/src/gds_parse.c +@@ -21,6 +21,7 @@ + # include + # include + # include ++# include + + # include + # include +@@ -742,9 +743,9 @@ FILE *fp; + } + } + if ((coord_nb < 5) || (ispolyrec(coord_tab, coord_nb) == 0)) { +- sprintf(texte, "(%ld, %ld", coord_tab[0].X, coord_tab[0].Y); ++ sprintf(texte, "(%" PRId32 ", %" PRId32 "", coord_tab[0].X, coord_tab[0].Y); + for (i = 1; i < coord_nb; i++) +- sprintf(&texte[strlen(texte)], ", %ld, %ld", coord_tab[i].X, coord_tab[i].Y); ++ sprintf(&texte[strlen(texte)], ", %" PRId32 ", %" PRId32 "", coord_tab[i].X, coord_tab[i].Y); + strcat(texte, ")"); + pv_emet_warning(pv_model->NAME, "Non rectangle polygon here", texte); + FLAG = -1; +-- +2.5.0 + diff --git a/0006-Use-ring_yy-instead-of-yy.patch b/0006-Use-ring_yy-instead-of-yy.patch new file mode 100644 index 0000000..9b1f7f1 --- /dev/null +++ b/0006-Use-ring_yy-instead-of-yy.patch @@ -0,0 +1,77 @@ +From b689820c62058c0e3b205efc0d604e15a128a5d4 Mon Sep 17 00:00:00 2001 +From: =?UTF-8?q?Ralf=20Cors=C3=A9pius?= +Date: Sun, 28 Feb 2016 09:31:44 +0100 +Subject: [PATCH 06/10] Use ring_yy instead of yy. + +--- + alliance/src/ring/src/lireplace.c | 2 +- + alliance/src/ring/src/ringram.y | 9 +++++++++ + alliance/src/ring/src/rinscan.l | 4 ++-- + alliance/src/ring/src/struct.h | 4 ++-- + 4 files changed, 14 insertions(+), 5 deletions(-) + +diff --git a/alliance/src/ring/src/lireplace.c b/alliance/src/ring/src/lireplace.c +index 296bb03..b057784 100644 +--- a/alliance/src/ring/src/lireplace.c ++++ b/alliance/src/ring/src/lireplace.c +@@ -100,7 +100,7 @@ void lecture_fic(char *nomfic, lofig_list *circuit_lo, + if (mode_debug) + printf("Avant analyse lex et yacc \n"); + +- yyin = mbkfopen(nomfic, NULL, READ_TEXT); ++ ring_yyin = mbkfopen(nomfic, NULL, READ_TEXT); + + /* ------------------------------------------------------------------ */ + /* lancement de lex et yacc pour interpreter le fichier de parametres */ +diff --git a/alliance/src/ring/src/ringram.y b/alliance/src/ring/src/ringram.y +index 1bb548c..677bd52 100644 +--- a/alliance/src/ring/src/ringram.y ++++ b/alliance/src/ring/src/ringram.y +@@ -51,3 +51,12 @@ lnomchiffre: lnomchiffre IDENT NOMBRE { declaration_width($2,$3);if (mode_debug) + | IDENT NOMBRE { declaration_width($1,$2);if (mode_debug) printf("yacc lnomchiffre \n");} + ; + ++%% ++ ++ ++void ++yyerror (char const *s) ++{ ++ ++ fprintf (stderr, "%s\n", s); ++} +diff --git a/alliance/src/ring/src/rinscan.l b/alliance/src/ring/src/rinscan.l +index 2c74c9e..a98e354 100644 +--- a/alliance/src/ring/src/rinscan.l ++++ b/alliance/src/ring/src/rinscan.l +@@ -24,10 +24,10 @@ comment [#]({lettre}*{chiffre}*{esp}*{pct}*)*{rc} + "west" {if (mode_debug) ECHO; return(M_WEST) ;} + "east" {if (mode_debug) ECHO; return(M_EAST) ;} + "width" {if (mode_debug) ECHO; return(M_WIDTH);} +-{nombre} {if (mode_debug) ECHO; sscanf(yytext,"%ld",&yylval.i); ++{nombre} {if (mode_debug) ECHO; sscanf(yytext,"%ld",&ring_yylval.i); + return(NOMBRE); + } +-{ident} {if (mode_debug) ECHO; yylval.s = namealloc(yytext); ++{ident} {if (mode_debug) ECHO; ring_yylval.s = namealloc(yytext); + return(IDENT); + } + {comment} {if (mode_debug) {ECHO; printf("commentaire\n");}} +diff --git a/alliance/src/ring/src/struct.h b/alliance/src/ring/src/struct.h +index 0d54a94..1cb5b7a 100644 +--- a/alliance/src/ring/src/struct.h ++++ b/alliance/src/ring/src/struct.h +@@ -321,8 +321,8 @@ extern char *pvssi_p; + + extern char *nom_fic_param; /* nom du fichier parametre */ + +-extern FILE *yyin; /* pointeur sur fichier lex */ +-extern int yylineno; /* no de la ligne traitee par lex */ ++extern FILE *ring_yyin; /* pointeur sur fichier lex */ ++extern int ring_yylineno; /* no de la ligne traitee par lex */ + extern chain_list *nom_plot[NB_FACES]; /* liste pour l'analyseur des noms de + plots */ + extern chain_list *liste_width; /* liste pour l'analyseur des noms +-- +2.5.0 + diff --git a/0007-Eliminate-CFLAGS.patch b/0007-Eliminate-CFLAGS.patch new file mode 100644 index 0000000..331593d --- /dev/null +++ b/0007-Eliminate-CFLAGS.patch @@ -0,0 +1,62 @@ +From 6c48c76ab601dd1f608e716bc598e16794b42789 Mon Sep 17 00:00:00 2001 +From: =?UTF-8?q?Ralf=20Cors=C3=A9pius?= +Date: Wed, 24 Feb 2016 08:03:54 +0100 +Subject: [PATCH 07/10] Eliminate CFLAGS. + +--- + alliance/src/druc/src/Makefile.am | 5 ++--- + alliance/src/m2e/src/Makefile.am | 2 +- + alliance/src/nero/src/Makefile.am | 3 --- + 3 files changed, 3 insertions(+), 7 deletions(-) + +diff --git a/alliance/src/druc/src/Makefile.am b/alliance/src/druc/src/Makefile.am +index 16ecb34..bb31154 100644 +--- a/alliance/src/druc/src/Makefile.am ++++ b/alliance/src/druc/src/Makefile.am +@@ -8,7 +8,8 @@ drucompi.h drucring.c drucring.h drucutil.c drucutil.h vmcaract.c vmcaract.h \ + vmcasmld.c vmcasmld.h vmcerror.c vmcerror.h vmcmesur.c vmcmesur.h vmcrelat.c \ + vmcrelat.h vmctools.c vmctools.h vmcunify.c vmcunify.h + +-CFLAGS = $(ALLIANCE_CFLAGS) -g -O0 ++AM_CFLAGS = $(ALLIANCE_CFLAGS) ++AM_CPPFLAGS = -I$(top_srcdir)/mbk/src -I$(top_srcdir)/rds/src + libVrd_la_LDFLAGS = -version-info @VRD_DLL_VERSION@ + libVrd_la_LIBADD = -lRds -lMut + +@@ -22,8 +23,6 @@ drucompi_l.c : $(srcdir)/drucompi_l.l drucompi_y.h + + bin_PROGRAMS = druc + +-AM_CFLAGS = -I$(top_srcdir)/mbk/src -I$(top_srcdir)/rds/src +- + druc_LDADD = $(ALLIANCE_LIBS) -L. libVrd.la \ + -L$(builddir)/../../rds/src/.libs -lRds \ + -L$(builddir)/../../mbk/src/.libs -lMpu -lMut +diff --git a/alliance/src/m2e/src/Makefile.am b/alliance/src/m2e/src/Makefile.am +index 969bc1a..04a817b 100644 +--- a/alliance/src/m2e/src/Makefile.am ++++ b/alliance/src/m2e/src/Makefile.am +@@ -1,6 +1,6 @@ + ## Process this file with automake to produce Makefile.in + +-AM_CFLAGS = -g -I$(top_srcdir)/mbk/src ++AM_CFLAGS = -I$(top_srcdir)/mbk/src + + bin_PROGRAMS = m2e + +diff --git a/alliance/src/nero/src/Makefile.am b/alliance/src/nero/src/Makefile.am +index 71e2810..f3a5abd 100644 +--- a/alliance/src/nero/src/Makefile.am ++++ b/alliance/src/nero/src/Makefile.am +@@ -1,8 +1,5 @@ + ## Process this file with automake to produce Makefile.in + +-#CXXFLAGS = -g -pg -O2 +-CXXFLAGS = -g -O2 +-#CXXFLAGS = -O2 + AM_CXXFLAGS = @ALLIANCE_CFLAGS@ \ + -I$(top_srcdir)/abl/src \ + -I$(top_srcdir)/aut/src \ +-- +2.5.0 + diff --git a/0008-Rework-Makefile.ams.patch b/0008-Rework-Makefile.ams.patch new file mode 100644 index 0000000..5cf87b0 --- /dev/null +++ b/0008-Rework-Makefile.ams.patch @@ -0,0 +1,1923 @@ +From 9346ac619fd8314e023ac3cc658119358945d872 Mon Sep 17 00:00:00 2001 +From: =?UTF-8?q?Ralf=20Cors=C3=A9pius?= +Date: Sun, 28 Feb 2016 09:44:14 +0100 +Subject: [PATCH 08/10] Rework Makefile.ams. + +--- + alliance/src/abe/src/Makefile.am | 7 ++++-- + alliance/src/abl/src/Makefile.am | 6 +++-- + alliance/src/abt/src/Makefile.am | 9 +++++-- + alliance/src/abv/src/Makefile.am | 10 ++++++-- + alliance/src/alcban/src/Makefile.am | 7 +++--- + alliance/src/asimut/src/Makefile.am | 16 +++--------- + alliance/src/aut/src/Makefile.am | 5 ++-- + alliance/src/b2f/src/Makefile.am | 31 +++++++++++------------ + alliance/src/bdd/src/Makefile.am | 4 +-- + alliance/src/beh/src/Makefile.am | 4 +-- + alliance/src/bhl/src/Makefile.am | 10 ++++++-- + alliance/src/boog/src/Makefile.am | 27 ++++++++++---------- + alliance/src/btr/src/Makefile.am | 7 ++++-- + alliance/src/bvl/src/Makefile.am | 13 ++++++++-- + alliance/src/ctl/src/Makefile.am | 5 ++-- + alliance/src/ctp/src/Makefile.am | 16 +++++++++--- + alliance/src/druc/src/Makefile.am | 13 ++++++---- + alliance/src/elp/src/Makefile.am | 9 +++++-- + alliance/src/exp/src/Makefile.am | 4 +-- + alliance/src/fks/src/Makefile.am | 9 +++++-- + alliance/src/flatbeh/src/Makefile.am | 14 +++-------- + alliance/src/flatph/src/Makefile.am | 12 ++++----- + alliance/src/fmi/src/Makefile.am | 24 +++++++++--------- + alliance/src/fsm/src/Makefile.am | 8 ++++-- + alliance/src/fsp/src/Makefile.am | 15 +++-------- + alliance/src/ftl/src/Makefile.am | 22 ++++++++++++++--- + alliance/src/fvh/src/Makefile.am | 11 +++++++-- + alliance/src/genlib/src/Makefile.am | 10 +++++--- + alliance/src/genpat/src/Makefile.am | 6 +++-- + alliance/src/graal/src/Makefile.am | 12 ++++----- + alliance/src/k2f/src/Makefile.am | 15 +++-------- + alliance/src/l2p/src/Makefile.am | 7 +++--- + alliance/src/log/src/Makefile.am | 5 ++-- + alliance/src/loon/src/Makefile.am | 16 ++++-------- + alliance/src/lvx/src/Makefile.am | 7 +++--- + alliance/src/lynx/src/Makefile.am | 11 +++------ + alliance/src/mbk/src/Makefile.am | 10 +++++--- + alliance/src/mips_asm/src/Makefile.am | 11 +++------ + alliance/src/mocha/src/Makefile.am | 41 +++++++++++++++--------------- + alliance/src/nero/src/Makefile.am | 22 +++++------------ + alliance/src/ocp/src/placer/Makefile.am | 31 ++++++++++++----------- + alliance/src/pat/src/Makefile.am | 7 ++++-- + alliance/src/pat2spi/src/Makefile.am | 8 +++--- + alliance/src/proof/src/Makefile.am | 18 ++++++-------- + alliance/src/rds/src/Makefile.am | 4 +-- + alliance/src/ring/src/Makefile.am | 26 ++++++++++--------- + alliance/src/rtd/src/Makefile.am | 7 ++++-- + alliance/src/rtn/src/Makefile.am | 7 ++++-- + alliance/src/s2r/src/Makefile.am | 17 +++++++------ + alliance/src/scapin/src/Makefile.am | 9 +++---- + alliance/src/scl/src/Makefile.am | 15 ++++++++--- + alliance/src/sea/src/Makefile.am | 15 ++++------- + alliance/src/syf/src/Makefile.am | 27 ++++++++++---------- + alliance/src/vasy/src/Makefile.am | 44 ++++++++++++++++----------------- + alliance/src/vbh/src/Makefile.am | 9 +++++-- + alliance/src/vex/src/Makefile.am | 6 +++-- + alliance/src/vpn/src/Makefile.am | 7 ++++-- + alliance/src/x2y/src/Makefile.am | 16 +++++++----- + alliance/src/xfsm/src/Makefile.am | 25 +++++++++---------- + alliance/src/xgra/src/Makefile.am | 8 +++--- + alliance/src/xpat/src/Makefile.am | 18 +++++++------- + alliance/src/xsch/src/Makefile.am | 23 ++++++++--------- + alliance/src/xvpn/src/Makefile.am | 18 +++++++------- + 63 files changed, 455 insertions(+), 401 deletions(-) + +diff --git a/alliance/src/abe/src/Makefile.am b/alliance/src/abe/src/Makefile.am +index 8b29638..10cff00 100644 +--- a/alliance/src/abe/src/Makefile.am ++++ b/alliance/src/abe/src/Makefile.am +@@ -1,7 +1,10 @@ +-AM_CFLAGS = -I$(top_srcdir)/mbk/src -I$(top_srcdir)/aut/src -I$(top_srcdir)/abl/src ++AM_CPPFLAGS = -I$(top_srcdir)/mbk/src -I$(top_srcdir)/aut/src -I$(top_srcdir)/abl/src + lib_LTLIBRARIES = libAbe.la + include_HEADERS = abe.h + libAbe_la_SOURCES = abe.h beh_del.c beh_error.c beh_getgenva.c beh_rmv.c beh_view.c \ + beh_add.c beh_dict.c beh_fre.c beh_message.c beh_toolbug.c + libAbe_la_LDFLAGS = -version-info @ABE_DLL_VERSION@ +-libAbe_la_LIBADD = -lAbl -lAut -lMut ++libAbe_la_LIBADD = ++libAbe_la_LIBADD += $(top_builddir)/abl/src/libAbl.la ++libAbe_la_LIBADD += $(top_builddir)/aut/src/libAut.la ++libAbe_la_LIBADD += $(top_builddir)/mbk/src/libMut.la +diff --git a/alliance/src/abl/src/Makefile.am b/alliance/src/abl/src/Makefile.am +index bae65f3..44462ab 100644 +--- a/alliance/src/abl/src/Makefile.am ++++ b/alliance/src/abl/src/Makefile.am +@@ -1,4 +1,4 @@ +-AM_CFLAGS = -I$(top_srcdir)/mbk/src -I$(top_srcdir)/aut/src ++AM_CPPFLAGS = -I$(top_srcdir)/mbk/src -I$(top_srcdir)/aut/src + lib_LTLIBRARIES = libAbl.la + include_HEADERS = abl.h + libAbl_la_SOURCES = abldel.h ablflat.h abloptim.h ablunflat.h \ +@@ -12,4 +12,6 @@ libAbl_la_SOURCES = abldel.h ablflat.h abloptim.h ablunflat.h + ablctlsimp.h ablerror.h ablmap.h ablsubst.h \ + abldel.c ablflat.c abloptim.c ablunflat.c + libAbl_la_LDFLAGS = -version-info @ABL_DLL_VERSION@ +-libAbl_la_LIBADD = -lAut -lMut ++libAbl_la_LIBADD = ++libAbl_la_LIBADD += $(top_builddir)/aut/src/libAut.la ++libAbl_la_LIBADD += $(top_builddir)/mbk/src/libMut.la +diff --git a/alliance/src/abt/src/Makefile.am b/alliance/src/abt/src/Makefile.am +index 28da65d..a22b830 100644 +--- a/alliance/src/abt/src/Makefile.am ++++ b/alliance/src/abt/src/Makefile.am +@@ -1,4 +1,4 @@ +-AM_CFLAGS = -I$(top_srcdir)/mbk/src \ ++AM_CPPFLAGS = -I$(top_srcdir)/mbk/src \ + -I$(top_srcdir)/aut/src \ + -I$(top_srcdir)/abl/src \ + -I$(top_srcdir)/bdd/src \ +@@ -9,4 +9,9 @@ libAbt_la_SOURCES = abt.h bhl_depend.c bhl_freabl.c bhl_makgex.c \ + bhl_delaux.c bhl_error.c bhl_makbdd.c bhl_orderbdd.c \ + bhl_delaux.h bhl_error.h bhl_makbdd.h bhl_orderbdd.h + libAbt_la_LDFLAGS = -version-info @ABT_DLL_VERSION@ +-libAbt_la_LIBADD = -lBdd -lAbe -lAbl -lAut -lMut ++libAbt_la_LIBADD = ++libAbt_la_LIBADD += $(top_builddir)/bdd/src/libBdd.la ++libAbt_la_LIBADD += $(top_builddir)/abe/src/libAbe.la ++libAbt_la_LIBADD += $(top_builddir)/abl/src/libAbl.la ++libAbt_la_LIBADD += $(top_builddir)/aut/src/libAut.la ++libAbt_la_LIBADD += $(top_builddir)/mbk/src/libMut.la +diff --git a/alliance/src/abv/src/Makefile.am b/alliance/src/abv/src/Makefile.am +index 73e5fdb..d7ec3b6 100644 +--- a/alliance/src/abv/src/Makefile.am ++++ b/alliance/src/abv/src/Makefile.am +@@ -1,4 +1,4 @@ +-AM_CFLAGS = -I$(top_srcdir)/mbk/src \ ++AM_CPPFLAGS = -I$(top_srcdir)/mbk/src \ + -I$(top_srcdir)/aut/src \ + -I$(top_srcdir)/abl/src \ + -I$(top_srcdir)/bdd/src \ +@@ -9,7 +9,11 @@ libAbv_la_SOURCES = bvl_bcomp_y.y bvl_bcomp_l.l \ + abv.h bvl_bspec.c bvl_drive.c bvl_parse.h bvl_util.h \ + bvl_bedef.h bvl_bspec.h bvl_drive.h bvl_utdef.h bvl_utype.h \ + bvl_blex.h bvl_byacc.h bvl_parse.c bvl_util.c +-libAbv_la_LIBADD = -lAbe -lBdd -lMut ++libAbv_la_LIBADD = ++libAbv_la_LIBADD += $(top_builddir)/abe/src/libAbe.la ++libAbv_la_LIBADD += $(top_builddir)/bdd/src/libBdd.la ++libAbv_la_LIBADD += $(top_builddir)/mbk/src/libMut.la ++ + + CLEANFILES = bvl_bcomp_y.c bvl_bcomp_y.h bvl_bcomp_l.c + +@@ -21,3 +25,5 @@ bvl_bcomp_l.c : $(srcdir)/bvl_bcomp_l.l bvl_bcomp_y.h + $(LEX) -t $(srcdir)/bvl_bcomp_l.l | sed -e "s/yy/bvl_y_/g" -e "s/YY/BVL_Y_/g" > bvl_bcomp_l.c + + libAbv_la_LDFLAGS = -version-info @ABV_DLL_VERSION@ ++ ++CLEANFILES += y.tab.c y.tab.h +diff --git a/alliance/src/alcban/src/Makefile.am b/alliance/src/alcban/src/Makefile.am +index 033fa40..f6b02d4 100644 +--- a/alliance/src/alcban/src/Makefile.am ++++ b/alliance/src/alcban/src/Makefile.am +@@ -2,9 +2,10 @@ + + bin_PROGRAMS = alcbanner + +-AM_CFLAGS = @ALLIANCE_CFLAGS@ -I$(top_srcdir)/mbk/src ++AM_CFLAGS = @ALLIANCE_CFLAGS@ ++AM_CPPFLAGS = -I$(top_srcdir)/mbk/src + +-alcbanner_LDADD = @ALLIANCE_LIBS@ \ +- -L$(top_builddir)/mbk/src/.libs -lMut ++alcbanner_LDADD = @ALLIANCE_LIBS@ ++alcbanner_LDADD += $(top_builddir)/mbk/src/libMut.la + + alcbanner_SOURCES = alcbanner.c +diff --git a/alliance/src/asimut/src/Makefile.am b/alliance/src/asimut/src/Makefile.am +index d7b5e77..aaad8cf 100644 +--- a/alliance/src/asimut/src/Makefile.am ++++ b/alliance/src/asimut/src/Makefile.am +@@ -1,4 +1,4 @@ +-AM_CFLAGS = -I$(top_srcdir)/mbk/src \ ++AM_CPPFLAGS = -I$(top_srcdir)/mbk/src \ + -I$(top_srcdir)/log/src \ + -I$(top_srcdir)/beh/src \ + -I$(top_srcdir)/pat/src \ +@@ -17,20 +17,12 @@ libSch_la_SOURCES = sch_addshent.c sch_CrtSch.c sch_GetCTim.c sch.h sch_r + sch_bug.c sch_Free.c sch_GoNTim.c sch_message.c + + libSch_la_LDFLAGS = -version-info @SCH_DLL_VERSION@ +-libSch_la_LIBADD = -lMut ++libSch_la_LIBADD = $(top_builddir)/mbk/src/libMut.la + + bin_PROGRAMS = asimut + +-asimut_LDADD = -L. libSch.la -lBvl -lBhl \ +- -L$(top_builddir)/mbk/src \ +- -L$(top_builddir)/bvl/src \ +- -L$(top_builddir)/bhl/src \ +- -L$(top_builddir)/beh/src \ +- -L$(top_builddir)/pat/src \ +- -L$(top_builddir)/log/src \ +- -L$(top_builddir)/abl/src \ +- -L$(top_builddir)/aut/src \ +- -lAut -lAbl -lMlu -lRcn -lBvl -lBhl -lBeh -lPat -lLog -lMut ++asimut_LDADD = libSch.la $(top_builddir)/bvl/src/libBvl.la $(top_builddir)/bhl/src/libBhl.la \ ++ $(top_builddir)/aut/src/libAut.la $(top_builddir)/abl/src/libAbl.la $(top_builddir)/mbk/src/libMlu.la $(top_builddir)/mbk/src/libRcn.la $(top_builddir)/bvl/src/libBvl.la $(top_builddir)/bhl/src/libBhl.la $(top_builddir)/beh/src/libBeh.la $(top_builddir)/pat/src/libPat.la $(top_builddir)/log/src/libLog.la $(top_builddir)/mbk/src/libMut.la + + asimut_SOURCES = beh_delay.h c_fsyn_sr1k_56.c vh_debug.c vh_lspec.c vh_util.h vh_init.h \ + beh_setdelay.c c_fsyn_sr4k_10.c vh_debug.h vh_lspec.h vh_xcomm.c \ +diff --git a/alliance/src/aut/src/Makefile.am b/alliance/src/aut/src/Makefile.am +index d26d76a..ae9af96 100644 +--- a/alliance/src/aut/src/Makefile.am ++++ b/alliance/src/aut/src/Makefile.am +@@ -1,4 +1,4 @@ +-AM_CFLAGS = -I$(top_srcdir)/mbk/src ++AM_CPPFLAGS = -I$(top_srcdir)/mbk/src + lib_LTLIBRARIES = libAut.la + include_HEADERS = aut.h + libAut_la_SOURCES = autenv.h autfree.h authash2.h autsort.h \ +@@ -9,4 +9,5 @@ autdebug.h autexit.h authash.h autresize.h \ + autenv.c autfree.c authash2.c autsort.c + + libAut_la_LDFLAGS = -version-info @AUT_DLL_VERSION@ +-libAut_la_LIBADD = -lMut ++libAut_la_LIBADD = ++libAut_la_LIBADD += $(top_builddir)/mbk/src/libMut.la +diff --git a/alliance/src/b2f/src/Makefile.am b/alliance/src/b2f/src/Makefile.am +index 883d4af..9ef32d6 100644 +--- a/alliance/src/b2f/src/Makefile.am ++++ b/alliance/src/b2f/src/Makefile.am +@@ -2,7 +2,8 @@ + + bin_PROGRAMS = b2f + +-AM_CFLAGS = @ALLIANCE_CFLAGS@ -I$(top_srcdir)/abe/src \ ++AM_CFLAGS = @ALLIANCE_CFLAGS@ ++AM_CPPFLAGS = -I$(top_srcdir)/abe/src \ + -I$(top_srcdir)/abl/src \ + -I$(top_srcdir)/abt/src \ + -I$(top_srcdir)/abv/src \ +@@ -13,21 +14,19 @@ AM_CFLAGS = @ALLIANCE_CFLAGS@ -I$(top_srcdir)/abe/src \ + -I$(top_srcdir)/ftl/src \ + -I$(top_srcdir)/mbk/src + +-b2f_LDADD = @ALLIANCE_LIBS@ \ +--L$(top_builddir)/abt/src/.libs \ +--L$(top_builddir)/abv/src/.libs \ +--L$(top_builddir)/abe/src/.libs \ +--L$(top_builddir)/ftl/src/.libs \ +--L$(top_builddir)/fks/src/.libs \ +--L$(top_builddir)/fvh/src/.libs \ +--L$(top_builddir)/fsm/src/.libs \ +--L$(top_builddir)/btr/src/.libs \ +--L$(top_builddir)/bdd/src/.libs \ +--L$(top_builddir)/abl/src/.libs \ +--L$(top_builddir)/aut/src/.libs \ +--L$(top_builddir)/mbk/src/.libs \ +- -lAbt -lAbv -lAbe -lFtl -lFks -lFvh -lFsm \ +- -lBtr -lBdd -lAbl -lAut -lMut ++b2f_LDADD = @ALLIANCE_LIBS@ ++b2f_LDADD += $(top_builddir)/abt/src/libAbt.la ++b2f_LDADD += $(top_builddir)/abv/src/libAbv.la ++b2f_LDADD += $(top_builddir)/abe/src/libAbe.la ++b2f_LDADD += $(top_builddir)/ftl/src/libFtl.la ++b2f_LDADD += $(top_builddir)/fks/src/libFks.la ++b2f_LDADD += $(top_builddir)/fvh/src/libFvh.la ++b2f_LDADD += $(top_builddir)/fsm/src/libFsm.la ++b2f_LDADD += $(top_builddir)/btr/src/libBtr.la ++b2f_LDADD += $(top_builddir)/bdd/src/libBdd.la ++b2f_LDADD += $(top_builddir)/abl/src/libAbl.la ++b2f_LDADD += $(top_builddir)/aut/src/libAut.la ++b2f_LDADD += $(top_builddir)/mbk/src/libMut.la + + b2f_SOURCES = \ + b2f_beh2fsm.c b2f_error.c b2f_main.c \ +diff --git a/alliance/src/bdd/src/Makefile.am b/alliance/src/bdd/src/Makefile.am +index 8b4df4e..41bf95a 100644 +--- a/alliance/src/bdd/src/Makefile.am ++++ b/alliance/src/bdd/src/Makefile.am +@@ -1,4 +1,4 @@ +-AM_CFLAGS = -I$(top_srcdir)/mbk/src -I$(top_srcdir)/aut/src -I$(top_srcdir)/abl/src ++AM_CPPFLAGS = -I$(top_srcdir)/mbk/src -I$(top_srcdir)/aut/src -I$(top_srcdir)/abl/src + lib_LTLIBRARIES = libBdd.la + include_HEADERS = bdd.h + libBdd_la_SOURCES = bdd.h bddenv.h bddimply.h bddsimpdc.h \ +@@ -25,4 +25,4 @@ libBdd_la_SOURCES = bdd.h bddenv.h bddimply.h bddsimp + bddenv.c bddimply.c bddsimpdc.c + + libBdd_la_LDFLAGS = -version-info @BDD_DLL_VERSION@ +-libBdd_la_LIBADD = -lAbl -lAut ++libBdd_la_LIBADD = $(top_builddir)/abl/src/libAbl.la $(top_builddir)/aut/src/libAut.la +diff --git a/alliance/src/beh/src/Makefile.am b/alliance/src/beh/src/Makefile.am +index f087c94..5f70ef1 100644 +--- a/alliance/src/beh/src/Makefile.am ++++ b/alliance/src/beh/src/Makefile.am +@@ -1,4 +1,4 @@ +-AM_CFLAGS = -I$(top_srcdir)/mbk/src -I$(top_srcdir)/log/src ++AM_CPPFLAGS = -I$(top_srcdir)/mbk/src -I$(top_srcdir)/log/src + lib_LTLIBRARIES = libBeh.la + include_HEADERS = beh.h cst.h + libBeh_la_SOURCES = beh_addbeaux.c beh_delbebus.c beh_frebeaux.c beh_message.c \ +@@ -25,4 +25,4 @@ libBeh_la_SOURCES = beh_addbeaux.c beh_delbebus.c beh_frebeaux.c beh_mess + cst_DisjunctSet.c cst_GetPrevElt.c cst_SetCmp.c + + libBeh_la_LDFLAGS = -version-info @BEH_DLL_VERSION@ +-libBeh_la_LIBADD = -lLog -lAbl -lAut -lMut ++libBeh_la_LIBADD = $(top_builddir)/log/src/libLog.la $(top_builddir)/abl/src/libAbl.la $(top_builddir)/aut/src/libAut.la $(top_builddir)/mbk/src/libMut.la +diff --git a/alliance/src/bhl/src/Makefile.am b/alliance/src/bhl/src/Makefile.am +index 1d52002..97936f3 100644 +--- a/alliance/src/bhl/src/Makefile.am ++++ b/alliance/src/bhl/src/Makefile.am +@@ -1,4 +1,7 @@ +-AM_CFLAGS = -I$(top_srcdir)/mbk/src -I$(top_srcdir)/log/src -I$(top_srcdir)/beh/src ++AM_CPPFLAGS = -I$(top_srcdir)/mbk/src ++AM_CPPFLAGS += -I$(top_srcdir)/log/src ++AM_CPPFLAGS += -I$(top_srcdir)/beh/src ++ + lib_LTLIBRARIES = libBhl.la + include_HEADERS = bhl.h + libBhl_la_SOURCES = beh_chkbefig.c beh_dly2sta.c beh_makbdd.c beh_makvarlist.c \ +@@ -7,4 +10,7 @@ libBhl_la_SOURCES = beh_chkbefig.c beh_dly2sta.c beh_makbdd.c beh_makvarlis + beh_debug.h beh_indexbdd.c beh_maknode.c beh_unamlist.c \ + beh_depend.c beh_makquad.c bhl.h + libBhl_la_LDFLAGS = -version-info @BHL_DLL_VERSION@ +-libBhl_la_LIBADD = -lBeh -lAut -lMut ++libBhl_la_LIBADD = ++libBhl_la_LIBADD += $(top_builddir)/beh/src/libBeh.la ++libBhl_la_LIBADD += $(top_builddir)/log/src/libLog.la ++libBhl_la_LIBADD += $(top_builddir)/mbk/src/libMut.la +diff --git a/alliance/src/boog/src/Makefile.am b/alliance/src/boog/src/Makefile.am +index 3581883..d66b486 100644 +--- a/alliance/src/boog/src/Makefile.am ++++ b/alliance/src/boog/src/Makefile.am +@@ -1,25 +1,26 @@ + ## Process this file with automake to produce Makefile.in + +-AM_CFLAGS = -I$(top_srcdir)/abe/src \ ++AM_CFLAGS = @ALLIANCE_CFLAGS@ ++AM_CPPFLAGS = -I$(top_srcdir)/abe/src \ + -I$(top_srcdir)/abl/src \ + -I$(top_srcdir)/abv/src \ + -I$(top_srcdir)/bdd/src \ + -I$(top_srcdir)/aut/src \ +- -I$(top_srcdir)/mbk/src \ +- @ALLIANCE_CFLAGS@ ++ -I$(top_srcdir)/mbk/src + + bin_PROGRAMS = boog + +-boog_LDADD = @ALLIANCE_LIBS@ \ +- -L$(builddir)/../../abv/src \ +- -L$(builddir)/../../abe/src \ +- -L$(builddir)/../../abt/src \ +- -L$(builddir)/../../mbk/src \ +- -L$(builddir)/../../mbk/src \ +- -L$(builddir)/../../bdd/src \ +- -L$(builddir)/../../abl/src \ +- -L$(builddir)/../../aut/src \ +- -lAbv -lAbe -lAbt -lMlu -lRcn -lMlo -lBdd -lAbl -lAut -lMut ++boog_LDADD = @ALLIANCE_LIBS@ ++boog_LDADD += $(top_builddir)/abv/src/libAbv.la ++boog_LDADD += $(top_builddir)/abe/src/libAbe.la ++boog_LDADD += $(top_builddir)/abt/src/libAbt.la ++boog_LDADD += $(top_builddir)/mbk/src/libMlu.la ++boog_LDADD += $(top_builddir)/mbk/src/libRcn.la ++boog_LDADD += $(top_builddir)/mbk/src/libMlo.la ++boog_LDADD += $(top_builddir)/bdd/src/libBdd.la ++boog_LDADD += $(top_builddir)/abl/src/libAbl.la ++boog_LDADD += $(top_builddir)/aut/src/libAut.la ++boog_LDADD += $(top_builddir)/mbk/src/libMut.la + + boog_SOURCES = bog_lax_param.c bog_map_adapt.h bog_normalize_simplify.h \ + bog_lax_param.h bog_map_befig.c bog_signal_adapt.c \ +diff --git a/alliance/src/btr/src/Makefile.am b/alliance/src/btr/src/Makefile.am +index d9eb2c3..f988e2d 100644 +--- a/alliance/src/btr/src/Makefile.am ++++ b/alliance/src/btr/src/Makefile.am +@@ -1,8 +1,11 @@ +-AM_CFLAGS = -I$(top_srcdir)/mbk/src -I$(top_srcdir)/aut/src -I$(top_srcdir)/abl/src -I$(top_srcdir)/bdd/src ++AM_CPPFLAGS = -I$(top_srcdir)/mbk/src ++AM_CPPFLAGS += -I$(top_srcdir)/aut/src ++AM_CPPFLAGS += -I$(top_srcdir)/abl/src ++AM_CPPFLAGS += -I$(top_srcdir)/bdd/src + lib_LTLIBRARIES = libBtr.la + include_HEADERS = btr.h + libBtr_la_SOURCES = btr.h btrenv.c btrerror.h btrfunc.c btrresize.h \ + btralloc.c btrenv.h btrfree.c btrfunc.h btrtrans.c \ + btralloc.h btrerror.c btrfree.h btrresize.c btrtrans.h + libBtr_la_LDFLAGS = -version-info @BTR_DLL_VERSION@ +-libBtr_la_LIBADD = -lBdd ++libBtr_la_LIBADD = $(top_builddir)/bdd/src/libBdd.la +diff --git a/alliance/src/bvl/src/Makefile.am b/alliance/src/bvl/src/Makefile.am +index 5d81aec..89fa559 100644 +--- a/alliance/src/bvl/src/Makefile.am ++++ b/alliance/src/bvl/src/Makefile.am +@@ -1,11 +1,18 @@ +-AM_CFLAGS = -I$(top_srcdir)/mbk/src -I$(top_srcdir)/log/src -I$(top_srcdir)/beh/src -I$(top_srcdir)/bhl/src ++AM_CPPFLAGS = -I$(top_srcdir)/mbk/src ++AM_CPPFLAGS += -I$(top_srcdir)/log/src ++AM_CPPFLAGS += -I$(top_srcdir)/beh/src ++AM_CPPFLAGS += -I$(top_srcdir)/bhl/src + lib_LTLIBRARIES = libBvl.la + include_HEADERS = bvl.h + libBvl_la_SOURCES = bvl_bcomp_y.y bvl_bcomp_l.l bvl_bcomp_y.h \ + bvl_bedef.h bvl_drive.c bvl.h bvl_util.c \ + bvl_byacc.h bvl_globals.c bvl_parse.c + libBvl_la_LDFLAGS = -version-info @BVL_DLL_VERSION@ +-libBvl_la_LIBADD = -lBhl -lBeh -lMut ++libBvl_la_LIBADD = ++libBvl_la_LIBADD += $(top_builddir)/bhl/src/libBhl.la ++libBvl_la_LIBADD += $(top_builddir)/beh/src/libBeh.la ++libBvl_la_LIBADD += $(top_builddir)/log/src/libLog.la ++libBvl_la_LIBADD += $(top_builddir)/mbk/src/libMut.la + + CLEANFILES = bvl_bcomp_y.c bvl_bcomp_y.h bvl_bcomp_l.c + +@@ -13,3 +20,5 @@ bvl_bcomp_y.c bvl_bcomp_y.h : $(srcdir)/bvl_bcomp_y.y + $(YACC) -d $(YFLAGS) $(srcdir)/bvl_bcomp_y.y && sed -e "s/yy/bvl_y_/g" -e "s/YY/BVL_Y_/g" y.tab.c > bvl_bcomp_y.c && sed -e "s/yy/bvl_y_/g" -e "s/YY/BVL_Y_/g" y.tab.h > bvl_bcomp_y.h + bvl_bcomp_l.c : $(srcdir)/bvl_bcomp_l.l bvl_bcomp_y.h + $(LEX) -t $(srcdir)/bvl_bcomp_l.l | sed -e "s/yy/bvl_y_/g" -e "s/YY/BVL_Y_/g" > bvl_bcomp_l.c ++ ++CLEANFILES += y.tab.c y.tab.h +diff --git a/alliance/src/ctl/src/Makefile.am b/alliance/src/ctl/src/Makefile.am +index b4c6000..3e441fd 100644 +--- a/alliance/src/ctl/src/Makefile.am ++++ b/alliance/src/ctl/src/Makefile.am +@@ -1,8 +1,9 @@ +-AM_CFLAGS = @ALLIANCE_CFLAGS@ -I$(top_srcdir)/mbk/src -I$(top_srcdir)/aut/src -I$(top_srcdir)/vex/src ++AM_CFLAGS = @ALLIANCE_CFLAGS@ ++AM_CPPFLAGS = -I$(top_srcdir)/mbk/src -I$(top_srcdir)/aut/src -I$(top_srcdir)/vex/src + lib_LTLIBRARIES = libCtl.la + include_HEADERS = ctl.h + libCtl_la_SOURCES = ctladd.c ctlalloc.h ctlenv.c ctlerror.h ctl.h ctlview.c \ + ctladd.h ctldel.c ctlenv.h ctlfree.c ctlsearch.c ctlview.h \ + ctlalloc.c ctldel.h ctlerror.c ctlfree.h ctlsearch.h + libCtl_la_LDFLAGS = -version-info @CTL_DLL_VERSION@ +-libCtl_la_LIBADD = -lVex -lAut -lMut ++libCtl_la_LIBADD = $(top_builddir)/vex/src/libVex.la $(top_builddir)/aut/src/libAut.la $(top_builddir)/mbk/src/libMut.la +diff --git a/alliance/src/ctp/src/Makefile.am b/alliance/src/ctp/src/Makefile.am +index 165e582..7c52107 100644 +--- a/alliance/src/ctp/src/Makefile.am ++++ b/alliance/src/ctp/src/Makefile.am +@@ -1,11 +1,15 @@ +-AM_CFLAGS = -I$(top_srcdir)/mbk/src -I$(top_srcdir)/aut/src -I$(top_srcdir)/vex/src -I$(top_srcdir)/ctl/src ++AM_CPPFLAGS = -I$(top_srcdir)/mbk/src -I$(top_srcdir)/aut/src -I$(top_srcdir)/vex/src -I$(top_srcdir)/ctl/src + lib_LTLIBRARIES = libCtp.la + include_HEADERS = ctp.h + libCtp_la_SOURCES = ctp_y.y ctp_l.l ctp.h \ + ctp_bedef.h ctp_bspec.c ctp_byacc.h ctp_parse.c ctp_util.h \ + ctp_blex.h ctp_bspec.h ctp_util.c ctp_utype.h + libCtp_la_LDFLAGS = -version-info @CTP_DLL_VERSION@ +-libCtp_la_LIBADD = -lCtl -lVex -lAut -lMut ++libCtp_la_LIBADD = ++libCtp_la_LIBADD += $(top_builddir)/ctl/src/libCtl.la ++libCtp_la_LIBADD += $(top_builddir)/vex/src/libVex.la ++libCtp_la_LIBADD += $(top_builddir)/aut/src/libAut.la ++libCtp_la_LIBADD += $(top_builddir)/mbk/src/libMut.la + + CLEANFILES = ctp_y.c ctp_y.h ctp_l.c + +@@ -19,6 +23,12 @@ ctp_l.c : $(srcdir)/ctp_l.l ctp_y.h + + EXTRA_PROGRAMS = ctptest + +-ctptest_LDADD = -L. -lCtp -lCtl -lVex -lAut -lMut ++ctptest_LDADD = libCtp.la ++ctptest_LDADD += $(top_builddir)/ctl/src/libCtl.la ++ctptest_LDADD += $(top_builddir)/vex/src/libVex.la ++ctptest_LDADD += $(top_builddir)/aut/src/libAut.la ++ctptest_LDADD += $(top_builddir)/mbk/src/libMut.la + + ctptest_SOURCES = main.c ++ ++CLEANFILES += y.tab.c y.tab.h +diff --git a/alliance/src/druc/src/Makefile.am b/alliance/src/druc/src/Makefile.am +index bb31154..f4c125e 100644 +--- a/alliance/src/druc/src/Makefile.am ++++ b/alliance/src/druc/src/Makefile.am +@@ -8,10 +8,11 @@ drucompi.h drucring.c drucring.h drucutil.c drucutil.h vmcaract.c vmcaract.h \ + vmcasmld.c vmcasmld.h vmcerror.c vmcerror.h vmcmesur.c vmcmesur.h vmcrelat.c \ + vmcrelat.h vmctools.c vmctools.h vmcunify.c vmcunify.h + +-AM_CFLAGS = $(ALLIANCE_CFLAGS) + AM_CPPFLAGS = -I$(top_srcdir)/mbk/src -I$(top_srcdir)/rds/src + libVrd_la_LDFLAGS = -version-info @VRD_DLL_VERSION@ +-libVrd_la_LIBADD = -lRds -lMut ++libVrd_la_LIBADD = ++libVrd_la_LIBADD += $(top_builddir)/rds/src/libRds.la ++libVrd_la_LIBADD += $(top_builddir)/mbk/src/libMut.la + + CLEANFILES = drucompi_l.c drucompi_y.h drucompi_y.c + +@@ -23,9 +24,11 @@ drucompi_l.c : $(srcdir)/drucompi_l.l drucompi_y.h + + bin_PROGRAMS = druc + +-druc_LDADD = $(ALLIANCE_LIBS) -L. libVrd.la \ +--L$(builddir)/../../rds/src/.libs -lRds \ +--L$(builddir)/../../mbk/src/.libs -lMpu -lMut ++druc_LDADD = libVrd.la ++druc_LDADD += $(top_builddir)/rds/src/libRds.la ++druc_LDADD += $(top_builddir)/mbk/src/libMut.la + + druc_SOURCES = \ + drucbath.c drucbath.h ++ ++CLEANFILES += y.tab.c y.tab.h +diff --git a/alliance/src/elp/src/Makefile.am b/alliance/src/elp/src/Makefile.am +index 41969ab..28581fa 100644 +--- a/alliance/src/elp/src/Makefile.am ++++ b/alliance/src/elp/src/Makefile.am +@@ -1,11 +1,14 @@ +-AM_CFLAGS = -DTECHNOLOGY=\"etc/prol.elp\" -I$(top_srcdir)/mbk/src ++AM_CPPFLAGS = -DTECHNOLOGY=\"etc/prol.elp\" ++AM_CPPFLAGS += -I$(top_srcdir)/mbk/src + + lib_LTLIBRARIES = libElp.la + include_HEADERS = elp.h + libElp_la_SOURCES = elp_y.y elp_l.l elp.c elperror.c elp.h + + libElp_la_LDFLAGS = -version-info @ELP_DLL_VERSION@ +-libElp_la_LIBADD = -lRcn -lMut ++libElp_la_LIBADD = ++libElp_la_LIBADD += $(top_builddir)/mbk/src/libRcn.la ++libElp_la_LIBADD += $(top_builddir)/mbk/src/libMut.la + + CLEANFILES = elp_y.c elp_y.h elp_l.c + +@@ -14,3 +17,5 @@ elp_y.c elp_y.h : $(srcdir)/elp_y.y + + elp_l.c : $(srcdir)/elp_l.l elp_y.h + $(LEX) -t $(srcdir)/elp_l.l | sed -e "s/yy/elpyy/g" -e "s/YY/elpYY/g" > elp_l.c ++ ++CLEANFILES += y.tab.c y.tab.h +diff --git a/alliance/src/exp/src/Makefile.am b/alliance/src/exp/src/Makefile.am +index 03f8892..21fdf5f 100644 +--- a/alliance/src/exp/src/Makefile.am ++++ b/alliance/src/exp/src/Makefile.am +@@ -2,9 +2,7 @@ + + bin_PROGRAMS = exp + +-YACC = @YACC@ -d -v --debug +-CFLAGS = @CFLAGS@ @ALLIANCE_CFLAGS@ +-exp_LDADD = ++AM_YFLAGS = -d --debug + + exp_SOURCES = exp.h expy.y expl.l ht.c ht.h main.c + +diff --git a/alliance/src/fks/src/Makefile.am b/alliance/src/fks/src/Makefile.am +index 49f46ba..884e6bd 100644 +--- a/alliance/src/fks/src/Makefile.am ++++ b/alliance/src/fks/src/Makefile.am +@@ -1,4 +1,4 @@ +-AM_CFLAGS = -I$(top_srcdir)/mbk/src \ ++AM_CPPFLAGS = -I$(top_srcdir)/mbk/src \ + -I$(top_srcdir)/aut/src \ + -I$(top_srcdir)/abl/src \ + -I$(top_srcdir)/bdd/src \ +@@ -7,4 +7,9 @@ lib_LTLIBRARIES = libFks.la + include_HEADERS = fks.h + libFks_la_SOURCES = fks.h fksdrive.c fksdrive.h fkserror.c fkserror.h fksparse.c fksparse.h + libFks_la_LDFLAGS = -version-info @FKS_DLL_VERSION@ +-libFks_la_LIBADD = -lFsm -lAbl -lBdd -lAut -lMut ++libFks_la_LIBADD = ++libFks_la_LIBADD += $(top_builddir)/fsm/src/libFsm.la ++libFks_la_LIBADD += $(top_builddir)/abl/src/libAbl.la ++libFks_la_LIBADD += $(top_builddir)/bdd/src/libBdd.la ++libFks_la_LIBADD += $(top_builddir)/aut/src/libAut.la ++libFks_la_LIBADD += $(top_builddir)/mbk/src/libMut.la +diff --git a/alliance/src/flatbeh/src/Makefile.am b/alliance/src/flatbeh/src/Makefile.am +index 9419dd8..fa6a82a 100644 +--- a/alliance/src/flatbeh/src/Makefile.am ++++ b/alliance/src/flatbeh/src/Makefile.am +@@ -1,6 +1,7 @@ + ## Process this file with automake to produce Makefile.in + +-AM_CFLAGS = @ALLIANCE_CFLAGS@ \ ++AM_CFLAGS = @ALLIANCE_CFLAGS@ ++AM_CPPFLAGS = \ + -I$(top_srcdir)/abe/src \ + -I$(top_srcdir)/abl/src \ + -I$(top_srcdir)/abv/src \ +@@ -11,14 +12,7 @@ AM_CFLAGS = @ALLIANCE_CFLAGS@ \ + bin_PROGRAMS = flatbeh + + flatbeh_LDADD = @ALLIANCE_LIBS@ \ +--L$(top_builddir)/abv/src/.libs \ +--L$(top_builddir)/abe/src/.libs \ +--L$(top_builddir)/abt/src/.libs \ +--L$(top_builddir)/mbk/src/.libs \ +--L$(top_builddir)/bdd/src/.libs \ +--L$(top_builddir)/abl/src/.libs \ +--L$(top_builddir)/aut/src/.libs \ +- -lAbv -lAbe -lAbt -lMlu -lRcn -lMlo -lBdd -lAbl -lAut -lMut +- ++ $(top_builddir)/abv/src/libAbv.la $(top_builddir)/abe/src/libAbe.la $(top_builddir)/abt/src/libAbt.la $(top_builddir)/mbk/src/libMlu.la $(top_builddir)/mbk/src/libRcn.la $(top_builddir)/mbk/src/libMlo.la $(top_builddir)/bdd/src/libBdd.la $(top_builddir)/abl/src/libAbl.la $(top_builddir)/aut/src/libAut.la $(top_builddir)/mbk/src/libMut.la ++ + flatbeh_SOURCES = abstract.c abstract.h utils.c utils.h main.c + +diff --git a/alliance/src/flatph/src/Makefile.am b/alliance/src/flatph/src/Makefile.am +index 6fcf5bd..6ecbbfd 100644 +--- a/alliance/src/flatph/src/Makefile.am ++++ b/alliance/src/flatph/src/Makefile.am +@@ -1,14 +1,12 @@ + # $Id: Makefile.am,v 1.5 2005/01/19 15:13:50 hcl Exp $ + +-AM_CFLAGS = @ALLIANCE_CFLAGS@ -I$(top_srcdir)/mbk/src ++AM_CFLAGS = @ALLIANCE_CFLAGS@ ++AM_CPPFLAGS = -I$(top_srcdir)/mbk/src + + bin_PROGRAMS = flatph + +-flatph_LDADD = @ALLIANCE_LIBS@ \ +--L$(top_builddir)/mbk/src/.libs \ +- -lMpu -lMlu \ +- -lMlo \ +- -lMph -lMut \ +- -lRcn ++flatph_LDADD = @ALLIANCE_LIBS@ ++flatph_LDADD += $(top_builddir)/mbk/src/libMpu.la ++flatph_LDADD += $(top_builddir)/mbk/src/libMut.la + + flatph_SOURCES = flatph.c +diff --git a/alliance/src/fmi/src/Makefile.am b/alliance/src/fmi/src/Makefile.am +index 0248fd3..157f536 100644 +--- a/alliance/src/fmi/src/Makefile.am ++++ b/alliance/src/fmi/src/Makefile.am +@@ -2,24 +2,24 @@ + + bin_PROGRAMS = fmi + +-AM_CFLAGS = @ALLIANCE_CFLAGS@ -I$(top_srcdir)/abl/src \ ++AM_CFLAGS = @ALLIANCE_CFLAGS@ ++AM_CPPFLAGS = \ ++-I$(top_srcdir)/abl/src \ + -I$(top_srcdir)/aut/src \ + -I$(top_srcdir)/bdd/src \ + -I$(top_srcdir)/fsm/src \ + -I$(top_srcdir)/ftl/src \ + -I$(top_srcdir)/mbk/src + +-fmi_LDADD = @ALLIANCE_LIBS@ \ +--L$(top_builddir)/abl/src/.libs \ +--L$(top_builddir)/aut/src/.libs \ +--L$(top_builddir)/bdd/src/.libs \ +--L$(top_builddir)/fks/src/.libs \ +--L$(top_builddir)/fsm/src/.libs \ +--L$(top_builddir)/ftl/src/.libs \ +--L$(top_builddir)/fvh/src/.libs \ +--L$(top_builddir)/mbk/src/.libs \ +- -lFtl -lFks -lFvh -lFsm \ +- -lBdd -lAbl -lAut -lMut ++fmi_LDADD = @ALLIANCE_LIBS@ ++fmi_LDADD += $(top_builddir)/abl/src/libAbl.la ++fmi_LDADD += $(top_builddir)/aut/src/libAut.la ++fmi_LDADD += $(top_builddir)/bdd/src/libBdd.la ++fmi_LDADD += $(top_builddir)/fks/src/libFks.la ++fmi_LDADD += $(top_builddir)/fsm/src/libFsm.la ++fmi_LDADD += $(top_builddir)/ftl/src/libFtl.la ++fmi_LDADD += $(top_builddir)/fvh/src/libFvh.la ++fmi_LDADD += $(top_builddir)/mbk/src/libMut.la + + fmi_SOURCES = \ + fmi_bdd.c fmi_main.c fmi_optim.c fmi_parse.c \ +diff --git a/alliance/src/fsm/src/Makefile.am b/alliance/src/fsm/src/Makefile.am +index 47f639a..b52b63e 100644 +--- a/alliance/src/fsm/src/Makefile.am ++++ b/alliance/src/fsm/src/Makefile.am +@@ -1,4 +1,4 @@ +-AM_CFLAGS = -I$(top_srcdir)/mbk/src -I$(top_srcdir)/aut/src -I$(top_srcdir)/abl/src -I$(top_srcdir)/bdd/src ++AM_CPPFLAGS = -I$(top_srcdir)/mbk/src -I$(top_srcdir)/aut/src -I$(top_srcdir)/abl/src -I$(top_srcdir)/bdd/src + lib_LTLIBRARIES = libFsm.la + include_HEADERS = fsm.h + libFsm_la_SOURCES = fsm.h fsmalloc.h fsmdel.h fsmfree.h fsmsearch.h fsmview.h \ +@@ -6,4 +6,8 @@ libFsm_la_SOURCES = fsm.h fsmalloc.h fsmdel.h fsmfree.h fsmsearch.h f + fsmadd.h fsmbdd.h fsmerror.h fsmorder.h fsmsimp.h \ + fsmalloc.c fsmdel.c fsmfree.c fsmsearch.c fsmview.c + libFsm_la_LDFLAGS = -version-info @FSM_DLL_VERSION@ +-libFsm_la_LIBADD = -lBdd -lAbl -lAut -lMut ++libFsm_la_LIBADD = ++libFsm_la_LIBADD += $(top_builddir)/bdd/src/libBdd.la ++libFsm_la_LIBADD += $(top_builddir)/abl/src/libAbl.la ++libFsm_la_LIBADD += $(top_builddir)/aut/src/libAut.la ++libFsm_la_LIBADD += $(top_builddir)/mbk/src/libMut.la +diff --git a/alliance/src/fsp/src/Makefile.am b/alliance/src/fsp/src/Makefile.am +index dca3a4a..198270a 100644 +--- a/alliance/src/fsp/src/Makefile.am ++++ b/alliance/src/fsp/src/Makefile.am +@@ -2,7 +2,8 @@ + + bin_PROGRAMS = fsp + +-AM_CFLAGS = @ALLIANCE_CFLAGS@ \ ++AM_CFLAGS = @ALLIANCE_CFLAGS@ ++AM_CPPFLAGS = \ + -I$(top_srcdir)/abl/src \ + -I$(top_srcdir)/aut/src \ + -I$(top_srcdir)/bdd/src \ +@@ -11,16 +12,8 @@ AM_CFLAGS = @ALLIANCE_CFLAGS@ \ + -I$(top_srcdir)/mbk/src + + fsp_LDADD = @ALLIANCE_LIBS@ \ +--L$(top_builddir)/abl/src/.libs \ +--L$(top_builddir)/aut/src/.libs \ +--L$(top_builddir)/bdd/src/.libs \ +--L$(top_builddir)/fks/src/.libs \ +--L$(top_builddir)/fsm/src/.libs \ +--L$(top_builddir)/ftl/src/.libs \ +--L$(top_builddir)/fvh/src/.libs \ +--L$(top_builddir)/mbk/src/.libs \ +- -lFtl -lFks -lFvh -lFsm \ +- -lBdd -lAbl -lAut -lMut ++ $(top_builddir)/ftl/src/libFtl.la $(top_builddir)/fks/src/libFks.la $(top_builddir)/fvh/src/libFvh.la $(top_builddir)/fsm/src/libFsm.la \ ++ $(top_builddir)/bdd/src/libBdd.la $(top_builddir)/abl/src/libAbl.la $(top_builddir)/aut/src/libAut.la $(top_builddir)/mbk/src/libMut.la + + + fsp_SOURCES = \ +diff --git a/alliance/src/ftl/src/Makefile.am b/alliance/src/ftl/src/Makefile.am +index b50d0ad..2c4b10d 100644 +--- a/alliance/src/ftl/src/Makefile.am ++++ b/alliance/src/ftl/src/Makefile.am +@@ -1,4 +1,4 @@ +-AM_CFLAGS = -I$(top_srcdir)/mbk/src \ ++AM_CPPFLAGS = -I$(top_srcdir)/mbk/src \ + -I$(top_srcdir)/aut/src \ + -I$(top_srcdir)/abl/src \ + -I$(top_srcdir)/bdd/src \ +@@ -7,10 +7,24 @@ lib_LTLIBRARIES = libFtl.la + include_HEADERS = ftl.h + libFtl_la_SOURCES = ftl.h ftlacces.c ftlacces.h ftlerror.c ftlerror.h + libFtl_la_LDFLAGS = -version-info @FTL_DLL_VERSION@ +-libFtl_la_LIBADD = -lFks -lFvh -lFsm -lBdd -lAbl -lAut -lMut +- ++libFtl_la_LIBADD = ++libFtl_la_LIBADD += $(top_builddir)/fks/src/libFks.la ++libFtl_la_LIBADD += $(top_builddir)/fvh/src/libFvh.la ++libFtl_la_LIBADD += $(top_builddir)/fsm/src/libFsm.la ++libFtl_la_LIBADD += $(top_builddir)/bdd/src/libBdd.la ++libFtl_la_LIBADD += $(top_builddir)/abl/src/libAbl.la ++libFtl_la_LIBADD += $(top_builddir)/aut/src/libAut.la ++libFtl_la_LIBADD += $(top_builddir)/mbk/src/libMut.la + EXTRA_PROGRAMS = fsmtest + + +-fsmtest_LDADD = -L. -lFtl -lFks -lFvh -lFsm -lBdd -lAbl -lAut -lMut ++fsmtest_LDADD = libFtl.la ++fsmtest_LDADD += $(top_builddir)/fks/src/libFks.la ++fsmtest_LDADD += $(top_builddir)/fvh/src/libFvh.la ++fsmtest_LDADD += $(top_builddir)/fsm/src/libFsm.la ++fsmtest_LDADD += $(top_builddir)/bdd/src/libBdd.la ++fsmtest_LDADD += $(top_builddir)/abl/src/libAbl.la ++fsmtest_LDADD += $(top_builddir)/aut/src/libAut.la ++fsmtest_LDADD += $(top_builddir)/mbk/src/libMut.la ++ + fsmtest_SOURCES = main.c +diff --git a/alliance/src/fvh/src/Makefile.am b/alliance/src/fvh/src/Makefile.am +index 29a3a31..008893b 100644 +--- a/alliance/src/fvh/src/Makefile.am ++++ b/alliance/src/fvh/src/Makefile.am +@@ -1,4 +1,4 @@ +-AM_CFLAGS = -I$(top_srcdir)/mbk/src \ ++AM_CPPFLAGS = -I$(top_srcdir)/mbk/src \ + -I$(top_srcdir)/aut/src \ + -I$(top_srcdir)/abl/src \ + -I$(top_srcdir)/bdd/src \ +@@ -14,7 +14,12 @@ libFvh_la_SOURCES = fbl_bcomp_y.y fbl_bcomp_l.l \ + fvhfbh2fsm.c fvhfbh2fsm.h fvh.h fvhparse.c fvhparse.h + + libFvh_la_LDFLAGS = -version-info @FVH_DLL_VERSION@ +-libFvh_la_LIBADD = -lFsm -lAbl -lBdd -lAut -lMut ++libFvh_la_LIBADD = ++libFvh_la_LIBADD += $(top_builddir)/fsm/src/libFsm.la ++libFvh_la_LIBADD += $(top_builddir)/abl/src/libAbl.la ++libFvh_la_LIBADD += $(top_builddir)/bdd/src/libBdd.la ++libFvh_la_LIBADD += $(top_builddir)/aut/src/libAut.la ++libFvh_la_LIBADD += $(top_builddir)/mbk/src/libMut.la + + CLEANFILES = fbl_bcomp_y.c fbl_bcomp_y.h fbl_bcomp_l.c + +@@ -24,3 +29,5 @@ fbl_bcomp_y.c fbl_bcomp_y.h : $(srcdir)/fbl_bcomp_y.y + sed -e "s/yy/fbl_y_/g" -e "s/YY/FBL_Y_/g" y.tab.h > fbl_bcomp_y.h + fbl_bcomp_l.c : $(srcdir)/fbl_bcomp_l.l fbl_bcomp_y.h + $(LEX) -t $(srcdir)/fbl_bcomp_l.l | sed -e "s/yy/fbl_y_/g" -e "s/YY/FBL_Y_/g" > fbl_bcomp_l.c ++ ++CLEANFILES += y.tab.h y.tab.c +diff --git a/alliance/src/genlib/src/Makefile.am b/alliance/src/genlib/src/Makefile.am +index 5ed3463..c78135b 100644 +--- a/alliance/src/genlib/src/Makefile.am ++++ b/alliance/src/genlib/src/Makefile.am +@@ -1,4 +1,4 @@ +-AM_CFLAGS = -I$(top_srcdir)/mbk/src ++AM_CPPFLAGS = -I$(top_srcdir)/mbk/src + AM_YFLAGS = + AM_LFLAGS = + lib_LTLIBRARIES = libMgn.la +@@ -26,8 +26,12 @@ libMgn_la_SOURCES = genlib.c \ + dpgen_Shifter.c + + libMgn_la_LDFLAGS = -version-info @MGN_DLL_VERSION@ +-libMgn_la_LIBADD = -lMlu -lMlo -lMpu -lMph -lMut +- ++libMgn_la_LIBADD = ++libMgn_la_LIBADD += $(top_builddir)/mbk/src/libMlu.la ++libMgn_la_LIBADD += $(top_builddir)/mbk/src/libMlo.la ++libMgn_la_LIBADD += $(top_builddir)/mbk/src/libMpu.la ++libMgn_la_LIBADD += $(top_builddir)/mbk/src/libMph.la ++libMgn_la_LIBADD += $(top_builddir)/mbk/src/libMut.la + bin_SCRIPTS = genlib + CLEANFILES = genlib y.output dpgen_ROM_code.c dpgen_ROM_code.h + +diff --git a/alliance/src/genpat/src/Makefile.am b/alliance/src/genpat/src/Makefile.am +index 8a81622..9bb71f9 100644 +--- a/alliance/src/genpat/src/Makefile.am ++++ b/alliance/src/genpat/src/Makefile.am +@@ -1,4 +1,4 @@ +-AM_CFLAGS = -I$(top_srcdir)/mbk/src \ ++AM_CPPFLAGS = -I$(top_srcdir)/mbk/src \ + -I$(top_srcdir)/pat/src + + lib_LTLIBRARIES = libPgn.la +@@ -8,7 +8,9 @@ libPgn_la_SOURCES = AFFECT.c ARRAY.c CONV.c DECLAR.c DEF_GEN.c GETCPAT.c \ + libpat_l.c libpat_l.h + + libPgn_la_LDFLAGS = -version-info @PGN_DLL_VERSION@ +-libPgn_la_LIBADD = -lPat -lMut ++libPgn_la_LIBADD = ++libPgn_la_LIBADD += $(top_builddir)/pat/src/libPat.la ++libPgn_la_LIBADD += $(top_builddir)/mbk/src/libMut.la + + bin_SCRIPTS = genpat + CLEANFILES = genpat +diff --git a/alliance/src/graal/src/Makefile.am b/alliance/src/graal/src/Makefile.am +index 28d295c..b827041 100644 +--- a/alliance/src/graal/src/Makefile.am ++++ b/alliance/src/graal/src/Makefile.am +@@ -1,8 +1,8 @@ + ## Process this file with automake to produce Makefile.in + + bin_PROGRAMS = graal +-AM_CFLAGS = @ALLIANCE_CFLAGS@ @X_CFLAGS@ \ +- -I$(top_srcdir)/mbk/src \ ++AM_CFLAGS = @ALLIANCE_CFLAGS@ @X_CFLAGS@ ++AM_CPPFLAGS = -I$(top_srcdir)/mbk/src \ + -I$(top_srcdir)/rds/src \ + -I$(top_srcdir)/druc/src \ + -DGRAAL_DEFAULT_TECHNO_NAME=\"etc/cmos.graal\" \ +@@ -48,11 +48,9 @@ ALL_X_LIBS = $(X_LDFLAGS) $(LIBXM) $(LIBXT) $(LIBXPM) \ + + + +-graal_LDADD = @ALLIANCE_LIBS@ $(ALL_X_LIBS) \ +- -L$(top_builddir)/druc/src \ +- -L$(top_builddir)/mbk/src \ +- -L$(top_builddir)/rds/src \ +- -lVrd -lRds -lMpu -lMph -lMut ++graal_LDADD = @ALLIANCE_LIBS@ $(ALL_X_LIBS) ++graal_LDADD += $(top_builddir)/druc/src/libVrd.la ++graal_LDADD += $(top_builddir)/mbk/src/libMut.la + + graal_SOURCES = \ + graal.c GMC_create.c GMC_create.h GMC_dialog.c GMC_dialog.h GMC.h GMC_menu.c GMC_menu.h \ +diff --git a/alliance/src/k2f/src/Makefile.am b/alliance/src/k2f/src/Makefile.am +index c36edea..76561d7 100644 +--- a/alliance/src/k2f/src/Makefile.am ++++ b/alliance/src/k2f/src/Makefile.am +@@ -2,7 +2,8 @@ + + bin_PROGRAMS = k2f + +-AM_CFLAGS = @ALLIANCE_CFLAGS@ -I$(top_srcdir)/aut/src \ ++AM_CFLAGS = @ALLIANCE_CFLAGS@ ++AM_CPPFLAGS = -I$(top_srcdir)/aut/src \ + -I$(top_srcdir)/abl/src \ + -I$(top_srcdir)/bdd/src \ + -I$(top_srcdir)/fsm/src \ +@@ -10,16 +11,8 @@ AM_CFLAGS = @ALLIANCE_CFLAGS@ -I$(top_srcdir)/aut/src \ + -I$(top_srcdir)/mbk/src + + k2f_LDADD = @ALLIANCE_LIBS@ \ +--L$(top_builddir)/abl/src/.libs \ +--L$(top_builddir)/aut/src/.libs \ +--L$(top_builddir)/bdd/src/.libs \ +--L$(top_builddir)/fks/src/.libs \ +--L$(top_builddir)/fsm/src/.libs \ +--L$(top_builddir)/ftl/src/.libs \ +--L$(top_builddir)/fvh/src/.libs \ +--L$(top_builddir)/mbk/src/.libs \ +- -lFtl -lFks -lFvh -lFsm \ +- -lBdd -lAbl -lAut -lMut ++ $(top_builddir)/ftl/src/libFtl.la $(top_builddir)/fks/src/libFks.la $(top_builddir)/fvh/src/libFvh.la $(top_builddir)/fsm/src/libFsm.la \ ++ $(top_builddir)/bdd/src/libBdd.la $(top_builddir)/abl/src/libAbl.la $(top_builddir)/aut/src/libAut.la $(top_builddir)/mbk/src/libMut.la + + + k2f_SOURCES = \ +diff --git a/alliance/src/l2p/src/Makefile.am b/alliance/src/l2p/src/Makefile.am +index 56ea85f..3cc9ead 100644 +--- a/alliance/src/l2p/src/Makefile.am ++++ b/alliance/src/l2p/src/Makefile.am +@@ -2,13 +2,12 @@ + + bin_PROGRAMS = l2p + +-AM_CFLAGS = @ALLIANCE_CFLAGS@ -I$(top_srcdir)/mbk/src \ ++AM_CFLAGS = @ALLIANCE_CFLAGS@ ++AM_CPPFLAGS = -I$(top_srcdir)/mbk/src \ + -I$(top_srcdir)/rds/src + + l2p_LDADD = @ALLIANCE_LIBS@ \ +- -L$(top_builddir)/mbk/src/.libs \ +- -L$(top_builddir)/rds/src/.libs \ +- -lMlu -lMpu -lMlo -lMph -lMut -lRds ++ $(top_builddir)/mbk/src/libMlu.la $(top_builddir)/mbk/src/libMpu.la $(top_builddir)/mbk/src/libMlo.la $(top_builddir)/mbk/src/libMph.la $(top_builddir)/mbk/src/libMut.la $(top_builddir)/rds/src/libRds.la + + l2p_SOURCES = drive_ps.c rps_inc.h tmp_man.c \ + dict_color.ps l2p.c tmp_dict.c +diff --git a/alliance/src/log/src/Makefile.am b/alliance/src/log/src/Makefile.am +index dc7e4e1..2c85f8c 100644 +--- a/alliance/src/log/src/Makefile.am ++++ b/alliance/src/log/src/Makefile.am +@@ -1,7 +1,8 @@ +-AM_CFLAGS = -I$(top_srcdir)/mbk/src ++AM_CPPFLAGS = -I$(top_srcdir)/mbk/src + lib_LTLIBRARIES = libLog.la + include_HEADERS = log.h + libLog_la_SOURCES = log_bdd0.c log.h log_thashbdd.c log_thashloc.c \ + log_bdd1.c log_prefbib.c log_thash.c + libLog_la_LDFLAGS = -version-info @LOG_DLL_VERSION@ +-libLog_la_LIBADD = -lMut ++libLog_la_LIBADD = $(top_builddir)/mbk/src/libMut.la ++ +diff --git a/alliance/src/loon/src/Makefile.am b/alliance/src/loon/src/Makefile.am +index a0a4f06..7ab7975 100644 +--- a/alliance/src/loon/src/Makefile.am ++++ b/alliance/src/loon/src/Makefile.am +@@ -2,23 +2,17 @@ + + bin_PROGRAMS = loon + +-AM_CFLAGS = -I$(top_srcdir)/abe/src \ ++AM_CFLAGS = @ALLIANCE_CFLAGS@ ++AM_CPPFLAGS = \ ++-I$(top_srcdir)/abe/src \ + -I$(top_srcdir)/abl/src \ + -I$(top_srcdir)/aut/src \ + -I$(top_srcdir)/abv/src \ + -I$(top_srcdir)/bdd/src \ +--I$(top_srcdir)/mbk/src \ +-@ALLIANCE_CFLAGS@ ++-I$(top_srcdir)/mbk/src + + loon_LDADD = @ALLIANCE_LIBS@ \ +--L$(top_builddir)/abe/src \ +--L$(top_builddir)/abl/src \ +--L$(top_builddir)/abt/src \ +--L$(top_builddir)/abv/src \ +--L$(top_builddir)/aut/src \ +--L$(top_builddir)/bdd/src \ +--L$(top_builddir)/mbk/src \ +- -lAbv -lAbe -lAbt -lMlu -lMlo -lBdd -lAbl -lAut -lMut ++ $(top_builddir)/abv/src/libAbv.la $(top_builddir)/abe/src/libAbe.la $(top_builddir)/abt/src/libAbt.la $(top_builddir)/mbk/src/libMlu.la $(top_builddir)/mbk/src/libMlo.la $(top_builddir)/bdd/src/libBdd.la $(top_builddir)/abl/src/libAbl.la $(top_builddir)/aut/src/libAut.la $(top_builddir)/mbk/src/libMut.la + + loon_SOURCES = \ + lon_lax_param.c lon_lib_utils.c lon_optim_capa.h \ +diff --git a/alliance/src/lvx/src/Makefile.am b/alliance/src/lvx/src/Makefile.am +index 620999a..3bbdade 100644 +--- a/alliance/src/lvx/src/Makefile.am ++++ b/alliance/src/lvx/src/Makefile.am +@@ -1,10 +1,9 @@ + ## Process this file with automake to produce Makefile.in + bin_PROGRAMS = lvx + +-AM_CFLAGS = @ALLIANCE_CFLAGS@ -I$(top_srcdir)/mbk/src ++AM_CPPFLAGS = -I$(top_srcdir)/mbk/src + +-lvx_LDADD = @ALLIANCE_LIBS@ \ +- -L$(top_builddir)/mbk/src/.libs \ +- -lMlu -lMlo -lMut -lRcn ++lvx_LDADD = \ ++ $(top_builddir)/mbk/src/libMlu.la $(top_builddir)/mbk/src/libMlo.la $(top_builddir)/mbk/src/libMut.la $(top_builddir)/mbk/src/libRcn.la + + lvx_SOURCES = lvx.c +diff --git a/alliance/src/lynx/src/Makefile.am b/alliance/src/lynx/src/Makefile.am +index 6aa94ba..21b0152 100644 +--- a/alliance/src/lynx/src/Makefile.am ++++ b/alliance/src/lynx/src/Makefile.am +@@ -2,19 +2,16 @@ + + bin_PROGRAMS = cougar flatrds + +-AM_CFLAGS = @ALLIANCE_CFLAGS@ \ ++AM_CFLAGS = @ALLIANCE_CFLAGS@ ++AM_CPPFLAGS = \ + -I$(top_srcdir)/mbk/src \ + -I$(top_srcdir)/rds/src + + cougar_LDADD = @ALLIANCE_LIBS@ \ +- -L$(top_builddir)/mbk/src/.libs \ +- -L$(top_builddir)/rds/src/.libs \ +- -lRds -lMlu -lMpu -lMlo -lMph -lMut ++ $(top_builddir)/rds/src/libRds.la $(top_builddir)/mbk/src/libMlu.la $(top_builddir)/mbk/src/libMpu.la $(top_builddir)/mbk/src/libMlo.la $(top_builddir)/mbk/src/libMph.la $(top_builddir)/mbk/src/libMut.la + + flatrds_LDADD = @ALLIANCE_LIBS@ \ +- -L$(top_builddir)/mbk/src/.libs \ +- -L$(top_builddir)/rds/src/.libs \ +- -lRds -lMlu -lMpu -lMlo -lMph -lMut ++ $(top_builddir)/rds/src/libRds.la $(top_builddir)/mbk/src/libMlu.la $(top_builddir)/mbk/src/libMpu.la $(top_builddir)/mbk/src/libMlo.la $(top_builddir)/mbk/src/libMph.la $(top_builddir)/mbk/src/libMut.la + + flatrds_SOURCES = flatrds.c + +diff --git a/alliance/src/mbk/src/Makefile.am b/alliance/src/mbk/src/Makefile.am +index 3830341..47820e0 100644 +--- a/alliance/src/mbk/src/Makefile.am ++++ b/alliance/src/mbk/src/Makefile.am +@@ -1,5 +1,5 @@ + AM_CFLAGS = -DTECHNO=\"symbolic_cmos\" +-YFLAGS = -d ++AM_YFLAGS = -d + + lib_LTLIBRARIES = libMut.la libMph.la libMpu.la libRcn.la libMlo.la libMlu.la + include_HEADERS = mlu.h mlo.h mpu.h mph.h mut.h rcn.h msl.h +@@ -49,22 +49,24 @@ CLEANFILES = mg2mbk_y.c mg2mbk_y.h mg2mbk_l.c \ + mvl_scomp_y.c mvl_scomp_y.h mvl_scomp_l.c + + mg2mbk_y.c mg2mbk_y.h : $(srcdir)/mg2mbk_y.y +- $(YACC) $(YFLAGS) $(srcdir)/mg2mbk_y.y && \ ++ $(YACC) $(AM_YFLAGS) $(srcdir)/mg2mbk_y.y && \ + sed -e "s/yy/mgn/g" -e "s/YY/MGN/g" y.tab.c > mg2mbk_y.c && \ + sed -e "s/yy/mgn/g" -e "s/YY/MGN/g" y.tab.h > mg2mbk_y.h + mg2mbk_l.c : $(srcdir)/mg2mbk_l.l mg2mbk_y.h + $(LEX) -t $(srcdir)/mg2mbk_l.l | sed -e "s/yy/mgn/g" -e "s/YY/MGN/g" > mg2mbk_l.c + + parser_y.c parser_y.h : $(srcdir)/parser_y.y +- $(YACC) $(YFLAGS) $(srcdir)/parser_y.y && \ ++ $(YACC) $(AM_YFLAGS) $(srcdir)/parser_y.y && \ + sed -e "s/yy/edif/g" -e "s/YY/EDIF/g" y.tab.c > parser_y.c && \ + sed -e "s/yy/edif/g" -e "s/YY/EDIF/g" y.tab.h > parser_y.h + parser_l.c : $(srcdir)/parser_l.l parser_y.h + $(LEX) -t $(srcdir)/parser_l.l | sed -e "s/yy/edif/g" -e "s/YY/EDIF/g" > parser_l.c + + mvl_scomp_y.c mvl_scomp_y.h : $(srcdir)/mvl_scomp_y.y +- $(YACC) $(YFLAGS) $(srcdir)/mvl_scomp_y.y && \ ++ $(YACC) $(AM_YFLAGS) $(srcdir)/mvl_scomp_y.y && \ + sed -e "s/yy/mvl_y_/g" -e "s/YY/MVL_Y_/g" y.tab.c > mvl_scomp_y.c && \ + sed -e "s/yy/mvl_y_/g" -e "s/YY/MVL_Y_/g" y.tab.h > mvl_scomp_y.h + mvl_scomp_l.c : $(srcdir)/mvl_scomp_l.l mvl_scomp_y.h + $(LEX) -t $(srcdir)/mvl_scomp_l.l | sed -e "s/yy/mvl_y_/g" -e "s/YY/MVL_Y_/g" > mvl_scomp_l.c ++ ++CLEANFILES += y.tab.c y.tab.h +diff --git a/alliance/src/mips_asm/src/Makefile.am b/alliance/src/mips_asm/src/Makefile.am +index f1bc628..6478ed8 100644 +--- a/alliance/src/mips_asm/src/Makefile.am ++++ b/alliance/src/mips_asm/src/Makefile.am +@@ -4,8 +4,8 @@ YACC = @YACC@ -d + + #INCLUDES = -I$(srcdir) + +-AM_CXXFLAGS = @ALLIANCE_CFLAGS@ +-AM_CFLAGS = @ALLIANCE_CFLAGS@ \ ++AM_CFLAGS = @ALLIANCE_CFLAGS@ ++AM_CPPFLAGS = \ + -I$(top_srcdir)/beh/src \ + -I$(top_srcdir)/log/src \ + -I$(top_srcdir)/mbk/src +@@ -13,12 +13,7 @@ AM_CFLAGS = @ALLIANCE_CFLAGS@ \ + bin_PROGRAMS = mips_asm + + mips_asm_LDADD = @ALLIANCE_LIBS@ \ +--L$(top_builddir)/abl/src/.libs \ +--L$(top_builddir)/aut/src/.libs \ +--L$(top_builddir)/beh/src/.libs \ +--L$(top_builddir)/log/src/.libs \ +--L$(top_builddir)/mbk/src/.libs \ +- -lBeh -lMut -lLog ++ $(top_builddir)/beh/src/libBeh.la $(top_builddir)/mbk/src/libMut.la $(top_builddir)/log/src/libLog.la + + mips_asm_SOURCES = mips_defs.h mips_y.y mips_l.l mips_globals.c mips_lex.h mips_type.h mips_yacc.h mips_util.c + +diff --git a/alliance/src/mocha/src/Makefile.am b/alliance/src/mocha/src/Makefile.am +index bb3cd6a..89f011e 100644 +--- a/alliance/src/mocha/src/Makefile.am ++++ b/alliance/src/mocha/src/Makefile.am +@@ -2,7 +2,9 @@ + + bin_PROGRAMS = moka + +-AM_CFLAGS = -Wall \ ++AM_CFLAGS = @ALLIANCE_CFLAGS@ ++ ++AM_CPPFLAGS = \ + -I$(top_srcdir)/abe/src \ + -I$(top_srcdir)/abl/src \ + -I$(top_srcdir)/abv/src \ +@@ -15,27 +17,24 @@ AM_CFLAGS = -Wall \ + -I$(top_srcdir)/ftl/src \ + -I$(top_srcdir)/mbk/src \ + -I$(top_srcdir)/fvh/src \ +--I$(top_srcdir)/vex/src \ +-@ALLIANCE_CFLAGS@ ++-I$(top_srcdir)/vex/src + +-moka_LDADD = @ALLIANCE_LIBS@ \ +--L$(top_builddir)/abe/src/.libs \ +--L$(top_builddir)/abl/src/.libs \ +--L$(top_builddir)/abt/src/.libs \ +--L$(top_builddir)/abv/src/.libs \ +--L$(top_builddir)/aut/src/.libs \ +--L$(top_builddir)/bdd/src/.libs \ +--L$(top_builddir)/btr/src/.libs \ +--L$(top_builddir)/ctl/src/.libs \ +--L$(top_builddir)/ctp/src/.libs \ +--L$(top_builddir)/fks/src/.libs \ +--L$(top_builddir)/fsm/src/.libs \ +--L$(top_builddir)/ftl/src/.libs \ +--L$(top_builddir)/fvh/src/.libs \ +--L$(top_builddir)/mbk/src/.libs \ +--L$(top_builddir)/vex/src/.libs \ +- -lFtl -lFks -lFvh -lFsm \ +- -lCtp -lCtl -lVex -lAbt -lAbv -lAbe -lBtr -lBdd -lAbl -lAut -lMut ++moka_LDADD = @ALLIANCE_LIBS@ ++moka_LDADD += $(top_builddir)/abe/src/libAbe.la ++moka_LDADD += $(top_builddir)/abl/src/libAbl.la ++moka_LDADD += $(top_builddir)/abt/src/libAbt.la ++moka_LDADD += $(top_builddir)/abv/src/libAbv.la ++moka_LDADD += $(top_builddir)/aut/src/libAut.la ++moka_LDADD += $(top_builddir)/bdd/src/libBdd.la ++moka_LDADD += $(top_builddir)/btr/src/libBtr.la ++moka_LDADD += $(top_builddir)/ctl/src/libCtl.la ++moka_LDADD += $(top_builddir)/ctp/src/libCtp.la ++moka_LDADD += $(top_builddir)/fks/src/libFks.la ++moka_LDADD += $(top_builddir)/fsm/src/libFsm.la ++moka_LDADD += $(top_builddir)/ftl/src/libFtl.la ++moka_LDADD += $(top_builddir)/fvh/src/libFvh.la ++moka_LDADD += $(top_builddir)/mbk/src/libMut.la ++moka_LDADD += $(top_builddir)/vex/src/libVex.la + + + moka_SOURCES = \ +diff --git a/alliance/src/nero/src/Makefile.am b/alliance/src/nero/src/Makefile.am +index f3a5abd..b24b5a3 100644 +--- a/alliance/src/nero/src/Makefile.am ++++ b/alliance/src/nero/src/Makefile.am +@@ -1,13 +1,8 @@ + ## Process this file with automake to produce Makefile.in + +-AM_CXXFLAGS = @ALLIANCE_CFLAGS@ \ +- -I$(top_srcdir)/abl/src \ +- -I$(top_srcdir)/aut/src \ +- -I$(top_srcdir)/beh/src \ +- -I$(top_srcdir)/genlib/src \ +- -I$(top_srcdir)/rds/src \ +- -I$(top_srcdir)/mbk/src +-AM_CFLAGS = @ALLIANCE_CFLAGS@ \ ++AM_CXXFLAGS = @ALLIANCE_CFLAGS@ ++AM_CFLAGS = @ALLIANCE_CFLAGS@ ++AM_CPPFLAGS = \ + -I$(top_srcdir)/abl/src \ + -I$(top_srcdir)/aut/src \ + -I$(top_srcdir)/beh/src \ +@@ -18,12 +13,9 @@ AM_CFLAGS = @ALLIANCE_CFLAGS@ \ + bin_PROGRAMS = nero pdv + #noinst_PROGRAMS = debug + +-nero_LDADD = -L$(libdir) @ALLIANCE_LIBS@ \ ++nero_LDADD = @ALLIANCE_LIBS@ \ + ./libU.a \ +- -L$(top_builddir)/aut/src/.libs \ +- -L$(top_builddir)/mbk/src/.libs \ +- -L$(top_builddir)/rds/src/.libs \ +- -lMpu -lRds -lMlu -lMlo -lMph -lMut -lRcn -lAut ++ $(top_builddir)/mbk/src/libMpu.la $(top_builddir)/rds/src/libRds.la $(top_builddir)/mbk/src/libMlu.la $(top_builddir)/mbk/src/libMlo.la $(top_builddir)/mbk/src/libMph.la $(top_builddir)/mbk/src/libMut.la $(top_builddir)/mbk/src/libRcn.la $(top_builddir)/aut/src/libAut.la + + noinst_LIBRARIES = libU.a + +@@ -51,9 +43,7 @@ libU_a_SOURCES = UConst.cpp \ + nero_SOURCES = nero.cpp + + pdv_LDADD = @ALLIANCE_LIBS@ \ +- -L$(top_builddir)/aut/src/.libs \ +- -L$(top_builddir)/mbk/src/.libs \ +- -lMpu -lMlu -lMlo -lMph -lMut -lRcn -lAut ++ $(top_builddir)/mbk/src/libMpu.la $(top_builddir)/mbk/src/libMlu.la $(top_builddir)/mbk/src/libMlo.la $(top_builddir)/mbk/src/libMph.la $(top_builddir)/mbk/src/libMut.la $(top_builddir)/mbk/src/libRcn.la $(top_builddir)/aut/src/libAut.la + + pdv_SOURCES = pdv.c + +diff --git a/alliance/src/ocp/src/placer/Makefile.am b/alliance/src/ocp/src/placer/Makefile.am +index 49093f6..30437f0 100644 +--- a/alliance/src/ocp/src/placer/Makefile.am ++++ b/alliance/src/ocp/src/placer/Makefile.am +@@ -1,16 +1,14 @@ + ## Process this file with automake to produce Makefile.in + +-YACC = @YACC@ -d ++AM_YFLAGS = -d + +-INCLUDES = -I$(srcdir)/../common ++AM_CPPFLAGS = -I$(srcdir)/../common + +-AM_CXXFLAGS = @ALLIANCE_CFLAGS@ \ +- -I$(top_srcdir)/rds/src \ +- -I$(top_srcdir)/mbk/src \ +- -std=gnu++0x +-AM_CFLAGS = @ALLIANCE_CFLAGS@ \ +- -I$(top_srcdir)/rds/src \ +- -I$(top_srcdir)/mbk/src ++AM_CPPFLAGS += -I$(top_srcdir)/rds/src ++AM_CPPFLAGS += -I$(top_srcdir)/mbk/src ++ ++# HACK ++AM_CXXFLAGS = -std=c++11 + + bin_PROGRAMS = ocp + +@@ -19,11 +17,14 @@ noinst_LIBRARIES = libOcp.a + libOcp_a_SOURCES = PElem.cpp PIns.cpp PNet.cpp \ + PCon.cpp + +-ocp_LDADD = @ALLIANCE_LIBS@ \ +- ../common/libPCommon.a \ +- -L$(top_builddir)/mbk/src/.libs \ +- -L$(top_builddir)/rds/src/.libs \ +- -lMpu -lRds -lMlu -lMlo -lMph -lMut -lRcn ++ocp_LDADD = ../common/libPCommon.a ++ocp_LDADD += $(top_builddir)/mbk/src/libMpu.la ++ocp_LDADD += $(top_builddir)/rds/src/libRds.la ++ocp_LDADD += $(top_builddir)/mbk/src/libMlu.la ++ocp_LDADD += $(top_builddir)/mbk/src/libMlo.la ++ocp_LDADD += $(top_builddir)/mbk/src/libMph.la ++ocp_LDADD += $(top_builddir)/mbk/src/libMut.la ++ocp_LDADD += $(top_builddir)/mbk/src/libRcn.la + + ocp_SOURCES = Ocp.cpp PBin.cpp PCon.cpp \ + PIns.cpp PMove.cpp PNet.cpp PONet.cpp \ +@@ -47,4 +48,4 @@ ocp_SOURCES = Ocp.cpp PBin.cpp PCon.cpp \ + + EXTRA_DIST = iocgram.h + +-CLEANFILES = iocgram.c iocgram.h ++CLEANFILES = iocgram.c iocgram.h iocscan.c +diff --git a/alliance/src/pat/src/Makefile.am b/alliance/src/pat/src/Makefile.am +index ac409be..d8875fb 100644 +--- a/alliance/src/pat/src/Makefile.am ++++ b/alliance/src/pat/src/Makefile.am +@@ -1,4 +1,4 @@ +-AM_CFLAGS = -I$(top_srcdir)/mbk/src ++AM_CPPFLAGS = -I$(top_srcdir)/mbk/src + lib_LTLIBRARIES = libPat.la + include_HEADERS = pat.h ppt.h phl.h + libPat_la_SOURCES = pat_addpacom.c pat_addpaevt.c pat_addpagrp.c pat_addpaini.c \ +@@ -13,7 +13,9 @@ libPat_la_SOURCES = pat_addpacom.c pat_addpaevt.c pat_addpagrp.c pat_addpaini. + pat_type.h ppt.h \ + pat_debug.c pat_debug.h pat_getusage.c phl.h + libPat_la_LDFLAGS = -version-info @PAT_DLL_VERSION@ +-libPat_la_LIBADD = -lAut -lMut ++libPat_la_LIBADD = ++libPat_la_LIBADD += $(top_builddir)/mbk/src/libMut.la ++ + + EXTRADIST = pat_decl_y.c pat_decl_y.h pat_desc_y.h pat_desc_y.c \ + pat_decl_l.c +@@ -45,3 +47,4 @@ pat_desc_y.c pat_desc_y.h : $(srcdir)/pat_desc_y.y + pat_desc_l.c : $(srcdir)/pat_desc_l.l pat_desc_y.h + $(LEX) -t $(srcdir)/pat_desc_l.l | sed -e "s/yy/pat_desc_y_/g" -e "s/YY/PAT_DESC_Y_/g" > pat_desc_l.c + ++CLEANFILES += y.tab.c y.tab.h +diff --git a/alliance/src/pat2spi/src/Makefile.am b/alliance/src/pat2spi/src/Makefile.am +index 55e24ba..d6c3e37 100644 +--- a/alliance/src/pat2spi/src/Makefile.am ++++ b/alliance/src/pat2spi/src/Makefile.am +@@ -2,14 +2,12 @@ + + bin_PROGRAMS = pat2spi + +-AM_CFLAGS = @ALLIANCE_CFLAGS@ -I$(top_srcdir)/aut/src \ ++AM_CFLAGS = @ALLIANCE_CFLAGS@ ++AM_CPPFLAGS = -I$(top_srcdir)/aut/src \ + -I$(top_srcdir)/mbk/src \ + -I$(top_srcdir)/pat/src + + pat2spi_LDADD = @ALLIANCE_LIBS@ \ +- -L$(top_builddir)/aut/src/.libs \ +- -L$(top_builddir)/mbk/src/.libs \ +- -L$(top_builddir)/pat/src/.libs \ +- -lPat -lAut -lMut ++ $(top_builddir)/pat/src/libPat.la $(top_builddir)/aut/src/libAut.la $(top_builddir)/mbk/src/libMut.la + + pat2spi_SOURCES = pat2spi.c pat2spi.h +diff --git a/alliance/src/proof/src/Makefile.am b/alliance/src/proof/src/Makefile.am +index c6b6130..094988e 100644 +--- a/alliance/src/proof/src/Makefile.am ++++ b/alliance/src/proof/src/Makefile.am +@@ -2,21 +2,17 @@ + + bin_PROGRAMS = proof + +-AM_CFLAGS = @ALLIANCE_CFLAGS@ -I$(top_srcdir)/beh/src \ ++AM_CFLAGS = @ALLIANCE_CFLAGS@ ++AM_CPPFLAGS = -I$(top_srcdir)/beh/src \ + -I$(top_srcdir)/bvl/src \ + -I$(top_srcdir)/log/src \ + -I$(top_srcdir)/mbk/src + +-proof_LDADD = @ALLIANCE_LIBS@ \ +- -L$(top_builddir)/asimut/src/.libs \ +- -L$(top_builddir)/abl/src/.libs \ +- -L$(top_builddir)/aut/src/.libs \ +- -L$(top_builddir)/beh/src/.libs \ +- -L$(top_builddir)/bhl/src/.libs \ +- -L$(top_builddir)/bvl/src/.libs \ +- -L$(top_builddir)/log/src/.libs \ +- -L$(top_builddir)/mbk/src/.libs \ +- -lBvl -lBhl -lBeh -lLog -lMut ++proof_LDADD = @ALLIANCE_LIBS@ ++proof_LDADD += $(top_builddir)/beh/src/libBeh.la ++proof_LDADD += $(top_builddir)/bvl/src/libBvl.la ++proof_LDADD += $(top_builddir)/log/src/libLog.la ++proof_LDADD += $(top_builddir)/mbk/src/libMut.la + + proof_SOURCES = proof_compile.c proof_main.c proof_util.c \ + proof_compile.h proof_util.h +diff --git a/alliance/src/rds/src/Makefile.am b/alliance/src/rds/src/Makefile.am +index 1773e3f..df695f1 100644 +--- a/alliance/src/rds/src/Makefile.am ++++ b/alliance/src/rds/src/Makefile.am +@@ -1,4 +1,4 @@ +-AM_CFLAGS = -DRTL_DEFAULT_TECHNO=\"etc/cmos.rds\" -I$(top_srcdir)/mbk/src ++AM_CPPFLAGS = -DRTL_DEFAULT_TECHNO=\"etc/cmos.rds\" -I$(top_srcdir)/mbk/src + + lib_LTLIBRARIES = libRds.la + include_HEADERS = rds.h rfm.h rtl.h rwi.h rpr.h rut.h +@@ -24,4 +24,4 @@ libRds_la_SOURCES = rdsalloc.c rdsfree.c rdsadd.c rdsdel.c rdsview.c \ + gds_drive.h gds_parse.c gds_swap.h gds.h \ + gds_error.c gds_parse.h rgs.h gds_drive.c gds_error.h gds_swap.c + libRds_la_LDFLAGS = -version-info @RDS_DLL_VERSION@ +-libRds_la_LIBADD = -lMpu -lMut ++libRds_la_LIBADD = $(top_builddir)/mbk/src/libMpu.la $(top_builddir)/mbk/src/libMut.la +diff --git a/alliance/src/ring/src/Makefile.am b/alliance/src/ring/src/Makefile.am +index 65e1653..ae13f98 100644 +--- a/alliance/src/ring/src/Makefile.am ++++ b/alliance/src/ring/src/Makefile.am +@@ -1,19 +1,23 @@ + ## Process this file with automake to produce Makefile.in + +-YACC = @YACC@ -d ++AM_YFLAGS = -d -p ring_yy ++AM_LFLAGS = -P ring_yy -o rinscan.c + +-AM_CFLAGS = @ALLIANCE_CFLAGS@ \ +- -I$(top_srcdir)/mbk/src \ +- -I$(top_srcdir)/genlib/src ++AM_CFLAGS = @ALLIANCE_CFLAGS@ ++AM_CPPFLAGS = ++AM_CPPFLAGS += -I$(top_srcdir)/mbk/src ++AM_CPPFLAGS += -I$(top_srcdir)/genlib/src + + bin_PROGRAMS = ring + +-ring_LDADD = @ALLIANCE_LIBS@ \ +- -L$(top_builddir)/genlib/src \ +- -L$(top_builddir)/mbk/src \ +- -L$(top_builddir)/rds/src \ +- -lMgn -lMpu -lMlu -lMlo -lMph -lMut -lRcn -lRds +- ++ring_LDADD = @ALLIANCE_LIBS@ ++ring_LDADD += $(top_builddir)/genlib/src/libMgn.la ++ring_LDADD += $(top_builddir)/rds/src/libRds.la ++ring_LDADD += $(top_builddir)/mbk/src/libMpu.la ++ring_LDADD += $(top_builddir)/mbk/src/libMlu.la ++ring_LDADD += $(top_builddir)/mbk/src/libMlo.la ++ring_LDADD += $(top_builddir)/mbk/src/libMut.la ++ + ring_SOURCES = bigvia.c bigvia.h \ + compress.c compress.h \ + deport.c deport.h \ +@@ -34,6 +38,6 @@ ring_SOURCES = bigvia.c bigvia.h \ + struct.h \ + barre.c barre.h + +-EXTRA_DIST = ringram.h ++# EXTRA_DIST = ringram.h + + CLEANFILES = ringram.c ringram.h rinscan.c +diff --git a/alliance/src/rtd/src/Makefile.am b/alliance/src/rtd/src/Makefile.am +index 509c9c8..c208ef1 100644 +--- a/alliance/src/rtd/src/Makefile.am ++++ b/alliance/src/rtd/src/Makefile.am +@@ -1,4 +1,4 @@ +-AM_CFLAGS = -I$(top_srcdir)/mbk/src \ ++AM_CPPFLAGS = -I$(top_srcdir)/mbk/src \ + -I$(top_srcdir)/aut/src \ + -I$(top_srcdir)/vex/src \ + -I$(top_srcdir)/rtn/src +@@ -7,4 +7,7 @@ include_HEADERS = rtd.h + libRtd_la_SOURCES = rtd.h rtd_drive.h rtd_error.h rtd_get.h rtd_parse.h \ + rtd_drive.c rtd_error.c rtd_get.c rtd_parse.c + libRtd_la_LDFLAGS = -version-info @RTD_DLL_VERSION@ +-libRtd_la_LIBADD = -lRtn -lVex -lMut ++libRtd_la_LIBADD = ++libRtd_la_LIBADD += $(top_builddir)/rtn/src/libRtn.la ++libRtd_la_LIBADD += $(top_builddir)/vex/src/libVex.la ++libRtd_la_LIBADD += $(top_builddir)/mbk/src/libMut.la +\ No newline at end of file +diff --git a/alliance/src/rtn/src/Makefile.am b/alliance/src/rtn/src/Makefile.am +index 0121f97..16a5028 100644 +--- a/alliance/src/rtn/src/Makefile.am ++++ b/alliance/src/rtn/src/Makefile.am +@@ -1,8 +1,11 @@ +-AM_CFLAGS = -I$(top_srcdir)/mbk/src -I$(top_srcdir)/aut/src -I$(top_srcdir)/vex/src ++AM_CPPFLAGS = -I$(top_srcdir)/mbk/src -I$(top_srcdir)/aut/src -I$(top_srcdir)/vex/src + lib_LTLIBRARIES = libRtn.la + include_HEADERS = rtn.h + libRtn_la_SOURCES = rtnadd.h rtndel.c rtnerror.h rtnget.c rtnsearch.h \ + rtn.h rtnalloc.c rtndel.h rtnfree.c rtnget.h rtnview.c \ + rtnadd.c rtnalloc.h rtnerror.c rtnfree.h rtnsearch.c rtnview.h + libRtn_la_LDFLAGS = -version-info @RTN_DLL_VERSION@ +-libRtn_la_LIBADD = -lVex -lAut -lMut ++libRtn_la_LIBADD = ++libRtn_la_LIBADD += $(top_builddir)/vex/src/libVex.la ++libRtn_la_LIBADD += $(top_builddir)/aut/src/libAut.la ++libRtn_la_LIBADD += $(top_builddir)/mbk/src/libMut.la +diff --git a/alliance/src/s2r/src/Makefile.am b/alliance/src/s2r/src/Makefile.am +index b193efd..06b3df8 100644 +--- a/alliance/src/s2r/src/Makefile.am ++++ b/alliance/src/s2r/src/Makefile.am +@@ -2,15 +2,16 @@ + + bin_PROGRAMS = s2r + +-AM_CFLAGS = @ALLIANCE_CFLAGS@ \ +- -I$(top_srcdir)/rds/src \ +- -I$(top_srcdir)/genview/src/gcc-1.42 \ +- -I$(top_srcdir)/mbk/src ++AM_CFLAGS = @ALLIANCE_CFLAGS@ ++AM_CPPFLAGS = ++AM_CPPFLAGS += -I$(top_srcdir)/rds/src ++AM_CPPFLAGS += -I$(top_srcdir)/mbk/src + +-s2r_LDADD = @ALLIANCE_LIBS@ \ +- -L$(top_builddir)/mbk/src/.libs \ +- -L$(top_builddir)/rds/src/.libs \ +- -lMpu -lRds -lMph -lMut ++s2r_LDADD = @ALLIANCE_LIBS@ ++s2r_LDADD += $(top_builddir)/mbk/src/libMpu.la ++s2r_LDADD += $(top_builddir)/rds/src/libRds.la ++s2r_LDADD += $(top_builddir)/mbk/src/libMph.la ++s2r_LDADD += $(top_builddir)/mbk/src/libMut.la + + s2r_SOURCES = generic.h hash.h maxima.h merge.h\ + postrat.h rdsacces.h statistics.c hash.c\ +diff --git a/alliance/src/scapin/src/Makefile.am b/alliance/src/scapin/src/Makefile.am +index 342d67c..a729da1 100644 +--- a/alliance/src/scapin/src/Makefile.am ++++ b/alliance/src/scapin/src/Makefile.am +@@ -2,15 +2,14 @@ + + bin_PROGRAMS = scapin + +-AM_CFLAGS = @ALLIANCE_CFLAGS@ \ ++AM_CFLAGS = @ALLIANCE_CFLAGS@ ++AM_CPPFLAGS = \ + -I$(top_srcdir)/aut/src \ + -I$(top_srcdir)/mbk/src \ + -DSCAPIN_DEFAULT_PARAM_NAME=\"etc/sxlib.scapin\" + +-scapin_LDADD = @ALLIANCE_LIBS@ \ +- -L$(top_builddir)/aut/src/.libs \ +- -L$(top_builddir)/mbk/src/.libs \ +- -lMlu -lMlo -lMut -lRcn -lAut ++scapin_LDADD = @ALLIANCE_LIBS@ ++scapin_LDADD += $(top_builddir)/mbk/src/libMlu.la $(top_builddir)/mbk/src/libMlo.la $(top_builddir)/mbk/src/libMut.la $(top_builddir)/mbk/src/libRcn.la $(top_builddir)/aut/src/libAut.la + + scapin_SOURCES = scan_insert.c scan_insert.h scan_main.c scan_main.h \ + scan_param.c scan_param.h scan_path.c scan_path.h +diff --git a/alliance/src/scl/src/Makefile.am b/alliance/src/scl/src/Makefile.am +index 77bf364..867c8d4 100644 +--- a/alliance/src/scl/src/Makefile.am ++++ b/alliance/src/scl/src/Makefile.am +@@ -1,6 +1,8 @@ +-AM_CFLAGS = -I$(top_srcdir)/mbk/src -I$(top_srcdir)/aut/src \ +- -I$(top_srcdir)/abl/src -I$(top_srcdir)/bdd/src \ +- -I$(top_srcdir)/abe/src ++AM_CPPFLAGS = -I$(top_srcdir)/mbk/src ++AM_CPPFLAGS += -I$(top_srcdir)/aut/src ++AM_CPPFLAGS += -I$(top_srcdir)/abl/src ++AM_CPPFLAGS += -I$(top_srcdir)/bdd/src ++AM_CPPFLAGS += -I$(top_srcdir)/abe/src + lib_LTLIBRARIES = libScl.la + include_HEADERS = scl.h + libScl_la_SOURCES = scgmain.h schenv.c schget.h scpadd.h scpfree.c \ +@@ -11,4 +13,9 @@ libScl_la_SOURCES = scgmain.h schenv.c schget.h scpadd.h scpfree.c \ + scglofig.h schdel.c schfree.h scp.h scpdel.c \ + scgmain.c schdel.h schget.c scpadd.c scpdel.h + libScl_la_LDFLAGS = -version-info @SCL_DLL_VERSION@ +-libScl_la_LIBADD = -lAbl -lAut -lMut ++libScl_la_LIBADD = ++libScl_la_LIBADD += $(top_builddir)/abe/src/libAbe.la ++libScl_la_LIBADD += $(top_builddir)/bdd/src/libBdd.la ++libScl_la_LIBADD += $(top_builddir)/abl/src/libAbl.la ++libScl_la_LIBADD += $(top_builddir)/aut/src/libAut.la ++libScl_la_LIBADD += $(top_builddir)/mbk/src/libMut.la +diff --git a/alliance/src/sea/src/Makefile.am b/alliance/src/sea/src/Makefile.am +index e1dcce1..2ba9e7f 100644 +--- a/alliance/src/sea/src/Makefile.am ++++ b/alliance/src/sea/src/Makefile.am +@@ -3,7 +3,8 @@ + AM_YFLAGS = -d -v -p DEF_grammar + AM_LFLAGS = -s -f -8 -pp -PDEF_grammar -olex.yy.c + +-AM_CFLAGS = @ALLIANCE_CFLAGS@ \ ++AM_CFLAGS = @ALLIANCE_CFLAGS@ ++AM_CPPFLAGS = \ + -I$(top_srcdir)/aut/src \ + -I$(top_srcdir)/mbk/src + +@@ -12,21 +13,15 @@ bin_SCRIPTS = sea seroute seplace a2lef + + a2def_LDADD = @ALLIANCE_LIBS@ \ + ./libUtil.a \ +- -L$(top_builddir)/aut/src/.libs \ +- -L$(top_builddir)/mbk/src/.libs \ +- -lMpu -lMlu -lMlo -lMph -lMut -lRcn -lAut ++ $(top_builddir)/mbk/src/libMpu.la $(top_builddir)/mbk/src/libMlu.la $(top_builddir)/mbk/src/libMlo.la $(top_builddir)/mbk/src/libMph.la $(top_builddir)/mbk/src/libMut.la $(top_builddir)/mbk/src/libRcn.la $(top_builddir)/aut/src/libAut.la + + def2a_LDADD = @ALLIANCE_LIBS@ \ + ./libUtil.a \ +- -L$(top_builddir)/aut/src/.libs \ +- -L$(top_builddir)/mbk/src/.libs \ +- -lMpu -lMlu -lMlo -lMph -lMut -lRcn -lAut ++ $(top_builddir)/mbk/src/libMpu.la $(top_builddir)/mbk/src/libMlu.la $(top_builddir)/mbk/src/libMlo.la $(top_builddir)/mbk/src/libMph.la $(top_builddir)/mbk/src/libMut.la $(top_builddir)/mbk/src/libRcn.la $(top_builddir)/aut/src/libAut.la + + sxlib2lef_LDADD = @ALLIANCE_LIBS@ \ + ./libUtil.a \ +- -L$(top_builddir)/aut/src/.libs \ +- -L$(top_builddir)/mbk/src/.libs \ +- -lMpu -lMlu -lMlo -lMph -lMut -lRcn -lAut ++ $(top_builddir)/mbk/src/libMpu.la $(top_builddir)/mbk/src/libMlu.la $(top_builddir)/mbk/src/libMlo.la $(top_builddir)/mbk/src/libMph.la $(top_builddir)/mbk/src/libMut.la $(top_builddir)/mbk/src/libRcn.la $(top_builddir)/aut/src/libAut.la + + noinst_LIBRARIES = libUtil.a + +diff --git a/alliance/src/syf/src/Makefile.am b/alliance/src/syf/src/Makefile.am +index 293e333..f1a4de5 100644 +--- a/alliance/src/syf/src/Makefile.am ++++ b/alliance/src/syf/src/Makefile.am +@@ -2,27 +2,26 @@ + + bin_PROGRAMS = syf + +-AM_CFLAGS = \ ++AM_CFLAGS = @ALLIANCE_CFLAGS@ ++ ++AM_CPPFLAGS = \ + -I$(top_srcdir)/abl/src \ + -I$(top_srcdir)/aut/src \ + -I$(top_srcdir)/bdd/src \ + -I$(top_srcdir)/fsm/src \ + -I$(top_srcdir)/ftl/src \ + -I$(top_srcdir)/fvh/src \ +--I$(top_srcdir)/mbk/src \ +-@ALLIANCE_CFLAGS@ ++-I$(top_srcdir)/mbk/src + +-syf_LDADD = @ALLIANCE_LIBS@ \ +--L$(top_builddir)/abl/src/.libs \ +--L$(top_builddir)/aut/src/.libs \ +--L$(top_builddir)/bdd/src/.libs \ +--L$(top_builddir)/fks/src/.libs \ +--L$(top_builddir)/fsm/src/.libs \ +--L$(top_builddir)/ftl/src/.libs \ +--L$(top_builddir)/fvh/src/.libs \ +--L$(top_builddir)/mbk/src/.libs \ +- -lFtl -lFks -lFvh -lFsm \ +- -lBdd -lAbl -lAut -lMut ++syf_LDADD = @ALLIANCE_LIBS@ ++syf_LDADD += $(top_builddir)/abl/src/libAbl.la ++syf_LDADD += $(top_builddir)/aut/src/libAut.la ++syf_LDADD += $(top_builddir)/bdd/src/libBdd.la ++syf_LDADD += $(top_builddir)/fks/src/libFks.la ++syf_LDADD += $(top_builddir)/fsm/src/libFsm.la ++syf_LDADD += $(top_builddir)/ftl/src/libFtl.la ++syf_LDADD += $(top_builddir)/fvh/src/libFvh.la ++syf_LDADD += $(top_builddir)/mbk/src/libMut.la + + + syf_SOURCES = \ +diff --git a/alliance/src/vasy/src/Makefile.am b/alliance/src/vasy/src/Makefile.am +index 168d186..b89eca2 100644 +--- a/alliance/src/vasy/src/Makefile.am ++++ b/alliance/src/vasy/src/Makefile.am +@@ -2,29 +2,29 @@ + + bin_PROGRAMS = vasy + +-AM_CFLAGS = @ALLIANCE_CFLAGS@ \ +--I$(top_srcdir)/abl/src \ +--I$(top_srcdir)/aut/src \ +--I$(top_srcdir)/bdd/src \ +--I$(top_srcdir)/mbk/src \ +--I$(top_srcdir)/rtd/src \ +--I$(top_srcdir)/rtn/src \ +--I$(top_srcdir)/vex/src \ +--I$(top_srcdir)/vbh/src \ +--I$(top_srcdir)/vpn/src ++AM_CFLAGS = @ALLIANCE_CFLAGS@ + +-vasy_LDADD = @ALLIANCE_LIBS@ \ +--L$(top_builddir)/abl/src/.libs \ +--L$(top_builddir)/aut/src/.libs \ +--L$(top_builddir)/bdd/src/.libs \ +--L$(top_builddir)/mbk/src/.libs \ +--L$(top_builddir)/rtd/src/.libs \ +--L$(top_builddir)/rtn/src/.libs \ +--L$(top_builddir)/vbh/src/.libs \ +--L$(top_builddir)/vex/src/.libs \ +--L$(top_builddir)/vpn/src/.libs \ +- -lRtd -lRtn -lVpn -lVbh \ +- -lVex -lBdd -lAbl -lAut -lMut ++AM_CPPFLAGS = ++AM_CPPFLAGS += -I$(top_srcdir)/abl/src ++AM_CPPFLAGS += -I$(top_srcdir)/aut/src ++AM_CPPFLAGS += -I$(top_srcdir)/bdd/src ++AM_CPPFLAGS += -I$(top_srcdir)/mbk/src ++AM_CPPFLAGS += -I$(top_srcdir)/rtd/src ++AM_CPPFLAGS += -I$(top_srcdir)/rtn/src ++AM_CPPFLAGS += -I$(top_srcdir)/vex/src ++AM_CPPFLAGS += -I$(top_srcdir)/vbh/src ++AM_CPPFLAGS += -I$(top_srcdir)/vpn/src ++ ++vasy_LDADD = @ALLIANCE_LIBS@ ++vasy_LDADD += $(top_builddir)/abl/src/libAbl.la ++vasy_LDADD += $(top_builddir)/aut/src/libAut.la ++vasy_LDADD += $(top_builddir)/bdd/src/libBdd.la ++vasy_LDADD += $(top_builddir)/mbk/src/libMut.la ++vasy_LDADD += $(top_builddir)/rtd/src/libRtd.la ++vasy_LDADD += $(top_builddir)/rtn/src/libRtn.la ++vasy_LDADD += $(top_builddir)/vbh/src/libVbh.la ++vasy_LDADD += $(top_builddir)/vex/src/libVex.la ++vasy_LDADD += $(top_builddir)/vpn/src/libVpn.la + + vasy_SOURCES = \ + vasy_analys.c vasy_drvvlog.h vasy_mulwait.c vasy_redwait.h \ +diff --git a/alliance/src/vbh/src/Makefile.am b/alliance/src/vbh/src/Makefile.am +index d017730..e3b8c97 100644 +--- a/alliance/src/vbh/src/Makefile.am ++++ b/alliance/src/vbh/src/Makefile.am +@@ -1,4 +1,4 @@ +-AM_CFLAGS = -I$(top_srcdir)/mbk/src \ ++AM_CPPFLAGS = -I$(top_srcdir)/mbk/src \ + -I$(top_srcdir)/aut/src \ + -I$(top_srcdir)/vex/src \ + -I$(top_srcdir)/vpn/src +@@ -13,7 +13,10 @@ libVbh_la_SOURCES = vbh.h vbh_add.c vbh_crt.c vbh_dup.c vbh_fre.c vbh_simp + vtl.h vtlacces.c vtlacces.h vtlerror.c vtlerror.h \ + vpd.h vpd_drive.h vpd_error.h vpd_parse.h \ + vpd_drive.c vpd_error.c vpd_parse.c +-libVbh_la_LIBADD = -lVpn -lVex -lAut -lMut ++libVbh_la_LIBADD = $(top_builddir)/vpn/src/libVpn.la ++libVbh_la_LIBADD += $(top_builddir)/vex/src/libVex.la ++libVbh_la_LIBADD += $(top_builddir)/aut/src/libAut.la ++libVbh_la_LIBADD += $(top_builddir)/mbk/src/libMut.la + + CLEANFILES = vbl_bcomp_y.c vbl_bcomp_y.h vbl_bcomp_l.c + +@@ -21,3 +24,5 @@ vbl_bcomp_y.c vbl_bcomp_y.h : $(srcdir)/vbl_bcomp_y.y + $(YACC) -d $(YFLAGS) $(srcdir)/vbl_bcomp_y.y && sed -e "s/yy/vbl_y_/g" -e "s/YY/VBL_Y_/g" y.tab.c > vbl_bcomp_y.c && sed -e "s/yy/vbl_y_/g" -e "s/YY/VBL_Y_/g" y.tab.h > vbl_bcomp_y.h + vbl_bcomp_l.c : $(srcdir)/vbl_bcomp_l.l vbl_bcomp_y.h + $(LEX) -t $(srcdir)/vbl_bcomp_l.l | sed -e "s/yy/vbl_y_/g" -e "s/YY/VBL_Y_/g" > vbl_bcomp_l.c ++ ++CLEANFILES += y.tab.c y.tab.h +diff --git a/alliance/src/vex/src/Makefile.am b/alliance/src/vex/src/Makefile.am +index 167c80e..f148ffc 100644 +--- a/alliance/src/vex/src/Makefile.am ++++ b/alliance/src/vex/src/Makefile.am +@@ -1,4 +1,4 @@ +-AM_CFLAGS = -I$(top_srcdir)/mbk/src -I$(top_srcdir)/aut/src ++AM_CPPFLAGS = -I$(top_srcdir)/mbk/src -I$(top_srcdir)/aut/src + lib_LTLIBRARIES = libVex.la + include_HEADERS = vex.h + libVex_la_SOURCES = vexcreate.h vexerror.c vexfree.h vexshift.c vexunflat.h \ +@@ -9,4 +9,6 @@ libVex_la_SOURCES = vexcreate.h vexerror.c vexfree.h vexshift.c vexunflat + vexalloc.h vexenv.c vexextend.h vexoptim.c vexslice.h \ + vexcreate.c vexenv.h vexfree.c vexoptim.h vexunflat.c + libVex_la_LDFLAGS = -version-info @VEX_DLL_VERSION@ +-libVex_la_LIBADD = -lAut -lMut ++libVex_la_LIBADD = ++libVex_la_LIBADD += $(top_builddir)/aut/src/libAut.la ++libVex_la_LIBADD += $(top_builddir)/mbk/src/libMut.la +diff --git a/alliance/src/vpn/src/Makefile.am b/alliance/src/vpn/src/Makefile.am +index c5687e9..e68b1af 100644 +--- a/alliance/src/vpn/src/Makefile.am ++++ b/alliance/src/vpn/src/Makefile.am +@@ -1,4 +1,4 @@ +-AM_CFLAGS = -I$(top_srcdir)/mbk/src -I$(top_srcdir)/aut/src -I$(top_srcdir)/vex/src ++AM_CPPFLAGS = -I$(top_srcdir)/mbk/src -I$(top_srcdir)/aut/src -I$(top_srcdir)/vex/src + lib_LTLIBRARIES = libVpn.la + include_HEADERS = vpn.h + libVpn_la_SOURCES = vpnalloc.c vpnenv.h vpnget.c vpnsimp.h \ +@@ -7,4 +7,7 @@ libVpn_la_SOURCES = vpnalloc.c vpnenv.h vpnget.c vpnsimp.h \ + vpnadd.c vpndel.h vpnfree.c vpnsearch.h vpnview.c \ + vpnadd.h vpnenv.c vpnfree.h vpnsimp.c vpnview.h + libVpn_la_LDFLAGS = -version-info @VPN_DLL_VERSION@ +-libVpn_la_LIBADD = -lVex -lAut -lMut ++libVpn_la_LIBADD = ++libVpn_la_LIBADD += $(top_builddir)/vex/src/libVex.la ++libVpn_la_LIBADD += $(top_builddir)/aut/src/libAut.la ++libVpn_la_LIBADD += $(top_builddir)/mbk/src/libMut.la +diff --git a/alliance/src/x2y/src/Makefile.am b/alliance/src/x2y/src/Makefile.am +index 48f3ae0..ffb43c7 100644 +--- a/alliance/src/x2y/src/Makefile.am ++++ b/alliance/src/x2y/src/Makefile.am +@@ -1,12 +1,16 @@ + # $Id: Makefile.am,v 1.8 2005/01/19 15:13:57 hcl Exp $ + +-AM_CFLAGS = @ALLIANCE_CFLAGS@ \ +--I$(top_srcdir)/mbk/src ++AM_CFLAGS = @ALLIANCE_CFLAGS@ ++AM_CPPFLAGS = -I$(top_srcdir)/mbk/src + + bin_PROGRAMS = x2y + +-x2y_LDADD = @ALLIANCE_LIBS@ \ +- -L$(top_builddir)/mbk/src/.libs \ +- -lMpu -lMlu -lMlo -lMph -lMut -lRcn +- ++x2y_LDADD = @ALLIANCE_LIBS@ ++x2y_LDADD += $(top_builddir)/mbk/src/libMpu.la ++x2y_LDADD += $(top_builddir)/mbk/src/libMlu.la ++x2y_LDADD += $(top_builddir)/mbk/src/libMlo.la ++x2y_LDADD += $(top_builddir)/mbk/src/libMph.la ++x2y_LDADD += $(top_builddir)/mbk/src/libMut.la ++x2y_LDADD += $(top_builddir)/mbk/src/libRcn.la ++ + x2y_SOURCES = x2y.c +diff --git a/alliance/src/xfsm/src/Makefile.am b/alliance/src/xfsm/src/Makefile.am +index e702229..7040cb1 100644 +--- a/alliance/src/xfsm/src/Makefile.am ++++ b/alliance/src/xfsm/src/Makefile.am +@@ -1,8 +1,9 @@ + ## Process this file with automake to produce Makefile.in + + bin_PROGRAMS = xfsm +-AM_CFLAGS = @ALLIANCE_CFLAGS@ @X_CFLAGS@ \ +- -DXFSM_DEFAULT_PARAM_NAME=\"${ALLIANCE_TOP}/etc/xfsm.par\" \ ++AM_CFLAGS = @ALLIANCE_CFLAGS@ @X_CFLAGS@ ++ ++AM_CPPFLAGS = -DXFSM_DEFAULT_PARAM_NAME=\"${ALLIANCE_TOP}/etc/xfsm.par\" \ + -DXMS_FILE_NAME=\".xfsm.cfg\" \ + -I$(top_srcdir)/abl/src \ + -I$(top_srcdir)/aut/src \ +@@ -42,18 +43,16 @@ ALL_X_LIBS = $(X_LDFLAGS) $(LIBXM) $(LIBXT) \ + $(LIBXP) $(LIBXEXT) $(LIBX11) + + ++xfsm_LDADD = @ALLIANCE_LIBS@ $(ALL_X_LIBS) ++xfsm_LDADD += $(top_builddir)/ftl/src/libFtl.la ++xfsm_LDADD += $(top_builddir)/fks/src/libFks.la ++xfsm_LDADD += $(top_builddir)/fvh/src/libFvh.la ++xfsm_LDADD += $(top_builddir)/fsm/src/libFsm.la ++xfsm_LDADD += $(top_builddir)/bdd/src/libBdd.la ++xfsm_LDADD += $(top_builddir)/abl/src/libAbl.la ++xfsm_LDADD += $(top_builddir)/aut/src/libAut.la ++xfsm_LDADD += $(top_builddir)/mbk/src/libMut.la + +-xfsm_LDADD = @ALLIANCE_LIBS@ $(ALL_X_LIBS) \ +--L$(top_builddir)/abl/src/.libs \ +--L$(top_builddir)/aut/src/.libs \ +--L$(top_builddir)/bdd/src/.libs \ +--L$(top_builddir)/fks/src/.libs \ +--L$(top_builddir)/fsm/src/.libs \ +--L$(top_builddir)/ftl/src/.libs \ +--L$(top_builddir)/fvh/src/.libs \ +--L$(top_builddir)/mbk/src/.libs \ +- -lFtl -lFks -lFvh -lFsm \ +- -lBdd -lAbl -lAut -lMut + + xfsm_SOURCES = \ + LIP6bw.h XME_search.c XMS_panel.c XMV_panel.h XMX_panel.h \ +diff --git a/alliance/src/xgra/src/Makefile.am b/alliance/src/xgra/src/Makefile.am +index 5ebd988..a78c146 100644 +--- a/alliance/src/xgra/src/Makefile.am ++++ b/alliance/src/xgra/src/Makefile.am +@@ -2,14 +2,14 @@ + + bin_PROGRAMS = xgra + AM_CFLAGS = @ALLIANCE_CFLAGS@ @X_CFLAGS@ \ ++ $(GLIB_CFLAGS) ++AM_CPPFLAGS = \ + -I$(top_srcdir)/aut/src \ + -I$(top_srcdir)/mbk/src \ + -DXGRA_DEFAULT_PARAM_NAME=\"${ALLIANCE_TOP}/etc/xgra.par\" \ + -DXMS_FILE_NAME=\".xgra.cfg\" \ +- $(GLIB_CFLAGS) \ + -DG_LOG_DOMAIN=\"xgra\" + +- + # ----------------------------------------------------------------------------- + # X Libraries. + # ----------------------------------------------------------------------------- +@@ -43,9 +43,7 @@ ALL_X_LIBS = $(X_LDFLAGS) $(LIBXM) $(LIBXT) \ + + + xgra_LDADD = @ALLIANCE_LIBS@ $(GLIB_CFLAGS) $(ALL_X_LIBS) \ +--L$(top_builddir)/aut/src \ +--L$(top_builddir)/mbk/src \ +--lAut -lMut ++$(top_builddir)/aut/src/libAut.la $(top_builddir)/mbk/src/libMut.la + + xgra_SOURCES = \ + LIP6bw.h XME_dialog.c XME_dialog.h XME_edit.c XME_edit.h XME.h XME_menu.c \ +diff --git a/alliance/src/xpat/src/Makefile.am b/alliance/src/xpat/src/Makefile.am +index 0ade0a1..9ab3be2 100644 +--- a/alliance/src/xpat/src/Makefile.am ++++ b/alliance/src/xpat/src/Makefile.am +@@ -1,10 +1,11 @@ + ## Process this file with automake to produce Makefile.in + + bin_PROGRAMS = xpat +-AM_CFLAGS = @ALLIANCE_CFLAGS@ @X_CFLAGS@ \ +- -DXPAT_DEFAULT_PARAM_NAME=\"${ALLIANCE_TOP}/etc/xpat.par\" \ +- -DXMS_FILE_NAME=\".xpat.cfg\" \ +- -I$(top_srcdir)/aut/src \ ++AM_CFLAGS = @ALLIANCE_CFLAGS@ @X_CFLAGS@ ++AM_CPPFLAGS = -DXPAT_DEFAULT_PARAM_NAME=\"${ALLIANCE_TOP}/etc/xpat.par\" \ ++ -DXMS_FILE_NAME=\".xpat.cfg\" ++ ++AM_CPPFLAGS += -I$(top_srcdir)/aut/src \ + -I$(top_srcdir)/mbk/src \ + -I$(top_srcdir)/pat/src + +@@ -40,11 +41,10 @@ ALL_X_LIBS = $(X_LDFLAGS) $(LIBXM) $(LIBXT) \ + + + +-xpat_LDADD = @ALLIANCE_LIBS@ $(ALL_X_LIBS) \ +- -L$(top_builddir)/aut/src/.libs \ +- -L$(top_builddir)/mbk/src/.libs \ +- -L$(top_builddir)/pat/src/.libs \ +- -lPat -lAut -lMut ++xpat_LDADD = @ALLIANCE_LIBS@ $(ALL_X_LIBS) ++xpat_LDADD += $(top_builddir)/pat/src/libPat.la ++xpat_LDADD += $(top_builddir)/aut/src/libAut.la ++xpat_LDADD += $(top_builddir)/mbk/src/libMut.la + + xpat_SOURCES = \ + LIP6bw.h XME_dialog.c XME_dialog.h XME_edit.c XME_edit.h \ +diff --git a/alliance/src/xsch/src/Makefile.am b/alliance/src/xsch/src/Makefile.am +index df964a2..677076a 100644 +--- a/alliance/src/xsch/src/Makefile.am ++++ b/alliance/src/xsch/src/Makefile.am +@@ -1,8 +1,8 @@ + ## Process this file with automake to produce Makefile.in + + bin_PROGRAMS = xsch +-AM_CFLAGS = @ALLIANCE_CFLAGS@ @X_CFLAGS@ \ +- -DXSCH_DEFAULT_PARAM_NAME=\"${ALLIANCE_TOP}/etc/xsch.par\" \ ++AM_CFLAGS = @ALLIANCE_CFLAGS@ @X_CFLAGS@ ++AM_CPPFLAGS = -DXSCH_DEFAULT_PARAM_NAME=\"${ALLIANCE_TOP}/etc/xsch.par\" \ + -DXMS_FILE_NAME=\".xsch.cfg\" \ + -I$(top_srcdir)/abe/src \ + -I$(top_srcdir)/abl/src \ +@@ -44,15 +44,16 @@ ALL_X_LIBS = $(X_LDFLAGS) $(LIBXM) $(LIBXT) \ + + + +-xsch_LDADD = @ALLIANCE_LIBS@ $(ALL_X_LIBS) \ +- -L$(top_builddir)/abe/src/.libs \ +- -L$(top_builddir)/abl/src/.libs \ +- -L$(top_builddir)/abv/src/.libs \ +- -L$(top_builddir)/aut/src/.libs \ +- -L$(top_builddir)/bdd/src/.libs \ +- -L$(top_builddir)/mbk/src/.libs \ +- -L$(top_builddir)/scl/src/.libs \ +- -lScl -lMlu -lMlo -lMut -lAbv -lAbe -lBdd -lAbl -lAut -lRcn ++xsch_LDADD = @ALLIANCE_LIBS@ $(ALL_X_LIBS) ++xsch_LDADD += $(top_builddir)/abe/src/libAbe.la ++xsch_LDADD += $(top_builddir)/abl/src/libAbl.la ++xsch_LDADD += $(top_builddir)/abv/src/libAbv.la ++xsch_LDADD += $(top_builddir)/aut/src/libAut.la ++xsch_LDADD += $(top_builddir)/bdd/src/libBdd.la ++xsch_LDADD += $(top_builddir)/mbk/src/libMut.la ++xsch_LDADD += $(top_builddir)/scl/src/libScl.la ++xsch_LDADD += $(top_builddir)/mbk/src/libMlo.la ++xsch_LDADD += $(top_builddir)/mbk/src/libMlu.la + + xsch_SOURCES = \ + LIP6bw.h XME_dialog.c XME_dialog.h XME_edit.c XME_edit.h XME.h XME_menu.c XME_menu.h \ +diff --git a/alliance/src/xvpn/src/Makefile.am b/alliance/src/xvpn/src/Makefile.am +index fdb4ff6..1a88cbe 100644 +--- a/alliance/src/xvpn/src/Makefile.am ++++ b/alliance/src/xvpn/src/Makefile.am +@@ -1,7 +1,8 @@ + ## Process this file with automake to produce Makefile.in + + bin_PROGRAMS = xvpn +-AM_CFLAGS = @ALLIANCE_CFLAGS@ @X_CFLAGS@ \ ++AM_CFLAGS = @ALLIANCE_CFLAGS@ @X_CFLAGS@ ++AM_CPPFLAGS = \ + -DXVPN_DEFAULT_PARAM_NAME=\"${ALLIANCE_TOP}/etc/xvpn.par\" \ + -DXMS_FILE_NAME=\".xvpn.cfg\" \ + -I$(top_srcdir)/aut/src \ +@@ -44,14 +45,13 @@ ALL_X_LIBS = $(X_LDFLAGS) $(LIBXM) $(LIBXT) \ + + + +-xvpn_LDADD = @ALLIANCE_LIBS@ $(ALL_X_LIBS) \ +- -L$(top_builddir)/abl/src/.libs \ +- -L$(top_builddir)/aut/src/.libs \ +- -L$(top_builddir)/mbk/src/.libs \ +- -L$(top_builddir)/vbh/src/.libs \ +- -L$(top_builddir)/vex/src/.libs \ +- -L$(top_builddir)/vpn/src/.libs \ +- -lVpn -lVbh -lVex -lAbl -lAut -lMut ++xvpn_LDADD = @ALLIANCE_LIBS@ $(ALL_X_LIBS) ++xvpn_LDADD += $(top_builddir)/abl/src/libAbl.la ++xvpn_LDADD += $(top_builddir)/aut/src/libAut.la ++xvpn_LDADD += $(top_builddir)/mbk/src/libMut.la ++xvpn_LDADD += $(top_builddir)/vbh/src/libVbh.la ++xvpn_LDADD += $(top_builddir)/vex/src/libVex.la ++xvpn_LDADD += $(top_builddir)/vpn/src/libVpn.la + + xvpn_SOURCES = \ + LIP6bw.h XME_dialog.c XME_dialog.h XME_edit.c XME_edit.h XME.h XME_menu.c \ +-- +2.5.0 + diff --git a/0009-Misc.-doc-fixes.patch b/0009-Misc.-doc-fixes.patch new file mode 100644 index 0000000..02b75ff --- /dev/null +++ b/0009-Misc.-doc-fixes.patch @@ -0,0 +1,388 @@ +From 57060f1447e54d636271433309a6813752ec26dc Mon Sep 17 00:00:00 2001 +From: =?UTF-8?q?Ralf=20Cors=C3=A9pius?= +Date: Sun, 28 Feb 2016 15:03:03 +0100 +Subject: [PATCH 09/10] Misc. doc fixes. + +--- + alliance/src/boog/doc/boog.1 | 2 +- + .../documentation/tutorials/place_and_route/tex/place_and_route.tex | 1 - + .../src/documentation/tutorials/simulation/src/addaccu_beh/addaccu.vbe | 0 + .../documentation/tutorials/simulation/src/addaccu_beh/addaccu4.vhdl | 0 + .../documentation/tutorials/simulation/src/addaccu_beh/addaccu_dly.vbe | 0 + .../documentation/tutorials/simulation/src/addaccu_beh/patterns.pat | 0 + .../tutorials/simulation/src/addaccu_beh/patterns_dly.pat | 0 + .../src/documentation/tutorials/simulation/src/addaccu_struct/accu.vbe | 0 + .../src/documentation/tutorials/simulation/src/addaccu_struct/accu.vst | 0 + .../documentation/tutorials/simulation/src/addaccu_struct/addaccu.vbe | 0 + .../documentation/tutorials/simulation/src/addaccu_struct/addaccu.vst | 0 + .../src/documentation/tutorials/simulation/src/addaccu_struct/alu.vbe | 0 + .../src/documentation/tutorials/simulation/src/addaccu_struct/alu.vst | 0 + .../src/documentation/tutorials/simulation/src/addaccu_struct/mux.vbe | 0 + .../src/documentation/tutorials/simulation/src/addaccu_struct/mux.vst | 0 + .../documentation/tutorials/simulation/src/addaccu_struct/pat_new.c | 0 + alliance/src/documentation/tutorials/simulation/tex/simulation.tex | 1 - + alliance/src/documentation/tutorials/start/Makefile | 2 +- + alliance/src/documentation/tutorials/start/start.tex | 2 +- + alliance/src/documentation/tutorials/synthesis/src/amdbug/amd_0.vbe | 0 + alliance/src/documentation/tutorials/synthesis/src/amdbug/amd_1.vbe | 0 + alliance/src/documentation/tutorials/synthesis/src/amdbug/amd_10.vbe | 0 + alliance/src/documentation/tutorials/synthesis/src/amdbug/amd_11.vbe | 0 + alliance/src/documentation/tutorials/synthesis/src/amdbug/amd_12.vbe | 0 + alliance/src/documentation/tutorials/synthesis/src/amdbug/amd_13.vbe | 0 + alliance/src/documentation/tutorials/synthesis/src/amdbug/amd_14.vbe | 0 + alliance/src/documentation/tutorials/synthesis/src/amdbug/amd_15.vbe | 0 + alliance/src/documentation/tutorials/synthesis/src/amdbug/amd_16.vbe | 0 + alliance/src/documentation/tutorials/synthesis/src/amdbug/amd_17.vbe | 0 + alliance/src/documentation/tutorials/synthesis/src/amdbug/amd_18.vbe | 0 + alliance/src/documentation/tutorials/synthesis/src/amdbug/amd_19.vbe | 0 + alliance/src/documentation/tutorials/synthesis/src/amdbug/amd_2.vbe | 0 + alliance/src/documentation/tutorials/synthesis/src/amdbug/amd_20.vbe | 0 + alliance/src/documentation/tutorials/synthesis/src/amdbug/amd_21.vbe | 0 + alliance/src/documentation/tutorials/synthesis/src/amdbug/amd_22.vbe | 0 + alliance/src/documentation/tutorials/synthesis/src/amdbug/amd_23.vbe | 0 + alliance/src/documentation/tutorials/synthesis/src/amdbug/amd_24.vbe | 0 + alliance/src/documentation/tutorials/synthesis/src/amdbug/amd_3.vbe | 0 + alliance/src/documentation/tutorials/synthesis/src/amdbug/amd_4.vbe | 0 + alliance/src/documentation/tutorials/synthesis/src/amdbug/amd_5.vbe | 0 + alliance/src/documentation/tutorials/synthesis/src/amdbug/amd_6.vbe | 0 + alliance/src/documentation/tutorials/synthesis/src/amdbug/amd_7.vbe | 0 + alliance/src/documentation/tutorials/synthesis/src/amdbug/amd_8.vbe | 0 + alliance/src/documentation/tutorials/synthesis/src/amdbug/amd_9.vbe | 0 + alliance/src/documentation/tutorials/synthesis/src/amdbug/amd_ok.vbe | 0 + alliance/src/documentation/tutorials/synthesis/tex/synthesis.tex | 1 - + alliance/src/fsm/man1/fsm.1 | 2 +- + alliance/src/mbk/man3/viewlofigcon.3 | 3 ++- + alliance/src/mbk/man3/viewphfig.3 | 3 ++- + alliance/src/mbk/man3/viewphvia.3 | 3 ++- + alliance/src/nero/doc/man1/nero.1 | 1 - + alliance/src/ring/doc/ring.1 | 2 +- + 52 files changed, 11 insertions(+), 12 deletions(-) + mode change 100755 => 100644 alliance/src/documentation/tutorials/simulation/src/addaccu_beh/addaccu.vbe + mode change 100755 => 100644 alliance/src/documentation/tutorials/simulation/src/addaccu_beh/addaccu4.vhdl + mode change 100755 => 100644 alliance/src/documentation/tutorials/simulation/src/addaccu_beh/addaccu_dly.vbe + mode change 100755 => 100644 alliance/src/documentation/tutorials/simulation/src/addaccu_beh/patterns.pat + mode change 100755 => 100644 alliance/src/documentation/tutorials/simulation/src/addaccu_beh/patterns_dly.pat + mode change 100755 => 100644 alliance/src/documentation/tutorials/simulation/src/addaccu_struct/accu.vbe + mode change 100755 => 100644 alliance/src/documentation/tutorials/simulation/src/addaccu_struct/accu.vst + mode change 100755 => 100644 alliance/src/documentation/tutorials/simulation/src/addaccu_struct/addaccu.vbe + mode change 100755 => 100644 alliance/src/documentation/tutorials/simulation/src/addaccu_struct/addaccu.vst + mode change 100755 => 100644 alliance/src/documentation/tutorials/simulation/src/addaccu_struct/alu.vbe + mode change 100755 => 100644 alliance/src/documentation/tutorials/simulation/src/addaccu_struct/alu.vst + mode change 100755 => 100644 alliance/src/documentation/tutorials/simulation/src/addaccu_struct/mux.vbe + mode change 100755 => 100644 alliance/src/documentation/tutorials/simulation/src/addaccu_struct/mux.vst + mode change 100755 => 100644 alliance/src/documentation/tutorials/simulation/src/addaccu_struct/pat_new.c + mode change 100755 => 100644 alliance/src/documentation/tutorials/start/Makefile + mode change 100755 => 100644 alliance/src/documentation/tutorials/start/start.tex + mode change 100755 => 100644 alliance/src/documentation/tutorials/synthesis/src/amdbug/amd_0.vbe + mode change 100755 => 100644 alliance/src/documentation/tutorials/synthesis/src/amdbug/amd_1.vbe + mode change 100755 => 100644 alliance/src/documentation/tutorials/synthesis/src/amdbug/amd_10.vbe + mode change 100755 => 100644 alliance/src/documentation/tutorials/synthesis/src/amdbug/amd_11.vbe + mode change 100755 => 100644 alliance/src/documentation/tutorials/synthesis/src/amdbug/amd_12.vbe + mode change 100755 => 100644 alliance/src/documentation/tutorials/synthesis/src/amdbug/amd_13.vbe + mode change 100755 => 100644 alliance/src/documentation/tutorials/synthesis/src/amdbug/amd_14.vbe + mode change 100755 => 100644 alliance/src/documentation/tutorials/synthesis/src/amdbug/amd_15.vbe + mode change 100755 => 100644 alliance/src/documentation/tutorials/synthesis/src/amdbug/amd_16.vbe + mode change 100755 => 100644 alliance/src/documentation/tutorials/synthesis/src/amdbug/amd_17.vbe + mode change 100755 => 100644 alliance/src/documentation/tutorials/synthesis/src/amdbug/amd_18.vbe + mode change 100755 => 100644 alliance/src/documentation/tutorials/synthesis/src/amdbug/amd_19.vbe + mode change 100755 => 100644 alliance/src/documentation/tutorials/synthesis/src/amdbug/amd_2.vbe + mode change 100755 => 100644 alliance/src/documentation/tutorials/synthesis/src/amdbug/amd_20.vbe + mode change 100755 => 100644 alliance/src/documentation/tutorials/synthesis/src/amdbug/amd_21.vbe + mode change 100755 => 100644 alliance/src/documentation/tutorials/synthesis/src/amdbug/amd_22.vbe + mode change 100755 => 100644 alliance/src/documentation/tutorials/synthesis/src/amdbug/amd_23.vbe + mode change 100755 => 100644 alliance/src/documentation/tutorials/synthesis/src/amdbug/amd_24.vbe + mode change 100755 => 100644 alliance/src/documentation/tutorials/synthesis/src/amdbug/amd_3.vbe + mode change 100755 => 100644 alliance/src/documentation/tutorials/synthesis/src/amdbug/amd_4.vbe + mode change 100755 => 100644 alliance/src/documentation/tutorials/synthesis/src/amdbug/amd_5.vbe + mode change 100755 => 100644 alliance/src/documentation/tutorials/synthesis/src/amdbug/amd_6.vbe + mode change 100755 => 100644 alliance/src/documentation/tutorials/synthesis/src/amdbug/amd_7.vbe + mode change 100755 => 100644 alliance/src/documentation/tutorials/synthesis/src/amdbug/amd_8.vbe + mode change 100755 => 100644 alliance/src/documentation/tutorials/synthesis/src/amdbug/amd_9.vbe + mode change 100755 => 100644 alliance/src/documentation/tutorials/synthesis/src/amdbug/amd_ok.vbe + mode change 100755 => 100644 alliance/src/documentation/tutorials/synthesis/tex/synthesis.tex + +diff --git a/alliance/src/boog/doc/boog.1 b/alliance/src/boog/doc/boog.1 +index 052524c..44f6014 100644 +--- a/alliance/src/boog/doc/boog.1 ++++ b/alliance/src/boog/doc/boog.1 +@@ -136,7 +136,7 @@ Just another way to show explicitely the \f4VST\fP output file name. + Just another way to show explicitely the \f4LAX\fP parameter file name. + .TP 10 + \f4\-d debug_file\fP +-Generates a \f4VBE\f debug file. It comes from internal result algorithm. Users aren't concerned. ++Generates a \f4VBE\fP debug file. It comes from internal result algorithm. Users aren't concerned. + .br + + .SH ENVIRONMENT VARIABLES +diff --git a/alliance/src/documentation/tutorials/place_and_route/tex/place_and_route.tex b/alliance/src/documentation/tutorials/place_and_route/tex/place_and_route.tex +index 8d51631..0115a94 100644 +--- a/alliance/src/documentation/tutorials/place_and_route/tex/place_and_route.tex ++++ b/alliance/src/documentation/tutorials/place_and_route/tex/place_and_route.tex +@@ -85,7 +85,6 @@ xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx + %\end{figure} + %---------------------------------- document --------------------------------- + \begin{document} +-\setlength{\footrulewidth}{0.6pt} + + \title{ + {\Huge ALLIANCE TUTORIAL \\} +diff --git a/alliance/src/documentation/tutorials/simulation/src/addaccu_beh/addaccu.vbe b/alliance/src/documentation/tutorials/simulation/src/addaccu_beh/addaccu.vbe +old mode 100755 +new mode 100644 +diff --git a/alliance/src/documentation/tutorials/simulation/src/addaccu_beh/addaccu4.vhdl b/alliance/src/documentation/tutorials/simulation/src/addaccu_beh/addaccu4.vhdl +old mode 100755 +new mode 100644 +diff --git a/alliance/src/documentation/tutorials/simulation/src/addaccu_beh/addaccu_dly.vbe b/alliance/src/documentation/tutorials/simulation/src/addaccu_beh/addaccu_dly.vbe +old mode 100755 +new mode 100644 +diff --git a/alliance/src/documentation/tutorials/simulation/src/addaccu_beh/patterns.pat b/alliance/src/documentation/tutorials/simulation/src/addaccu_beh/patterns.pat +old mode 100755 +new mode 100644 +diff --git a/alliance/src/documentation/tutorials/simulation/src/addaccu_beh/patterns_dly.pat b/alliance/src/documentation/tutorials/simulation/src/addaccu_beh/patterns_dly.pat +old mode 100755 +new mode 100644 +diff --git a/alliance/src/documentation/tutorials/simulation/src/addaccu_struct/accu.vbe b/alliance/src/documentation/tutorials/simulation/src/addaccu_struct/accu.vbe +old mode 100755 +new mode 100644 +diff --git a/alliance/src/documentation/tutorials/simulation/src/addaccu_struct/accu.vst b/alliance/src/documentation/tutorials/simulation/src/addaccu_struct/accu.vst +old mode 100755 +new mode 100644 +diff --git a/alliance/src/documentation/tutorials/simulation/src/addaccu_struct/addaccu.vbe b/alliance/src/documentation/tutorials/simulation/src/addaccu_struct/addaccu.vbe +old mode 100755 +new mode 100644 +diff --git a/alliance/src/documentation/tutorials/simulation/src/addaccu_struct/addaccu.vst b/alliance/src/documentation/tutorials/simulation/src/addaccu_struct/addaccu.vst +old mode 100755 +new mode 100644 +diff --git a/alliance/src/documentation/tutorials/simulation/src/addaccu_struct/alu.vbe b/alliance/src/documentation/tutorials/simulation/src/addaccu_struct/alu.vbe +old mode 100755 +new mode 100644 +diff --git a/alliance/src/documentation/tutorials/simulation/src/addaccu_struct/alu.vst b/alliance/src/documentation/tutorials/simulation/src/addaccu_struct/alu.vst +old mode 100755 +new mode 100644 +diff --git a/alliance/src/documentation/tutorials/simulation/src/addaccu_struct/mux.vbe b/alliance/src/documentation/tutorials/simulation/src/addaccu_struct/mux.vbe +old mode 100755 +new mode 100644 +diff --git a/alliance/src/documentation/tutorials/simulation/src/addaccu_struct/mux.vst b/alliance/src/documentation/tutorials/simulation/src/addaccu_struct/mux.vst +old mode 100755 +new mode 100644 +diff --git a/alliance/src/documentation/tutorials/simulation/src/addaccu_struct/pat_new.c b/alliance/src/documentation/tutorials/simulation/src/addaccu_struct/pat_new.c +old mode 100755 +new mode 100644 +diff --git a/alliance/src/documentation/tutorials/simulation/tex/simulation.tex b/alliance/src/documentation/tutorials/simulation/tex/simulation.tex +index 7a7bc19..b7c6299 100644 +--- a/alliance/src/documentation/tutorials/simulation/tex/simulation.tex ++++ b/alliance/src/documentation/tutorials/simulation/tex/simulation.tex +@@ -91,7 +91,6 @@ xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx + %---------------------------------- document --------------------------------- + + \begin{document} +-\setlength{\footrulewidth}{0.6pt} + + \title{ + {\Huge ALLIANCE TUTORIAL\\} +diff --git a/alliance/src/documentation/tutorials/start/Makefile b/alliance/src/documentation/tutorials/start/Makefile +old mode 100755 +new mode 100644 +index 2a99685..4649755 +--- a/alliance/src/documentation/tutorials/start/Makefile ++++ b/alliance/src/documentation/tutorials/start/Makefile +@@ -14,4 +14,4 @@ start.dvi : start.tex + latex start.tex + + clean : +- rm -f $(MYFILE).ps $(MYFILE).pdf *.log *.dvi *.aux ++ rm -f start.ps start.pdf *.log *.dvi *.aux +diff --git a/alliance/src/documentation/tutorials/start/start.tex b/alliance/src/documentation/tutorials/start/start.tex +old mode 100755 +new mode 100644 +index c88481b..7ee4a90 +--- a/alliance/src/documentation/tutorials/start/start.tex ++++ b/alliance/src/documentation/tutorials/start/start.tex +@@ -144,7 +144,7 @@ To see it, please enter the following command : + ~alp/addaccu %-) env | grep MBK + \end{phraseverbatim} + +-\begin{figure}[H]\center\leavevmode ++\begin{figure}[p]\center\leavevmode + \begin{framedverbatim} + ~alp/addaccu %-) env | grep MBK + MBK_OUT_PH=ap +diff --git a/alliance/src/documentation/tutorials/synthesis/src/amdbug/amd_0.vbe b/alliance/src/documentation/tutorials/synthesis/src/amdbug/amd_0.vbe +old mode 100755 +new mode 100644 +diff --git a/alliance/src/documentation/tutorials/synthesis/src/amdbug/amd_1.vbe b/alliance/src/documentation/tutorials/synthesis/src/amdbug/amd_1.vbe +old mode 100755 +new mode 100644 +diff --git a/alliance/src/documentation/tutorials/synthesis/src/amdbug/amd_10.vbe b/alliance/src/documentation/tutorials/synthesis/src/amdbug/amd_10.vbe +old mode 100755 +new mode 100644 +diff --git a/alliance/src/documentation/tutorials/synthesis/src/amdbug/amd_11.vbe b/alliance/src/documentation/tutorials/synthesis/src/amdbug/amd_11.vbe +old mode 100755 +new mode 100644 +diff --git a/alliance/src/documentation/tutorials/synthesis/src/amdbug/amd_12.vbe b/alliance/src/documentation/tutorials/synthesis/src/amdbug/amd_12.vbe +old mode 100755 +new mode 100644 +diff --git a/alliance/src/documentation/tutorials/synthesis/src/amdbug/amd_13.vbe b/alliance/src/documentation/tutorials/synthesis/src/amdbug/amd_13.vbe +old mode 100755 +new mode 100644 +diff --git a/alliance/src/documentation/tutorials/synthesis/src/amdbug/amd_14.vbe b/alliance/src/documentation/tutorials/synthesis/src/amdbug/amd_14.vbe +old mode 100755 +new mode 100644 +diff --git a/alliance/src/documentation/tutorials/synthesis/src/amdbug/amd_15.vbe b/alliance/src/documentation/tutorials/synthesis/src/amdbug/amd_15.vbe +old mode 100755 +new mode 100644 +diff --git a/alliance/src/documentation/tutorials/synthesis/src/amdbug/amd_16.vbe b/alliance/src/documentation/tutorials/synthesis/src/amdbug/amd_16.vbe +old mode 100755 +new mode 100644 +diff --git a/alliance/src/documentation/tutorials/synthesis/src/amdbug/amd_17.vbe b/alliance/src/documentation/tutorials/synthesis/src/amdbug/amd_17.vbe +old mode 100755 +new mode 100644 +diff --git a/alliance/src/documentation/tutorials/synthesis/src/amdbug/amd_18.vbe b/alliance/src/documentation/tutorials/synthesis/src/amdbug/amd_18.vbe +old mode 100755 +new mode 100644 +diff --git a/alliance/src/documentation/tutorials/synthesis/src/amdbug/amd_19.vbe b/alliance/src/documentation/tutorials/synthesis/src/amdbug/amd_19.vbe +old mode 100755 +new mode 100644 +diff --git a/alliance/src/documentation/tutorials/synthesis/src/amdbug/amd_2.vbe b/alliance/src/documentation/tutorials/synthesis/src/amdbug/amd_2.vbe +old mode 100755 +new mode 100644 +diff --git a/alliance/src/documentation/tutorials/synthesis/src/amdbug/amd_20.vbe b/alliance/src/documentation/tutorials/synthesis/src/amdbug/amd_20.vbe +old mode 100755 +new mode 100644 +diff --git a/alliance/src/documentation/tutorials/synthesis/src/amdbug/amd_21.vbe b/alliance/src/documentation/tutorials/synthesis/src/amdbug/amd_21.vbe +old mode 100755 +new mode 100644 +diff --git a/alliance/src/documentation/tutorials/synthesis/src/amdbug/amd_22.vbe b/alliance/src/documentation/tutorials/synthesis/src/amdbug/amd_22.vbe +old mode 100755 +new mode 100644 +diff --git a/alliance/src/documentation/tutorials/synthesis/src/amdbug/amd_23.vbe b/alliance/src/documentation/tutorials/synthesis/src/amdbug/amd_23.vbe +old mode 100755 +new mode 100644 +diff --git a/alliance/src/documentation/tutorials/synthesis/src/amdbug/amd_24.vbe b/alliance/src/documentation/tutorials/synthesis/src/amdbug/amd_24.vbe +old mode 100755 +new mode 100644 +diff --git a/alliance/src/documentation/tutorials/synthesis/src/amdbug/amd_3.vbe b/alliance/src/documentation/tutorials/synthesis/src/amdbug/amd_3.vbe +old mode 100755 +new mode 100644 +diff --git a/alliance/src/documentation/tutorials/synthesis/src/amdbug/amd_4.vbe b/alliance/src/documentation/tutorials/synthesis/src/amdbug/amd_4.vbe +old mode 100755 +new mode 100644 +diff --git a/alliance/src/documentation/tutorials/synthesis/src/amdbug/amd_5.vbe b/alliance/src/documentation/tutorials/synthesis/src/amdbug/amd_5.vbe +old mode 100755 +new mode 100644 +diff --git a/alliance/src/documentation/tutorials/synthesis/src/amdbug/amd_6.vbe b/alliance/src/documentation/tutorials/synthesis/src/amdbug/amd_6.vbe +old mode 100755 +new mode 100644 +diff --git a/alliance/src/documentation/tutorials/synthesis/src/amdbug/amd_7.vbe b/alliance/src/documentation/tutorials/synthesis/src/amdbug/amd_7.vbe +old mode 100755 +new mode 100644 +diff --git a/alliance/src/documentation/tutorials/synthesis/src/amdbug/amd_8.vbe b/alliance/src/documentation/tutorials/synthesis/src/amdbug/amd_8.vbe +old mode 100755 +new mode 100644 +diff --git a/alliance/src/documentation/tutorials/synthesis/src/amdbug/amd_9.vbe b/alliance/src/documentation/tutorials/synthesis/src/amdbug/amd_9.vbe +old mode 100755 +new mode 100644 +diff --git a/alliance/src/documentation/tutorials/synthesis/src/amdbug/amd_ok.vbe b/alliance/src/documentation/tutorials/synthesis/src/amdbug/amd_ok.vbe +old mode 100755 +new mode 100644 +diff --git a/alliance/src/documentation/tutorials/synthesis/tex/synthesis.tex b/alliance/src/documentation/tutorials/synthesis/tex/synthesis.tex +old mode 100755 +new mode 100644 +index bf2fdde..11cd8e9 +--- a/alliance/src/documentation/tutorials/synthesis/tex/synthesis.tex ++++ b/alliance/src/documentation/tutorials/synthesis/tex/synthesis.tex +@@ -85,7 +85,6 @@ xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx + + %---------------------------------- document --------------------------------- + \begin{document} +-\setlength{\footrulewidth}{0.6pt} + + \title{ + {\Huge ALLIANCE TUTORIAL\\} +diff --git a/alliance/src/fsm/man1/fsm.1 b/alliance/src/fsm/man1/fsm.1 +index a0f6142..ca58505 100644 +--- a/alliance/src/fsm/man1/fsm.1 ++++ b/alliance/src/fsm/man1/fsm.1 +@@ -40,7 +40,7 @@ Functions : + .TP 20 + .br + +-... ++\&... + + .TP 0 + libFsm101.a : +diff --git a/alliance/src/mbk/man3/viewlofigcon.3 b/alliance/src/mbk/man3/viewlofigcon.3 +index 413f80f..805ce0d 100644 +--- a/alliance/src/mbk/man3/viewlofigcon.3 ++++ b/alliance/src/mbk/man3/viewlofigcon.3 +@@ -10,10 +10,11 @@ viewlofigcon + .ti 0.2i + viewlofigcon + .XE2 \} +-.so man1/alc_origin.1 ++.TH VIEWLOFIGCON 3 "October 1, 1997" "ASIM/LIP6" "MBK LOGICAL FUNCTIONS" + .SH NAME + viewlofigcon \- display elements of a \fBlocon_list\fP attached to a + figure ++.so man1/alc_origin.1 + .SH SYNOPSYS + .nf + .if n \{\ +diff --git a/alliance/src/mbk/man3/viewphfig.3 b/alliance/src/mbk/man3/viewphfig.3 +index 1aa0842..374bb20 100644 +--- a/alliance/src/mbk/man3/viewphfig.3 ++++ b/alliance/src/mbk/man3/viewphfig.3 +@@ -10,9 +10,10 @@ viewphfig + .ti 0.2i + viewphfig + .XE0 \} +-.so man1/alc_origin.1 ++.TH VIEWPHSEG 3 "October 1, 1997" "ASIM/LIP6" "MBK PHYSICAL FUNCTIONS" + .SH NAME + viewphfig \- display elements of a \fBphfig_list\fP ++.so man1/alc_origin.1 + .SH SYNOPSYS + .nf + .if n \{\ +diff --git a/alliance/src/mbk/man3/viewphvia.3 b/alliance/src/mbk/man3/viewphvia.3 +index 1d58e48..209602a 100644 +--- a/alliance/src/mbk/man3/viewphvia.3 ++++ b/alliance/src/mbk/man3/viewphvia.3 +@@ -10,9 +10,10 @@ viewphvia + .ti 0.2i + viewphvia + .XE0 \} +-.so man1/alc_origin.1 ++.TH VIEWPHVIA 3 "October 1, 1997" "ASIM/LIP6" "MBK PHYSICAL FUNCTIONS" + .SH NAME + viewphvia \- display elements of a \fBphvia_list\fP ++.so man1/alc_origin.1 + .SH SYNOPSYS + .nf + .if n \{\ +diff --git a/alliance/src/nero/doc/man1/nero.1 b/alliance/src/nero/doc/man1/nero.1 +index e13b1ea..ed6f488 100644 +--- a/alliance/src/nero/doc/man1/nero.1 ++++ b/alliance/src/nero/doc/man1/nero.1 +@@ -1,4 +1,3 @@ +-.\\" auto-generated by docbook2man-spec $Revision: 1.4 $ + .TH "NERO" "1" "13 October 2002" "ASIM/LIP6" "Alliance - nero User's Manual" + .SH NAME + nero \- Negotiating Router +diff --git a/alliance/src/ring/doc/ring.1 b/alliance/src/ring/doc/ring.1 +index 054aa47..43a6be3 100644 +--- a/alliance/src/ring/doc/ring.1 ++++ b/alliance/src/ring/doc/ring.1 +@@ -110,7 +110,7 @@ piot_sp C + .br + pvssick_sp C + .br +-\.\.\.\. ++\&... + .br + pvdde_sp C + .br +-- +2.5.0 + diff --git a/0010-Fedora-profiles.patch b/0010-Fedora-profiles.patch new file mode 100644 index 0000000..d475ca8 --- /dev/null +++ b/0010-Fedora-profiles.patch @@ -0,0 +1,114 @@ +From 52c5cec07b86e606d5062da6e83ada94cf214c13 Mon Sep 17 00:00:00 2001 +From: =?UTF-8?q?Ralf=20Cors=C3=A9pius?= +Date: Tue, 1 Mar 2016 15:27:11 +0100 +Subject: [PATCH 10/10] Fedora profiles. + +--- + alliance/src/distrib/etc/alc_env.csh.in | 32 ++----------------------------- + alliance/src/distrib/etc/alc_env.sh.in | 34 +++------------------------------ + 2 files changed, 5 insertions(+), 61 deletions(-) + +diff --git a/alliance/src/distrib/etc/alc_env.csh.in b/alliance/src/distrib/etc/alc_env.csh.in +index cea6941..4051fba 100644 +--- a/alliance/src/distrib/etc/alc_env.csh.in ++++ b/alliance/src/distrib/etc/alc_env.csh.in +@@ -21,13 +21,8 @@ + + # Where the Alliance CAD is installed + setenv ALLIANCE_TOP "@prefix@" +- set SYSCONF_TOP "${ALLIANCE_TOP}/etc" +- set CELLS_TOP "${ALLIANCE_TOP}/cells" +- if ( "${ALLIANCE_TOP}" == "/usr/lib/alliance" ) then +-# For installation in the FHS. +- set SYSCONF_TOP "/etc/alliance" +- set CELLS_TOP "/usr/share/alliance/cells" +- endif ++ set SYSCONF_TOP "@sysconfdir@/alliance" ++ set CELLS_TOP "@datadir@/alliance/cells" + + + # Alliance environment variables. +@@ -75,29 +70,6 @@ + setenv ELP_TECHNO_NAME "${SYSCONF_TOP}/prol.elp" + + +-# System PATH variables, only needed when not installed in the FHS. +- if ( "${ALLIANCE_TOP}" != "/usr/lib/alliance" ) then +- if ( $?PATH ) then +- setenv PATH "${PATH}:${ALLIANCE_TOP}/bin" +- else +- setenv PATH "${ALLIANCE_TOP}/bin" +- endif +- +- if ( "`uname -o`" != "GNU/Linux" ) then +- # Only needed on Solaris (included in /etc/ld.so.conf under Linux). +- if ( $?LD_LIBRARY_PATH ) then +- setenv LD_LIBRARY_PATH "${LD_LIBRARY_PATH}:${ALLIANCE_TOP}/lib" +- else +- setenv LD_LIBRARY_PATH "${ALLIANCE_TOP}/lib" +- endif +- endif +- +- if ( $?MANPATH ) then +- setenv MANPATH "${MANPATH}:${ALLIANCE_TOP}/share/man" +- else +- setenv MANPATH ":${ALLIANCE_TOP}/share/man:`manpath`" +- endif +- endif + + # fixing *** ERROR *** : Variable MBK_SPI_MODEL not found. + setenv MBK_SPI_MODEL "${SYSCONF_TOP}/spimodel.cfg" +diff --git a/alliance/src/distrib/etc/alc_env.sh.in b/alliance/src/distrib/etc/alc_env.sh.in +index a4115f2..246eec6 100644 +--- a/alliance/src/distrib/etc/alc_env.sh.in ++++ b/alliance/src/distrib/etc/alc_env.sh.in +@@ -20,14 +20,9 @@ + + + # Where the Alliance CAD is installed +- ALLIANCE_TOP=@prefix@; export ALLIANCE_TOP +- SYSCONF_TOP=$ALLIANCE_TOP/etc +- CELLS_TOP=$ALLIANCE_TOP/cells +- if [ "$ALLIANCE_TOP" = "/usr/lib/alliance" ]; then +- # FHS Installation. +- SYSCONF_TOP="/etc/alliance" +- CELLS_TOP="/usr/share/alliance/cells" +- fi ++ ALLIANCE_TOP="@prefix@"; export ALLIANCE_TOP ++ SYSCONF_TOP="@sysconfdir@/alliance" ++ CELLS_TOP="@datadir@/alliance/cells" + + # Alliance environment variables. + MBK_IN_LO=vst; export MBK_IN_LO +@@ -76,28 +71,5 @@ + ELP_TECHNO_NAME=$SYSCONF_TOP/prol.elp; export ELP_TECHNO_NAME + + +-# System PATH variables, only needed when not installed in the FHS. +- if [ "$ALLIANCE_TOP" != "/usr/lib/alliance" ]; then +- PATH=$PATH:$ALLIANCE_TOP/bin +- export PATH +- +- # Only needed on Solaris (included in /etc/ld.so.conf under Linux). +- #if [ "`uname -o`" != "GNU/Linux" ]; then +- if [ -z "${LD_LIBRARY_PATH}" ]; then +- LD_LIBRARY_PATH=$ALLIANCE_TOP/lib +- else +- LD_LIBRARY_PATH=$LD_LIBRARY_PATH:$ALLIANCE_TOP/lib +- fi +- export LD_LIBRARY_PATH +- #fi +- +- if [ -z "${MANPATH}" ]; then +- MANPATH=:$ALLIANCE_TOP/share/man:$(manpath) +- else +- MANPATH=$MANPATH:$ALLIANCE_TOP/share/man +- fi +- export MANPATH +- fi +- + # fixing *** ERROR *** : Variable MBK_SPI_MODEL not found. + MBK_SPI_MODEL=$SYSCONF_TOP/spimodel.cfg; export MBK_SPI_MODEL +-- +2.5.0 + diff --git a/alliance-5.0-20090901-bison.patch b/alliance-5.0-20090901-bison.patch deleted file mode 100644 index 62998be..0000000 --- a/alliance-5.0-20090901-bison.patch +++ /dev/null @@ -1,25 +0,0 @@ -From debian/patches/10-fix-parser-extern.patch -Fix duplicate extern error with newer bison - ---- a/ppt/src/Makefile.am -+++ b/ppt/src/Makefile.am -@@ -19,7 +19,7 @@ pat_decl_y.c pat_decl_y.h : $(srcdir)/pat_decl_y.y - $(YACC) -d $(YFLAGS) $(srcdir)/pat_decl_y.y \ - && sed -e "s/yy/pat_decl_y_/g" -e "s/YY/PAT_DECL_Y_/g" y.tab.c \ - | sed -e "s/int[ ]*pat_decl_y_char;/extern int pat_decl_y_char;/" \ -- | sed -e "s/PAT_DECL_Y_STYPE[ ]*pat_decl_y_lval;/extern PAT_DECL_Y_STYPE pat_decl_y_lval;/" \ -+ | sed -e "s/PAT_DECL_Y_STYPE[ ]*pat_decl_y_lval;/PAT_DECL_Y_STYPE pat_decl_y_lval;/" \ - | sed -e "s/int[ ]*pat_decl_y_nerrs;/extern int pat_decl_y_nerrs;/" \ - > pat_decl_y.c \ - && sed -e "s/yy/pat_decl_y_/g" -e "s/YY/PAT_DECL_Y_/g" y.tab.h > pat_decl_y.h ---- a/ppt/src/Makefile.in -+++ b/ppt/src/Makefile.in -@@ -701,7 +701,7 @@ pat_decl_y.c pat_decl_y.h : $(srcdir)/pat_decl_y.y - $(YACC) -d $(YFLAGS) $(srcdir)/pat_decl_y.y \ - && sed -e "s/yy/pat_decl_y_/g" -e "s/YY/PAT_DECL_Y_/g" y.tab.c \ - | sed -e "s/int[ ]*pat_decl_y_char;/extern int pat_decl_y_char;/" \ -- | sed -e "s/PAT_DECL_Y_STYPE[ ]*pat_decl_y_lval;/extern PAT_DECL_Y_STYPE pat_decl_y_lval;/" \ -+ | sed -e "s/PAT_DECL_Y_STYPE[ ]*pat_decl_y_lval;/PAT_DECL_Y_STYPE pat_decl_y_lval;/" \ - | sed -e "s/int[ ]*pat_decl_y_nerrs;/extern int pat_decl_y_nerrs;/" \ - > pat_decl_y.c \ - && sed -e "s/yy/pat_decl_y_/g" -e "s/YY/PAT_DECL_Y_/g" y.tab.h > pat_decl_y.h diff --git a/alliance-5.0-20090901-format-security.patch b/alliance-5.0-20090901-format-security.patch deleted file mode 100644 index de54d36..0000000 --- a/alliance-5.0-20090901-format-security.patch +++ /dev/null @@ -1,85 +0,0 @@ ---- a/rtd/src/rtd_drive.c -+++ b/rtd/src/rtd_drive.c -@@ -100,7 +100,7 @@ static void RtlWriteNameFile( Name ) - RtlExprLength = Length; - } - -- fprintf( RtlFile, Name ); -+ fprintf( RtlFile, "%s", Name ); - } - - /*------------------------------------------------------------\ ---- a/vpd/src/vpd_drive.c -+++ b/vpd/src/vpd_drive.c -@@ -100,7 +100,7 @@ static void VpnWriteNameFile( Name ) - VpnExprLength = Length; - } - -- fprintf( VpnFile, Name ); -+ fprintf( VpnFile, "%s", Name ); - } - - /*------------------------------------------------------------\ ---- a/boog/src/bog_normalize_message.c -+++ b/boog/src/bog_normalize_message.c -@@ -106,7 +106,7 @@ extern void display_error_in_abl(char* message, chain_list *abl) - } - - fprintf(stderr,"BEH: "); -- fprintf(stderr,message); -+ fprintf(stderr,"%s",message); - fprintf(stderr," in '"); - fflush(stderr); - display_abl(abl); ---- a/l2p/src/drive_ps.c -+++ b/l2p/src/drive_ps.c -@@ -83,22 +83,22 @@ char *msg; - break; - case E_OPEN : - fprintf (stderr, "Problem while opening file "); -- fprintf (stderr, msg); -+ fprintf (stderr, "%s", msg); - break; - case E_CLOSE : - fprintf (stderr, "Problem while closing file "); -- fprintf (stderr, msg); -+ fprintf (stderr, "%s", msg); - break; - case E_WRITE : - fprintf (stderr, "Problem while writing file "); -- fprintf (stderr, msg); -+ fprintf (stderr, "%s", msg); - break; - case E_READ : - fprintf (stderr, "Problem while reading file "); -- fprintf (stderr, msg); -+ fprintf (stderr, "%s", msg); - break; - case E_OUTBOX : -- fprintf (stderr, msg); -+ fprintf (stderr, "%s", msg); - break; - default : - fprintf (stderr, "Unknow internal error"); ---- a/loon/src/lon_normalize_message.c -+++ b/loon/src/lon_normalize_message.c -@@ -106,7 +106,7 @@ extern void display_error_in_abl(char* message, chain_list *abl) - } - - fprintf(stderr,"BEH: "); -- fprintf(stderr,message); -+ fprintf(stderr,"%s",message); - fprintf(stderr," in '"); - fflush(stderr); - display_abl(abl); ---- a/sea/src/util_LEFDEF.c -+++ b/sea/src/util_LEFDEF.c -@@ -213,7 +213,7 @@ extern char *MBK2DEF_name(asLEF, asMBK) - *pI = (char)0; pI += 1; - sprintf (asLEF, "%s(%s)", sTmp, pI); - } else { -- sprintf (asLEF, sTmp); -+ sprintf (asLEF, "%s", sTmp); - } - - return (asLEF); diff --git a/alliance.spec b/alliance.spec index fcd0801..a90dad3 100644 --- a/alliance.spec +++ b/alliance.spec @@ -1,23 +1,37 @@ +%global snapdate 20160220 +%global commit 10a7b7e755d633a83e3f213198b59a69751259f1 +%global shortcommit %(c=%{commit}; echo ${c:0:7}) + Name: alliance Version: 5.1.1 -Release: 3%{?dist} +Release: 4.%{snapdate}git%{shortcommit}%{?dist} Summary: VLSI EDA System License: GPLv2 URL: https://soc-extras.lip6.fr/en/alliance-abstract-en/ Source: http://www-asim.lip6.fr/pub/alliance/distribution/latest/alliance-%{version}.tar.bz2 Source1: alliance.fedora -# Chitlesh's donated pictures to alliance -# included asfrom snapshot 20090901 - Source2: alliance-tutorials-go-all.sh Source3: alliance-tutorials-go-all-clean.sh Source4: alliance-examples-go-all.sh Source5: alliance-examples-go-all-clean.sh -# 2014-07-01: Notified upstream via e-mail to alliance-users@asim.lip6.fr -#Patch0: alliance-5.0-20090901-format-security.patch -# 2014-07-01: From debian: debian/patches/10-fix-parser-extern.patch -#Patch1: alliance-5.0-20090901-bison.patch + +# Update alliance-5.1.1 to commit %%{shortcommit} from +# https://www-soc.lip6.fr/git/alliance.git +Patch00: 0000-alliance-5.1.1-git%{shortcommit}.patch + +Patch11: 0001-Remove-stray-files.patch +Patch12: 0002-Update-autostuff.patch +Patch13: 0003-Consolidate-installation-dirs.patch +Patch14: 0004-Misc-installation-dirs-fixes.patch +Patch15: 0005-Use-inttypes-macros-to-print-int32_t.patch +Patch16: 0006-Use-ring_yy-instead-of-yy.patch +Patch17: 0007-Eliminate-CFLAGS.patch +Patch18: 0008-Rework-Makefile.ams.patch +Patch19: 0009-Misc.-doc-fixes.patch +Patch20: 0010-Fedora-profiles.patch + + BuildRequires: bison BuildRequires: byacc BuildRequires: desktop-file-utils @@ -34,12 +48,19 @@ BuildRequires: tex(picinpar.sty) BuildRequires: tex(subfigure.sty) BuildRequires: tex(wrapfig.sty) BuildRequires: transfig +BuildRequires: /usr/bin/convert +BuildRequires: autoconf automake libtool + %if 0%{?rhel} BuildRequires: openmotif-devel BuildRequires: pkgconfig %else +%if 0%{?fedora} >= 23 +BuildRequires: motif-devel +%else BuildRequires: lesstif-devel %endif +%endif Requires: xorg-x11-fonts-misc # RHBZ 442379 Requires(post): %{name}-libs%{?_isa} = %{version}-%{release} @@ -69,15 +90,22 @@ Alliance provides CAD tools covering most of all the digital design flow: Alliance is listed among Fedora Electronic Lab (FEL) packages. %package libs -Summary: Alliance VLSI CAD Sytem - multilibs +Summary: Alliance VLSI CAD System - Libraries Requires: %{name}%{?_isa} = %{version}-%{release} Requires: electronics-menu %description libs Architecture dependent files for the Alliance VLSI CAD Sytem. +%package devel +Summary: Alliance VLSI CAD System - Development libraries +Requires: %{name}-libs%{?_isa} = %{version}-%{release} + +%description devel +%{summary} + %package doc -Summary: Alliance VLSI CAD Sytem - Documentations +Summary: Alliance VLSI CAD System - Documentations BuildArch: noarch Requires: gnuplot BuildRequires: tetex-latex @@ -86,122 +114,103 @@ BuildRequires: tetex-latex Documentation and tutorials for the Alliance VLSI CAD Sytem. %prep -%setup -qn %{name}/src -#%patch0 -p1 -#%patch1 -p1 -rm -frv autom4te.cache +%setup -qn %{name} +%patch00 -p2 +%patch11 -p2 +%patch12 -p2 +%patch13 -p2 +%patch14 -p2 +%patch15 -p2 +%patch16 -p2 +%patch17 -p2 +%patch18 -p2 +%patch19 -p2 +%patch20 -p2 + +pushd src > /dev/null + +# Don't build attila +rm -r attila + +# Setup auto*stuff +./autostuff + +# The configure.ins confuse rpm +# rename them into configure.in~ +sed -i -e 's/configure.in/configure.in~/g' autostuff +for x in $(find */* -name configure.in); do +mv $x $x~ +done -cp -p %{SOURCE1} . -sed -i "s|ALLIANCE_TOP|%{prefix}|" distrib/*.desktop +chmod +x configure -# removed useless copyrighted (by Cadence) lines from the examples -# and even in alliance-run -# https://www-asim.lip6.fr/wws/arc/alliance-users/2007-07/msg00006.html +cp -p %{SOURCE1} . +sed -i "s|ALLIANCE_TOP/bin|%{_libdir}/alliance/bin|" distrib/*.desktop # ------------------------------------------------------------------------------ -# Description : 2008 March : TexLive introduction to Rawhide -sed -i "s|tutorials||" documentation/Makefile.in -sed -i "s|documentation/tutorials/Makefile||" configure* -pushd documentation/tutorials - # clean unneccessary files - rm Makefile* - rm *.pdf - # build documentation - for folder in place_and_route/tex start simulation/tex synthesis/tex; do - pushd $folder - make - popd - # remove useless directories before %%doc - rm -rf $folder - done - # Add automated scripts to tutorials - install -pm 755 %{SOURCE2} go-all.sh - install -pm 755 %{SOURCE3} go-all-clean.sh - # Fedora Electronic Lab self test for alliance - #./go-all.sh 2>&1 | tee self-test-tutorials.log - # clean temporary files - ./go-all-clean.sh -popd -# ------------------------------------------------------------------------------ - -# fixing flex and bison update on rawhide -sed -i '30i\#include \"string.h\"' ocp/src/placer/Ocp.cpp ocp/src/placer/PPlacement.h -sed -i '18i\#include \"bvl_bcomp_y.h\"' bvl/src/bvl_bcomp_y.y -# make sure the man pages are UTF-8... -for nonUTF8 in FAQ README LICENCE distrib/doc/alc_origin.1 alcban/man1/alcbanner.1 \ - loon/doc/loon.1 m2e/doc/man1/m2e.1 boog/doc/boog.1 ; do +## Convert to UTF-8 +for nonUTF8 in \ + FAQ \ + alcban/man1/alcbanner.1 \ + distrib/doc/alc_origin.1 \ + loon/doc/loon.1 \ + boog/doc/boog.1 \ + m2e/doc/man1/m2e.1 \ + documentation/overview/overview.tex \ + documentation/alliance-examples/tuner/build_tuner \ + documentation/alliance-examples/tuner/README \ + documentation/alliance-examples/tuner/tuner.vbe \ + documentation/alliance-examples/mipsR3000/sce/mips_dpt.c \ + documentation/alliance-examples/mipsR3000/asm/mips_defs.h \ +; do \ %{_bindir}/iconv -f ISO-8859-1 -t utf-8 $nonUTF8 > $nonUTF8.conv mv -f $nonUTF8.conv $nonUTF8 done pushd documentation/alliance-examples/ -# make sure the man pages are UTF-8... -for nonUTF8 in tuner/build_tuner mipsR3000/asm/mips_defs.h tuner/tuner.vbe \ - tuner/README mipsR3000/sce/mips_dpt.c ; do - %{_bindir}/iconv -f ISO-8859-1 -t utf-8 $nonUTF8 > $nonUTF8.conv - mv -f $nonUTF8.conv $nonUTF8 -done - #wrong-file-end-of-line-encoding sed -i 's/\r//' mipsR3000/asm/* popd find documentation/tutorials/ \ - -name *.vbe -o \ + \( -name *.vbe -o \ -name *.pat -o \ -name *.vhdl -o \ -name *.vst -o \ - -name *.c \ + -name *.c \) \ -exec chmod 0644 {} ';' +popd > /dev/null %build -export ALLIANCE_TOP=%{prefix} -%configure --enable-alc-shared \ - --disable-static \ - --includedir=%{prefix}/include \ - --libdir=%{prefix}/lib \ - --mandir=%{_datadir}/%{name}/man # RHBZ 252941 - -# disabling rpath -sed -i 's|^hardcode_libdir_flag_spec="\\${wl}--rpath \\${wl}\\$libdir"|hardcode_libdir_flag_spec=""|g' libtool -sed -i 's|^runpath_var=LD_RUN_PATH|runpath_var=DIE_RPATH_DIE|g' libtool - -# clean unused-direct-shlib-dependencies -sed -i -e 's! -shared ! -Wl,--as-needed\0!g' libtool +pushd src > /dev/null +%configure --enable-alc-shared \ + --disable-static \ + --prefix=%{_libdir}/%{name} \ + --bindir=%{_libdir}/%{name}/bin \ + --libdir=%{_libdir}/%{name}/lib \ + --includedir=%{_libdir}/%{name}/include \ + --docdir=%{_pkgdocdir} \ + --mandir=%{_mandir} # Is not parallel-build-safe make +popd %install +pushd src > /dev/null %make_install -# Set execution rights on the alc_env.* batchs and adjust ALLIANCE_TOP. -pushd %{buildroot}%{_sysconfdir}/profile.d - chmod 0644 alc_env.* - sed -i "s|@DATE@|`date`|" alc_env* - sed "s|ALLIANCE_TOP *= *\([^;]*\)|ALLIANCE_TOP=%{prefix}|" alc_env.sh - sed "s|setenv *ALLIANCE_TOP *\([^;]*\)|setenv ALLIANCE_TOP %{prefix}|" alc_env.csh -popd - - -# documentation -cp -pr %{buildroot}%{prefix}/doc/ . -cp -pr %{buildroot}%{prefix}/examples/alliance-examples/ . - -rm -rf %{buildroot}%{prefix}/doc/ -rm -rf %{buildroot}%{prefix}/examples/ - # Add automated scripts to examples -install -pm 755 %{SOURCE4} alliance-examples/go-all.sh -install -pm 755 %{SOURCE5} alliance-examples/go-all-clean.sh - -pushd alliance-examples/ - # FEL self test for alliance - #./go-all.sh 2>&1 | tee self-test-examples.log - # clean temporary files - ./go-all-clean.sh -popd +#install -pm 755 %{SOURCE4} alliance-examples/go-all.sh +#install -pm 755 %{SOURCE5} alliance-examples/go-all-clean.sh + +#pushd alliance-examples/ +# # FEL self test for alliance +# #./go-all.sh 2>&1 | tee self-test-examples.log +# # clean temporary files +# ./go-all-clean.sh +#popd find %{buildroot} -name '*.la' -delete -print @@ -216,83 +225,94 @@ for d in distrib/*.desktop; do desktop-file-install --dir %{buildroot}%{_datadir}/applications/ $d done -# Architecture independent files -mv %{buildroot}%{prefix}/cells %{buildroot}%{_datadir}/%{name}/ -mv %{buildroot}%{prefix}/etc %{buildroot}%{_datadir}/%{name}/ - # protecting hardcoded links -ln -sf ../../..%{_datadir}/%{name}/cells %{buildroot}%{prefix}/cells -ln -sf ../../..%{_datadir}/%{name}/etc %{buildroot}%{prefix}/etc -ln -sf ../../..%{_datadir}/%{name}/man %{buildroot}%{prefix}/man +#ln -sf ../../..%{_datadir}/%{name}/cells %{buildroot}%{_prefix}/cells +#ln -sf ../../..%{_datadir}/%{name}/etc %{buildroot}%{_prefix}/etc +#ln -sf ../../..%{_datadir}/%{name}/man %{buildroot}%{_prefix}/man + +# rename manpages to avoid conflicts +# RHBZ 252941 +pushd $RPM_BUILD_ROOT%{_mandir} > /dev/null +/usr/bin/rename .1 .1alc man1/* +/usr/bin/rename .3 .3alc man3/* +/usr/bin/rename .5 .5alc man5/* +# Reflect man page renamer to man page includes +sed -i -e 's,^\(.so man[13]/alc_.*.[13]\)$,\1alc,' man*/* +popd > /dev/null + +# Rename alliance subdir into html +mv %{buildroot}%{_pkgdocdir}/alliance %{buildroot}%{_pkgdocdir}/html +# Directly install files to go into 5%{_pkgdocdir} +install -m 644 README CHANGES FAQ alliance.fedora %{buildroot}%{_pkgdocdir} -# manpage-not-gzipped -find %{prefix}/man -type f -not -name '*.gz' -print | xargs gzip -9f %{__mkdir} -p %{buildroot}%{_sysconfdir}/ld.so.conf.d/ cat > %{buildroot}%{_sysconfdir}/ld.so.conf.d/%{name}.conf << EOF # Alliance VLSI design system -%{prefix}/lib +%{_libdir}/%{name}/lib EOF - -# removing tools for compiling and installing Alliance tools -# These are for the packager (i.e me) and not for user -rm -f %{buildroot}%{_sysconfdir}/%{name}/attila.conf -rm -f %{buildroot}%{prefix}/etc/attila.conf -rm -f %{buildroot}%{prefix}/bin/attila -rm -f %{buildroot}%{_datadir}/man/man1/attila* -rm -f doc/html/alliance/*attila.html -rm -f doc/pdf/attila.pdf - -# correcting minor documentation details -sed -i "s|/bin/zsh|/bin/sh|" doc/alliance-run/bench.zsh - %{_fixperms} %{buildroot}/* +popd > /dev/null -%post +%post libs /sbin/ldconfig + +%post source %{_sysconfdir}/profile.d/alc_env.sh touch --no-create %{_datadir}/icons/hicolor || : %{_bindir}/gtk-update-icon-cache --quiet %{_datadir}/icons/hicolor || : +%postun libs +/sbin/ldconfig + %postun /sbin/ldconfig touch --no-create %{_datadir}/icons/hicolor || : %{_bindir}/gtk-update-icon-cache --quiet %{_datadir}/icons/hicolor || : -#These headers are useful for the _usage_ of the binaries -#without these headers some of the binaries will be broken by default - %files -%license LICENCE COPYING* -%doc CHANGES FAQ alliance.fedora -#%{prefix}/ -%{_datadir}/%{name}/ +%{_pkgdocdir}/README +%{_pkgdocdir}/CHANGES +%{_pkgdocdir}/FAQ +%{_pkgdocdir}/alliance.fedora +%license src/LICENCE src/COPYING* + +%{_datadir}/alliance %{_datadir}/icons/hicolor/48x48/apps/* +%{_datadir}/applications/*.desktop +%dir %{_libdir}/alliance +%{_libdir}/alliance/bin +%{_mandir}/man1/*.1* +%config(noreplace) %{_sysconfdir}/alliance +%config(noreplace) %{_sysconfdir}/profile.d/alc_env.* + +%files devel +%dir %{_libdir}/alliance +%{_libdir}/alliance/include +%dir %{_libdir}/alliance/lib +%{_libdir}/alliance/lib/*.so +%{_mandir}/man3/*.3* %files libs +%dir %{_libdir}/alliance +%dir %{_libdir}/alliance/lib +%{_libdir}/alliance/lib/lib*.so.* +%{_mandir}/man5/*.5* %config(noreplace) %{_sysconfdir}/ld.so.conf.d/* -%{_datadir}/applications/*.desktop -%config(noreplace) %{_sysconfdir}/profile.d/alc_env.* %files doc -%license LICENCE COPYING* -%doc doc/html/ -%doc doc/design-flow -%doc doc/pdf/*.pdf -%doc doc/overview/*.ps -%doc doc/overview/*.pdf -%doc documentation/tutorials/ -#Makefiles are present in alliance-examples/*. It is normal because -# * it gives the VLSI designer a template on how to create his own -# Makefile for alliance (VLSI designers normally don't know how to do so) -# * it is not part of the build, but part of the working environment of the user -%doc alliance-examples/ -%doc doc/alliance-run/ +%{_pkgdocdir} %changelog +* Tue Mar 01 2016 Ralf Corsépius - 5.1.1-4.20160220git10a7b7e +- Rework spec. +- Add upstream changes. +- Rework package configuration. +- Introduce *-devel. + * Wed Feb 03 2016 Fedora Release Engineering - 5.1.1-3 - Rebuilt for https://fedoraproject.org/wiki/Fedora_24_Mass_Rebuild