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Commit: fcc0aa98874b439661e674831393e9aaff321b1a
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diff -rcp ../binutils-2.23.51.0.3.orig/gas/ChangeLog ./gas/ChangeLog
*** ../binutils-2.23.51.0.3.orig/gas/ChangeLog	2012-10-23 10:15:13.038870720 +0100
--- ./gas/ChangeLog	2012-10-23 10:17:56.688907041 +0100
***************
*** 1,3 ****
--- 1,8 ----
+ 2012-09-18  Kyrylo Tkachov  <kyrylo.tkachov@arm.com>
+ 
+ 	* config/tc-arm.c: Changed ldra and strl-form mnemonics
+ 	to lda and stl-form for armv8.
+ 
  2012-09-17  Yufeng Zhang  <yufeng.zhang@arm.com>
  
  	* config/tc-aarch64.c (aarch64_archs): Rename 'armv8' to 'armv8-a'.
diff -rcp ../binutils-2.23.51.0.3.orig/gas/config/tc-arm.c ./gas/config/tc-arm.c
*** ../binutils-2.23.51.0.3.orig/gas/config/tc-arm.c	2012-10-23 10:15:13.379871049 +0100
--- ./gas/config/tc-arm.c	2012-10-23 10:16:50.892897421 +0100
*************** do_strexd (void)
*** 8738,8744 ****
  
  /* ARM V8 STRL.  */
  static void
! do_strlex (void)
  {
    constraint (inst.operands[0].reg == inst.operands[1].reg
  	      || inst.operands[0].reg == inst.operands[2].reg, BAD_OVERLAP);
--- 8738,8744 ----
  
  /* ARM V8 STRL.  */
  static void
! do_stlex (void)
  {
    constraint (inst.operands[0].reg == inst.operands[1].reg
  	      || inst.operands[0].reg == inst.operands[2].reg, BAD_OVERLAP);
*************** do_strlex (void)
*** 8747,8753 ****
  }
  
  static void
! do_t_strlex (void)
  {
    constraint (inst.operands[0].reg == inst.operands[1].reg
  	      || inst.operands[0].reg == inst.operands[2].reg, BAD_OVERLAP);
--- 8747,8753 ----
  }
  
  static void
! do_t_stlex (void)
  {
    constraint (inst.operands[0].reg == inst.operands[1].reg
  	      || inst.operands[0].reg == inst.operands[2].reg, BAD_OVERLAP);
*************** static const struct asm_opcode insns[] =
*** 18476,18500 ****
  
   tCE("sevl",	320f005, _sevl,    0, (),		noargs,	t_hint),
   TUE("hlt",	1000070, ba80,     1, (oIffffb),	bkpt,	t_hlt),
!  TCE("ldraex",	1900e9f, e8d00fef, 2, (RRnpc, RRnpcb),	rd_rn,	rd_rn),
!  TCE("ldraexd",	1b00e9f, e8d000ff, 3, (RRnpc, oRRnpc, RRnpcb),
  							ldrexd, t_ldrexd),
!  TCE("ldraexb",	1d00e9f, e8d00fcf, 2, (RRnpc,RRnpcb),	rd_rn,  rd_rn),
!  TCE("ldraexh",	1f00e9f, e8d00fdf, 2, (RRnpc, RRnpcb),	rd_rn,  rd_rn),
!  TCE("strlex",	1800e90, e8c00fe0, 3, (RRnpc, RRnpc, RRnpcb),
! 							strlex,  t_strlex),
!  TCE("strlexd",	1a00e90, e8c000f0, 4, (RRnpc, RRnpc, oRRnpc, RRnpcb),
  							strexd, t_strexd),
!  TCE("strlexb",	1c00e90, e8c00fc0, 3, (RRnpc, RRnpc, RRnpcb),
! 							strlex, t_strlex),
!  TCE("strlexh",	1e00e90, e8c00fd0, 3, (RRnpc, RRnpc, RRnpcb),
! 							strlex, t_strlex),
!  TCE("ldra",	1900c9f, e8d00faf, 2, (RRnpc, RRnpcb),	rd_rn,	rd_rn),
!  TCE("ldrab",	1d00c9f, e8d00f8f, 2, (RRnpc, RRnpcb),	rd_rn,  rd_rn),
!  TCE("ldrah",	1f00c9f, e8d00f9f, 2, (RRnpc, RRnpcb),	rd_rn,  rd_rn),
!  TCE("strl",	180fc90, e8c00faf, 2, (RRnpc, RRnpcb),	rm_rn,  rd_rn),
!  TCE("strlb",	1c0fc90, e8c00f8f, 2, (RRnpc, RRnpcb),	rm_rn,  rd_rn),
!  TCE("strlh",	1e0fc90, e8c00f9f, 2, (RRnpc, RRnpcb),	rm_rn,  rd_rn),
  
   /* ARMv8 T32 only.  */
  #undef ARM_VARIANT
--- 18476,18500 ----
  
   tCE("sevl",	320f005, _sevl,    0, (),		noargs,	t_hint),
   TUE("hlt",	1000070, ba80,     1, (oIffffb),	bkpt,	t_hlt),
!  TCE("ldaex",	1900e9f, e8d00fef, 2, (RRnpc, RRnpcb),	rd_rn,	rd_rn),
!  TCE("ldaexd",	1b00e9f, e8d000ff, 3, (RRnpc, oRRnpc, RRnpcb),
  							ldrexd, t_ldrexd),
!  TCE("ldaexb",	1d00e9f, e8d00fcf, 2, (RRnpc,RRnpcb),	rd_rn,  rd_rn),
!  TCE("ldaexh",	1f00e9f, e8d00fdf, 2, (RRnpc, RRnpcb),	rd_rn,  rd_rn),
!  TCE("stlex",	1800e90, e8c00fe0, 3, (RRnpc, RRnpc, RRnpcb),
! 							stlex,  t_stlex),
!  TCE("stlexd",	1a00e90, e8c000f0, 4, (RRnpc, RRnpc, oRRnpc, RRnpcb),
  							strexd, t_strexd),
!  TCE("stlexb",	1c00e90, e8c00fc0, 3, (RRnpc, RRnpc, RRnpcb),
! 							stlex, t_stlex),
!  TCE("stlexh",	1e00e90, e8c00fd0, 3, (RRnpc, RRnpc, RRnpcb),
! 							stlex, t_stlex),
!  TCE("lda",	1900c9f, e8d00faf, 2, (RRnpc, RRnpcb),	rd_rn,	rd_rn),
!  TCE("ldab",	1d00c9f, e8d00f8f, 2, (RRnpc, RRnpcb),	rd_rn,  rd_rn),
!  TCE("ldah",	1f00c9f, e8d00f9f, 2, (RRnpc, RRnpcb),	rd_rn,  rd_rn),
!  TCE("stl",	180fc90, e8c00faf, 2, (RRnpc, RRnpcb),	rm_rn,  rd_rn),
!  TCE("stlb",	1c0fc90, e8c00f8f, 2, (RRnpc, RRnpcb),	rm_rn,  rd_rn),
!  TCE("stlh",	1e0fc90, e8c00f9f, 2, (RRnpc, RRnpcb),	rm_rn,  rd_rn),
  
   /* ARMv8 T32 only.  */
  #undef ARM_VARIANT
diff -rcp ../binutils-2.23.51.0.3.orig/opcodes/arm-dis.c ./opcodes/arm-dis.c
*** ../binutils-2.23.51.0.3.orig/opcodes/arm-dis.c	2012-10-23 10:15:16.976873621 +0100
--- ./opcodes/arm-dis.c	2012-10-23 10:16:34.204894516 +0100
*************** static const struct opcode32 arm_opcodes
*** 889,908 ****
    /* V8 instructions.  */
    {ARM_EXT_V8,   0x0320f005, 0x0fffffff, "sevl"},
    {ARM_EXT_V8,   0xe1000070, 0xfff000f0, "hlt\t0x%16-19X%12-15X%8-11X%0-3X"},
!   {ARM_EXT_V8,	 0x01800e90, 0x0ff00ff0, "strlex%c\t%12-15r, %0-3r, [%16-19R]"},
!   {ARM_EXT_V8,	 0x01900e9f, 0x0ff00fff, "ldraex%c\t%12-15r, [%16-19R]"},
!   {ARM_EXT_V8,	 0x01a00e90, 0x0ff00ff0, "strlexd%c\t%12-15r, %0-3r, %0-3T, [%16-19R]"},
!   {ARM_EXT_V8,	 0x01b00e9f, 0x0ff00fff, "ldraexd%c\t%12-15r, %12-15T, [%16-19R]"},
!   {ARM_EXT_V8,	 0x01c00e90, 0x0ff00ff0, "strlexb%c\t%12-15r, %0-3r, [%16-19R]"},
!   {ARM_EXT_V8,	 0x01d00e9f, 0x0ff00fff, "ldraexb%c\t%12-15r, [%16-19R]"},
!   {ARM_EXT_V8,	 0x01e00e90, 0x0ff00ff0, "strlexh%c\t%12-15r, %0-3r, [%16-19R]"},
!   {ARM_EXT_V8,	 0x01f00e9f, 0x0ff00fff, "ldraexh%c\t%12-15r, [%16-19R]"},
!   {ARM_EXT_V8,	 0x0180fc90, 0x0ff0fff0, "strl%c\t%0-3r, [%16-19R]"},
!   {ARM_EXT_V8,	 0x01900c9f, 0x0ff00fff, "ldra%c\t%12-15r, [%16-19R]"},
!   {ARM_EXT_V8,	 0x01c0fc90, 0x0ff0fff0, "strlb%c\t%0-3r, [%16-19R]"},
!   {ARM_EXT_V8,	 0x01d00c9f, 0x0ff00fff, "ldrab%c\t%12-15r, [%16-19R]"},
!   {ARM_EXT_V8,	 0x01e0fc90, 0x0ff0fff0, "strlh%c\t%0-3r, [%16-19R]"},
!   {ARM_EXT_V8,	 0x01f00c9f, 0x0ff00fff, "ldraexh%c\t%12-15r, [%16-19R]"},
  
    /* Virtualization Extension instructions.  */
    {ARM_EXT_VIRT, 0x0160006e, 0x0fffffff, "eret%c"},
--- 889,908 ----
    /* V8 instructions.  */
    {ARM_EXT_V8,   0x0320f005, 0x0fffffff, "sevl"},
    {ARM_EXT_V8,   0xe1000070, 0xfff000f0, "hlt\t0x%16-19X%12-15X%8-11X%0-3X"},
!   {ARM_EXT_V8,	 0x01800e90, 0x0ff00ff0, "stlex%c\t%12-15r, %0-3r, [%16-19R]"},
!   {ARM_EXT_V8,	 0x01900e9f, 0x0ff00fff, "ldaex%c\t%12-15r, [%16-19R]"},
!   {ARM_EXT_V8,	 0x01a00e90, 0x0ff00ff0, "stlexd%c\t%12-15r, %0-3r, %0-3T, [%16-19R]"},
!   {ARM_EXT_V8,	 0x01b00e9f, 0x0ff00fff, "ldaexd%c\t%12-15r, %12-15T, [%16-19R]"},
!   {ARM_EXT_V8,	 0x01c00e90, 0x0ff00ff0, "stlexb%c\t%12-15r, %0-3r, [%16-19R]"},
!   {ARM_EXT_V8,	 0x01d00e9f, 0x0ff00fff, "ldaexb%c\t%12-15r, [%16-19R]"},
!   {ARM_EXT_V8,	 0x01e00e90, 0x0ff00ff0, "stlexh%c\t%12-15r, %0-3r, [%16-19R]"},
!   {ARM_EXT_V8,	 0x01f00e9f, 0x0ff00fff, "ldaexh%c\t%12-15r, [%16-19R]"},
!   {ARM_EXT_V8,	 0x0180fc90, 0x0ff0fff0, "stl%c\t%0-3r, [%16-19R]"},
!   {ARM_EXT_V8,	 0x01900c9f, 0x0ff00fff, "lda%c\t%12-15r, [%16-19R]"},
!   {ARM_EXT_V8,	 0x01c0fc90, 0x0ff0fff0, "stlb%c\t%0-3r, [%16-19R]"},
!   {ARM_EXT_V8,	 0x01d00c9f, 0x0ff00fff, "ldab%c\t%12-15r, [%16-19R]"},
!   {ARM_EXT_V8,	 0x01e0fc90, 0x0ff0fff0, "stlh%c\t%0-3r, [%16-19R]"},
!   {ARM_EXT_V8,	 0x01f00c9f, 0x0ff00fff, "ldaexh%c\t%12-15r, [%16-19R]"},
  
    /* Virtualization Extension instructions.  */
    {ARM_EXT_VIRT, 0x0160006e, 0x0fffffff, "eret%c"},
*************** static const struct opcode32 thumb32_opc
*** 1475,1494 ****
    /* V8 instructions.  */
    {ARM_EXT_V8, 0xf3af8005, 0xffffffff, "sevl%c.w"},
    {ARM_EXT_V8, 0xf78f8000, 0xfffffffc, "dcps%0-1d"},
!   {ARM_EXT_V8, 0xe8c00f8f, 0xfff00fff, "strlb%c\t%12-15r, [%16-19R]"},
!   {ARM_EXT_V8, 0xe8c00f9f, 0xfff00fff, "strlh%c\t%12-15r, [%16-19R]"},
!   {ARM_EXT_V8, 0xe8c00faf, 0xfff00fff, "strl%c\t%12-15r, [%16-19R]"},
!   {ARM_EXT_V8, 0xe8c00fc0, 0xfff00ff0, "strlexb%c\t%0-3r, %12-15r, [%16-19R]"},
!   {ARM_EXT_V8, 0xe8c00fd0, 0xfff00ff0, "strlexh%c\t%0-3r, %12-15r, [%16-19R]"},
!   {ARM_EXT_V8, 0xe8c00fe0, 0xfff00ff0, "strlex%c\t%0-3r, %12-15r, [%16-19R]"},
!   {ARM_EXT_V8, 0xe8c000f0, 0xfff000f0, "strlexd%c\t%0-3r, %12-15r, %8-11r, [%16-19R]"},
!   {ARM_EXT_V8, 0xe8d00f8f, 0xfff00fff, "ldrab%c\t%12-15r, [%16-19R]"},
!   {ARM_EXT_V8, 0xe8d00f9f, 0xfff00fff, "ldrah%c\t%12-15r, [%16-19R]"},
!   {ARM_EXT_V8, 0xe8d00faf, 0xfff00fff, "ldra%c\t%12-15r, [%16-19R]"},
!   {ARM_EXT_V8, 0xe8d00fcf, 0xfff00fff, "ldraexb%c\t%12-15r, [%16-19R]"},
!   {ARM_EXT_V8, 0xe8d00fdf, 0xfff00fff, "ldraexh%c\t%12-15r, [%16-19R]"},
!   {ARM_EXT_V8, 0xe8d00fef, 0xfff00fff, "ldraex%c\t%12-15r, [%16-19R]"},
!   {ARM_EXT_V8, 0xe8d000ff, 0xfff000ff, "ldraexd%c\t%12-15r, %8-11r, [%16-19R]"},
  
    /* V7 instructions.  */
    {ARM_EXT_V7, 0xf910f000, 0xff70f000, "pli%c\t%a"},
--- 1475,1494 ----
    /* V8 instructions.  */
    {ARM_EXT_V8, 0xf3af8005, 0xffffffff, "sevl%c.w"},
    {ARM_EXT_V8, 0xf78f8000, 0xfffffffc, "dcps%0-1d"},
!   {ARM_EXT_V8, 0xe8c00f8f, 0xfff00fff, "stlb%c\t%12-15r, [%16-19R]"},
!   {ARM_EXT_V8, 0xe8c00f9f, 0xfff00fff, "stlh%c\t%12-15r, [%16-19R]"},
!   {ARM_EXT_V8, 0xe8c00faf, 0xfff00fff, "stl%c\t%12-15r, [%16-19R]"},
!   {ARM_EXT_V8, 0xe8c00fc0, 0xfff00ff0, "stlexb%c\t%0-3r, %12-15r, [%16-19R]"},
!   {ARM_EXT_V8, 0xe8c00fd0, 0xfff00ff0, "stlexh%c\t%0-3r, %12-15r, [%16-19R]"},
!   {ARM_EXT_V8, 0xe8c00fe0, 0xfff00ff0, "stlex%c\t%0-3r, %12-15r, [%16-19R]"},
!   {ARM_EXT_V8, 0xe8c000f0, 0xfff000f0, "stlexd%c\t%0-3r, %12-15r, %8-11r, [%16-19R]"},
!   {ARM_EXT_V8, 0xe8d00f8f, 0xfff00fff, "ldab%c\t%12-15r, [%16-19R]"},
!   {ARM_EXT_V8, 0xe8d00f9f, 0xfff00fff, "ldah%c\t%12-15r, [%16-19R]"},
!   {ARM_EXT_V8, 0xe8d00faf, 0xfff00fff, "lda%c\t%12-15r, [%16-19R]"},
!   {ARM_EXT_V8, 0xe8d00fcf, 0xfff00fff, "ldaexb%c\t%12-15r, [%16-19R]"},
!   {ARM_EXT_V8, 0xe8d00fdf, 0xfff00fff, "ldaexh%c\t%12-15r, [%16-19R]"},
!   {ARM_EXT_V8, 0xe8d00fef, 0xfff00fff, "ldaex%c\t%12-15r, [%16-19R]"},
!   {ARM_EXT_V8, 0xe8d000ff, 0xfff000ff, "ldaexd%c\t%12-15r, %8-11r, [%16-19R]"},
  
    /* V7 instructions.  */
    {ARM_EXT_V7, 0xf910f000, 0xff70f000, "pli%c\t%a"},
diff -rcp ../binutils-2.23.51.0.3.orig/opcodes/ChangeLog ./opcodes/ChangeLog
*** ../binutils-2.23.51.0.3.orig/opcodes/ChangeLog	2012-10-23 10:15:17.783874153 +0100
--- ./opcodes/ChangeLog	2012-10-23 10:18:43.593915807 +0100
***************
*** 1,3 ****
--- 1,8 ----
+ 2012-09-18  Kyrylo Tkachov  <kyrylo.tkachov@arm.com>
+ 
+ 	* arm-dis.c: Changed ldra and strl-form mnemonics
+ 	to lda and stl-form.
+ 
  2012-09-17  Yufeng Zhang  <yufeng.zhang@arm.com>
  
  	* aarch64-asm.c (aarch64_ins_imm_half): Remove ATTRIBUTE_UNUSED from
rpms / binutils

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