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#1 Add support RISC-V (riscv64)
Opened 2 years ago by milkice. Modified 2 years ago
https://github.com/milkice-fedora-patches/cln.git main  into  rawhide

Merge
Add support RISC-V (riscv64)
Milkice Qiu • 2 years ago  
c81370c
cln-1.3.4-riscv.patch
file added
+57 
@@ -0,0 +1,57 @@
 

+ diff --git a/include/cln/object.h b/include/cln/object.h
 

+ index 56f6f07..e26e079 100644
 

+ --- a/include/cln/object.h
 

+ +++ b/include/cln/object.h
 

+ @@ -22,10 +22,10 @@ namespace cln {
 

+  #if defined(__m68k__)
 

+    #define cl_word_alignment  2
 

+  #endif
 

+ -#if defined(__i386__) || (defined(__mips__) && !defined(__LP64__)) || (defined(__sparc__) && !defined(__arch64__)) || defined(__hppa__) || defined(__arm__) || defined(__rs6000__) || defined(__m88k__) || defined(__convex__) || (defined(__s390__) && !defined(__s390x__)) || defined(__sh__) || (defined(__x86_64__) && defined(__ILP32__))
 

+ +#if defined(__i386__) || (defined(__mips__) && !defined(__LP64__)) || (defined(__sparc__) && !defined(__arch64__)) || defined(__hppa__) || defined(__arm__) || defined(__rs6000__) || defined(__m88k__) || defined(__convex__) || (defined(__s390__) && !defined(__s390x__)) || defined(__sh__) || (defined(__x86_64__) && defined(__ILP32__)) || (defined(__riscv) && __riscv_xlen == 32)
 

+    #define cl_word_alignment  4
 

+  #endif
 

+ -#if defined(__alpha__) || defined(__ia64__) || defined(__mips64__) || defined(__powerpc64__) || (defined(__sparc__) && defined(__arch64__)) || (defined(__x86_64__) && !defined(__ILP32__)) || defined(__s390x__) || defined(__aarch64__)
 

+ +#if defined(__alpha__) || defined(__ia64__) || defined(__mips64__) || defined(__powerpc64__) || (defined(__sparc__) && defined(__arch64__)) || (defined(__x86_64__) && !defined(__ILP32__)) || defined(__s390x__) || defined(__aarch64__) || (defined(__riscv) && __riscv_xlen == 64)
 

+    #define cl_word_alignment  8
 

+  #endif
 

+  #if !defined(cl_word_alignment)
 

+ diff --git a/include/cln/types.h b/include/cln/types.h
 

+ index 159e8bc..1cccecb 100644
 

+ --- a/include/cln/types.h
 

+ +++ b/include/cln/types.h
 

+ @@ -48,7 +48,7 @@
 

+      #undef HAVE_LONGLONG
 

+     #endif
 

+    #endif
 

+ -  #if defined(HAVE_LONGLONG) && (defined(__alpha__) || defined(__ia64__) || defined(__mips64__) || defined(__powerpc64__) || defined(__s390x__) || (defined(__sparc__) && defined(__arch64__)) || defined(__x86_64__) || defined(__aarch64__))
 

+ +  #if defined(HAVE_LONGLONG) && (defined(__alpha__) || defined(__ia64__) || defined(__mips64__) || defined(__powerpc64__) || defined(__s390x__) || (defined(__sparc__) && defined(__arch64__)) || defined(__x86_64__) || defined(__aarch64__)) || (defined(__riscv) && __riscv_xlen == 64)
 

+      // 64 bit registers in hardware
 

+      #define HAVE_FAST_LONGLONG
 

+    #endif
 

+ @@ -76,7 +76,7 @@
 

+  

+  // Integer type used for counters.
 

+  // Constraint: sizeof(uintC) >= sizeof(uintL)
 

+ -  #if (defined(HAVE_FAST_LONGLONG) && (defined(__alpha__) || defined(__ia64__) || defined(__powerpc64__) || defined(__s390x__) || (defined(__sparc__) && defined(__arch64__)) || defined(__x86_64__) || defined(__aarch64__) || defined(__mips64__)))
 

+ +  #if (defined(HAVE_FAST_LONGLONG) && (defined(__alpha__) || defined(__ia64__) || defined(__powerpc64__) || defined(__s390x__) || (defined(__sparc__) && defined(__arch64__)) || defined(__x86_64__) || defined(__aarch64__) || defined(__mips64__) || (defined(__riscv) && __riscv_xlen == 64)))
 

+      #define intCsize long_bitsize
 

+      typedef long           sintC;
 

+      typedef unsigned long  uintC;
 

+ @@ -88,7 +88,7 @@
 

+  

+  // Integer type used for lfloat exponents.
 

+  // Constraint: sizeof(uintE) >= sizeof(uintC)
 

+ -  #if (defined(HAVE_LONGLONG) && (defined(__alpha__) || defined(__ia64__) || defined(__powerpc64__) || defined(__s390x__) || (defined(__sparc__) && defined(__arch64__)) || defined(__x86_64__) || defined(__i386__) || defined(__mips__) || defined(__rs6000__) || defined(__aarch64__)))
 

+ +  #if (defined(HAVE_LONGLONG) && (defined(__alpha__) || defined(__ia64__) || defined(__powerpc64__) || defined(__s390x__) || (defined(__sparc__) && defined(__arch64__)) || defined(__x86_64__) || defined(__i386__) || defined(__mips__) || defined(__rs6000__) || defined(__aarch64__) || (defined(__riscv) && __riscv_xlen == 64)))
 

+      #define intEsize 64
 

+      typedef sint64  sintE;
 

+      typedef uint64  uintE;
 

+ @@ -127,7 +127,7 @@
 

+      typedef int sintD;
 

+      typedef unsigned int uintD;
 

+    #else  // we are not using GMP, so just guess something reasonable
 

+ -    #if (defined(HAVE_FAST_LONGLONG) && (defined(__alpha__) || defined(__ia64__) || defined(__powerpc64__) || (defined(__sparc__) && defined(__arch64__)) || defined(__s390x__) || defined(__x86_64__) || defined(__aarch64__) || defined(__mips64__)))
 

+ +    #if (defined(HAVE_FAST_LONGLONG) && (defined(__alpha__) || defined(__ia64__) || defined(__powerpc64__) || (defined(__sparc__) && defined(__arch64__)) || defined(__s390x__) || defined(__x86_64__) || defined(__aarch64__) || defined(__mips64__) || (defined(__riscv) && __riscv_xlen == 64)))
 

+        #define intDsize 64
 

+        typedef sint64  sintD;
 

+        typedef uint64  uintD;

cln.spec
file modified
+8 -1 
@@ -1,10 +1,12 @@
 

  Name:           cln
 

  Version:        1.3.4
 

- Release:        17%{?dist}
 

+ Release:        18%{?dist}
 

  Summary:        Class Library for Numbers
 

  License:        GPLv2+
 

  URL:            http://www.ginac.de/CLN/
 

  Source0:        http://www.ginac.de/CLN/%{name}-%{version}.tar.bz2
 

+ # Adds definitions for RISC-V (riscv64)
 

+ Patch0:         cln-1.3.4-riscv.patch
 

  BuildRequires:  gcc-c++
 

  BuildRequires:  gmp-devel
 

  BuildRequires:  texi2html
 
@@ -40,6 +42,7 @@
 

  

  %prep
 

  %setup -q
 

+ %patch0 -p1 -b .riscv~
 

  

  %build
 

  %configure --disable-static CXXFLAGS="%{XFLAGS}" CFLAGS="%{XFLAGS}"
 
@@ -71,6 +74,10 @@
 

  %doc doc/cln.pdf doc/cln.html
 

  

  %changelog
 

+ * Sat Apr 16 2022 Milkice Qiu <milkice@milkice.me> - 1.3.4-18
 

+ - Add support for RISC-V (riscv64)
 

+ - Patch from David Abdurachmanov <david.abdurachmanov@gmail.com>
 

+ 

  * Wed Jan 19 2022 Fedora Release Engineering <releng@fedoraproject.org> - 1.3.4-17
 

  - Rebuilt for https://fedoraproject.org/wiki/Fedora_36_Mass_Rebuild

no initial comment

Merge from http://fedora.riscv.rocks:3000/rpms/cln
This patch is for cln 1.3.4, and RISC-V seems to be officially supported in cln 1.3.6

Signed-off-by: David Abdurachmanov david.abdurachmanov@gmail.com
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+57
file added
cln-1.3.4-riscv.patch
+8 -1
file changed
cln.spec
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