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From 528a5cd576861f90f51398c707c602a79623492d Mon Sep 17 00:00:00 2001
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From: Hans de Goede <hdegoede@redhat.com>
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Date: Thu, 5 Sep 2013 19:52:41 -0300
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Subject: [PATCH] ARM: sunxi: Add driver for SD/MMC hosts found on Allwinner
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 sunxi SoCs
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MIME-Version: 1.0
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Content-Type: text/plain; charset=UTF-8
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Content-Transfer-Encoding: 8bit
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The Allwinner sunxi mmc host uses dma in bus-master mode using a built-in
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designware idmac controller, which is identical to the one found in the mmc-dw
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hosts. However the rest of the host is not identical to mmc-dw, it deals with
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sending stop commands in hardware which makes it significantly different
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from the mmc-dw devices.
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Signed-off-by: David Lanzend├Ârfer <david.lanzendoerfer@o2s.ch>
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Signed-off-by: Emilio L├│pez <emilio@elopez.com.ar>
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Signed-off-by: Hans de Goede <hdegoede@redhat.com>
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---
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 .../devicetree/bindings/mmc/sunxi-mmc.txt          |   43 +
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 arch/arm/boot/dts/Makefile                         |    1 +
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 arch/arm/boot/dts/sun4i-a10-a1000.dts              |    9 +
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 arch/arm/boot/dts/sun4i-a10-cubieboard.dts         |    9 +
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 arch/arm/boot/dts/sun4i-a10-hackberry.dts          |    9 +
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 arch/arm/boot/dts/sun4i-a10-inet97fv2.dts          |    9 +
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 arch/arm/boot/dts/sun4i-a10-mini-xplus.dts         |    9 +
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 arch/arm/boot/dts/sun4i-a10-olinuxino-lime.dts     |    9 +
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 arch/arm/boot/dts/sun4i-a10-pcduino.dts            |    9 +
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 arch/arm/boot/dts/sun4i-a10.dtsi                   |   50 +
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 arch/arm/boot/dts/sun5i-a10s-olinuxino-micro.dts   |   32 +
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 arch/arm/boot/dts/sun5i-a10s.dtsi                  |   41 +
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 arch/arm/boot/dts/sun5i-a13-olinuxino-micro.dts    |   16 +
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 arch/arm/boot/dts/sun5i-a13-olinuxino.dts          |   16 +
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 arch/arm/boot/dts/sun5i-a13.dtsi                   |   25 +
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 arch/arm/boot/dts/sun6i-a31-m9.dts                 |   46 +
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 arch/arm/boot/dts/sun6i-a31.dtsi                   |   91 ++
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 arch/arm/boot/dts/sun7i-a20-cubieboard2.dts        |    9 +
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 arch/arm/boot/dts/sun7i-a20-cubietruck.dts         |   40 +
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 arch/arm/boot/dts/sun7i-a20-olinuxino-micro.dts    |   25 +
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 arch/arm/boot/dts/sun7i-a20.dtsi                   |   57 +
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 drivers/clk/sunxi/clk-factors.c                    |   36 +
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 drivers/clk/sunxi/clk-sunxi.c                      |   36 +
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 drivers/mmc/host/Kconfig                           |    7 +
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 drivers/mmc/host/Makefile                          |    2 +
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 drivers/mmc/host/sunxi-mmc.c                       | 1125 ++++++++++++++++++++
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 include/linux/clk/sunxi.h                          |   22 +
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 27 files changed, 1783 insertions(+)
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 create mode 100644 Documentation/devicetree/bindings/mmc/sunxi-mmc.txt
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 create mode 100644 arch/arm/boot/dts/sun6i-a31-m9.dts
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 create mode 100644 drivers/mmc/host/sunxi-mmc.c
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 create mode 100644 include/linux/clk/sunxi.h
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diff --git a/Documentation/devicetree/bindings/mmc/sunxi-mmc.txt b/Documentation/devicetree/bindings/mmc/sunxi-mmc.txt
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new file mode 100644
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index 0000000..f0c06e7
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--- /dev/null
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+++ b/Documentation/devicetree/bindings/mmc/sunxi-mmc.txt
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@@ -0,0 +1,43 @@
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+* Allwinner sunxi MMC controller
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+
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+The highspeed MMC host controller on Allwinner SoCs provides an interface
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+for MMC, SD and SDIO types of memory cards.
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+
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+Supported maximum speeds are the ones of the eMMC standard 4.5 as well
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+as the speed of SD standard 3.0.
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+Absolute maximum transfer rate is 200MB/s
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+
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+Required properties:
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+ - compatible : "allwinner,sun4i-a10-mmc" or "allwinner,sun5i-a13-mmc"
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+ - reg : mmc controller base registers
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+ - clocks : a list with 2 phandle + clock specifier pairs
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+ - clock-names : must contain "ahb" and "mod"
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+ - interrupts : mmc controller interrupt
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+
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+Optional properties:
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+ - resets : phandle + reset specifier pair
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+ - reset-names : must contain "ahb"
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+ - for cd, bus-width and additional generic mmc parameters
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+   please refer to mmc.txt within this directory
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+
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+Examples:
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+	- Within .dtsi:
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+	mmc0: mmc@01c0f000 {
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+		compatible = "allwinner,sun5i-a13-mmc";
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+		reg = <0x01c0f000 0x1000>;
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+		clocks = <&ahb_gates 8>, <&mmc0_clk>;
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+		clock-names = "ahb", "mod";
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+		interrupts = <0 32 4>;
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+		status = "disabled";
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+	};
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+
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+	- Within dts:
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+	mmc0: mmc@01c0f000 {
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+		pinctrl-names = "default", "default";
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+		pinctrl-0 = <&mmc0_pins_a>;
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+		pinctrl-1 = <&mmc0_cd_pin_reference_design>;
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+		bus-width = <4>;
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+		cd-gpios = <&pio 7 1 0>; /* PH1 */
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+		cd-inverted;
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+		status = "okay";
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+	};
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diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
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index 35c146f..1cd137d 100644
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--- a/arch/arm/boot/dts/Makefile
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+++ b/arch/arm/boot/dts/Makefile
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@@ -351,6 +351,7 @@ dtb-$(CONFIG_ARCH_SUNXI) += \
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 	sun5i-a13-olinuxino.dtb \
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 	sun5i-a13-olinuxino-micro.dtb \
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 	sun6i-a31-colombus.dtb \
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+	sun6i-a31-m9.dtb \
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 	sun7i-a20-cubieboard2.dtb \
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 	sun7i-a20-cubietruck.dtb \
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 	sun7i-a20-olinuxino-micro.dtb
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diff --git a/arch/arm/boot/dts/sun4i-a10-a1000.dts b/arch/arm/boot/dts/sun4i-a10-a1000.dts
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index fa746aea..3056db5 100644
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--- a/arch/arm/boot/dts/sun4i-a10-a1000.dts
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+++ b/arch/arm/boot/dts/sun4i-a10-a1000.dts
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@@ -36,6 +36,15 @@
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 			};
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 		};
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+		mmc0: mmc@01c0f000 {
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+			pinctrl-names = "default";
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+			pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_a>;
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+			bus-width = <4>;
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+			cd-gpios = <&pio 7 1 0>; /* PH1 */
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+			cd-inverted;
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+			status = "okay";
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+		};
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+
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 		usbphy: phy@01c13400 {
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 			usb1_vbus-supply = <&reg_usb1_vbus>;
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 			usb2_vbus-supply = <&reg_usb2_vbus>;
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diff --git a/arch/arm/boot/dts/sun4i-a10-cubieboard.dts b/arch/arm/boot/dts/sun4i-a10-cubieboard.dts
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index 4684cbe..ad9321b 100644
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--- a/arch/arm/boot/dts/sun4i-a10-cubieboard.dts
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+++ b/arch/arm/boot/dts/sun4i-a10-cubieboard.dts
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@@ -34,6 +34,15 @@
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 			};
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 		};
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+		mmc0: mmc@01c0f000 {
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+			pinctrl-names = "default";
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+			pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_a>;
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+			bus-width = <4>;
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+			cd-gpios = <&pio 7 1 0>; /* PH1 */
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+			cd-inverted;
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+			status = "okay";
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+		};
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+
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 		usbphy: phy@01c13400 {
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 			usb1_vbus-supply = <&reg_usb1_vbus>;
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 			usb2_vbus-supply = <&reg_usb2_vbus>;
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diff --git a/arch/arm/boot/dts/sun4i-a10-hackberry.dts b/arch/arm/boot/dts/sun4i-a10-hackberry.dts
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index d7c17e4..62defd5 100644
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--- a/arch/arm/boot/dts/sun4i-a10-hackberry.dts
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+++ b/arch/arm/boot/dts/sun4i-a10-hackberry.dts
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@@ -36,6 +36,15 @@
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 			};
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 		};
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+		mmc0: mmc@01c0f000 {
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+			pinctrl-names = "default";
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+			pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_a>;
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+			bus-width = <4>;
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+			cd-gpios = <&pio 7 1 0>; /* PH1 */
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+			cd-inverted;
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+			status = "okay";
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+		};
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+
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 		usbphy: phy@01c13400 {
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 			usb1_vbus-supply = <&reg_usb1_vbus>;
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 			usb2_vbus-supply = <&reg_usb2_vbus>;
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diff --git a/arch/arm/boot/dts/sun4i-a10-inet97fv2.dts b/arch/arm/boot/dts/sun4i-a10-inet97fv2.dts
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index fe9272e..d1a9e34 100644
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--- a/arch/arm/boot/dts/sun4i-a10-inet97fv2.dts
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+++ b/arch/arm/boot/dts/sun4i-a10-inet97fv2.dts
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@@ -24,6 +24,15 @@
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 	};
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 	soc@01c00000 {
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+		mmc0: mmc@01c0f000 {
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+			pinctrl-names = "default";
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+			pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_a>;
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+			bus-width = <4>;
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+			cd-gpios = <&pio 7 1 0>; /* PH1 */
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+			cd-inverted;
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+			status = "okay";
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+		};
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+
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 		uart0: serial@01c28000 {
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 			pinctrl-names = "default";
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 			pinctrl-0 = <&uart0_pins_a>;
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diff --git a/arch/arm/boot/dts/sun4i-a10-mini-xplus.dts b/arch/arm/boot/dts/sun4i-a10-mini-xplus.dts
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index dd84a9e..07a598f 100644
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--- a/arch/arm/boot/dts/sun4i-a10-mini-xplus.dts
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+++ b/arch/arm/boot/dts/sun4i-a10-mini-xplus.dts
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@@ -20,6 +20,15 @@
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 	compatible = "pineriver,mini-xplus", "allwinner,sun4i-a10";
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 	soc@01c00000 {
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+		mmc0: mmc@01c0f000 {
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+			pinctrl-names = "default";
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+			pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_a>;
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+			bus-width = <4>;
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+			cd-gpios = <&pio 7 1 0>; /* PH1 */
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+			cd-inverted;
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+			status = "okay";
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+		};
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+
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 		usbphy: phy@01c13400 {
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 			usb1_vbus-supply = <&reg_usb1_vbus>;
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 			usb2_vbus-supply = <&reg_usb2_vbus>;
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diff --git a/arch/arm/boot/dts/sun4i-a10-olinuxino-lime.dts b/arch/arm/boot/dts/sun4i-a10-olinuxino-lime.dts
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index 66cf0c7..8d5d321 100644
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--- a/arch/arm/boot/dts/sun4i-a10-olinuxino-lime.dts
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+++ b/arch/arm/boot/dts/sun4i-a10-olinuxino-lime.dts
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@@ -33,6 +33,15 @@
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 			};
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 		};
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+		mmc0: mmc@01c0f000 {
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+			pinctrl-names = "default";
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+			pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_a>;
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+			bus-width = <4>;
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+			cd-gpios = <&pio 7 1 0>; /* PH1 */
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+			cd-inverted;
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+			status = "okay";
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+		};
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+
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 		usbphy: phy@01c13400 {
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 			usb1_vbus-supply = <&reg_usb1_vbus>;
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 			usb2_vbus-supply = <&reg_usb2_vbus>;
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diff --git a/arch/arm/boot/dts/sun4i-a10-pcduino.dts b/arch/arm/boot/dts/sun4i-a10-pcduino.dts
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index 255b47e..ce02086 100644
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--- a/arch/arm/boot/dts/sun4i-a10-pcduino.dts
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+++ b/arch/arm/boot/dts/sun4i-a10-pcduino.dts
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@@ -34,6 +34,15 @@
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 			};
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 		};
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+		mmc0: mmc@01c0f000 {
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+			pinctrl-names = "default";
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+			pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_a>;
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+			bus-width = <4>;
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+			cd-gpios = <&pio 7 1 0>; /* PH1 */
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+			cd-inverted;
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+			status = "okay";
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+		};
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+
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 		usbphy: phy@01c13400 {
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 			usb1_vbus-supply = <&reg_usb1_vbus>;
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 			usb2_vbus-supply = <&reg_usb2_vbus>;
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diff --git a/arch/arm/boot/dts/sun4i-a10.dtsi b/arch/arm/boot/dts/sun4i-a10.dtsi
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index 9174724..29fd4f5 100644
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--- a/arch/arm/boot/dts/sun4i-a10.dtsi
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+++ b/arch/arm/boot/dts/sun4i-a10.dtsi
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@@ -377,6 +377,42 @@
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 			#size-cells = <0>;
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 		};
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+		mmc0: mmc@01c0f000 {
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+			compatible = "allwinner,sun4i-a10-mmc";
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+			reg = <0x01c0f000 0x1000>;
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+			clocks = <&ahb_gates 8>, <&mmc0_clk>;
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+			clock-names = "ahb", "mod";
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+			interrupts = <32>;
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+			status = "disabled";
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+		};
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+
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+		mmc1: mmc@01c10000 {
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+			compatible = "allwinner,sun4i-a10-mmc";
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+			reg = <0x01c10000 0x1000>;
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+			clocks = <&ahb_gates 9>, <&mmc1_clk>;
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+			clock-names = "ahb", "mod";
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+			interrupts = <33>;
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+			status = "disabled";
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+		};
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+
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+		mmc2: mmc@01c11000 {
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+			compatible = "allwinner,sun4i-a10-mmc";
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+			reg = <0x01c11000 0x1000>;
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+			clocks = <&ahb_gates 10>, <&mmc2_clk>;
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+			clock-names = "ahb", "mod";
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+			interrupts = <34>;
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+			status = "disabled";
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+		};
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+
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+		mmc3: mmc@01c12000 {
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+			compatible = "allwinner,sun4i-a10-mmc";
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+			reg = <0x01c12000 0x1000>;
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+			clocks = <&ahb_gates 11>, <&mmc3_clk>;
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+			clock-names = "ahb", "mod";
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+			interrupts = <35>;
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+			status = "disabled";
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+		};
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+
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 		usbphy: phy@01c13400 {
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 			#phy-cells = <1>;
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 			compatible = "allwinner,sun4i-a10-usb-phy";
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@@ -529,6 +565,20 @@
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 				allwinner,drive = <0>;
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 				allwinner,pull = <0>;
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 			};
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+
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+			mmc0_pins_a: mmc0@0 {
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+				allwinner,pins = "PF0","PF1","PF2","PF3","PF4","PF5";
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+				allwinner,function = "mmc0";
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+				allwinner,drive = <2>;
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+				allwinner,pull = <0>;
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+			};
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+
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+			mmc0_cd_pin_a: mmc0_cd_pin@0 {
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+				allwinner,pins = "PH1";
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+				allwinner,function = "gpio_in";
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+				allwinner,drive = <0>;
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+				allwinner,pull = <1>;
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+			};
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 		};
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 		timer@01c20c00 {
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diff --git a/arch/arm/boot/dts/sun5i-a10s-olinuxino-micro.dts b/arch/arm/boot/dts/sun5i-a10s-olinuxino-micro.dts
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index 23611b7..de91308 100644
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--- a/arch/arm/boot/dts/sun5i-a10s-olinuxino-micro.dts
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+++ b/arch/arm/boot/dts/sun5i-a10s-olinuxino-micro.dts
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@@ -35,6 +35,24 @@
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 			};
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 		};
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+		mmc0: mmc@01c0f000 {
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+			pinctrl-names = "default";
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+			pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_olinuxino_micro>;
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+			bus-width = <4>;
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+			cd-gpios = <&pio 6 1 0>; /* PG1 */
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+			cd-inverted;
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+			status = "okay";
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+		};
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+
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+		mmc1: mmc@01c10000 {
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+			pinctrl-names = "default";
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+			pinctrl-0 = <&mmc1_pins_a>, <&mmc1_cd_pin_olinuxino_micro>;
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+			bus-width = <4>;
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+			cd-gpios = <&pio 6 13 0>; /* PG13 */
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+			cd-inverted;
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+			status = "okay";
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+		};
1d586d6
+
1d586d6
 		usbphy: phy@01c13400 {
1d586d6
 			usb1_vbus-supply = <&reg_usb1_vbus>;
1d586d6
 			status = "okay";
1d586d6
@@ -49,6 +67,20 @@
1d586d6
 		};
1d586d6
 
1d586d6
 		pinctrl@01c20800 {
1d586d6
+			mmc0_cd_pin_olinuxino_micro: mmc0_cd_pin@0 {
1d586d6
+				allwinner,pins = "PG1";
1d586d6
+				allwinner,function = "gpio_in";
1d586d6
+				allwinner,drive = <0>;
1d586d6
+				allwinner,pull = <1>;
1d586d6
+			};
1d586d6
+
1d586d6
+			mmc1_cd_pin_olinuxino_micro: mmc1_cd_pin@0 {
1d586d6
+				allwinner,pins = "PG13";
1d586d6
+				allwinner,function = "gpio_in";
1d586d6
+				allwinner,drive = <0>;
1d586d6
+				allwinner,pull = <1>;
1d586d6
+			};
1d586d6
+
1d586d6
 			led_pins_olinuxino: led_pins@0 {
1d586d6
 				allwinner,pins = "PE3";
1d586d6
 				allwinner,function = "gpio_out";
1d586d6
diff --git a/arch/arm/boot/dts/sun5i-a10s.dtsi b/arch/arm/boot/dts/sun5i-a10s.dtsi
1d586d6
index 79989ed..fb345c2 100644
1d586d6
--- a/arch/arm/boot/dts/sun5i-a10s.dtsi
1d586d6
+++ b/arch/arm/boot/dts/sun5i-a10s.dtsi
1d586d6
@@ -338,6 +338,33 @@
1d586d6
 			#size-cells = <0>;
1d586d6
 		};
1d586d6
 
1d586d6
+		mmc0: mmc@01c0f000 {
1d586d6
+			compatible = "allwinner,sun5i-a13-mmc";
1d586d6
+			reg = <0x01c0f000 0x1000>;
1d586d6
+			clocks = <&ahb_gates 8>, <&mmc0_clk>;
1d586d6
+			clock-names = "ahb", "mod";
1d586d6
+			interrupts = <32>;
1d586d6
+			status = "disabled";
1d586d6
+		};
1d586d6
+
1d586d6
+		mmc1: mmc@01c10000 {
1d586d6
+			compatible = "allwinner,sun5i-a13-mmc";
1d586d6
+			reg = <0x01c10000 0x1000>;
1d586d6
+			clocks = <&ahb_gates 9>, <&mmc1_clk>;
1d586d6
+			clock-names = "ahb", "mod";
1d586d6
+			interrupts = <33>;
1d586d6
+			status = "disabled";
1d586d6
+		};
1d586d6
+
1d586d6
+		mmc2: mmc@01c11000 {
1d586d6
+			compatible = "allwinner,sun5i-a13-mmc";
1d586d6
+			reg = <0x01c11000 0x1000>;
1d586d6
+			clocks = <&ahb_gates 10>, <&mmc2_clk>;
1d586d6
+			clock-names = "ahb", "mod";
1d586d6
+			interrupts = <34>;
1d586d6
+			status = "disabled";
1d586d6
+		};
1d586d6
+
1d586d6
 		usbphy: phy@01c13400 {
1d586d6
 			#phy-cells = <1>;
1d586d6
 			compatible = "allwinner,sun5i-a13-usb-phy";
1d586d6
@@ -451,6 +478,20 @@
1d586d6
 				allwinner,drive = <0>;
1d586d6
 				allwinner,pull = <0>;
1d586d6
 			};
1d586d6
+
1d586d6
+			mmc0_pins_a: mmc0@0 {
1d586d6
+				allwinner,pins = "PF0","PF1","PF2","PF3","PF4","PF5";
1d586d6
+				allwinner,function = "mmc0";
1d586d6
+				allwinner,drive = <2>;
1d586d6
+				allwinner,pull = <0>;
1d586d6
+			};
1d586d6
+
1d586d6
+			mmc1_pins_a: mmc1@0 {
1d586d6
+				allwinner,pins = "PG3","PG4","PG5","PG6","PG7","PG8";
1d586d6
+				allwinner,function = "mmc1";
1d586d6
+				allwinner,drive = <2>;
1d586d6
+				allwinner,pull = <0>;
1d586d6
+			};
1d586d6
 		};
1d586d6
 
1d586d6
 		timer@01c20c00 {
1d586d6
diff --git a/arch/arm/boot/dts/sun5i-a13-olinuxino-micro.dts b/arch/arm/boot/dts/sun5i-a13-olinuxino-micro.dts
1d586d6
index 11169d5..8515f19 100644
1d586d6
--- a/arch/arm/boot/dts/sun5i-a13-olinuxino-micro.dts
1d586d6
+++ b/arch/arm/boot/dts/sun5i-a13-olinuxino-micro.dts
1d586d6
@@ -21,6 +21,15 @@
1d586d6
 	compatible = "olimex,a13-olinuxino-micro", "allwinner,sun5i-a13";
1d586d6
 
1d586d6
 	soc@01c00000 {
1d586d6
+		mmc0: mmc@01c0f000 {
1d586d6
+			pinctrl-names = "default";
1d586d6
+			pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_olinuxinom>;
1d586d6
+			bus-width = <4>;
1d586d6
+			cd-gpios = <&pio 6 0 0>; /* PG0 */
1d586d6
+			cd-inverted;
1d586d6
+			status = "okay";
1d586d6
+		};
1d586d6
+
1d586d6
 		usbphy: phy@01c13400 {
1d586d6
 			usb1_vbus-supply = <&reg_usb1_vbus>;
1d586d6
 			status = "okay";
1d586d6
@@ -35,6 +44,13 @@
1d586d6
 		};
1d586d6
 
1d586d6
 		pinctrl@01c20800 {
1d586d6
+			mmc0_cd_pin_olinuxinom: mmc0_cd_pin@0 {
1d586d6
+				allwinner,pins = "PG0";
1d586d6
+				allwinner,function = "gpio_in";
1d586d6
+				allwinner,drive = <0>;
1d586d6
+				allwinner,pull = <1>;
1d586d6
+			};
1d586d6
+
1d586d6
 			led_pins_olinuxinom: led_pins@0 {
1d586d6
 				allwinner,pins = "PG9";
1d586d6
 				allwinner,function = "gpio_out";
1d586d6
diff --git a/arch/arm/boot/dts/sun5i-a13-olinuxino.dts b/arch/arm/boot/dts/sun5i-a13-olinuxino.dts
1d586d6
index 7a9187b..51a9438 100644
1d586d6
--- a/arch/arm/boot/dts/sun5i-a13-olinuxino.dts
1d586d6
+++ b/arch/arm/boot/dts/sun5i-a13-olinuxino.dts
1d586d6
@@ -20,6 +20,15 @@
1d586d6
 	compatible = "olimex,a13-olinuxino", "allwinner,sun5i-a13";
1d586d6
 
1d586d6
 	soc@01c00000 {
1d586d6
+		mmc0: mmc@01c0f000 {
1d586d6
+			pinctrl-names = "default";
1d586d6
+			pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_olinuxino>;
1d586d6
+			bus-width = <4>;
1d586d6
+			cd-gpios = <&pio 6 0 0>; /* PG0 */
1d586d6
+			cd-inverted;
1d586d6
+			status = "okay";
1d586d6
+		};
1d586d6
+
1d586d6
 		usbphy: phy@01c13400 {
1d586d6
 			usb1_vbus-supply = <&reg_usb1_vbus>;
1d586d6
 			status = "okay";
1d586d6
@@ -34,6 +43,13 @@
1d586d6
 		};
1d586d6
 
1d586d6
 		pinctrl@01c20800 {
1d586d6
+			mmc0_cd_pin_olinuxino: mmc0_cd_pin@0 {
1d586d6
+				allwinner,pins = "PG0";
1d586d6
+				allwinner,function = "gpio_in";
1d586d6
+				allwinner,drive = <0>;
1d586d6
+				allwinner,pull = <1>;
1d586d6
+			};
1d586d6
+
1d586d6
 			led_pins_olinuxino: led_pins@0 {
1d586d6
 				allwinner,pins = "PG9";
1d586d6
 				allwinner,function = "gpio_out";
1d586d6
diff --git a/arch/arm/boot/dts/sun5i-a13.dtsi b/arch/arm/boot/dts/sun5i-a13.dtsi
1d586d6
index f01c315..48ffa51 100644
1d586d6
--- a/arch/arm/boot/dts/sun5i-a13.dtsi
1d586d6
+++ b/arch/arm/boot/dts/sun5i-a13.dtsi
1d586d6
@@ -320,6 +320,24 @@
1d586d6
 			#size-cells = <0>;
1d586d6
 		};
1d586d6
 
1d586d6
+		mmc0: mmc@01c0f000 {
1d586d6
+			compatible = "allwinner,sun5i-a13-mmc";
1d586d6
+			reg = <0x01c0f000 0x1000>;
1d586d6
+			clocks = <&ahb_gates 8>, <&mmc0_clk>;
1d586d6
+			clock-names = "ahb", "mod";
1d586d6
+			interrupts = <32>;
1d586d6
+			status = "disabled";
1d586d6
+		};
1d586d6
+
1d586d6
+		mmc2: mmc@01c11000 {
1d586d6
+			compatible = "allwinner,sun5i-a13-mmc";
1d586d6
+			reg = <0x01c11000 0x1000>;
1d586d6
+			clocks = <&ahb_gates 10>, <&mmc2_clk>;
1d586d6
+			clock-names = "ahb", "mod";
1d586d6
+			interrupts = <34>;
1d586d6
+			status = "disabled";
1d586d6
+		};
1d586d6
+
1d586d6
 		usbphy: phy@01c13400 {
1d586d6
 			#phy-cells = <1>;
1d586d6
 			compatible = "allwinner,sun5i-a13-usb-phy";
1d586d6
@@ -415,6 +433,13 @@
1d586d6
 				allwinner,drive = <0>;
1d586d6
 				allwinner,pull = <0>;
1d586d6
 			};
1d586d6
+
1d586d6
+			mmc0_pins_a: mmc0@0 {
1d586d6
+				allwinner,pins = "PF0","PF1","PF2","PF3","PF4","PF5";
1d586d6
+				allwinner,function = "mmc0";
1d586d6
+				allwinner,drive = <2>;
1d586d6
+				allwinner,pull = <0>;
1d586d6
+			};
1d586d6
 		};
1d586d6
 
1d586d6
 		timer@01c20c00 {
1d586d6
diff --git a/arch/arm/boot/dts/sun6i-a31-m9.dts b/arch/arm/boot/dts/sun6i-a31-m9.dts
1d586d6
new file mode 100644
1d586d6
index 0000000..a188721
1d586d6
--- /dev/null
1d586d6
+++ b/arch/arm/boot/dts/sun6i-a31-m9.dts
1d586d6
@@ -0,0 +1,46 @@
1d586d6
+/*
1d586d6
+ * Copyright 2014 Hans de Goede <hdegoede@redhat.com>
1d586d6
+ *
1d586d6
+ * The code contained herein is licensed under the GNU General Public
1d586d6
+ * License. You may obtain a copy of the GNU General Public License
1d586d6
+ * Version 2 or later at the following locations:
1d586d6
+ *
1d586d6
+ * http://www.opensource.org/licenses/gpl-license.html
1d586d6
+ * http://www.gnu.org/copyleft/gpl.html
1d586d6
+ */
1d586d6
+
1d586d6
+/dts-v1/;
1d586d6
+/include/ "sun6i-a31.dtsi"
1d586d6
+
1d586d6
+/ {
1d586d6
+	model = "Mele M9 / A1000G Quad top set box";
1d586d6
+	compatible = "mele,m9", "allwinner,sun6i-a31";
1d586d6
+
1d586d6
+	chosen {
1d586d6
+		bootargs = "earlyprintk console=ttyS0,115200";
1d586d6
+	};
1d586d6
+
1d586d6
+	soc@01c00000 {
1d586d6
+		mmc0: mmc@01c0f000 {
1d586d6
+			pinctrl-names = "default";
1d586d6
+			pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_m9>;
1d586d6
+			cd-gpios = <&pio 7 22 0>; /* PH22 */
1d586d6
+			status = "okay";
1d586d6
+		};
1d586d6
+
1d586d6
+		pio: pinctrl@01c20800 {
1d586d6
+			mmc0_cd_pin_m9: mmc0_cd_pin@0 {
1d586d6
+				allwinner,pins = "PH22";
1d586d6
+				allwinner,function = "gpio_in";
1d586d6
+				allwinner,drive = <0>;
1d586d6
+				allwinner,pull = <1>;
1d586d6
+			};
1d586d6
+		};
1d586d6
+
1d586d6
+		uart0: serial@01c28000 {
1d586d6
+			pinctrl-names = "default";
1d586d6
+			pinctrl-0 = <&uart0_pins_a>;
1d586d6
+			status = "okay";
1d586d6
+		};
1d586d6
+	};
1d586d6
+};
1d586d6
diff --git a/arch/arm/boot/dts/sun6i-a31.dtsi b/arch/arm/boot/dts/sun6i-a31.dtsi
1d586d6
index d45efa7..0939fc1 100644
1d586d6
--- a/arch/arm/boot/dts/sun6i-a31.dtsi
1d586d6
+++ b/arch/arm/boot/dts/sun6i-a31.dtsi
1d586d6
@@ -198,6 +198,38 @@
1d586d6
 					"apb2_uart4", "apb2_uart5";
1d586d6
 		};
1d586d6
 
1d586d6
+		mmc0_clk: clk@01c20088 {
1d586d6
+			#clock-cells = <0>;
1d586d6
+			compatible = "allwinner,sun4i-a10-mod0-clk";
1d586d6
+			reg = <0x01c20088 0x4>;
1d586d6
+			clocks = <&osc24M>, <&pll6>;
1d586d6
+			clock-output-names = "mmc0";
1d586d6
+		};
1d586d6
+
1d586d6
+		mmc1_clk: clk@01c2008c {
1d586d6
+			#clock-cells = <0>;
1d586d6
+			compatible = "allwinner,sun4i-a10-mod0-clk";
1d586d6
+			reg = <0x01c2008c 0x4>;
1d586d6
+			clocks = <&osc24M>, <&pll6>;
1d586d6
+			clock-output-names = "mmc1";
1d586d6
+		};
1d586d6
+
1d586d6
+		mmc2_clk: clk@01c20090 {
1d586d6
+			#clock-cells = <0>;
1d586d6
+			compatible = "allwinner,sun4i-a10-mod0-clk";
1d586d6
+			reg = <0x01c20090 0x4>;
1d586d6
+			clocks = <&osc24M>, <&pll6>;
1d586d6
+			clock-output-names = "mmc2";
1d586d6
+		};
1d586d6
+
1d586d6
+		mmc3_clk: clk@01c20094 {
1d586d6
+			#clock-cells = <0>;
1d586d6
+			compatible = "allwinner,sun4i-a10-mod0-clk";
1d586d6
+			reg = <0x01c20094 0x4>;
1d586d6
+			clocks = <&osc24M>, <&pll6>;
1d586d6
+			clock-output-names = "mmc3";
1d586d6
+		};
1d586d6
+
1d586d6
 		spi0_clk: clk@01c200a0 {
1d586d6
 			#clock-cells = <0>;
1d586d6
 			compatible = "allwinner,sun4i-a10-mod0-clk";
1d586d6
@@ -237,6 +269,58 @@
1d586d6
 		#size-cells = <1>;
1d586d6
 		ranges;
1d586d6
 
1d586d6
+		mmc0: mmc@01c0f000 {
1d586d6
+			compatible = "allwinner,sun5i-a13-mmc";
1d586d6
+			reg = <0x01c0f000 0x1000>;
1d586d6
+			clocks = <&ahb1_gates 8>, <&mmc0_clk>;
1d586d6
+			clock-names = "ahb", "mod";
1d586d6
+			resets = <&ahb1_rst 8>;
1d586d6
+			reset-names = "ahb";
1d586d6
+			interrupts = <0 60 4>;
1d586d6
+			bus-width = <4>;
1d586d6
+			cd-inverted;
1d586d6
+			status = "disabled";
1d586d6
+		};
1d586d6
+
1d586d6
+		mmc1: mmc@01c10000 {
1d586d6
+			compatible = "allwinner,sun5i-a13-mmc";
1d586d6
+			reg = <0x01c10000 0x1000>;
1d586d6
+			clocks = <&ahb1_gates 9>, <&mmc1_clk>;
1d586d6
+			clock-names = "ahb", "mod";
1d586d6
+			resets = <&ahb1_rst 9>;
1d586d6
+			reset-names = "reset";
1d586d6
+			interrupts = <0 61 4>;
1d586d6
+			bus-width = <4>;
1d586d6
+			cd-inverted;
1d586d6
+			status = "disabled";
1d586d6
+		};
1d586d6
+
1d586d6
+		mmc2: mmc@01c11000 {
1d586d6
+			compatible = "allwinner,sun5i-a13-mmc";
1d586d6
+			reg = <0x01c11000 0x1000>;
1d586d6
+			clocks = <&ahb1_gates 10>, <&mmc2_clk>;
1d586d6
+			clock-names = "ahb", "mod";
1d586d6
+			resets = <&ahb1_rst 10>;
1d586d6
+			reset-names = "reset";
1d586d6
+			interrupts = <0 62 4>;
1d586d6
+			bus-width = <4>;
1d586d6
+			cd-inverted;
1d586d6
+			status = "disabled";
1d586d6
+		};
1d586d6
+
1d586d6
+		mmc3: mmc@01c12000 {
1d586d6
+			compatible = "allwinner,sun5i-a13-mmc";
1d586d6
+			reg = <0x01c12000 0x1000>;
1d586d6
+			clocks = <&ahb1_gates 11>, <&mmc3_clk>;
1d586d6
+			clock-names = "ahb", "mod";
1d586d6
+			resets = <&ahb1_rst 11>;
1d586d6
+			reset-names = "reset";
1d586d6
+			interrupts = <0 63 4>;
1d586d6
+			bus-width = <4>;
1d586d6
+			cd-inverted;
1d586d6
+			status = "disabled";
1d586d6
+		};
1d586d6
+
1d586d6
 		nmi_intc: interrupt-controller@01f00c0c {
1d586d6
 			compatible = "allwinner,sun6i-a31-sc-nmi";
1d586d6
 			interrupt-controller;
1d586d6
@@ -286,6 +370,13 @@
1d586d6
 				allwinner,drive = <0>;
1d586d6
 				allwinner,pull = <0>;
1d586d6
 			};
1d586d6
+
1d586d6
+			mmc0_pins_a: mmc0@0 {
1d586d6
+				allwinner,pins = "PF0","PF1","PF2","PF3","PF4","PF5";
1d586d6
+				allwinner,function = "mmc0";
1d586d6
+				allwinner,drive = <2>;
1d586d6
+				allwinner,pull = <0>;
1d586d6
+			};
1d586d6
 		};
1d586d6
 
1d586d6
 		ahb1_rst: reset@01c202c0 {
1d586d6
diff --git a/arch/arm/boot/dts/sun7i-a20-cubieboard2.dts b/arch/arm/boot/dts/sun7i-a20-cubieboard2.dts
1d586d6
index 68de89f..b41aa99 100644
1d586d6
--- a/arch/arm/boot/dts/sun7i-a20-cubieboard2.dts
1d586d6
+++ b/arch/arm/boot/dts/sun7i-a20-cubieboard2.dts
1d586d6
@@ -20,6 +20,15 @@
1d586d6
 	compatible = "cubietech,cubieboard2", "allwinner,sun7i-a20";
1d586d6
 
1d586d6
 	soc@01c00000 {
1d586d6
+		mmc0: mmc@01c0f000 {
1d586d6
+			pinctrl-names = "default";
1d586d6
+			pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_a>;
1d586d6
+			bus-width = <4>;
1d586d6
+			cd-gpios = <&pio 7 1 0>; /* PH1 */
1d586d6
+			cd-inverted;
1d586d6
+			status = "okay";
1d586d6
+		};
1d586d6
+
1d586d6
 		usbphy: phy@01c13400 {
1d586d6
 			usb1_vbus-supply = <&reg_usb1_vbus>;
1d586d6
 			usb2_vbus-supply = <&reg_usb2_vbus>;
1d586d6
diff --git a/arch/arm/boot/dts/sun7i-a20-cubietruck.dts b/arch/arm/boot/dts/sun7i-a20-cubietruck.dts
1d586d6
index cb25d3c..270bac0 100644
1d586d6
--- a/arch/arm/boot/dts/sun7i-a20-cubietruck.dts
1d586d6
+++ b/arch/arm/boot/dts/sun7i-a20-cubietruck.dts
1d586d6
@@ -20,6 +20,23 @@
1d586d6
 	compatible = "cubietech,cubietruck", "allwinner,sun7i-a20";
1d586d6
 
1d586d6
 	soc@01c00000 {
1d586d6
+		mmc0: mmc@01c0f000 {
1d586d6
+			pinctrl-names = "default";
1d586d6
+			pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_a>;
1d586d6
+			bus-width = <4>;
1d586d6
+			cd-gpios = <&pio 7 1 0>; /* PH1 */
1d586d6
+			cd-inverted;
1d586d6
+			status = "okay";
1d586d6
+		};
1d586d6
+
1d586d6
+		mmc3: mmc@01c12000 {
1d586d6
+			pinctrl-names = "default";
1d586d6
+			pinctrl-0 = <&mmc3_pins_a>;
1d586d6
+			vmmc-supply = <&reg_vmmc3>;
1d586d6
+			non-removable;
1d586d6
+			status = "okay";
1d586d6
+		};
1d586d6
+
1d586d6
 		usbphy: phy@01c13400 {
1d586d6
 			usb1_vbus-supply = <&reg_usb1_vbus>;
1d586d6
 			usb2_vbus-supply = <&reg_usb2_vbus>;
1d586d6
@@ -48,6 +65,18 @@
1d586d6
 		};
1d586d6
 
1d586d6
 		pinctrl@01c20800 {
1d586d6
+			mmc3_pins_a: mmc3@0 {
1d586d6
+				/* AP6210 requires pull-up */
1d586d6
+				allwinner,pull = <1>;
1d586d6
+			};
1d586d6
+
1d586d6
+			vmmc3_pin_cubietruck: vmmc3_pin@0 {
1d586d6
+				allwinner,pins = "PH9";
1d586d6
+				allwinner,function = "gpio_out";
1d586d6
+				allwinner,drive = <0>;
1d586d6
+				allwinner,pull = <0>;
1d586d6
+			};
1d586d6
+
1d586d6
 			ahci_pwr_pin_cubietruck: ahci_pwr_pin@1 {
1d586d6
 				allwinner,pins = "PH12";
1d586d6
 				allwinner,function = "gpio_out";
1d586d6
@@ -139,4 +168,15 @@
1d586d6
 	reg_usb2_vbus: usb2-vbus {
1d586d6
 		status = "okay";
1d586d6
 	};
1d586d6
+
1d586d6
+	reg_vmmc3: vmmc3 {
1d586d6
+		compatible = "regulator-fixed";
1d586d6
+		pinctrl-names = "default";
1d586d6
+		pinctrl-0 = <&vmmc3_pin_cubietruck>;
1d586d6
+		regulator-name = "vmmc3";
1d586d6
+		regulator-min-microvolt = <3300000>;
1d586d6
+		regulator-max-microvolt = <3300000>;
1d586d6
+		enable-active-high;
1d586d6
+		gpio = <&pio 7 9 0>;
1d586d6
+	};
1d586d6
 };
1d586d6
diff --git a/arch/arm/boot/dts/sun7i-a20-olinuxino-micro.dts b/arch/arm/boot/dts/sun7i-a20-olinuxino-micro.dts
1d586d6
index eeadf76..f989554 100644
1d586d6
--- a/arch/arm/boot/dts/sun7i-a20-olinuxino-micro.dts
1d586d6
+++ b/arch/arm/boot/dts/sun7i-a20-olinuxino-micro.dts
1d586d6
@@ -31,6 +31,24 @@
1d586d6
 			status = "okay";
1d586d6
 		};
1d586d6
 
1d586d6
+		mmc0: mmc@01c0f000 {
1d586d6
+			pinctrl-names = "default";
1d586d6
+			pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_a>;
1d586d6
+			bus-width = <4>;
1d586d6
+			cd-gpios = <&pio 7 1 0>; /* PH1 */
1d586d6
+			cd-inverted;
1d586d6
+			status = "okay";
1d586d6
+		};
1d586d6
+
1d586d6
+		mmc3: mmc@01c12000 {
1d586d6
+			pinctrl-names = "default";
1d586d6
+			pinctrl-0 = <&mmc3_pins_a>, <&mmc3_cd_pin_olinuxinom>;
1d586d6
+			bus-width = <4>;
1d586d6
+			cd-gpios = <&pio 7 11 0>; /* PH11 */
1d586d6
+			cd-inverted;
1d586d6
+			status = "okay";
1d586d6
+		};
1d586d6
+
1d586d6
 		usbphy: phy@01c13400 {
1d586d6
 			usb1_vbus-supply = <&reg_usb1_vbus>;
1d586d6
 			usb2_vbus-supply = <&reg_usb2_vbus>;
1d586d6
@@ -65,6 +83,13 @@
1d586d6
 		};
1d586d6
 
1d586d6
 		pinctrl@01c20800 {
1d586d6
+			mmc3_cd_pin_olinuxinom: mmc3_cd_pin@0 {
1d586d6
+				allwinner,pins = "PH11";
1d586d6
+				allwinner,function = "gpio_in";
1d586d6
+				allwinner,drive = <0>;
1d586d6
+				allwinner,pull = <1>;
1d586d6
+			};
1d586d6
+
1d586d6
 			led_pins_olinuxino: led_pins@0 {
1d586d6
 				allwinner,pins = "PH2";
1d586d6
 				allwinner,function = "gpio_out";
1d586d6
diff --git a/arch/arm/boot/dts/sun7i-a20.dtsi b/arch/arm/boot/dts/sun7i-a20.dtsi
1d586d6
index 32efc10..99e8336 100644
1d586d6
--- a/arch/arm/boot/dts/sun7i-a20.dtsi
1d586d6
+++ b/arch/arm/boot/dts/sun7i-a20.dtsi
1d586d6
@@ -447,6 +447,42 @@
1d586d6
 			#size-cells = <0>;
1d586d6
 		};
1d586d6
 
1d586d6
+		mmc0: mmc@01c0f000 {
1d586d6
+			compatible = "allwinner,sun5i-a13-mmc";
1d586d6
+			reg = <0x01c0f000 0x1000>;
1d586d6
+			clocks = <&ahb_gates 8>, <&mmc0_clk>;
1d586d6
+			clock-names = "ahb", "mod";
1d586d6
+			interrupts = <0 32 4>;
1d586d6
+			status = "disabled";
1d586d6
+		};
1d586d6
+
1d586d6
+		mmc1: mmc@01c10000 {
1d586d6
+			compatible = "allwinner,sun5i-a13-mmc";
1d586d6
+			reg = <0x01c10000 0x1000>;
1d586d6
+			clocks = <&ahb_gates 9>, <&mmc1_clk>;
1d586d6
+			clock-names = "ahb", "mod";
1d586d6
+			interrupts = <0 33 4>;
1d586d6
+			status = "disabled";
1d586d6
+		};
1d586d6
+
1d586d6
+		mmc2: mmc@01c11000 {
1d586d6
+			compatible = "allwinner,sun5i-a13-mmc";
1d586d6
+			reg = <0x01c11000 0x1000>;
1d586d6
+			clocks = <&ahb_gates 10>, <&mmc2_clk>;
1d586d6
+			clock-names = "ahb", "mod";
1d586d6
+			interrupts = <0 34 4>;
1d586d6
+			status = "disabled";
1d586d6
+		};
1d586d6
+
1d586d6
+		mmc3: mmc@01c12000 {
1d586d6
+			compatible = "allwinner,sun5i-a13-mmc";
1d586d6
+			reg = <0x01c12000 0x1000>;
1d586d6
+			clocks = <&ahb_gates 11>, <&mmc3_clk>;
1d586d6
+			clock-names = "ahb", "mod";
1d586d6
+			interrupts = <0 35 4>;
1d586d6
+			status = "disabled";
1d586d6
+		};
1d586d6
+
1d586d6
 		usbphy: phy@01c13400 {
1d586d6
 			#phy-cells = <1>;
1d586d6
 			compatible = "allwinner,sun7i-a20-usb-phy";
1d586d6
@@ -653,6 +689,27 @@
1d586d6
 				allwinner,drive = <0>;
1d586d6
 				allwinner,pull = <0>;
1d586d6
 			};
1d586d6
+
1d586d6
+			mmc0_pins_a: mmc0@0 {
1d586d6
+				allwinner,pins = "PF0","PF1","PF2","PF3","PF4","PF5";
1d586d6
+				allwinner,function = "mmc0";
1d586d6
+				allwinner,drive = <2>;
1d586d6
+				allwinner,pull = <0>;
1d586d6
+			};
1d586d6
+
1d586d6
+			mmc0_cd_pin_a: mmc0_cd_pin@0 {
1d586d6
+				allwinner,pins = "PH1";
1d586d6
+				allwinner,function = "gpio_in";
1d586d6
+				allwinner,drive = <0>;
1d586d6
+				allwinner,pull = <1>;
1d586d6
+			};
1d586d6
+
1d586d6
+			mmc3_pins_a: mmc3@0 {
1d586d6
+				allwinner,pins = "PI4","PI5","PI6","PI7","PI8","PI9";
1d586d6
+				allwinner,function = "mmc3";
1d586d6
+				allwinner,drive = <2>;
1d586d6
+				allwinner,pull = <0>;
1d586d6
+			};
1d586d6
 		};
1d586d6
 
1d586d6
 		timer@01c20c00 {
1d586d6
diff --git a/drivers/clk/sunxi/clk-factors.c b/drivers/clk/sunxi/clk-factors.c
1d586d6
index 9e23264..3806d97 100644
1d586d6
--- a/drivers/clk/sunxi/clk-factors.c
1d586d6
+++ b/drivers/clk/sunxi/clk-factors.c
1d586d6
@@ -77,6 +77,41 @@ static long clk_factors_round_rate(struct clk_hw *hw, unsigned long rate,
1d586d6
 	return rate;
1d586d6
 }
1d586d6
 
1d586d6
+static long clk_factors_determine_rate(struct clk_hw *hw, unsigned long rate,
1d586d6
+				       unsigned long *best_parent_rate,
1d586d6
+				       struct clk **best_parent_p)
1d586d6
+{
1d586d6
+	struct clk *clk = hw->clk, *parent, *best_parent = NULL;
1d586d6
+	int i, num_parents;
1d586d6
+	unsigned long parent_rate, best = 0, child_rate, best_child_rate = 0;
1d586d6
+
1d586d6
+	/* find the parent that can help provide the fastest rate <= rate */
1d586d6
+	num_parents = __clk_get_num_parents(clk);
1d586d6
+	for (i = 0; i < num_parents; i++) {
1d586d6
+		parent = clk_get_parent_by_index(clk, i);
1d586d6
+		if (!parent)
1d586d6
+			continue;
1d586d6
+		if (__clk_get_flags(clk) & CLK_SET_RATE_PARENT)
1d586d6
+			parent_rate = __clk_round_rate(parent, rate);
1d586d6
+		else
1d586d6
+			parent_rate = __clk_get_rate(parent);
1d586d6
+
1d586d6
+		child_rate = clk_factors_round_rate(hw, rate, &parent_rate);
1d586d6
+
1d586d6
+		if (child_rate <= rate && child_rate > best_child_rate) {
1d586d6
+			best_parent = parent;
1d586d6
+			best = parent_rate;
1d586d6
+			best_child_rate = child_rate;
1d586d6
+		}
1d586d6
+	}
1d586d6
+
1d586d6
+	if (best_parent)
1d586d6
+		*best_parent_p = best_parent;
1d586d6
+	*best_parent_rate = best;
1d586d6
+
1d586d6
+	return best_child_rate;
1d586d6
+}
1d586d6
+
1d586d6
 static int clk_factors_set_rate(struct clk_hw *hw, unsigned long rate,
1d586d6
 				unsigned long parent_rate)
1d586d6
 {
1d586d6
@@ -113,6 +148,7 @@ static int clk_factors_set_rate(struct clk_hw *hw, unsigned long rate,
1d586d6
 }
1d586d6
 
1d586d6
 const struct clk_ops clk_factors_ops = {
1d586d6
+	.determine_rate = clk_factors_determine_rate,
1d586d6
 	.recalc_rate = clk_factors_recalc_rate,
1d586d6
 	.round_rate = clk_factors_round_rate,
1d586d6
 	.set_rate = clk_factors_set_rate,
1d586d6
diff --git a/drivers/clk/sunxi/clk-sunxi.c b/drivers/clk/sunxi/clk-sunxi.c
1d586d6
index bd7dc73..59f9040 100644
1d586d6
--- a/drivers/clk/sunxi/clk-sunxi.c
1d586d6
+++ b/drivers/clk/sunxi/clk-sunxi.c
1d586d6
@@ -507,6 +507,42 @@ CLK_OF_DECLARE(sun7i_a20_gmac, "allwinner,sun7i-a20-gmac-clk",
1d586d6
 
1d586d6
 
1d586d6
 /**
1d586d6
+ * clk_sunxi_mmc_phase_control() - configures MMC clock phase control
1d586d6
+ */
1d586d6
+
1d586d6
+void clk_sunxi_mmc_phase_control(struct clk_hw *hw, u8 sample, u8 output)
1d586d6
+{
1d586d6
+	#define to_clk_composite(_hw) container_of(_hw, struct clk_composite, hw)
1d586d6
+	#define to_clk_factors(_hw) container_of(_hw, struct clk_factors, hw)
1d586d6
+
1d586d6
+	struct clk_composite *composite = to_clk_composite(hw);
1d586d6
+	struct clk_hw *rate_hw = composite->rate_hw;
1d586d6
+	struct clk_factors *factors = to_clk_factors(rate_hw);
1d586d6
+	unsigned long flags = 0;
1d586d6
+	u32 reg;
1d586d6
+
1d586d6
+	if (factors->lock)
1d586d6
+		spin_lock_irqsave(factors->lock, flags);
1d586d6
+
1d586d6
+	reg = readl(factors->reg);
1d586d6
+
1d586d6
+	/* set sample clock phase control */
1d586d6
+	reg &= ~(0x7 << 20);
1d586d6
+	reg |= ((sample & 0x7) << 20);
1d586d6
+
1d586d6
+	/* set output clock phase control */
1d586d6
+	reg &= ~(0x7 << 8);
1d586d6
+	reg |= ((output & 0x7) << 8);
1d586d6
+
1d586d6
+	writel(reg, factors->reg);
1d586d6
+
1d586d6
+	if (factors->lock)
1d586d6
+		spin_unlock_irqrestore(factors->lock, flags);
1d586d6
+}
1d586d6
+EXPORT_SYMBOL(clk_sunxi_mmc_phase_control);
1d586d6
+
1d586d6
+
1d586d6
+/**
1d586d6
  * sunxi_factors_clk_setup() - Setup function for factor clocks
1d586d6
  */
1d586d6
 
1d586d6
diff --git a/drivers/mmc/host/Kconfig b/drivers/mmc/host/Kconfig
1d586d6
index 8aaf8c1..d50ac1c 100644
1d586d6
--- a/drivers/mmc/host/Kconfig
1d586d6
+++ b/drivers/mmc/host/Kconfig
1d586d6
@@ -694,3 +694,10 @@ config MMC_REALTEK_PCI
1d586d6
 	help
1d586d6
 	  Say Y here to include driver code to support SD/MMC card interface
1d586d6
 	  of Realtek PCI-E card reader
1d586d6
+
1d586d6
+config MMC_SUNXI
1d586d6
+	tristate "Allwinner sunxi SD/MMC Host Controller support"
1d586d6
+	depends on ARCH_SUNXI
1d586d6
+	help
1d586d6
+	  This selects support for the SD/MMC Host Controller on
1d586d6
+	  Allwinner sunxi SoCs.
1d586d6
diff --git a/drivers/mmc/host/Makefile b/drivers/mmc/host/Makefile
1d586d6
index 0c8aa5e..c706c0f 100644
1d586d6
--- a/drivers/mmc/host/Makefile
1d586d6
+++ b/drivers/mmc/host/Makefile
1d586d6
@@ -53,6 +53,8 @@ obj-$(CONFIG_MMC_WMT)		+= wmt-sdmmc.o
1d586d6
 
1d586d6
 obj-$(CONFIG_MMC_REALTEK_PCI)	+= rtsx_pci_sdmmc.o
1d586d6
 
1d586d6
+obj-$(CONFIG_MMC_SUNXI)		+= sunxi-mmc.o
1d586d6
+
1d586d6
 obj-$(CONFIG_MMC_SDHCI_PLTFM)		+= sdhci-pltfm.o
1d586d6
 obj-$(CONFIG_MMC_SDHCI_CNS3XXX)		+= sdhci-cns3xxx.o
1d586d6
 obj-$(CONFIG_MMC_SDHCI_ESDHC_IMX)	+= sdhci-esdhc-imx.o
1d586d6
diff --git a/drivers/mmc/host/sunxi-mmc.c b/drivers/mmc/host/sunxi-mmc.c
1d586d6
new file mode 100644
1d586d6
index 0000000..f1de52c
1d586d6
--- /dev/null
1d586d6
+++ b/drivers/mmc/host/sunxi-mmc.c
1d586d6
@@ -0,0 +1,1125 @@
1d586d6
+/*
1d586d6
+ * Driver for sunxi SD/MMC host controllers
1d586d6
+ * (C) Copyright 2007-2011 Reuuimlla Technology Co., Ltd.
1d586d6
+ * (C) Copyright 2007-2011 Aaron Maoye <leafy.myeh@reuuimllatech.com>
1d586d6
+ * (C) Copyright 2013-2014 O2S GmbH <www.o2s.ch>
1d586d6
+ * (C) Copyright 2013-2014 David Lanzend÷rfer <david.lanzendoerfer@o2s.ch>
1d586d6
+ * (C) Copyright 2013-2014 Hans de Goede <hdegoede@redhat.com>
1d586d6
+ *
1d586d6
+ * This program is free software; you can redistribute it and/or
1d586d6
+ * modify it under the terms of the GNU General Public License as
1d586d6
+ * published by the Free Software Foundation; either version 2 of
1d586d6
+ * the License, or (at your option) any later version.
1d586d6
+ */
1d586d6
+
1d586d6
+#include <linux/kernel.h>
1d586d6
+#include <linux/module.h>
1d586d6
+#include <linux/io.h>
1d586d6
+#include <linux/device.h>
1d586d6
+#include <linux/interrupt.h>
1d586d6
+#include <linux/delay.h>
1d586d6
+#include <linux/err.h>
1d586d6
+
1d586d6
+#include <linux/clk.h>
1d586d6
+#include <linux/clk-private.h>
1d586d6
+#include <linux/clk/sunxi.h>
1d586d6
+
1d586d6
+#include <linux/gpio.h>
1d586d6
+#include <linux/platform_device.h>
1d586d6
+#include <linux/spinlock.h>
1d586d6
+#include <linux/scatterlist.h>
1d586d6
+#include <linux/dma-mapping.h>
1d586d6
+#include <linux/slab.h>
1d586d6
+#include <linux/regulator/consumer.h>
1d586d6
+#include <linux/reset.h>
1d586d6
+
1d586d6
+#include <linux/of_address.h>
1d586d6
+#include <linux/of_gpio.h>
1d586d6
+#include <linux/of_platform.h>
1d586d6
+
1d586d6
+#include <linux/mmc/host.h>
1d586d6
+#include <linux/mmc/sd.h>
1d586d6
+#include <linux/mmc/sdio.h>
1d586d6
+#include <linux/mmc/mmc.h>
1d586d6
+#include <linux/mmc/core.h>
1d586d6
+#include <linux/mmc/card.h>
1d586d6
+#include <linux/mmc/slot-gpio.h>
1d586d6
+
1d586d6
+/* register offset definitions */
1d586d6
+#define SDXC_REG_GCTRL	(0x00) /* SMC Global Control Register */
1d586d6
+#define SDXC_REG_CLKCR	(0x04) /* SMC Clock Control Register */
1d586d6
+#define SDXC_REG_TMOUT	(0x08) /* SMC Time Out Register */
1d586d6
+#define SDXC_REG_WIDTH	(0x0C) /* SMC Bus Width Register */
1d586d6
+#define SDXC_REG_BLKSZ	(0x10) /* SMC Block Size Register */
1d586d6
+#define SDXC_REG_BCNTR	(0x14) /* SMC Byte Count Register */
1d586d6
+#define SDXC_REG_CMDR	(0x18) /* SMC Command Register */
1d586d6
+#define SDXC_REG_CARG	(0x1C) /* SMC Argument Register */
1d586d6
+#define SDXC_REG_RESP0	(0x20) /* SMC Response Register 0 */
1d586d6
+#define SDXC_REG_RESP1	(0x24) /* SMC Response Register 1 */
1d586d6
+#define SDXC_REG_RESP2	(0x28) /* SMC Response Register 2 */
1d586d6
+#define SDXC_REG_RESP3	(0x2C) /* SMC Response Register 3 */
1d586d6
+#define SDXC_REG_IMASK	(0x30) /* SMC Interrupt Mask Register */
1d586d6
+#define SDXC_REG_MISTA	(0x34) /* SMC Masked Interrupt Status Register */
1d586d6
+#define SDXC_REG_RINTR	(0x38) /* SMC Raw Interrupt Status Register */
1d586d6
+#define SDXC_REG_STAS	(0x3C) /* SMC Status Register */
1d586d6
+#define SDXC_REG_FTRGL	(0x40) /* SMC FIFO Threshold Watermark Registe */
1d586d6
+#define SDXC_REG_FUNS	(0x44) /* SMC Function Select Register */
1d586d6
+#define SDXC_REG_CBCR	(0x48) /* SMC CIU Byte Count Register */
1d586d6
+#define SDXC_REG_BBCR	(0x4C) /* SMC BIU Byte Count Register */
1d586d6
+#define SDXC_REG_DBGC	(0x50) /* SMC Debug Enable Register */
1d586d6
+#define SDXC_REG_HWRST	(0x78) /* SMC Card Hardware Reset for Register */
1d586d6
+#define SDXC_REG_DMAC	(0x80) /* SMC IDMAC Control Register */
1d586d6
+#define SDXC_REG_DLBA	(0x84) /* SMC IDMAC Descriptor List Base Addre */
1d586d6
+#define SDXC_REG_IDST	(0x88) /* SMC IDMAC Status Register */
1d586d6
+#define SDXC_REG_IDIE	(0x8C) /* SMC IDMAC Interrupt Enable Register */
1d586d6
+#define SDXC_REG_CHDA	(0x90)
1d586d6
+#define SDXC_REG_CBDA	(0x94)
1d586d6
+
1d586d6
+#define mci_readl(host, reg) \
1d586d6
+	readl((host)->reg_base + SDXC_##reg)
1d586d6
+#define mci_writel(host, reg, value) \
1d586d6
+	writel((value), (host)->reg_base + SDXC_##reg)
1d586d6
+
1d586d6
+/* global control register bits */
1d586d6
+#define SDXC_SOFT_RESET			BIT(0)
1d586d6
+#define SDXC_FIFO_RESET			BIT(1)
1d586d6
+#define SDXC_DMA_RESET			BIT(2)
1d586d6
+#define SDXC_INTERRUPT_ENABLE_BIT	BIT(4)
1d586d6
+#define SDXC_DMA_ENABLE_BIT		BIT(5)
1d586d6
+#define SDXC_DEBOUNCE_ENABLE_BIT	BIT(8)
1d586d6
+#define SDXC_POSEDGE_LATCH_DATA		BIT(9)
1d586d6
+#define SDXC_DDR_MODE			BIT(10)
1d586d6
+#define SDXC_MEMORY_ACCESS_DONE		BIT(29)
1d586d6
+#define SDXC_ACCESS_DONE_DIRECT		BIT(30)
1d586d6
+#define SDXC_ACCESS_BY_AHB		BIT(31)
1d586d6
+#define SDXC_ACCESS_BY_DMA		(0 << 31)
1d586d6
+#define SDXC_HARDWARE_RESET \
1d586d6
+	(SDXC_SOFT_RESET | SDXC_FIFO_RESET | SDXC_DMA_RESET)
1d586d6
+
1d586d6
+/* clock control bits */
1d586d6
+#define SDXC_CARD_CLOCK_ON		BIT(16)
1d586d6
+#define SDXC_LOW_POWER_ON		BIT(17)
1d586d6
+
1d586d6
+/* bus width */
1d586d6
+#define SDXC_WIDTH1			0
1d586d6
+#define SDXC_WIDTH4			1
1d586d6
+#define SDXC_WIDTH8			2
1d586d6
+
1d586d6
+/* smc command bits */
1d586d6
+#define SDXC_RESP_EXPIRE		BIT(6)
1d586d6
+#define SDXC_LONG_RESPONSE		BIT(7)
1d586d6
+#define SDXC_CHECK_RESPONSE_CRC		BIT(8)
1d586d6
+#define SDXC_DATA_EXPIRE		BIT(9)
1d586d6
+#define SDXC_WRITE			BIT(10)
1d586d6
+#define SDXC_SEQUENCE_MODE		BIT(11)
1d586d6
+#define SDXC_SEND_AUTO_STOP		BIT(12)
1d586d6
+#define SDXC_WAIT_PRE_OVER		BIT(13)
1d586d6
+#define SDXC_STOP_ABORT_CMD		BIT(14)
1d586d6
+#define SDXC_SEND_INIT_SEQUENCE		BIT(15)
1d586d6
+#define SDXC_UPCLK_ONLY			BIT(21)
1d586d6
+#define SDXC_READ_CEATA_DEV		BIT(22)
1d586d6
+#define SDXC_CCS_EXPIRE			BIT(23)
1d586d6
+#define SDXC_ENABLE_BIT_BOOT		BIT(24)
1d586d6
+#define SDXC_ALT_BOOT_OPTIONS		BIT(25)
1d586d6
+#define SDXC_BOOT_ACK_EXPIRE		BIT(26)
1d586d6
+#define SDXC_BOOT_ABORT			BIT(27)
1d586d6
+#define SDXC_VOLTAGE_SWITCH	        BIT(28)
1d586d6
+#define SDXC_USE_HOLD_REGISTER	        BIT(29)
1d586d6
+#define SDXC_START			BIT(31)
1d586d6
+
1d586d6
+/* interrupt bits */
1d586d6
+#define SDXC_RESP_ERROR			BIT(1)
1d586d6
+#define SDXC_COMMAND_DONE		BIT(2)
1d586d6
+#define SDXC_DATA_OVER			BIT(3)
1d586d6
+#define SDXC_TX_DATA_REQUEST		BIT(4)
1d586d6
+#define SDXC_RX_DATA_REQUEST		BIT(5)
1d586d6
+#define SDXC_RESP_CRC_ERROR		BIT(6)
1d586d6
+#define SDXC_DATA_CRC_ERROR		BIT(7)
1d586d6
+#define SDXC_RESP_TIMEOUT		BIT(8)
1d586d6
+#define SDXC_DATA_TIMEOUT		BIT(9)
1d586d6
+#define SDXC_VOLTAGE_CHANGE_DONE	BIT(10)
1d586d6
+#define SDXC_FIFO_RUN_ERROR		BIT(11)
1d586d6
+#define SDXC_HARD_WARE_LOCKED		BIT(12)
1d586d6
+#define SDXC_START_BIT_ERROR		BIT(13)
1d586d6
+#define SDXC_AUTO_COMMAND_DONE		BIT(14)
1d586d6
+#define SDXC_END_BIT_ERROR		BIT(15)
1d586d6
+#define SDXC_SDIO_INTERRUPT		BIT(16)
1d586d6
+#define SDXC_CARD_INSERT		BIT(30)
1d586d6
+#define SDXC_CARD_REMOVE		BIT(31)
1d586d6
+#define SDXC_INTERRUPT_ERROR_BIT \
1d586d6
+	(SDXC_RESP_ERROR | SDXC_RESP_CRC_ERROR | SDXC_DATA_CRC_ERROR | \
1d586d6
+	 SDXC_RESP_TIMEOUT | SDXC_DATA_TIMEOUT | SDXC_FIFO_RUN_ERROR | \
1d586d6
+	 SDXC_HARD_WARE_LOCKED | SDXC_START_BIT_ERROR | SDXC_END_BIT_ERROR)
1d586d6
+#define SDXC_INTERRUPT_DONE_BIT \
1d586d6
+	(SDXC_AUTO_COMMAND_DONE | SDXC_DATA_OVER | \
1d586d6
+	 SDXC_COMMAND_DONE | SDXC_VOLTAGE_CHANGE_DONE)
1d586d6
+
1d586d6
+/* status */
1d586d6
+#define SDXC_RXWL_FLAG			BIT(0)
1d586d6
+#define SDXC_TXWL_FLAG			BIT(1)
1d586d6
+#define SDXC_FIFO_EMPTY			BIT(2)
1d586d6
+#define SDXC_FIFO_FULL			BIT(3)
1d586d6
+#define SDXC_CARD_PRESENT		BIT(8)
1d586d6
+#define SDXC_CARD_DATA_BUSY		BIT(9)
1d586d6
+#define SDXC_DATA_FSM_BUSY		BIT(10)
1d586d6
+#define SDXC_DMA_REQUEST		BIT(31)
1d586d6
+#define SDXC_FIFO_SIZE			16
1d586d6
+
1d586d6
+/* Function select */
1d586d6
+#define SDXC_CEATA_ON			(0xceaa << 16)
1d586d6
+#define SDXC_SEND_IRQ_RESPONSE		BIT(0)
1d586d6
+#define SDXC_SDIO_READ_WAIT		BIT(1)
1d586d6
+#define SDXC_ABORT_READ_DATA		BIT(2)
1d586d6
+#define SDXC_SEND_CCSD			BIT(8)
1d586d6
+#define SDXC_SEND_AUTO_STOPCCSD		BIT(9)
1d586d6
+#define SDXC_CEATA_DEV_IRQ_ENABLE	BIT(10)
1d586d6
+
1d586d6
+/* IDMA controller bus mod bit field */
1d586d6
+#define SDXC_IDMAC_SOFT_RESET		BIT(0)
1d586d6
+#define SDXC_IDMAC_FIX_BURST		BIT(1)
1d586d6
+#define SDXC_IDMAC_IDMA_ON		BIT(7)
1d586d6
+#define SDXC_IDMAC_REFETCH_DES		BIT(31)
1d586d6
+
1d586d6
+/* IDMA status bit field */
1d586d6
+#define SDXC_IDMAC_TRANSMIT_INTERRUPT		BIT(0)
1d586d6
+#define SDXC_IDMAC_RECEIVE_INTERRUPT		BIT(1)
1d586d6
+#define SDXC_IDMAC_FATAL_BUS_ERROR		BIT(2)
1d586d6
+#define SDXC_IDMAC_DESTINATION_INVALID		BIT(4)
1d586d6
+#define SDXC_IDMAC_CARD_ERROR_SUM		BIT(5)
1d586d6
+#define SDXC_IDMAC_NORMAL_INTERRUPT_SUM		BIT(8)
1d586d6
+#define SDXC_IDMAC_ABNORMAL_INTERRUPT_SUM	BIT(9)
1d586d6
+#define SDXC_IDMAC_HOST_ABORT_INTERRUPT		BIT(10)
1d586d6
+#define SDXC_IDMAC_IDLE				(0 << 13)
1d586d6
+#define SDXC_IDMAC_SUSPEND			(1 << 13)
1d586d6
+#define SDXC_IDMAC_DESC_READ			(2 << 13)
1d586d6
+#define SDXC_IDMAC_DESC_CHECK			(3 << 13)
1d586d6
+#define SDXC_IDMAC_READ_REQUEST_WAIT		(4 << 13)
1d586d6
+#define SDXC_IDMAC_WRITE_REQUEST_WAIT		(5 << 13)
1d586d6
+#define SDXC_IDMAC_READ				(6 << 13)
1d586d6
+#define SDXC_IDMAC_WRITE			(7 << 13)
1d586d6
+#define SDXC_IDMAC_DESC_CLOSE			(8 << 13)
1d586d6
+
1d586d6
+/*
1d586d6
+* If the idma-des-size-bits of property is ie 13, bufsize bits are:
1d586d6
+*  Bits  0-12: buf1 size
1d586d6
+*  Bits 13-25: buf2 size
1d586d6
+*  Bits 26-31: not used
1d586d6
+* Since we only ever set buf1 size, we can simply store it directly.
1d586d6
+*/
1d586d6
+#define SDXC_IDMAC_DES0_DIC	BIT(1)  /* disable interrupt on completion */
1d586d6
+#define SDXC_IDMAC_DES0_LD	BIT(2)  /* last descriptor */
1d586d6
+#define SDXC_IDMAC_DES0_FD	BIT(3)  /* first descriptor */
1d586d6
+#define SDXC_IDMAC_DES0_CH	BIT(4)  /* chain mode */
1d586d6
+#define SDXC_IDMAC_DES0_ER	BIT(5)  /* end of ring */
1d586d6
+#define SDXC_IDMAC_DES0_CES	BIT(30) /* card error summary */
1d586d6
+#define SDXC_IDMAC_DES0_OWN	BIT(31) /* 1-idma owns it, 0-host owns it */
1d586d6
+
1d586d6
+struct sunxi_idma_des {
1d586d6
+	u32	config;
1d586d6
+	u32	buf_size;
1d586d6
+	u32	buf_addr_ptr1;
1d586d6
+	u32	buf_addr_ptr2;
1d586d6
+};
1d586d6
+
1d586d6
+struct sunxi_mmc_host {
1d586d6
+	struct mmc_host	*mmc;
1d586d6
+	struct regulator *vmmc;
1d586d6
+	struct reset_control *reset;
1d586d6
+
1d586d6
+	/* IO mapping base */
1d586d6
+	void __iomem	*reg_base;
1d586d6
+
1d586d6
+	spinlock_t	lock;
1d586d6
+	struct tasklet_struct manual_stop_tasklet;
1d586d6
+
1d586d6
+	/* clock management */
1d586d6
+	struct clk	*clk_ahb;
1d586d6
+	struct clk	*clk_mod;
1d586d6
+
1d586d6
+	/* ios information */
1d586d6
+	u32		clk_mod_rate;
1d586d6
+	u32		bus_width;
1d586d6
+	u32		idma_des_size_bits;
1d586d6
+	u32		ddr;
1d586d6
+	u32		voltage_switching;
1d586d6
+
1d586d6
+	/* irq */
1d586d6
+	int		irq;
1d586d6
+	u32		int_sum;
1d586d6
+	u32		sdio_imask;
1d586d6
+
1d586d6
+	/* flags */
1d586d6
+	bool		wait_dma;
1d586d6
+
1d586d6
+	dma_addr_t	sg_dma;
1d586d6
+	void		*sg_cpu;
1d586d6
+
1d586d6
+	struct mmc_request *mrq;
1d586d6
+	struct mmc_request *manual_stop_mrq;
1d586d6
+	u32		ferror;
1d586d6
+};
1d586d6
+
1d586d6
+static int sunxi_mmc_init_host(struct mmc_host *mmc)
1d586d6
+{
1d586d6
+	u32 rval;
1d586d6
+	struct sunxi_mmc_host *smc_host = mmc_priv(mmc);
1d586d6
+	int ret;
1d586d6
+
1d586d6
+	ret =  clk_prepare_enable(smc_host->clk_ahb);
1d586d6
+	if (ret) {
1d586d6
+		dev_err(mmc_dev(smc_host->mmc), "AHB clk err %d\n", ret);
1d586d6
+		return ret;
1d586d6
+	}
1d586d6
+
1d586d6
+	ret =  clk_prepare_enable(smc_host->clk_mod);
1d586d6
+	if (ret) {
1d586d6
+		dev_err(mmc_dev(smc_host->mmc), "MOD clk err %d\n", ret);
1d586d6
+		clk_disable_unprepare(smc_host->clk_ahb);
1d586d6
+		return ret;
1d586d6
+	}
1d586d6
+
1d586d6
+	if (smc_host->reset) {
1d586d6
+		ret = reset_control_deassert(smc_host->reset);
1d586d6
+		if (ret) {
1d586d6
+			dev_err(mmc_dev(smc_host->mmc), "reset err %d\n", ret);
1d586d6
+			clk_disable_unprepare(smc_host->clk_ahb);
1d586d6
+			clk_disable_unprepare(smc_host->clk_mod);
1d586d6
+			return ret;
1d586d6
+		}
1d586d6
+	}
1d586d6
+
1d586d6
+	/* reset controller */
1d586d6
+	rval = mci_readl(smc_host, REG_GCTRL);
1d586d6
+	rval |= SDXC_HARDWARE_RESET;
1d586d6
+	mci_writel(smc_host, REG_GCTRL, rval);
1d586d6
+
1d586d6
+	mci_writel(smc_host, REG_FTRGL, 0x20070008);
1d586d6
+	mci_writel(smc_host, REG_TMOUT, 0xffffffff);
1d586d6
+	mci_writel(smc_host, REG_IMASK, smc_host->sdio_imask);
1d586d6
+	mci_writel(smc_host, REG_RINTR, 0xffffffff);
1d586d6
+	mci_writel(smc_host, REG_DBGC, 0xdeb);
1d586d6
+	mci_writel(smc_host, REG_FUNS, SDXC_CEATA_ON);
1d586d6
+	mci_writel(smc_host, REG_DLBA, smc_host->sg_dma);
1d586d6
+
1d586d6
+	rval = mci_readl(smc_host, REG_GCTRL);
1d586d6
+	rval |= SDXC_INTERRUPT_ENABLE_BIT;
1d586d6
+	rval &= ~SDXC_ACCESS_DONE_DIRECT;
1d586d6
+	mci_writel(smc_host, REG_GCTRL, rval);
1d586d6
+
1d586d6
+	return 0;
1d586d6
+}
1d586d6
+
1d586d6
+static void sunxi_mmc_exit_host(struct sunxi_mmc_host *smc_host)
1d586d6
+{
1d586d6
+	mci_writel(smc_host, REG_GCTRL, SDXC_HARDWARE_RESET);
1d586d6
+
1d586d6
+	if (smc_host->reset)
1d586d6
+		reset_control_assert(smc_host->reset);
1d586d6
+
1d586d6
+	clk_disable_unprepare(smc_host->clk_ahb);
1d586d6
+	clk_disable_unprepare(smc_host->clk_mod);
1d586d6
+}
1d586d6
+
1d586d6
+/* /\* UHS-I Operation Modes */
1d586d6
+/*  * DS		25MHz	12.5MB/s	3.3V */
1d586d6
+/*  * HS		50MHz	25MB/s		3.3V */
1d586d6
+/*  * SDR12	25MHz	12.5MB/s	1.8V */
1d586d6
+/*  * SDR25	50MHz	25MB/s		1.8V */
1d586d6
+/*  * SDR50	100MHz	50MB/s		1.8V */
1d586d6
+/*  * SDR104	208MHz	104MB/s		1.8V */
1d586d6
+/*  * DDR50	50MHz	50MB/s		1.8V */
1d586d6
+/*  * MMC Operation Modes */
1d586d6
+/*  * DS		26MHz	26MB/s		3/1.8/1.2V */
1d586d6
+/*  * HS		52MHz	52MB/s		3/1.8/1.2V */
1d586d6
+/*  * HSDDR	52MHz	104MB/s		3/1.8/1.2V */
1d586d6
+/*  * HS200	200MHz	200MB/s		1.8/1.2V */
1d586d6
+/*  * */
1d586d6
+/*  * Spec. Timing */
1d586d6
+/*  * SD3.0 */
1d586d6
+/*  * Fcclk    Tcclk   Fsclk   Tsclk   Tis     Tih     odly  RTis     RTih */
1d586d6
+/*  * 400K     2.5us   24M     41ns    5ns     5ns     1     2209ns   41ns */
1d586d6
+/*  * 25M      40ns    600M    1.67ns  5ns     5ns     3     14.99ns  5.01ns */
1d586d6
+/*  * 50M      20ns    600M    1.67ns  6ns     2ns     3     14.99ns  5.01ns */
1d586d6
+/*  * 50MDDR   20ns    600M    1.67ns  6ns     0.8ns   2     6.67ns   3.33ns */
1d586d6
+/*  * 104M     9.6ns   600M    1.67ns  3ns     0.8ns   1     7.93ns   1.67ns */
1d586d6
+/*  * 208M     4.8ns   600M    1.67ns  1.4ns   0.8ns   1     3.33ns   1.67ns */
1d586d6
+
1d586d6
+/*  * 25M      40ns    300M    3.33ns  5ns     5ns     2     13.34ns   6.66ns */
1d586d6
+/*  * 50M      20ns    300M    3.33ns  6ns     2ns     2     13.34ns   6.66ns */
1d586d6
+/*  * 50MDDR   20ns    300M    3.33ns  6ns     0.8ns   1     6.67ns    3.33ns */
1d586d6
+/*  * 104M     9.6ns   300M    3.33ns  3ns     0.8ns   0     7.93ns    1.67ns */
1d586d6
+/*  * 208M     4.8ns   300M    3.33ns  1.4ns   0.8ns   0     3.13ns    1.67ns */
1d586d6
+
1d586d6
+/*  * eMMC4.5 */
1d586d6
+/*  * 400K     2.5us   24M     41ns    3ns     3ns     1     2209ns    41ns */
1d586d6
+/*  * 25M      40ns    600M    1.67ns  3ns     3ns     3     14.99ns   5.01ns */
1d586d6
+/*  * 50M      20ns    600M    1.67ns  3ns     3ns     3     14.99ns   5.01ns */
1d586d6
+/*  * 50MDDR   20ns    600M    1.67ns  2.5ns   2.5ns   2     6.67ns    3.33ns */
1d586d6
+/*  * 200M     5ns     600M    1.67ns  1.4ns   0.8ns   1     3.33ns    1.67ns */
1d586d6
+/*  *\/ */
1d586d6
+
1d586d6
+static void sunxi_mmc_init_idma_des(struct sunxi_mmc_host *host,
1d586d6
+				    struct mmc_data *data)
1d586d6
+{
1d586d6
+	struct sunxi_idma_des *pdes = (struct sunxi_idma_des *)host->sg_cpu;
1d586d6
+	struct sunxi_idma_des *pdes_pa = (struct sunxi_idma_des *)host->sg_dma;
1d586d6
+	int i, max_len = (1 << host->idma_des_size_bits);
1d586d6
+
1d586d6
+	for (i = 0; i < data->sg_len; i++) {
1d586d6
+		pdes[i].config = SDXC_IDMAC_DES0_CH | SDXC_IDMAC_DES0_OWN |
1d586d6
+				 SDXC_IDMAC_DES0_DIC;
1d586d6
+
1d586d6
+		if (data->sg[i].length == max_len)
1d586d6
+			pdes[i].buf_size = 0; /* 0 == max_len */
1d586d6
+		else
1d586d6
+			pdes[i].buf_size = data->sg[i].length;
1d586d6
+
1d586d6
+		pdes[i].buf_addr_ptr1 = sg_dma_address(&data->sg[i]);
1d586d6
+		pdes[i].buf_addr_ptr2 = (u32)&pdes_pa[i + 1];
1d586d6
+	}
1d586d6
+
1d586d6
+	pdes[0].config |= SDXC_IDMAC_DES0_FD;
1d586d6
+	pdes[i - 1].config = SDXC_IDMAC_DES0_OWN | SDXC_IDMAC_DES0_LD;
1d586d6
+
1d586d6
+	/*
1d586d6
+	 * Avoid the io-store starting the idmac hitting io-mem before the
1d586d6
+	 * descriptors hit the main-mem.
1d586d6
+	 */
1d586d6
+	wmb();
1d586d6
+}
1d586d6
+
1d586d6
+static enum dma_data_direction sunxi_mmc_get_dma_dir(struct mmc_data *data)
1d586d6
+{
1d586d6
+	if (data->flags & MMC_DATA_WRITE)
1d586d6
+		return DMA_TO_DEVICE;
1d586d6
+	else
1d586d6
+		return DMA_FROM_DEVICE;
1d586d6
+}
1d586d6
+
1d586d6
+static int sunxi_mmc_map_dma(struct sunxi_mmc_host *smc_host,
1d586d6
+			     struct mmc_data *data)
1d586d6
+{
1d586d6
+	u32 i, dma_len;
1d586d6
+	struct scatterlist *sg;
1d586d6
+
1d586d6
+	dma_len = dma_map_sg(mmc_dev(smc_host->mmc), data->sg, data->sg_len,
1d586d6
+			     sunxi_mmc_get_dma_dir(data));
1d586d6
+	if (dma_len == 0) {
1d586d6
+		dev_err(mmc_dev(smc_host->mmc), "dma_map_sg failed\n");
1d586d6
+		return -ENOMEM;
1d586d6
+	}
1d586d6
+
1d586d6
+	for_each_sg(data->sg, sg, data->sg_len, i) {
1d586d6
+		if (sg->offset & 3 || sg->length & 3) {
1d586d6
+			dev_err(mmc_dev(smc_host->mmc),
1d586d6
+				"unaligned scatterlist: os %x length %d\n",
1d586d6
+				sg->offset, sg->length);
1d586d6
+			return -EINVAL;
1d586d6
+		}
1d586d6
+	}
1d586d6
+
1d586d6
+	return 0;
1d586d6
+}
1d586d6
+
1d586d6
+static void sunxi_mmc_start_dma(struct sunxi_mmc_host *smc_host,
1d586d6
+				struct mmc_data *data)
1d586d6
+{
1d586d6
+	u32 rval;
1d586d6
+
1d586d6
+	sunxi_mmc_init_idma_des(smc_host, data);
1d586d6
+
1d586d6
+	rval = mci_readl(smc_host, REG_GCTRL);
1d586d6
+	rval |= SDXC_DMA_ENABLE_BIT;
1d586d6
+	mci_writel(smc_host, REG_GCTRL, rval);
1d586d6
+	rval |= SDXC_DMA_RESET;
1d586d6
+	mci_writel(smc_host, REG_GCTRL, rval);
1d586d6
+
1d586d6
+	mci_writel(smc_host, REG_DMAC, SDXC_IDMAC_SOFT_RESET);
1d586d6
+
1d586d6
+	if (!(data->flags & MMC_DATA_WRITE))
1d586d6
+		mci_writel(smc_host, REG_IDIE, SDXC_IDMAC_RECEIVE_INTERRUPT);
1d586d6
+
1d586d6
+	mci_writel(smc_host, REG_DMAC,
1d586d6
+		   SDXC_IDMAC_FIX_BURST | SDXC_IDMAC_IDMA_ON);
1d586d6
+}
1d586d6
+
1d586d6
+static void sunxi_mmc_send_manual_stop(struct sunxi_mmc_host *host,
1d586d6
+				       struct mmc_request *req)
1d586d6
+{
1d586d6
+	u32 cmd_val = SDXC_START | SDXC_RESP_EXPIRE | SDXC_STOP_ABORT_CMD
1d586d6
+			| SDXC_CHECK_RESPONSE_CRC | MMC_STOP_TRANSMISSION;
1d586d6
+	u32 ri = 0;
1d586d6
+	unsigned long expire = jiffies + msecs_to_jiffies(1000);
1d586d6
+
1d586d6
+	mci_writel(host, REG_CARG, 0);
1d586d6
+	mci_writel(host, REG_CMDR, cmd_val);
1d586d6
+
1d586d6
+	do {
1d586d6
+		ri = mci_readl(host, REG_RINTR);
1d586d6
+	} while (!(ri & (SDXC_COMMAND_DONE | SDXC_INTERRUPT_ERROR_BIT)) &&
1d586d6
+		 time_before(jiffies, expire));
1d586d6
+
1d586d6
+	if (ri & SDXC_INTERRUPT_ERROR_BIT) {
1d586d6
+		dev_err(mmc_dev(host->mmc), "send stop command failed\n");
1d586d6
+		if (req->stop)
1d586d6
+			req->stop->resp[0] = -ETIMEDOUT;
1d586d6
+	} else {
1d586d6
+		if (req->stop)
1d586d6
+			req->stop->resp[0] = mci_readl(host, REG_RESP0);
1d586d6
+	}
1d586d6
+
1d586d6
+	mci_writel(host, REG_RINTR, 0xffff);
1d586d6
+}
1d586d6
+
1d586d6
+static void sunxi_mmc_dump_errinfo(struct sunxi_mmc_host *smc_host)
1d586d6
+{
1d586d6
+	struct mmc_command *cmd = smc_host->mrq->cmd;
1d586d6
+	struct mmc_data *data = smc_host->mrq->data;
1d586d6
+
1d586d6
+	/* For some cmds timeout is normal with sd/mmc cards */
1d586d6
+	if ((smc_host->int_sum & SDXC_INTERRUPT_ERROR_BIT) ==
1d586d6
+		SDXC_RESP_TIMEOUT && (cmd->opcode == SD_IO_SEND_OP_COND ||
1d586d6
+				      cmd->opcode == SD_IO_RW_DIRECT))
1d586d6
+		return;
1d586d6
+
1d586d6
+	dev_err(mmc_dev(smc_host->mmc),
1d586d6
+		"smc %d err, cmd %d,%s%s%s%s%s%s%s%s%s%s !!\n",
1d586d6
+		smc_host->mmc->index, cmd->opcode,
1d586d6
+		data ? (data->flags & MMC_DATA_WRITE ? " WR" : " RD") : "",
1d586d6
+		smc_host->int_sum & SDXC_RESP_ERROR     ? " RE"     : "",
1d586d6
+		smc_host->int_sum & SDXC_RESP_CRC_ERROR  ? " RCE"    : "",
1d586d6
+		smc_host->int_sum & SDXC_DATA_CRC_ERROR  ? " DCE"    : "",
1d586d6
+		smc_host->int_sum & SDXC_RESP_TIMEOUT ? " RTO"    : "",
1d586d6
+		smc_host->int_sum & SDXC_DATA_TIMEOUT ? " DTO"    : "",
1d586d6
+		smc_host->int_sum & SDXC_FIFO_RUN_ERROR  ? " FE"     : "",
1d586d6
+		smc_host->int_sum & SDXC_HARD_WARE_LOCKED ? " HL"     : "",
1d586d6
+		smc_host->int_sum & SDXC_START_BIT_ERROR ? " SBE"    : "",
1d586d6
+		smc_host->int_sum & SDXC_END_BIT_ERROR   ? " EBE"    : ""
1d586d6
+		);
1d586d6
+}
1d586d6
+
1d586d6
+/* Called in interrupt context! */
1d586d6
+static int sunxi_mmc_finalize_request(struct sunxi_mmc_host *host)
1d586d6
+{
1d586d6
+	struct mmc_request *mrq = host->mrq;
1d586d6
+
1d586d6
+	mci_writel(host, REG_IMASK, host->sdio_imask);
1d586d6
+	mci_writel(host, REG_IDIE, 0);
1d586d6
+
1d586d6
+	if (host->int_sum & SDXC_INTERRUPT_ERROR_BIT) {
1d586d6
+		sunxi_mmc_dump_errinfo(host);
1d586d6
+		mrq->cmd->error = -ETIMEDOUT;
1d586d6
+
1d586d6
+		if (mrq->data)
1d586d6
+			mrq->data->error = -ETIMEDOUT;
1d586d6
+
1d586d6
+		if (mrq->stop)
1d586d6
+			mrq->stop->error = -ETIMEDOUT;
1d586d6
+	} else {
1d586d6
+		if (mrq->cmd->flags & MMC_RSP_136) {
1d586d6
+			mrq->cmd->resp[0] = mci_readl(host, REG_RESP3);
1d586d6
+			mrq->cmd->resp[1] = mci_readl(host, REG_RESP2);
1d586d6
+			mrq->cmd->resp[2] = mci_readl(host, REG_RESP1);
1d586d6
+			mrq->cmd->resp[3] = mci_readl(host, REG_RESP0);
1d586d6
+		} else {
1d586d6
+			mrq->cmd->resp[0] = mci_readl(host, REG_RESP0);
1d586d6
+		}
1d586d6
+
1d586d6
+		if (mrq->data)
1d586d6
+			mrq->data->bytes_xfered =
1d586d6
+				mrq->data->blocks * mrq->data->blksz;
1d586d6
+	}
1d586d6
+
1d586d6
+	if (mrq->data) {
1d586d6
+		struct mmc_data *data = mrq->data;
1d586d6
+		u32 rval;
1d586d6
+
1d586d6
+		mci_writel(host, REG_IDST, 0x337);
1d586d6
+		mci_writel(host, REG_DMAC, 0);
1d586d6
+		rval = mci_readl(host, REG_GCTRL);
1d586d6
+		rval |= SDXC_DMA_RESET;
1d586d6
+		mci_writel(host, REG_GCTRL, rval);
1d586d6
+		rval &= ~SDXC_DMA_ENABLE_BIT;
1d586d6
+		mci_writel(host, REG_GCTRL, rval);
1d586d6
+		rval |= SDXC_FIFO_RESET;
1d586d6
+		mci_writel(host, REG_GCTRL, rval);
1d586d6
+		dma_unmap_sg(mmc_dev(host->mmc), data->sg, data->sg_len,
1d586d6
+				     sunxi_mmc_get_dma_dir(data));
1d586d6
+	}
1d586d6
+
1d586d6
+	mci_writel(host, REG_RINTR, 0xffff);
1d586d6
+
1d586d6
+	dev_dbg(mmc_dev(host->mmc), "req done, resp %08x %08x %08x %08x\n",
1d586d6
+		mrq->cmd->resp[0], mrq->cmd->resp[1],
1d586d6
+		mrq->cmd->resp[2], mrq->cmd->resp[3]);
1d586d6
+
1d586d6
+	host->mrq = NULL;
1d586d6
+	host->int_sum = 0;
1d586d6
+	host->wait_dma = false;
1d586d6
+
1d586d6
+	if (mrq->data && mrq->data->error) {
1d586d6
+		host->manual_stop_mrq = mrq;
1d586d6
+		tasklet_schedule(&host->manual_stop_tasklet);
1d586d6
+		return -EBUSY;
1d586d6
+	}
1d586d6
+
1d586d6
+	return 0;
1d586d6
+}
1d586d6
+
1d586d6
+static irqreturn_t sunxi_mmc_irq(int irq, void *dev_id)
1d586d6
+{
1d586d6
+	struct sunxi_mmc_host *host = dev_id;
1d586d6
+	struct mmc_request *mrq;
1d586d6
+	bool finalize = false;
1d586d6
+	bool complete = false;
1d586d6
+	bool sdio_int = false;
1d586d6
+	u32 msk_int;
1d586d6
+	u32 idma_int;
1d586d6
+
1d586d6
+	spin_lock(&host->lock);
1d586d6
+
1d586d6
+	idma_int  = mci_readl(host, REG_IDST);
1d586d6
+	msk_int   = mci_readl(host, REG_MISTA);
1d586d6
+
1d586d6
+	dev_dbg(mmc_dev(host->mmc), "irq: rq %p mi %08x idi %08x\n",
1d586d6
+		host->mrq, msk_int, idma_int);
1d586d6
+
1d586d6
+	mrq = host->mrq;
1d586d6
+	if (mrq) {
1d586d6
+		if (idma_int & SDXC_IDMAC_RECEIVE_INTERRUPT)
1d586d6
+			host->wait_dma = false;
1d586d6
+
1d586d6
+		host->int_sum |= msk_int;
1d586d6
+
1d586d6
+		/* Wait for COMMAND_DONE on RESPONSE_TIMEOUT before finalize */
1d586d6
+		if ((host->int_sum & SDXC_RESP_TIMEOUT) &&
1d586d6
+				!(host->int_sum & SDXC_COMMAND_DONE))
1d586d6
+			mci_writel(host, REG_IMASK,
1d586d6
+				   host->sdio_imask | SDXC_COMMAND_DONE);
1d586d6
+		/* Don't wait for dma on error */
1d586d6
+		else if (host->int_sum & SDXC_INTERRUPT_ERROR_BIT)
1d586d6
+			finalize = true;
1d586d6
+		else if ((host->int_sum & SDXC_INTERRUPT_DONE_BIT) &&
1d586d6
+				!host->wait_dma)
1d586d6
+			finalize = true;
1d586d6
+	}
1d586d6
+
1d586d6
+	if (msk_int & SDXC_SDIO_INTERRUPT)
1d586d6
+		sdio_int = true;
1d586d6
+
1d586d6
+	mci_writel(host, REG_RINTR, msk_int);
1d586d6
+	mci_writel(host, REG_IDST, idma_int);
1d586d6
+
1d586d6
+	if (finalize) {
1d586d6
+		if (sunxi_mmc_finalize_request(host) == 0)
1d586d6
+			complete = true;
1d586d6
+	}
1d586d6
+
1d586d6
+	spin_unlock(&host->lock);
1d586d6
+
1d586d6
+	if (complete)
1d586d6
+		mmc_request_done(host->mmc, mrq);
1d586d6
+
1d586d6
+	if (sdio_int)
1d586d6
+		mmc_signal_sdio_irq(host->mmc);
1d586d6
+
1d586d6
+	return IRQ_HANDLED;
1d586d6
+}
1d586d6
+
1d586d6
+static void sunxi_mmc_manual_stop_tasklet(unsigned long data)
1d586d6
+{
1d586d6
+	struct sunxi_mmc_host *host = (struct sunxi_mmc_host *) data;
1d586d6
+	struct mmc_request *mrq;
1d586d6
+	unsigned long iflags;
1d586d6
+
1d586d6
+	spin_lock_irqsave(&host->lock, iflags);
1d586d6
+	mrq = host->manual_stop_mrq;
1d586d6
+	spin_unlock_irqrestore(&host->lock, iflags);
1d586d6
+
1d586d6
+	if (!mrq) {
1d586d6
+		dev_err(mmc_dev(host->mmc), "no request for manual stop\n");
1d586d6
+		return;
1d586d6
+	}
1d586d6
+
1d586d6
+	dev_err(mmc_dev(host->mmc), "data error, sending stop command\n");
1d586d6
+	sunxi_mmc_send_manual_stop(host, mrq);
1d586d6
+
1d586d6
+	spin_lock_irqsave(&host->lock, iflags);
1d586d6
+	host->manual_stop_mrq = NULL;
1d586d6
+	spin_unlock_irqrestore(&host->lock, iflags);
1d586d6
+
1d586d6
+	mmc_request_done(host->mmc, mrq);
1d586d6
+}
1d586d6
+
1d586d6
+static void sunxi_mmc_oclk_onoff(struct sunxi_mmc_host *host, u32 oclk_en)
1d586d6
+{
1d586d6
+	unsigned long expire = jiffies + msecs_to_jiffies(2000);
1d586d6
+	u32 rval;
1d586d6
+
1d586d6
+	rval = mci_readl(host, REG_CLKCR);
1d586d6
+	rval &= ~(SDXC_CARD_CLOCK_ON | SDXC_LOW_POWER_ON);
1d586d6
+
1d586d6
+	if (oclk_en)
1d586d6
+		rval |= SDXC_CARD_CLOCK_ON;
1d586d6
+
1d586d6
+	mci_writel(host, REG_CLKCR, rval);
1d586d6
+
1d586d6
+	rval = SDXC_START | SDXC_UPCLK_ONLY | SDXC_WAIT_PRE_OVER;
1d586d6
+	if (host->voltage_switching)
1d586d6
+		rval |= SDXC_VOLTAGE_SWITCH;
1d586d6
+	mci_writel(host, REG_CMDR, rval);
1d586d6
+
1d586d6
+	do {
1d586d6
+		rval = mci_readl(host, REG_CMDR);
1d586d6
+	} while (time_before(jiffies, expire) && (rval & SDXC_START));
1d586d6
+
1d586d6
+	if (rval & SDXC_START) {
1d586d6
+		dev_err(mmc_dev(host->mmc), "fatal err update clk timeout\n");
1d586d6
+		host->ferror = 1;
1d586d6
+	}
1d586d6
+}
1d586d6
+
1d586d6
+static void sunxi_mmc_clk_set_rate(struct sunxi_mmc_host *smc_host,
1d586d6
+				   unsigned int rate)
1d586d6
+{
1d586d6
+	u32 newrate, oclk_dly, rval, sclk_dly, src_clk;
1d586d6
+	struct clk_hw *hw = __clk_get_hw(smc_host->clk_mod);
1d586d6
+
1d586d6
+	newrate = clk_round_rate(smc_host->clk_mod, rate);
1d586d6
+	if (smc_host->clk_mod_rate == newrate) {
1d586d6
+		dev_dbg(mmc_dev(smc_host->mmc), "clk already %d, rounded %d\n",
1d586d6
+			rate, newrate);
1d586d6
+		return;
1d586d6
+	}
1d586d6
+
1d586d6
+	dev_dbg(mmc_dev(smc_host->mmc), "setting clk to %d, rounded %d\n",
1d586d6
+		rate, newrate);
1d586d6
+
1d586d6
+	/* setting clock rate */
1d586d6
+	clk_set_rate(smc_host->clk_mod, newrate);
1d586d6
+	smc_host->clk_mod_rate = clk_get_rate(smc_host->clk_mod);
1d586d6
+	dev_dbg(mmc_dev(smc_host->mmc), "clk is now %d\n",
1d586d6
+		smc_host->clk_mod_rate);
1d586d6
+
1d586d6
+	sunxi_mmc_oclk_onoff(smc_host, 0);
1d586d6
+	/* clear internal divider */
1d586d6
+	rval = mci_readl(smc_host, REG_CLKCR);
1d586d6
+	rval &= ~0xff;
1d586d6
+	mci_writel(smc_host, REG_CLKCR, rval);
1d586d6
+
1d586d6
+	/* determine delays */
1d586d6
+	if (rate <= 400000) {
1d586d6
+		oclk_dly = 0;
1d586d6
+		sclk_dly = 7;
1d586d6
+	} else if (rate <= 25000000) {
1d586d6
+		oclk_dly = 0;
1d586d6
+		sclk_dly = 5;
1d586d6
+	} else if (rate <= 50000000) {
1d586d6
+		if (smc_host->ddr) {
1d586d6
+			oclk_dly = 2;
1d586d6
+			sclk_dly = 4;
1d586d6
+		} else {
1d586d6
+			oclk_dly = 3;
1d586d6
+			sclk_dly = 5;
1d586d6
+		}
1d586d6
+	} else {
1d586d6
+		/* rate > 50000000 */
1d586d6
+		oclk_dly = 2;
1d586d6
+		sclk_dly = 4;
1d586d6
+	}
1d586d6
+
1d586d6
+	src_clk = clk_get_rate(clk_get_parent(smc_host->clk_mod));
1d586d6
+	if (src_clk >= 300000000 && src_clk <= 400000000) {
1d586d6
+		if (oclk_dly)
1d586d6
+			oclk_dly--;
1d586d6
+		if (sclk_dly)
1d586d6
+			sclk_dly--;
1d586d6
+	}
1d586d6
+
1d586d6
+	clk_sunxi_mmc_phase_control(hw, sclk_dly, oclk_dly);
1d586d6
+	sunxi_mmc_oclk_onoff(smc_host, 1);
1d586d6
+
1d586d6
+	/* oclk_onoff sets various irq status bits, clear these */
1d586d6
+	mci_writel(smc_host, REG_RINTR,
1d586d6
+		   mci_readl(smc_host, REG_RINTR) & ~SDXC_SDIO_INTERRUPT);
1d586d6
+}
1d586d6
+
1d586d6
+static void sunxi_mmc_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
1d586d6
+{
1d586d6
+	struct sunxi_mmc_host *host = mmc_priv(mmc);
1d586d6
+	u32 rval;
1d586d6
+	s32 err;
1d586d6
+
1d586d6
+	/* Set the power state */
1d586d6
+	switch (ios->power_mode) {
1d586d6
+	case MMC_POWER_ON:
1d586d6
+		break;
1d586d6
+
1d586d6
+	case MMC_POWER_UP:
1d586d6
+		if (!IS_ERR(host->vmmc)) {
1d586d6
+			mmc_regulator_set_ocr(host->mmc, host->vmmc, ios->vdd);
1d586d6
+			udelay(200);
1d586d6
+		}
1d586d6
+
1d586d6
+		err = sunxi_mmc_init_host(mmc);
1d586d6
+		if (err) {
1d586d6
+			host->ferror = 1;
1d586d6
+			return;
1d586d6
+		}
1d586d6
+
1d586d6
+		enable_irq(host->irq);
1d586d6
+
1d586d6
+		dev_dbg(mmc_dev(host->mmc), "power on!\n");
1d586d6
+		host->ferror = 0;
1d586d6
+		break;
1d586d6
+
1d586d6
+	case MMC_POWER_OFF:
1d586d6
+		dev_dbg(mmc_dev(host->mmc), "power off!\n");
1d586d6
+		disable_irq(host->irq);
1d586d6
+		sunxi_mmc_exit_host(host);
1d586d6
+		if (!IS_ERR(host->vmmc))
1d586d6
+			mmc_regulator_set_ocr(host->mmc, host->vmmc, 0);
1d586d6
+
1d586d6
+		host->ferror = 0;
1d586d6
+		break;
1d586d6
+	}
1d586d6
+
1d586d6
+	/* set bus width */
1d586d6
+	switch (ios->bus_width) {
1d586d6
+	case MMC_BUS_WIDTH_1:
1d586d6
+		mci_writel(host, REG_WIDTH, SDXC_WIDTH1);
1d586d6
+		host->bus_width = 1;
1d586d6
+		break;
1d586d6
+	case MMC_BUS_WIDTH_4:
1d586d6
+		mci_writel(host, REG_WIDTH, SDXC_WIDTH4);
1d586d6
+		host->bus_width = 4;
1d586d6
+		break;
1d586d6
+	case MMC_BUS_WIDTH_8:
1d586d6
+		mci_writel(host, REG_WIDTH, SDXC_WIDTH8);
1d586d6
+		host->bus_width = 8;
1d586d6
+		break;
1d586d6
+	}
1d586d6
+
1d586d6
+	/* set ddr mode */
1d586d6
+	rval = mci_readl(host, REG_GCTRL);
1d586d6
+	if (ios->timing == MMC_TIMING_UHS_DDR50) {
1d586d6
+		rval |= SDXC_DDR_MODE;
1d586d6
+		host->ddr = 1;
1d586d6
+	} else {
1d586d6
+		rval &= ~SDXC_DDR_MODE;
1d586d6
+		host->ddr = 0;
1d586d6
+	}
1d586d6
+	mci_writel(host, REG_GCTRL, rval);
1d586d6
+
1d586d6
+	/* set up clock */
1d586d6
+	if (ios->clock && ios->power_mode) {
1d586d6
+		dev_dbg(mmc_dev(host->mmc), "ios->clock: %d\n", ios->clock);
1d586d6
+		sunxi_mmc_clk_set_rate(host, ios->clock);
1d586d6
+		usleep_range(50000, 55000);
1d586d6
+	}
1d586d6
+}
1d586d6
+
1d586d6
+static void sunxi_mmc_enable_sdio_irq(struct mmc_host *mmc, int enable)
1d586d6
+{
1d586d6
+	struct sunxi_mmc_host *smc_host = mmc_priv(mmc);
1d586d6
+	unsigned long flags;
1d586d6
+	u32 imask;
1d586d6
+
1d586d6
+	spin_lock_irqsave(&smc_host->lock, flags);
1d586d6
+
1d586d6
+	imask = mci_readl(smc_host, REG_IMASK);
1d586d6
+	if (enable) {
1d586d6
+		smc_host->sdio_imask = SDXC_SDIO_INTERRUPT;
1d586d6
+		imask |= SDXC_SDIO_INTERRUPT;
1d586d6
+	} else {
1d586d6
+		smc_host->sdio_imask = 0;
1d586d6
+		imask &= ~SDXC_SDIO_INTERRUPT;
1d586d6
+	}
1d586d6
+	mci_writel(smc_host, REG_IMASK, imask);
1d586d6
+	spin_unlock_irqrestore(&smc_host->lock, flags);
1d586d6
+}
1d586d6
+
1d586d6
+static void sunxi_mmc_hw_reset(struct mmc_host *mmc)
1d586d6
+{
1d586d6
+	struct sunxi_mmc_host *smc_host = mmc_priv(mmc);
1d586d6
+	mci_writel(smc_host, REG_HWRST, 0);
1d586d6
+	udelay(10);
1d586d6
+	mci_writel(smc_host, REG_HWRST, 1);
1d586d6
+	udelay(300);
1d586d6
+}
1d586d6
+
1d586d6
+static void sunxi_mmc_request(struct mmc_host *mmc, struct mmc_request *mrq)
1d586d6
+{
1d586d6
+	struct sunxi_mmc_host *host = mmc_priv(mmc);
1d586d6
+	struct mmc_command *cmd = mrq->cmd;
1d586d6
+	struct mmc_data *data = mrq->data;
1d586d6
+	unsigned long iflags;
1d586d6
+	u32 imask = SDXC_INTERRUPT_ERROR_BIT;
1d586d6
+	u32 cmd_val = SDXC_START | (cmd->opcode & 0x3f);
1d586d6
+	int ret;
1d586d6
+
1d586d6
+	if (!mmc_gpio_get_cd(mmc) || host->ferror) {
1d586d6
+		dev_dbg(mmc_dev(host->mmc), "no medium present\n");
1d586d6
+		mrq->cmd->error = -ENOMEDIUM;
1d586d6
+		mmc_request_done(mmc, mrq);
1d586d6
+		return;
1d586d6
+	}
1d586d6
+
1d586d6
+	if (data) {
1d586d6
+		ret = sunxi_mmc_map_dma(host, data);
1d586d6
+		if (ret < 0) {
1d586d6
+			dev_err(mmc_dev(host->mmc), "map DMA failed\n");
1d586d6
+			cmd->error = ret;
1d586d6
+			cmd->data->error = ret;
1d586d6
+			mmc_request_done(host->mmc, mrq);
1d586d6
+			return;
1d586d6
+		}
1d586d6
+	}
1d586d6
+
1d586d6
+	if (cmd->opcode == MMC_GO_IDLE_STATE) {
1d586d6
+		cmd_val |= SDXC_SEND_INIT_SEQUENCE;
1d586d6
+		imask |= SDXC_COMMAND_DONE;
1d586d6
+	}
1d586d6
+
1d586d6
+	if (cmd->opcode == SD_SWITCH_VOLTAGE) {
1d586d6
+		cmd_val |= SDXC_VOLTAGE_SWITCH;
1d586d6
+		imask |= SDXC_VOLTAGE_CHANGE_DONE;
1d586d6
+		host->voltage_switching = 1;
1d586d6
+		sunxi_mmc_oclk_onoff(host, 1);
1d586d6
+	}
1d586d6
+
1d586d6
+	if (cmd->flags & MMC_RSP_PRESENT) {
1d586d6
+		cmd_val |= SDXC_RESP_EXPIRE;
1d586d6
+		if (cmd->flags & MMC_RSP_136)
1d586d6
+			cmd_val |= SDXC_LONG_RESPONSE;
1d586d6
+		if (cmd->flags & MMC_RSP_CRC)
1d586d6
+			cmd_val |= SDXC_CHECK_RESPONSE_CRC;
1d586d6
+
1d586d6
+		if ((cmd->flags & MMC_CMD_MASK) == MMC_CMD_ADTC) {
1d586d6
+			cmd_val |= SDXC_DATA_EXPIRE | SDXC_WAIT_PRE_OVER;
1d586d6
+			if (cmd->data->flags & MMC_DATA_STREAM) {
1d586d6
+				imask |= SDXC_AUTO_COMMAND_DONE;
1d586d6
+				cmd_val |= SDXC_SEQUENCE_MODE |
1d586d6
+					   SDXC_SEND_AUTO_STOP;
1d586d6
+			}
1d586d6
+
1d586d6
+			if (cmd->data->stop) {
1d586d6
+				imask |= SDXC_AUTO_COMMAND_DONE;
1d586d6
+				cmd_val |= SDXC_SEND_AUTO_STOP;
1d586d6
+			} else {
1d586d6
+				imask |= SDXC_DATA_OVER;
1d586d6
+			}
1d586d6
+
1d586d6
+			if (cmd->data->flags & MMC_DATA_WRITE)
1d586d6
+				cmd_val |= SDXC_WRITE;
1d586d6
+			else
1d586d6
+				host->wait_dma = true;
1d586d6
+		} else {
1d586d6
+			imask |= SDXC_COMMAND_DONE;
1d586d6
+		}
1d586d6
+	} else {
1d586d6
+		imask |= SDXC_COMMAND_DONE;
1d586d6
+	}
1d586d6
+
1d586d6
+	dev_dbg(mmc_dev(host->mmc), "cmd %d(%08x) arg %x ie 0x%08x len %d\n",
1d586d6
+		cmd_val & 0x3f, cmd_val, cmd->arg, imask,
1d586d6
+		mrq->data ? mrq->data->blksz * mrq->data->blocks : 0);
1d586d6
+
1d586d6
+	spin_lock_irqsave(&host->lock, iflags);
1d586d6
+
1d586d6
+	if (host->mrq || host->manual_stop_mrq) {
1d586d6
+		spin_unlock_irqrestore(&host->lock, iflags);
1d586d6
+
1d586d6
+		if (data)
1d586d6
+			dma_unmap_sg(mmc_dev(host->mmc), data->sg,
1d586d6
+				data->sg_len, sunxi_mmc_get_dma_dir(data));
1d586d6
+
1d586d6
+		dev_err(mmc_dev(host->mmc), "request already pending\n");
1d586d6
+		mrq->cmd->error = -EBUSY;
1d586d6
+		mmc_request_done(host->mmc, mrq);
1d586d6
+		return;
1d586d6
+	}
1d586d6
+
1d586d6
+	if (data) {
1d586d6
+		mci_writel(host, REG_BLKSZ, data->blksz);
1d586d6
+		mci_writel(host, REG_BCNTR, data->blksz * data->blocks);
1d586d6
+		sunxi_mmc_start_dma(host, data);
1d586d6
+	}
1d586d6
+
1d586d6
+	host->mrq = mrq;
1d586d6
+	mci_writel(host, REG_IMASK, host->sdio_imask | imask);
1d586d6
+	mci_writel(host, REG_CARG, cmd->arg);
1d586d6
+	mci_writel(host, REG_CMDR, cmd_val);
1d586d6
+
1d586d6
+	spin_unlock_irqrestore(&host->lock, iflags);
1d586d6
+}
1d586d6
+
1d586d6
+static const struct of_device_id sunxi_mmc_of_match[] = {
1d586d6
+	{ .compatible = "allwinner,sun4i-a10-mmc", },
1d586d6
+	{ .compatible = "allwinner,sun5i-a13-mmc", },
1d586d6
+	{ /* sentinel */ }
1d586d6
+};
1d586d6
+MODULE_DEVICE_TABLE(of, sunxi_mmc_of_match);
1d586d6
+
1d586d6
+static struct mmc_host_ops sunxi_mmc_ops = {
1d586d6
+	.request	 = sunxi_mmc_request,
1d586d6
+	.set_ios	 = sunxi_mmc_set_ios,
1d586d6
+	.get_ro		 = mmc_gpio_get_ro,
1d586d6
+	.get_cd		 = mmc_gpio_get_cd,
1d586d6
+	.enable_sdio_irq = sunxi_mmc_enable_sdio_irq,
1d586d6
+	.hw_reset	 = sunxi_mmc_hw_reset,
1d586d6
+};