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From 262135cf058c28d248b997bd11b2c124e27d8d47 Mon Sep 17 00:00:00 2001
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From: Hans de Goede <hdegoede@redhat.com>
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Date: Mon, 27 Nov 2017 15:32:01 +0100
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Subject: [PATCH 3/3] ahci: Allow setting a default LPM policy for mobile
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 chipsets
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On many laptops setting a different LPM policy then unknown /
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max_performance can lead to power-savings of 1.0 - 1.5 Watts (when idle).
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Modern ultrabooks idle around 6W (at 50% screen brightness), 1.0 - 1.5W
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is a significant chunk of this.
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There are some performance / latency costs to enabling LPM by default,
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so it is desirable to make it possible to set a different LPM policy
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for mobile / laptop variants of chipsets / "South Bridges" vs their
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desktop / server counterparts. Also enabling LPM by default is not
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entirely without risk of regressions. At least min_power is known to
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cause issues with some disks, including some reports of data corruption.
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This commits adds a new ahci.mobile_lpm_policy kernel cmdline option,
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which defaults to a new SATA_MOBILE_LPM_POLICY Kconfig option so that
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Linux distributions can choose to set a LPM policy for mobile chipsets
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by default.
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The reason to have both a kernel cmdline option and a Kconfig default
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value for it, is to allow easy overriding of the default to allow
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trouble-shooting without needing to rebuild the kernel.
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Signed-off-by: Hans de Goede <hdegoede@redhat.com>
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---
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Changes in v2:
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-Remove .config changes from the patch
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---
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 drivers/ata/Kconfig | 19 +++++++++++
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 drivers/ata/ahci.c  | 97 +++++++++++++++++++++++++++++++----------------------
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 drivers/ata/ahci.h  |  3 ++
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 3 files changed, 78 insertions(+), 41 deletions(-)
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diff --git a/drivers/ata/Kconfig b/drivers/ata/Kconfig
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index cb5339166563..b3fad5663aeb 100644
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--- a/drivers/ata/Kconfig
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+++ b/drivers/ata/Kconfig
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@@ -92,6 +92,25 @@ config SATA_AHCI
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 	  If unsure, say N.
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+config SATA_MOBILE_LPM_POLICY
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+	int "Default SATA Link Power Management policy for mobile chipsets"
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+	range 0 4
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+	default 0
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+	depends on SATA_AHCI
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+	help
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+	  Select the Default SATA Link Power Management (LPM) policy to use
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+	  for mobile / laptop variants of chipsets / "South Bridges".
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+
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+	  The value set has the following meanings:
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+		0 => Keep firmware settings
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+		1 => Maximum performance
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+		2 => Medium power
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+		3 => Medium power with Device Initiated PM enabled
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+		4 => Minimum power
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+
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+	  Note "Minimum power" is known to cause issues, including disk
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+	  corruption, with some disks and should not be used.
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+
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 config SATA_AHCI_PLATFORM
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 	tristate "Platform AHCI SATA support"
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 	help
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diff --git a/drivers/ata/ahci.c b/drivers/ata/ahci.c
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index 844f697bedbf..8e910fae8892 100644
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--- a/drivers/ata/ahci.c
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+++ b/drivers/ata/ahci.c
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@@ -65,6 +65,7 @@ enum board_ids {
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 	/* board IDs by feature in alphabetical order */
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 	board_ahci,
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 	board_ahci_ign_iferr,
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+	board_ahci_mobile,
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 	board_ahci_nomsi,
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 	board_ahci_noncq,
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 	board_ahci_nosntf,
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@@ -140,6 +141,13 @@ static const struct ata_port_info ahci_port_info[] = {
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 		.udma_mask	= ATA_UDMA6,
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 		.port_ops	= &ahci_ops,
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 	},
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+	[board_ahci_mobile] = {
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+		AHCI_HFLAGS	(AHCI_HFLAG_IS_MOBILE),
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+		.flags		= AHCI_FLAG_COMMON,
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+		.pio_mask	= ATA_PIO4,
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+		.udma_mask	= ATA_UDMA6,
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+		.port_ops	= &ahci_ops,
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+	},
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 	[board_ahci_nomsi] = {
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 		AHCI_HFLAGS	(AHCI_HFLAG_NO_MSI),
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 		.flags		= AHCI_FLAG_COMMON,
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@@ -252,13 +260,13 @@ static const struct pci_device_id ahci_pci_tbl[] = {
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 	{ PCI_VDEVICE(INTEL, 0x2924), board_ahci }, /* ICH9 */
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 	{ PCI_VDEVICE(INTEL, 0x2925), board_ahci }, /* ICH9 */
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 	{ PCI_VDEVICE(INTEL, 0x2927), board_ahci }, /* ICH9 */
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-	{ PCI_VDEVICE(INTEL, 0x2929), board_ahci }, /* ICH9M */
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-	{ PCI_VDEVICE(INTEL, 0x292a), board_ahci }, /* ICH9M */
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-	{ PCI_VDEVICE(INTEL, 0x292b), board_ahci }, /* ICH9M */
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-	{ PCI_VDEVICE(INTEL, 0x292c), board_ahci }, /* ICH9M */
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-	{ PCI_VDEVICE(INTEL, 0x292f), board_ahci }, /* ICH9M */
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+	{ PCI_VDEVICE(INTEL, 0x2929), board_ahci_mobile }, /* ICH9M */
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+	{ PCI_VDEVICE(INTEL, 0x292a), board_ahci_mobile }, /* ICH9M */
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+	{ PCI_VDEVICE(INTEL, 0x292b), board_ahci_mobile }, /* ICH9M */
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+	{ PCI_VDEVICE(INTEL, 0x292c), board_ahci_mobile }, /* ICH9M */
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+	{ PCI_VDEVICE(INTEL, 0x292f), board_ahci_mobile }, /* ICH9M */
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 	{ PCI_VDEVICE(INTEL, 0x294d), board_ahci }, /* ICH9 */
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-	{ PCI_VDEVICE(INTEL, 0x294e), board_ahci }, /* ICH9M */
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+	{ PCI_VDEVICE(INTEL, 0x294e), board_ahci_mobile }, /* ICH9M */
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 	{ PCI_VDEVICE(INTEL, 0x502a), board_ahci }, /* Tolapai */
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 	{ PCI_VDEVICE(INTEL, 0x502b), board_ahci }, /* Tolapai */
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 	{ PCI_VDEVICE(INTEL, 0x3a05), board_ahci }, /* ICH10 */
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@@ -268,9 +276,9 @@ static const struct pci_device_id ahci_pci_tbl[] = {
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 	{ PCI_VDEVICE(INTEL, 0x3b23), board_ahci }, /* PCH AHCI */
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 	{ PCI_VDEVICE(INTEL, 0x3b24), board_ahci }, /* PCH RAID */
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 	{ PCI_VDEVICE(INTEL, 0x3b25), board_ahci }, /* PCH RAID */
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-	{ PCI_VDEVICE(INTEL, 0x3b29), board_ahci }, /* PCH M AHCI */
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+	{ PCI_VDEVICE(INTEL, 0x3b29), board_ahci_mobile }, /* PCH M AHCI */
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 	{ PCI_VDEVICE(INTEL, 0x3b2b), board_ahci }, /* PCH RAID */
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-	{ PCI_VDEVICE(INTEL, 0x3b2c), board_ahci }, /* PCH M RAID */
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+	{ PCI_VDEVICE(INTEL, 0x3b2c), board_ahci_mobile }, /* PCH M RAID */
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 	{ PCI_VDEVICE(INTEL, 0x3b2f), board_ahci }, /* PCH AHCI */
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 	{ PCI_VDEVICE(INTEL, 0x19b0), board_ahci }, /* DNV AHCI */
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 	{ PCI_VDEVICE(INTEL, 0x19b1), board_ahci }, /* DNV AHCI */
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@@ -293,9 +301,9 @@ static const struct pci_device_id ahci_pci_tbl[] = {
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 	{ PCI_VDEVICE(INTEL, 0x19cE), board_ahci }, /* DNV AHCI */
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 	{ PCI_VDEVICE(INTEL, 0x19cF), board_ahci }, /* DNV AHCI */
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 	{ PCI_VDEVICE(INTEL, 0x1c02), board_ahci }, /* CPT AHCI */
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-	{ PCI_VDEVICE(INTEL, 0x1c03), board_ahci }, /* CPT M AHCI */
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+	{ PCI_VDEVICE(INTEL, 0x1c03), board_ahci_mobile }, /* CPT M AHCI */
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 	{ PCI_VDEVICE(INTEL, 0x1c04), board_ahci }, /* CPT RAID */
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-	{ PCI_VDEVICE(INTEL, 0x1c05), board_ahci }, /* CPT M RAID */
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+	{ PCI_VDEVICE(INTEL, 0x1c05), board_ahci_mobile }, /* CPT M RAID */
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 	{ PCI_VDEVICE(INTEL, 0x1c06), board_ahci }, /* CPT RAID */
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 	{ PCI_VDEVICE(INTEL, 0x1c07), board_ahci }, /* CPT RAID */
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 	{ PCI_VDEVICE(INTEL, 0x1d02), board_ahci }, /* PBG AHCI */
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@@ -304,28 +312,28 @@ static const struct pci_device_id ahci_pci_tbl[] = {
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 	{ PCI_VDEVICE(INTEL, 0x2826), board_ahci }, /* PBG RAID */
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 	{ PCI_VDEVICE(INTEL, 0x2323), board_ahci }, /* DH89xxCC AHCI */
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 	{ PCI_VDEVICE(INTEL, 0x1e02), board_ahci }, /* Panther Point AHCI */
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-	{ PCI_VDEVICE(INTEL, 0x1e03), board_ahci }, /* Panther Point M AHCI */
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+	{ PCI_VDEVICE(INTEL, 0x1e03), board_ahci_mobile }, /* Panther M AHCI */
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 	{ PCI_VDEVICE(INTEL, 0x1e04), board_ahci }, /* Panther Point RAID */
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 	{ PCI_VDEVICE(INTEL, 0x1e05), board_ahci }, /* Panther Point RAID */
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 	{ PCI_VDEVICE(INTEL, 0x1e06), board_ahci }, /* Panther Point RAID */
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-	{ PCI_VDEVICE(INTEL, 0x1e07), board_ahci }, /* Panther Point M RAID */
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+	{ PCI_VDEVICE(INTEL, 0x1e07), board_ahci_mobile }, /* Panther M RAID */
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 	{ PCI_VDEVICE(INTEL, 0x1e0e), board_ahci }, /* Panther Point RAID */
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 	{ PCI_VDEVICE(INTEL, 0x8c02), board_ahci }, /* Lynx Point AHCI */
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-	{ PCI_VDEVICE(INTEL, 0x8c03), board_ahci }, /* Lynx Point M AHCI */
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+	{ PCI_VDEVICE(INTEL, 0x8c03), board_ahci_mobile }, /* Lynx M AHCI */
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 	{ PCI_VDEVICE(INTEL, 0x8c04), board_ahci }, /* Lynx Point RAID */
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-	{ PCI_VDEVICE(INTEL, 0x8c05), board_ahci }, /* Lynx Point M RAID */
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+	{ PCI_VDEVICE(INTEL, 0x8c05), board_ahci_mobile }, /* Lynx M RAID */
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 	{ PCI_VDEVICE(INTEL, 0x8c06), board_ahci }, /* Lynx Point RAID */
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-	{ PCI_VDEVICE(INTEL, 0x8c07), board_ahci }, /* Lynx Point M RAID */
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+	{ PCI_VDEVICE(INTEL, 0x8c07), board_ahci_mobile }, /* Lynx M RAID */
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 	{ PCI_VDEVICE(INTEL, 0x8c0e), board_ahci }, /* Lynx Point RAID */
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-	{ PCI_VDEVICE(INTEL, 0x8c0f), board_ahci }, /* Lynx Point M RAID */
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-	{ PCI_VDEVICE(INTEL, 0x9c02), board_ahci }, /* Lynx Point-LP AHCI */
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-	{ PCI_VDEVICE(INTEL, 0x9c03), board_ahci }, /* Lynx Point-LP AHCI */
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-	{ PCI_VDEVICE(INTEL, 0x9c04), board_ahci }, /* Lynx Point-LP RAID */
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-	{ PCI_VDEVICE(INTEL, 0x9c05), board_ahci }, /* Lynx Point-LP RAID */
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-	{ PCI_VDEVICE(INTEL, 0x9c06), board_ahci }, /* Lynx Point-LP RAID */
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-	{ PCI_VDEVICE(INTEL, 0x9c07), board_ahci }, /* Lynx Point-LP RAID */
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-	{ PCI_VDEVICE(INTEL, 0x9c0e), board_ahci }, /* Lynx Point-LP RAID */
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-	{ PCI_VDEVICE(INTEL, 0x9c0f), board_ahci }, /* Lynx Point-LP RAID */
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+	{ PCI_VDEVICE(INTEL, 0x8c0f), board_ahci_mobile }, /* Lynx M RAID */
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+	{ PCI_VDEVICE(INTEL, 0x9c02), board_ahci_mobile }, /* Lynx LP AHCI */
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+	{ PCI_VDEVICE(INTEL, 0x9c03), board_ahci_mobile }, /* Lynx LP AHCI */
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+	{ PCI_VDEVICE(INTEL, 0x9c04), board_ahci_mobile }, /* Lynx LP RAID */
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+	{ PCI_VDEVICE(INTEL, 0x9c05), board_ahci_mobile }, /* Lynx LP RAID */
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+	{ PCI_VDEVICE(INTEL, 0x9c06), board_ahci_mobile }, /* Lynx LP RAID */
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+	{ PCI_VDEVICE(INTEL, 0x9c07), board_ahci_mobile }, /* Lynx LP RAID */
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+	{ PCI_VDEVICE(INTEL, 0x9c0e), board_ahci_mobile }, /* Lynx LP RAID */
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+	{ PCI_VDEVICE(INTEL, 0x9c0f), board_ahci_mobile }, /* Lynx LP RAID */
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 	{ PCI_VDEVICE(INTEL, 0x1f22), board_ahci }, /* Avoton AHCI */
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 	{ PCI_VDEVICE(INTEL, 0x1f23), board_ahci }, /* Avoton AHCI */
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 	{ PCI_VDEVICE(INTEL, 0x1f24), board_ahci }, /* Avoton RAID */
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@@ -353,26 +361,26 @@ static const struct pci_device_id ahci_pci_tbl[] = {
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 	{ PCI_VDEVICE(INTEL, 0x8d66), board_ahci }, /* Wellsburg RAID */
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 	{ PCI_VDEVICE(INTEL, 0x8d6e), board_ahci }, /* Wellsburg RAID */
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 	{ PCI_VDEVICE(INTEL, 0x23a3), board_ahci }, /* Coleto Creek AHCI */
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-	{ PCI_VDEVICE(INTEL, 0x9c83), board_ahci }, /* Wildcat Point-LP AHCI */
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-	{ PCI_VDEVICE(INTEL, 0x9c85), board_ahci }, /* Wildcat Point-LP RAID */
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-	{ PCI_VDEVICE(INTEL, 0x9c87), board_ahci }, /* Wildcat Point-LP RAID */
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-	{ PCI_VDEVICE(INTEL, 0x9c8f), board_ahci }, /* Wildcat Point-LP RAID */
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+	{ PCI_VDEVICE(INTEL, 0x9c83), board_ahci_mobile }, /* Wildcat LP AHCI */
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+	{ PCI_VDEVICE(INTEL, 0x9c85), board_ahci_mobile }, /* Wildcat LP RAID */
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+	{ PCI_VDEVICE(INTEL, 0x9c87), board_ahci_mobile }, /* Wildcat LP RAID */
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+	{ PCI_VDEVICE(INTEL, 0x9c8f), board_ahci_mobile }, /* Wildcat LP RAID */
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 	{ PCI_VDEVICE(INTEL, 0x8c82), board_ahci }, /* 9 Series AHCI */
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-	{ PCI_VDEVICE(INTEL, 0x8c83), board_ahci }, /* 9 Series M AHCI */
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+	{ PCI_VDEVICE(INTEL, 0x8c83), board_ahci_mobile }, /* 9 Series M AHCI */
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 	{ PCI_VDEVICE(INTEL, 0x8c84), board_ahci }, /* 9 Series RAID */
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-	{ PCI_VDEVICE(INTEL, 0x8c85), board_ahci }, /* 9 Series M RAID */
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+	{ PCI_VDEVICE(INTEL, 0x8c85), board_ahci_mobile }, /* 9 Series M RAID */
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 	{ PCI_VDEVICE(INTEL, 0x8c86), board_ahci }, /* 9 Series RAID */
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-	{ PCI_VDEVICE(INTEL, 0x8c87), board_ahci }, /* 9 Series M RAID */
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+	{ PCI_VDEVICE(INTEL, 0x8c87), board_ahci_mobile }, /* 9 Series M RAID */
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 	{ PCI_VDEVICE(INTEL, 0x8c8e), board_ahci }, /* 9 Series RAID */
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-	{ PCI_VDEVICE(INTEL, 0x8c8f), board_ahci }, /* 9 Series M RAID */
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-	{ PCI_VDEVICE(INTEL, 0x9d03), board_ahci }, /* Sunrise Point-LP AHCI */
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-	{ PCI_VDEVICE(INTEL, 0x9d05), board_ahci }, /* Sunrise Point-LP RAID */
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-	{ PCI_VDEVICE(INTEL, 0x9d07), board_ahci }, /* Sunrise Point-LP RAID */
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+	{ PCI_VDEVICE(INTEL, 0x8c8f), board_ahci_mobile }, /* 9 Series M RAID */
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+	{ PCI_VDEVICE(INTEL, 0x9d03), board_ahci_mobile }, /* Sunrise LP AHCI */
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+	{ PCI_VDEVICE(INTEL, 0x9d05), board_ahci_mobile }, /* Sunrise LP RAID */
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+	{ PCI_VDEVICE(INTEL, 0x9d07), board_ahci_mobile }, /* Sunrise LP RAID */
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 	{ PCI_VDEVICE(INTEL, 0xa102), board_ahci }, /* Sunrise Point-H AHCI */
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-	{ PCI_VDEVICE(INTEL, 0xa103), board_ahci }, /* Sunrise Point-H M AHCI */
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+	{ PCI_VDEVICE(INTEL, 0xa103), board_ahci_mobile }, /* Sunrise M AHCI */
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 	{ PCI_VDEVICE(INTEL, 0xa105), board_ahci }, /* Sunrise Point-H RAID */
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 	{ PCI_VDEVICE(INTEL, 0xa106), board_ahci }, /* Sunrise Point-H RAID */
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-	{ PCI_VDEVICE(INTEL, 0xa107), board_ahci }, /* Sunrise Point-H M RAID */
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+	{ PCI_VDEVICE(INTEL, 0xa107), board_ahci_mobile }, /* Sunrise M RAID */
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 	{ PCI_VDEVICE(INTEL, 0xa10f), board_ahci }, /* Sunrise Point-H RAID */
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 	{ PCI_VDEVICE(INTEL, 0x2822), board_ahci }, /* Lewisburg RAID*/
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 	{ PCI_VDEVICE(INTEL, 0x2823), board_ahci }, /* Lewisburg AHCI*/
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@@ -386,10 +394,10 @@ static const struct pci_device_id ahci_pci_tbl[] = {
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 	{ PCI_VDEVICE(INTEL, 0xa206), board_ahci }, /* Lewisburg RAID*/
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 	{ PCI_VDEVICE(INTEL, 0xa252), board_ahci }, /* Lewisburg RAID*/
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 	{ PCI_VDEVICE(INTEL, 0xa256), board_ahci }, /* Lewisburg RAID*/
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-	{ PCI_VDEVICE(INTEL, 0x0f22), board_ahci }, /* Bay Trail AHCI */
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-	{ PCI_VDEVICE(INTEL, 0x0f23), board_ahci }, /* Bay Trail AHCI */
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-	{ PCI_VDEVICE(INTEL, 0x22a3), board_ahci }, /* Cherry Trail AHCI */
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-	{ PCI_VDEVICE(INTEL, 0x5ae3), board_ahci }, /* Apollo Lake AHCI */
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+	{ PCI_VDEVICE(INTEL, 0x0f22), board_ahci_mobile }, /* Bay Trail AHCI */
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+	{ PCI_VDEVICE(INTEL, 0x0f23), board_ahci_mobile }, /* Bay Trail AHCI */
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+	{ PCI_VDEVICE(INTEL, 0x22a3), board_ahci_mobile }, /* Cherry Tr. AHCI */
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+	{ PCI_VDEVICE(INTEL, 0x5ae3), board_ahci_mobile }, /* ApolloLake AHCI */
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 	/* JMicron 360/1/3/5/6, match class to avoid IDE function */
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 	{ PCI_VENDOR_ID_JMICRON, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
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@@ -597,6 +605,9 @@ static int marvell_enable = 1;
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 module_param(marvell_enable, int, 0644);
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 MODULE_PARM_DESC(marvell_enable, "Marvell SATA via AHCI (1 = enabled)");
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+static int mobile_lpm_policy = CONFIG_SATA_MOBILE_LPM_POLICY;
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+module_param(mobile_lpm_policy, int, 0644);
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+MODULE_PARM_DESC(mobile_lpm_policy, "Default LPM policy for mobile chipsets");
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 static void ahci_pci_save_initial_config(struct pci_dev *pdev,
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 					 struct ahci_host_priv *hpriv)
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@@ -1732,6 +1743,10 @@ static int ahci_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
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 		if (ap->flags & ATA_FLAG_EM)
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 			ap->em_message_type = hpriv->em_msg_type;
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+		if ((hpriv->flags & AHCI_HFLAG_IS_MOBILE) &&
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+		    mobile_lpm_policy >= ATA_LPM_UNKNOWN &&
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+		    mobile_lpm_policy <= ATA_LPM_MIN_POWER)
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+			ap->target_lpm_policy = mobile_lpm_policy;
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 		/* disabled/not-implemented port */
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 		if (!(hpriv->port_map & (1 << i)))
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diff --git a/drivers/ata/ahci.h b/drivers/ata/ahci.h
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index 749fd94441b0..a9d996e17d75 100644
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--- a/drivers/ata/ahci.h
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+++ b/drivers/ata/ahci.h
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@@ -251,6 +251,9 @@ enum {
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 	AHCI_HFLAG_YES_ALPM		= (1 << 23), /* force ALPM cap on */
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 	AHCI_HFLAG_NO_WRITE_TO_RO	= (1 << 24), /* don't write to read
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 							only registers */
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+	AHCI_HFLAG_IS_MOBILE		= (1 << 25), /* mobile chipset, use
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+							SATA_MOBILE_LPM_POLICY
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+							as default lpm_policy */
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 	/* ap->flags bits */
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-- 
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2.14.3
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