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From 99dd9c3733696d4a2536b21988c9b1b8f5195c5b Mon Sep 17 00:00:00 2001
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From: Fedora Kernel Team <kernel-team@fedoraproject.org>
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Date: Mon, 20 Jun 2016 12:40:00 +0200
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Subject: [PATCH 07/17] drm/i915/gen9: Allow skl_allocate_pipe_ddb() to operate
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on in-flight state (v3)
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Upstream: since drm-intel-next-2016-05-22
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commit c107acfeb03187873657ccc8af4fc5c704b3626b
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Author: Matt Roper <matthew.d.roper@intel.com>
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AuthorDate: Thu May 12 07:06:01 2016 -0700
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Commit: Matt Roper <matthew.d.roper@intel.com>
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CommitDate: Fri May 13 07:33:16 2016 -0700
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drm/i915/gen9: Allow skl_allocate_pipe_ddb() to operate on in-flight state (v3)
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We eventually want to calculate watermark values at atomic 'check' time
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instead of atomic 'commit' time so that any requested configurations
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that result in impossible watermark requirements are properly rejected.
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The first step along this path is to allocate the DDB at atomic 'check'
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time. As we perform this transition, allow the main allocation function
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to operate successfully on either an in-flight state or an
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already-commited state. Once we complete the transition in a future
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patch, we'll come back and remove the unnecessary logic for the
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already-committed case.
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v2: Rebase/refactor; we should no longer need to grab extra plane states
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while allocating the DDB since we can pull cached data rates and
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minimum block counts from the CRTC state for any planes that aren't
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being modified by this transaction.
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v3:
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- Simplify memsets to clear DDB plane entries. (Maarten)
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- Drop a redundant memset of plane[pipe][PLANE_CURSOR] that was added
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by an earlier Coccinelle patch. (Maarten)
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- Assign *num_active at the top of skl_ddb_get_pipe_allocation_limits()
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so that no code paths return without setting it. (kbuild robot)
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Cc: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
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Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
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Reviewed-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
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Link: http://patchwork.freedesktop.org/patch/msgid/1463061971-19638-8-git-send-email-matthew.d.roper@intel.com
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---
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drivers/gpu/drm/i915/i915_drv.h | 6 ++
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drivers/gpu/drm/i915/intel_pm.c | 179 +++++++++++++++++++++++++++++-----------
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2 files changed, 139 insertions(+), 46 deletions(-)
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diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
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index daba7eb..804af6f 100644
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--- a/drivers/gpu/drm/i915/i915_drv.h
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+++ b/drivers/gpu/drm/i915/i915_drv.h
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@@ -281,6 +281,12 @@ struct i915_hotplug {
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&dev->mode_config.plane_list, \
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base.head)
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+#define for_each_intel_plane_mask(dev, intel_plane, plane_mask) \
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+ list_for_each_entry(intel_plane, &dev->mode_config.plane_list, \
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+ base.head) \
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+ for_each_if ((plane_mask) & \
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+ (1 << drm_plane_index(&intel_plane->base)))
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+
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#define for_each_intel_plane_on_crtc(dev, intel_crtc, intel_plane) \
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list_for_each_entry(intel_plane, \
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&(dev)->mode_config.plane_list, \
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diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
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index 00db6e9..ee82b1f 100644
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--- a/drivers/gpu/drm/i915/intel_pm.c
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+++ b/drivers/gpu/drm/i915/intel_pm.c
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@@ -2788,13 +2788,25 @@ skl_wm_plane_id(const struct intel_plane *plane)
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static void
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skl_ddb_get_pipe_allocation_limits(struct drm_device *dev,
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const struct intel_crtc_state *cstate,
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- const struct intel_wm_config *config,
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- struct skl_ddb_entry *alloc /* out */)
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+ struct intel_wm_config *config,
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+ struct skl_ddb_entry *alloc, /* out */
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+ int *num_active /* out */)
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{
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+ struct drm_atomic_state *state = cstate->base.state;
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+ struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
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+ struct drm_i915_private *dev_priv = to_i915(dev);
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struct drm_crtc *for_crtc = cstate->base.crtc;
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struct drm_crtc *crtc;
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unsigned int pipe_size, ddb_size;
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int nth_active_pipe;
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+ int pipe = to_intel_crtc(for_crtc)->pipe;
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+
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+ if (intel_state && intel_state->active_pipe_changes)
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+ *num_active = hweight32(intel_state->active_crtcs);
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+ else if (intel_state)
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+ *num_active = hweight32(dev_priv->active_crtcs);
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+ else
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+ *num_active = config->num_pipes_active;
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if (!cstate->base.active) {
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alloc->start = 0;
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@@ -2809,25 +2821,56 @@ skl_ddb_get_pipe_allocation_limits(struct drm_device *dev,
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ddb_size -= 4; /* 4 blocks for bypass path allocation */
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- nth_active_pipe = 0;
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- for_each_crtc(dev, crtc) {
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- if (!to_intel_crtc(crtc)->active)
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- continue;
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+ /*
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+ * FIXME: At the moment we may be called on either in-flight or fully
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+ * committed cstate's. Once we fully move DDB allocation in the check
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+ * phase, we'll only be called on in-flight states and the 'else'
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+ * branch here will go away.
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+ *
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+ * The 'else' branch is slightly racy here, but it was racy to begin
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+ * with; since it's going away soon, no effort is made to address that.
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+ */
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+ if (state) {
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+ /*
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+ * If the state doesn't change the active CRTC's, then there's
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+ * no need to recalculate; the existing pipe allocation limits
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+ * should remain unchanged. Note that we're safe from racing
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+ * commits since any racing commit that changes the active CRTC
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+ * list would need to grab _all_ crtc locks, including the one
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+ * we currently hold.
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+ */
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+ if (!intel_state->active_pipe_changes) {
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+ *alloc = dev_priv->wm.skl_hw.ddb.pipe[pipe];
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+ return;
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+ }
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- if (crtc == for_crtc)
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- break;
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+ nth_active_pipe = hweight32(intel_state->active_crtcs &
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+ (drm_crtc_mask(for_crtc) - 1));
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+ pipe_size = ddb_size / hweight32(intel_state->active_crtcs);
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+ alloc->start = nth_active_pipe * ddb_size / *num_active;
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+ alloc->end = alloc->start + pipe_size;
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+ } else {
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+ nth_active_pipe = 0;
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+ for_each_crtc(dev, crtc) {
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+ if (!to_intel_crtc(crtc)->active)
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+ continue;
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- nth_active_pipe++;
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- }
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+ if (crtc == for_crtc)
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+ break;
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+
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+ nth_active_pipe++;
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+ }
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- pipe_size = ddb_size / config->num_pipes_active;
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- alloc->start = nth_active_pipe * ddb_size / config->num_pipes_active;
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- alloc->end = alloc->start + pipe_size;
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+ pipe_size = ddb_size / config->num_pipes_active;
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+ alloc->start = nth_active_pipe * ddb_size /
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+ config->num_pipes_active;
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+ alloc->end = alloc->start + pipe_size;
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+ }
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}
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-static unsigned int skl_cursor_allocation(const struct intel_wm_config *config)
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+static unsigned int skl_cursor_allocation(int num_active)
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{
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- if (config->num_pipes_active == 1)
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+ if (num_active == 1)
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return 32;
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return 8;
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@@ -2993,33 +3036,44 @@ skl_get_total_relative_data_rate(struct intel_crtc_state *intel_cstate)
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return total_data_rate;
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}
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-static void
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+static int
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skl_allocate_pipe_ddb(struct intel_crtc_state *cstate,
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struct skl_ddb_allocation *ddb /* out */)
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{
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+ struct drm_atomic_state *state = cstate->base.state;
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struct drm_crtc *crtc = cstate->base.crtc;
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struct drm_device *dev = crtc->dev;
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struct drm_i915_private *dev_priv = to_i915(dev);
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struct intel_wm_config *config = &dev_priv->wm.config;
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struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
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struct intel_plane *intel_plane;
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+ struct drm_plane *plane;
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+ struct drm_plane_state *pstate;
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enum pipe pipe = intel_crtc->pipe;
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struct skl_ddb_entry *alloc = &ddb->pipe[pipe];
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uint16_t alloc_size, start, cursor_blocks;
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uint16_t *minimum = cstate->wm.skl.minimum_blocks;
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uint16_t *y_minimum = cstate->wm.skl.minimum_y_blocks;
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unsigned int total_data_rate;
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+ int num_active;
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+ int id, i;
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+
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+ if (!cstate->base.active) {
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+ ddb->pipe[pipe].start = ddb->pipe[pipe].end = 0;
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+ memset(ddb->plane[pipe], 0, sizeof(ddb->plane[pipe]));
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+ memset(ddb->y_plane[pipe], 0, sizeof(ddb->y_plane[pipe]));
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+ return 0;
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+ }
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- skl_ddb_get_pipe_allocation_limits(dev, cstate, config, alloc);
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+ skl_ddb_get_pipe_allocation_limits(dev, cstate, config, alloc,
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+ &num_active);
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alloc_size = skl_ddb_entry_size(alloc);
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if (alloc_size == 0) {
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memset(ddb->plane[pipe], 0, sizeof(ddb->plane[pipe]));
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- memset(&ddb->plane[pipe][PLANE_CURSOR], 0,
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- sizeof(ddb->plane[pipe][PLANE_CURSOR]));
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- return;
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+ return 0;
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}
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- cursor_blocks = skl_cursor_allocation(config);
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+ cursor_blocks = skl_cursor_allocation(num_active);
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ddb->plane[pipe][PLANE_CURSOR].start = alloc->end - cursor_blocks;
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ddb->plane[pipe][PLANE_CURSOR].end = alloc->end;
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@@ -3027,21 +3081,55 @@ skl_allocate_pipe_ddb(struct intel_crtc_state *cstate,
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alloc->end -= cursor_blocks;
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/* 1. Allocate the mininum required blocks for each active plane */
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- for_each_intel_plane_on_crtc(dev, intel_crtc, intel_plane) {
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- struct drm_plane *plane = &intel_plane->base;
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- struct drm_framebuffer *fb = plane->state->fb;
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- int id = skl_wm_plane_id(intel_plane);
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+ /*
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+ * TODO: Remove support for already-committed state once we
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+ * only allocate DDB on in-flight states.
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+ */
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+ if (state) {
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+ for_each_plane_in_state(state, plane, pstate, i) {
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+ intel_plane = to_intel_plane(plane);
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+ id = skl_wm_plane_id(intel_plane);
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- if (!to_intel_plane_state(plane->state)->visible)
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- continue;
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+ if (intel_plane->pipe != pipe)
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+ continue;
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- if (plane->type == DRM_PLANE_TYPE_CURSOR)
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- continue;
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+ if (!to_intel_plane_state(pstate)->visible) {
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+ minimum[id] = 0;
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+ y_minimum[id] = 0;
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+ continue;
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+ }
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+ if (plane->type == DRM_PLANE_TYPE_CURSOR) {
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+ minimum[id] = 0;
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+ y_minimum[id] = 0;
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+ continue;
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+ }
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- minimum[id] = 8;
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- alloc_size -= minimum[id];
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- y_minimum[id] = (fb->pixel_format == DRM_FORMAT_NV12) ? 8 : 0;
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- alloc_size -= y_minimum[id];
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+ minimum[id] = 8;
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+ if (pstate->fb->pixel_format == DRM_FORMAT_NV12)
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+ y_minimum[id] = 8;
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+ else
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+ y_minimum[id] = 0;
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0903551 |
+ }
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+ } else {
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+ for_each_intel_plane_on_crtc(dev, intel_crtc, intel_plane) {
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0903551 |
+ struct drm_plane *plane = &intel_plane->base;
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0903551 |
+ struct drm_framebuffer *fb = plane->state->fb;
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0903551 |
+ int id = skl_wm_plane_id(intel_plane);
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+
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+ if (!to_intel_plane_state(plane->state)->visible)
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0903551 |
+ continue;
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0903551 |
+
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+ if (plane->type == DRM_PLANE_TYPE_CURSOR)
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0903551 |
+ continue;
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+
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+ minimum[id] = 8;
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+ y_minimum[id] = (fb->pixel_format == DRM_FORMAT_NV12) ? 8 : 0;
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0903551 |
+ }
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0903551 |
+ }
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+
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+ for (i = 0; i < PLANE_CURSOR; i++) {
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0903551 |
+ alloc_size -= minimum[i];
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0903551 |
+ alloc_size -= y_minimum[i];
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0903551 |
}
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0903551 |
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0903551 |
/*
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@@ -3052,21 +3140,14 @@ skl_allocate_pipe_ddb(struct intel_crtc_state *cstate,
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*/
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total_data_rate = skl_get_total_relative_data_rate(cstate);
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if (total_data_rate == 0)
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- return;
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+ return 0;
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start = alloc->start;
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for_each_intel_plane_on_crtc(dev, intel_crtc, intel_plane) {
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- struct drm_plane *plane = &intel_plane->base;
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- struct drm_plane_state *pstate = intel_plane->base.state;
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unsigned int data_rate, y_data_rate;
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uint16_t plane_blocks, y_plane_blocks = 0;
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int id = skl_wm_plane_id(intel_plane);
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- if (!to_intel_plane_state(pstate)->visible)
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- continue;
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- if (plane->type == DRM_PLANE_TYPE_CURSOR)
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- continue;
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-
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data_rate = cstate->wm.skl.plane_data_rate[id];
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/*
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@@ -3078,8 +3159,11 @@ skl_allocate_pipe_ddb(struct intel_crtc_state *cstate,
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plane_blocks += div_u64((uint64_t)alloc_size * data_rate,
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total_data_rate);
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- ddb->plane[pipe][id].start = start;
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- ddb->plane[pipe][id].end = start + plane_blocks;
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+ /* Leave disabled planes at (0,0) */
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+ if (data_rate) {
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+ ddb->plane[pipe][id].start = start;
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+ ddb->plane[pipe][id].end = start + plane_blocks;
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+ }
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start += plane_blocks;
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0903551 |
@@ -3092,12 +3176,15 @@ skl_allocate_pipe_ddb(struct intel_crtc_state *cstate,
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y_plane_blocks += div_u64((uint64_t)alloc_size * y_data_rate,
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total_data_rate);
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- ddb->y_plane[pipe][id].start = start;
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- ddb->y_plane[pipe][id].end = start + y_plane_blocks;
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+ if (y_data_rate) {
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+ ddb->y_plane[pipe][id].start = start;
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+ ddb->y_plane[pipe][id].end = start + y_plane_blocks;
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+ }
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start += y_plane_blocks;
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}
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+ return 0;
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0903551 |
}
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0903551 |
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0903551 |
static uint32_t skl_pipe_pixel_rate(const struct intel_crtc_state *config)
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0903551 |
@@ -3588,7 +3675,7 @@ static bool skl_update_pipe_wm(struct drm_crtc *crtc,
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0903551 |
struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
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struct intel_crtc_state *cstate = to_intel_crtc_state(crtc->state);
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0903551 |
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- skl_allocate_pipe_ddb(cstate, ddb);
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+ WARN_ON(skl_allocate_pipe_ddb(cstate, ddb) != 0);
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0903551 |
skl_build_pipe_wm(cstate, ddb, pipe_wm);
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0903551 |
if (!memcmp(&intel_crtc->wm.active.skl, pipe_wm, sizeof(*pipe_wm)))
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--
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0903551 |
2.7.4
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0903551 |
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