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From 2dda82bdd570042820241e71c02ea36081835f67 Mon Sep 17 00:00:00 2001
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From: Fedora Kernel Team <kernel-team@fedoraproject.org>
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Date: Mon, 20 Jun 2016 12:41:35 +0200
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Subject: [PATCH 14/17] drm/i915/gen9: Propagate watermark calculation failures
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up the call chain
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Upstream: since drm-intel-next-2016-05-22
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commit 55994c2c38a1101f84cdf277b228f830af8a9c1b
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Author: Matt Roper <matthew.d.roper@intel.com>
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AuthorDate: Thu May 12 07:06:08 2016 -0700
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Commit: Matt Roper <matthew.d.roper@intel.com>
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CommitDate: Fri May 13 07:34:48 2016 -0700
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drm/i915/gen9: Propagate watermark calculation failures up the call chain
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Once we move watermark calculation to the atomic check phase, we'll want
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to start rejecting display configurations that exceed out watermark
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limits. At the moment we just assume that there's always a valid set of
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watermarks, even though this may not actually be true. Let's prepare by
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passing return codes up through the call stack in preparation.
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Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
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Reviewed-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
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Link: http://patchwork.freedesktop.org/patch/msgid/1463061971-19638-15-git-send-email-matthew.d.roper@intel.com
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---
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drivers/gpu/drm/i915/intel_display.c | 10 ++--
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drivers/gpu/drm/i915/intel_pm.c | 90 ++++++++++++++++++++++--------------
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2 files changed, 61 insertions(+), 39 deletions(-)
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diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
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index b484fda..9ac2346 100644
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--- a/drivers/gpu/drm/i915/intel_display.c
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+++ b/drivers/gpu/drm/i915/intel_display.c
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@@ -13222,7 +13222,7 @@ static int intel_modeset_checks(struct drm_atomic_state *state)
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* phase. The code here should be run after the per-crtc and per-plane 'check'
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* handlers to ensure that all derived state has been updated.
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*/
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-static void calc_watermark_data(struct drm_atomic_state *state)
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+static int calc_watermark_data(struct drm_atomic_state *state)
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{
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struct drm_device *dev = state->dev;
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struct drm_i915_private *dev_priv = to_i915(dev);
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@@ -13258,7 +13258,9 @@ static void calc_watermark_data(struct drm_atomic_state *state)
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/* Is there platform-specific watermark information to calculate? */
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if (dev_priv->display.compute_global_watermarks)
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- dev_priv->display.compute_global_watermarks(state);
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+ return dev_priv->display.compute_global_watermarks(state);
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+
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+ return 0;
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}
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/**
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@@ -13345,9 +13347,7 @@ static int intel_atomic_check(struct drm_device *dev,
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return ret;
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intel_fbc_choose_crtc(dev_priv, state);
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- calc_watermark_data(state);
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-
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- return 0;
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+ return calc_watermark_data(state);
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}
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static int intel_atomic_prepare_commit(struct drm_device *dev,
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diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
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index 611c5a1..ec22d93 100644
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--- a/drivers/gpu/drm/i915/intel_pm.c
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+++ b/drivers/gpu/drm/i915/intel_pm.c
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@@ -3177,13 +3177,14 @@ static bool skl_ddb_allocation_changed(const struct skl_ddb_allocation *new_ddb,
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return false;
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}
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-static bool skl_compute_plane_wm(const struct drm_i915_private *dev_priv,
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- struct intel_crtc_state *cstate,
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- struct intel_plane_state *intel_pstate,
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- uint16_t ddb_allocation,
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- int level,
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- uint16_t *out_blocks, /* out */
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- uint8_t *out_lines /* out */)
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+static int skl_compute_plane_wm(const struct drm_i915_private *dev_priv,
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+ struct intel_crtc_state *cstate,
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+ struct intel_plane_state *intel_pstate,
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+ uint16_t ddb_allocation,
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+ int level,
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+ uint16_t *out_blocks, /* out */
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+ uint8_t *out_lines, /* out */
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+ bool *enabled /* out */)
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{
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struct drm_plane_state *pstate = &intel_pstate->base;
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struct drm_framebuffer *fb = pstate->fb;
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@@ -3195,8 +3196,10 @@ static bool skl_compute_plane_wm(const struct drm_i915_private *dev_priv,
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uint8_t cpp;
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uint32_t width = 0, height = 0;
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- if (latency == 0 || !cstate->base.active || !intel_pstate->visible)
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- return false;
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+ if (latency == 0 || !cstate->base.active || !intel_pstate->visible) {
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+ *enabled = false;
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+ return 0;
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+ }
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width = drm_rect_width(&intel_pstate->src) >> 16;
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height = drm_rect_height(&intel_pstate->src) >> 16;
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@@ -3257,13 +3260,16 @@ static bool skl_compute_plane_wm(const struct drm_i915_private *dev_priv,
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res_blocks++;
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}
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- if (res_blocks >= ddb_allocation || res_lines > 31)
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- return false;
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+ if (res_blocks >= ddb_allocation || res_lines > 31) {
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+ *enabled = false;
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+ return 0;
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+ }
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*out_blocks = res_blocks;
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*out_lines = res_lines;
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+ *enabled = true;
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- return true;
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+ return 0;
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}
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static int
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@@ -3281,6 +3287,7 @@ skl_compute_wm_level(const struct drm_i915_private *dev_priv,
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struct intel_plane_state *intel_pstate;
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uint16_t ddb_blocks;
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enum pipe pipe = intel_crtc->pipe;
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+ int ret;
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/*
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* We'll only calculate watermarks for planes that are actually
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@@ -3318,13 +3325,16 @@ skl_compute_wm_level(const struct drm_i915_private *dev_priv,
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ddb_blocks = skl_ddb_entry_size(&ddb->plane[pipe][i]);
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- result->plane_en[i] = skl_compute_plane_wm(dev_priv,
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- cstate,
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- intel_pstate,
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- ddb_blocks,
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- level,
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- &result->plane_res_b[i],
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- &result->plane_res_l[i]);
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+ ret = skl_compute_plane_wm(dev_priv,
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+ cstate,
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+ intel_pstate,
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+ ddb_blocks,
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+ level,
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+ &result->plane_res_b[i],
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+ &result->plane_res_l[i],
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+ &result->plane_en[i]);
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+ if (ret)
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+ return ret;
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}
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return 0;
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@@ -3361,21 +3371,26 @@ static void skl_compute_transition_wm(struct intel_crtc_state *cstate,
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}
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}
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-static void skl_build_pipe_wm(struct intel_crtc_state *cstate,
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- struct skl_ddb_allocation *ddb,
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- struct skl_pipe_wm *pipe_wm)
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+static int skl_build_pipe_wm(struct intel_crtc_state *cstate,
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+ struct skl_ddb_allocation *ddb,
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+ struct skl_pipe_wm *pipe_wm)
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{
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struct drm_device *dev = cstate->base.crtc->dev;
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const struct drm_i915_private *dev_priv = dev->dev_private;
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int level, max_level = ilk_wm_max_level(dev);
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+ int ret;
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for (level = 0; level <= max_level; level++) {
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- skl_compute_wm_level(dev_priv, ddb, cstate,
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- level, &pipe_wm->wm[level]);
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+ ret = skl_compute_wm_level(dev_priv, ddb, cstate,
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+ level, &pipe_wm->wm[level]);
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+ if (ret)
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+ return ret;
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}
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pipe_wm->linetime = skl_compute_linetime_wm(cstate);
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skl_compute_transition_wm(cstate, &pipe_wm->trans_wm);
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+
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+ return 0;
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}
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static void skl_compute_wm_results(struct drm_device *dev,
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@@ -3622,21 +3637,27 @@ static void skl_flush_wm_values(struct drm_i915_private *dev_priv,
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}
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}
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-static bool skl_update_pipe_wm(struct drm_crtc_state *cstate,
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- struct skl_ddb_allocation *ddb, /* out */
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- struct skl_pipe_wm *pipe_wm /* out */)
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+static int skl_update_pipe_wm(struct drm_crtc_state *cstate,
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+ struct skl_ddb_allocation *ddb, /* out */
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+ struct skl_pipe_wm *pipe_wm, /* out */
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+ bool *changed /* out */)
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{
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struct intel_crtc *intel_crtc = to_intel_crtc(cstate->crtc);
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struct intel_crtc_state *intel_cstate = to_intel_crtc_state(cstate);
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+ int ret;
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- skl_build_pipe_wm(intel_cstate, ddb, pipe_wm);
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+ ret = skl_build_pipe_wm(intel_cstate, ddb, pipe_wm);
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+ if (ret)
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+ return ret;
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if (!memcmp(&intel_crtc->wm.active.skl, pipe_wm, sizeof(*pipe_wm)))
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- return false;
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+ *changed = false;
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+ else
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+ *changed = true;
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intel_crtc->wm.active.skl = *pipe_wm;
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- return true;
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+ return 0;
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}
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static void skl_update_other_pipe_wm(struct drm_device *dev,
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@@ -3669,8 +3690,8 @@ static void skl_update_other_pipe_wm(struct drm_device *dev,
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if (!intel_crtc->active)
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continue;
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- wm_changed = skl_update_pipe_wm(intel_crtc->base.state,
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- &r->ddb, &pipe_wm);
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+ skl_update_pipe_wm(intel_crtc->base.state,
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+ &r->ddb, &pipe_wm, &wm_changed);
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/*
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* If we end up re-computing the other pipe WM values, it's
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@@ -3780,14 +3801,15 @@ static void skl_update_wm(struct drm_crtc *crtc)
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struct skl_wm_values *results = &dev_priv->wm.skl_results;
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struct intel_crtc_state *cstate = to_intel_crtc_state(crtc->state);
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struct skl_pipe_wm *pipe_wm = &cstate->wm.skl.optimal;
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-
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+ bool wm_changed;
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/* Clear all dirty flags */
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results->dirty_pipes = 0;
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skl_clear_wm(results, intel_crtc->pipe);
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- if (!skl_update_pipe_wm(crtc->state, &results->ddb, pipe_wm))
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+ skl_update_pipe_wm(crtc->state, &results->ddb, pipe_wm, &wm_changed);
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+ if (!wm_changed)
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return;
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skl_compute_wm_results(dev, pipe_wm, results, intel_crtc);
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--
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2.7.4
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