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id <B5e18cd3e0001>; Fri, 10 Jan 2020 11:15:14 -0800
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From: Vidya Sagar <vidyas@nvidia.com>
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5564a81 |
To: <bhelgaas@google.com>, <lorenzo.pieralisi@arm.com>,
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<rjw@rjwysocki.net>, <lenb@kernel.org>, <andrew.murray@arm.com>,
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<treding@nvidia.com>, <jonathanh@nvidia.com>
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CC: <linux-tegra@vger.kernel.org>, <linux-pci@vger.kernel.org>,
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<linux-acpi@vger.kernel.org>, <linux-kernel@vger.kernel.org>,
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<kthota@nvidia.com>, <mmaddireddy@nvidia.com>, <vidyas@nvidia.com>,
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<sagar.tv@gmail.com>
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5564a81 |
Subject: [PATCH V3 1/2] arm64: tegra: Re-order PCIe aperture mappings to
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5564a81 |
support ACPI boot
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5564a81 |
Date: Sat, 11 Jan 2020 00:44:59 +0530
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5564a81 |
Message-ID: <20200110191500.9538-2-vidyas@nvidia.com>
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X-Mailer: git-send-email 2.17.1
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In-Reply-To: <20200110191500.9538-1-vidyas@nvidia.com>
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References: <20200106082709.14370-1-vidyas@nvidia.com>
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5564a81 |
<20200110191500.9538-1-vidyas@nvidia.com>
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X-NVConfidentiality: public
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t9tsBwoqjGJn5WWPiQMaUZ8OHdSvPrUDuyKEFPjjr9IpczNvMzJE8SyHDZci42N+s+
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jBNjNRTUtey9w==
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Sender: linux-pci-owner@vger.kernel.org
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Precedence: bulk
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5564a81 |
List-ID: <linux-pci.vger.kernel.org>
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5564a81 |
X-Mailing-List: linux-pci@vger.kernel.org
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5564a81 |
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5564a81 |
Re-order Tegra194's PCIe aperture mappings to have IO window moved to
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64-bit aperture and have the entire 32-bit aperture used for accessing
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the configuration space. This makes it to use the entire 32MB of the 32-bit
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aperture for ECAM purpose while booting through ACPI.
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5564a81 |
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Signed-off-by: Vidya Sagar <vidyas@nvidia.com>
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---
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5564a81 |
V3:
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* New change in this series
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arch/arm64/boot/dts/nvidia/tegra194.dtsi | 36 ++++++++++++------------
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1 file changed, 18 insertions(+), 18 deletions(-)
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diff --git a/arch/arm64/boot/dts/nvidia/tegra194.dtsi b/arch/arm64/boot/dts/nvidia/tegra194.dtsi
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index ccac43be12ac..5d790ec5bdef 100644
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--- a/arch/arm64/boot/dts/nvidia/tegra194.dtsi
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+++ b/arch/arm64/boot/dts/nvidia/tegra194.dtsi
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@@ -1247,9 +1247,9 @@
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nvidia,aspm-l0s-entrance-latency-us = <3>;
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bus-range = <0x0 0xff>;
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- ranges = <0x81000000 0x0 0x30100000 0x0 0x30100000 0x0 0x00100000 /* downstream I/O (1MB) */
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- 0xc2000000 0x12 0x00000000 0x12 0x00000000 0x0 0x30000000 /* prefetchable memory (768MB) */
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- 0x82000000 0x0 0x40000000 0x12 0x30000000 0x0 0x10000000>; /* non-prefetchable memory (256MB) */
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+ ranges = <0xc2000000 0x12 0x00000000 0x12 0x00000000 0x0 0x30000000 /* prefetchable memory (768MB) */
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+ 0x82000000 0x00 0x40000000 0x12 0x30000000 0x0 0x0fff0000 /* non-prefetchable memory (256MB - 64KB) */
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+ 0x81000000 0x00 0x00000000 0x12 0x3fff0000 0x0 0x00010000>; /* downstream I/O (64KB) */
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};
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pcie@14120000 {
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@@ -1292,9 +1292,9 @@
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nvidia,aspm-l0s-entrance-latency-us = <3>;
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bus-range = <0x0 0xff>;
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- ranges = <0x81000000 0x0 0x32100000 0x0 0x32100000 0x0 0x00100000 /* downstream I/O (1MB) */
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- 0xc2000000 0x12 0x40000000 0x12 0x40000000 0x0 0x30000000 /* prefetchable memory (768MB) */
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- 0x82000000 0x0 0x40000000 0x12 0x70000000 0x0 0x10000000>; /* non-prefetchable memory (256MB) */
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+ ranges = <0xc2000000 0x12 0x40000000 0x12 0x40000000 0x0 0x30000000 /* prefetchable memory (768MB) */
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+ 0x82000000 0x00 0x40000000 0x12 0x70000000 0x0 0x0fff0000 /* non-prefetchable memory (256MB - 64KB) */
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+ 0x81000000 0x00 0x00000000 0x12 0x7fff0000 0x0 0x00010000>; /* downstream I/O (64KB) */
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};
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pcie@14140000 {
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@@ -1337,9 +1337,9 @@
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nvidia,aspm-l0s-entrance-latency-us = <3>;
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bus-range = <0x0 0xff>;
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- ranges = <0x81000000 0x0 0x34100000 0x0 0x34100000 0x0 0x00100000 /* downstream I/O (1MB) */
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- 0xc2000000 0x12 0x80000000 0x12 0x80000000 0x0 0x30000000 /* prefetchable memory (768MB) */
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- 0x82000000 0x0 0x40000000 0x12 0xb0000000 0x0 0x10000000>; /* non-prefetchable memory (256MB) */
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+ ranges = <0xc2000000 0x12 0x80000000 0x12 0x80000000 0x0 0x30000000 /* prefetchable memory (768MB) */
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+ 0x82000000 0x00 0x40000000 0x12 0xb0000000 0x0 0x0fff0000 /* non-prefetchable memory (256MB - 64KB) */
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+ 0x81000000 0x00 0x00000000 0x12 0xbfff0000 0x0 0x00010000>; /* downstream I/O (64KB) */
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};
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pcie@14160000 {
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5564a81 |
@@ -1382,9 +1382,9 @@
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nvidia,aspm-l0s-entrance-latency-us = <3>;
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bus-range = <0x0 0xff>;
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- ranges = <0x81000000 0x0 0x36100000 0x0 0x36100000 0x0 0x00100000 /* downstream I/O (1MB) */
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- 0xc2000000 0x14 0x00000000 0x14 0x00000000 0x3 0x40000000 /* prefetchable memory (13GB) */
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- 0x82000000 0x0 0x40000000 0x17 0x40000000 0x0 0xc0000000>; /* non-prefetchable memory (3GB) */
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+ ranges = <0xc2000000 0x14 0x00000000 0x14 0x00000000 0x3 0x40000000 /* prefetchable memory (13GB) */
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+ 0x82000000 0x00 0x40000000 0x17 0x40000000 0x0 0xbfff0000 /* non-prefetchable memory (3GB - 64KB) */
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+ 0x81000000 0x00 0x00000000 0x17 0xffff0000 0x0 0x00010000>; /* downstream I/O (64KB) */
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};
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pcie@14180000 {
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@@ -1427,9 +1427,9 @@
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nvidia,aspm-l0s-entrance-latency-us = <3>;
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bus-range = <0x0 0xff>;
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- ranges = <0x81000000 0x0 0x38100000 0x0 0x38100000 0x0 0x00100000 /* downstream I/O (1MB) */
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- 0xc2000000 0x18 0x00000000 0x18 0x00000000 0x3 0x40000000 /* prefetchable memory (13GB) */
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- 0x82000000 0x0 0x40000000 0x1b 0x40000000 0x0 0xc0000000>; /* non-prefetchable memory (3GB) */
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+ ranges = <0xc2000000 0x18 0x00000000 0x18 0x00000000 0x3 0x40000000 /* prefetchable memory (13GB) */
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+ 0x82000000 0x00 0x40000000 0x1b 0x40000000 0x0 0xbfff0000 /* non-prefetchable memory (3GB - 64KB) */
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+ 0x81000000 0x00 0x00000000 0x1b 0xffff0000 0x0 0x00010000>; /* downstream I/O (64KB) */
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};
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pcie@141a0000 {
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@@ -1476,9 +1476,9 @@
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nvidia,aspm-l0s-entrance-latency-us = <3>;
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bus-range = <0x0 0xff>;
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- ranges = <0x81000000 0x0 0x3a100000 0x0 0x3a100000 0x0 0x00100000 /* downstream I/O (1MB) */
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- 0xc2000000 0x1c 0x00000000 0x1c 0x00000000 0x3 0x40000000 /* prefetchable memory (13GB) */
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- 0x82000000 0x0 0x40000000 0x1f 0x40000000 0x0 0xc0000000>; /* non-prefetchable memory (3GB) */
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+ ranges = <0xc2000000 0x1c 0x00000000 0x1c 0x00000000 0x3 0x40000000 /* prefetchable memory (13GB) */
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+ 0x82000000 0x00 0x40000000 0x1f 0x40000000 0x0 0xbfff0000 /* non-prefetchable memory (3GB - 64KB) */
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+ 0x81000000 0x00 0x00000000 0x1f 0xffff0000 0x0 0x00010000>; /* downstream I/O (64KB) */
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};
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81203d2 |
pcie_ep@14160000 {
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From patchwork Fri Jan 10 19:15:00 2020
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hqnvemgate24.nvidia.com (using TLS: TLSv1.2, DES-CBC3-SHA)
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5564a81 |
id <B5e18cd160001>; Fri, 10 Jan 2020 11:14:30 -0800
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5564a81 |
Received: from hqmail.nvidia.com ([172.20.161.6])
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5564a81 |
by hqpgpgate101.nvidia.com (PGP Universal service);
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5564a81 |
Fri, 10 Jan 2020 11:15:21 -0800
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5564a81 |
X-PGP-Universal: processed;
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5564a81 |
by hqpgpgate101.nvidia.com on Fri, 10 Jan 2020 11:15:21 -0800
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5564a81 |
Received: from HQMAIL109.nvidia.com (172.20.187.15) by HQMAIL111.nvidia.com
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5564a81 |
(172.20.187.18) with Microsoft SMTP Server (TLS) id 15.0.1473.3;
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5564a81 |
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5564a81 |
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5564a81 |
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5564a81 |
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5564a81 |
Received: from vidyas-desktop.nvidia.com (Not Verified[10.24.37.48]) by
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5564a81 |
rnnvemgw01.nvidia.com with Trustwave SEG (v7, 5, 8, 10121)
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5564a81 |
id <B5e18cd440002>; Fri, 10 Jan 2020 11:15:20 -0800
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5564a81 |
From: Vidya Sagar <vidyas@nvidia.com>
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5564a81 |
To: <bhelgaas@google.com>, <lorenzo.pieralisi@arm.com>,
|
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5564a81 |
<rjw@rjwysocki.net>, <lenb@kernel.org>, <andrew.murray@arm.com>,
|
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5564a81 |
<treding@nvidia.com>, <jonathanh@nvidia.com>
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5564a81 |
CC: <linux-tegra@vger.kernel.org>, <linux-pci@vger.kernel.org>,
|
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5564a81 |
<linux-acpi@vger.kernel.org>, <linux-kernel@vger.kernel.org>,
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5564a81 |
<kthota@nvidia.com>, <mmaddireddy@nvidia.com>, <vidyas@nvidia.com>,
|
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5564a81 |
<sagar.tv@gmail.com>
|
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5564a81 |
Subject: [PATCH V3 2/2] PCI: Add MCFG quirks for Tegra194 host controllers
|
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|
5564a81 |
Date: Sat, 11 Jan 2020 00:45:00 +0530
|
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|
5564a81 |
Message-ID: <20200110191500.9538-3-vidyas@nvidia.com>
|
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5564a81 |
X-Mailer: git-send-email 2.17.1
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5564a81 |
In-Reply-To: <20200110191500.9538-1-vidyas@nvidia.com>
|
|
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5564a81 |
References: <20200106082709.14370-1-vidyas@nvidia.com>
|
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5564a81 |
<20200110191500.9538-1-vidyas@nvidia.com>
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5564a81 |
X-NVConfidentiality: public
|
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5564a81 |
MIME-Version: 1.0
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5564a81 |
DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nvidia.com; s=n1;
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5564a81 |
t=1578683671; bh=6wJT/II+S2upRtJe41MS3kcnFzRRB57EIPkoU3txnnc=;
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5564a81 |
h=X-PGP-Universal:From:To:CC:Subject:Date:Message-ID:X-Mailer:
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5564a81 |
In-Reply-To:References:X-NVConfidentiality:MIME-Version:
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5564a81 |
Content-Type;
|
|
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5564a81 |
b=KDh6KAfT+xBJE0n0yRibTvav8qocX0wdxtjjCMNH+VNrt1Gvwgt8htMQvTCpi08Hz
|
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5564a81 |
OLS6piubtsXb2Fk+J0rDcwmB2QM0YMKe6eA3DQkuJTPhl6PRxtvXdAYPfl/Z2pvG38
|
|
|
5564a81 |
dq6SIor6Yw4e76ncsvt69w6UXoLZHF7AywICq0jGnmPjWoKDnjID3qKSj5/u7tE+/L
|
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5564a81 |
6hJUZ2QQebXRI17dRdfleyir+rRCS0wMl9tVNiAHplY3Wlxw895LJqvmVRZDVA+kg5
|
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5564a81 |
8DPKJY2JbazS6P4QcywESwuhDfejJGaJUz+1/6oSiHBMCI5OhfhFZ/lyTf0iZycdTQ
|
|
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5564a81 |
gnZUMkPu2QZOg==
|
|
|
5564a81 |
Sender: linux-pci-owner@vger.kernel.org
|
|
|
5564a81 |
Precedence: bulk
|
|
|
5564a81 |
List-ID: <linux-pci.vger.kernel.org>
|
|
|
5564a81 |
X-Mailing-List: linux-pci@vger.kernel.org
|
|
|
5564a81 |
|
|
|
5564a81 |
The PCIe controller in Tegra194 SoC is not completely ECAM-compliant.
|
|
|
5564a81 |
With the current hardware design limitations in place, ECAM can be enabled
|
|
|
5564a81 |
only for one controller (C5 controller to be precise) with bus numbers
|
|
|
5564a81 |
starting from 160 instead of 0. A different approach is taken to avoid this
|
|
|
5564a81 |
abnormal way of enabling ECAM for just one controller but to enable
|
|
|
5564a81 |
configuration space access for all the other controllers. In this approach,
|
|
|
5564a81 |
ops are added through MCFG quirk mechanism which access the configuration
|
|
|
5564a81 |
spaces by dynamically programming iATU (internal AddressTranslation Unit)
|
|
|
5564a81 |
to generate respective configuration accesses just like the way it is
|
|
|
5564a81 |
done in DesignWare core sub-system.
|
|
|
5564a81 |
|
|
|
5564a81 |
Signed-off-by: Vidya Sagar <vidyas@nvidia.com>
|
|
|
5564a81 |
Reported-by: kbuild test robot <lkp@intel.com>
|
|
|
5564a81 |
Acked-by: Thierry Reding <treding@nvidia.com>
|
|
|
5564a81 |
---
|
|
|
5564a81 |
V3:
|
|
|
5564a81 |
* Removed MCFG address hardcoding in pci_mcfg.c file
|
|
|
5564a81 |
* Started using 'dbi_base' for accessing root port's own config space
|
|
|
5564a81 |
* and using 'config_base' for accessing config space of downstream hierarchy
|
|
|
5564a81 |
|
|
|
5564a81 |
V2:
|
|
|
5564a81 |
* Fixed build issues reported by kbuild test bot
|
|
|
5564a81 |
|
|
|
5564a81 |
drivers/acpi/pci_mcfg.c | 7 ++
|
|
|
5564a81 |
drivers/pci/controller/dwc/Kconfig | 3 +-
|
|
|
5564a81 |
drivers/pci/controller/dwc/Makefile | 2 +-
|
|
|
5564a81 |
drivers/pci/controller/dwc/pcie-tegra194.c | 102 +++++++++++++++++++++
|
|
|
5564a81 |
include/linux/pci-ecam.h | 1 +
|
|
|
5564a81 |
5 files changed, 113 insertions(+), 2 deletions(-)
|
|
|
5564a81 |
|
|
|
5564a81 |
diff --git a/drivers/acpi/pci_mcfg.c b/drivers/acpi/pci_mcfg.c
|
|
|
5564a81 |
index 6b347d9920cc..707181408173 100644
|
|
|
5564a81 |
--- a/drivers/acpi/pci_mcfg.c
|
|
|
5564a81 |
+++ b/drivers/acpi/pci_mcfg.c
|
|
|
5564a81 |
@@ -116,6 +116,13 @@ static struct mcfg_fixup mcfg_quirks[] = {
|
|
|
5564a81 |
THUNDER_ECAM_QUIRK(2, 12),
|
|
|
5564a81 |
THUNDER_ECAM_QUIRK(2, 13),
|
|
|
5564a81 |
|
|
|
5564a81 |
+ { "NVIDIA", "TEGRA194", 1, 0, MCFG_BUS_ANY, &tegra194_pcie_ops},
|
|
|
5564a81 |
+ { "NVIDIA", "TEGRA194", 1, 1, MCFG_BUS_ANY, &tegra194_pcie_ops},
|
|
|
5564a81 |
+ { "NVIDIA", "TEGRA194", 1, 2, MCFG_BUS_ANY, &tegra194_pcie_ops},
|
|
|
5564a81 |
+ { "NVIDIA", "TEGRA194", 1, 3, MCFG_BUS_ANY, &tegra194_pcie_ops},
|
|
|
5564a81 |
+ { "NVIDIA", "TEGRA194", 1, 4, MCFG_BUS_ANY, &tegra194_pcie_ops},
|
|
|
5564a81 |
+ { "NVIDIA", "TEGRA194", 1, 5, MCFG_BUS_ANY, &tegra194_pcie_ops},
|
|
|
5564a81 |
+
|
|
|
5564a81 |
#define XGENE_V1_ECAM_MCFG(rev, seg) \
|
|
|
5564a81 |
{"APM ", "XGENE ", rev, seg, MCFG_BUS_ANY, \
|
|
|
5564a81 |
&xgene_v1_pcie_ecam_ops }
|
|
|
5564a81 |
diff --git a/drivers/pci/controller/dwc/Kconfig b/drivers/pci/controller/dwc/Kconfig
|
|
|
5564a81 |
index 0830dfcfa43a..f5b9e75aceed 100644
|
|
|
5564a81 |
--- a/drivers/pci/controller/dwc/Kconfig
|
|
|
5564a81 |
+++ b/drivers/pci/controller/dwc/Kconfig
|
|
|
5564a81 |
@@ -255,7 +255,8 @@ config PCIE_TEGRA194
|
|
|
5564a81 |
select PHY_TEGRA194_P2U
|
|
|
5564a81 |
help
|
|
|
5564a81 |
Say Y here if you want support for DesignWare core based PCIe host
|
|
|
5564a81 |
- controller found in NVIDIA Tegra194 SoC.
|
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|
5564a81 |
+ controller found in NVIDIA Tegra194 SoC. ACPI platforms with Tegra194
|
|
|
5564a81 |
+ don't need to enable this.
|
|
|
5564a81 |
|
|
|
5564a81 |
config PCIE_UNIPHIER
|
|
|
5564a81 |
bool "Socionext UniPhier PCIe controllers"
|
|
|
5564a81 |
diff --git a/drivers/pci/controller/dwc/Makefile b/drivers/pci/controller/dwc/Makefile
|
|
|
5564a81 |
index 8a637cfcf6e9..76a6c52b8500 100644
|
|
|
5564a81 |
--- a/drivers/pci/controller/dwc/Makefile
|
|
|
5564a81 |
+++ b/drivers/pci/controller/dwc/Makefile
|
|
|
5564a81 |
@@ -17,7 +17,6 @@ obj-$(CONFIG_PCIE_INTEL_GW) += pcie-intel-gw.o
|
|
|
5564a81 |
obj-$(CONFIG_PCIE_KIRIN) += pcie-kirin.o
|
|
|
5564a81 |
obj-$(CONFIG_PCIE_HISI_STB) += pcie-histb.o
|
|
|
5564a81 |
obj-$(CONFIG_PCI_MESON) += pci-meson.o
|
|
|
5564a81 |
-obj-$(CONFIG_PCIE_TEGRA194) += pcie-tegra194.o
|
|
|
5564a81 |
obj-$(CONFIG_PCIE_UNIPHIER) += pcie-uniphier.o
|
|
|
5564a81 |
|
|
|
5564a81 |
# The following drivers are for devices that use the generic ACPI
|
|
|
5564a81 |
@@ -33,4 +32,5 @@ obj-$(CONFIG_PCIE_UNIPHIER) += pcie-uniphier.o
|
|
|
5564a81 |
ifdef CONFIG_PCI
|
|
|
5564a81 |
obj-$(CONFIG_ARM64) += pcie-al.o
|
|
|
5564a81 |
obj-$(CONFIG_ARM64) += pcie-hisi.o
|
|
|
5564a81 |
+obj-$(CONFIG_ARM64) += pcie-tegra194.o
|
|
|
5564a81 |
endif
|
|
|
5564a81 |
diff --git a/drivers/pci/controller/dwc/pcie-tegra194.c b/drivers/pci/controller/dwc/pcie-tegra194.c
|
|
|
5564a81 |
index cbe95f0ea0ca..660f55caa8be 100644
|
|
|
5564a81 |
--- a/drivers/pci/controller/dwc/pcie-tegra194.c
|
|
|
5564a81 |
+++ b/drivers/pci/controller/dwc/pcie-tegra194.c
|
|
|
5564a81 |
@@ -21,6 +21,8 @@
|
|
|
5564a81 |
#include <linux/of_irq.h>
|
|
|
5564a81 |
#include <linux/of_pci.h>
|
|
|
5564a81 |
#include <linux/pci.h>
|
|
|
5564a81 |
+#include <linux/pci-acpi.h>
|
|
|
5564a81 |
+#include <linux/pci-ecam.h>
|
|
|
5564a81 |
#include <linux/phy/phy.h>
|
|
|
5564a81 |
#include <linux/pinctrl/consumer.h>
|
|
|
5564a81 |
#include <linux/platform_device.h>
|
|
|
5564a81 |
@@ -285,6 +287,103 @@ struct tegra_pcie_dw {
|
|
|
5564a81 |
struct dentry *debugfs;
|
|
|
5564a81 |
};
|
|
|
5564a81 |
|
|
|
5564a81 |
+#if defined(CONFIG_ACPI) && defined(CONFIG_PCI_QUIRKS)
|
|
|
5564a81 |
+struct tegra194_pcie_acpi {
|
|
|
5564a81 |
+ void __iomem *config_base;
|
|
|
5564a81 |
+ void __iomem *iatu_base;
|
|
|
5564a81 |
+ void __iomem *dbi_base;
|
|
|
5564a81 |
+};
|
|
|
5564a81 |
+
|
|
|
5564a81 |
+static int tegra194_acpi_init(struct pci_config_window *cfg)
|
|
|
5564a81 |
+{
|
|
|
5564a81 |
+ struct device *dev = cfg->parent;
|
|
|
5564a81 |
+ struct tegra194_pcie_acpi *pcie;
|
|
|
5564a81 |
+
|
|
|
5564a81 |
+ pcie = devm_kzalloc(dev, sizeof(*pcie), GFP_KERNEL);
|
|
|
5564a81 |
+ if (!pcie)
|
|
|
5564a81 |
+ return -ENOMEM;
|
|
|
5564a81 |
+
|
|
|
5564a81 |
+ pcie->config_base = cfg->win;
|
|
|
5564a81 |
+ pcie->iatu_base = cfg->win + SZ_256K;
|
|
|
5564a81 |
+ pcie->dbi_base = cfg->win + SZ_512K;
|
|
|
5564a81 |
+ cfg->priv = pcie;
|
|
|
5564a81 |
+
|
|
|
5564a81 |
+ return 0;
|
|
|
5564a81 |
+}
|
|
|
5564a81 |
+
|
|
|
5564a81 |
+static inline void atu_reg_write(struct tegra194_pcie_acpi *pcie, int index,
|
|
|
5564a81 |
+ u32 val, u32 reg)
|
|
|
5564a81 |
+{
|
|
|
5564a81 |
+ u32 offset = PCIE_GET_ATU_OUTB_UNR_REG_OFFSET(index);
|
|
|
5564a81 |
+
|
|
|
5564a81 |
+ writel(val, pcie->iatu_base + offset + reg);
|
|
|
5564a81 |
+}
|
|
|
5564a81 |
+
|
|
|
5564a81 |
+static void program_outbound_atu(struct tegra194_pcie_acpi *pcie, int index,
|
|
|
5564a81 |
+ int type, u64 cpu_addr, u64 pci_addr, u64 size)
|
|
|
5564a81 |
+{
|
|
|
5564a81 |
+ atu_reg_write(pcie, index, lower_32_bits(cpu_addr),
|
|
|
5564a81 |
+ PCIE_ATU_LOWER_BASE);
|
|
|
5564a81 |
+ atu_reg_write(pcie, index, upper_32_bits(cpu_addr),
|
|
|
5564a81 |
+ PCIE_ATU_UPPER_BASE);
|
|
|
5564a81 |
+ atu_reg_write(pcie, index, lower_32_bits(pci_addr),
|
|
|
5564a81 |
+ PCIE_ATU_LOWER_TARGET);
|
|
|
5564a81 |
+ atu_reg_write(pcie, index, lower_32_bits(cpu_addr + size - 1),
|
|
|
5564a81 |
+ PCIE_ATU_LIMIT);
|
|
|
5564a81 |
+ atu_reg_write(pcie, index, upper_32_bits(pci_addr),
|
|
|
5564a81 |
+ PCIE_ATU_UPPER_TARGET);
|
|
|
5564a81 |
+ atu_reg_write(pcie, index, type, PCIE_ATU_CR1);
|
|
|
5564a81 |
+ atu_reg_write(pcie, index, PCIE_ATU_ENABLE, PCIE_ATU_CR2);
|
|
|
5564a81 |
+}
|
|
|
5564a81 |
+
|
|
|
5564a81 |
+static void __iomem *tegra194_map_bus(struct pci_bus *bus,
|
|
|
5564a81 |
+ unsigned int devfn, int where)
|
|
|
5564a81 |
+{
|
|
|
5564a81 |
+ struct pci_config_window *cfg = bus->sysdata;
|
|
|
5564a81 |
+ struct tegra194_pcie_acpi *pcie = cfg->priv;
|
|
|
5564a81 |
+ u32 busdev;
|
|
|
5564a81 |
+ int type;
|
|
|
5564a81 |
+
|
|
|
5564a81 |
+ if (bus->number < cfg->busr.start || bus->number > cfg->busr.end)
|
|
|
5564a81 |
+ return NULL;
|
|
|
5564a81 |
+
|
|
|
5564a81 |
+ if (bus->number == cfg->busr.start) {
|
|
|
5564a81 |
+ if (PCI_SLOT(devfn) == 0)
|
|
|
5564a81 |
+ return pcie->dbi_base + where;
|
|
|
5564a81 |
+ else
|
|
|
5564a81 |
+ return NULL;
|
|
|
5564a81 |
+ }
|
|
|
5564a81 |
+
|
|
|
5564a81 |
+ busdev = PCIE_ATU_BUS(bus->number) | PCIE_ATU_DEV(PCI_SLOT(devfn)) |
|
|
|
5564a81 |
+ PCIE_ATU_FUNC(PCI_FUNC(devfn));
|
|
|
5564a81 |
+
|
|
|
5564a81 |
+ if (bus->parent->number == cfg->busr.start) {
|
|
|
5564a81 |
+ if (PCI_SLOT(devfn) == 0)
|
|
|
5564a81 |
+ type = PCIE_ATU_TYPE_CFG0;
|
|
|
5564a81 |
+ else
|
|
|
5564a81 |
+ return NULL;
|
|
|
5564a81 |
+ } else {
|
|
|
5564a81 |
+ type = PCIE_ATU_TYPE_CFG1;
|
|
|
5564a81 |
+ }
|
|
|
5564a81 |
+
|
|
|
5564a81 |
+ program_outbound_atu(pcie, PCIE_ATU_REGION_INDEX0, type,
|
|
|
5564a81 |
+ cfg->res.start, busdev, SZ_256K);
|
|
|
5564a81 |
+ return (void __iomem *)(pcie->config_base + where);
|
|
|
5564a81 |
+}
|
|
|
5564a81 |
+
|
|
|
5564a81 |
+struct pci_ecam_ops tegra194_pcie_ops = {
|
|
|
5564a81 |
+ .bus_shift = 20,
|
|
|
5564a81 |
+ .init = tegra194_acpi_init,
|
|
|
5564a81 |
+ .pci_ops = {
|
|
|
5564a81 |
+ .map_bus = tegra194_map_bus,
|
|
|
5564a81 |
+ .read = pci_generic_config_read,
|
|
|
5564a81 |
+ .write = pci_generic_config_write,
|
|
|
5564a81 |
+ }
|
|
|
5564a81 |
+};
|
|
|
5564a81 |
+#endif /* defined(CONFIG_ACPI) && defined(CONFIG_PCI_QUIRKS) */
|
|
|
5564a81 |
+
|
|
|
5564a81 |
+#ifdef CONFIG_PCIE_TEGRA194
|
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+
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static inline struct tegra_pcie_dw *to_tegra_pcie(struct dw_pcie *pci)
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{
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return container_of(pci, struct tegra_pcie_dw, pci);
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@@ -1728,3 +1827,6 @@ MODULE_DEVICE_TABLE(of, tegra_pcie_dw_of_match);
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MODULE_AUTHOR("Vidya Sagar <vidyas@nvidia.com>");
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MODULE_DESCRIPTION("NVIDIA PCIe host controller driver");
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MODULE_LICENSE("GPL v2");
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+
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+#endif /* CONFIG_PCIE_TEGRA194 */
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+
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diff --git a/include/linux/pci-ecam.h b/include/linux/pci-ecam.h
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index a73164c85e78..6156140dcbb6 100644
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--- a/include/linux/pci-ecam.h
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+++ b/include/linux/pci-ecam.h
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@@ -57,6 +57,7 @@ extern struct pci_ecam_ops pci_thunder_ecam_ops; /* Cavium ThunderX 1.x */
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extern struct pci_ecam_ops xgene_v1_pcie_ecam_ops; /* APM X-Gene PCIe v1 */
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extern struct pci_ecam_ops xgene_v2_pcie_ecam_ops; /* APM X-Gene PCIe v2.x */
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extern struct pci_ecam_ops al_pcie_ops; /* Amazon Annapurna Labs PCIe */
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+extern struct pci_ecam_ops tegra194_pcie_ops; /* Tegra194 PCIe */
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#endif
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#ifdef CONFIG_PCI_HOST_COMMON
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