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commit 285994a62c80f1d72c6924282bcb59608098d5ec
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Author: Catalin Marinas <catalin.marinas@arm.com>
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Date: Wed Mar 11 12:20:39 2015 +0000
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arm64: Invalidate the TLB corresponding to intermediate page table levels
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The ARM architecture allows the caching of intermediate page table
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levels and page table freeing requires a sequence like:
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pmd_clear()
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TLB invalidation
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pte page freeing
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With commit 5e5f6dc10546 (arm64: mm: enable HAVE_RCU_TABLE_FREE logic),
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the page table freeing batching was moved from tlb_remove_page() to
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tlb_remove_table(). The former takes care of TLB invalidation as this is
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also shared with pte clearing and page cache page freeing. The latter,
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however, does not invalidate the TLBs for intermediate page table levels
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as it probably relies on the architecture code to do it if required.
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When the mm->mm_users < 2, tlb_remove_table() does not do any batching
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and page table pages are freed before tlb_finish_mmu() which performs
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the actual TLB invalidation.
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This patch introduces __tlb_flush_pgtable() for arm64 and calls it from
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the {pte,pmd,pud}_free_tlb() directly without relying on deferred page
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table freeing.
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Fixes: 5e5f6dc10546 arm64: mm: enable HAVE_RCU_TABLE_FREE logic
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Reported-by: Jon Masters <jcm@redhat.com>
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Tested-by: Jon Masters <jcm@redhat.com>
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Tested-by: Steve Capper <steve.capper@linaro.org>
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Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
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diff --git a/arch/arm64/include/asm/tlb.h b/arch/arm64/include/asm/tlb.h
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index c028fe3..53d9c35 100644
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--- a/arch/arm64/include/asm/tlb.h
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+++ b/arch/arm64/include/asm/tlb.h
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@@ -48,6 +48,7 @@ static inline void tlb_flush(struct mmu_gather *tlb)
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static inline void __pte_free_tlb(struct mmu_gather *tlb, pgtable_t pte,
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unsigned long addr)
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{
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+ __flush_tlb_pgtable(tlb->mm, addr);
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pgtable_page_dtor(pte);
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tlb_remove_entry(tlb, pte);
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}
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@@ -56,6 +57,7 @@ static inline void __pte_free_tlb(struct mmu_gather *tlb, pgtable_t pte,
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static inline void __pmd_free_tlb(struct mmu_gather *tlb, pmd_t *pmdp,
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unsigned long addr)
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{
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+ __flush_tlb_pgtable(tlb->mm, addr);
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tlb_remove_entry(tlb, virt_to_page(pmdp));
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}
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#endif
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@@ -64,6 +66,7 @@ static inline void __pmd_free_tlb(struct mmu_gather *tlb, pmd_t *pmdp,
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static inline void __pud_free_tlb(struct mmu_gather *tlb, pud_t *pudp,
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unsigned long addr)
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{
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+ __flush_tlb_pgtable(tlb->mm, addr);
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tlb_remove_entry(tlb, virt_to_page(pudp));
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}
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#endif
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diff --git a/arch/arm64/include/asm/tlbflush.h b/arch/arm64/include/asm/tlbflush.h
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index 4abe9b9..c3bb05b 100644
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--- a/arch/arm64/include/asm/tlbflush.h
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+++ b/arch/arm64/include/asm/tlbflush.h
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@@ -144,6 +144,19 @@ static inline void flush_tlb_kernel_range(unsigned long start, unsigned long end
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}
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/*
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+ * Used to invalidate the TLB (walk caches) corresponding to intermediate page
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+ * table levels (pgd/pud/pmd).
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+ */
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+static inline void __flush_tlb_pgtable(struct mm_struct *mm,
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+ unsigned long uaddr)
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+{
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+ unsigned long addr = uaddr >> 12 | ((unsigned long)ASID(mm) << 48);
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+
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+ dsb(ishst);
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+ asm("tlbi vae1is, %0" : : "r" (addr));
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+ dsb(ish);
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+}
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+/*
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* On AArch64, the cache coherency is handled via the set_pte_at() function.
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*/
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static inline void update_mmu_cache(struct vm_area_struct *vma,
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