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From 83e18f0ad4793ea83e03cb8e608bdd2939e76d78 Mon Sep 17 00:00:00 2001
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From: Peter Robinson <pbrobinson@gmail.com>
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Date: Mon, 4 Sep 2017 13:04:34 +0100
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Subject: [PATCH 1/4] Revert "net: stmmac: sun8i: Remove the compatibles"
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This reverts commit ad4540cc5aa3dccb8e1e12458d57f8c40fae5a1c.
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---
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 drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c | 8 ++++++++
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 1 file changed, 8 insertions(+)
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diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c b/drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c
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index 39c2122a4f26..fffd6d5fc907 100644
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--- a/drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c
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+++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c
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@@ -979,6 +979,14 @@ static int sun8i_dwmac_probe(struct platform_device *pdev)
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 }
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 static const struct of_device_id sun8i_dwmac_match[] = {
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+	{ .compatible = "allwinner,sun8i-h3-emac",
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+		.data = &emac_variant_h3 },
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+	{ .compatible = "allwinner,sun8i-v3s-emac",
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+		.data = &emac_variant_v3s },
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+	{ .compatible = "allwinner,sun8i-a83t-emac",
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+		.data = &emac_variant_a83t },
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+	{ .compatible = "allwinner,sun50i-a64-emac",
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+		.data = &emac_variant_a64 },
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 	{ }
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 };
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 MODULE_DEVICE_TABLE(of, sun8i_dwmac_match);
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-- 
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2.13.5
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From fa4788d88903c1e535d034c3dd3fcd386685a02c Mon Sep 17 00:00:00 2001
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From: Peter Robinson <pbrobinson@gmail.com>
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Date: Mon, 4 Sep 2017 13:04:41 +0100
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Subject: [PATCH 2/4] Revert "arm: dts: sunxi: Revert EMAC changes"
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This reverts commit fe45174b72aead678da581bab9e9a37c9b26a070.
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---
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 arch/arm/boot/dts/sun8i-h2-plus-orangepi-zero.dts |  9 ++++++++
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 arch/arm/boot/dts/sun8i-h3-bananapi-m2-plus.dts   | 19 +++++++++++++++++
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 arch/arm/boot/dts/sun8i-h3-nanopi-neo.dts         |  7 ++++++
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 arch/arm/boot/dts/sun8i-h3-orangepi-2.dts         |  8 +++++++
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 arch/arm/boot/dts/sun8i-h3-orangepi-one.dts       |  8 +++++++
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 arch/arm/boot/dts/sun8i-h3-orangepi-pc-plus.dts   |  5 +++++
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 arch/arm/boot/dts/sun8i-h3-orangepi-pc.dts        |  8 +++++++
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 arch/arm/boot/dts/sun8i-h3-orangepi-plus.dts      | 22 +++++++++++++++++++
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 arch/arm/boot/dts/sun8i-h3-orangepi-plus2e.dts    | 16 ++++++++++++++
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 arch/arm/boot/dts/sunxi-h3-h5.dtsi                | 26 +++++++++++++++++++++++
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 10 files changed, 128 insertions(+)
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diff --git a/arch/arm/boot/dts/sun8i-h2-plus-orangepi-zero.dts b/arch/arm/boot/dts/sun8i-h2-plus-orangepi-zero.dts
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index b1502df7b509..6713d0f2b3f4 100644
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--- a/arch/arm/boot/dts/sun8i-h2-plus-orangepi-zero.dts
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+++ b/arch/arm/boot/dts/sun8i-h2-plus-orangepi-zero.dts
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@@ -56,6 +56,8 @@
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 	aliases {
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 		serial0 = &uart;;
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+		/* ethernet0 is the H3 emac, defined in sun8i-h3.dtsi */
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+		ethernet0 = &emac;
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 		ethernet1 = &xr819;
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 	};
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@@ -102,6 +104,13 @@
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 	status = "okay";
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 };
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+&emac {
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+	phy-handle = <&int_mii_phy>;
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+	phy-mode = "mii";
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+	allwinner,leds-active-low;
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+	status = "okay";
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+};
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+
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 &mmc0 {
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 	pinctrl-names = "default";
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 	pinctrl-0 = <&mmc0_pins_a>;
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diff --git a/arch/arm/boot/dts/sun8i-h3-bananapi-m2-plus.dts b/arch/arm/boot/dts/sun8i-h3-bananapi-m2-plus.dts
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index a337af1de322..d756ff825116 100644
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--- a/arch/arm/boot/dts/sun8i-h3-bananapi-m2-plus.dts
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+++ b/arch/arm/boot/dts/sun8i-h3-bananapi-m2-plus.dts
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@@ -52,6 +52,7 @@
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 	compatible = "sinovoip,bpi-m2-plus", "allwinner,sun8i-h3";
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 	aliases {
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+		ethernet0 = &emac;
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 		serial0 = &uart;;
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 		serial1 = &uart;;
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 	};
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@@ -114,12 +115,30 @@
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 	status = "okay";
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 };
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+&emac {
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+	pinctrl-names = "default";
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+	pinctrl-0 = <&emac_rgmii_pins>;
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+	phy-supply = <&reg_gmac_3v3>;
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+	phy-handle = <&ext_rgmii_phy>;
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+	phy-mode = "rgmii";
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+
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+	allwinner,leds-active-low;
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+	status = "okay";
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+};
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+
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 &ir {
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 	pinctrl-names = "default";
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 	pinctrl-0 = <&ir_pins_a>;
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 	status = "okay";
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 };
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+&mdio {
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+	ext_rgmii_phy: ethernet-phy@1 {
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+		compatible = "ethernet-phy-ieee802.3-c22";
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+		reg = <0>;
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+	};
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+};
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+
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 &mmc0 {
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 	pinctrl-names = "default";
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 	pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin>;
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diff --git a/arch/arm/boot/dts/sun8i-h3-nanopi-neo.dts b/arch/arm/boot/dts/sun8i-h3-nanopi-neo.dts
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index 8d2cc6e9a03f..78f6c24952dd 100644
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--- a/arch/arm/boot/dts/sun8i-h3-nanopi-neo.dts
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+++ b/arch/arm/boot/dts/sun8i-h3-nanopi-neo.dts
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@@ -46,3 +46,10 @@
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 	model = "FriendlyARM NanoPi NEO";
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 	compatible = "friendlyarm,nanopi-neo", "allwinner,sun8i-h3";
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 };
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+
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+&emac {
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+	phy-handle = <&int_mii_phy>;
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+	phy-mode = "mii";
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+	allwinner,leds-active-low;
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+	status = "okay";
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+};
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diff --git a/arch/arm/boot/dts/sun8i-h3-orangepi-2.dts b/arch/arm/boot/dts/sun8i-h3-orangepi-2.dts
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index 8ff71b1bb45b..17cdeae19c6f 100644
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--- a/arch/arm/boot/dts/sun8i-h3-orangepi-2.dts
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+++ b/arch/arm/boot/dts/sun8i-h3-orangepi-2.dts
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@@ -54,6 +54,7 @@
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 	aliases {
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 		serial0 = &uart;;
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 		/* ethernet0 is the H3 emac, defined in sun8i-h3.dtsi */
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+		ethernet0 = &emac;
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 		ethernet1 = &rtl8189;
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 	};
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@@ -117,6 +118,13 @@
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 	status = "okay";
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 };
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+&emac {
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+	phy-handle = <&int_mii_phy>;
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+	phy-mode = "mii";
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+	allwinner,leds-active-low;
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+	status = "okay";
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+};
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+
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 &ir {
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 	pinctrl-names = "default";
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 	pinctrl-0 = <&ir_pins_a>;
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diff --git a/arch/arm/boot/dts/sun8i-h3-orangepi-one.dts b/arch/arm/boot/dts/sun8i-h3-orangepi-one.dts
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index 5fea430e0eb1..6880268e8b87 100644
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--- a/arch/arm/boot/dts/sun8i-h3-orangepi-one.dts
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+++ b/arch/arm/boot/dts/sun8i-h3-orangepi-one.dts
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@@ -52,6 +52,7 @@
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 	compatible = "xunlong,orangepi-one", "allwinner,sun8i-h3";
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 	aliases {
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+		ethernet0 = &emac;
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 		serial0 = &uart;;
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 	};
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@@ -97,6 +98,13 @@
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 	status = "okay";
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 };
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+&emac {
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+	phy-handle = <&int_mii_phy>;
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+	phy-mode = "mii";
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+	allwinner,leds-active-low;
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+	status = "okay";
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+};
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+
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 &mmc0 {
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 	pinctrl-names = "default";
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 	pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin>;
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diff --git a/arch/arm/boot/dts/sun8i-h3-orangepi-pc-plus.dts b/arch/arm/boot/dts/sun8i-h3-orangepi-pc-plus.dts
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index 8b93f5c781a7..a10281b455f5 100644
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--- a/arch/arm/boot/dts/sun8i-h3-orangepi-pc-plus.dts
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+++ b/arch/arm/boot/dts/sun8i-h3-orangepi-pc-plus.dts
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@@ -53,6 +53,11 @@
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 	};
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 };
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+&emac {
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+	/* LEDs changed to active high on the plus */
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+	/delete-property/ allwinner,leds-active-low;
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+};
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+
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 &mmc1 {
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 	pinctrl-names = "default";
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 	pinctrl-0 = <&mmc1_pins_a>;
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diff --git a/arch/arm/boot/dts/sun8i-h3-orangepi-pc.dts b/arch/arm/boot/dts/sun8i-h3-orangepi-pc.dts
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index 1a044b17d6c6..998b60f8d295 100644
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--- a/arch/arm/boot/dts/sun8i-h3-orangepi-pc.dts
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+++ b/arch/arm/boot/dts/sun8i-h3-orangepi-pc.dts
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@@ -52,6 +52,7 @@
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 	compatible = "xunlong,orangepi-pc", "allwinner,sun8i-h3";
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 	aliases {
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+		ethernet0 = &emac;
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 		serial0 = &uart;;
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 	};
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@@ -113,6 +114,13 @@
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 	status = "okay";
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 };
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+&emac {
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+	phy-handle = <&int_mii_phy>;
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+	phy-mode = "mii";
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+	allwinner,leds-active-low;
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+	status = "okay";
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+};
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+
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 &ir {
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 	pinctrl-names = "default";
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 	pinctrl-0 = <&ir_pins_a>;
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diff --git a/arch/arm/boot/dts/sun8i-h3-orangepi-plus.dts b/arch/arm/boot/dts/sun8i-h3-orangepi-plus.dts
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index 828ae7a526d9..331ed683ac62 100644
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--- a/arch/arm/boot/dts/sun8i-h3-orangepi-plus.dts
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+++ b/arch/arm/boot/dts/sun8i-h3-orangepi-plus.dts
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@@ -47,6 +47,10 @@
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 	model = "Xunlong Orange Pi Plus / Plus 2";
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 	compatible = "xunlong,orangepi-plus", "allwinner,sun8i-h3";
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+	aliases {
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+		ethernet0 = &emac;
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+	};
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+
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 	reg_gmac_3v3: gmac-3v3 {
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 		compatible = "regulator-fixed";
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 		regulator-name = "gmac-3v3";
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@@ -74,6 +78,24 @@
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 	status = "okay";
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 };
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+&emac {
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+	pinctrl-names = "default";
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+	pinctrl-0 = <&emac_rgmii_pins>;
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+	phy-supply = <&reg_gmac_3v3>;
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+	phy-handle = <&ext_rgmii_phy>;
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+	phy-mode = "rgmii";
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+
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+	allwinner,leds-active-low;
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+	status = "okay";
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+};
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+
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+&mdio {
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+	ext_rgmii_phy: ethernet-phy@1 {
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+		compatible = "ethernet-phy-ieee802.3-c22";
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+		reg = <0>;
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+	};
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+};
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+
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 &mmc2 {
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 	pinctrl-names = "default";
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 	pinctrl-0 = <&mmc2_8bit_pins>;
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diff --git a/arch/arm/boot/dts/sun8i-h3-orangepi-plus2e.dts b/arch/arm/boot/dts/sun8i-h3-orangepi-plus2e.dts
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index 97920b12a944..80026f3caafc 100644
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--- a/arch/arm/boot/dts/sun8i-h3-orangepi-plus2e.dts
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+++ b/arch/arm/boot/dts/sun8i-h3-orangepi-plus2e.dts
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@@ -61,3 +61,19 @@
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 		gpio = <&pio 3 6 GPIO_ACTIVE_HIGH>; /* PD6 */
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 	};
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 };
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+
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+&emac {
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+	pinctrl-names = "default";
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+	pinctrl-0 = <&emac_rgmii_pins>;
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+	phy-supply = <&reg_gmac_3v3>;
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+	phy-handle = <&ext_rgmii_phy>;
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+	phy-mode = "rgmii";
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+	status = "okay";
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+};
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+
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+&mdio {
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+	ext_rgmii_phy: ethernet-phy@1 {
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+		compatible = "ethernet-phy-ieee802.3-c22";
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+		reg = <1>;
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+	};
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+};
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diff --git a/arch/arm/boot/dts/sunxi-h3-h5.dtsi b/arch/arm/boot/dts/sunxi-h3-h5.dtsi
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index 11240a8313c2..d38282b9e5d4 100644
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--- a/arch/arm/boot/dts/sunxi-h3-h5.dtsi
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+++ b/arch/arm/boot/dts/sunxi-h3-h5.dtsi
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@@ -391,6 +391,32 @@
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 			clocks = <&osc24M>;
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 		};
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+		emac: ethernet@1c30000 {
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+			compatible = "allwinner,sun8i-h3-emac";
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+			syscon = <&syscon>;
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+			reg = <0x01c30000 0x10000>;
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+			interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
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+			interrupt-names = "macirq";
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+			resets = <&ccu RST_BUS_EMAC>;
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+			reset-names = "stmmaceth";
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+			clocks = <&ccu CLK_BUS_EMAC>;
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+			clock-names = "stmmaceth";
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+			#address-cells = <1>;
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+			#size-cells = <0>;
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+			status = "disabled";
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+
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+			mdio: mdio {
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+				#address-cells = <1>;
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+				#size-cells = <0>;
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+				int_mii_phy: ethernet-phy@1 {
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+					compatible = "ethernet-phy-ieee802.3-c22";
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+					reg = <1>;
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+					clocks = <&ccu CLK_BUS_EPHY>;
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+					resets = <&ccu RST_BUS_EPHY>;
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+				};
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+			};
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+		};
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+
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 		spi0: spi@01c68000 {
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 			compatible = "allwinner,sun8i-h3-spi";
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 			reg = <0x01c68000 0x1000>;
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-- 
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2.13.5
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From 11190f020b948ccdf15061b6df8cc2836a2afcb1 Mon Sep 17 00:00:00 2001
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From: Peter Robinson <pbrobinson@gmail.com>
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Date: Mon, 4 Sep 2017 13:04:55 +0100
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Subject: [PATCH 4/4] Revert "dt-bindings: net: Revert sun8i dwmac binding"
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This reverts commit 8aa33ec2f4812d1ee96f4c02ba013f5b9c514343.
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---
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 .../devicetree/bindings/net/dwmac-sun8i.txt        | 84 ++++++++++++++++++++++
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 1 file changed, 84 insertions(+)
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 create mode 100644 Documentation/devicetree/bindings/net/dwmac-sun8i.txt
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diff --git a/Documentation/devicetree/bindings/net/dwmac-sun8i.txt b/Documentation/devicetree/bindings/net/dwmac-sun8i.txt
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new file mode 100644
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index 000000000000..725f3b187886
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--- /dev/null
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+++ b/Documentation/devicetree/bindings/net/dwmac-sun8i.txt
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@@ -0,0 +1,84 @@
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+* Allwinner sun8i GMAC ethernet controller
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+
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+This device is a platform glue layer for stmmac.
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+Please see stmmac.txt for the other unchanged properties.
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+
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+Required properties:
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+- compatible: should be one of the following string:
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+		"allwinner,sun8i-a83t-emac"
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+		"allwinner,sun8i-h3-emac"
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+		"allwinner,sun8i-v3s-emac"
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+		"allwinner,sun50i-a64-emac"
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+- reg: address and length of the register for the device.
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+- interrupts: interrupt for the device
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+- interrupt-names: should be "macirq"
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+- clocks: A phandle to the reference clock for this device
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+- clock-names: should be "stmmaceth"
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+- resets: A phandle to the reset control for this device
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+- reset-names: should be "stmmaceth"
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+- phy-mode: See ethernet.txt
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+- phy-handle: See ethernet.txt
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+- #address-cells: shall be 1
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+- #size-cells: shall be 0
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+- syscon: A phandle to the syscon of the SoC with one of the following
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+ compatible string:
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+  - allwinner,sun8i-h3-system-controller
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+  - allwinner,sun8i-v3s-system-controller
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+  - allwinner,sun50i-a64-system-controller
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+  - allwinner,sun8i-a83t-system-controller
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+
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+Optional properties:
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+- allwinner,tx-delay-ps: TX clock delay chain value in ps. Range value is 0-700. Default is 0)
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+- allwinner,rx-delay-ps: RX clock delay chain value in ps. Range value is 0-3100. Default is 0)
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+Both delay properties need to be a multiple of 100. They control the delay for
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+external PHY.
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+
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+Optional properties for the following compatibles:
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+  - "allwinner,sun8i-h3-emac",
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+  - "allwinner,sun8i-v3s-emac":
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+- allwinner,leds-active-low: EPHY LEDs are active low
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+
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+Required child node of emac:
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+- mdio bus node: should be named mdio
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+
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+Required properties of the mdio node:
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+- #address-cells: shall be 1
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+- #size-cells: shall be 0
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+
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+The device node referenced by "phy" or "phy-handle" should be a child node
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+of the mdio node. See phy.txt for the generic PHY bindings.
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+
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+Required properties of the phy node with the following compatibles:
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+  - "allwinner,sun8i-h3-emac",
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+  - "allwinner,sun8i-v3s-emac":
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+- clocks: a phandle to the reference clock for the EPHY
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+- resets: a phandle to the reset control for the EPHY
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+
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+Example:
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+
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+emac: ethernet@1c0b000 {
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+	compatible = "allwinner,sun8i-h3-emac";
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+	syscon = <&syscon>;
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+	reg = <0x01c0b000 0x104>;
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+	interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
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+	interrupt-names = "macirq";
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+	resets = <&ccu RST_BUS_EMAC>;
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+	reset-names = "stmmaceth";
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+	clocks = <&ccu CLK_BUS_EMAC>;
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+	clock-names = "stmmaceth";
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+	#address-cells = <1>;
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+	#size-cells = <0>;
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+
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+	phy-handle = <&int_mii_phy>;
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+	phy-mode = "mii";
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+	allwinner,leds-active-low;
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+	mdio: mdio {
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+		#address-cells = <1>;
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+		#size-cells = <0>;
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+		int_mii_phy: ethernet-phy@1 {
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+			reg = <1>;
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+			clocks = <&ccu CLK_BUS_EPHY>;
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+			resets = <&ccu RST_BUS_EPHY>;
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+		};
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+	};
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+};
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-- 
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2.13.5
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