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From: Tom Lendacky <thomas.lendacky@amd.com>
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Date: Sat, 21 Feb 2015 12:25:12 -0500
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Subject: [PATCH] amd-xgbe-a0: Add support for XGBE on A0
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Add XGBE driver support for A0 hardware.
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Signed-off-by: Tom Lendacky <thomas.lendacky@amd.com>
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[fixup timespec -> timespec64]
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Signed-off-by: Mark Salter <msalter@redhat.com>
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---
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 drivers/net/ethernet/amd/Makefile               |    1 +
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 drivers/net/ethernet/amd/xgbe-a0/Makefile       |    8 +
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 drivers/net/ethernet/amd/xgbe-a0/xgbe-common.h  | 1142 +++++++++
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 drivers/net/ethernet/amd/xgbe-a0/xgbe-dcb.c     |  269 +++
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 drivers/net/ethernet/amd/xgbe-a0/xgbe-debugfs.c |  373 +++
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 drivers/net/ethernet/amd/xgbe-a0/xgbe-desc.c    |  636 +++++
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 drivers/net/ethernet/amd/xgbe-a0/xgbe-dev.c     | 2930 +++++++++++++++++++++++
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 drivers/net/ethernet/amd/xgbe-a0/xgbe-drv.c     | 2218 +++++++++++++++++
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 drivers/net/ethernet/amd/xgbe-a0/xgbe-ethtool.c |  616 +++++
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 drivers/net/ethernet/amd/xgbe-a0/xgbe-main.c    |  643 +++++
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 drivers/net/ethernet/amd/xgbe-a0/xgbe-mdio.c    |  312 +++
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 drivers/net/ethernet/amd/xgbe-a0/xgbe-ptp.c     |  278 +++
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 drivers/net/ethernet/amd/xgbe-a0/xgbe.h         |  868 +++++++
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 13 files changed, 10294 insertions(+)
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 create mode 100644 drivers/net/ethernet/amd/xgbe-a0/Makefile
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 create mode 100644 drivers/net/ethernet/amd/xgbe-a0/xgbe-common.h
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 create mode 100644 drivers/net/ethernet/amd/xgbe-a0/xgbe-dcb.c
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 create mode 100644 drivers/net/ethernet/amd/xgbe-a0/xgbe-debugfs.c
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 create mode 100644 drivers/net/ethernet/amd/xgbe-a0/xgbe-desc.c
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 create mode 100644 drivers/net/ethernet/amd/xgbe-a0/xgbe-dev.c
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 create mode 100644 drivers/net/ethernet/amd/xgbe-a0/xgbe-drv.c
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 create mode 100644 drivers/net/ethernet/amd/xgbe-a0/xgbe-ethtool.c
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 create mode 100644 drivers/net/ethernet/amd/xgbe-a0/xgbe-main.c
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 create mode 100644 drivers/net/ethernet/amd/xgbe-a0/xgbe-mdio.c
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 create mode 100644 drivers/net/ethernet/amd/xgbe-a0/xgbe-ptp.c
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 create mode 100644 drivers/net/ethernet/amd/xgbe-a0/xgbe.h
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diff --git a/drivers/net/ethernet/amd/Makefile b/drivers/net/ethernet/amd/Makefile
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index a38a2dce3eb3..bf0cf2f8d2db 100644
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--- a/drivers/net/ethernet/amd/Makefile
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+++ b/drivers/net/ethernet/amd/Makefile
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@@ -18,3 +18,4 @@ obj-$(CONFIG_PCNET32) += pcnet32.o
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 obj-$(CONFIG_SUN3LANCE) += sun3lance.o
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 obj-$(CONFIG_SUNLANCE) += sunlance.o
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 obj-$(CONFIG_AMD_XGBE) += xgbe/
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+obj-$(CONFIG_AMD_XGBE) += xgbe-a0/
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diff --git a/drivers/net/ethernet/amd/xgbe-a0/Makefile b/drivers/net/ethernet/amd/xgbe-a0/Makefile
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new file mode 100644
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index 000000000000..561116faadae
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--- /dev/null
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+++ b/drivers/net/ethernet/amd/xgbe-a0/Makefile
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@@ -0,0 +1,8 @@
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+obj-$(CONFIG_AMD_XGBE) += amd-xgbe-a0.o
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+
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+amd-xgbe-a0-objs := xgbe-main.o xgbe-drv.o xgbe-dev.o \
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+		 xgbe-desc.o xgbe-ethtool.o xgbe-mdio.o \
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+		 xgbe-ptp.o
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+
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+amd-xgbe-a0-$(CONFIG_AMD_XGBE_DCB) += xgbe-dcb.o
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+amd-xgbe-a0-$(CONFIG_DEBUG_FS) += xgbe-debugfs.o
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diff --git a/drivers/net/ethernet/amd/xgbe-a0/xgbe-common.h b/drivers/net/ethernet/amd/xgbe-a0/xgbe-common.h
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new file mode 100644
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index 000000000000..75b08c63d39f
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--- /dev/null
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+++ b/drivers/net/ethernet/amd/xgbe-a0/xgbe-common.h
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@@ -0,0 +1,1142 @@
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+/*
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+ * AMD 10Gb Ethernet driver
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+ *
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+ * This file is available to you under your choice of the following two
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+ * licenses:
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+ *
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+ * License 1: GPLv2
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+ *
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+ * Copyright (c) 2014 Advanced Micro Devices, Inc.
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+ *
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+ * This file is free software; you may copy, redistribute and/or modify
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+ * it under the terms of the GNU General Public License as published by
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+ * the Free Software Foundation, either version 2 of the License, or (at
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+ * your option) any later version.
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+ *
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+ * This file is distributed in the hope that it will be useful, but
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+ * WITHOUT ANY WARRANTY; without even the implied warranty of
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+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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+ * General Public License for more details.
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+ *
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+ * You should have received a copy of the GNU General Public License
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+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
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+ *
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+ * This file incorporates work covered by the following copyright and
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+ * permission notice:
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+ *     The Synopsys DWC ETHER XGMAC Software Driver and documentation
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+ *     (hereinafter "Software") is an unsupported proprietary work of Synopsys,
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+ *     Inc. unless otherwise expressly agreed to in writing between Synopsys
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+ *     and you.
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+ *
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+ *     The Software IS NOT an item of Licensed Software or Licensed Product
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+ *     under any End User Software License Agreement or Agreement for Licensed
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+ *     Product with Synopsys or any supplement thereto.  Permission is hereby
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+ *     granted, free of charge, to any person obtaining a copy of this software
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+ *     annotated with this license and the Software, to deal in the Software
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+ *     without restriction, including without limitation the rights to use,
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+ *     copy, modify, merge, publish, distribute, sublicense, and/or sell copies
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+ *     of the Software, and to permit persons to whom the Software is furnished
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+ *     to do so, subject to the following conditions:
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+ *
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+ *     The above copyright notice and this permission notice shall be included
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+ *     in all copies or substantial portions of the Software.
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+ *
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+ *     THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS"
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+ *     BASIS AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
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+ *     TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
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+ *     PARTICULAR PURPOSE ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS
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+ *     BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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+ *     CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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+ *     SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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+ *     INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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+ *     CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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+ *     ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
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+ *     THE POSSIBILITY OF SUCH DAMAGE.
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+ *
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+ *
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+ * License 2: Modified BSD
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+ *
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+ * Copyright (c) 2014 Advanced Micro Devices, Inc.
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+ * All rights reserved.
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+ *
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+ * Redistribution and use in source and binary forms, with or without
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+ * modification, are permitted provided that the following conditions are met:
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+ *     * Redistributions of source code must retain the above copyright
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+ *       notice, this list of conditions and the following disclaimer.
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+ *     * Redistributions in binary form must reproduce the above copyright
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+ *       notice, this list of conditions and the following disclaimer in the
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+ *       documentation and/or other materials provided with the distribution.
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+ *     * Neither the name of Advanced Micro Devices, Inc. nor the
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+ *       names of its contributors may be used to endorse or promote products
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+ *       derived from this software without specific prior written permission.
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+ *
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+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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+ * ARE DISCLAIMED. IN NO EVENT SHALL <COPYRIGHT HOLDER> BE LIABLE FOR ANY
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+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
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+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
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+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
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+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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+ *
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+ * This file incorporates work covered by the following copyright and
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+ * permission notice:
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+ *     The Synopsys DWC ETHER XGMAC Software Driver and documentation
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+ *     (hereinafter "Software") is an unsupported proprietary work of Synopsys,
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+ *     Inc. unless otherwise expressly agreed to in writing between Synopsys
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+ *     and you.
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+ *
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+ *     The Software IS NOT an item of Licensed Software or Licensed Product
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+ *     under any End User Software License Agreement or Agreement for Licensed
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+ *     Product with Synopsys or any supplement thereto.  Permission is hereby
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+ *     granted, free of charge, to any person obtaining a copy of this software
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+ *     annotated with this license and the Software, to deal in the Software
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+ *     without restriction, including without limitation the rights to use,
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+ *     copy, modify, merge, publish, distribute, sublicense, and/or sell copies
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+ *     of the Software, and to permit persons to whom the Software is furnished
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+ *     to do so, subject to the following conditions:
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+ *
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+ *     The above copyright notice and this permission notice shall be included
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+ *     in all copies or substantial portions of the Software.
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+ *
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+ *     THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS"
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+ *     BASIS AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
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+ *     TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
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+ *     PARTICULAR PURPOSE ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS
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+ *     BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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+ *     CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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+ *     SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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+ *     INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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+ *     CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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+ *     ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
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+ *     THE POSSIBILITY OF SUCH DAMAGE.
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+ */
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+
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+#ifndef __XGBE_COMMON_H__
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+#define __XGBE_COMMON_H__
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+
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+/* DMA register offsets */
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+#define DMA_MR				0x3000
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+#define DMA_SBMR			0x3004
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+#define DMA_ISR				0x3008
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+#define DMA_AXIARCR			0x3010
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+#define DMA_AXIAWCR			0x3018
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+#define DMA_DSR0			0x3020
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+#define DMA_DSR1			0x3024
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+
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+/* DMA register entry bit positions and sizes */
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+#define DMA_AXIARCR_DRC_INDEX		0
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+#define DMA_AXIARCR_DRC_WIDTH		4
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+#define DMA_AXIARCR_DRD_INDEX		4
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+#define DMA_AXIARCR_DRD_WIDTH		2
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+#define DMA_AXIARCR_TEC_INDEX		8
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+#define DMA_AXIARCR_TEC_WIDTH		4
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+#define DMA_AXIARCR_TED_INDEX		12
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+#define DMA_AXIARCR_TED_WIDTH		2
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+#define DMA_AXIARCR_THC_INDEX		16
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+#define DMA_AXIARCR_THC_WIDTH		4
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+#define DMA_AXIARCR_THD_INDEX		20
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+#define DMA_AXIARCR_THD_WIDTH		2
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+#define DMA_AXIAWCR_DWC_INDEX		0
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+#define DMA_AXIAWCR_DWC_WIDTH		4
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+#define DMA_AXIAWCR_DWD_INDEX		4
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+#define DMA_AXIAWCR_DWD_WIDTH		2
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+#define DMA_AXIAWCR_RPC_INDEX		8
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+#define DMA_AXIAWCR_RPC_WIDTH		4
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+#define DMA_AXIAWCR_RPD_INDEX		12
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+#define DMA_AXIAWCR_RPD_WIDTH		2
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+#define DMA_AXIAWCR_RHC_INDEX		16
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+#define DMA_AXIAWCR_RHC_WIDTH		4
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+#define DMA_AXIAWCR_RHD_INDEX		20
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+#define DMA_AXIAWCR_RHD_WIDTH		2
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+#define DMA_AXIAWCR_TDC_INDEX		24
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+#define DMA_AXIAWCR_TDC_WIDTH		4
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+#define DMA_AXIAWCR_TDD_INDEX		28
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+#define DMA_AXIAWCR_TDD_WIDTH		2
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+#define DMA_ISR_MACIS_INDEX		17
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+#define DMA_ISR_MACIS_WIDTH		1
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+#define DMA_ISR_MTLIS_INDEX		16
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+#define DMA_ISR_MTLIS_WIDTH		1
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+#define DMA_MR_SWR_INDEX		0
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+#define DMA_MR_SWR_WIDTH		1
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+#define DMA_SBMR_EAME_INDEX		11
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+#define DMA_SBMR_EAME_WIDTH		1
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+#define DMA_SBMR_BLEN_256_INDEX		7
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+#define DMA_SBMR_BLEN_256_WIDTH		1
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+#define DMA_SBMR_UNDEF_INDEX		0
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+#define DMA_SBMR_UNDEF_WIDTH		1
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+
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+/* DMA register values */
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+#define DMA_DSR_RPS_WIDTH		4
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+#define DMA_DSR_TPS_WIDTH		4
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+#define DMA_DSR_Q_WIDTH			(DMA_DSR_RPS_WIDTH + DMA_DSR_TPS_WIDTH)
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+#define DMA_DSR0_RPS_START		8
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+#define DMA_DSR0_TPS_START		12
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+#define DMA_DSRX_FIRST_QUEUE		3
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+#define DMA_DSRX_INC			4
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+#define DMA_DSRX_QPR			4
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+#define DMA_DSRX_RPS_START		0
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+#define DMA_DSRX_TPS_START		4
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+#define DMA_TPS_STOPPED			0x00
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+#define DMA_TPS_SUSPENDED		0x06
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+
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+/* DMA channel register offsets
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+ *   Multiple channels can be active.  The first channel has registers
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+ *   that begin at 0x3100.  Each subsequent channel has registers that
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+ *   are accessed using an offset of 0x80 from the previous channel.
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+ */
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+#define DMA_CH_BASE			0x3100
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+#define DMA_CH_INC			0x80
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+
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+#define DMA_CH_CR			0x00
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+#define DMA_CH_TCR			0x04
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+#define DMA_CH_RCR			0x08
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+#define DMA_CH_TDLR_HI			0x10
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+#define DMA_CH_TDLR_LO			0x14
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+#define DMA_CH_RDLR_HI			0x18
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+#define DMA_CH_RDLR_LO			0x1c
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+#define DMA_CH_TDTR_LO			0x24
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+#define DMA_CH_RDTR_LO			0x2c
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+#define DMA_CH_TDRLR			0x30
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+#define DMA_CH_RDRLR			0x34
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+#define DMA_CH_IER			0x38
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+#define DMA_CH_RIWT			0x3c
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+#define DMA_CH_CATDR_LO			0x44
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+#define DMA_CH_CARDR_LO			0x4c
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+#define DMA_CH_CATBR_HI			0x50
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+#define DMA_CH_CATBR_LO			0x54
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+#define DMA_CH_CARBR_HI			0x58
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+#define DMA_CH_CARBR_LO			0x5c
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+#define DMA_CH_SR			0x60
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+
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+/* DMA channel register entry bit positions and sizes */
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+#define DMA_CH_CR_PBLX8_INDEX		16
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+#define DMA_CH_CR_PBLX8_WIDTH		1
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+#define DMA_CH_CR_SPH_INDEX		24
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+#define DMA_CH_CR_SPH_WIDTH		1
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+#define DMA_CH_IER_AIE_INDEX		15
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+#define DMA_CH_IER_AIE_WIDTH		1
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+#define DMA_CH_IER_FBEE_INDEX		12
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+#define DMA_CH_IER_FBEE_WIDTH		1
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+#define DMA_CH_IER_NIE_INDEX		16
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+#define DMA_CH_IER_NIE_WIDTH		1
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+#define DMA_CH_IER_RBUE_INDEX		7
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+#define DMA_CH_IER_RBUE_WIDTH		1
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+#define DMA_CH_IER_RIE_INDEX		6
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+#define DMA_CH_IER_RIE_WIDTH		1
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+#define DMA_CH_IER_RSE_INDEX		8
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+#define DMA_CH_IER_RSE_WIDTH		1
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+#define DMA_CH_IER_TBUE_INDEX		2
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+#define DMA_CH_IER_TBUE_WIDTH		1
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+#define DMA_CH_IER_TIE_INDEX		0
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+#define DMA_CH_IER_TIE_WIDTH		1
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+#define DMA_CH_IER_TXSE_INDEX		1
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+#define DMA_CH_IER_TXSE_WIDTH		1
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+#define DMA_CH_RCR_PBL_INDEX		16
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+#define DMA_CH_RCR_PBL_WIDTH		6
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+#define DMA_CH_RCR_RBSZ_INDEX		1
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+#define DMA_CH_RCR_RBSZ_WIDTH		14
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+#define DMA_CH_RCR_SR_INDEX		0
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+#define DMA_CH_RCR_SR_WIDTH		1
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+#define DMA_CH_RIWT_RWT_INDEX		0
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+#define DMA_CH_RIWT_RWT_WIDTH		8
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+#define DMA_CH_SR_FBE_INDEX		12
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+#define DMA_CH_SR_FBE_WIDTH		1
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+#define DMA_CH_SR_RBU_INDEX		7
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+#define DMA_CH_SR_RBU_WIDTH		1
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+#define DMA_CH_SR_RI_INDEX		6
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+#define DMA_CH_SR_RI_WIDTH		1
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+#define DMA_CH_SR_RPS_INDEX		8
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+#define DMA_CH_SR_RPS_WIDTH		1
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+#define DMA_CH_SR_TBU_INDEX		2
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+#define DMA_CH_SR_TBU_WIDTH		1
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+#define DMA_CH_SR_TI_INDEX		0
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+#define DMA_CH_SR_TI_WIDTH		1
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+#define DMA_CH_SR_TPS_INDEX		1
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+#define DMA_CH_SR_TPS_WIDTH		1
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+#define DMA_CH_TCR_OSP_INDEX		4
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+#define DMA_CH_TCR_OSP_WIDTH		1
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+#define DMA_CH_TCR_PBL_INDEX		16
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+#define DMA_CH_TCR_PBL_WIDTH		6
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+#define DMA_CH_TCR_ST_INDEX		0
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+#define DMA_CH_TCR_ST_WIDTH		1
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+#define DMA_CH_TCR_TSE_INDEX		12
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+#define DMA_CH_TCR_TSE_WIDTH		1
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+
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+/* DMA channel register values */
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+#define DMA_OSP_DISABLE			0x00
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+#define DMA_OSP_ENABLE			0x01
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+#define DMA_PBL_1			1
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+#define DMA_PBL_2			2
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+#define DMA_PBL_4			4
1b5309d
+#define DMA_PBL_8			8
1b5309d
+#define DMA_PBL_16			16
1b5309d
+#define DMA_PBL_32			32
1b5309d
+#define DMA_PBL_64			64      /* 8 x 8 */
1b5309d
+#define DMA_PBL_128			128     /* 8 x 16 */
1b5309d
+#define DMA_PBL_256			256     /* 8 x 32 */
1b5309d
+#define DMA_PBL_X8_DISABLE		0x00
1b5309d
+#define DMA_PBL_X8_ENABLE		0x01
1b5309d
+
1b5309d
+/* MAC register offsets */
1b5309d
+#define MAC_TCR				0x0000
1b5309d
+#define MAC_RCR				0x0004
1b5309d
+#define MAC_PFR				0x0008
1b5309d
+#define MAC_WTR				0x000c
1b5309d
+#define MAC_HTR0			0x0010
1b5309d
+#define MAC_VLANTR			0x0050
1b5309d
+#define MAC_VLANHTR			0x0058
1b5309d
+#define MAC_VLANIR			0x0060
1b5309d
+#define MAC_IVLANIR			0x0064
1b5309d
+#define MAC_RETMR			0x006c
1b5309d
+#define MAC_Q0TFCR			0x0070
1b5309d
+#define MAC_RFCR			0x0090
1b5309d
+#define MAC_RQC0R			0x00a0
1b5309d
+#define MAC_RQC1R			0x00a4
1b5309d
+#define MAC_RQC2R			0x00a8
1b5309d
+#define MAC_RQC3R			0x00ac
1b5309d
+#define MAC_ISR				0x00b0
1b5309d
+#define MAC_IER				0x00b4
1b5309d
+#define MAC_RTSR			0x00b8
1b5309d
+#define MAC_PMTCSR			0x00c0
1b5309d
+#define MAC_RWKPFR			0x00c4
1b5309d
+#define MAC_LPICSR			0x00d0
1b5309d
+#define MAC_LPITCR			0x00d4
1b5309d
+#define MAC_VR				0x0110
1b5309d
+#define MAC_DR				0x0114
1b5309d
+#define MAC_HWF0R			0x011c
1b5309d
+#define MAC_HWF1R			0x0120
1b5309d
+#define MAC_HWF2R			0x0124
1b5309d
+#define MAC_GPIOCR			0x0278
1b5309d
+#define MAC_GPIOSR			0x027c
1b5309d
+#define MAC_MACA0HR			0x0300
1b5309d
+#define MAC_MACA0LR			0x0304
1b5309d
+#define MAC_MACA1HR			0x0308
1b5309d
+#define MAC_MACA1LR			0x030c
1b5309d
+#define MAC_RSSCR			0x0c80
1b5309d
+#define MAC_RSSAR			0x0c88
1b5309d
+#define MAC_RSSDR			0x0c8c
1b5309d
+#define MAC_TSCR			0x0d00
1b5309d
+#define MAC_SSIR			0x0d04
1b5309d
+#define MAC_STSR			0x0d08
1b5309d
+#define MAC_STNR			0x0d0c
1b5309d
+#define MAC_STSUR			0x0d10
1b5309d
+#define MAC_STNUR			0x0d14
1b5309d
+#define MAC_TSAR			0x0d18
1b5309d
+#define MAC_TSSR			0x0d20
1b5309d
+#define MAC_TXSNR			0x0d30
1b5309d
+#define MAC_TXSSR			0x0d34
1b5309d
+
1b5309d
+#define MAC_QTFCR_INC			4
1b5309d
+#define MAC_MACA_INC			4
1b5309d
+#define MAC_HTR_INC			4
1b5309d
+
1b5309d
+#define MAC_RQC2_INC			4
1b5309d
+#define MAC_RQC2_Q_PER_REG		4
1b5309d
+
1b5309d
+/* MAC register entry bit positions and sizes */
1b5309d
+#define MAC_HWF0R_ADDMACADRSEL_INDEX	18
1b5309d
+#define MAC_HWF0R_ADDMACADRSEL_WIDTH	5
1b5309d
+#define MAC_HWF0R_ARPOFFSEL_INDEX	9
1b5309d
+#define MAC_HWF0R_ARPOFFSEL_WIDTH	1
1b5309d
+#define MAC_HWF0R_EEESEL_INDEX		13
1b5309d
+#define MAC_HWF0R_EEESEL_WIDTH		1
1b5309d
+#define MAC_HWF0R_GMIISEL_INDEX		1
1b5309d
+#define MAC_HWF0R_GMIISEL_WIDTH		1
1b5309d
+#define MAC_HWF0R_MGKSEL_INDEX		7
1b5309d
+#define MAC_HWF0R_MGKSEL_WIDTH		1
1b5309d
+#define MAC_HWF0R_MMCSEL_INDEX		8
1b5309d
+#define MAC_HWF0R_MMCSEL_WIDTH		1
1b5309d
+#define MAC_HWF0R_RWKSEL_INDEX		6
1b5309d
+#define MAC_HWF0R_RWKSEL_WIDTH		1
1b5309d
+#define MAC_HWF0R_RXCOESEL_INDEX	16
1b5309d
+#define MAC_HWF0R_RXCOESEL_WIDTH	1
1b5309d
+#define MAC_HWF0R_SAVLANINS_INDEX	27
1b5309d
+#define MAC_HWF0R_SAVLANINS_WIDTH	1
1b5309d
+#define MAC_HWF0R_SMASEL_INDEX		5
1b5309d
+#define MAC_HWF0R_SMASEL_WIDTH		1
1b5309d
+#define MAC_HWF0R_TSSEL_INDEX		12
1b5309d
+#define MAC_HWF0R_TSSEL_WIDTH		1
1b5309d
+#define MAC_HWF0R_TSSTSSEL_INDEX	25
1b5309d
+#define MAC_HWF0R_TSSTSSEL_WIDTH	2
1b5309d
+#define MAC_HWF0R_TXCOESEL_INDEX	14
1b5309d
+#define MAC_HWF0R_TXCOESEL_WIDTH	1
1b5309d
+#define MAC_HWF0R_VLHASH_INDEX		4
1b5309d
+#define MAC_HWF0R_VLHASH_WIDTH		1
1b5309d
+#define MAC_HWF1R_ADVTHWORD_INDEX	13
1b5309d
+#define MAC_HWF1R_ADVTHWORD_WIDTH	1
1b5309d
+#define MAC_HWF1R_DBGMEMA_INDEX		19
1b5309d
+#define MAC_HWF1R_DBGMEMA_WIDTH		1
1b5309d
+#define MAC_HWF1R_DCBEN_INDEX		16
1b5309d
+#define MAC_HWF1R_DCBEN_WIDTH		1
1b5309d
+#define MAC_HWF1R_HASHTBLSZ_INDEX	24
1b5309d
+#define MAC_HWF1R_HASHTBLSZ_WIDTH	3
1b5309d
+#define MAC_HWF1R_L3L4FNUM_INDEX	27
1b5309d
+#define MAC_HWF1R_L3L4FNUM_WIDTH	4
1b5309d
+#define MAC_HWF1R_NUMTC_INDEX		21
1b5309d
+#define MAC_HWF1R_NUMTC_WIDTH		3
1b5309d
+#define MAC_HWF1R_RSSEN_INDEX		20
1b5309d
+#define MAC_HWF1R_RSSEN_WIDTH		1
1b5309d
+#define MAC_HWF1R_RXFIFOSIZE_INDEX	0
1b5309d
+#define MAC_HWF1R_RXFIFOSIZE_WIDTH	5
1b5309d
+#define MAC_HWF1R_SPHEN_INDEX		17
1b5309d
+#define MAC_HWF1R_SPHEN_WIDTH		1
1b5309d
+#define MAC_HWF1R_TSOEN_INDEX		18
1b5309d
+#define MAC_HWF1R_TSOEN_WIDTH		1
1b5309d
+#define MAC_HWF1R_TXFIFOSIZE_INDEX	6
1b5309d
+#define MAC_HWF1R_TXFIFOSIZE_WIDTH	5
1b5309d
+#define MAC_HWF2R_AUXSNAPNUM_INDEX	28
1b5309d
+#define MAC_HWF2R_AUXSNAPNUM_WIDTH	3
1b5309d
+#define MAC_HWF2R_PPSOUTNUM_INDEX	24
1b5309d
+#define MAC_HWF2R_PPSOUTNUM_WIDTH	3
1b5309d
+#define MAC_HWF2R_RXCHCNT_INDEX		12
1b5309d
+#define MAC_HWF2R_RXCHCNT_WIDTH		4
1b5309d
+#define MAC_HWF2R_RXQCNT_INDEX		0
1b5309d
+#define MAC_HWF2R_RXQCNT_WIDTH		4
1b5309d
+#define MAC_HWF2R_TXCHCNT_INDEX		18
1b5309d
+#define MAC_HWF2R_TXCHCNT_WIDTH		4
1b5309d
+#define MAC_HWF2R_TXQCNT_INDEX		6
1b5309d
+#define MAC_HWF2R_TXQCNT_WIDTH		4
1b5309d
+#define MAC_IER_TSIE_INDEX		12
1b5309d
+#define MAC_IER_TSIE_WIDTH		1
1b5309d
+#define MAC_ISR_MMCRXIS_INDEX		9
1b5309d
+#define MAC_ISR_MMCRXIS_WIDTH		1
1b5309d
+#define MAC_ISR_MMCTXIS_INDEX		10
1b5309d
+#define MAC_ISR_MMCTXIS_WIDTH		1
1b5309d
+#define MAC_ISR_PMTIS_INDEX		4
1b5309d
+#define MAC_ISR_PMTIS_WIDTH		1
1b5309d
+#define MAC_ISR_TSIS_INDEX		12
1b5309d
+#define MAC_ISR_TSIS_WIDTH		1
1b5309d
+#define MAC_MACA1HR_AE_INDEX		31
1b5309d
+#define MAC_MACA1HR_AE_WIDTH		1
1b5309d
+#define MAC_PFR_HMC_INDEX		2
1b5309d
+#define MAC_PFR_HMC_WIDTH		1
1b5309d
+#define MAC_PFR_HPF_INDEX		10
1b5309d
+#define MAC_PFR_HPF_WIDTH		1
1b5309d
+#define MAC_PFR_HUC_INDEX		1
1b5309d
+#define MAC_PFR_HUC_WIDTH		1
1b5309d
+#define MAC_PFR_PM_INDEX		4
1b5309d
+#define MAC_PFR_PM_WIDTH		1
1b5309d
+#define MAC_PFR_PR_INDEX		0
1b5309d
+#define MAC_PFR_PR_WIDTH		1
1b5309d
+#define MAC_PFR_VTFE_INDEX		16
1b5309d
+#define MAC_PFR_VTFE_WIDTH		1
1b5309d
+#define MAC_PMTCSR_MGKPKTEN_INDEX	1
1b5309d
+#define MAC_PMTCSR_MGKPKTEN_WIDTH	1
1b5309d
+#define MAC_PMTCSR_PWRDWN_INDEX		0
1b5309d
+#define MAC_PMTCSR_PWRDWN_WIDTH		1
1b5309d
+#define MAC_PMTCSR_RWKFILTRST_INDEX	31
1b5309d
+#define MAC_PMTCSR_RWKFILTRST_WIDTH	1
1b5309d
+#define MAC_PMTCSR_RWKPKTEN_INDEX	2
1b5309d
+#define MAC_PMTCSR_RWKPKTEN_WIDTH	1
1b5309d
+#define MAC_Q0TFCR_PT_INDEX		16
1b5309d
+#define MAC_Q0TFCR_PT_WIDTH		16
1b5309d
+#define MAC_Q0TFCR_TFE_INDEX		1
1b5309d
+#define MAC_Q0TFCR_TFE_WIDTH		1
1b5309d
+#define MAC_RCR_ACS_INDEX		1
1b5309d
+#define MAC_RCR_ACS_WIDTH		1
1b5309d
+#define MAC_RCR_CST_INDEX		2
1b5309d
+#define MAC_RCR_CST_WIDTH		1
1b5309d
+#define MAC_RCR_DCRCC_INDEX		3
1b5309d
+#define MAC_RCR_DCRCC_WIDTH		1
1b5309d
+#define MAC_RCR_HDSMS_INDEX		12
1b5309d
+#define MAC_RCR_HDSMS_WIDTH		3
1b5309d
+#define MAC_RCR_IPC_INDEX		9
1b5309d
+#define MAC_RCR_IPC_WIDTH		1
1b5309d
+#define MAC_RCR_JE_INDEX		8
1b5309d
+#define MAC_RCR_JE_WIDTH		1
1b5309d
+#define MAC_RCR_LM_INDEX		10
1b5309d
+#define MAC_RCR_LM_WIDTH		1
1b5309d
+#define MAC_RCR_RE_INDEX		0
1b5309d
+#define MAC_RCR_RE_WIDTH		1
1b5309d
+#define MAC_RFCR_PFCE_INDEX		8
1b5309d
+#define MAC_RFCR_PFCE_WIDTH		1
1b5309d
+#define MAC_RFCR_RFE_INDEX		0
1b5309d
+#define MAC_RFCR_RFE_WIDTH		1
1b5309d
+#define MAC_RFCR_UP_INDEX		1
1b5309d
+#define MAC_RFCR_UP_WIDTH		1
1b5309d
+#define MAC_RQC0R_RXQ0EN_INDEX		0
1b5309d
+#define MAC_RQC0R_RXQ0EN_WIDTH		2
1b5309d
+#define MAC_RSSAR_ADDRT_INDEX		2
1b5309d
+#define MAC_RSSAR_ADDRT_WIDTH		1
1b5309d
+#define MAC_RSSAR_CT_INDEX		1
1b5309d
+#define MAC_RSSAR_CT_WIDTH		1
1b5309d
+#define MAC_RSSAR_OB_INDEX		0
1b5309d
+#define MAC_RSSAR_OB_WIDTH		1
1b5309d
+#define MAC_RSSAR_RSSIA_INDEX		8
1b5309d
+#define MAC_RSSAR_RSSIA_WIDTH		8
1b5309d
+#define MAC_RSSCR_IP2TE_INDEX		1
1b5309d
+#define MAC_RSSCR_IP2TE_WIDTH		1
1b5309d
+#define MAC_RSSCR_RSSE_INDEX		0
1b5309d
+#define MAC_RSSCR_RSSE_WIDTH		1
1b5309d
+#define MAC_RSSCR_TCP4TE_INDEX		2
1b5309d
+#define MAC_RSSCR_TCP4TE_WIDTH		1
1b5309d
+#define MAC_RSSCR_UDP4TE_INDEX		3
1b5309d
+#define MAC_RSSCR_UDP4TE_WIDTH		1
1b5309d
+#define MAC_RSSDR_DMCH_INDEX		0
1b5309d
+#define MAC_RSSDR_DMCH_WIDTH		4
1b5309d
+#define MAC_SSIR_SNSINC_INDEX		8
1b5309d
+#define MAC_SSIR_SNSINC_WIDTH		8
1b5309d
+#define MAC_SSIR_SSINC_INDEX		16
1b5309d
+#define MAC_SSIR_SSINC_WIDTH		8
1b5309d
+#define MAC_TCR_SS_INDEX		29
1b5309d
+#define MAC_TCR_SS_WIDTH		2
1b5309d
+#define MAC_TCR_TE_INDEX		0
1b5309d
+#define MAC_TCR_TE_WIDTH		1
1b5309d
+#define MAC_TSCR_AV8021ASMEN_INDEX	28
1b5309d
+#define MAC_TSCR_AV8021ASMEN_WIDTH	1
1b5309d
+#define MAC_TSCR_SNAPTYPSEL_INDEX	16
1b5309d
+#define MAC_TSCR_SNAPTYPSEL_WIDTH	2
1b5309d
+#define MAC_TSCR_TSADDREG_INDEX		5
1b5309d
+#define MAC_TSCR_TSADDREG_WIDTH		1
1b5309d
+#define MAC_TSCR_TSCFUPDT_INDEX		1
1b5309d
+#define MAC_TSCR_TSCFUPDT_WIDTH		1
1b5309d
+#define MAC_TSCR_TSCTRLSSR_INDEX	9
1b5309d
+#define MAC_TSCR_TSCTRLSSR_WIDTH	1
1b5309d
+#define MAC_TSCR_TSENA_INDEX		0
1b5309d
+#define MAC_TSCR_TSENA_WIDTH		1
1b5309d
+#define MAC_TSCR_TSENALL_INDEX		8
1b5309d
+#define MAC_TSCR_TSENALL_WIDTH		1
1b5309d
+#define MAC_TSCR_TSEVNTENA_INDEX	14
1b5309d
+#define MAC_TSCR_TSEVNTENA_WIDTH	1
1b5309d
+#define MAC_TSCR_TSINIT_INDEX		2
1b5309d
+#define MAC_TSCR_TSINIT_WIDTH		1
1b5309d
+#define MAC_TSCR_TSIPENA_INDEX		11
1b5309d
+#define MAC_TSCR_TSIPENA_WIDTH		1
1b5309d
+#define MAC_TSCR_TSIPV4ENA_INDEX	13
1b5309d
+#define MAC_TSCR_TSIPV4ENA_WIDTH	1
1b5309d
+#define MAC_TSCR_TSIPV6ENA_INDEX	12
1b5309d
+#define MAC_TSCR_TSIPV6ENA_WIDTH	1
1b5309d
+#define MAC_TSCR_TSMSTRENA_INDEX	15
1b5309d
+#define MAC_TSCR_TSMSTRENA_WIDTH	1
1b5309d
+#define MAC_TSCR_TSVER2ENA_INDEX	10
1b5309d
+#define MAC_TSCR_TSVER2ENA_WIDTH	1
1b5309d
+#define MAC_TSCR_TXTSSTSM_INDEX		24
1b5309d
+#define MAC_TSCR_TXTSSTSM_WIDTH		1
1b5309d
+#define MAC_TSSR_TXTSC_INDEX		15
1b5309d
+#define MAC_TSSR_TXTSC_WIDTH		1
1b5309d
+#define MAC_TXSNR_TXTSSTSMIS_INDEX	31
1b5309d
+#define MAC_TXSNR_TXTSSTSMIS_WIDTH	1
1b5309d
+#define MAC_VLANHTR_VLHT_INDEX		0
1b5309d
+#define MAC_VLANHTR_VLHT_WIDTH		16
1b5309d
+#define MAC_VLANIR_VLTI_INDEX		20
1b5309d
+#define MAC_VLANIR_VLTI_WIDTH		1
1b5309d
+#define MAC_VLANIR_CSVL_INDEX		19
1b5309d
+#define MAC_VLANIR_CSVL_WIDTH		1
1b5309d
+#define MAC_VLANTR_DOVLTC_INDEX		20
1b5309d
+#define MAC_VLANTR_DOVLTC_WIDTH		1
1b5309d
+#define MAC_VLANTR_ERSVLM_INDEX		19
1b5309d
+#define MAC_VLANTR_ERSVLM_WIDTH		1
1b5309d
+#define MAC_VLANTR_ESVL_INDEX		18
1b5309d
+#define MAC_VLANTR_ESVL_WIDTH		1
1b5309d
+#define MAC_VLANTR_ETV_INDEX		16
1b5309d
+#define MAC_VLANTR_ETV_WIDTH		1
1b5309d
+#define MAC_VLANTR_EVLS_INDEX		21
1b5309d
+#define MAC_VLANTR_EVLS_WIDTH		2
1b5309d
+#define MAC_VLANTR_EVLRXS_INDEX		24
1b5309d
+#define MAC_VLANTR_EVLRXS_WIDTH		1
1b5309d
+#define MAC_VLANTR_VL_INDEX		0
1b5309d
+#define MAC_VLANTR_VL_WIDTH		16
1b5309d
+#define MAC_VLANTR_VTHM_INDEX		25
1b5309d
+#define MAC_VLANTR_VTHM_WIDTH		1
1b5309d
+#define MAC_VLANTR_VTIM_INDEX		17
1b5309d
+#define MAC_VLANTR_VTIM_WIDTH		1
1b5309d
+#define MAC_VR_DEVID_INDEX		8
1b5309d
+#define MAC_VR_DEVID_WIDTH		8
1b5309d
+#define MAC_VR_SNPSVER_INDEX		0
1b5309d
+#define MAC_VR_SNPSVER_WIDTH		8
1b5309d
+#define MAC_VR_USERVER_INDEX		16
1b5309d
+#define MAC_VR_USERVER_WIDTH		8
1b5309d
+
1b5309d
+/* MMC register offsets */
1b5309d
+#define MMC_CR				0x0800
1b5309d
+#define MMC_RISR			0x0804
1b5309d
+#define MMC_TISR			0x0808
1b5309d
+#define MMC_RIER			0x080c
1b5309d
+#define MMC_TIER			0x0810
1b5309d
+#define MMC_TXOCTETCOUNT_GB_LO		0x0814
1b5309d
+#define MMC_TXOCTETCOUNT_GB_HI		0x0818
1b5309d
+#define MMC_TXFRAMECOUNT_GB_LO		0x081c
1b5309d
+#define MMC_TXFRAMECOUNT_GB_HI		0x0820
1b5309d
+#define MMC_TXBROADCASTFRAMES_G_LO	0x0824
1b5309d
+#define MMC_TXBROADCASTFRAMES_G_HI	0x0828
1b5309d
+#define MMC_TXMULTICASTFRAMES_G_LO	0x082c
1b5309d
+#define MMC_TXMULTICASTFRAMES_G_HI	0x0830
1b5309d
+#define MMC_TX64OCTETS_GB_LO		0x0834
1b5309d
+#define MMC_TX64OCTETS_GB_HI		0x0838
1b5309d
+#define MMC_TX65TO127OCTETS_GB_LO	0x083c
1b5309d
+#define MMC_TX65TO127OCTETS_GB_HI	0x0840
1b5309d
+#define MMC_TX128TO255OCTETS_GB_LO	0x0844
1b5309d
+#define MMC_TX128TO255OCTETS_GB_HI	0x0848
1b5309d
+#define MMC_TX256TO511OCTETS_GB_LO	0x084c
1b5309d
+#define MMC_TX256TO511OCTETS_GB_HI	0x0850
1b5309d
+#define MMC_TX512TO1023OCTETS_GB_LO	0x0854
1b5309d
+#define MMC_TX512TO1023OCTETS_GB_HI	0x0858
1b5309d
+#define MMC_TX1024TOMAXOCTETS_GB_LO	0x085c
1b5309d
+#define MMC_TX1024TOMAXOCTETS_GB_HI	0x0860
1b5309d
+#define MMC_TXUNICASTFRAMES_GB_LO	0x0864
1b5309d
+#define MMC_TXUNICASTFRAMES_GB_HI	0x0868
1b5309d
+#define MMC_TXMULTICASTFRAMES_GB_LO	0x086c
1b5309d
+#define MMC_TXMULTICASTFRAMES_GB_HI	0x0870
1b5309d
+#define MMC_TXBROADCASTFRAMES_GB_LO	0x0874
1b5309d
+#define MMC_TXBROADCASTFRAMES_GB_HI	0x0878
1b5309d
+#define MMC_TXUNDERFLOWERROR_LO		0x087c
1b5309d
+#define MMC_TXUNDERFLOWERROR_HI		0x0880
1b5309d
+#define MMC_TXOCTETCOUNT_G_LO		0x0884
1b5309d
+#define MMC_TXOCTETCOUNT_G_HI		0x0888
1b5309d
+#define MMC_TXFRAMECOUNT_G_LO		0x088c
1b5309d
+#define MMC_TXFRAMECOUNT_G_HI		0x0890
1b5309d
+#define MMC_TXPAUSEFRAMES_LO		0x0894
1b5309d
+#define MMC_TXPAUSEFRAMES_HI		0x0898
1b5309d
+#define MMC_TXVLANFRAMES_G_LO		0x089c
1b5309d
+#define MMC_TXVLANFRAMES_G_HI		0x08a0
1b5309d
+#define MMC_RXFRAMECOUNT_GB_LO		0x0900
1b5309d
+#define MMC_RXFRAMECOUNT_GB_HI		0x0904
1b5309d
+#define MMC_RXOCTETCOUNT_GB_LO		0x0908
1b5309d
+#define MMC_RXOCTETCOUNT_GB_HI		0x090c
1b5309d
+#define MMC_RXOCTETCOUNT_G_LO		0x0910
1b5309d
+#define MMC_RXOCTETCOUNT_G_HI		0x0914
1b5309d
+#define MMC_RXBROADCASTFRAMES_G_LO	0x0918
1b5309d
+#define MMC_RXBROADCASTFRAMES_G_HI	0x091c
1b5309d
+#define MMC_RXMULTICASTFRAMES_G_LO	0x0920
1b5309d
+#define MMC_RXMULTICASTFRAMES_G_HI	0x0924
1b5309d
+#define MMC_RXCRCERROR_LO		0x0928
1b5309d
+#define MMC_RXCRCERROR_HI		0x092c
1b5309d
+#define MMC_RXRUNTERROR			0x0930
1b5309d
+#define MMC_RXJABBERERROR		0x0934
1b5309d
+#define MMC_RXUNDERSIZE_G		0x0938
1b5309d
+#define MMC_RXOVERSIZE_G		0x093c
1b5309d
+#define MMC_RX64OCTETS_GB_LO		0x0940
1b5309d
+#define MMC_RX64OCTETS_GB_HI		0x0944
1b5309d
+#define MMC_RX65TO127OCTETS_GB_LO	0x0948
1b5309d
+#define MMC_RX65TO127OCTETS_GB_HI	0x094c
1b5309d
+#define MMC_RX128TO255OCTETS_GB_LO	0x0950
1b5309d
+#define MMC_RX128TO255OCTETS_GB_HI	0x0954
1b5309d
+#define MMC_RX256TO511OCTETS_GB_LO	0x0958
1b5309d
+#define MMC_RX256TO511OCTETS_GB_HI	0x095c
1b5309d
+#define MMC_RX512TO1023OCTETS_GB_LO	0x0960
1b5309d
+#define MMC_RX512TO1023OCTETS_GB_HI	0x0964
1b5309d
+#define MMC_RX1024TOMAXOCTETS_GB_LO	0x0968
1b5309d
+#define MMC_RX1024TOMAXOCTETS_GB_HI	0x096c
1b5309d
+#define MMC_RXUNICASTFRAMES_G_LO	0x0970
1b5309d
+#define MMC_RXUNICASTFRAMES_G_HI	0x0974
1b5309d
+#define MMC_RXLENGTHERROR_LO		0x0978
1b5309d
+#define MMC_RXLENGTHERROR_HI		0x097c
1b5309d
+#define MMC_RXOUTOFRANGETYPE_LO		0x0980
1b5309d
+#define MMC_RXOUTOFRANGETYPE_HI		0x0984
1b5309d
+#define MMC_RXPAUSEFRAMES_LO		0x0988
1b5309d
+#define MMC_RXPAUSEFRAMES_HI		0x098c
1b5309d
+#define MMC_RXFIFOOVERFLOW_LO		0x0990
1b5309d
+#define MMC_RXFIFOOVERFLOW_HI		0x0994
1b5309d
+#define MMC_RXVLANFRAMES_GB_LO		0x0998
1b5309d
+#define MMC_RXVLANFRAMES_GB_HI		0x099c
1b5309d
+#define MMC_RXWATCHDOGERROR		0x09a0
1b5309d
+
1b5309d
+/* MMC register entry bit positions and sizes */
1b5309d
+#define MMC_CR_CR_INDEX				0
1b5309d
+#define MMC_CR_CR_WIDTH				1
1b5309d
+#define MMC_CR_CSR_INDEX			1
1b5309d
+#define MMC_CR_CSR_WIDTH			1
1b5309d
+#define MMC_CR_ROR_INDEX			2
1b5309d
+#define MMC_CR_ROR_WIDTH			1
1b5309d
+#define MMC_CR_MCF_INDEX			3
1b5309d
+#define MMC_CR_MCF_WIDTH			1
1b5309d
+#define MMC_CR_MCT_INDEX			4
1b5309d
+#define MMC_CR_MCT_WIDTH			2
1b5309d
+#define MMC_RIER_ALL_INTERRUPTS_INDEX		0
1b5309d
+#define MMC_RIER_ALL_INTERRUPTS_WIDTH		23
1b5309d
+#define MMC_RISR_RXFRAMECOUNT_GB_INDEX		0
1b5309d
+#define MMC_RISR_RXFRAMECOUNT_GB_WIDTH		1
1b5309d
+#define MMC_RISR_RXOCTETCOUNT_GB_INDEX		1
1b5309d
+#define MMC_RISR_RXOCTETCOUNT_GB_WIDTH		1
1b5309d
+#define MMC_RISR_RXOCTETCOUNT_G_INDEX		2
1b5309d
+#define MMC_RISR_RXOCTETCOUNT_G_WIDTH		1
1b5309d
+#define MMC_RISR_RXBROADCASTFRAMES_G_INDEX	3
1b5309d
+#define MMC_RISR_RXBROADCASTFRAMES_G_WIDTH	1
1b5309d
+#define MMC_RISR_RXMULTICASTFRAMES_G_INDEX	4
1b5309d
+#define MMC_RISR_RXMULTICASTFRAMES_G_WIDTH	1
1b5309d
+#define MMC_RISR_RXCRCERROR_INDEX		5
1b5309d
+#define MMC_RISR_RXCRCERROR_WIDTH		1
1b5309d
+#define MMC_RISR_RXRUNTERROR_INDEX		6
1b5309d
+#define MMC_RISR_RXRUNTERROR_WIDTH		1
1b5309d
+#define MMC_RISR_RXJABBERERROR_INDEX		7
1b5309d
+#define MMC_RISR_RXJABBERERROR_WIDTH		1
1b5309d
+#define MMC_RISR_RXUNDERSIZE_G_INDEX		8
1b5309d
+#define MMC_RISR_RXUNDERSIZE_G_WIDTH		1
1b5309d
+#define MMC_RISR_RXOVERSIZE_G_INDEX		9
1b5309d
+#define MMC_RISR_RXOVERSIZE_G_WIDTH		1
1b5309d
+#define MMC_RISR_RX64OCTETS_GB_INDEX		10
1b5309d
+#define MMC_RISR_RX64OCTETS_GB_WIDTH		1
1b5309d
+#define MMC_RISR_RX65TO127OCTETS_GB_INDEX	11
1b5309d
+#define MMC_RISR_RX65TO127OCTETS_GB_WIDTH	1
1b5309d
+#define MMC_RISR_RX128TO255OCTETS_GB_INDEX	12
1b5309d
+#define MMC_RISR_RX128TO255OCTETS_GB_WIDTH	1
1b5309d
+#define MMC_RISR_RX256TO511OCTETS_GB_INDEX	13
1b5309d
+#define MMC_RISR_RX256TO511OCTETS_GB_WIDTH	1
1b5309d
+#define MMC_RISR_RX512TO1023OCTETS_GB_INDEX	14
1b5309d
+#define MMC_RISR_RX512TO1023OCTETS_GB_WIDTH	1
1b5309d
+#define MMC_RISR_RX1024TOMAXOCTETS_GB_INDEX	15
1b5309d
+#define MMC_RISR_RX1024TOMAXOCTETS_GB_WIDTH	1
1b5309d
+#define MMC_RISR_RXUNICASTFRAMES_G_INDEX	16
1b5309d
+#define MMC_RISR_RXUNICASTFRAMES_G_WIDTH	1
1b5309d
+#define MMC_RISR_RXLENGTHERROR_INDEX		17
1b5309d
+#define MMC_RISR_RXLENGTHERROR_WIDTH		1
1b5309d
+#define MMC_RISR_RXOUTOFRANGETYPE_INDEX		18
1b5309d
+#define MMC_RISR_RXOUTOFRANGETYPE_WIDTH		1
1b5309d
+#define MMC_RISR_RXPAUSEFRAMES_INDEX		19
1b5309d
+#define MMC_RISR_RXPAUSEFRAMES_WIDTH		1
1b5309d
+#define MMC_RISR_RXFIFOOVERFLOW_INDEX		20
1b5309d
+#define MMC_RISR_RXFIFOOVERFLOW_WIDTH		1
1b5309d
+#define MMC_RISR_RXVLANFRAMES_GB_INDEX		21
1b5309d
+#define MMC_RISR_RXVLANFRAMES_GB_WIDTH		1
1b5309d
+#define MMC_RISR_RXWATCHDOGERROR_INDEX		22
1b5309d
+#define MMC_RISR_RXWATCHDOGERROR_WIDTH		1
1b5309d
+#define MMC_TIER_ALL_INTERRUPTS_INDEX		0
1b5309d
+#define MMC_TIER_ALL_INTERRUPTS_WIDTH		18
1b5309d
+#define MMC_TISR_TXOCTETCOUNT_GB_INDEX		0
1b5309d
+#define MMC_TISR_TXOCTETCOUNT_GB_WIDTH		1
1b5309d
+#define MMC_TISR_TXFRAMECOUNT_GB_INDEX		1
1b5309d
+#define MMC_TISR_TXFRAMECOUNT_GB_WIDTH		1
1b5309d
+#define MMC_TISR_TXBROADCASTFRAMES_G_INDEX	2
1b5309d
+#define MMC_TISR_TXBROADCASTFRAMES_G_WIDTH	1
1b5309d
+#define MMC_TISR_TXMULTICASTFRAMES_G_INDEX	3
1b5309d
+#define MMC_TISR_TXMULTICASTFRAMES_G_WIDTH	1
1b5309d
+#define MMC_TISR_TX64OCTETS_GB_INDEX		4
1b5309d
+#define MMC_TISR_TX64OCTETS_GB_WIDTH		1
1b5309d
+#define MMC_TISR_TX65TO127OCTETS_GB_INDEX	5
1b5309d
+#define MMC_TISR_TX65TO127OCTETS_GB_WIDTH	1
1b5309d
+#define MMC_TISR_TX128TO255OCTETS_GB_INDEX	6
1b5309d
+#define MMC_TISR_TX128TO255OCTETS_GB_WIDTH	1
1b5309d
+#define MMC_TISR_TX256TO511OCTETS_GB_INDEX	7
1b5309d
+#define MMC_TISR_TX256TO511OCTETS_GB_WIDTH	1
1b5309d
+#define MMC_TISR_TX512TO1023OCTETS_GB_INDEX	8
1b5309d
+#define MMC_TISR_TX512TO1023OCTETS_GB_WIDTH	1
1b5309d
+#define MMC_TISR_TX1024TOMAXOCTETS_GB_INDEX	9
1b5309d
+#define MMC_TISR_TX1024TOMAXOCTETS_GB_WIDTH	1
1b5309d
+#define MMC_TISR_TXUNICASTFRAMES_GB_INDEX	10
1b5309d
+#define MMC_TISR_TXUNICASTFRAMES_GB_WIDTH	1
1b5309d
+#define MMC_TISR_TXMULTICASTFRAMES_GB_INDEX	11
1b5309d
+#define MMC_TISR_TXMULTICASTFRAMES_GB_WIDTH	1
1b5309d
+#define MMC_TISR_TXBROADCASTFRAMES_GB_INDEX	12
1b5309d
+#define MMC_TISR_TXBROADCASTFRAMES_GB_WIDTH	1
1b5309d
+#define MMC_TISR_TXUNDERFLOWERROR_INDEX		13
1b5309d
+#define MMC_TISR_TXUNDERFLOWERROR_WIDTH		1
1b5309d
+#define MMC_TISR_TXOCTETCOUNT_G_INDEX		14
1b5309d
+#define MMC_TISR_TXOCTETCOUNT_G_WIDTH		1
1b5309d
+#define MMC_TISR_TXFRAMECOUNT_G_INDEX		15
1b5309d
+#define MMC_TISR_TXFRAMECOUNT_G_WIDTH		1
1b5309d
+#define MMC_TISR_TXPAUSEFRAMES_INDEX		16
1b5309d
+#define MMC_TISR_TXPAUSEFRAMES_WIDTH		1
1b5309d
+#define MMC_TISR_TXVLANFRAMES_G_INDEX		17
1b5309d
+#define MMC_TISR_TXVLANFRAMES_G_WIDTH		1
1b5309d
+
1b5309d
+/* MTL register offsets */
1b5309d
+#define MTL_OMR				0x1000
1b5309d
+#define MTL_FDCR			0x1008
1b5309d
+#define MTL_FDSR			0x100c
1b5309d
+#define MTL_FDDR			0x1010
1b5309d
+#define MTL_ISR				0x1020
1b5309d
+#define MTL_RQDCM0R			0x1030
1b5309d
+#define MTL_TCPM0R			0x1040
1b5309d
+#define MTL_TCPM1R			0x1044
1b5309d
+
1b5309d
+#define MTL_RQDCM_INC			4
1b5309d
+#define MTL_RQDCM_Q_PER_REG		4
1b5309d
+#define MTL_TCPM_INC			4
1b5309d
+#define MTL_TCPM_TC_PER_REG		4
1b5309d
+
1b5309d
+/* MTL register entry bit positions and sizes */
1b5309d
+#define MTL_OMR_ETSALG_INDEX		5
1b5309d
+#define MTL_OMR_ETSALG_WIDTH		2
1b5309d
+#define MTL_OMR_RAA_INDEX		2
1b5309d
+#define MTL_OMR_RAA_WIDTH		1
1b5309d
+
1b5309d
+/* MTL queue register offsets
1b5309d
+ *   Multiple queues can be active.  The first queue has registers
1b5309d
+ *   that begin at 0x1100.  Each subsequent queue has registers that
1b5309d
+ *   are accessed using an offset of 0x80 from the previous queue.
1b5309d
+ */
1b5309d
+#define MTL_Q_BASE			0x1100
1b5309d
+#define MTL_Q_INC			0x80
1b5309d
+
1b5309d
+#define MTL_Q_TQOMR			0x00
1b5309d
+#define MTL_Q_TQUR			0x04
1b5309d
+#define MTL_Q_TQDR			0x08
1b5309d
+#define MTL_Q_RQOMR			0x40
1b5309d
+#define MTL_Q_RQMPOCR			0x44
1b5309d
+#define MTL_Q_RQDR			0x4c
1b5309d
+#define MTL_Q_IER			0x70
1b5309d
+#define MTL_Q_ISR			0x74
1b5309d
+
1b5309d
+/* MTL queue register entry bit positions and sizes */
1b5309d
+#define MTL_Q_RQOMR_EHFC_INDEX		7
1b5309d
+#define MTL_Q_RQOMR_EHFC_WIDTH		1
1b5309d
+#define MTL_Q_RQOMR_RFA_INDEX		8
1b5309d
+#define MTL_Q_RQOMR_RFA_WIDTH		3
1b5309d
+#define MTL_Q_RQOMR_RFD_INDEX		13
1b5309d
+#define MTL_Q_RQOMR_RFD_WIDTH		3
1b5309d
+#define MTL_Q_RQOMR_RQS_INDEX		16
1b5309d
+#define MTL_Q_RQOMR_RQS_WIDTH		9
1b5309d
+#define MTL_Q_RQOMR_RSF_INDEX		5
1b5309d
+#define MTL_Q_RQOMR_RSF_WIDTH		1
1b5309d
+#define MTL_Q_RQOMR_RTC_INDEX		0
1b5309d
+#define MTL_Q_RQOMR_RTC_WIDTH		2
1b5309d
+#define MTL_Q_TQOMR_FTQ_INDEX		0
1b5309d
+#define MTL_Q_TQOMR_FTQ_WIDTH		1
1b5309d
+#define MTL_Q_TQOMR_Q2TCMAP_INDEX	8
1b5309d
+#define MTL_Q_TQOMR_Q2TCMAP_WIDTH	3
1b5309d
+#define MTL_Q_TQOMR_TQS_INDEX		16
1b5309d
+#define MTL_Q_TQOMR_TQS_WIDTH		10
1b5309d
+#define MTL_Q_TQOMR_TSF_INDEX		1
1b5309d
+#define MTL_Q_TQOMR_TSF_WIDTH		1
1b5309d
+#define MTL_Q_TQOMR_TTC_INDEX		4
1b5309d
+#define MTL_Q_TQOMR_TTC_WIDTH		3
1b5309d
+#define MTL_Q_TQOMR_TXQEN_INDEX		2
1b5309d
+#define MTL_Q_TQOMR_TXQEN_WIDTH		2
1b5309d
+
1b5309d
+/* MTL queue register value */
1b5309d
+#define MTL_RSF_DISABLE			0x00
1b5309d
+#define MTL_RSF_ENABLE			0x01
1b5309d
+#define MTL_TSF_DISABLE			0x00
1b5309d
+#define MTL_TSF_ENABLE			0x01
1b5309d
+
1b5309d
+#define MTL_RX_THRESHOLD_64		0x00
1b5309d
+#define MTL_RX_THRESHOLD_96		0x02
1b5309d
+#define MTL_RX_THRESHOLD_128		0x03
1b5309d
+#define MTL_TX_THRESHOLD_32		0x01
1b5309d
+#define MTL_TX_THRESHOLD_64		0x00
1b5309d
+#define MTL_TX_THRESHOLD_96		0x02
1b5309d
+#define MTL_TX_THRESHOLD_128		0x03
1b5309d
+#define MTL_TX_THRESHOLD_192		0x04
1b5309d
+#define MTL_TX_THRESHOLD_256		0x05
1b5309d
+#define MTL_TX_THRESHOLD_384		0x06
1b5309d
+#define MTL_TX_THRESHOLD_512		0x07
1b5309d
+
1b5309d
+#define MTL_ETSALG_WRR			0x00
1b5309d
+#define MTL_ETSALG_WFQ			0x01
1b5309d
+#define MTL_ETSALG_DWRR			0x02
1b5309d
+#define MTL_RAA_SP			0x00
1b5309d
+#define MTL_RAA_WSP			0x01
1b5309d
+
1b5309d
+#define MTL_Q_DISABLED			0x00
1b5309d
+#define MTL_Q_ENABLED			0x02
1b5309d
+
1b5309d
+/* MTL traffic class register offsets
1b5309d
+ *   Multiple traffic classes can be active.  The first class has registers
1b5309d
+ *   that begin at 0x1100.  Each subsequent queue has registers that
1b5309d
+ *   are accessed using an offset of 0x80 from the previous queue.
1b5309d
+ */
1b5309d
+#define MTL_TC_BASE			MTL_Q_BASE
1b5309d
+#define MTL_TC_INC			MTL_Q_INC
1b5309d
+
1b5309d
+#define MTL_TC_ETSCR			0x10
1b5309d
+#define MTL_TC_ETSSR			0x14
1b5309d
+#define MTL_TC_QWR			0x18
1b5309d
+
1b5309d
+/* MTL traffic class register entry bit positions and sizes */
1b5309d
+#define MTL_TC_ETSCR_TSA_INDEX		0
1b5309d
+#define MTL_TC_ETSCR_TSA_WIDTH		2
1b5309d
+#define MTL_TC_QWR_QW_INDEX		0
1b5309d
+#define MTL_TC_QWR_QW_WIDTH		21
1b5309d
+
1b5309d
+/* MTL traffic class register value */
1b5309d
+#define MTL_TSA_SP			0x00
1b5309d
+#define MTL_TSA_ETS			0x02
1b5309d
+
1b5309d
+/* PCS MMD select register offset
1b5309d
+ *  The MMD select register is used for accessing PCS registers
1b5309d
+ *  when the underlying APB3 interface is using indirect addressing.
1b5309d
+ *  Indirect addressing requires accessing registers in two phases,
1b5309d
+ *  an address phase and a data phase.  The address phases requires
1b5309d
+ *  writing an address selection value to the MMD select regiesters.
1b5309d
+ */
1b5309d
+#define PCS_MMD_SELECT			0xff
1b5309d
+
1b5309d
+/* Descriptor/Packet entry bit positions and sizes */
1b5309d
+#define RX_PACKET_ERRORS_CRC_INDEX		2
1b5309d
+#define RX_PACKET_ERRORS_CRC_WIDTH		1
1b5309d
+#define RX_PACKET_ERRORS_FRAME_INDEX		3
1b5309d
+#define RX_PACKET_ERRORS_FRAME_WIDTH		1
1b5309d
+#define RX_PACKET_ERRORS_LENGTH_INDEX		0
1b5309d
+#define RX_PACKET_ERRORS_LENGTH_WIDTH		1
1b5309d
+#define RX_PACKET_ERRORS_OVERRUN_INDEX		1
1b5309d
+#define RX_PACKET_ERRORS_OVERRUN_WIDTH		1
1b5309d
+
1b5309d
+#define RX_PACKET_ATTRIBUTES_CSUM_DONE_INDEX	0
1b5309d
+#define RX_PACKET_ATTRIBUTES_CSUM_DONE_WIDTH	1
1b5309d
+#define RX_PACKET_ATTRIBUTES_VLAN_CTAG_INDEX	1
1b5309d
+#define RX_PACKET_ATTRIBUTES_VLAN_CTAG_WIDTH	1
1b5309d
+#define RX_PACKET_ATTRIBUTES_INCOMPLETE_INDEX	2
1b5309d
+#define RX_PACKET_ATTRIBUTES_INCOMPLETE_WIDTH	1
1b5309d
+#define RX_PACKET_ATTRIBUTES_CONTEXT_NEXT_INDEX	3
1b5309d
+#define RX_PACKET_ATTRIBUTES_CONTEXT_NEXT_WIDTH	1
1b5309d
+#define RX_PACKET_ATTRIBUTES_CONTEXT_INDEX	4
1b5309d
+#define RX_PACKET_ATTRIBUTES_CONTEXT_WIDTH	1
1b5309d
+#define RX_PACKET_ATTRIBUTES_RX_TSTAMP_INDEX	5
1b5309d
+#define RX_PACKET_ATTRIBUTES_RX_TSTAMP_WIDTH	1
1b5309d
+#define RX_PACKET_ATTRIBUTES_RSS_HASH_INDEX	6
1b5309d
+#define RX_PACKET_ATTRIBUTES_RSS_HASH_WIDTH	1
1b5309d
+
1b5309d
+#define RX_NORMAL_DESC0_OVT_INDEX		0
1b5309d
+#define RX_NORMAL_DESC0_OVT_WIDTH		16
1b5309d
+#define RX_NORMAL_DESC2_HL_INDEX		0
1b5309d
+#define RX_NORMAL_DESC2_HL_WIDTH		10
1b5309d
+#define RX_NORMAL_DESC3_CDA_INDEX		27
1b5309d
+#define RX_NORMAL_DESC3_CDA_WIDTH		1
1b5309d
+#define RX_NORMAL_DESC3_CTXT_INDEX		30
1b5309d
+#define RX_NORMAL_DESC3_CTXT_WIDTH		1
1b5309d
+#define RX_NORMAL_DESC3_ES_INDEX		15
1b5309d
+#define RX_NORMAL_DESC3_ES_WIDTH		1
1b5309d
+#define RX_NORMAL_DESC3_ETLT_INDEX		16
1b5309d
+#define RX_NORMAL_DESC3_ETLT_WIDTH		4
1b5309d
+#define RX_NORMAL_DESC3_FD_INDEX		29
1b5309d
+#define RX_NORMAL_DESC3_FD_WIDTH		1
1b5309d
+#define RX_NORMAL_DESC3_INTE_INDEX		30
1b5309d
+#define RX_NORMAL_DESC3_INTE_WIDTH		1
1b5309d
+#define RX_NORMAL_DESC3_L34T_INDEX		20
1b5309d
+#define RX_NORMAL_DESC3_L34T_WIDTH		4
1b5309d
+#define RX_NORMAL_DESC3_LD_INDEX		28
1b5309d
+#define RX_NORMAL_DESC3_LD_WIDTH		1
1b5309d
+#define RX_NORMAL_DESC3_OWN_INDEX		31
1b5309d
+#define RX_NORMAL_DESC3_OWN_WIDTH		1
1b5309d
+#define RX_NORMAL_DESC3_PL_INDEX		0
1b5309d
+#define RX_NORMAL_DESC3_PL_WIDTH		14
1b5309d
+#define RX_NORMAL_DESC3_RSV_INDEX		26
1b5309d
+#define RX_NORMAL_DESC3_RSV_WIDTH		1
1b5309d
+
1b5309d
+#define RX_DESC3_L34T_IPV4_TCP			1
1b5309d
+#define RX_DESC3_L34T_IPV4_UDP			2
1b5309d
+#define RX_DESC3_L34T_IPV4_ICMP			3
1b5309d
+#define RX_DESC3_L34T_IPV6_TCP			9
1b5309d
+#define RX_DESC3_L34T_IPV6_UDP			10
1b5309d
+#define RX_DESC3_L34T_IPV6_ICMP			11
1b5309d
+
1b5309d
+#define RX_CONTEXT_DESC3_TSA_INDEX		4
1b5309d
+#define RX_CONTEXT_DESC3_TSA_WIDTH		1
1b5309d
+#define RX_CONTEXT_DESC3_TSD_INDEX		6
1b5309d
+#define RX_CONTEXT_DESC3_TSD_WIDTH		1
1b5309d
+
1b5309d
+#define TX_PACKET_ATTRIBUTES_CSUM_ENABLE_INDEX	0
1b5309d
+#define TX_PACKET_ATTRIBUTES_CSUM_ENABLE_WIDTH	1
1b5309d
+#define TX_PACKET_ATTRIBUTES_TSO_ENABLE_INDEX	1
1b5309d
+#define TX_PACKET_ATTRIBUTES_TSO_ENABLE_WIDTH	1
1b5309d
+#define TX_PACKET_ATTRIBUTES_VLAN_CTAG_INDEX	2
1b5309d
+#define TX_PACKET_ATTRIBUTES_VLAN_CTAG_WIDTH	1
1b5309d
+#define TX_PACKET_ATTRIBUTES_PTP_INDEX		3
1b5309d
+#define TX_PACKET_ATTRIBUTES_PTP_WIDTH		1
1b5309d
+
1b5309d
+#define TX_CONTEXT_DESC2_MSS_INDEX		0
1b5309d
+#define TX_CONTEXT_DESC2_MSS_WIDTH		15
1b5309d
+#define TX_CONTEXT_DESC3_CTXT_INDEX		30
1b5309d
+#define TX_CONTEXT_DESC3_CTXT_WIDTH		1
1b5309d
+#define TX_CONTEXT_DESC3_TCMSSV_INDEX		26
1b5309d
+#define TX_CONTEXT_DESC3_TCMSSV_WIDTH		1
1b5309d
+#define TX_CONTEXT_DESC3_VLTV_INDEX		16
1b5309d
+#define TX_CONTEXT_DESC3_VLTV_WIDTH		1
1b5309d
+#define TX_CONTEXT_DESC3_VT_INDEX		0
1b5309d
+#define TX_CONTEXT_DESC3_VT_WIDTH		16
1b5309d
+
1b5309d
+#define TX_NORMAL_DESC2_HL_B1L_INDEX		0
1b5309d
+#define TX_NORMAL_DESC2_HL_B1L_WIDTH		14
1b5309d
+#define TX_NORMAL_DESC2_IC_INDEX		31
1b5309d
+#define TX_NORMAL_DESC2_IC_WIDTH		1
1b5309d
+#define TX_NORMAL_DESC2_TTSE_INDEX		30
1b5309d
+#define TX_NORMAL_DESC2_TTSE_WIDTH		1
1b5309d
+#define TX_NORMAL_DESC2_VTIR_INDEX		14
1b5309d
+#define TX_NORMAL_DESC2_VTIR_WIDTH		2
1b5309d
+#define TX_NORMAL_DESC3_CIC_INDEX		16
1b5309d
+#define TX_NORMAL_DESC3_CIC_WIDTH		2
1b5309d
+#define TX_NORMAL_DESC3_CPC_INDEX		26
1b5309d
+#define TX_NORMAL_DESC3_CPC_WIDTH		2
1b5309d
+#define TX_NORMAL_DESC3_CTXT_INDEX		30
1b5309d
+#define TX_NORMAL_DESC3_CTXT_WIDTH		1
1b5309d
+#define TX_NORMAL_DESC3_FD_INDEX		29
1b5309d
+#define TX_NORMAL_DESC3_FD_WIDTH		1
1b5309d
+#define TX_NORMAL_DESC3_FL_INDEX		0
1b5309d
+#define TX_NORMAL_DESC3_FL_WIDTH		15
1b5309d
+#define TX_NORMAL_DESC3_LD_INDEX		28
1b5309d
+#define TX_NORMAL_DESC3_LD_WIDTH		1
1b5309d
+#define TX_NORMAL_DESC3_OWN_INDEX		31
1b5309d
+#define TX_NORMAL_DESC3_OWN_WIDTH		1
1b5309d
+#define TX_NORMAL_DESC3_TCPHDRLEN_INDEX		19
1b5309d
+#define TX_NORMAL_DESC3_TCPHDRLEN_WIDTH		4
1b5309d
+#define TX_NORMAL_DESC3_TCPPL_INDEX		0
1b5309d
+#define TX_NORMAL_DESC3_TCPPL_WIDTH		18
1b5309d
+#define TX_NORMAL_DESC3_TSE_INDEX		18
1b5309d
+#define TX_NORMAL_DESC3_TSE_WIDTH		1
1b5309d
+
1b5309d
+#define TX_NORMAL_DESC2_VLAN_INSERT		0x2
1b5309d
+
1b5309d
+/* MDIO undefined or vendor specific registers */
1b5309d
+#ifndef MDIO_AN_COMP_STAT
1b5309d
+#define MDIO_AN_COMP_STAT		0x0030
1b5309d
+#endif
1b5309d
+
1b5309d
+/* Bit setting and getting macros
1b5309d
+ *  The get macro will extract the current bit field value from within
1b5309d
+ *  the variable
1b5309d
+ *
1b5309d
+ *  The set macro will clear the current bit field value within the
1b5309d
+ *  variable and then set the bit field of the variable to the
1b5309d
+ *  specified value
1b5309d
+ */
1b5309d
+#define GET_BITS(_var, _index, _width)					\
1b5309d
+	(((_var) >> (_index)) & ((0x1 << (_width)) - 1))
1b5309d
+
1b5309d
+#define SET_BITS(_var, _index, _width, _val)				\
1b5309d
+do {									\
1b5309d
+	(_var) &= ~(((0x1 << (_width)) - 1) << (_index));		\
1b5309d
+	(_var) |= (((_val) & ((0x1 << (_width)) - 1)) << (_index));	\
1b5309d
+} while (0)
1b5309d
+
1b5309d
+#define GET_BITS_LE(_var, _index, _width)				\
1b5309d
+	((le32_to_cpu((_var)) >> (_index)) & ((0x1 << (_width)) - 1))
1b5309d
+
1b5309d
+#define SET_BITS_LE(_var, _index, _width, _val)				\
1b5309d
+do {									\
1b5309d
+	(_var) &= cpu_to_le32(~(((0x1 << (_width)) - 1) << (_index)));	\
1b5309d
+	(_var) |= cpu_to_le32((((_val) &				\
1b5309d
+			      ((0x1 << (_width)) - 1)) << (_index)));	\
1b5309d
+} while (0)
1b5309d
+
1b5309d
+/* Bit setting and getting macros based on register fields
1b5309d
+ *  The get macro uses the bit field definitions formed using the input
1b5309d
+ *  names to extract the current bit field value from within the
1b5309d
+ *  variable
1b5309d
+ *
1b5309d
+ *  The set macro uses the bit field definitions formed using the input
1b5309d
+ *  names to set the bit field of the variable to the specified value
1b5309d
+ */
1b5309d
+#define XGMAC_GET_BITS(_var, _prefix, _field)				\
1b5309d
+	GET_BITS((_var),						\
1b5309d
+		 _prefix##_##_field##_INDEX,				\
1b5309d
+		 _prefix##_##_field##_WIDTH)
1b5309d
+
1b5309d
+#define XGMAC_SET_BITS(_var, _prefix, _field, _val)			\
1b5309d
+	SET_BITS((_var),						\
1b5309d
+		 _prefix##_##_field##_INDEX,				\
1b5309d
+		 _prefix##_##_field##_WIDTH, (_val))
1b5309d
+
1b5309d
+#define XGMAC_GET_BITS_LE(_var, _prefix, _field)			\
1b5309d
+	GET_BITS_LE((_var),						\
1b5309d
+		 _prefix##_##_field##_INDEX,				\
1b5309d
+		 _prefix##_##_field##_WIDTH)
1b5309d
+
1b5309d
+#define XGMAC_SET_BITS_LE(_var, _prefix, _field, _val)			\
1b5309d
+	SET_BITS_LE((_var),						\
1b5309d
+		 _prefix##_##_field##_INDEX,				\
1b5309d
+		 _prefix##_##_field##_WIDTH, (_val))
1b5309d
+
1b5309d
+/* Macros for reading or writing registers
1b5309d
+ *  The ioread macros will get bit fields or full values using the
1b5309d
+ *  register definitions formed using the input names
1b5309d
+ *
1b5309d
+ *  The iowrite macros will set bit fields or full values using the
1b5309d
+ *  register definitions formed using the input names
1b5309d
+ */
1b5309d
+#define XGMAC_IOREAD(_pdata, _reg)					\
1b5309d
+	ioread32((_pdata)->xgmac_regs + _reg)
1b5309d
+
1b5309d
+#define XGMAC_IOREAD_BITS(_pdata, _reg, _field)				\
1b5309d
+	GET_BITS(XGMAC_IOREAD((_pdata), _reg),				\
1b5309d
+		 _reg##_##_field##_INDEX,				\
1b5309d
+		 _reg##_##_field##_WIDTH)
1b5309d
+
1b5309d
+#define XGMAC_IOWRITE(_pdata, _reg, _val)				\
1b5309d
+	iowrite32((_val), (_pdata)->xgmac_regs + _reg)
1b5309d
+
1b5309d
+#define XGMAC_IOWRITE_BITS(_pdata, _reg, _field, _val)			\
1b5309d
+do {									\
1b5309d
+	u32 reg_val = XGMAC_IOREAD((_pdata), _reg);			\
1b5309d
+	SET_BITS(reg_val,						\
1b5309d
+		 _reg##_##_field##_INDEX,				\
1b5309d
+		 _reg##_##_field##_WIDTH, (_val));			\
1b5309d
+	XGMAC_IOWRITE((_pdata), _reg, reg_val);				\
1b5309d
+} while (0)
1b5309d
+
1b5309d
+/* Macros for reading or writing MTL queue or traffic class registers
1b5309d
+ *  Similar to the standard read and write macros except that the
1b5309d
+ *  base register value is calculated by the queue or traffic class number
1b5309d
+ */
1b5309d
+#define XGMAC_MTL_IOREAD(_pdata, _n, _reg)				\
1b5309d
+	ioread32((_pdata)->xgmac_regs +					\
1b5309d
+		 MTL_Q_BASE + ((_n) * MTL_Q_INC) + _reg)
1b5309d
+
1b5309d
+#define XGMAC_MTL_IOREAD_BITS(_pdata, _n, _reg, _field)			\
1b5309d
+	GET_BITS(XGMAC_MTL_IOREAD((_pdata), (_n), _reg),		\
1b5309d
+		 _reg##_##_field##_INDEX,				\
1b5309d
+		 _reg##_##_field##_WIDTH)
1b5309d
+
1b5309d
+#define XGMAC_MTL_IOWRITE(_pdata, _n, _reg, _val)			\
1b5309d
+	iowrite32((_val), (_pdata)->xgmac_regs +			\
1b5309d
+		  MTL_Q_BASE + ((_n) * MTL_Q_INC) + _reg)
1b5309d
+
1b5309d
+#define XGMAC_MTL_IOWRITE_BITS(_pdata, _n, _reg, _field, _val)		\
1b5309d
+do {									\
1b5309d
+	u32 reg_val = XGMAC_MTL_IOREAD((_pdata), (_n), _reg);		\
1b5309d
+	SET_BITS(reg_val,						\
1b5309d
+		 _reg##_##_field##_INDEX,				\
1b5309d
+		 _reg##_##_field##_WIDTH, (_val));			\
1b5309d
+	XGMAC_MTL_IOWRITE((_pdata), (_n), _reg, reg_val);		\
1b5309d
+} while (0)
1b5309d
+
1b5309d
+/* Macros for reading or writing DMA channel registers
1b5309d
+ *  Similar to the standard read and write macros except that the
1b5309d
+ *  base register value is obtained from the ring
1b5309d
+ */
1b5309d
+#define XGMAC_DMA_IOREAD(_channel, _reg)				\
1b5309d
+	ioread32((_channel)->dma_regs + _reg)
1b5309d
+
1b5309d
+#define XGMAC_DMA_IOREAD_BITS(_channel, _reg, _field)			\
1b5309d
+	GET_BITS(XGMAC_DMA_IOREAD((_channel), _reg),			\
1b5309d
+		 _reg##_##_field##_INDEX,				\
1b5309d
+		 _reg##_##_field##_WIDTH)
1b5309d
+
1b5309d
+#define XGMAC_DMA_IOWRITE(_channel, _reg, _val)				\
1b5309d
+	iowrite32((_val), (_channel)->dma_regs + _reg)
1b5309d
+
1b5309d
+#define XGMAC_DMA_IOWRITE_BITS(_channel, _reg, _field, _val)		\
1b5309d
+do {									\
1b5309d
+	u32 reg_val = XGMAC_DMA_IOREAD((_channel), _reg);		\
1b5309d
+	SET_BITS(reg_val,						\
1b5309d
+		 _reg##_##_field##_INDEX,				\
1b5309d
+		 _reg##_##_field##_WIDTH, (_val));			\
1b5309d
+	XGMAC_DMA_IOWRITE((_channel), _reg, reg_val);			\
1b5309d
+} while (0)
1b5309d
+
1b5309d
+/* Macros for building, reading or writing register values or bits
1b5309d
+ * within the register values of XPCS registers.
1b5309d
+ */
1b5309d
+#define XPCS_IOWRITE(_pdata, _off, _val)				\
1b5309d
+	iowrite32(_val, (_pdata)->xpcs_regs + (_off))
1b5309d
+
1b5309d
+#define XPCS_IOREAD(_pdata, _off)					\
1b5309d
+	ioread32((_pdata)->xpcs_regs + (_off))
1b5309d
+
1b5309d
+/* Macros for building, reading or writing register values or bits
1b5309d
+ * using MDIO.  Different from above because of the use of standardized
1b5309d
+ * Linux include values.  No shifting is performed with the bit
1b5309d
+ * operations, everything works on mask values.
1b5309d
+ */
1b5309d
+#define XMDIO_READ(_pdata, _mmd, _reg)					\
1b5309d
+	((_pdata)->hw_if.read_mmd_regs((_pdata), 0,			\
1b5309d
+		MII_ADDR_C45 | (_mmd << 16) | ((_reg) & 0xffff)))
1b5309d
+
1b5309d
+#define XMDIO_READ_BITS(_pdata, _mmd, _reg, _mask)			\
1b5309d
+	(XMDIO_READ((_pdata), _mmd, _reg) & _mask)
1b5309d
+
1b5309d
+#define XMDIO_WRITE(_pdata, _mmd, _reg, _val)				\
1b5309d
+	((_pdata)->hw_if.write_mmd_regs((_pdata), 0,			\
1b5309d
+		MII_ADDR_C45 | (_mmd << 16) | ((_reg) & 0xffff), (_val)))
1b5309d
+
1b5309d
+#define XMDIO_WRITE_BITS(_pdata, _mmd, _reg, _mask, _val)		\
1b5309d
+do {									\
1b5309d
+	u32 mmd_val = XMDIO_READ((_pdata), _mmd, _reg);			\
1b5309d
+	mmd_val &= ~_mask;						\
1b5309d
+	mmd_val |= (_val);						\
1b5309d
+	XMDIO_WRITE((_pdata), _mmd, _reg, mmd_val);			\
1b5309d
+} while (0)
1b5309d
+
1b5309d
+#endif
1b5309d
diff --git a/drivers/net/ethernet/amd/xgbe-a0/xgbe-dcb.c b/drivers/net/ethernet/amd/xgbe-a0/xgbe-dcb.c
1b5309d
new file mode 100644
0d59e0e
index 000000000000..343301cbf7b4
1b5309d
--- /dev/null
1b5309d
+++ b/drivers/net/ethernet/amd/xgbe-a0/xgbe-dcb.c
1b5309d
@@ -0,0 +1,269 @@
1b5309d
+/*
1b5309d
+ * AMD 10Gb Ethernet driver
1b5309d
+ *
1b5309d
+ * This file is available to you under your choice of the following two
1b5309d
+ * licenses:
1b5309d
+ *
1b5309d
+ * License 1: GPLv2
1b5309d
+ *
1b5309d
+ * Copyright (c) 2014 Advanced Micro Devices, Inc.
1b5309d
+ *
1b5309d
+ * This file is free software; you may copy, redistribute and/or modify
1b5309d
+ * it under the terms of the GNU General Public License as published by
1b5309d
+ * the Free Software Foundation, either version 2 of the License, or (at
1b5309d
+ * your option) any later version.
1b5309d
+ *
1b5309d
+ * This file is distributed in the hope that it will be useful, but
1b5309d
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
1b5309d
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
1b5309d
+ * General Public License for more details.
1b5309d
+ *
1b5309d
+ * You should have received a copy of the GNU General Public License
1b5309d
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
1b5309d
+ *
1b5309d
+ * This file incorporates work covered by the following copyright and
1b5309d
+ * permission notice:
1b5309d
+ *     The Synopsys DWC ETHER XGMAC Software Driver and documentation
1b5309d
+ *     (hereinafter "Software") is an unsupported proprietary work of Synopsys,
1b5309d
+ *     Inc. unless otherwise expressly agreed to in writing between Synopsys
1b5309d
+ *     and you.
1b5309d
+ *
1b5309d
+ *     The Software IS NOT an item of Licensed Software or Licensed Product
1b5309d
+ *     under any End User Software License Agreement or Agreement for Licensed
1b5309d
+ *     Product with Synopsys or any supplement thereto.  Permission is hereby
1b5309d
+ *     granted, free of charge, to any person obtaining a copy of this software
1b5309d
+ *     annotated with this license and the Software, to deal in the Software
1b5309d
+ *     without restriction, including without limitation the rights to use,
1b5309d
+ *     copy, modify, merge, publish, distribute, sublicense, and/or sell copies
1b5309d
+ *     of the Software, and to permit persons to whom the Software is furnished
1b5309d
+ *     to do so, subject to the following conditions:
1b5309d
+ *
1b5309d
+ *     The above copyright notice and this permission notice shall be included
1b5309d
+ *     in all copies or substantial portions of the Software.
1b5309d
+ *
1b5309d
+ *     THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS"
1b5309d
+ *     BASIS AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
1b5309d
+ *     TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
1b5309d
+ *     PARTICULAR PURPOSE ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS
1b5309d
+ *     BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
1b5309d
+ *     CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
1b5309d
+ *     SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
1b5309d
+ *     INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
1b5309d
+ *     CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
1b5309d
+ *     ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
1b5309d
+ *     THE POSSIBILITY OF SUCH DAMAGE.
1b5309d
+ *
1b5309d
+ *
1b5309d
+ * License 2: Modified BSD
1b5309d
+ *
1b5309d
+ * Copyright (c) 2014 Advanced Micro Devices, Inc.
1b5309d
+ * All rights reserved.
1b5309d
+ *
1b5309d
+ * Redistribution and use in source and binary forms, with or without
1b5309d
+ * modification, are permitted provided that the following conditions are met:
1b5309d
+ *     * Redistributions of source code must retain the above copyright
1b5309d
+ *       notice, this list of conditions and the following disclaimer.
1b5309d
+ *     * Redistributions in binary form must reproduce the above copyright
1b5309d
+ *       notice, this list of conditions and the following disclaimer in the
1b5309d
+ *       documentation and/or other materials provided with the distribution.
1b5309d
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the
1b5309d
+ *       names of its contributors may be used to endorse or promote products
1b5309d
+ *       derived from this software without specific prior written permission.
1b5309d
+ *
1b5309d
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
1b5309d
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
1b5309d
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
1b5309d
+ * ARE DISCLAIMED. IN NO EVENT SHALL <COPYRIGHT HOLDER> BE LIABLE FOR ANY
1b5309d
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
1b5309d
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
1b5309d
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
1b5309d
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
1b5309d
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
1b5309d
+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
1b5309d
+ *
1b5309d
+ * This file incorporates work covered by the following copyright and
1b5309d
+ * permission notice:
1b5309d
+ *     The Synopsys DWC ETHER XGMAC Software Driver and documentation
1b5309d
+ *     (hereinafter "Software") is an unsupported proprietary work of Synopsys,
1b5309d
+ *     Inc. unless otherwise expressly agreed to in writing between Synopsys
1b5309d
+ *     and you.
1b5309d
+ *
1b5309d
+ *     The Software IS NOT an item of Licensed Software or Licensed Product
1b5309d
+ *     under any End User Software License Agreement or Agreement for Licensed
1b5309d
+ *     Product with Synopsys or any supplement thereto.  Permission is hereby
1b5309d
+ *     granted, free of charge, to any person obtaining a copy of this software
1b5309d
+ *     annotated with this license and the Software, to deal in the Software
1b5309d
+ *     without restriction, including without limitation the rights to use,
1b5309d
+ *     copy, modify, merge, publish, distribute, sublicense, and/or sell copies
1b5309d
+ *     of the Software, and to permit persons to whom the Software is furnished
1b5309d
+ *     to do so, subject to the following conditions:
1b5309d
+ *
1b5309d
+ *     The above copyright notice and this permission notice shall be included
1b5309d
+ *     in all copies or substantial portions of the Software.
1b5309d
+ *
1b5309d
+ *     THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS"
1b5309d
+ *     BASIS AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
1b5309d
+ *     TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
1b5309d
+ *     PARTICULAR PURPOSE ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS
1b5309d
+ *     BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
1b5309d
+ *     CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
1b5309d
+ *     SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
1b5309d
+ *     INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
1b5309d
+ *     CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
1b5309d
+ *     ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
1b5309d
+ *     THE POSSIBILITY OF SUCH DAMAGE.
1b5309d
+ */
1b5309d
+
1b5309d
+#include <linux/netdevice.h>
1b5309d
+#include <net/dcbnl.h>
1b5309d
+
1b5309d
+#include "xgbe.h"
1b5309d
+#include "xgbe-common.h"
1b5309d
+
1b5309d
+static int xgbe_dcb_ieee_getets(struct net_device *netdev,
1b5309d
+				struct ieee_ets *ets)
1b5309d
+{
1b5309d
+	struct xgbe_prv_data *pdata = netdev_priv(netdev);
1b5309d
+
1b5309d
+	/* Set number of supported traffic classes */
1b5309d
+	ets->ets_cap = pdata->hw_feat.tc_cnt;
1b5309d
+
1b5309d
+	if (pdata->ets) {
1b5309d
+		ets->cbs = pdata->ets->cbs;
1b5309d
+		memcpy(ets->tc_tx_bw, pdata->ets->tc_tx_bw,
1b5309d
+		       sizeof(ets->tc_tx_bw));
1b5309d
+		memcpy(ets->tc_tsa, pdata->ets->tc_tsa,
1b5309d
+		       sizeof(ets->tc_tsa));
1b5309d
+		memcpy(ets->prio_tc, pdata->ets->prio_tc,
1b5309d
+		       sizeof(ets->prio_tc));
1b5309d
+	}
1b5309d
+
1b5309d
+	return 0;
1b5309d
+}
1b5309d
+
1b5309d
+static int xgbe_dcb_ieee_setets(struct net_device *netdev,
1b5309d
+				struct ieee_ets *ets)
1b5309d
+{
1b5309d
+	struct xgbe_prv_data *pdata = netdev_priv(netdev);
1b5309d
+	unsigned int i, tc_ets, tc_ets_weight;
1b5309d
+
1b5309d
+	tc_ets = 0;
1b5309d
+	tc_ets_weight = 0;
1b5309d
+	for (i = 0; i < IEEE_8021QAZ_MAX_TCS; i++) {
1b5309d
+		DBGPR("  TC%u: tx_bw=%hhu, rx_bw=%hhu, tsa=%hhu\n", i,
1b5309d
+		      ets->tc_tx_bw[i], ets->tc_rx_bw[i], ets->tc_tsa[i]);
1b5309d
+		DBGPR("  PRIO%u: TC=%hhu\n", i, ets->prio_tc[i]);
1b5309d
+
1b5309d
+		if ((ets->tc_tx_bw[i] || ets->tc_tsa[i]) &&
1b5309d
+		    (i >= pdata->hw_feat.tc_cnt))
1b5309d
+				return -EINVAL;
1b5309d
+
1b5309d
+		if (ets->prio_tc[i] >= pdata->hw_feat.tc_cnt)
1b5309d
+			return -EINVAL;
1b5309d
+
1b5309d
+		switch (ets->tc_tsa[i]) {
1b5309d
+		case IEEE_8021QAZ_TSA_STRICT:
1b5309d
+			break;
1b5309d
+		case IEEE_8021QAZ_TSA_ETS:
1b5309d
+			tc_ets = 1;
1b5309d
+			tc_ets_weight += ets->tc_tx_bw[i];
1b5309d
+			break;
1b5309d
+
1b5309d
+		default:
1b5309d
+			return -EINVAL;
1b5309d
+		}
1b5309d
+	}
1b5309d
+
1b5309d
+	/* Weights must add up to 100% */
1b5309d
+	if (tc_ets && (tc_ets_weight != 100))
1b5309d
+		return -EINVAL;
1b5309d
+
1b5309d
+	if (!pdata->ets) {
1b5309d
+		pdata->ets = devm_kzalloc(pdata->dev, sizeof(*pdata->ets),
1b5309d
+					  GFP_KERNEL);
1b5309d
+		if (!pdata->ets)
1b5309d
+			return -ENOMEM;
1b5309d
+	}
1b5309d
+
1b5309d
+	memcpy(pdata->ets, ets, sizeof(*pdata->ets));
1b5309d
+
1b5309d
+	pdata->hw_if.config_dcb_tc(pdata);
1b5309d
+
1b5309d
+	return 0;
1b5309d
+}
1b5309d
+
1b5309d
+static int xgbe_dcb_ieee_getpfc(struct net_device *netdev,
1b5309d
+				struct ieee_pfc *pfc)
1b5309d
+{
1b5309d
+	struct xgbe_prv_data *pdata = netdev_priv(netdev);
1b5309d
+
1b5309d
+	/* Set number of supported PFC traffic classes */
1b5309d
+	pfc->pfc_cap = pdata->hw_feat.tc_cnt;
1b5309d
+
1b5309d
+	if (pdata->pfc) {
1b5309d
+		pfc->pfc_en = pdata->pfc->pfc_en;
1b5309d
+		pfc->mbc = pdata->pfc->mbc;
1b5309d
+		pfc->delay = pdata->pfc->delay;
1b5309d
+	}
1b5309d
+
1b5309d
+	return 0;
1b5309d
+}
1b5309d
+
1b5309d
+static int xgbe_dcb_ieee_setpfc(struct net_device *netdev,
1b5309d
+				struct ieee_pfc *pfc)
1b5309d
+{
1b5309d
+	struct xgbe_prv_data *pdata = netdev_priv(netdev);
1b5309d
+
1b5309d
+	DBGPR("  cap=%hhu, en=%hhx, mbc=%hhu, delay=%hhu\n",
1b5309d
+	      pfc->pfc_cap, pfc->pfc_en, pfc->mbc, pfc->delay);
1b5309d
+
1b5309d
+	if (!pdata->pfc) {
1b5309d
+		pdata->pfc = devm_kzalloc(pdata->dev, sizeof(*pdata->pfc),
1b5309d
+					  GFP_KERNEL);
1b5309d
+		if (!pdata->pfc)
1b5309d
+			return -ENOMEM;
1b5309d
+	}
1b5309d
+
1b5309d
+	memcpy(pdata->pfc, pfc, sizeof(*pdata->pfc));
1b5309d
+
1b5309d
+	pdata->hw_if.config_dcb_pfc(pdata);
1b5309d
+
1b5309d
+	return 0;
1b5309d
+}
1b5309d
+
1b5309d
+static u8 xgbe_dcb_getdcbx(struct net_device *netdev)
1b5309d
+{
1b5309d
+	return DCB_CAP_DCBX_HOST | DCB_CAP_DCBX_VER_IEEE;
1b5309d
+}
1b5309d
+
1b5309d
+static u8 xgbe_dcb_setdcbx(struct net_device *netdev, u8 dcbx)
1b5309d
+{
1b5309d
+	u8 support = xgbe_dcb_getdcbx(netdev);
1b5309d
+
1b5309d
+	DBGPR("  DCBX=%#hhx\n", dcbx);
1b5309d
+
1b5309d
+	if (dcbx & ~support)
1b5309d
+		return 1;
1b5309d
+
1b5309d
+	if ((dcbx & support) != support)
1b5309d
+		return 1;
1b5309d
+
1b5309d
+	return 0;
1b5309d
+}
1b5309d
+
1b5309d
+static const struct dcbnl_rtnl_ops xgbe_dcbnl_ops = {
1b5309d
+	/* IEEE 802.1Qaz std */
1b5309d
+	.ieee_getets = xgbe_dcb_ieee_getets,
1b5309d
+	.ieee_setets = xgbe_dcb_ieee_setets,
1b5309d
+	.ieee_getpfc = xgbe_dcb_ieee_getpfc,
1b5309d
+	.ieee_setpfc = xgbe_dcb_ieee_setpfc,
1b5309d
+
1b5309d
+	/* DCBX configuration */
1b5309d
+	.getdcbx     = xgbe_dcb_getdcbx,
1b5309d
+	.setdcbx     = xgbe_dcb_setdcbx,
1b5309d
+};
1b5309d
+
1b5309d
+const struct dcbnl_rtnl_ops *xgbe_a0_get_dcbnl_ops(void)
1b5309d
+{
1b5309d
+	return &xgbe_dcbnl_ops;
1b5309d
+}
1b5309d
diff --git a/drivers/net/ethernet/amd/xgbe-a0/xgbe-debugfs.c b/drivers/net/ethernet/amd/xgbe-a0/xgbe-debugfs.c
1b5309d
new file mode 100644
0d59e0e
index 000000000000..ecfa6f91da22
1b5309d
--- /dev/null
1b5309d
+++ b/drivers/net/ethernet/amd/xgbe-a0/xgbe-debugfs.c
1b5309d
@@ -0,0 +1,373 @@
1b5309d
+/*
1b5309d
+ * AMD 10Gb Ethernet driver
1b5309d
+ *
1b5309d
+ * This file is available to you under your choice of the following two
1b5309d
+ * licenses:
1b5309d
+ *
1b5309d
+ * License 1: GPLv2
1b5309d
+ *
1b5309d
+ * Copyright (c) 2014 Advanced Micro Devices, Inc.
1b5309d
+ *
1b5309d
+ * This file is free software; you may copy, redistribute and/or modify
1b5309d
+ * it under the terms of the GNU General Public License as published by
1b5309d
+ * the Free Software Foundation, either version 2 of the License, or (at
1b5309d
+ * your option) any later version.
1b5309d
+ *
1b5309d
+ * This file is distributed in the hope that it will be useful, but
1b5309d
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
1b5309d
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
1b5309d
+ * General Public License for more details.
1b5309d
+ *
1b5309d
+ * You should have received a copy of the GNU General Public License
1b5309d
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
1b5309d
+ *
1b5309d
+ * This file incorporates work covered by the following copyright and
1b5309d
+ * permission notice:
1b5309d
+ *     The Synopsys DWC ETHER XGMAC Software Driver and documentation
1b5309d
+ *     (hereinafter "Software") is an unsupported proprietary work of Synopsys,
1b5309d
+ *     Inc. unless otherwise expressly agreed to in writing between Synopsys
1b5309d
+ *     and you.
1b5309d
+ *
1b5309d
+ *     The Software IS NOT an item of Licensed Software or Licensed Product
1b5309d
+ *     under any End User Software License Agreement or Agreement for Licensed
1b5309d
+ *     Product with Synopsys or any supplement thereto.  Permission is hereby
1b5309d
+ *     granted, free of charge, to any person obtaining a copy of this software
1b5309d
+ *     annotated with this license and the Software, to deal in the Software
1b5309d
+ *     without restriction, including without limitation the rights to use,
1b5309d
+ *     copy, modify, merge, publish, distribute, sublicense, and/or sell copies
1b5309d
+ *     of the Software, and to permit persons to whom the Software is furnished
1b5309d
+ *     to do so, subject to the following conditions:
1b5309d
+ *
1b5309d
+ *     The above copyright notice and this permission notice shall be included
1b5309d
+ *     in all copies or substantial portions of the Software.
1b5309d
+ *
1b5309d
+ *     THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS"
1b5309d
+ *     BASIS AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
1b5309d
+ *     TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
1b5309d
+ *     PARTICULAR PURPOSE ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS
1b5309d
+ *     BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
1b5309d
+ *     CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
1b5309d
+ *     SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
1b5309d
+ *     INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
1b5309d
+ *     CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
1b5309d
+ *     ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
1b5309d
+ *     THE POSSIBILITY OF SUCH DAMAGE.
1b5309d
+ *
1b5309d
+ *
1b5309d
+ * License 2: Modified BSD
1b5309d
+ *
1b5309d
+ * Copyright (c) 2014 Advanced Micro Devices, Inc.
1b5309d
+ * All rights reserved.
1b5309d
+ *
1b5309d
+ * Redistribution and use in source and binary forms, with or without
1b5309d
+ * modification, are permitted provided that the following conditions are met:
1b5309d
+ *     * Redistributions of source code must retain the above copyright
1b5309d
+ *       notice, this list of conditions and the following disclaimer.
1b5309d
+ *     * Redistributions in binary form must reproduce the above copyright
1b5309d
+ *       notice, this list of conditions and the following disclaimer in the
1b5309d
+ *       documentation and/or other materials provided with the distribution.
1b5309d
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the
1b5309d
+ *       names of its contributors may be used to endorse or promote products
1b5309d
+ *       derived from this software without specific prior written permission.
1b5309d
+ *
1b5309d
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
1b5309d
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
1b5309d
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
1b5309d
+ * ARE DISCLAIMED. IN NO EVENT SHALL <COPYRIGHT HOLDER> BE LIABLE FOR ANY
1b5309d
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
1b5309d
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
1b5309d
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
1b5309d
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
1b5309d
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
1b5309d
+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
1b5309d
+ *
1b5309d
+ * This file incorporates work covered by the following copyright and
1b5309d
+ * permission notice:
1b5309d
+ *     The Synopsys DWC ETHER XGMAC Software Driver and documentation
1b5309d
+ *     (hereinafter "Software") is an unsupported proprietary work of Synopsys,
1b5309d
+ *     Inc. unless otherwise expressly agreed to in writing between Synopsys
1b5309d
+ *     and you.
1b5309d
+ *
1b5309d
+ *     The Software IS NOT an item of Licensed Software or Licensed Product
1b5309d
+ *     under any End User Software License Agreement or Agreement for Licensed
1b5309d
+ *     Product with Synopsys or any supplement thereto.  Permission is hereby
1b5309d
+ *     granted, free of charge, to any person obtaining a copy of this software
1b5309d
+ *     annotated with this license and the Software, to deal in the Software
1b5309d
+ *     without restriction, including without limitation the rights to use,
1b5309d
+ *     copy, modify, merge, publish, distribute, sublicense, and/or sell copies
1b5309d
+ *     of the Software, and to permit persons to whom the Software is furnished
1b5309d
+ *     to do so, subject to the following conditions:
1b5309d
+ *
1b5309d
+ *     The above copyright notice and this permission notice shall be included
1b5309d
+ *     in all copies or substantial portions of the Software.
1b5309d
+ *
1b5309d
+ *     THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS"
1b5309d
+ *     BASIS AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
1b5309d
+ *     TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
1b5309d
+ *     PARTICULAR PURPOSE ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS
1b5309d
+ *     BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
1b5309d
+ *     CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
1b5309d
+ *     SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
1b5309d
+ *     INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
1b5309d
+ *     CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
1b5309d
+ *     ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
1b5309d
+ *     THE POSSIBILITY OF SUCH DAMAGE.
1b5309d
+ */
1b5309d
+
1b5309d
+#include <linux/debugfs.h>
1b5309d
+#include <linux/module.h>
1b5309d
+#include <linux/slab.h>
1b5309d
+
1b5309d
+#include "xgbe.h"
1b5309d
+#include "xgbe-common.h"
1b5309d
+
1b5309d
+static ssize_t xgbe_common_read(char __user *buffer, size_t count,
1b5309d
+				loff_t *ppos, unsigned int value)
1b5309d
+{
1b5309d
+	char *buf;
1b5309d
+	ssize_t len;
1b5309d
+
1b5309d
+	if (*ppos != 0)
1b5309d
+		return 0;
1b5309d
+
1b5309d
+	buf = kasprintf(GFP_KERNEL, "0x%08x\n", value);
1b5309d
+	if (!buf)
1b5309d
+		return -ENOMEM;
1b5309d
+
1b5309d
+	if (count < strlen(buf)) {
1b5309d
+		kfree(buf);
1b5309d
+		return -ENOSPC;
1b5309d
+	}
1b5309d
+
1b5309d
+	len = simple_read_from_buffer(buffer, count, ppos, buf, strlen(buf));
1b5309d
+	kfree(buf);
1b5309d
+
1b5309d
+	return len;
1b5309d
+}
1b5309d
+
1b5309d
+static ssize_t xgbe_common_write(const char __user *buffer, size_t count,
1b5309d
+				 loff_t *ppos, unsigned int *value)
1b5309d
+{
1b5309d
+	char workarea[32];
1b5309d
+	ssize_t len;
1b5309d
+	int ret;
1b5309d
+
1b5309d
+	if (*ppos != 0)
1b5309d
+		return 0;
1b5309d
+
1b5309d
+	if (count >= sizeof(workarea))
1b5309d
+		return -ENOSPC;
1b5309d
+
1b5309d
+	len = simple_write_to_buffer(workarea, sizeof(workarea) - 1, ppos,
1b5309d
+				     buffer, count);
1b5309d
+	if (len < 0)
1b5309d
+		return len;
1b5309d
+
1b5309d
+	workarea[len] = '\0';
1b5309d
+	ret = kstrtouint(workarea, 16, value);
1b5309d
+	if (ret)
1b5309d
+		return -EIO;
1b5309d
+
1b5309d
+	return len;
1b5309d
+}
1b5309d
+
1b5309d
+static ssize_t xgmac_reg_addr_read(struct file *filp, char __user *buffer,
1b5309d
+				   size_t count, loff_t *ppos)
1b5309d
+{
1b5309d
+	struct xgbe_prv_data *pdata = filp->private_data;
1b5309d
+
1b5309d
+	return xgbe_common_read(buffer, count, ppos, pdata->debugfs_xgmac_reg);
1b5309d
+}
1b5309d
+
1b5309d
+static ssize_t xgmac_reg_addr_write(struct file *filp,
1b5309d
+				    const char __user *buffer,
1b5309d
+				    size_t count, loff_t *ppos)
1b5309d
+{
1b5309d
+	struct xgbe_prv_data *pdata = filp->private_data;
1b5309d
+
1b5309d
+	return xgbe_common_write(buffer, count, ppos,
1b5309d
+				 &pdata->debugfs_xgmac_reg);
1b5309d
+}
1b5309d
+
1b5309d
+static ssize_t xgmac_reg_value_read(struct file *filp, char __user *buffer,
1b5309d
+				    size_t count, loff_t *ppos)
1b5309d
+{
1b5309d
+	struct xgbe_prv_data *pdata = filp->private_data;
1b5309d
+	unsigned int value;
1b5309d
+
1b5309d
+	value = XGMAC_IOREAD(pdata, pdata->debugfs_xgmac_reg);
1b5309d
+
1b5309d
+	return xgbe_common_read(buffer, count, ppos, value);
1b5309d
+}
1b5309d
+
1b5309d
+static ssize_t xgmac_reg_value_write(struct file *filp,
1b5309d
+				     const char __user *buffer,
1b5309d
+				     size_t count, loff_t *ppos)
1b5309d
+{
1b5309d
+	struct xgbe_prv_data *pdata = filp->private_data;
1b5309d
+	unsigned int value;
1b5309d
+	ssize_t len;
1b5309d
+
1b5309d
+	len = xgbe_common_write(buffer, count, ppos, &value);
1b5309d
+	if (len < 0)
1b5309d
+		return len;
1b5309d
+
1b5309d
+	XGMAC_IOWRITE(pdata, pdata->debugfs_xgmac_reg, value);
1b5309d
+
1b5309d
+	return len;
1b5309d
+}
1b5309d
+
1b5309d
+static const struct file_operations xgmac_reg_addr_fops = {
1b5309d
+	.owner = THIS_MODULE,
1b5309d
+	.open = simple_open,
1b5309d
+	.read =  xgmac_reg_addr_read,
1b5309d
+	.write = xgmac_reg_addr_write,
1b5309d
+};
1b5309d
+
1b5309d
+static const struct file_operations xgmac_reg_value_fops = {
1b5309d
+	.owner = THIS_MODULE,
1b5309d
+	.open = simple_open,
1b5309d
+	.read =  xgmac_reg_value_read,
1b5309d
+	.write = xgmac_reg_value_write,
1b5309d
+};
1b5309d
+
1b5309d
+static ssize_t xpcs_mmd_read(struct file *filp, char __user *buffer,
1b5309d
+			     size_t count, loff_t *ppos)
1b5309d
+{
1b5309d
+	struct xgbe_prv_data *pdata = filp->private_data;
1b5309d
+
1b5309d
+	return xgbe_common_read(buffer, count, ppos, pdata->debugfs_xpcs_mmd);
1b5309d
+}
1b5309d
+
1b5309d
+static ssize_t xpcs_mmd_write(struct file *filp, const char __user *buffer,
1b5309d
+			      size_t count, loff_t *ppos)
1b5309d
+{
1b5309d
+	struct xgbe_prv_data *pdata = filp->private_data;
1b5309d
+
1b5309d
+	return xgbe_common_write(buffer, count, ppos,
1b5309d
+				 &pdata->debugfs_xpcs_mmd);
1b5309d
+}
1b5309d
+
1b5309d
+static ssize_t xpcs_reg_addr_read(struct file *filp, char __user *buffer,
1b5309d
+				  size_t count, loff_t *ppos)
1b5309d
+{
1b5309d
+	struct xgbe_prv_data *pdata = filp->private_data;
1b5309d
+
1b5309d
+	return xgbe_common_read(buffer, count, ppos, pdata->debugfs_xpcs_reg);
1b5309d
+}
1b5309d
+
1b5309d
+static ssize_t xpcs_reg_addr_write(struct file *filp, const char __user *buffer,
1b5309d
+				   size_t count, loff_t *ppos)
1b5309d
+{
1b5309d
+	struct xgbe_prv_data *pdata = filp->private_data;
1b5309d
+
1b5309d
+	return xgbe_common_write(buffer, count, ppos,
1b5309d
+				 &pdata->debugfs_xpcs_reg);
1b5309d
+}
1b5309d
+
1b5309d
+static ssize_t xpcs_reg_value_read(struct file *filp, char __user *buffer,
1b5309d
+				   size_t count, loff_t *ppos)
1b5309d
+{
1b5309d
+	struct xgbe_prv_data *pdata = filp->private_data;
1b5309d
+	unsigned int value;
1b5309d
+
1b5309d
+	value = XMDIO_READ(pdata, pdata->debugfs_xpcs_mmd,
1b5309d
+			   pdata->debugfs_xpcs_reg);
1b5309d
+
1b5309d
+	return xgbe_common_read(buffer, count, ppos, value);
1b5309d
+}
1b5309d
+
1b5309d
+static ssize_t xpcs_reg_value_write(struct file *filp,
1b5309d
+				    const char __user *buffer,
1b5309d
+				    size_t count, loff_t *ppos)
1b5309d
+{
1b5309d
+	struct xgbe_prv_data *pdata = filp->private_data;
1b5309d
+	unsigned int value;
1b5309d
+	ssize_t len;
1b5309d
+
1b5309d
+	len = xgbe_common_write(buffer, count, ppos, &value);
1b5309d
+	if (len < 0)
1b5309d
+		return len;
1b5309d
+
1b5309d
+	XMDIO_WRITE(pdata, pdata->debugfs_xpcs_mmd, pdata->debugfs_xpcs_reg,
1b5309d
+		    value);
1b5309d
+
1b5309d
+	return len;
1b5309d
+}
1b5309d
+
1b5309d
+static const struct file_operations xpcs_mmd_fops = {
1b5309d
+	.owner = THIS_MODULE,
1b5309d
+	.open = simple_open,
1b5309d
+	.read =  xpcs_mmd_read,
1b5309d
+	.write = xpcs_mmd_write,
1b5309d
+};
1b5309d
+
1b5309d
+static const struct file_operations xpcs_reg_addr_fops = {
1b5309d
+	.owner = THIS_MODULE,
1b5309d
+	.open = simple_open,
1b5309d
+	.read =  xpcs_reg_addr_read,
1b5309d
+	.write = xpcs_reg_addr_write,
1b5309d
+};
1b5309d
+
1b5309d
+static const struct file_operations xpcs_reg_value_fops = {
1b5309d
+	.owner = THIS_MODULE,
1b5309d
+	.open = simple_open,
1b5309d
+	.read =  xpcs_reg_value_read,
1b5309d
+	.write = xpcs_reg_value_write,
1b5309d
+};
1b5309d
+
1b5309d
+void xgbe_a0_debugfs_init(struct xgbe_prv_data *pdata)
1b5309d
+{
1b5309d
+	struct dentry *pfile;
1b5309d
+	char *buf;
1b5309d
+
1b5309d
+	/* Set defaults */
1b5309d
+	pdata->debugfs_xgmac_reg = 0;
1b5309d
+	pdata->debugfs_xpcs_mmd = 1;
1b5309d
+	pdata->debugfs_xpcs_reg = 0;
1b5309d
+
1b5309d
+	buf = kasprintf(GFP_KERNEL, "amd-xgbe-a0-%s", pdata->netdev->name);
1b5309d
+	pdata->xgbe_debugfs = debugfs_create_dir(buf, NULL);
1b5309d
+	if (!pdata->xgbe_debugfs) {
1b5309d
+		netdev_err(pdata->netdev, "debugfs_create_dir failed\n");
1b5309d
+		return;
1b5309d
+	}
1b5309d
+
1b5309d
+	pfile = debugfs_create_file("xgmac_register", 0600,
1b5309d
+				    pdata->xgbe_debugfs, pdata,
1b5309d
+				    &xgmac_reg_addr_fops);
1b5309d
+	if (!pfile)
1b5309d
+		netdev_err(pdata->netdev, "debugfs_create_file failed\n");
1b5309d
+
1b5309d
+	pfile = debugfs_create_file("xgmac_register_value", 0600,
1b5309d
+				    pdata->xgbe_debugfs, pdata,
1b5309d
+				    &xgmac_reg_value_fops);
1b5309d
+	if (!pfile)
1b5309d
+		netdev_err(pdata->netdev, "debugfs_create_file failed\n");
1b5309d
+
1b5309d
+	pfile = debugfs_create_file("xpcs_mmd", 0600,
1b5309d
+				    pdata->xgbe_debugfs, pdata,
1b5309d
+				    &xpcs_mmd_fops);
1b5309d
+	if (!pfile)
1b5309d
+		netdev_err(pdata->netdev, "debugfs_create_file failed\n");
1b5309d
+
1b5309d
+	pfile = debugfs_create_file("xpcs_register", 0600,
1b5309d
+				    pdata->xgbe_debugfs, pdata,
1b5309d
+				    &xpcs_reg_addr_fops);
1b5309d
+	if (!pfile)
1b5309d
+		netdev_err(pdata->netdev, "debugfs_create_file failed\n");
1b5309d
+
1b5309d
+	pfile = debugfs_create_file("xpcs_register_value", 0600,
1b5309d
+				    pdata->xgbe_debugfs, pdata,
1b5309d
+				    &xpcs_reg_value_fops);
1b5309d
+	if (!pfile)
1b5309d
+		netdev_err(pdata->netdev, "debugfs_create_file failed\n");
1b5309d
+
1b5309d
+	kfree(buf);
1b5309d
+}
1b5309d
+
1b5309d
+void xgbe_a0_debugfs_exit(struct xgbe_prv_data *pdata)
1b5309d
+{
1b5309d
+	debugfs_remove_recursive(pdata->xgbe_debugfs);
1b5309d
+	pdata->xgbe_debugfs = NULL;
1b5309d
+}
1b5309d
diff --git a/drivers/net/ethernet/amd/xgbe-a0/xgbe-desc.c b/drivers/net/ethernet/amd/xgbe-a0/xgbe-desc.c
1b5309d
new file mode 100644
0d59e0e
index 000000000000..5dd57779c82c
1b5309d
--- /dev/null
1b5309d
+++ b/drivers/net/ethernet/amd/xgbe-a0/xgbe-desc.c
1b5309d
@@ -0,0 +1,636 @@
1b5309d
+/*
1b5309d
+ * AMD 10Gb Ethernet driver
1b5309d
+ *
1b5309d
+ * This file is available to you under your choice of the following two
1b5309d
+ * licenses:
1b5309d
+ *
1b5309d
+ * License 1: GPLv2
1b5309d
+ *
1b5309d
+ * Copyright (c) 2014 Advanced Micro Devices, Inc.
1b5309d
+ *
1b5309d
+ * This file is free software; you may copy, redistribute and/or modify
1b5309d
+ * it under the terms of the GNU General Public License as published by
1b5309d
+ * the Free Software Foundation, either version 2 of the License, or (at
1b5309d
+ * your option) any later version.
1b5309d
+ *
1b5309d
+ * This file is distributed in the hope that it will be useful, but
1b5309d
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
1b5309d
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
1b5309d
+ * General Public License for more details.
1b5309d
+ *
1b5309d
+ * You should have received a copy of the GNU General Public License
1b5309d
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
1b5309d
+ *
1b5309d
+ * This file incorporates work covered by the following copyright and
1b5309d
+ * permission notice:
1b5309d
+ *     The Synopsys DWC ETHER XGMAC Software Driver and documentation
1b5309d
+ *     (hereinafter "Software") is an unsupported proprietary work of Synopsys,
1b5309d
+ *     Inc. unless otherwise expressly agreed to in writing between Synopsys
1b5309d
+ *     and you.
1b5309d
+ *
1b5309d
+ *     The Software IS NOT an item of Licensed Software or Licensed Product
1b5309d
+ *     under any End User Software License Agreement or Agreement for Licensed
1b5309d
+ *     Product with Synopsys or any supplement thereto.  Permission is hereby
1b5309d
+ *     granted, free of charge, to any person obtaining a copy of this software
1b5309d
+ *     annotated with this license and the Software, to deal in the Software
1b5309d
+ *     without restriction, including without limitation the rights to use,
1b5309d
+ *     copy, modify, merge, publish, distribute, sublicense, and/or sell copies
1b5309d
+ *     of the Software, and to permit persons to whom the Software is furnished
1b5309d
+ *     to do so, subject to the following conditions:
1b5309d
+ *
1b5309d
+ *     The above copyright notice and this permission notice shall be included
1b5309d
+ *     in all copies or substantial portions of the Software.
1b5309d
+ *
1b5309d
+ *     THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS"
1b5309d
+ *     BASIS AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
1b5309d
+ *     TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
1b5309d
+ *     PARTICULAR PURPOSE ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS
1b5309d
+ *     BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
1b5309d
+ *     CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
1b5309d
+ *     SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
1b5309d
+ *     INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
1b5309d
+ *     CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
1b5309d
+ *     ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
1b5309d
+ *     THE POSSIBILITY OF SUCH DAMAGE.
1b5309d
+ *
1b5309d
+ *
1b5309d
+ * License 2: Modified BSD
1b5309d
+ *
1b5309d
+ * Copyright (c) 2014 Advanced Micro Devices, Inc.
1b5309d
+ * All rights reserved.
1b5309d
+ *
1b5309d
+ * Redistribution and use in source and binary forms, with or without
1b5309d
+ * modification, are permitted provided that the following conditions are met:
1b5309d
+ *     * Redistributions of source code must retain the above copyright
1b5309d
+ *       notice, this list of conditions and the following disclaimer.
1b5309d
+ *     * Redistributions in binary form must reproduce the above copyright
1b5309d
+ *       notice, this list of conditions and the following disclaimer in the
1b5309d
+ *       documentation and/or other materials provided with the distribution.
1b5309d
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the
1b5309d
+ *       names of its contributors may be used to endorse or promote products
1b5309d
+ *       derived from this software without specific prior written permission.
1b5309d
+ *
1b5309d
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
1b5309d
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
1b5309d
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
1b5309d
+ * ARE DISCLAIMED. IN NO EVENT SHALL <COPYRIGHT HOLDER> BE LIABLE FOR ANY
1b5309d
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
1b5309d
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
1b5309d
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
1b5309d
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
1b5309d
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
1b5309d
+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
1b5309d
+ *
1b5309d
+ * This file incorporates work covered by the following copyright and
1b5309d
+ * permission notice:
1b5309d
+ *     The Synopsys DWC ETHER XGMAC Software Driver and documentation
1b5309d
+ *     (hereinafter "Software") is an unsupported proprietary work of Synopsys,
1b5309d
+ *     Inc. unless otherwise expressly agreed to in writing between Synopsys
1b5309d
+ *     and you.
1b5309d
+ *
1b5309d
+ *     The Software IS NOT an item of Licensed Software or Licensed Product
1b5309d
+ *     under any End User Software License Agreement or Agreement for Licensed
1b5309d
+ *     Product with Synopsys or any supplement thereto.  Permission is hereby
1b5309d
+ *     granted, free of charge, to any person obtaining a copy of this software
1b5309d
+ *     annotated with this license and the Software, to deal in the Software
1b5309d
+ *     without restriction, including without limitation the rights to use,
1b5309d
+ *     copy, modify, merge, publish, distribute, sublicense, and/or sell copies
1b5309d
+ *     of the Software, and to permit persons to whom the Software is furnished
1b5309d
+ *     to do so, subject to the following conditions:
1b5309d
+ *
1b5309d
+ *     The above copyright notice and this permission notice shall be included
1b5309d
+ *     in all copies or substantial portions of the Software.
1b5309d
+ *
1b5309d
+ *     THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS"
1b5309d
+ *     BASIS AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
1b5309d
+ *     TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
1b5309d
+ *     PARTICULAR PURPOSE ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS
1b5309d
+ *     BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
1b5309d
+ *     CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
1b5309d
+ *     SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
1b5309d
+ *     INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
1b5309d
+ *     CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
1b5309d
+ *     ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
1b5309d
+ *     THE POSSIBILITY OF SUCH DAMAGE.
1b5309d
+ */
1b5309d
+
1b5309d
+#include "xgbe.h"
1b5309d
+#include "xgbe-common.h"