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From 6809645a740693c8c7fe1f86e396ae4c0cdac9ff Mon Sep 17 00:00:00 2001
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6a91557 |
From: Peter Robinson <pbrobinson@gmail.com>
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767f0d5 |
Date: Sun, 29 May 2016 11:34:51 +0100
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6a91557 |
Subject: [PATCH] arm: i.MX6 Utilite device dtb
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6a91557 |
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6a91557 |
---
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arch/arm/boot/dts/Makefile | 1 +
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arch/arm/boot/dts/imx6q-cm-fx6.dts | 136 ++++++++++++++++++++++++++++++++
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arch/arm/boot/dts/imx6q-utilite-pro.dts | 128 ++++++++++++++++++++++++++++++
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3 files changed, 265 insertions(+)
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create mode 100644 arch/arm/boot/dts/imx6q-utilite-pro.dts
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6a91557 |
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diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
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index a4a6d70..90a85a2 100644
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--- a/arch/arm/boot/dts/Makefile
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+++ b/arch/arm/boot/dts/Makefile
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@@ -348,6 +348,7 @@ dtb-$(CONFIG_SOC_IMX6Q) += \
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imx6q-tx6q-1020-comtft.dtb \
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imx6q-tx6q-1110.dtb \
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imx6q-udoo.dtb \
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+ imx6q-utilite-pro.dtb \
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imx6q-wandboard.dtb \
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imx6q-wandboard-revb1.dtb
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dtb-$(CONFIG_SOC_IMX6SL) += \
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889d497 |
diff --git a/arch/arm/boot/dts/imx6q-cm-fx6.dts b/arch/arm/boot/dts/imx6q-cm-fx6.dts
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index 99b46f8..f4fc22e 100644
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--- a/arch/arm/boot/dts/imx6q-cm-fx6.dts
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+++ b/arch/arm/boot/dts/imx6q-cm-fx6.dts
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@@ -31,6 +31,61 @@
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linux,default-trigger = "heartbeat";
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};
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};
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+
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+ regulators {
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+ compatible = "simple-bus";
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+ #address-cells = <1>;
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+ #size-cells = <0>;
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+
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+ reg_usb_otg_vbus: usb_otg_vbus {
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+ compatible = "regulator-fixed";
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+ regulator-name = "usb_otg_vbus";
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+ regulator-min-microvolt = <5000000>;
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+ regulator-max-microvolt = <5000000>;
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+ gpio = <&gpio3 22 0>;
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+ enable-active-high;
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+ };
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+
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+ reg_usb_h1_vbus: usb_h1_vbus {
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+ compatible = "regulator-fixed";
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+ regulator-name = "usb_h1_vbus";
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+ regulator-min-microvolt = <5000000>;
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+ regulator-max-microvolt = <5000000>;
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+ gpio = <&gpio7 8 0>;
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+ enable-active-high;
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+ };
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+ };
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+};
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+
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+&ecspi1 {
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+ fsl,spi-num-chipselects = <2>;
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+ cs-gpios = <&gpio2 30 0>, <&gpio3 19 0>;
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+ pinctrl-names = "default";
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+ pinctrl-0 = <&pinctrl_ecspi1>;
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+ status = "okay";
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+
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+ flash: m25p80@0 {
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+ #address-cells = <1>;
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+ #size-cells = <1>;
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+ compatible = "st,m25p", "jedec,spi-nor";
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+ spi-max-frequency = <20000000>;
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+ reg = <0>;
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+
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+ partition@0 {
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+ label = "uboot";
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+ reg = <0x0 0xc0000>;
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+ };
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+
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+ partition@c0000 {
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+ label = "uboot environment";
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+ reg = <0xc0000 0x40000>;
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+ };
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+
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+ partition@100000 {
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+ label = "reserved";
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+ reg = <0x100000 0x100000>;
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+ };
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+ };
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};
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&fec {
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@@ -46,8 +101,31 @@
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status = "okay";
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};
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+&i2c3 {
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+ pinctrl-names = "default";
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+ pinctrl-0 = <&pinctrl_i2c3>;
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+ status = "okay";
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+ clock-frequency = <100000>;
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+
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+ eeprom@50 {
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+ compatible = "at24,24c02";
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+ reg = <0x50>;
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+ pagesize = <16>;
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+ };
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+};
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+
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&iomuxc {
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imx6q-cm-fx6 {
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+ pinctrl_ecspi1: ecspi1grp {
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+ fsl,pins = <
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+ MX6QDL_PAD_EIM_D16__ECSPI1_SCLK 0x100b1
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+ MX6QDL_PAD_EIM_D17__ECSPI1_MISO 0x100b1
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+ MX6QDL_PAD_EIM_D18__ECSPI1_MOSI 0x100b1
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+ MX6QDL_PAD_EIM_EB2__GPIO2_IO30 0x100b1
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+ MX6QDL_PAD_EIM_D19__GPIO3_IO19 0x100b1
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+ >;
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+ };
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+
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pinctrl_enet: enetgrp {
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fsl,pins = <
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MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b0b0
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@@ -91,17 +169,75 @@
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>;
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};
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+ pinctrl_i2c3: i2c3grp {
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+ fsl,pins = <
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+ MX6QDL_PAD_GPIO_3__I2C3_SCL 0x4001b8b1
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+ MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001b8b1
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+ >;
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+ };
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+
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+ pinctrl_pcie: pciegrp {
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+ fsl,pins = <
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+ MX6QDL_PAD_ENET_RXD1__GPIO1_IO26 0x80000000
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+ MX6QDL_PAD_EIM_CS1__GPIO2_IO24 0x80000000
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+ >;
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+ };
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+
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pinctrl_uart4: uart4grp {
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fsl,pins = <
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MX6QDL_PAD_KEY_COL0__UART4_TX_DATA 0x1b0b1
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MX6QDL_PAD_KEY_ROW0__UART4_RX_DATA 0x1b0b1
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>;
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};
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+
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+ pinctrl_usbh1: usbh1grp {
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+ fsl,pins = <
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+ MX6QDL_PAD_SD3_RST__GPIO7_IO08 0x80000000
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+ >;
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+ };
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+
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+ pinctrl_usbotg: usbotggrp {
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+ fsl,pins = <
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+ MX6QDL_PAD_ENET_RX_ER__USB_OTG_ID 0x17059
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+ MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x80000000
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+ >;
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+ };
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};
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};
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+&pcie {
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+ pinctrl-names = "default";
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+ pinctrl-0 = <&pinctrl_pcie>;
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+ reset-gpio = <&gpio1 26 0>;
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+ power-on-gpio = <&gpio2 24 0>;
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+ status = "okay";
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+};
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+
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+&sata {
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+ status = "okay";
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+};
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+
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+&snvs_poweroff {
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+ status = "okay";
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+};
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+
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&uart4 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_uart4>;
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status = "okay";
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};
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+
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+&usbotg {
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+ vbus-supply = <®_usb_otg_vbus>;
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+ pinctrl-names = "default";
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+ pinctrl-0 = <&pinctrl_usbotg>;
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+ dr_mode = "otg";
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+ status = "okay";
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+};
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+
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+&usbh1 {
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+ vbus-supply = <®_usb_h1_vbus>;
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+ pinctrl-names = "default";
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+ pinctrl-0 = <&pinctrl_usbh1>;
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+ status = "okay";
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+};
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diff --git a/arch/arm/boot/dts/imx6q-utilite-pro.dts b/arch/arm/boot/dts/imx6q-utilite-pro.dts
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new file mode 100644
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index 0000000..3966595
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--- /dev/null
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+++ b/arch/arm/boot/dts/imx6q-utilite-pro.dts
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@@ -0,0 +1,128 @@
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+/*
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+ * Copyright 2016 Christopher Spinrath
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+ * Copyright 2013 CompuLab Ltd.
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+ *
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+ * Based on the GPLv2 licensed devicetree distributed with the vendor
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+ * kernel for the Utilite Pro:
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+ * Copyright 2013 CompuLab Ltd.
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+ * Author: Valentin Raevsky <valentin@xxxxxxxxxxxxxx>
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+ *
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+ * The code contained herein is licensed under the GNU General Public
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+ * License. You may obtain a copy of the GNU General Public License
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+ * Version 2 or later at the following locations:
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+ *
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+ * http://www.opensource.org/licenses/gpl-license.html
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+ * http://www.gnu.org/copyleft/gpl.html
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+ */
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+
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+#include "imx6q-cm-fx6.dts"
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+
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+/ {
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+ model = "CompuLab Utilite Pro";
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+ compatible = "compulab,utilite-pro", "compulab,cm-fx6", "fsl,imx6q";
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+
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+ aliases {
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+ ethernet1 = ð1;
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+ rtc0 = &em3027;
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+ rtc1 = &snvs_rtc;
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+ };
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+
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+ gpio-keys {
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+ compatible = "gpio-keys";
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+ power {
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+ label = "Power Button";
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+ gpios = <&gpio1 29 1>;
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+ linux,code = <116>; /* KEY_POWER */
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+ gpio-key,wakeup;
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+ };
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+ };
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+};
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+
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+&hdmi {
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+ ddc-i2c-bus = <&i2c2>;
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+ status = "okay";
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+};
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+
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+&i2c1 {
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+ pinctrl-names = "default";
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+ pinctrl-0 = <&pinctrl_i2c1>;
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+ status = "okay";
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+
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+ eeprom@50 {
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+ compatible = "at24,24c02";
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+ reg = <0x50>;
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+ pagesize = <16>;
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+ };
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+
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+ em3027: rtc@56 {
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+ compatible = "emmicro,em3027";
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767f0d5 |
+ reg = <0x56>;
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767f0d5 |
+ };
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+};
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+
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+&i2c2 {
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+ pinctrl-names = "default";
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+ pinctrl-0 = <&pinctrl_i2c2>;
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889d497 |
+ status = "okay";
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889d497 |
+};
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889d497 |
+
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+&iomuxc {
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889d497 |
+ pinctrl-names = "default";
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767f0d5 |
+ pinctrl-0 = <&pinctrl_hog>;
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+
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+ hog {
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767f0d5 |
+ pinctrl_hog: hoggrp {
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+ fsl,pins = <
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767f0d5 |
+ /* power button */
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767f0d5 |
+ MX6QDL_PAD_ENET_TXD1__GPIO1_IO29 0x80000000
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767f0d5 |
+ >;
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767f0d5 |
+ };
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767f0d5 |
+ };
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767f0d5 |
+
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767f0d5 |
+ imx6q-utilite-pro {
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767f0d5 |
+ pinctrl_i2c1: i2c1grp {
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767f0d5 |
+ fsl,pins = <
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767f0d5 |
+ MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1
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767f0d5 |
+ MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1
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767f0d5 |
+ >;
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767f0d5 |
+ };
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767f0d5 |
+
|
|
|
767f0d5 |
+ pinctrl_i2c2: i2c2grp {
|
|
|
767f0d5 |
+ fsl,pins = <
|
|
|
767f0d5 |
+ MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1
|
|
|
767f0d5 |
+ MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1
|
|
|
767f0d5 |
+ >;
|
|
|
767f0d5 |
+ };
|
|
|
767f0d5 |
+
|
|
|
767f0d5 |
+ pinctrl_uart2: uart2grp {
|
|
|
767f0d5 |
+ fsl,pins = <
|
|
|
767f0d5 |
+ MX6QDL_PAD_GPIO_7__UART2_TX_DATA 0x1b0b1
|
|
|
767f0d5 |
+ MX6QDL_PAD_GPIO_8__UART2_RX_DATA 0x1b0b1
|
|
|
767f0d5 |
+ MX6QDL_PAD_SD4_DAT5__UART2_RTS_B 0x1b0b1
|
|
|
767f0d5 |
+ MX6QDL_PAD_SD4_DAT6__UART2_CTS_B 0x1b0b1
|
|
|
767f0d5 |
+ >;
|
|
|
767f0d5 |
+ };
|
|
|
767f0d5 |
+ };
|
|
|
767f0d5 |
+};
|
|
|
767f0d5 |
+
|
|
|
767f0d5 |
+&pcie {
|
|
|
767f0d5 |
+ pcie@0,0 {
|
|
|
767f0d5 |
+ reg = <0x000000 0 0 0 0>;
|
|
|
767f0d5 |
+ #address-cells = <3>;
|
|
|
767f0d5 |
+ #size-cells = <2>;
|
|
|
767f0d5 |
+
|
|
|
767f0d5 |
+ /* non-removable i211 ethernet card */
|
|
|
767f0d5 |
+ eth1: intel,i211@pcie0,0 {
|
|
|
767f0d5 |
+ reg = <0x010000 0 0 0 0>;
|
|
|
767f0d5 |
+ };
|
|
|
767f0d5 |
+ };
|
|
|
767f0d5 |
+};
|
|
|
767f0d5 |
+
|
|
|
767f0d5 |
+&uart2 {
|
|
|
767f0d5 |
+ pinctrl-names = "default";
|
|
|
767f0d5 |
+ pinctrl-0 = <&pinctrl_uart2>;
|
|
|
767f0d5 |
+ fsl,uart-has-rtscts;
|
|
|
767f0d5 |
+ dma-names = "rx", "tx";
|
|
|
767f0d5 |
+ dmas = <&sdma 27 4 0>, <&sdma 28 4 0>;
|
|
|
889d497 |
+ status = "okay";
|
|
|
889d497 |
+};
|
|
|
767f0d5 |
--
|
|
|
767f0d5 |
2.7.4
|
|
|
767f0d5 |
|