|
 |
1a62f62 |
commit 682d055e6ac5c3855f51649de6d68e9bb29c26a6
|
|
|
1a62f62 |
Author: Valentin Raevsky <valentin@compulab.co.il>
|
|
|
1a62f62 |
Date: Tue Oct 29 14:11:43 2013 +0200
|
|
 |
4c74055 |
|
|
|
1a62f62 |
ARM: dts: Add initial support for cm-fx6.
|
|
|
1a62f62 |
|
|
|
1a62f62 |
Add initial support for cm-fx6 module.
|
|
|
1a62f62 |
|
|
|
1a62f62 |
cm-fx6 is a module based on mx6q SoC with the following features:
|
|
|
1a62f62 |
- Up to 4GB of DDR3
|
|
|
1a62f62 |
- 1 LCD/DVI output port
|
|
|
1a62f62 |
- 1 HDMI output port
|
|
|
1a62f62 |
- 2 LVDS LCD ports
|
|
|
1a62f62 |
- Gigabit Ethernet
|
|
|
1a62f62 |
- Analog Audio
|
|
|
1a62f62 |
- CAN
|
|
|
1a62f62 |
- SATA
|
|
|
1a62f62 |
- NAND
|
|
|
1a62f62 |
- PCIE
|
|
|
1a62f62 |
|
|
|
1a62f62 |
This patch allows to boot up the module, configures the serial console,
|
|
|
1a62f62 |
the Ethernet adapter and the heartbeat led.
|
|
|
1a62f62 |
|
|
|
1a62f62 |
cm-fx6 is embedded inside the Utilite computer.
|
|
|
1a62f62 |
|
|
|
1a62f62 |
Signed-off-by: Valentin Raevsky <valentin@compulab.co.il>
|
|
|
1a62f62 |
Signed-off-by: Igor Grinberg <grinberg@compulab.co.il>
|
|
|
1a62f62 |
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
|
|
|
4c74055 |
|
|
|
1a62f62 |
diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
|
|
|
1a62f62 |
index 8081479..5672e91 100644
|
|
|
1a62f62 |
--- a/arch/arm/boot/dts/Makefile
|
|
|
1a62f62 |
+++ b/arch/arm/boot/dts/Makefile
|
|
|
b1bf9ea |
@@ -162,6 +162,7 @@ dtb-$(CONFIG_ARCH_MXC) += \
|
|
|
1a62f62 |
imx6dl-sabresd.dtb \
|
|
|
1a62f62 |
imx6dl-wandboard.dtb \
|
|
|
1a62f62 |
imx6q-arm2.dtb \
|
|
|
1a62f62 |
+ imx6q-cm-fx6.dtb \
|
|
|
b1bf9ea |
imx6q-cubox-i.dtb \
|
|
|
1a62f62 |
imx6q-phytec-pbab01.dtb \
|
|
|
1a62f62 |
imx6q-sabreauto.dtb \
|
|
|
4c74055 |
diff --git a/arch/arm/boot/dts/imx6q-cm-fx6.dts b/arch/arm/boot/dts/imx6q-cm-fx6.dts
|
|
|
4c74055 |
new file mode 100644
|
|
|
1a62f62 |
index 0000000..99b46f8
|
|
|
4c74055 |
--- /dev/null
|
|
|
4c74055 |
+++ b/arch/arm/boot/dts/imx6q-cm-fx6.dts
|
|
|
1a62f62 |
@@ -0,0 +1,107 @@
|
|
|
4c74055 |
+/*
|
|
|
4c74055 |
+ * Copyright 2013 CompuLab Ltd.
|
|
|
4c74055 |
+ *
|
|
|
1a62f62 |
+ * Author: Valentin Raevsky <valentin@compulab.co.il>
|
|
|
1a62f62 |
+ *
|
|
|
4c74055 |
+ * The code contained herein is licensed under the GNU General Public
|
|
|
4c74055 |
+ * License. You may obtain a copy of the GNU General Public License
|
|
|
4c74055 |
+ * Version 2 or later at the following locations:
|
|
|
4c74055 |
+ *
|
|
|
4c74055 |
+ * http://www.opensource.org/licenses/gpl-license.html
|
|
|
4c74055 |
+ * http://www.gnu.org/copyleft/gpl.html
|
|
|
4c74055 |
+ */
|
|
|
4c74055 |
+
|
|
|
4c74055 |
+/dts-v1/;
|
|
|
4c74055 |
+#include "imx6q.dtsi"
|
|
|
4c74055 |
+
|
|
|
4c74055 |
+/ {
|
|
|
4c74055 |
+ model = "CompuLab CM-FX6";
|
|
|
4c74055 |
+ compatible = "compulab,cm-fx6", "fsl,imx6q";
|
|
|
4c74055 |
+
|
|
|
4c74055 |
+ memory {
|
|
|
4c74055 |
+ reg = <0x10000000 0x80000000>;
|
|
|
4c74055 |
+ };
|
|
|
4c74055 |
+
|
|
|
4c74055 |
+ leds {
|
|
|
4c74055 |
+ compatible = "gpio-leds";
|
|
|
4c74055 |
+
|
|
|
1a62f62 |
+ heartbeat-led {
|
|
|
4c74055 |
+ label = "Heartbeat";
|
|
|
4c74055 |
+ gpios = <&gpio2 31 0>;
|
|
|
4c74055 |
+ linux,default-trigger = "heartbeat";
|
|
|
4c74055 |
+ };
|
|
|
4c74055 |
+ };
|
|
|
4c74055 |
+};
|
|
|
4c74055 |
+
|
|
|
1a62f62 |
+&fec {
|
|
|
4c74055 |
+ pinctrl-names = "default";
|
|
|
1a62f62 |
+ pinctrl-0 = <&pinctrl_enet>;
|
|
|
1a62f62 |
+ phy-mode = "rgmii";
|
|
|
4c74055 |
+ status = "okay";
|
|
|
4c74055 |
+};
|
|
|
4c74055 |
+
|
|
|
1a62f62 |
+&gpmi {
|
|
|
4c74055 |
+ pinctrl-names = "default";
|
|
|
1a62f62 |
+ pinctrl-0 = <&pinctrl_gpmi_nand>;
|
|
|
4c74055 |
+ status = "okay";
|
|
|
4c74055 |
+};
|
|
|
4c74055 |
+
|
|
|
1a62f62 |
+&iomuxc {
|
|
|
1a62f62 |
+ imx6q-cm-fx6 {
|
|
|
1a62f62 |
+ pinctrl_enet: enetgrp {
|
|
|
1a62f62 |
+ fsl,pins = <
|
|
|
1a62f62 |
+ MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b0b0
|
|
|
1a62f62 |
+ MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b0b0
|
|
|
1a62f62 |
+ MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b0b0
|
|
|
1a62f62 |
+ MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b0b0
|
|
|
1a62f62 |
+ MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b0b0
|
|
|
1a62f62 |
+ MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b0b0
|
|
|
1a62f62 |
+ MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b0b0
|
|
|
1a62f62 |
+ MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b0b0
|
|
|
1a62f62 |
+ MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b0b0
|
|
|
1a62f62 |
+ MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b0b0
|
|
|
1a62f62 |
+ MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b0b0
|
|
|
1a62f62 |
+ MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b0b0
|
|
|
1a62f62 |
+ MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0
|
|
|
1a62f62 |
+ MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0
|
|
|
1a62f62 |
+ MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0
|
|
|
1a62f62 |
+ MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x4001b0a8
|
|
|
1a62f62 |
+ >;
|
|
|
1a62f62 |
+ };
|
|
|
1a62f62 |
+
|
|
|
1a62f62 |
+ pinctrl_gpmi_nand: gpminandgrp {
|
|
|
1a62f62 |
+ fsl,pins = <
|
|
|
1a62f62 |
+ MX6QDL_PAD_NANDF_CLE__NAND_CLE 0xb0b1
|
|
|
1a62f62 |
+ MX6QDL_PAD_NANDF_ALE__NAND_ALE 0xb0b1
|
|
|
1a62f62 |
+ MX6QDL_PAD_NANDF_WP_B__NAND_WP_B 0xb0b1
|
|
|
1a62f62 |
+ MX6QDL_PAD_NANDF_RB0__NAND_READY_B 0xb000
|
|
|
1a62f62 |
+ MX6QDL_PAD_NANDF_CS0__NAND_CE0_B 0xb0b1
|
|
|
1a62f62 |
+ MX6QDL_PAD_NANDF_CS1__NAND_CE1_B 0xb0b1
|
|
|
1a62f62 |
+ MX6QDL_PAD_SD4_CMD__NAND_RE_B 0xb0b1
|
|
|
1a62f62 |
+ MX6QDL_PAD_SD4_CLK__NAND_WE_B 0xb0b1
|
|
|
1a62f62 |
+ MX6QDL_PAD_NANDF_D0__NAND_DATA00 0xb0b1
|
|
|
1a62f62 |
+ MX6QDL_PAD_NANDF_D1__NAND_DATA01 0xb0b1
|
|
|
1a62f62 |
+ MX6QDL_PAD_NANDF_D2__NAND_DATA02 0xb0b1
|
|
|
1a62f62 |
+ MX6QDL_PAD_NANDF_D3__NAND_DATA03 0xb0b1
|
|
|
1a62f62 |
+ MX6QDL_PAD_NANDF_D4__NAND_DATA04 0xb0b1
|
|
|
1a62f62 |
+ MX6QDL_PAD_NANDF_D5__NAND_DATA05 0xb0b1
|
|
|
1a62f62 |
+ MX6QDL_PAD_NANDF_D6__NAND_DATA06 0xb0b1
|
|
|
1a62f62 |
+ MX6QDL_PAD_NANDF_D7__NAND_DATA07 0xb0b1
|
|
|
1a62f62 |
+ MX6QDL_PAD_SD4_DAT0__NAND_DQS 0x00b1
|
|
|
1a62f62 |
+ >;
|
|
|
1a62f62 |
+ };
|
|
|
1a62f62 |
+
|
|
|
1a62f62 |
+ pinctrl_uart4: uart4grp {
|
|
|
1a62f62 |
+ fsl,pins = <
|
|
|
1a62f62 |
+ MX6QDL_PAD_KEY_COL0__UART4_TX_DATA 0x1b0b1
|
|
|
1a62f62 |
+ MX6QDL_PAD_KEY_ROW0__UART4_RX_DATA 0x1b0b1
|
|
|
1a62f62 |
+ >;
|
|
|
1a62f62 |
+ };
|
|
|
1a62f62 |
+ };
|
|
|
1a62f62 |
+};
|
|
|
1a62f62 |
+
|
|
|
4c74055 |
+&uart4 {
|
|
|
4c74055 |
+ pinctrl-names = "default";
|
|
|
1a62f62 |
+ pinctrl-0 = <&pinctrl_uart4>;
|
|
|
4c74055 |
+ status = "okay";
|
|
|
4c74055 |
+};
|
|
|
1a62f62 |
+
|
|
|
b1bf9ea |
+&sata {
|
|
|
b1bf9ea |
+ status = "okay";
|
|
|
b1bf9ea |
+};
|