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9b985dc |
From b41023282d07b61a53e2c9b9508912b1e7ce7b4f Mon Sep 17 00:00:00 2001
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9b985dc |
From: Randy Li <ayaka@soulik.info>
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9b985dc |
Date: Thu, 21 Jun 2018 21:32:10 +0800
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9b985dc |
Subject: arm64: dts: rockchip: add some common pin-settings to rk3399
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9b985dc |
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9b985dc |
Those pins would be used by many boards.
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9b985dc |
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9b985dc |
Signed-off-by: Randy Li <ayaka@soulik.info>
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9b985dc |
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
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9b985dc |
---
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9b985dc |
arch/arm64/boot/dts/rockchip/rk3399.dtsi | 86 ++++++++++++++++++++++++++------
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9b985dc |
1 file changed, 72 insertions(+), 14 deletions(-)
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9b985dc |
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9b985dc |
diff --git a/arch/arm64/boot/dts/rockchip/rk3399.dtsi b/arch/arm64/boot/dts/rockchip/rk3399.dtsi
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9b985dc |
index adb037cd80fe..87350c694b38 100644
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9b985dc |
--- a/arch/arm64/boot/dts/rockchip/rk3399.dtsi
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9b985dc |
+++ b/arch/arm64/boot/dts/rockchip/rk3399.dtsi
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9b985dc |
@@ -1923,19 +1923,49 @@
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drive-strength = <12>;
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9b985dc |
};
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9b985dc |
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9b985dc |
+ pcfg_pull_none_13ma: pcfg-pull-none-13ma {
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9b985dc |
+ bias-disable;
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+ drive-strength = <13>;
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9b985dc |
+ };
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9b985dc |
+
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9b985dc |
+ pcfg_pull_none_18ma: pcfg-pull-none-18ma {
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9b985dc |
+ bias-disable;
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+ drive-strength = <18>;
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+ };
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9b985dc |
+
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9b985dc |
+ pcfg_pull_none_20ma: pcfg-pull-none-20ma {
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9b985dc |
+ bias-disable;
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+ drive-strength = <20>;
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+ };
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+
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+ pcfg_pull_up_2ma: pcfg-pull-up-2ma {
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+ bias-pull-up;
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+ drive-strength = <2>;
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+ };
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+
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pcfg_pull_up_8ma: pcfg-pull-up-8ma {
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9b985dc |
bias-pull-up;
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drive-strength = <8>;
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9b985dc |
};
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9b985dc |
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+ pcfg_pull_up_18ma: pcfg-pull-up-18ma {
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+ bias-pull-up;
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+ drive-strength = <18>;
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+ };
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+
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+ pcfg_pull_up_20ma: pcfg-pull-up-20ma {
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+ bias-pull-up;
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+ drive-strength = <20>;
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+ };
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+
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pcfg_pull_down_4ma: pcfg-pull-down-4ma {
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bias-pull-down;
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drive-strength = <4>;
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};
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- pcfg_pull_up_2ma: pcfg-pull-up-2ma {
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- bias-pull-up;
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- drive-strength = <2>;
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+ pcfg_pull_down_8ma: pcfg-pull-down-8ma {
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+ bias-pull-down;
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+ drive-strength = <8>;
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};
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pcfg_pull_down_12ma: pcfg-pull-down-12ma {
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@@ -1943,9 +1973,22 @@
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drive-strength = <12>;
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};
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- pcfg_pull_none_13ma: pcfg-pull-none-13ma {
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- bias-disable;
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- drive-strength = <13>;
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+ pcfg_pull_down_18ma: pcfg-pull-down-18ma {
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+ bias-pull-down;
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+ drive-strength = <18>;
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+ };
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+
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+ pcfg_pull_down_20ma: pcfg-pull-down-20ma {
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+ bias-pull-down;
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+ drive-strength = <20>;
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+ };
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+
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+ pcfg_output_high: pcfg-output-high {
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+ output-high;
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+ };
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+
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+ pcfg_output_low: pcfg-output-low {
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+ output-low;
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};
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clock {
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@@ -2468,45 +2511,60 @@
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pwm0 {
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pwm0_pin: pwm0-pin {
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rockchip,pins =
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- <4 18 RK_FUNC_1 &pcfg_pull_none>;
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+ <4 RK_PC2 RK_FUNC_1 &pcfg_pull_none>;
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+ };
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+
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+ pwm0_pin_pull_down: pwm0-pin-pull-down {
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+ rockchip,pins =
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+ <4 RK_PC2 RK_FUNC_1 &pcfg_pull_down>;
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};
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vop0_pwm_pin: vop0-pwm-pin {
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rockchip,pins =
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- <4 18 RK_FUNC_2 &pcfg_pull_none>;
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+ <4 RK_PC2 RK_FUNC_2 &pcfg_pull_none>;
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+ };
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+
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+ vop1_pwm_pin: vop1-pwm-pin {
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+ rockchip,pins =
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+ <4 RK_PC2 RK_FUNC_3 &pcfg_pull_none>;
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};
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};
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pwm1 {
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pwm1_pin: pwm1-pin {
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rockchip,pins =
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- <4 22 RK_FUNC_1 &pcfg_pull_none>;
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+ <4 RK_PC6 RK_FUNC_1 &pcfg_pull_none>;
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9b985dc |
};
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9b985dc |
- vop1_pwm_pin: vop1-pwm-pin {
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+ pwm1_pin_pull_down: pwm1-pin-pull-down {
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9b985dc |
rockchip,pins =
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- <4 18 RK_FUNC_3 &pcfg_pull_none>;
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+ <4 RK_PC6 RK_FUNC_1 &pcfg_pull_down>;
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};
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};
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pwm2 {
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pwm2_pin: pwm2-pin {
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rockchip,pins =
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- <1 19 RK_FUNC_1 &pcfg_pull_none>;
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+ <1 RK_PC3 RK_FUNC_1 &pcfg_pull_none>;
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+ };
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9b985dc |
+
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9b985dc |
+ pwm2_pin_pull_down: pwm2-pin-pull-down {
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9b985dc |
+ rockchip,pins =
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9b985dc |
+ <1 RK_PC3 RK_FUNC_1 &pcfg_pull_down>;
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};
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};
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pwm3a {
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pwm3a_pin: pwm3a-pin {
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rockchip,pins =
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- <0 6 RK_FUNC_1 &pcfg_pull_none>;
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+ <0 RK_PA6 RK_FUNC_1 &pcfg_pull_none>;
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};
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};
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pwm3b {
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pwm3b_pin: pwm3b-pin {
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rockchip,pins =
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- <1 14 RK_FUNC_1 &pcfg_pull_none>;
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+ <1 RK_PB6 RK_FUNC_1 &pcfg_pull_none>;
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9b985dc |
};
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9b985dc |
};
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9b985dc |
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9b985dc |
--
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9b985dc |
cgit 1.2-0.3.lf.el7
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2f12b3e |
From 7c41a3f42a51d88e271c989c16be178bd6d38dfe Mon Sep 17 00:00:00 2001
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2f12b3e |
From: Peter Robinson <pbrobinson@gmail.com>
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2f12b3e |
Date: Mon, 10 Sep 2018 18:17:36 +0100
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2f12b3e |
Subject: [PATCH 1/4] arm64: dts: rockchip: add 96boards RK3399 Ficus board
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2f12b3e |
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2f12b3e |
The RK3399 Ficus board is an Enterprise Edition board
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2f12b3e |
manufactured by Vamrs Ltd., based on the Rockchip RK3399 SoC.
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2f12b3e |
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2f12b3e |
The board exposes a bunch of nice peripherals, including
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2f12b3e |
SATA, HDMI, MIPI CSI, Ethernet, WiFi, and PCIe.
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2f12b3e |
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2f12b3e |
Signed-off-by: Ezequiel Garcia <ezequiel@collabora.com>
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2f12b3e |
Reviewed-by: Rob Herring <robh@kernel.org>
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2f12b3e |
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
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2f12b3e |
Signed-off-by: Peter Robinson <pbrobinson@gmail.com>
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2f12b3e |
---
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2f12b3e |
.../devicetree/bindings/arm/rockchip.txt | 5 +
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2f12b3e |
arch/arm64/boot/dts/rockchip/Makefile | 1 +
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arch/arm64/boot/dts/rockchip/rk3399-ficus.dts | 514 ++++++++++++++++++
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3 files changed, 520 insertions(+)
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create mode 100644 arch/arm64/boot/dts/rockchip/rk3399-ficus.dts
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2f12b3e |
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diff --git a/Documentation/devicetree/bindings/arm/rockchip.txt b/Documentation/devicetree/bindings/arm/rockchip.txt
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index 1c1d62d03c4f..d46c5d43e27f 100644
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2f12b3e |
--- a/Documentation/devicetree/bindings/arm/rockchip.txt
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+++ b/Documentation/devicetree/bindings/arm/rockchip.txt
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@@ -1,5 +1,10 @@
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Rockchip platforms device tree bindings
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2f12b3e |
---------------------------------------
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+
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+- 96boards RK3399 Ficus (ROCK960 Enterprise Edition)
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2f12b3e |
+ Required root node properties:
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2f12b3e |
+ - compatible = "vamrs,ficus", "rockchip,rk3399";
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2f12b3e |
+
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2f12b3e |
- Amarula Vyasa RK3288 board
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2f12b3e |
Required root node properties:
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2f12b3e |
- compatible = "amarula,vyasa-rk3288", "rockchip,rk3288";
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2f12b3e |
diff --git a/arch/arm64/boot/dts/rockchip/Makefile b/arch/arm64/boot/dts/rockchip/Makefile
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2f12b3e |
index 48a83f882947..2811fb701f12 100644
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2f12b3e |
--- a/arch/arm64/boot/dts/rockchip/Makefile
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2f12b3e |
+++ b/arch/arm64/boot/dts/rockchip/Makefile
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2f12b3e |
@@ -9,6 +9,7 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3368-orion-r68-meta.dtb
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2f12b3e |
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3368-px5-evb.dtb
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2f12b3e |
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3368-r88.dtb
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2f12b3e |
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-evb.dtb
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2f12b3e |
+dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-ficus.dtb
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dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-firefly.dtb
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2f12b3e |
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-gru-kevin.dtb
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2f12b3e |
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-puma-haikou.dtb
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2f12b3e |
diff --git a/arch/arm64/boot/dts/rockchip/rk3399-ficus.dts b/arch/arm64/boot/dts/rockchip/rk3399-ficus.dts
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2f12b3e |
new file mode 100644
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2f12b3e |
index 000000000000..0d14183dd4a9
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2f12b3e |
--- /dev/null
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2f12b3e |
+++ b/arch/arm64/boot/dts/rockchip/rk3399-ficus.dts
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2f12b3e |
@@ -0,0 +1,514 @@
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2f12b3e |
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
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2f12b3e |
+/*
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2f12b3e |
+ * Copyright (c) 2018 Collabora Ltd.
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2f12b3e |
+ * Copyright (c) 2018 Fuzhou Rockchip Electronics Co., Ltd.
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2f12b3e |
+ *
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2f12b3e |
+ * Schematics available at https://dl.vamrs.com/products/ficus/docs/hw
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2f12b3e |
+ */
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2f12b3e |
+
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2f12b3e |
+/dts-v1/;
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2f12b3e |
+#include "rk3399.dtsi"
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2f12b3e |
+#include "rk3399-opp.dtsi"
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2f12b3e |
+
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2f12b3e |
+/ {
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2f12b3e |
+ model = "96boards RK3399 Ficus";
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2f12b3e |
+ compatible = "vamrs,ficus", "rockchip,rk3399";
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2f12b3e |
+
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2f12b3e |
+ chosen {
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2f12b3e |
+ stdout-path = "serial2:1500000n8";
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2f12b3e |
+ };
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2f12b3e |
+
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2f12b3e |
+ clkin_gmac: external-gmac-clock {
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2f12b3e |
+ compatible = "fixed-clock";
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2f12b3e |
+ clock-frequency = <125000000>;
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2f12b3e |
+ clock-output-names = "clkin_gmac";
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2f12b3e |
+ #clock-cells = <0>;
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2f12b3e |
+ };
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2f12b3e |
+
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2f12b3e |
+ vcc1v8_s0: vcc1v8-s0 {
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2f12b3e |
+ compatible = "regulator-fixed";
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2f12b3e |
+ regulator-name = "vcc1v8_s0";
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2f12b3e |
+ regulator-min-microvolt = <1800000>;
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2f12b3e |
+ regulator-max-microvolt = <1800000>;
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2f12b3e |
+ regulator-always-on;
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2f12b3e |
+ };
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2f12b3e |
+
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2f12b3e |
+ vcc_sys: vcc-sys {
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2f12b3e |
+ compatible = "regulator-fixed";
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2f12b3e |
+ regulator-name = "vcc_sys";
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2f12b3e |
+ regulator-min-microvolt = <5000000>;
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2f12b3e |
+ regulator-max-microvolt = <5000000>;
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2f12b3e |
+ regulator-always-on;
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2f12b3e |
+ };
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2f12b3e |
+
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2f12b3e |
+ vcc3v3_sys: vcc3v3-sys {
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2f12b3e |
+ compatible = "regulator-fixed";
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2f12b3e |
+ regulator-name = "vcc3v3_sys";
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2f12b3e |
+ regulator-min-microvolt = <3300000>;
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2f12b3e |
+ regulator-max-microvolt = <3300000>;
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2f12b3e |
+ regulator-always-on;
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2f12b3e |
+ vin-supply = <&vcc_sys>;
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2f12b3e |
+ };
|
|
|
2f12b3e |
+
|
|
|
2f12b3e |
+ vcc3v3_pcie: vcc3v3-pcie-regulator {
|
|
|
2f12b3e |
+ compatible = "regulator-fixed";
|
|
|
2f12b3e |
+ enable-active-high;
|
|
|
2f12b3e |
+ gpio = <&gpio1 24 GPIO_ACTIVE_HIGH>;
|
|
|
2f12b3e |
+ pinctrl-names = "default";
|
|
|
2f12b3e |
+ pinctrl-0 = <&pcie_drv>;
|
|
|
2f12b3e |
+ regulator-boot-on;
|
|
|
2f12b3e |
+ regulator-name = "vcc3v3_pcie";
|
|
|
2f12b3e |
+ vin-supply = <&vcc3v3_sys>;
|
|
|
2f12b3e |
+ };
|
|
|
2f12b3e |
+
|
|
|
2f12b3e |
+ vdd_log: vdd-log {
|
|
|
2f12b3e |
+ compatible = "pwm-regulator";
|
|
|
2f12b3e |
+ pwms = <&pwm2 0 25000 0>;
|
|
|
2f12b3e |
+ regulator-name = "vdd_log";
|
|
|
2f12b3e |
+ regulator-min-microvolt = <800000>;
|
|
|
2f12b3e |
+ regulator-max-microvolt = <1400000>;
|
|
|
2f12b3e |
+ regulator-always-on;
|
|
|
2f12b3e |
+ regulator-boot-on;
|
|
|
2f12b3e |
+
|
|
|
2f12b3e |
+ /* for rockchip boot on */
|
|
|
2f12b3e |
+ rockchip,pwm_id= <2>;
|
|
|
2f12b3e |
+ rockchip,pwm_voltage = <900000>;
|
|
|
2f12b3e |
+
|
|
|
2f12b3e |
+ vin-supply = <&vcc_sys>;
|
|
|
2f12b3e |
+ };
|
|
|
2f12b3e |
+
|
|
|
2f12b3e |
+};
|
|
|
2f12b3e |
+
|
|
|
2f12b3e |
+&cpu_l0 {
|
|
|
2f12b3e |
+ cpu-supply = <&vdd_cpu_l>;
|
|
|
2f12b3e |
+};
|
|
|
2f12b3e |
+
|
|
|
2f12b3e |
+&cpu_l1 {
|
|
|
2f12b3e |
+ cpu-supply = <&vdd_cpu_l>;
|
|
|
2f12b3e |
+};
|
|
|
2f12b3e |
+
|
|
|
2f12b3e |
+&cpu_l2 {
|
|
|
2f12b3e |
+ cpu-supply = <&vdd_cpu_l>;
|
|
|
2f12b3e |
+};
|
|
|
2f12b3e |
+
|
|
|
2f12b3e |
+&cpu_l3 {
|
|
|
2f12b3e |
+ cpu-supply = <&vdd_cpu_l>;
|
|
|
2f12b3e |
+};
|
|
|
2f12b3e |
+
|
|
|
2f12b3e |
+&cpu_b0 {
|
|
|
2f12b3e |
+ cpu-supply = <&vdd_cpu_b>;
|
|
|
2f12b3e |
+};
|
|
|
2f12b3e |
+
|
|
|
2f12b3e |
+&cpu_b1 {
|
|
|
2f12b3e |
+ cpu-supply = <&vdd_cpu_b>;
|
|
|
2f12b3e |
+};
|
|
|
2f12b3e |
+
|
|
|
2f12b3e |
+&emmc_phy {
|
|
|
2f12b3e |
+ status = "okay";
|
|
|
2f12b3e |
+};
|
|
|
2f12b3e |
+
|
|
|
2f12b3e |
+&gmac {
|
|
|
2f12b3e |
+ assigned-clocks = <&cru SCLK_RMII_SRC>;
|
|
|
2f12b3e |
+ assigned-clock-parents = <&clkin_gmac>;
|
|
|
2f12b3e |
+ clock_in_out = "input";
|
|
|
2f12b3e |
+ phy-supply = <&vcc3v3_sys>;
|
|
|
2f12b3e |
+ phy-mode = "rgmii";
|
|
|
2f12b3e |
+ pinctrl-names = "default";
|
|
|
2f12b3e |
+ pinctrl-0 = <&rgmii_pins>;
|
|
|
2f12b3e |
+ snps,reset-gpio = <&gpio3 RK_PB7 GPIO_ACTIVE_LOW>;
|
|
|
2f12b3e |
+ snps,reset-active-low;
|
|
|
2f12b3e |
+ snps,reset-delays-us = <0 10000 50000>;
|
|
|
2f12b3e |
+ tx_delay = <0x28>;
|
|
|
2f12b3e |
+ rx_delay = <0x11>;
|
|
|
2f12b3e |
+ status = "okay";
|
|
|
2f12b3e |
+};
|
|
|
2f12b3e |
+
|
|
|
2f12b3e |
+&hdmi {
|
|
|
2f12b3e |
+ ddc-i2c-bus = <&i2c3>;
|
|
|
2f12b3e |
+ pinctrl-names = "default";
|
|
|
2f12b3e |
+ pinctrl-0 = <&hdmi_cec>;
|
|
|
2f12b3e |
+ status = "okay";
|
|
|
2f12b3e |
+};
|
|
|
2f12b3e |
+
|
|
|
2f12b3e |
+&i2c0 {
|
|
|
2f12b3e |
+ clock-frequency = <400000>;
|
|
|
2f12b3e |
+ i2c-scl-rising-time-ns = <168>;
|
|
|
2f12b3e |
+ i2c-scl-falling-time-ns = <4>;
|
|
|
2f12b3e |
+ status = "okay";
|
|
|
2f12b3e |
+
|
|
|
2f12b3e |
+ vdd_cpu_b: regulator@40 {
|
|
|
2f12b3e |
+ compatible = "silergy,syr827";
|
|
|
2f12b3e |
+ reg = <0x40>;
|
|
|
2f12b3e |
+ fcs,suspend-voltage-selector = <1>;
|
|
|
2f12b3e |
+ regulator-name = "vdd_cpu_b";
|
|
|
2f12b3e |
+ regulator-min-microvolt = <712500>;
|
|
|
2f12b3e |
+ regulator-max-microvolt = <1500000>;
|
|
|
2f12b3e |
+ regulator-ramp-delay = <1000>;
|
|
|
2f12b3e |
+ regulator-always-on;
|
|
|
2f12b3e |
+ regulator-boot-on;
|
|
|
2f12b3e |
+ vin-supply = <&vcc_sys>;
|
|
|
2f12b3e |
+ status = "okay";
|
|
|
2f12b3e |
+
|
|
|
2f12b3e |
+ regulator-state-mem {
|
|
|
2f12b3e |
+ regulator-off-in-suspend;
|
|
|
2f12b3e |
+ };
|
|
|
2f12b3e |
+ };
|
|
|
2f12b3e |
+
|
|
|
2f12b3e |
+ vdd_gpu: regulator@41 {
|
|
|
2f12b3e |
+ compatible = "silergy,syr828";
|
|
|
2f12b3e |
+ reg = <0x41>;
|
|
|
2f12b3e |
+ fcs,suspend-voltage-selector = <1>;
|
|
|
2f12b3e |
+ regulator-name = "vdd_gpu";
|
|
|
2f12b3e |
+ regulator-min-microvolt = <712500>;
|
|
|
2f12b3e |
+ regulator-max-microvolt = <1500000>;
|
|
|
2f12b3e |
+ regulator-ramp-delay = <1000>;
|
|
|
2f12b3e |
+ regulator-always-on;
|
|
|
2f12b3e |
+ regulator-boot-on;
|
|
|
2f12b3e |
+ vin-supply = <&vcc_sys>;
|
|
|
2f12b3e |
+ regulator-state-mem {
|
|
|
2f12b3e |
+ regulator-off-in-suspend;
|
|
|
2f12b3e |
+ };
|
|
|
2f12b3e |
+ };
|
|
|
2f12b3e |
+
|
|
|
2f12b3e |
+ rk808: pmic@1b {
|
|
|
2f12b3e |
+ compatible = "rockchip,rk808";
|
|
|
2f12b3e |
+ reg = <0x1b>;
|
|
|
2f12b3e |
+ interrupt-parent = <&gpio1>;
|
|
|
2f12b3e |
+ interrupts = <21 IRQ_TYPE_LEVEL_LOW>;
|
|
|
2f12b3e |
+ pinctrl-names = "default";
|
|
|
2f12b3e |
+ pinctrl-0 = <&pmic_int_l>;
|
|
|
2f12b3e |
+ rockchip,system-power-controller;
|
|
|
2f12b3e |
+ wakeup-source;
|
|
|
2f12b3e |
+ #clock-cells = <1>;
|
|
|
2f12b3e |
+ clock-output-names = "xin32k", "rk808-clkout2";
|
|
|
2f12b3e |
+
|
|
|
2f12b3e |
+ vcc1-supply = <&vcc_sys>;
|
|
|
2f12b3e |
+ vcc2-supply = <&vcc_sys>;
|
|
|
2f12b3e |
+ vcc3-supply = <&vcc_sys>;
|
|
|
2f12b3e |
+ vcc4-supply = <&vcc_sys>;
|
|
|
2f12b3e |
+ vcc6-supply = <&vcc_sys>;
|
|
|
2f12b3e |
+ vcc7-supply = <&vcc_sys>;
|
|
|
2f12b3e |
+ vcc8-supply = <&vcc3v3_sys>;
|
|
|
2f12b3e |
+ vcc9-supply = <&vcc_sys>;
|
|
|
2f12b3e |
+ vcc10-supply = <&vcc_sys>;
|
|
|
2f12b3e |
+ vcc11-supply = <&vcc_sys>;
|
|
|
2f12b3e |
+ vcc12-supply = <&vcc3v3_sys>;
|
|
|
2f12b3e |
+ vddio-supply = <&vcc_1v8>;
|
|
|
2f12b3e |
+
|
|
|
2f12b3e |
+ regulators {
|
|
|
2f12b3e |
+ vdd_center: DCDC_REG1 {
|
|
|
2f12b3e |
+ regulator-name = "vdd_center";
|
|
|
2f12b3e |
+ regulator-min-microvolt = <750000>;
|
|
|
2f12b3e |
+ regulator-max-microvolt = <1350000>;
|
|
|
2f12b3e |
+ regulator-always-on;
|
|
|
2f12b3e |
+ regulator-boot-on;
|
|
|
2f12b3e |
+ regulator-state-mem {
|
|
|
2f12b3e |
+ regulator-off-in-suspend;
|
|
|
2f12b3e |
+ };
|
|
|
2f12b3e |
+ };
|
|
|
2f12b3e |
+
|
|
|
2f12b3e |
+ vdd_cpu_l: DCDC_REG2 {
|
|
|
2f12b3e |
+ regulator-name = "vdd_cpu_l";
|
|
|
2f12b3e |
+ regulator-min-microvolt = <750000>;
|
|
|
2f12b3e |
+ regulator-max-microvolt = <1350000>;
|
|
|
2f12b3e |
+ regulator-always-on;
|
|
|
2f12b3e |
+ regulator-boot-on;
|
|
|
2f12b3e |
+ regulator-state-mem {
|
|
|
2f12b3e |
+ regulator-off-in-suspend;
|
|
|
2f12b3e |
+ };
|
|
|
2f12b3e |
+ };
|
|
|
2f12b3e |
+
|
|
|
2f12b3e |
+ vcc_ddr: DCDC_REG3 {
|
|
|
2f12b3e |
+ regulator-name = "vcc_ddr";
|
|
|
2f12b3e |
+ regulator-always-on;
|
|
|
2f12b3e |
+ regulator-boot-on;
|
|
|
2f12b3e |
+ regulator-state-mem {
|
|
|
2f12b3e |
+ regulator-on-in-suspend;
|
|
|
2f12b3e |
+ };
|
|
|
2f12b3e |
+ };
|
|
|
2f12b3e |
+
|
|
|
2f12b3e |
+ vcc_1v8: DCDC_REG4 {
|
|
|
2f12b3e |
+ regulator-name = "vcc_1v8";
|
|
|
2f12b3e |
+ regulator-min-microvolt = <1800000>;
|
|
|
2f12b3e |
+ regulator-max-microvolt = <1800000>;
|
|
|
2f12b3e |
+ regulator-always-on;
|
|
|
2f12b3e |
+ regulator-boot-on;
|
|
|
2f12b3e |
+ regulator-state-mem {
|
|
|
2f12b3e |
+ regulator-on-in-suspend;
|
|
|
2f12b3e |
+ regulator-suspend-microvolt = <1800000>;
|
|
|
2f12b3e |
+ };
|
|
|
2f12b3e |
+ };
|
|
|
2f12b3e |
+
|
|
|
2f12b3e |
+ vcc1v8_dvp: LDO_REG1 {
|
|
|
2f12b3e |
+ regulator-name = "vcc1v8_dvp";
|
|
|
2f12b3e |
+ regulator-min-microvolt = <1800000>;
|
|
|
2f12b3e |
+ regulator-max-microvolt = <1800000>;
|
|
|
2f12b3e |
+ regulator-always-on;
|
|
|
2f12b3e |
+ regulator-boot-on;
|
|
|
2f12b3e |
+ regulator-state-mem {
|
|
|
2f12b3e |
+ regulator-on-in-suspend;
|
|
|
2f12b3e |
+ regulator-suspend-microvolt = <1800000>;
|
|
|
2f12b3e |
+ };
|
|
|
2f12b3e |
+ };
|
|
|
2f12b3e |
+
|
|
|
2f12b3e |
+ vcca1v8_hdmi: LDO_REG2 {
|
|
|
2f12b3e |
+ regulator-name = "vcca1v8_hdmi";
|
|
|
2f12b3e |
+ regulator-min-microvolt = <1800000>;
|
|
|
2f12b3e |
+ regulator-max-microvolt = <1800000>;
|
|
|
2f12b3e |
+ regulator-always-on;
|
|
|
2f12b3e |
+ regulator-boot-on;
|
|
|
2f12b3e |
+ regulator-state-mem {
|
|
|
2f12b3e |
+ regulator-on-in-suspend;
|
|
|
2f12b3e |
+ regulator-suspend-microvolt = <1800000>;
|
|
|
2f12b3e |
+ };
|
|
|
2f12b3e |
+ };
|
|
|
2f12b3e |
+
|
|
|
2f12b3e |
+ vcca_1v8: LDO_REG3 {
|
|
|
2f12b3e |
+ regulator-name = "vcca_1v8";
|
|
|
2f12b3e |
+ regulator-min-microvolt = <1800000>;
|
|
|
2f12b3e |
+ regulator-max-microvolt = <1800000>;
|
|
|
2f12b3e |
+ regulator-always-on;
|
|
|
2f12b3e |
+ regulator-boot-on;
|
|
|
2f12b3e |
+ regulator-state-mem {
|
|
|
2f12b3e |
+ regulator-on-in-suspend;
|
|
|
2f12b3e |
+ regulator-suspend-microvolt = <1800000>;
|
|
|
2f12b3e |
+ };
|
|
|
2f12b3e |
+ };
|
|
|
2f12b3e |
+
|
|
|
2f12b3e |
+ vcc_sd: LDO_REG4 {
|
|
|
2f12b3e |
+ regulator-name = "vcc_sd";
|
|
|
2f12b3e |
+ regulator-min-microvolt = <1800000>;
|
|
|
2f12b3e |
+ regulator-max-microvolt = <3300000>;
|
|
|
2f12b3e |
+ regulator-always-on;
|
|
|
2f12b3e |
+ regulator-boot-on;
|
|
|
2f12b3e |
+ regulator-state-mem {
|
|
|
2f12b3e |
+ regulator-on-in-suspend;
|
|
|
2f12b3e |
+ regulator-suspend-microvolt = <3300000>;
|
|
|
2f12b3e |
+ };
|
|
|
2f12b3e |
+ };
|
|
|
2f12b3e |
+
|
|
|
2f12b3e |
+ vcc3v0_sd: LDO_REG5 {
|
|
|
2f12b3e |
+ regulator-name = "vcc3v0_sd";
|
|
|
2f12b3e |
+ regulator-min-microvolt = <3000000>;
|
|
|
2f12b3e |
+ regulator-max-microvolt = <3000000>;
|
|
|
2f12b3e |
+ regulator-always-on;
|
|
|
2f12b3e |
+ regulator-boot-on;
|
|
|
2f12b3e |
+ regulator-state-mem {
|
|
|
2f12b3e |
+ regulator-on-in-suspend;
|
|
|
2f12b3e |
+ regulator-suspend-microvolt = <3000000>;
|
|
|
2f12b3e |
+ };
|
|
|
2f12b3e |
+ };
|
|
|
2f12b3e |
+
|
|
|
2f12b3e |
+ vcc_1v5: LDO_REG6 {
|
|
|
2f12b3e |
+ regulator-name = "vcc_1v5";
|
|
|
2f12b3e |
+ regulator-min-microvolt = <1500000>;
|
|
|
2f12b3e |
+ regulator-max-microvolt = <1500000>;
|
|
|
2f12b3e |
+ regulator-always-on;
|
|
|
2f12b3e |
+ regulator-boot-on;
|
|
|
2f12b3e |
+ regulator-state-mem {
|
|
|
2f12b3e |
+ regulator-on-in-suspend;
|
|
|
2f12b3e |
+ regulator-suspend-microvolt = <1500000>;
|
|
|
2f12b3e |
+ };
|
|
|
2f12b3e |
+ };
|
|
|
2f12b3e |
+
|
|
|
2f12b3e |
+ vcca0v9_hdmi: LDO_REG7 {
|
|
|
2f12b3e |
+ regulator-name = "vcca0v9_hdmi";
|
|
|
2f12b3e |
+ regulator-min-microvolt = <900000>;
|
|
|
2f12b3e |
+ regulator-max-microvolt = <900000>;
|
|
|
2f12b3e |
+ regulator-always-on;
|
|
|
2f12b3e |
+ regulator-boot-on;
|
|
|
2f12b3e |
+ regulator-state-mem {
|
|
|
2f12b3e |
+ regulator-on-in-suspend;
|
|
|
2f12b3e |
+ regulator-suspend-microvolt = <900000>;
|
|
|
2f12b3e |
+ };
|
|
|
2f12b3e |
+ };
|
|
|
2f12b3e |
+
|
|
|
2f12b3e |
+ vcc_3v0: LDO_REG8 {
|
|
|
2f12b3e |
+ regulator-name = "vcc_3v0";
|
|
|
2f12b3e |
+ regulator-min-microvolt = <3000000>;
|
|
|
2f12b3e |
+ regulator-max-microvolt = <3000000>;
|
|
|
2f12b3e |
+ regulator-always-on;
|
|
|
2f12b3e |
+ regulator-boot-on;
|
|
|
2f12b3e |
+ regulator-state-mem {
|
|
|
2f12b3e |
+ regulator-on-in-suspend;
|
|
|
2f12b3e |
+ regulator-suspend-microvolt = <3000000>;
|
|
|
2f12b3e |
+ };
|
|
|
2f12b3e |
+ };
|
|
|
2f12b3e |
+
|
|
|
2f12b3e |
+ vcc3v3_s3: SWITCH_REG1 {
|
|
|
2f12b3e |
+ regulator-name = "vcc3v3_s3";
|
|
|
2f12b3e |
+ regulator-always-on;
|
|
|
2f12b3e |
+ regulator-boot-on;
|
|
|
2f12b3e |
+ regulator-state-mem {
|
|
|
2f12b3e |
+ regulator-on-in-suspend;
|
|
|
2f12b3e |
+ };
|
|
|
2f12b3e |
+ };
|
|
|
2f12b3e |
+
|
|
|
2f12b3e |
+ vcc3v3_s0: SWITCH_REG2 {
|
|
|
2f12b3e |
+ regulator-name = "vcc3v3_s0";
|
|
|
2f12b3e |
+ regulator-always-on;
|
|
|
2f12b3e |
+ regulator-boot-on;
|
|
|
2f12b3e |
+ regulator-state-mem {
|
|
|
2f12b3e |
+ regulator-on-in-suspend;
|
|
|
2f12b3e |
+ };
|
|
|
2f12b3e |
+ };
|
|
|
2f12b3e |
+ };
|
|
|
2f12b3e |
+ };
|
|
|
2f12b3e |
+};
|
|
|
2f12b3e |
+
|
|
|
2f12b3e |
+&i2c1 {
|
|
|
2f12b3e |
+ status = "okay";
|
|
|
2f12b3e |
+};
|
|
|
2f12b3e |
+
|
|
|
2f12b3e |
+&i2c2 {
|
|
|
2f12b3e |
+ status = "okay";
|
|
|
2f12b3e |
+};
|
|
|
2f12b3e |
+
|
|
|
2f12b3e |
+&i2c3 {
|
|
|
2f12b3e |
+ status = "okay";
|
|
|
2f12b3e |
+};
|
|
|
2f12b3e |
+
|
|
|
2f12b3e |
+&i2c4 {
|
|
|
2f12b3e |
+ status = "okay";
|
|
|
2f12b3e |
+};
|
|
|
2f12b3e |
+
|
|
|
2f12b3e |
+&io_domains {
|
|
|
2f12b3e |
+ bt656-supply = <&vcc1v8_s0>; /* bt656_gpio2ab_ms */
|
|
|
2f12b3e |
+ audio-supply = <&vcc1v8_s0>; /* audio_gpio3d4a_ms */
|
|
|
2f12b3e |
+ sdmmc-supply = <&vcc_sd>; /* sdmmc_gpio4b_ms */
|
|
|
2f12b3e |
+ gpio1830-supply = <&vcc_3v0>; /* gpio1833_gpio4cd_ms */
|
|
|
2f12b3e |
+ status = "okay";
|
|
|
2f12b3e |
+};
|
|
|
2f12b3e |
+
|
|
|
2f12b3e |
+&pcie_phy {
|
|
|
2f12b3e |
+ status = "okay";
|
|
|
2f12b3e |
+};
|
|
|
2f12b3e |
+
|
|
|
2f12b3e |
+&pcie0 {
|
|
|
2f12b3e |
+ ep-gpios = <&gpio4 RK_PD4 GPIO_ACTIVE_HIGH>;
|
|
|
2f12b3e |
+ num-lanes = <4>;
|
|
|
2f12b3e |
+ pinctrl-names = "default";
|
|
|
2f12b3e |
+ pinctrl-0 = <&pcie_clkreqn_cpm>;
|
|
|
2f12b3e |
+ vpcie3v3-supply = <&vcc3v3_pcie>;
|
|
|
2f12b3e |
+ status = "okay";
|
|
|
2f12b3e |
+};
|
|
|
2f12b3e |
+
|
|
|
2f12b3e |
+&pmu_io_domains {
|
|
|
2f12b3e |
+ pmu1830-supply = <&vcc_1v8>;
|
|
|
2f12b3e |
+ status = "okay";
|
|
|
2f12b3e |
+};
|
|
|
2f12b3e |
+
|
|
|
2f12b3e |
+&pinctrl {
|
|
|
2f12b3e |
+ gmac {
|
|
|
2f12b3e |
+ rgmii_sleep_pins: rgmii-sleep-pins {
|
|
|
2f12b3e |
+ rockchip,pins =
|
|
|
2f12b3e |
+ <3 15 RK_FUNC_GPIO &pcfg_output_low>;
|
|
|
2f12b3e |
+ };
|
|
|
2f12b3e |
+ };
|
|
|
2f12b3e |
+
|
|
|
2f12b3e |
+ sdmmc {
|
|
|
2f12b3e |
+ sdmmc_bus1: sdmmc-bus1 {
|
|
|
2f12b3e |
+ rockchip,pins =
|
|
|
2f12b3e |
+ <4 8 RK_FUNC_1 &pcfg_pull_up_8ma>;
|
|
|
2f12b3e |
+ };
|
|
|
2f12b3e |
+
|
|
|
2f12b3e |
+ sdmmc_bus4: sdmmc-bus4 {
|
|
|
2f12b3e |
+ rockchip,pins =
|
|
|
2f12b3e |
+ <4 8 RK_FUNC_1 &pcfg_pull_up_8ma>,
|
|
|
2f12b3e |
+ <4 9 RK_FUNC_1 &pcfg_pull_up_8ma>,
|
|
|
2f12b3e |
+ <4 10 RK_FUNC_1 &pcfg_pull_up_8ma>,
|
|
|
2f12b3e |
+ <4 11 RK_FUNC_1 &pcfg_pull_up_8ma>;
|
|
|
2f12b3e |
+ };
|
|
|
2f12b3e |
+
|
|
|
2f12b3e |
+ sdmmc_clk: sdmmc-clk {
|
|
|
2f12b3e |
+ rockchip,pins =
|
|
|
2f12b3e |
+ <4 12 RK_FUNC_1 &pcfg_pull_none_18ma>;
|
|
|
2f12b3e |
+ };
|
|
|
2f12b3e |
+
|
|
|
2f12b3e |
+ sdmmc_cmd: sdmmc-cmd {
|
|
|
2f12b3e |
+ rockchip,pins =
|
|
|
2f12b3e |
+ <4 13 RK_FUNC_1 &pcfg_pull_up_8ma>;
|
|
|
2f12b3e |
+ };
|
|
|
2f12b3e |
+ };
|
|
|
2f12b3e |
+
|
|
|
2f12b3e |
+ pcie {
|
|
|
2f12b3e |
+ pcie_drv: pcie-drv {
|
|
|
2f12b3e |
+ rockchip,pins =
|
|
|
2f12b3e |
+ <1 24 RK_FUNC_GPIO &pcfg_pull_none>;
|
|
|
2f12b3e |
+ };
|
|
|
2f12b3e |
+ };
|
|
|
2f12b3e |
+
|
|
|
2f12b3e |
+ pmic {
|
|
|
2f12b3e |
+ pmic_int_l: pmic-int-l {
|
|
|
2f12b3e |
+ rockchip,pins =
|
|
|
2f12b3e |
+ <1 21 RK_FUNC_GPIO &pcfg_pull_up>;
|
|
|
2f12b3e |
+ };
|
|
|
2f12b3e |
+
|
|
|
2f12b3e |
+ vsel1_gpio: vsel1-gpio {
|
|
|
2f12b3e |
+ rockchip,pins =
|
|
|
2f12b3e |
+ <1 17 RK_FUNC_GPIO &pcfg_pull_down>;
|
|
|
2f12b3e |
+ };
|
|
|
2f12b3e |
+
|
|
|
2f12b3e |
+ vsel2_gpio: vsel2-gpio {
|
|
|
2f12b3e |
+ rockchip,pins =
|
|
|
2f12b3e |
+ <1 14 RK_FUNC_GPIO &pcfg_pull_down>;
|
|
|
2f12b3e |
+ };
|
|
|
2f12b3e |
+ };
|
|
|
2f12b3e |
+};
|
|
|
2f12b3e |
+
|
|
|
2f12b3e |
+&pwm2 {
|
|
|
2f12b3e |
+ status = "okay";
|
|
|
2f12b3e |
+};
|
|
|
2f12b3e |
+
|
|
|
2f12b3e |
+&pwm3 {
|
|
|
2f12b3e |
+ status = "okay";
|
|
|
2f12b3e |
+};
|
|
|
2f12b3e |
+
|
|
|
2f12b3e |
+&sdhci {
|
|
|
2f12b3e |
+ bus-width = <8>;
|
|
|
2f12b3e |
+ mmc-hs400-1_8v;
|
|
|
2f12b3e |
+ mmc-hs400-enhanced-strobe;
|
|
|
2f12b3e |
+ non-removable;
|
|
|
2f12b3e |
+ status = "okay";
|
|
|
2f12b3e |
+};
|
|
|
2f12b3e |
+
|
|
|
2f12b3e |
+&sdmmc {
|
|
|
2f12b3e |
+ bus-width = <4>;
|
|
|
2f12b3e |
+ cap-mmc-highspeed;
|
|
|
2f12b3e |
+ cap-sd-highspeed;
|
|
|
2f12b3e |
+ clock-frequency = <100000000>;
|
|
|
2f12b3e |
+ clock-freq-min-max = <100000 100000000>;
|
|
|
2f12b3e |
+ disable-wp;
|
|
|
2f12b3e |
+ sd-uhs-sdr104;
|
|
|
2f12b3e |
+ vqmmc-supply = <&vcc_sd>;
|
|
|
2f12b3e |
+ card-detect-delay = <800>;
|
|
|
2f12b3e |
+ pinctrl-names = "default";
|
|
|
2f12b3e |
+ pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_cd &sdmmc_bus4>;
|
|
|
2f12b3e |
+ status = "okay";
|
|
|
2f12b3e |
+};
|
|
|
2f12b3e |
+
|
|
|
2f12b3e |
+&uart0 {
|
|
|
2f12b3e |
+ pinctrl-names = "default";
|
|
|
2f12b3e |
+ pinctrl-0 = <&uart0_xfer &uart0_cts>;
|
|
|
2f12b3e |
+ status = "okay";
|
|
|
2f12b3e |
+};
|
|
|
2f12b3e |
+
|
|
|
2f12b3e |
+&uart2 {
|
|
|
2f12b3e |
+ status = "okay";
|
|
|
2f12b3e |
+};
|
|
|
2f12b3e |
+
|
|
|
2f12b3e |
+&vopb {
|
|
|
2f12b3e |
+ status = "okay";
|
|
|
2f12b3e |
+};
|
|
|
2f12b3e |
+
|
|
|
2f12b3e |
+&vopb_mmu {
|
|
|
2f12b3e |
+ status = "okay";
|
|
|
2f12b3e |
+};
|
|
|
2f12b3e |
+
|
|
|
2f12b3e |
+&vopl {
|
|
|
2f12b3e |
+ status = "okay";
|
|
|
2f12b3e |
+};
|
|
|
2f12b3e |
+
|
|
|
2f12b3e |
+&vopl_mmu {
|
|
|
2f12b3e |
+ status = "okay";
|
|
|
2f12b3e |
+};
|
|
|
2f12b3e |
--
|
|
|
2f12b3e |
2.19.0.rc1
|
|
|
2f12b3e |
|
|
|
2f12b3e |
From 2e3f4fb6f0a94b6cf56407536414b93bd3c45471 Mon Sep 17 00:00:00 2001
|
|
|
2f12b3e |
From: Enric Balletbo i Serra <enric.balletbo@collabora.com>
|
|
|
2f12b3e |
Date: Sat, 14 Jul 2018 14:09:22 -0300
|
|
|
2f12b3e |
Subject: [PATCH 2/4] arm64: dts: rockchip: add USB 2.0 and 3.0 support on
|
|
|
2f12b3e |
Ficus board
|
|
|
2f12b3e |
|
|
|
2f12b3e |
The board exposes two types A ports, one is USB 3.0, up to 5.0Gbps and
|
|
|
2f12b3e |
another one is USB 2.0 up to 480Mbps. Enable the USB PHYs and the USB
|
|
|
2f12b3e |
controllers to enable theses devices.
|
|
|
2f12b3e |
|
|
|
2f12b3e |
Signed-off-by: Enric Balletbo i Serra <enric.balletbo@collabora.com>
|
|
|
2f12b3e |
Signed-off-by: Ezequiel Garcia <ezequiel@collabora.com>
|
|
|
2f12b3e |
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
|
|
|
2f12b3e |
---
|
|
|
2f12b3e |
arch/arm64/boot/dts/rockchip/rk3399-ficus.dts | 88 +++++++++++++++++++
|
|
|
2f12b3e |
1 file changed, 88 insertions(+)
|
|
|
2f12b3e |
|
|
|
2f12b3e |
diff --git a/arch/arm64/boot/dts/rockchip/rk3399-ficus.dts b/arch/arm64/boot/dts/rockchip/rk3399-ficus.dts
|
|
|
2f12b3e |
index 0d14183dd4a9..890b9e13cfe8 100644
|
|
|
2f12b3e |
--- a/arch/arm64/boot/dts/rockchip/rk3399-ficus.dts
|
|
|
2f12b3e |
+++ b/arch/arm64/boot/dts/rockchip/rk3399-ficus.dts
|
|
|
2f12b3e |
@@ -61,6 +61,19 @@
|
|
|
2f12b3e |
vin-supply = <&vcc3v3_sys>;
|
|
|
2f12b3e |
};
|
|
|
2f12b3e |
|
|
|
2f12b3e |
+ vcc5v0_host: vcc5v0-host-regulator {
|
|
|
2f12b3e |
+ compatible = "regulator-fixed";
|
|
|
2f12b3e |
+ enable-active-high;
|
|
|
2f12b3e |
+ gpio = <&gpio4 27 GPIO_ACTIVE_HIGH>;
|
|
|
2f12b3e |
+ pinctrl-names = "default";
|
|
|
2f12b3e |
+ pinctrl-0 = <&host_vbus_drv>;
|
|
|
2f12b3e |
+ regulator-name = "vcc5v0_host";
|
|
|
2f12b3e |
+ regulator-min-microvolt = <5000000>;
|
|
|
2f12b3e |
+ regulator-max-microvolt = <5000000>;
|
|
|
2f12b3e |
+ regulator-always-on;
|
|
|
2f12b3e |
+ vin-supply = <&vcc_sys>;
|
|
|
2f12b3e |
+ };
|
|
|
2f12b3e |
+
|
|
|
2f12b3e |
vdd_log: vdd-log {
|
|
|
2f12b3e |
compatible = "pwm-regulator";
|
|
|
2f12b3e |
pwms = <&pwm2 0 25000 0>;
|
|
|
2f12b3e |
@@ -454,6 +467,13 @@
|
|
|
2f12b3e |
<1 14 RK_FUNC_GPIO &pcfg_pull_down>;
|
|
|
2f12b3e |
};
|
|
|
2f12b3e |
};
|
|
|
2f12b3e |
+
|
|
|
2f12b3e |
+ usb2 {
|
|
|
2f12b3e |
+ host_vbus_drv: host-vbus-drv {
|
|
|
2f12b3e |
+ rockchip,pins =
|
|
|
2f12b3e |
+ <4 27 RK_FUNC_GPIO &pcfg_pull_none>;
|
|
|
2f12b3e |
+ };
|
|
|
2f12b3e |
+ };
|
|
|
2f12b3e |
};
|
|
|
2f12b3e |
|
|
|
2f12b3e |
&pwm2 {
|
|
|
2f12b3e |
@@ -487,6 +507,40 @@
|
|
|
2f12b3e |
status = "okay";
|
|
|
2f12b3e |
};
|
|
|
2f12b3e |
|
|
|
2f12b3e |
+&tcphy0 {
|
|
|
2f12b3e |
+ status = "okay";
|
|
|
2f12b3e |
+};
|
|
|
2f12b3e |
+
|
|
|
2f12b3e |
+&tcphy1 {
|
|
|
2f12b3e |
+ status = "okay";
|
|
|
2f12b3e |
+};
|
|
|
2f12b3e |
+
|
|
|
2f12b3e |
+&u2phy0 {
|
|
|
2f12b3e |
+ status = "okay";
|
|
|
2f12b3e |
+};
|
|
|
2f12b3e |
+
|
|
|
2f12b3e |
+&u2phy1 {
|
|
|
2f12b3e |
+ status = "okay";
|
|
|
2f12b3e |
+};
|
|
|
2f12b3e |
+
|
|
|
2f12b3e |
+&u2phy0_host {
|
|
|
2f12b3e |
+ phy-supply = <&vcc5v0_host>;
|
|
|
2f12b3e |
+ status = "okay";
|
|
|
2f12b3e |
+};
|
|
|
2f12b3e |
+
|
|
|
2f12b3e |
+&u2phy1_host {
|
|
|
2f12b3e |
+ phy-supply = <&vcc5v0_host>;
|
|
|
2f12b3e |
+ status = "okay";
|
|
|
2f12b3e |
+};
|
|
|
2f12b3e |
+
|
|
|
2f12b3e |
+&u2phy0_otg {
|
|
|
2f12b3e |
+ status = "okay";
|
|
|
2f12b3e |
+};
|
|
|
2f12b3e |
+
|
|
|
2f12b3e |
+&u2phy1_otg {
|
|
|
2f12b3e |
+ status = "okay";
|
|
|
2f12b3e |
+};
|
|
|
2f12b3e |
+
|
|
|
2f12b3e |
&uart0 {
|
|
|
2f12b3e |
pinctrl-names = "default";
|
|
|
2f12b3e |
pinctrl-0 = <&uart0_xfer &uart0_cts>;
|
|
|
2f12b3e |
@@ -497,6 +551,40 @@
|
|
|
2f12b3e |
status = "okay";
|
|
|
2f12b3e |
};
|
|
|
2f12b3e |
|
|
|
2f12b3e |
+&usb_host0_ehci {
|
|
|
2f12b3e |
+ status = "okay";
|
|
|
2f12b3e |
+};
|
|
|
2f12b3e |
+
|
|
|
2f12b3e |
+&usb_host0_ohci {
|
|
|
2f12b3e |
+ status = "okay";
|
|
|
2f12b3e |
+};
|
|
|
2f12b3e |
+
|
|
|
2f12b3e |
+&usb_host1_ehci {
|
|
|
2f12b3e |
+ status = "okay";
|
|
|
2f12b3e |
+};
|
|
|
2f12b3e |
+
|
|
|
2f12b3e |
+&usb_host1_ohci {
|
|
|
2f12b3e |
+ status = "okay";
|
|
|
2f12b3e |
+};
|
|
|
2f12b3e |
+
|
|
|
2f12b3e |
+&usbdrd3_0 {
|
|
|
2f12b3e |
+ status = "okay";
|
|
|
2f12b3e |
+};
|
|
|
2f12b3e |
+
|
|
|
2f12b3e |
+&usbdrd_dwc3_0 {
|
|
|
2f12b3e |
+ status = "okay";
|
|
|
2f12b3e |
+ dr_mode = "host";
|
|
|
2f12b3e |
+};
|
|
|
2f12b3e |
+
|
|
|
2f12b3e |
+&usbdrd3_1 {
|
|
|
2f12b3e |
+ status = "okay";
|
|
|
2f12b3e |
+};
|
|
|
2f12b3e |
+
|
|
|
2f12b3e |
+&usbdrd_dwc3_1 {
|
|
|
2f12b3e |
+ status = "okay";
|
|
|
2f12b3e |
+ dr_mode = "host";
|
|
|
2f12b3e |
+};
|
|
|
2f12b3e |
+
|
|
|
2f12b3e |
&vopb {
|
|
|
2f12b3e |
status = "okay";
|
|
|
2f12b3e |
};
|
|
|
2f12b3e |
--
|
|
|
2f12b3e |
2.19.0.rc1
|
|
|
2f12b3e |
|
|
|
2f12b3e |
From d875193399378e17911829b9df9d27fd4a1ba195 Mon Sep 17 00:00:00 2001
|
|
|
2f12b3e |
From: Enric Balletbo i Serra <enric.balletbo@collabora.com>
|
|
|
2f12b3e |
Date: Sat, 14 Jul 2018 14:09:22 -0300
|
|
|
2f12b3e |
Subject: [PATCH 3/4] arm64: dts: rockchip: add voltage properties for
|
|
|
2f12b3e |
vcc3v3_pcie on rk3399 ficus
|
|
|
2f12b3e |
|
|
|
2f12b3e |
The vcc3v3_pcie regulator supplies 3.3V so add voltage properties
|
|
|
2f12b3e |
for it.
|
|
|
2f12b3e |
|
|
|
2f12b3e |
Signed-off-by: Enric Balletbo i Serra <enric.balletbo@collabora.com>
|
|
|
2f12b3e |
Signed-off-by: Ezequiel Garcia <ezequiel@collabora.com>
|
|
|
2f12b3e |
[split off from original patch]
|
|
|
2f12b3e |
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
|
|
|
2f12b3e |
---
|
|
|
2f12b3e |
arch/arm64/boot/dts/rockchip/rk3399-ficus.dts | 2 ++
|
|
|
2f12b3e |
1 file changed, 2 insertions(+)
|
|
|
2f12b3e |
|
|
|
2f12b3e |
diff --git a/arch/arm64/boot/dts/rockchip/rk3399-ficus.dts b/arch/arm64/boot/dts/rockchip/rk3399-ficus.dts
|
|
|
2f12b3e |
index 890b9e13cfe8..6295483b701f 100644
|
|
|
2f12b3e |
--- a/arch/arm64/boot/dts/rockchip/rk3399-ficus.dts
|
|
|
2f12b3e |
+++ b/arch/arm64/boot/dts/rockchip/rk3399-ficus.dts
|
|
|
2f12b3e |
@@ -58,6 +58,8 @@
|
|
|
2f12b3e |
pinctrl-0 = <&pcie_drv>;
|
|
|
2f12b3e |
regulator-boot-on;
|
|
|
2f12b3e |
regulator-name = "vcc3v3_pcie";
|
|
|
2f12b3e |
+ regulator-min-microvolt = <3300000>;
|
|
|
2f12b3e |
+ regulator-max-microvolt = <3300000>;
|
|
|
2f12b3e |
vin-supply = <&vcc3v3_sys>;
|
|
|
2f12b3e |
};
|
|
|
2f12b3e |
|
|
|
2f12b3e |
--
|
|
|
2f12b3e |
2.19.0.rc1
|
|
|
2f12b3e |
|
|
|
2f12b3e |
From 416756dbf32ff2394b320fa88c09e9461496fc4c Mon Sep 17 00:00:00 2001
|
|
|
2f12b3e |
From: Heiko Stuebner <heiko@sntech.de>
|
|
|
2f12b3e |
Date: Mon, 16 Jul 2018 18:52:44 +0200
|
|
|
2f12b3e |
Subject: [PATCH 4/4] arm64: dts: rockchip: drop out-of-tree properties from
|
|
|
2f12b3e |
rk3399-ficus regulator
|
|
|
2f12b3e |
|
|
|
2f12b3e |
The pwm-regulator for vdd_log uses additional unreviewed properties in the
|
|
|
2f12b3e |
vendor kernel, which slipped in with the devicetree.
|
|
|
2f12b3e |
As written, they are unreviewed and unused in all mainline implementations
|
|
|
2f12b3e |
so drop them again.
|
|
|
2f12b3e |
|
|
|
2f12b3e |
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
|
|
|
2f12b3e |
---
|
|
|
2f12b3e |
arch/arm64/boot/dts/rockchip/rk3399-ficus.dts | 5 -----
|
|
|
2f12b3e |
1 file changed, 5 deletions(-)
|
|
|
2f12b3e |
|
|
|
2f12b3e |
diff --git a/arch/arm64/boot/dts/rockchip/rk3399-ficus.dts b/arch/arm64/boot/dts/rockchip/rk3399-ficus.dts
|
|
|
2f12b3e |
index 6295483b701f..8978d924eb83 100644
|
|
|
2f12b3e |
--- a/arch/arm64/boot/dts/rockchip/rk3399-ficus.dts
|
|
|
2f12b3e |
+++ b/arch/arm64/boot/dts/rockchip/rk3399-ficus.dts
|
|
|
2f12b3e |
@@ -84,11 +84,6 @@
|
|
|
2f12b3e |
regulator-max-microvolt = <1400000>;
|
|
|
2f12b3e |
regulator-always-on;
|
|
|
2f12b3e |
regulator-boot-on;
|
|
|
2f12b3e |
-
|
|
|
2f12b3e |
- /* for rockchip boot on */
|
|
|
2f12b3e |
- rockchip,pwm_id= <2>;
|
|
|
2f12b3e |
- rockchip,pwm_voltage = <900000>;
|
|
|
2f12b3e |
-
|
|
|
2f12b3e |
vin-supply = <&vcc_sys>;
|
|
|
2f12b3e |
};
|
|
|
2f12b3e |
|
|
|
2f12b3e |
--
|
|
|
2f12b3e |
2.19.0.rc1
|
|
|
2f12b3e |
|