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From daae9f66b29a04a94708b1b5a9b61e3ee14df031 Mon Sep 17 00:00:00 2001
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From: Jernej Skrabec <jernej.skrabec@siol.net>
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Date: Mon, 10 Feb 2020 18:06:52 +0100
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Subject: [PATCH 1/2] dt-bindings: interconnect: sunxi: Add A64 MBUS compatible
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A64 contains MBUS controller. Add a compatible for it.
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Acked-by: Rob Herring <robh@kernel.org>
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Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net>
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Signed-off-by: Maxime Ripard <maxime@cerno.tech>
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---
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.../devicetree/bindings/arm/sunxi/allwinner,sun4i-a10-mbus.yaml | 1 +
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1 file changed, 1 insertion(+)
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diff --git a/Documentation/devicetree/bindings/arm/sunxi/allwinner,sun4i-a10-mbus.yaml b/Documentation/devicetree/bindings/arm/sunxi/allwinner,sun4i-a10-mbus.yaml
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index 9370e64992dd..aa0738b4d534 100644
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--- a/Documentation/devicetree/bindings/arm/sunxi/allwinner,sun4i-a10-mbus.yaml
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+++ b/Documentation/devicetree/bindings/arm/sunxi/allwinner,sun4i-a10-mbus.yaml
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@@ -30,6 +30,7 @@ properties:
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enum:
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- allwinner,sun5i-a13-mbus
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- allwinner,sun8i-h3-mbus
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+ - allwinner,sun50i-a64-mbus
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reg:
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maxItems: 1
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--
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2.24.1
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From 410bb2be7e1f1d329c238e2d6d06b6c25dcee404 Mon Sep 17 00:00:00 2001
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From: Jernej Skrabec <jernej.skrabec@siol.net>
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Date: Mon, 10 Feb 2020 18:06:54 +0100
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Subject: [PATCH 2/2] arm64: dts: allwinner: a64: Add MBUS controller node
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A64 contains MBUS, which is the bus used by DMA devices to access
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system memory.
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MBUS controller is responsible for arbitration between channels based
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on set priority and can do some other things as well, like report
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bandwidth used. It also maps RAM region to different address than CPU.
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Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net>
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Signed-off-by: Maxime Ripard <maxime@cerno.tech>
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---
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arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi | 8 ++++++++
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1 file changed, 8 insertions(+)
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diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
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index 862b47dc9dc9..251c91724de1 100644
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--- a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
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+++ b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
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@@ -1061,6 +1061,14 @@ pwm: pwm@1c21400 {
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status = "disabled";
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};
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+ mbus: dram-controller@1c62000 {
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+ compatible = "allwinner,sun50i-a64-mbus";
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+ reg = <0x01c62000 0x1000>;
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+ clocks = <&ccu 112>;
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+ dma-ranges = <0x00000000 0x40000000 0xc0000000>;
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+ #interconnect-cells = <1>;
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+ };
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+
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csi: csi@1cb0000 {
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compatible = "allwinner,sun50i-a64-csi";
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reg = <0x01cb0000 0x1000>;
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--
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2.24.1
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