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Tue, 11 Feb 2020 05:48:52 -0800 (PST)
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From: Alifer Moraes <alifer.wsdm@gmail.com>
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To: robh+dt@kernel.org
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fab1332 |
Subject: [PATCH] arm64: dts: imx8mq-phanbell: Add support for ethernet
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fab1332 |
Date: Tue, 11 Feb 2020 10:48:28 -0300
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Message-Id: <20200211134828.138-1-alifer.wsdm@gmail.com>
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pts rule name description
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---- ----------------------
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--------------------------------------------------
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Cc: mark.rutland@arm.com, devicetree@vger.kernel.org, festevam@gmail.com,
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fab1332 |
s.hauer@pengutronix.de, linux-kernel@vger.kernel.org,
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fab1332 |
Alifer Moraes <alifer.wsdm@gmail.com>, marco.franchi@nxp.com,
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shawnguo@kernel.org, linux-arm-kernel@lists.infradead.org
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linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org
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fab1332 |
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fab1332 |
Add support for ethernet on Google's i.MX 8MQ Phanbell
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fab1332 |
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fab1332 |
Signed-off-by: Alifer Moraes <alifer.wsdm@gmail.com>
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fab1332 |
---
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fab1332 |
.../boot/dts/freescale/imx8mq-phanbell.dts | 41 +++++++++++++++++++
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1 file changed, 41 insertions(+)
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fab1332 |
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diff --git a/arch/arm64/boot/dts/freescale/imx8mq-phanbell.dts b/arch/arm64/boot/dts/freescale/imx8mq-phanbell.dts
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fab1332 |
index 3f2a489a4ad8..16ed13c44a47 100644
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fab1332 |
--- a/arch/arm64/boot/dts/freescale/imx8mq-phanbell.dts
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fab1332 |
+++ b/arch/arm64/boot/dts/freescale/imx8mq-phanbell.dts
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fab1332 |
@@ -201,6 +201,27 @@
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};
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};
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+&fec1 {
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+ pinctrl-names = "default";
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+ pinctrl-0 = <&pinctrl_fec1>;
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+ phy-mode = "rgmii-id";
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+ phy-reset-gpios = <&gpio1 9 GPIO_ACTIVE_LOW>;
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+ phy-reset-duration = <10>;
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+ phy-reset-post-delay = <30>;
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+ phy-handle = <ðphy0>;
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+ fsl,magic-packet;
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+ status = "okay";
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+
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+ mdio {
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+ #address-cells = <1>;
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+ #size-cells = <0>;
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+ ethphy0: ethernet-phy@0 {
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fab1332 |
+ compatible = "ethernet-phy-ieee802.3-c22";
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+ reg = <0>;
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+ };
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+ };
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+};
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+
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&uart1 {
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fab1332 |
pinctrl-names = "default";
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fab1332 |
pinctrl-0 = <&pinctrl_uart1>;
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fab1332 |
@@ -254,6 +275,26 @@
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};
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fab1332 |
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&iomuxc {
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fab1332 |
+ pinctrl_fec1: fec1grp {
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fab1332 |
+ fsl,pins = <
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fab1332 |
+ MX8MQ_IOMUXC_ENET_MDC_ENET1_MDC 0x3
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fab1332 |
+ MX8MQ_IOMUXC_ENET_MDIO_ENET1_MDIO 0x23
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fab1332 |
+ MX8MQ_IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x1f
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fab1332 |
+ MX8MQ_IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x1f
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fab1332 |
+ MX8MQ_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x1f
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fab1332 |
+ MX8MQ_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x1f
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fab1332 |
+ MX8MQ_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x91
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fab1332 |
+ MX8MQ_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x91
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fab1332 |
+ MX8MQ_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x91
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fab1332 |
+ MX8MQ_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x91
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fab1332 |
+ MX8MQ_IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x1f
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fab1332 |
+ MX8MQ_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x91
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fab1332 |
+ MX8MQ_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x91
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fab1332 |
+ MX8MQ_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x1f
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fab1332 |
+ MX8MQ_IOMUXC_GPIO1_IO09_GPIO1_IO9 0x19
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fab1332 |
+ >;
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fab1332 |
+ };
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fab1332 |
+
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fab1332 |
pinctrl_i2c1: i2c1grp {
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fab1332 |
fsl,pins = <
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fab1332 |
MX8MQ_IOMUXC_I2C1_SCL_I2C1_SCL 0x4000007f
|