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X-Patchwork-Id: 10858639
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From: Thierry Reding <thierry.reding@gmail.com>
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To: Thierry Reding <thierry.reding@gmail.com>
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Subject: [PATCH] arm64: tegra: Add NVIDIA Jetson Nano Developer Kit support
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Date: Tue, 19 Mar 2019 00:23:13 +0100
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Cc: linux-tegra@vger.kernel.org, linux-arm-kernel@lists.infradead.org,
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From: Thierry Reding <treding@nvidia.com>
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The Jetson Nano Developer Kit is a Tegra X1 based development board. It
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is similar to Jetson TX1 but it is not pin compatible. It features 4 GB
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of LPDDR4, an SPI NOR flash for early boot firmware and an SD card slot
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used for storage.
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HDMI 2.0 or DP 1.2 are available for display, four USB ports (3 USB 2.0
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and 1 USB 3.0) can be used to attach a variety of peripherals and a PCI
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Ethernet controller provides onboard network connectivity.
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A 40-pin header on the board can be used to extend the capabilities and
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exposed interfaces of the Jetson Nano.
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Signed-off-by: Thierry Reding <treding@nvidia.com>
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---
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This patch, along with some related patches can be found in the p3450
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branch in the following repository:
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	https://github.com/thierryreding/linux
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 arch/arm64/boot/dts/nvidia/Makefile           |    1 +
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 .../boot/dts/nvidia/tegra210-p3450-0000.dts   | 1911 +++++++++++++++++
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 2 files changed, 1912 insertions(+)
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 create mode 100644 arch/arm64/boot/dts/nvidia/tegra210-p3450-0000.dts
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diff --git a/arch/arm64/boot/dts/nvidia/Makefile b/arch/arm64/boot/dts/nvidia/Makefile
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index 6b8ab5568481..bcd018c3162b 100644
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--- a/arch/arm64/boot/dts/nvidia/Makefile
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+++ b/arch/arm64/boot/dts/nvidia/Makefile
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@@ -3,6 +3,7 @@ dtb-$(CONFIG_ARCH_TEGRA_132_SOC) += tegra132-norrin.dtb
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 dtb-$(CONFIG_ARCH_TEGRA_210_SOC) += tegra210-p2371-0000.dtb
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 dtb-$(CONFIG_ARCH_TEGRA_210_SOC) += tegra210-p2371-2180.dtb
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 dtb-$(CONFIG_ARCH_TEGRA_210_SOC) += tegra210-p2571.dtb
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+dtb-$(CONFIG_ARCH_TEGRA_210_SOC) += tegra210-p3450-0000.dtb
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 dtb-$(CONFIG_ARCH_TEGRA_210_SOC) += tegra210-smaug.dtb
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 dtb-$(CONFIG_ARCH_TEGRA_210_SOC) += tegra210-p2894-0050-a08.dtb
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 dtb-$(CONFIG_ARCH_TEGRA_186_SOC) += tegra186-p2771-0000.dtb
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diff --git a/arch/arm64/boot/dts/nvidia/tegra210-p3450-0000.dts b/arch/arm64/boot/dts/nvidia/tegra210-p3450-0000.dts
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new file mode 100644
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index 000000000000..b1d8a49ca8c4
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--- /dev/null
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+++ b/arch/arm64/boot/dts/nvidia/tegra210-p3450-0000.dts
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@@ -0,0 +1,1911 @@
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+// SPDX-License-Identifier: GPL-2.0
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+/dts-v1/;
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+
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+#include <dt-bindings/input/gpio-keys.h>
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+#include <dt-bindings/input/linux-event-codes.h>
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+#include <dt-bindings/mfd/max77620.h>
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+
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+#include "tegra210.dtsi"
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+
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+/ {
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+	model = "NVIDIA Jetson Nano Developer Kit";
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+	compatible = "nvidia,p3450-0000", "nvidia,tegra210";
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+
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+	aliases {
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+		ethernet = "/pcie@1003000/pci@2,0/ethernet@0,0";
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+		rtc0 = "/i2c@7000d000/pmic@3c";
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+		rtc1 = "/rtc@7000e000";
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+		serial0 = &uart;;
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+	};
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+
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+	chosen {
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+		stdout-path = "serial0:115200n8";
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+	};
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+
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+	memory {
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+		device_type = "memory";
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+		reg = <0x0 0x80000000 0x1 0x0>;
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+	};
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+
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+	pcie@1003000 {
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+		status = "okay";
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+
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+		hvddio-pex-supply = <&vdd_1v8>;
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+		dvddio-pex-supply = <&vdd_pex_1v05>;
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+		vddio-pex-ctl-supply = <&vdd_1v8>;
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+
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+		pci@1,0 {
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+			phys = <&{/padctl@7009f000/pads/pcie/lanes/pcie-1}>,
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+			       <&{/padctl@7009f000/pads/pcie/lanes/pcie-2}>,
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+			       <&{/padctl@7009f000/pads/pcie/lanes/pcie-3}>,
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+			       <&{/padctl@7009f000/pads/pcie/lanes/pcie-4}>;
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+			phy-names = "pcie-0", "pcie-1", "pcie-2", "pcie-3";
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+			nvidia,num-lanes = <4>;
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+			status = "okay";
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+		};
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+
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+		pci@2,0 {
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+			phys = <&{/padctl@7009f000/pads/pcie/lanes/pcie-0}>;
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+			phy-names = "pcie-0";
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+			status = "okay";
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+
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+			ethernet@0,0 {
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+				reg = <0x000000 0 0 0 0>;
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+				mac-address = [ 00 00 00 00 00 00 ];
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+			};
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+		};
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+	};
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+
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+	host1x@50000000 {
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+		dpaux@54040000 {
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+			status = "okay";
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+		};
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+
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+		sor@54580000 {
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+			status = "okay";
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+
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+			avdd-io-supply = <&avdd_1v05>;
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+			vdd-pll-supply = <&vdd_1v8>;
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+			hdmi-supply = <&vdd_hdmi>;
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+
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+			nvidia,ddc-i2c-bus = <&hdmi_ddc>;
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+			nvidia,hpd-gpio = <&gpio TEGRA_GPIO(CC, 1)
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+					   GPIO_ACTIVE_LOW>;
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+			nvidia,xbar-cfg = <0 1 2 3 4>;
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+		};
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+	};
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+
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+	gpu@57000000 {
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+		vdd-supply = <&vdd_gpu>;
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+		status = "okay";
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+	};
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+
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+	pinmux: pinmux@700008d4 {
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+		pinctrl-names = "boot";
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+		pinctrl-0 = <&state_boot>;
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+
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+		state_boot: pinmux {
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+			pex_l0_rst_n_pa0 {
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+				nvidia,pins = "pex_l0_rst_n_pa0";
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+				nvidia,function = "pe0";
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+				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
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+				nvidia,tristate = <TEGRA_PIN_DISABLE>;
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+				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
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+				nvidia,open-drain = <TEGRA_PIN_DISABLE>;
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+				nvidia,io-hv = <TEGRA_PIN_DISABLE>;
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+			};
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+			pex_l0_clkreq_n_pa1 {
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+				nvidia,pins = "pex_l0_clkreq_n_pa1";
Jeremy Cline 36b34bf
+				nvidia,function = "pe0";
Jeremy Cline 36b34bf
+				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
Jeremy Cline 36b34bf
+				nvidia,tristate = <TEGRA_PIN_DISABLE>;
Jeremy Cline 36b34bf
+				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
Jeremy Cline 36b34bf
+				nvidia,open-drain = <TEGRA_PIN_DISABLE>;
Jeremy Cline 36b34bf
+				nvidia,io-hv = <TEGRA_PIN_DISABLE>;
Jeremy Cline 36b34bf
+			};
Jeremy Cline 36b34bf
+			pex_wake_n_pa2 {
Jeremy Cline 36b34bf
+				nvidia,pins = "pex_wake_n_pa2";
Jeremy Cline 36b34bf
+				nvidia,function = "pe";
Jeremy Cline 36b34bf
+				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
Jeremy Cline 36b34bf
+				nvidia,tristate = <TEGRA_PIN_DISABLE>;
Jeremy Cline 36b34bf
+				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
Jeremy Cline 36b34bf
+				nvidia,open-drain = <TEGRA_PIN_DISABLE>;
Jeremy Cline 36b34bf
+				nvidia,io-hv = <TEGRA_PIN_DISABLE>;
Jeremy Cline 36b34bf
+			};
Jeremy Cline 36b34bf
+			pex_l1_rst_n_pa3 {
Jeremy Cline 36b34bf
+				nvidia,pins = "pex_l1_rst_n_pa3";
Jeremy Cline 36b34bf
+				nvidia,function = "pe1";
Jeremy Cline 36b34bf
+				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
Jeremy Cline 36b34bf
+				nvidia,tristate = <TEGRA_PIN_DISABLE>;
Jeremy Cline 36b34bf
+				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
Jeremy Cline 36b34bf
+				nvidia,open-drain = <TEGRA_PIN_DISABLE>;
Jeremy Cline 36b34bf
+				nvidia,io-hv = <TEGRA_PIN_DISABLE>;
Jeremy Cline 36b34bf
+			};
Jeremy Cline 36b34bf
+			pex_l1_clkreq_n_pa4 {
Jeremy Cline 36b34bf
+				nvidia,pins = "pex_l1_clkreq_n_pa4";
Jeremy Cline 36b34bf
+				nvidia,function = "pe1";
Jeremy Cline 36b34bf
+				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
Jeremy Cline 36b34bf
+				nvidia,tristate = <TEGRA_PIN_DISABLE>;
Jeremy Cline 36b34bf
+				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
Jeremy Cline 36b34bf
+				nvidia,open-drain = <TEGRA_PIN_DISABLE>;
Jeremy Cline 36b34bf
+				nvidia,io-hv = <TEGRA_PIN_DISABLE>;
Jeremy Cline 36b34bf
+			};
Jeremy Cline 36b34bf
+			sata_led_active_pa5 {
Jeremy Cline 36b34bf
+				nvidia,pins = "sata_led_active_pa5";
Jeremy Cline 36b34bf
+				nvidia,pull = <TEGRA_PIN_PULL_UP>;
Jeremy Cline 36b34bf
+				nvidia,tristate = <TEGRA_PIN_DISABLE>;
Jeremy Cline 36b34bf
+				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
Jeremy Cline 36b34bf
+				nvidia,open-drain = <TEGRA_PIN_DISABLE>;
Jeremy Cline 36b34bf
+			};
Jeremy Cline 36b34bf
+			pa6 {
Jeremy Cline 36b34bf
+				nvidia,pins = "pa6";
Jeremy Cline 36b34bf
+				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
Jeremy Cline 36b34bf
+				nvidia,tristate = <TEGRA_PIN_DISABLE>;
Jeremy Cline 36b34bf
+				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
Jeremy Cline 36b34bf
+				nvidia,open-drain = <TEGRA_PIN_DISABLE>;
Jeremy Cline 36b34bf
+			};
Jeremy Cline 36b34bf
+			dap1_fs_pb0 {
Jeremy Cline 36b34bf
+				nvidia,pins = "dap1_fs_pb0";
Jeremy Cline 36b34bf
+				nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
Jeremy Cline 36b34bf
+				nvidia,tristate = <TEGRA_PIN_DISABLE>;
Jeremy Cline 36b34bf
+				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
Jeremy Cline 36b34bf
+				nvidia,open-drain = <TEGRA_PIN_DISABLE>;
Jeremy Cline 36b34bf
+			};
Jeremy Cline 36b34bf
+			dap1_din_pb1 {
Jeremy Cline 36b34bf
+				nvidia,pins = "dap1_din_pb1";
Jeremy Cline 36b34bf
+				nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
Jeremy Cline 36b34bf
+				nvidia,tristate = <TEGRA_PIN_DISABLE>;
Jeremy Cline 36b34bf
+				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
Jeremy Cline 36b34bf
+				nvidia,open-drain = <TEGRA_PIN_DISABLE>;
Jeremy Cline 36b34bf
+			};
Jeremy Cline 36b34bf
+			dap1_dout_pb2 {
Jeremy Cline 36b34bf
+				nvidia,pins = "dap1_dout_pb2";
Jeremy Cline 36b34bf
+				nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
Jeremy Cline 36b34bf
+				nvidia,tristate = <TEGRA_PIN_DISABLE>;
Jeremy Cline 36b34bf
+				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
Jeremy Cline 36b34bf
+				nvidia,open-drain = <TEGRA_PIN_DISABLE>;
Jeremy Cline 36b34bf
+			};
Jeremy Cline 36b34bf
+			dap1_sclk_pb3 {
Jeremy Cline 36b34bf
+				nvidia,pins = "dap1_sclk_pb3";
Jeremy Cline 36b34bf
+				nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
Jeremy Cline 36b34bf
+				nvidia,tristate = <TEGRA_PIN_DISABLE>;
Jeremy Cline 36b34bf
+				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
Jeremy Cline 36b34bf
+				nvidia,open-drain = <TEGRA_PIN_DISABLE>;
Jeremy Cline 36b34bf
+			};
Jeremy Cline 36b34bf
+			spi2_mosi_pb4 {
Jeremy Cline 36b34bf
+				nvidia,pins = "spi2_mosi_pb4";
Jeremy Cline 36b34bf
+				nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
Jeremy Cline 36b34bf
+				nvidia,tristate = <TEGRA_PIN_DISABLE>;
Jeremy Cline 36b34bf
+				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
Jeremy Cline 36b34bf
+				nvidia,open-drain = <TEGRA_PIN_DISABLE>;
Jeremy Cline 36b34bf
+			};
Jeremy Cline 36b34bf
+			spi2_miso_pb5 {
Jeremy Cline 36b34bf
+				nvidia,pins = "spi2_miso_pb5";
Jeremy Cline 36b34bf
+				nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
Jeremy Cline 36b34bf
+				nvidia,tristate = <TEGRA_PIN_DISABLE>;
Jeremy Cline 36b34bf
+				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
Jeremy Cline 36b34bf
+				nvidia,open-drain = <TEGRA_PIN_DISABLE>;
Jeremy Cline 36b34bf
+			};
Jeremy Cline 36b34bf
+			spi2_sck_pb6 {
Jeremy Cline 36b34bf
+				nvidia,pins = "spi2_sck_pb6";
Jeremy Cline 36b34bf
+				nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
Jeremy Cline 36b34bf
+				nvidia,tristate = <TEGRA_PIN_DISABLE>;
Jeremy Cline 36b34bf
+				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
Jeremy Cline 36b34bf
+				nvidia,open-drain = <TEGRA_PIN_DISABLE>;
Jeremy Cline 36b34bf
+			};
Jeremy Cline 36b34bf
+			spi2_cs0_pb7 {
Jeremy Cline 36b34bf
+				nvidia,pins = "spi2_cs0_pb7";
Jeremy Cline 36b34bf
+				nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
Jeremy Cline 36b34bf
+				nvidia,tristate = <TEGRA_PIN_DISABLE>;
Jeremy Cline 36b34bf
+				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
Jeremy Cline 36b34bf
+				nvidia,open-drain = <TEGRA_PIN_DISABLE>;
Jeremy Cline 36b34bf
+			};
Jeremy Cline 36b34bf
+			spi1_mosi_pc0 {
Jeremy Cline 36b34bf
+				nvidia,pins = "spi1_mosi_pc0";
Jeremy Cline 36b34bf
+				nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
Jeremy Cline 36b34bf
+				nvidia,tristate = <TEGRA_PIN_DISABLE>;
Jeremy Cline 36b34bf
+				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
Jeremy Cline 36b34bf
+				nvidia,open-drain = <TEGRA_PIN_DISABLE>;
Jeremy Cline 36b34bf
+			};
Jeremy Cline 36b34bf
+			spi1_miso_pc1 {
Jeremy Cline 36b34bf
+				nvidia,pins = "spi1_miso_pc1";
Jeremy Cline 36b34bf
+				nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
Jeremy Cline 36b34bf
+				nvidia,tristate = <TEGRA_PIN_DISABLE>;
Jeremy Cline 36b34bf
+				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
Jeremy Cline 36b34bf
+				nvidia,open-drain = <TEGRA_PIN_DISABLE>;
Jeremy Cline 36b34bf
+			};
Jeremy Cline 36b34bf
+			spi1_sck_pc2 {
Jeremy Cline 36b34bf
+				nvidia,pins = "spi1_sck_pc2";
Jeremy Cline 36b34bf
+				nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
Jeremy Cline 36b34bf
+				nvidia,tristate = <TEGRA_PIN_DISABLE>;
Jeremy Cline 36b34bf
+				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
Jeremy Cline 36b34bf
+				nvidia,open-drain = <TEGRA_PIN_DISABLE>;
Jeremy Cline 36b34bf
+			};
Jeremy Cline 36b34bf
+			spi1_cs0_pc3 {
Jeremy Cline 36b34bf
+				nvidia,pins = "spi1_cs0_pc3";
Jeremy Cline 36b34bf
+				nvidia,pull = <TEGRA_PIN_PULL_UP>;
Jeremy Cline 36b34bf
+				nvidia,tristate = <TEGRA_PIN_DISABLE>;
Jeremy Cline 36b34bf
+				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
Jeremy Cline 36b34bf
+				nvidia,open-drain = <TEGRA_PIN_DISABLE>;
Jeremy Cline 36b34bf
+			};
Jeremy Cline 36b34bf
+			spi1_cs1_pc4 {
Jeremy Cline 36b34bf
+				nvidia,pins = "spi1_cs1_pc4";
Jeremy Cline 36b34bf
+				nvidia,pull = <TEGRA_PIN_PULL_UP>;
Jeremy Cline 36b34bf
+				nvidia,tristate = <TEGRA_PIN_DISABLE>;
Jeremy Cline 36b34bf
+				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
Jeremy Cline 36b34bf
+				nvidia,open-drain = <TEGRA_PIN_DISABLE>;
Jeremy Cline 36b34bf
+			};
Jeremy Cline 36b34bf
+			spi4_sck_pc5 {
Jeremy Cline 36b34bf
+				nvidia,pins = "spi4_sck_pc5";
Jeremy Cline 36b34bf
+				nvidia,function = "rsvd1";
Jeremy Cline 36b34bf
+				nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
Jeremy Cline 36b34bf
+				nvidia,tristate = <TEGRA_PIN_ENABLE>;
Jeremy Cline 36b34bf
+				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
Jeremy Cline 36b34bf
+				nvidia,open-drain = <TEGRA_PIN_DISABLE>;
Jeremy Cline 36b34bf
+			};
Jeremy Cline 36b34bf
+			spi4_cs0_pc6 {
Jeremy Cline 36b34bf
+				nvidia,pins = "spi4_cs0_pc6";
Jeremy Cline 36b34bf
+				nvidia,function = "rsvd1";
Jeremy Cline 36b34bf
+				nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
Jeremy Cline 36b34bf
+				nvidia,tristate = <TEGRA_PIN_ENABLE>;
Jeremy Cline 36b34bf
+				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
Jeremy Cline 36b34bf
+				nvidia,open-drain = <TEGRA_PIN_DISABLE>;
Jeremy Cline 36b34bf
+			};
Jeremy Cline 36b34bf
+			spi4_mosi_pc7 {
Jeremy Cline 36b34bf
+				nvidia,pins = "spi4_mosi_pc7";
Jeremy Cline 36b34bf
+				nvidia,function = "rsvd1";
Jeremy Cline 36b34bf
+				nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
Jeremy Cline 36b34bf
+				nvidia,tristate = <TEGRA_PIN_ENABLE>;
Jeremy Cline 36b34bf
+				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
Jeremy Cline 36b34bf
+				nvidia,open-drain = <TEGRA_PIN_DISABLE>;
Jeremy Cline 36b34bf
+			};
Jeremy Cline 36b34bf
+			spi4_miso_pd0 {
Jeremy Cline 36b34bf
+				nvidia,pins = "spi4_miso_pd0";
Jeremy Cline 36b34bf
+				nvidia,function = "rsvd1";
Jeremy Cline 36b34bf
+				nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
Jeremy Cline 36b34bf
+				nvidia,tristate = <TEGRA_PIN_ENABLE>;
Jeremy Cline 36b34bf
+				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
Jeremy Cline 36b34bf
+				nvidia,open-drain = <TEGRA_PIN_DISABLE>;
Jeremy Cline 36b34bf
+			};
Jeremy Cline 36b34bf
+			uart3_tx_pd1 {
Jeremy Cline 36b34bf
+				nvidia,pins = "uart3_tx_pd1";
Jeremy Cline 36b34bf
+				nvidia,function = "uartc";
Jeremy Cline 36b34bf
+				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
Jeremy Cline 36b34bf
+				nvidia,tristate = <TEGRA_PIN_DISABLE>;
Jeremy Cline 36b34bf
+				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
Jeremy Cline 36b34bf
+				nvidia,open-drain = <TEGRA_PIN_DISABLE>;
Jeremy Cline 36b34bf
+			};
Jeremy Cline 36b34bf
+			uart3_rx_pd2 {
Jeremy Cline 36b34bf
+				nvidia,pins = "uart3_rx_pd2";
Jeremy Cline 36b34bf
+				nvidia,function = "uartc";
Jeremy Cline 36b34bf
+				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
Jeremy Cline 36b34bf
+				nvidia,tristate = <TEGRA_PIN_DISABLE>;
Jeremy Cline 36b34bf
+				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
Jeremy Cline 36b34bf
+				nvidia,open-drain = <TEGRA_PIN_DISABLE>;
Jeremy Cline 36b34bf
+			};
Jeremy Cline 36b34bf
+			uart3_rts_pd3 {
Jeremy Cline 36b34bf
+				nvidia,pins = "uart3_rts_pd3";
Jeremy Cline 36b34bf
+				nvidia,function = "uartc";
Jeremy Cline 36b34bf
+				nvidia,pull = <TEGRA_PIN_PULL_UP>;
Jeremy Cline 36b34bf
+				nvidia,tristate = <TEGRA_PIN_DISABLE>;
Jeremy Cline 36b34bf
+				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
Jeremy Cline 36b34bf
+				nvidia,open-drain = <TEGRA_PIN_DISABLE>;
Jeremy Cline 36b34bf
+			};
Jeremy Cline 36b34bf
+			uart3_cts_pd4 {
Jeremy Cline 36b34bf
+				nvidia,pins = "uart3_cts_pd4";
Jeremy Cline 36b34bf
+				nvidia,function = "uartc";
Jeremy Cline 36b34bf
+				nvidia,pull = <TEGRA_PIN_PULL_UP>;
Jeremy Cline 36b34bf
+				nvidia,tristate = <TEGRA_PIN_DISABLE>;
Jeremy Cline 36b34bf
+				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
Jeremy Cline 36b34bf
+				nvidia,open-drain = <TEGRA_PIN_DISABLE>;
Jeremy Cline 36b34bf
+			};
Jeremy Cline 36b34bf
+			dmic1_clk_pe0 {
Jeremy Cline 36b34bf
+				nvidia,pins = "dmic1_clk_pe0";
Jeremy Cline 36b34bf
+				nvidia,function = "i2s3";
Jeremy Cline 36b34bf
+				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
Jeremy Cline 36b34bf
+				nvidia,tristate = <TEGRA_PIN_DISABLE>;
Jeremy Cline 36b34bf
+				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
Jeremy Cline 36b34bf
+				nvidia,open-drain = <TEGRA_PIN_DISABLE>;
Jeremy Cline 36b34bf
+			};
Jeremy Cline 36b34bf
+			dmic1_dat_pe1 {
Jeremy Cline 36b34bf
+				nvidia,pins = "dmic1_dat_pe1";
Jeremy Cline 36b34bf
+				nvidia,function = "i2s3";
Jeremy Cline 36b34bf
+				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
Jeremy Cline 36b34bf
+				nvidia,tristate = <TEGRA_PIN_DISABLE>;
Jeremy Cline 36b34bf
+				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
Jeremy Cline 36b34bf
+				nvidia,open-drain = <TEGRA_PIN_DISABLE>;
Jeremy Cline 36b34bf
+			};
Jeremy Cline 36b34bf
+			dmic2_clk_pe2 {
Jeremy Cline 36b34bf
+				nvidia,pins = "dmic2_clk_pe2";
Jeremy Cline 36b34bf
+				nvidia,function = "i2s3";
Jeremy Cline 36b34bf
+				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
Jeremy Cline 36b34bf
+				nvidia,tristate = <TEGRA_PIN_DISABLE>;
Jeremy Cline 36b34bf
+				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
Jeremy Cline 36b34bf
+				nvidia,open-drain = <TEGRA_PIN_DISABLE>;
Jeremy Cline 36b34bf
+			};
Jeremy Cline 36b34bf
+			dmic2_dat_pe3 {
Jeremy Cline 36b34bf
+				nvidia,pins = "dmic2_dat_pe3";
Jeremy Cline 36b34bf
+				nvidia,function = "i2s3";
Jeremy Cline 36b34bf
+				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
Jeremy Cline 36b34bf
+				nvidia,tristate = <TEGRA_PIN_DISABLE>;
Jeremy Cline 36b34bf
+				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
Jeremy Cline 36b34bf
+				nvidia,open-drain = <TEGRA_PIN_DISABLE>;
Jeremy Cline 36b34bf
+			};
Jeremy Cline 36b34bf
+			dmic3_clk_pe4 {
Jeremy Cline 36b34bf
+				nvidia,pins = "dmic3_clk_pe4";
Jeremy Cline 36b34bf
+				nvidia,function = "rsvd2";
Jeremy Cline 36b34bf
+				nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
Jeremy Cline 36b34bf
+				nvidia,tristate = <TEGRA_PIN_ENABLE>;
Jeremy Cline 36b34bf
+				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
Jeremy Cline 36b34bf
+				nvidia,open-drain = <TEGRA_PIN_DISABLE>;
Jeremy Cline 36b34bf
+			};
Jeremy Cline 36b34bf
+			dmic3_dat_pe5 {
Jeremy Cline 36b34bf
+				nvidia,pins = "dmic3_dat_pe5";
Jeremy Cline 36b34bf
+				nvidia,function = "rsvd2";
Jeremy Cline 36b34bf
+				nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
Jeremy Cline 36b34bf
+				nvidia,tristate = <TEGRA_PIN_ENABLE>;
Jeremy Cline 36b34bf
+				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
Jeremy Cline 36b34bf
+				nvidia,open-drain = <TEGRA_PIN_DISABLE>;
Jeremy Cline 36b34bf
+			};
Jeremy Cline 36b34bf
+			pe6 {
Jeremy Cline 36b34bf
+				nvidia,pins = "pe6";
Jeremy Cline 36b34bf
+				nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
Jeremy Cline 36b34bf
+				nvidia,tristate = <TEGRA_PIN_DISABLE>;
Jeremy Cline 36b34bf
+				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
Jeremy Cline 36b34bf
+				nvidia,open-drain = <TEGRA_PIN_DISABLE>;
Jeremy Cline 36b34bf
+			};
Jeremy Cline 36b34bf
+			pe7 {
Jeremy Cline 36b34bf
+				nvidia,pins = "pe7";
Jeremy Cline 36b34bf
+				nvidia,function = "pwm3";
Jeremy Cline 36b34bf
+				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
Jeremy Cline 36b34bf
+				nvidia,tristate = <TEGRA_PIN_DISABLE>;
Jeremy Cline 36b34bf
+				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
Jeremy Cline 36b34bf
+				nvidia,open-drain = <TEGRA_PIN_DISABLE>;
Jeremy Cline 36b34bf
+			};
Jeremy Cline 36b34bf
+			gen3_i2c_scl_pf0 {
Jeremy Cline 36b34bf
+				nvidia,pins = "gen3_i2c_scl_pf0";
Jeremy Cline 36b34bf
+				nvidia,function = "i2c3";
Jeremy Cline 36b34bf
+				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
Jeremy Cline 36b34bf
+				nvidia,tristate = <TEGRA_PIN_DISABLE>;
Jeremy Cline 36b34bf
+				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
Jeremy Cline 36b34bf
+				nvidia,open-drain = <TEGRA_PIN_DISABLE>;
Jeremy Cline 36b34bf
+				nvidia,io-hv = <TEGRA_PIN_DISABLE>;
Jeremy Cline 36b34bf
+			};
Jeremy Cline 36b34bf
+			gen3_i2c_sda_pf1 {
Jeremy Cline 36b34bf
+				nvidia,pins = "gen3_i2c_sda_pf1";
Jeremy Cline 36b34bf
+				nvidia,function = "i2c3";
Jeremy Cline 36b34bf
+				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
Jeremy Cline 36b34bf
+				nvidia,tristate = <TEGRA_PIN_DISABLE>;
Jeremy Cline 36b34bf
+				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
Jeremy Cline 36b34bf
+				nvidia,open-drain = <TEGRA_PIN_DISABLE>;
Jeremy Cline 36b34bf
+				nvidia,io-hv = <TEGRA_PIN_DISABLE>;
Jeremy Cline 36b34bf
+			};
Jeremy Cline 36b34bf
+			uart2_tx_pg0 {
Jeremy Cline 36b34bf
+				nvidia,pins = "uart2_tx_pg0";
Jeremy Cline 36b34bf
+				nvidia,function = "uartb";
Jeremy Cline 36b34bf
+				nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
Jeremy Cline 36b34bf
+				nvidia,tristate = <TEGRA_PIN_DISABLE>;
Jeremy Cline 36b34bf
+				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
Jeremy Cline 36b34bf
+				nvidia,open-drain = <TEGRA_PIN_DISABLE>;
Jeremy Cline 36b34bf
+			};
Jeremy Cline 36b34bf
+			uart2_rx_pg1 {
Jeremy Cline 36b34bf
+				nvidia,pins = "uart2_rx_pg1";
Jeremy Cline 36b34bf
+				nvidia,function = "uartb";
Jeremy Cline 36b34bf
+				nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
Jeremy Cline 36b34bf
+				nvidia,tristate = <TEGRA_PIN_DISABLE>;
Jeremy Cline 36b34bf
+				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
Jeremy Cline 36b34bf
+				nvidia,open-drain = <TEGRA_PIN_DISABLE>;
Jeremy Cline 36b34bf
+			};
Jeremy Cline 36b34bf
+			uart2_rts_pg2 {
Jeremy Cline 36b34bf
+				nvidia,pins = "uart2_rts_pg2";
Jeremy Cline 36b34bf
+				nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
Jeremy Cline 36b34bf
+				nvidia,tristate = <TEGRA_PIN_DISABLE>;
Jeremy Cline 36b34bf
+				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
Jeremy Cline 36b34bf
+				nvidia,open-drain = <TEGRA_PIN_DISABLE>;
Jeremy Cline 36b34bf
+			};
Jeremy Cline 36b34bf
+			uart2_cts_pg3 {
Jeremy Cline 36b34bf
+				nvidia,pins = "uart2_cts_pg3";
Jeremy Cline 36b34bf
+				nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
Jeremy Cline 36b34bf
+				nvidia,tristate = <TEGRA_PIN_DISABLE>;
Jeremy Cline 36b34bf
+				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
Jeremy Cline 36b34bf
+				nvidia,open-drain = <TEGRA_PIN_DISABLE>;
Jeremy Cline 36b34bf
+			};
Jeremy Cline 36b34bf
+			wifi_en_ph0 {
Jeremy Cline 36b34bf
+				nvidia,pins = "wifi_en_ph0";
Jeremy Cline 36b34bf
+				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
Jeremy Cline 36b34bf
+				nvidia,tristate = <TEGRA_PIN_DISABLE>;
Jeremy Cline 36b34bf
+				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
Jeremy Cline 36b34bf
+				nvidia,open-drain = <TEGRA_PIN_DISABLE>;
Jeremy Cline 36b34bf
+			};
Jeremy Cline 36b34bf
+			wifi_rst_ph1 {
Jeremy Cline 36b34bf
+				nvidia,pins = "wifi_rst_ph1";
Jeremy Cline 36b34bf
+				nvidia,function = "rsvd0";
Jeremy Cline 36b34bf
+				nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
Jeremy Cline 36b34bf
+				nvidia,tristate = <TEGRA_PIN_ENABLE>;
Jeremy Cline 36b34bf
+				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
Jeremy Cline 36b34bf
+				nvidia,open-drain = <TEGRA_PIN_DISABLE>;
Jeremy Cline 36b34bf
+			};
Jeremy Cline 36b34bf
+			wifi_wake_ap_ph2 {
Jeremy Cline 36b34bf
+				nvidia,pins = "wifi_wake_ap_ph2";
Jeremy Cline 36b34bf
+				nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
Jeremy Cline 36b34bf
+				nvidia,tristate = <TEGRA_PIN_DISABLE>;
Jeremy Cline 36b34bf
+				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
Jeremy Cline 36b34bf
+				nvidia,open-drain = <TEGRA_PIN_DISABLE>;
Jeremy Cline 36b34bf
+			};
Jeremy Cline 36b34bf
+			ap_wake_bt_ph3 {
Jeremy Cline 36b34bf
+				nvidia,pins = "ap_wake_bt_ph3";
Jeremy Cline 36b34bf
+				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
Jeremy Cline 36b34bf
+				nvidia,tristate = <TEGRA_PIN_DISABLE>;
Jeremy Cline 36b34bf
+				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
Jeremy Cline 36b34bf
+				nvidia,open-drain = <TEGRA_PIN_DISABLE>;
Jeremy Cline 36b34bf
+			};
Jeremy Cline 36b34bf
+			bt_rst_ph4 {
Jeremy Cline 36b34bf
+				nvidia,pins = "bt_rst_ph4";
Jeremy Cline 36b34bf
+				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
Jeremy Cline 36b34bf
+				nvidia,tristate = <TEGRA_PIN_DISABLE>;
Jeremy Cline 36b34bf
+				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
Jeremy Cline 36b34bf
+				nvidia,open-drain = <TEGRA_PIN_DISABLE>;
Jeremy Cline 36b34bf
+			};
Jeremy Cline 36b34bf
+			bt_wake_ap_ph5 {
Jeremy Cline 36b34bf
+				nvidia,pins = "bt_wake_ap_ph5";
Jeremy Cline 36b34bf
+				nvidia,pull = <TEGRA_PIN_PULL_UP>;
Jeremy Cline 36b34bf
+				nvidia,tristate = <TEGRA_PIN_DISABLE>;
Jeremy Cline 36b34bf
+				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
Jeremy Cline 36b34bf
+				nvidia,open-drain = <TEGRA_PIN_DISABLE>;
Jeremy Cline 36b34bf
+			};
Jeremy Cline 36b34bf
+			ph6 {
Jeremy Cline 36b34bf
+				nvidia,pins = "ph6";
Jeremy Cline 36b34bf
+				nvidia,pull = <TEGRA_PIN_PULL_UP>;
Jeremy Cline 36b34bf
+				nvidia,tristate = <TEGRA_PIN_DISABLE>;
Jeremy Cline 36b34bf
+				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
Jeremy Cline 36b34bf
+				nvidia,open-drain = <TEGRA_PIN_DISABLE>;
Jeremy Cline 36b34bf
+			};
Jeremy Cline 36b34bf
+			ap_wake_nfc_ph7 {
Jeremy Cline 36b34bf
+				nvidia,pins = "ap_wake_nfc_ph7";
Jeremy Cline 36b34bf
+				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
Jeremy Cline 36b34bf
+				nvidia,tristate = <TEGRA_PIN_DISABLE>;
Jeremy Cline 36b34bf
+				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
Jeremy Cline 36b34bf
+				nvidia,open-drain = <TEGRA_PIN_DISABLE>;
Jeremy Cline 36b34bf
+			};
Jeremy Cline 36b34bf
+			nfc_en_pi0 {
Jeremy Cline 36b34bf
+				nvidia,pins = "nfc_en_pi0";
Jeremy Cline 36b34bf
+				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
Jeremy Cline 36b34bf
+				nvidia,tristate = <TEGRA_PIN_DISABLE>;
Jeremy Cline 36b34bf
+				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
Jeremy Cline 36b34bf
+				nvidia,open-drain = <TEGRA_PIN_DISABLE>;
Jeremy Cline 36b34bf
+			};
Jeremy Cline 36b34bf
+			nfc_int_pi1 {
Jeremy Cline 36b34bf
+				nvidia,pins = "nfc_int_pi1";
Jeremy Cline 36b34bf
+				nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
Jeremy Cline 36b34bf
+				nvidia,tristate = <TEGRA_PIN_DISABLE>;
Jeremy Cline 36b34bf
+				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
Jeremy Cline 36b34bf
+				nvidia,open-drain = <TEGRA_PIN_DISABLE>;
Jeremy Cline 36b34bf
+			};
Jeremy Cline 36b34bf
+			gps_en_pi2 {
Jeremy Cline 36b34bf
+				nvidia,pins = "gps_en_pi2";
Jeremy Cline 36b34bf
+				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
Jeremy Cline 36b34bf
+				nvidia,tristate = <TEGRA_PIN_DISABLE>;
Jeremy Cline 36b34bf
+				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
Jeremy Cline 36b34bf
+				nvidia,open-drain = <TEGRA_PIN_DISABLE>;
Jeremy Cline 36b34bf
+			};
Jeremy Cline 36b34bf
+			gps_rst_pi3 {
Jeremy Cline 36b34bf
+				nvidia,pins = "gps_rst_pi3";
Jeremy Cline 36b34bf
+				nvidia,function = "rsvd0";
Jeremy Cline 36b34bf
+				nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
Jeremy Cline 36b34bf
+				nvidia,tristate = <TEGRA_PIN_ENABLE>;
Jeremy Cline 36b34bf
+				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
Jeremy Cline 36b34bf
+				nvidia,open-drain = <TEGRA_PIN_DISABLE>;
Jeremy Cline 36b34bf
+			};
Jeremy Cline 36b34bf
+			uart4_tx_pi4 {
Jeremy Cline 36b34bf
+				nvidia,pins = "uart4_tx_pi4";
Jeremy Cline 36b34bf
+				nvidia,function = "uartd";
Jeremy Cline 36b34bf
+				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
Jeremy Cline 36b34bf
+				nvidia,tristate = <TEGRA_PIN_DISABLE>;
Jeremy Cline 36b34bf
+				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
Jeremy Cline 36b34bf
+				nvidia,open-drain = <TEGRA_PIN_DISABLE>;
Jeremy Cline 36b34bf
+			};
Jeremy Cline 36b34bf
+			uart4_rx_pi5 {
Jeremy Cline 36b34bf
+				nvidia,pins = "uart4_rx_pi5";
Jeremy Cline 36b34bf
+				nvidia,function = "uartd";
Jeremy Cline 36b34bf
+				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
Jeremy Cline 36b34bf
+				nvidia,tristate = <TEGRA_PIN_DISABLE>;
Jeremy Cline 36b34bf
+				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
Jeremy Cline 36b34bf
+				nvidia,open-drain = <TEGRA_PIN_DISABLE>;
Jeremy Cline 36b34bf
+			};
Jeremy Cline 36b34bf
+			uart4_rts_pi6 {
Jeremy Cline 36b34bf
+				nvidia,pins = "uart4_rts_pi6";
Jeremy Cline 36b34bf
+				nvidia,function = "uartd";
Jeremy Cline 36b34bf
+				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
Jeremy Cline 36b34bf
+				nvidia,tristate = <TEGRA_PIN_DISABLE>;
Jeremy Cline 36b34bf
+				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
Jeremy Cline 36b34bf
+				nvidia,open-drain = <TEGRA_PIN_DISABLE>;
Jeremy Cline 36b34bf
+			};
Jeremy Cline 36b34bf
+			uart4_cts_pi7 {
Jeremy Cline 36b34bf
+				nvidia,pins = "uart4_cts_pi7";
Jeremy Cline 36b34bf
+				nvidia,function = "uartd";
Jeremy Cline 36b34bf
+				nvidia,pull = <TEGRA_PIN_PULL_UP>;
Jeremy Cline 36b34bf
+				nvidia,tristate = <TEGRA_PIN_DISABLE>;
Jeremy Cline 36b34bf
+				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
Jeremy Cline 36b34bf
+				nvidia,open-drain = <TEGRA_PIN_DISABLE>;
Jeremy Cline 36b34bf
+			};
Jeremy Cline 36b34bf
+			gen1_i2c_sda_pj0 {
Jeremy Cline 36b34bf
+				nvidia,pins = "gen1_i2c_sda_pj0";
Jeremy Cline 36b34bf
+				nvidia,function = "i2c1";
Jeremy Cline 36b34bf
+				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
Jeremy Cline 36b34bf
+				nvidia,tristate = <TEGRA_PIN_DISABLE>;
Jeremy Cline 36b34bf
+				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
Jeremy Cline 36b34bf
+				nvidia,open-drain = <TEGRA_PIN_DISABLE>;
Jeremy Cline 36b34bf
+				nvidia,io-hv = <TEGRA_PIN_ENABLE>;
Jeremy Cline 36b34bf
+			};
Jeremy Cline 36b34bf
+			gen1_i2c_scl_pj1 {
Jeremy Cline 36b34bf
+				nvidia,pins = "gen1_i2c_scl_pj1";
Jeremy Cline 36b34bf
+				nvidia,function = "i2c1";
Jeremy Cline 36b34bf
+				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
Jeremy Cline 36b34bf
+				nvidia,tristate = <TEGRA_PIN_DISABLE>;
Jeremy Cline 36b34bf
+				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
Jeremy Cline 36b34bf
+				nvidia,open-drain = <TEGRA_PIN_DISABLE>;
Jeremy Cline 36b34bf
+				nvidia,io-hv = <TEGRA_PIN_ENABLE>;
Jeremy Cline 36b34bf
+			};
Jeremy Cline 36b34bf
+			gen2_i2c_scl_pj2 {
Jeremy Cline 36b34bf
+				nvidia,pins = "gen2_i2c_scl_pj2";
Jeremy Cline 36b34bf
+				nvidia,function = "i2c2";
Jeremy Cline 36b34bf
+				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
Jeremy Cline 36b34bf
+				nvidia,tristate = <TEGRA_PIN_DISABLE>;
Jeremy Cline 36b34bf
+				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
Jeremy Cline 36b34bf
+				nvidia,open-drain = <TEGRA_PIN_DISABLE>;
Jeremy Cline 36b34bf
+				nvidia,io-hv = <TEGRA_PIN_ENABLE>;
Jeremy Cline 36b34bf
+			};
Jeremy Cline 36b34bf
+			gen2_i2c_sda_pj3 {
Jeremy Cline 36b34bf
+				nvidia,pins = "gen2_i2c_sda_pj3";
Jeremy Cline 36b34bf
+				nvidia,function = "i2c2";
Jeremy Cline 36b34bf
+				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
Jeremy Cline 36b34bf
+				nvidia,tristate = <TEGRA_PIN_DISABLE>;
Jeremy Cline 36b34bf
+				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
Jeremy Cline 36b34bf
+				nvidia,open-drain = <TEGRA_PIN_DISABLE>;
Jeremy Cline 36b34bf
+				nvidia,io-hv = <TEGRA_PIN_ENABLE>;
Jeremy Cline 36b34bf
+			};
Jeremy Cline 36b34bf
+			dap4_fs_pj4 {
Jeremy Cline 36b34bf
+				nvidia,pins = "dap4_fs_pj4";
Jeremy Cline 36b34bf
+				nvidia,function = "rsvd1";
Jeremy Cline 36b34bf
+				nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
Jeremy Cline 36b34bf
+				nvidia,tristate = <TEGRA_PIN_ENABLE>;
Jeremy Cline 36b34bf
+				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
Jeremy Cline 36b34bf
+				nvidia,open-drain = <TEGRA_PIN_DISABLE>;
Jeremy Cline 36b34bf
+			};
Jeremy Cline 36b34bf
+			dap4_din_pj5 {
Jeremy Cline 36b34bf
+				nvidia,pins = "dap4_din_pj5";
Jeremy Cline 36b34bf
+				nvidia,function = "rsvd1";
Jeremy Cline 36b34bf
+				nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
Jeremy Cline 36b34bf
+				nvidia,tristate = <TEGRA_PIN_ENABLE>;
Jeremy Cline 36b34bf
+				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
Jeremy Cline 36b34bf
+				nvidia,open-drain = <TEGRA_PIN_DISABLE>;
Jeremy Cline 36b34bf
+			};
Jeremy Cline 36b34bf
+			dap4_dout_pj6 {
Jeremy Cline 36b34bf
+				nvidia,pins = "dap4_dout_pj6";
Jeremy Cline 36b34bf
+				nvidia,function = "rsvd1";
Jeremy Cline 36b34bf
+				nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
Jeremy Cline 36b34bf
+				nvidia,tristate = <TEGRA_PIN_ENABLE>;
Jeremy Cline 36b34bf
+				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
Jeremy Cline 36b34bf
+				nvidia,open-drain = <TEGRA_PIN_DISABLE>;
Jeremy Cline 36b34bf
+			};
Jeremy Cline 36b34bf
+			dap4_sclk_pj7 {
Jeremy Cline 36b34bf
+				nvidia,pins = "dap4_sclk_pj7";
Jeremy Cline 36b34bf
+				nvidia,function = "rsvd1";
Jeremy Cline 36b34bf
+				nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
Jeremy Cline 36b34bf
+				nvidia,tristate = <TEGRA_PIN_ENABLE>;
Jeremy Cline 36b34bf
+				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
Jeremy Cline 36b34bf
+				nvidia,open-drain = <TEGRA_PIN_DISABLE>;
Jeremy Cline 36b34bf
+			};
Jeremy Cline 36b34bf
+			pk0 {
Jeremy Cline 36b34bf
+				nvidia,pins = "pk0";
Jeremy Cline 36b34bf
+				nvidia,function = "rsvd2";
Jeremy Cline 36b34bf
+				nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
Jeremy Cline 36b34bf
+				nvidia,tristate = <TEGRA_PIN_ENABLE>;
Jeremy Cline 36b34bf
+				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
Jeremy Cline 36b34bf
+				nvidia,open-drain = <TEGRA_PIN_DISABLE>;
Jeremy Cline 36b34bf
+			};
Jeremy Cline 36b34bf
+			pk1 {
Jeremy Cline 36b34bf
+				nvidia,pins = "pk1";
Jeremy Cline 36b34bf
+				nvidia,function = "rsvd2";
Jeremy Cline 36b34bf
+				nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
Jeremy Cline 36b34bf
+				nvidia,tristate = <TEGRA_PIN_ENABLE>;
Jeremy Cline 36b34bf
+				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
Jeremy Cline 36b34bf
+				nvidia,open-drain = <TEGRA_PIN_DISABLE>;
Jeremy Cline 36b34bf
+			};
Jeremy Cline 36b34bf
+			pk2 {
Jeremy Cline 36b34bf
+				nvidia,pins = "pk2";
Jeremy Cline 36b34bf
+				nvidia,function = "rsvd2";
Jeremy Cline 36b34bf
+				nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
Jeremy Cline 36b34bf
+				nvidia,tristate = <TEGRA_PIN_ENABLE>;
Jeremy Cline 36b34bf
+				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
Jeremy Cline 36b34bf
+				nvidia,open-drain = <TEGRA_PIN_DISABLE>;
Jeremy Cline 36b34bf
+			};
Jeremy Cline 36b34bf
+			pk3 {
Jeremy Cline 36b34bf
+				nvidia,pins = "pk3";
Jeremy Cline 36b34bf
+				nvidia,function = "rsvd2";
Jeremy Cline 36b34bf
+				nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
Jeremy Cline 36b34bf
+				nvidia,tristate = <TEGRA_PIN_ENABLE>;
Jeremy Cline 36b34bf
+				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
Jeremy Cline 36b34bf
+				nvidia,open-drain = <TEGRA_PIN_DISABLE>;
Jeremy Cline 36b34bf
+			};
Jeremy Cline 36b34bf
+			pk4 {
Jeremy Cline 36b34bf
+				nvidia,pins = "pk4";
Jeremy Cline 36b34bf
+				nvidia,function = "rsvd1";
Jeremy Cline 36b34bf
+				nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
Jeremy Cline 36b34bf
+				nvidia,tristate = <TEGRA_PIN_ENABLE>;
Jeremy Cline 36b34bf
+				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
Jeremy Cline 36b34bf
+				nvidia,open-drain = <TEGRA_PIN_DISABLE>;
Jeremy Cline 36b34bf
+			};
Jeremy Cline 36b34bf
+			pk5 {
Jeremy Cline 36b34bf
+				nvidia,pins = "pk5";
Jeremy Cline 36b34bf
+				nvidia,function = "rsvd1";
Jeremy Cline 36b34bf
+				nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
Jeremy Cline 36b34bf
+				nvidia,tristate = <TEGRA_PIN_ENABLE>;
Jeremy Cline 36b34bf
+				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
Jeremy Cline 36b34bf
+				nvidia,open-drain = <TEGRA_PIN_DISABLE>;
Jeremy Cline 36b34bf
+			};
Jeremy Cline 36b34bf
+			pk6 {
Jeremy Cline 36b34bf
+				nvidia,pins = "pk6";
Jeremy Cline 36b34bf
+				nvidia,function = "rsvd1";
Jeremy Cline 36b34bf
+				nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
Jeremy Cline 36b34bf
+				nvidia,tristate = <TEGRA_PIN_ENABLE>;
Jeremy Cline 36b34bf
+				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
Jeremy Cline 36b34bf
+				nvidia,open-drain = <TEGRA_PIN_DISABLE>;
Jeremy Cline 36b34bf
+			};
Jeremy Cline 36b34bf
+			pk7 {
Jeremy Cline 36b34bf
+				nvidia,pins = "pk7";
Jeremy Cline 36b34bf
+				nvidia,function = "rsvd1";
Jeremy Cline 36b34bf
+				nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
Jeremy Cline 36b34bf
+				nvidia,tristate = <TEGRA_PIN_ENABLE>;
Jeremy Cline 36b34bf
+				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
Jeremy Cline 36b34bf
+				nvidia,open-drain = <TEGRA_PIN_DISABLE>;
Jeremy Cline 36b34bf
+			};
Jeremy Cline 36b34bf
+			pl0 {
Jeremy Cline 36b34bf
+				nvidia,pins = "pl0";
Jeremy Cline 36b34bf
+				nvidia,function = "rsvd0";
Jeremy Cline 36b34bf
+				nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
Jeremy Cline 36b34bf
+				nvidia,tristate = <TEGRA_PIN_ENABLE>;
Jeremy Cline 36b34bf
+				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
Jeremy Cline 36b34bf
+				nvidia,open-drain = <TEGRA_PIN_DISABLE>;
Jeremy Cline 36b34bf
+			};
Jeremy Cline 36b34bf
+			pl1 {
Jeremy Cline 36b34bf
+				nvidia,pins = "pl1";
Jeremy Cline 36b34bf
+				nvidia,function = "rsvd1";
Jeremy Cline 36b34bf
+				nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
Jeremy Cline 36b34bf
+				nvidia,tristate = <TEGRA_PIN_ENABLE>;
Jeremy Cline 36b34bf
+				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
Jeremy Cline 36b34bf
+				nvidia,open-drain = <TEGRA_PIN_DISABLE>;
Jeremy Cline 36b34bf
+			};
Jeremy Cline 36b34bf
+			sdmmc1_clk_pm0 {
Jeremy Cline 36b34bf
+				nvidia,pins = "sdmmc1_clk_pm0";
Jeremy Cline 36b34bf
+				nvidia,function = "sdmmc1";
Jeremy Cline 36b34bf
+				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
Jeremy Cline 36b34bf
+				nvidia,tristate = <TEGRA_PIN_DISABLE>;
Jeremy Cline 36b34bf
+				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
Jeremy Cline 36b34bf
+				nvidia,open-drain = <TEGRA_PIN_DISABLE>;
Jeremy Cline 36b34bf
+			};
Jeremy Cline 36b34bf
+			sdmmc1_cmd_pm1 {
Jeremy Cline 36b34bf
+				nvidia,pins = "sdmmc1_cmd_pm1";
Jeremy Cline 36b34bf
+				nvidia,function = "sdmmc1";
Jeremy Cline 36b34bf
+				nvidia,pull = <TEGRA_PIN_PULL_UP>;
Jeremy Cline 36b34bf
+				nvidia,tristate = <TEGRA_PIN_DISABLE>;
Jeremy Cline 36b34bf
+				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
Jeremy Cline 36b34bf
+				nvidia,open-drain = <TEGRA_PIN_DISABLE>;
Jeremy Cline 36b34bf
+			};
Jeremy Cline 36b34bf
+			sdmmc1_dat3_pm2 {
Jeremy Cline 36b34bf
+				nvidia,pins = "sdmmc1_dat3_pm2";
Jeremy Cline 36b34bf
+				nvidia,function = "sdmmc1";
Jeremy Cline 36b34bf
+				nvidia,pull = <TEGRA_PIN_PULL_UP>;
Jeremy Cline 36b34bf
+				nvidia,tristate = <TEGRA_PIN_DISABLE>;
Jeremy Cline 36b34bf
+				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
Jeremy Cline 36b34bf
+				nvidia,open-drain = <TEGRA_PIN_DISABLE>;
Jeremy Cline 36b34bf
+			};
Jeremy Cline 36b34bf
+			sdmmc1_dat2_pm3 {
Jeremy Cline 36b34bf
+				nvidia,pins = "sdmmc1_dat2_pm3";
Jeremy Cline 36b34bf
+				nvidia,function = "sdmmc1";
Jeremy Cline 36b34bf
+				nvidia,pull = <TEGRA_PIN_PULL_UP>;
Jeremy Cline 36b34bf
+				nvidia,tristate = <TEGRA_PIN_DISABLE>;
Jeremy Cline 36b34bf
+				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
Jeremy Cline 36b34bf
+				nvidia,open-drain = <TEGRA_PIN_DISABLE>;
Jeremy Cline 36b34bf
+			};
Jeremy Cline 36b34bf
+			sdmmc1_dat1_pm4 {
Jeremy Cline 36b34bf
+				nvidia,pins = "sdmmc1_dat1_pm4";
Jeremy Cline 36b34bf
+				nvidia,function = "sdmmc1";
Jeremy Cline 36b34bf
+				nvidia,pull = <TEGRA_PIN_PULL_UP>;
Jeremy Cline 36b34bf
+				nvidia,tristate = <TEGRA_PIN_DISABLE>;
Jeremy Cline 36b34bf
+				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
Jeremy Cline 36b34bf
+				nvidia,open-drain = <TEGRA_PIN_DISABLE>;
Jeremy Cline 36b34bf
+			};
Jeremy Cline 36b34bf
+			sdmmc1_dat0_pm5 {
Jeremy Cline 36b34bf
+				nvidia,pins = "sdmmc1_dat0_pm5";
Jeremy Cline 36b34bf
+				nvidia,function = "sdmmc1";
Jeremy Cline 36b34bf
+				nvidia,pull = <TEGRA_PIN_PULL_UP>;
Jeremy Cline 36b34bf
+				nvidia,tristate = <TEGRA_PIN_DISABLE>;
Jeremy Cline 36b34bf
+				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
Jeremy Cline 36b34bf
+				nvidia,open-drain = <TEGRA_PIN_DISABLE>;
Jeremy Cline 36b34bf
+			};
Jeremy Cline 36b34bf
+			sdmmc3_clk_pp0 {
Jeremy Cline 36b34bf
+				nvidia,pins = "sdmmc3_clk_pp0";
Jeremy Cline 36b34bf
+				nvidia,function = "sdmmc3";
Jeremy Cline 36b34bf
+				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
Jeremy Cline 36b34bf
+				nvidia,tristate = <TEGRA_PIN_DISABLE>;
Jeremy Cline 36b34bf
+				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
Jeremy Cline 36b34bf
+				nvidia,open-drain = <TEGRA_PIN_DISABLE>;
Jeremy Cline 36b34bf
+			};
Jeremy Cline 36b34bf
+			sdmmc3_cmd_pp1 {
Jeremy Cline 36b34bf
+				nvidia,pins = "sdmmc3_cmd_pp1";
Jeremy Cline 36b34bf
+				nvidia,function = "sdmmc3";
Jeremy Cline 36b34bf
+				nvidia,pull = <TEGRA_PIN_PULL_UP>;
Jeremy Cline 36b34bf
+				nvidia,tristate = <TEGRA_PIN_DISABLE>;
Jeremy Cline 36b34bf
+				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
Jeremy Cline 36b34bf
+				nvidia,open-drain = <TEGRA_PIN_DISABLE>;
Jeremy Cline 36b34bf
+			};
Jeremy Cline 36b34bf
+			sdmmc3_dat3_pp2 {
Jeremy Cline 36b34bf
+				nvidia,pins = "sdmmc3_dat3_pp2";
Jeremy Cline 36b34bf
+				nvidia,function = "sdmmc3";
Jeremy Cline 36b34bf
+				nvidia,pull = <TEGRA_PIN_PULL_UP>;
Jeremy Cline 36b34bf
+				nvidia,tristate = <TEGRA_PIN_DISABLE>;
Jeremy Cline 36b34bf
+				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
Jeremy Cline 36b34bf
+				nvidia,open-drain = <TEGRA_PIN_DISABLE>;
Jeremy Cline 36b34bf
+			};
Jeremy Cline 36b34bf
+			sdmmc3_dat2_pp3 {
Jeremy Cline 36b34bf
+				nvidia,pins = "sdmmc3_dat2_pp3";
Jeremy Cline 36b34bf
+				nvidia,function = "sdmmc3";
Jeremy Cline 36b34bf
+				nvidia,pull = <TEGRA_PIN_PULL_UP>;
Jeremy Cline 36b34bf
+				nvidia,tristate = <TEGRA_PIN_DISABLE>;
Jeremy Cline 36b34bf
+				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
Jeremy Cline 36b34bf
+				nvidia,open-drain = <TEGRA_PIN_DISABLE>;
Jeremy Cline 36b34bf
+			};
Jeremy Cline 36b34bf
+			sdmmc3_dat1_pp4 {
Jeremy Cline 36b34bf
+				nvidia,pins = "sdmmc3_dat1_pp4";
Jeremy Cline 36b34bf
+				nvidia,function = "sdmmc3";
Jeremy Cline 36b34bf
+				nvidia,pull = <TEGRA_PIN_PULL_UP>;
Jeremy Cline 36b34bf
+				nvidia,tristate = <TEGRA_PIN_DISABLE>;
Jeremy Cline 36b34bf
+				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
Jeremy Cline 36b34bf
+				nvidia,open-drain = <TEGRA_PIN_DISABLE>;
Jeremy Cline 36b34bf
+			};
Jeremy Cline 36b34bf
+			sdmmc3_dat0_pp5 {
Jeremy Cline 36b34bf
+				nvidia,pins = "sdmmc3_dat0_pp5";
Jeremy Cline 36b34bf
+				nvidia,function = "sdmmc3";
Jeremy Cline 36b34bf
+				nvidia,pull = <TEGRA_PIN_PULL_UP>;
Jeremy Cline 36b34bf
+				nvidia,tristate = <TEGRA_PIN_DISABLE>;
Jeremy Cline 36b34bf
+				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
Jeremy Cline 36b34bf
+				nvidia,open-drain = <TEGRA_PIN_DISABLE>;
Jeremy Cline 36b34bf
+			};
Jeremy Cline 36b34bf
+			cam1_mclk_ps0 {
Jeremy Cline 36b34bf
+				nvidia,pins = "cam1_mclk_ps0";
Jeremy Cline 36b34bf
+				nvidia,function = "extperiph3";
Jeremy Cline 36b34bf
+				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
Jeremy Cline 36b34bf
+				nvidia,tristate = <TEGRA_PIN_DISABLE>;
Jeremy Cline 36b34bf
+				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
Jeremy Cline 36b34bf
+				nvidia,open-drain = <TEGRA_PIN_DISABLE>;
Jeremy Cline 36b34bf
+			};
Jeremy Cline 36b34bf
+			cam2_mclk_ps1 {
Jeremy Cline 36b34bf
+				nvidia,pins = "cam2_mclk_ps1";
Jeremy Cline 36b34bf
+				nvidia,function = "extperiph3";
Jeremy Cline 36b34bf
+				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
Jeremy Cline 36b34bf
+				nvidia,tristate = <TEGRA_PIN_DISABLE>;
Jeremy Cline 36b34bf
+				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
Jeremy Cline 36b34bf
+				nvidia,open-drain = <TEGRA_PIN_DISABLE>;
Jeremy Cline 36b34bf
+			};
Jeremy Cline 36b34bf
+			cam_i2c_scl_ps2 {
Jeremy Cline 36b34bf
+				nvidia,pins = "cam_i2c_scl_ps2";
Jeremy Cline 36b34bf
+				nvidia,function = "i2cvi";
Jeremy Cline 36b34bf
+				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
Jeremy Cline 36b34bf
+				nvidia,tristate = <TEGRA_PIN_DISABLE>;
Jeremy Cline 36b34bf
+				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
Jeremy Cline 36b34bf
+				nvidia,open-drain = <TEGRA_PIN_DISABLE>;
Jeremy Cline 36b34bf
+				nvidia,io-hv = <TEGRA_PIN_ENABLE>;
Jeremy Cline 36b34bf
+			};
Jeremy Cline 36b34bf
+			cam_i2c_sda_ps3 {
Jeremy Cline 36b34bf
+				nvidia,pins = "cam_i2c_sda_ps3";
Jeremy Cline 36b34bf
+				nvidia,function = "i2cvi";
Jeremy Cline 36b34bf
+				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
Jeremy Cline 36b34bf
+				nvidia,tristate = <TEGRA_PIN_DISABLE>;
Jeremy Cline 36b34bf
+				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
Jeremy Cline 36b34bf
+				nvidia,open-drain = <TEGRA_PIN_DISABLE>;
Jeremy Cline 36b34bf
+				nvidia,io-hv = <TEGRA_PIN_ENABLE>;
Jeremy Cline 36b34bf
+			};
Jeremy Cline 36b34bf
+			cam_rst_ps4 {
Jeremy Cline 36b34bf
+				nvidia,pins = "cam_rst_ps4";
Jeremy Cline 36b34bf
+				nvidia,function = "rsvd1";
Jeremy Cline 36b34bf
+				nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
Jeremy Cline 36b34bf
+				nvidia,tristate = <TEGRA_PIN_ENABLE>;
Jeremy Cline 36b34bf
+				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
Jeremy Cline 36b34bf
+				nvidia,open-drain = <TEGRA_PIN_DISABLE>;
Jeremy Cline 36b34bf
+			};
Jeremy Cline 36b34bf
+			cam_af_en_ps5 {
Jeremy Cline 36b34bf
+				nvidia,pins = "cam_af_en_ps5";
Jeremy Cline 36b34bf
+				nvidia,pull = <TEGRA_PIN_PULL_UP>;
Jeremy Cline 36b34bf
+				nvidia,tristate = <TEGRA_PIN_DISABLE>;
Jeremy Cline 36b34bf
+				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
Jeremy Cline 36b34bf
+				nvidia,open-drain = <TEGRA_PIN_DISABLE>;
Jeremy Cline 36b34bf
+			};
Jeremy Cline 36b34bf
+			cam_flash_en_ps6 {
Jeremy Cline 36b34bf
+				nvidia,pins = "cam_flash_en_ps6";
Jeremy Cline 36b34bf
+				nvidia,function = "rsvd2";
Jeremy Cline 36b34bf
+				nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
Jeremy Cline 36b34bf
+				nvidia,tristate = <TEGRA_PIN_ENABLE>;
Jeremy Cline 36b34bf
+				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
Jeremy Cline 36b34bf
+				nvidia,open-drain = <TEGRA_PIN_DISABLE>;
Jeremy Cline 36b34bf
+			};
Jeremy Cline 36b34bf
+			cam1_pwdn_ps7 {
Jeremy Cline 36b34bf
+				nvidia,pins = "cam1_pwdn_ps7";
Jeremy Cline 36b34bf
+				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
Jeremy Cline 36b34bf
+				nvidia,tristate = <TEGRA_PIN_DISABLE>;
Jeremy Cline 36b34bf
+				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
Jeremy Cline 36b34bf
+				nvidia,open-drain = <TEGRA_PIN_DISABLE>;
Jeremy Cline 36b34bf
+			};
Jeremy Cline 36b34bf
+			cam2_pwdn_pt0 {
Jeremy Cline 36b34bf
+				nvidia,pins = "cam2_pwdn_pt0";
Jeremy Cline 36b34bf
+				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
Jeremy Cline 36b34bf
+				nvidia,tristate = <TEGRA_PIN_DISABLE>;
Jeremy Cline 36b34bf
+				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
Jeremy Cline 36b34bf
+				nvidia,open-drain = <TEGRA_PIN_DISABLE>;
Jeremy Cline 36b34bf
+			};
Jeremy Cline 36b34bf
+			cam1_strobe_pt1 {
Jeremy Cline 36b34bf
+				nvidia,pins = "cam1_strobe_pt1";
Jeremy Cline 36b34bf
+				nvidia,function = "rsvd1";
Jeremy Cline 36b34bf
+				nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
Jeremy Cline 36b34bf
+				nvidia,tristate = <TEGRA_PIN_ENABLE>;
Jeremy Cline 36b34bf
+				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
Jeremy Cline 36b34bf
+				nvidia,open-drain = <TEGRA_PIN_DISABLE>;
Jeremy Cline 36b34bf
+			};
Jeremy Cline 36b34bf
+			uart1_tx_pu0 {
Jeremy Cline 36b34bf
+				nvidia,pins = "uart1_tx_pu0";
Jeremy Cline 36b34bf
+				nvidia,function = "uarta";
Jeremy Cline 36b34bf
+				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
Jeremy Cline 36b34bf
+				nvidia,tristate = <TEGRA_PIN_DISABLE>;
Jeremy Cline 36b34bf
+				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
Jeremy Cline 36b34bf
+				nvidia,open-drain = <TEGRA_PIN_DISABLE>;
Jeremy Cline 36b34bf
+			};
Jeremy Cline 36b34bf
+			uart1_rx_pu1 {
Jeremy Cline 36b34bf
+				nvidia,pins = "uart1_rx_pu1";
Jeremy Cline 36b34bf
+				nvidia,function = "uarta";
Jeremy Cline 36b34bf
+				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
Jeremy Cline 36b34bf
+				nvidia,tristate = <TEGRA_PIN_DISABLE>;
Jeremy Cline 36b34bf
+				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
Jeremy Cline 36b34bf
+				nvidia,open-drain = <TEGRA_PIN_DISABLE>;
Jeremy Cline 36b34bf
+			};
Jeremy Cline 36b34bf
+			uart1_rts_pu2 {
Jeremy Cline 36b34bf
+				nvidia,pins = "uart1_rts_pu2";
Jeremy Cline 36b34bf
+				nvidia,function = "uarta";
Jeremy Cline 36b34bf
+				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
Jeremy Cline 36b34bf
+				nvidia,tristate = <TEGRA_PIN_DISABLE>;
Jeremy Cline 36b34bf
+				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
Jeremy Cline 36b34bf
+				nvidia,open-drain = <TEGRA_PIN_DISABLE>;
Jeremy Cline 36b34bf
+			};
Jeremy Cline 36b34bf
+			uart1_cts_pu3 {
Jeremy Cline 36b34bf
+				nvidia,pins = "uart1_cts_pu3";
Jeremy Cline 36b34bf
+				nvidia,function = "rsvd1";
Jeremy Cline 36b34bf
+				nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
Jeremy Cline 36b34bf
+				nvidia,tristate = <TEGRA_PIN_ENABLE>;
Jeremy Cline 36b34bf
+				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
Jeremy Cline 36b34bf
+				nvidia,open-drain = <TEGRA_PIN_DISABLE>;
Jeremy Cline 36b34bf
+			};
Jeremy Cline 36b34bf
+			lcd_bl_pwm_pv0 {
Jeremy Cline 36b34bf
+				nvidia,pins = "lcd_bl_pwm_pv0";
Jeremy Cline 36b34bf
+				nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
Jeremy Cline 36b34bf
+				nvidia,tristate = <TEGRA_PIN_DISABLE>;
Jeremy Cline 36b34bf
+				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
Jeremy Cline 36b34bf
+				nvidia,open-drain = <TEGRA_PIN_DISABLE>;
Jeremy Cline 36b34bf
+			};
Jeremy Cline 36b34bf
+			lcd_bl_en_pv1 {
Jeremy Cline 36b34bf
+				nvidia,pins = "lcd_bl_en_pv1";
Jeremy Cline 36b34bf
+				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
Jeremy Cline 36b34bf
+				nvidia,tristate = <TEGRA_PIN_DISABLE>;
Jeremy Cline 36b34bf
+				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
Jeremy Cline 36b34bf
+				nvidia,open-drain = <TEGRA_PIN_DISABLE>;
Jeremy Cline 36b34bf
+			};
Jeremy Cline 36b34bf
+			lcd_rst_pv2 {
Jeremy Cline 36b34bf
+				nvidia,pins = "lcd_rst_pv2";
Jeremy Cline 36b34bf
+				nvidia,function = "rsvd0";
Jeremy Cline 36b34bf
+				nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
Jeremy Cline 36b34bf
+				nvidia,tristate = <TEGRA_PIN_ENABLE>;
Jeremy Cline 36b34bf
+				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
Jeremy Cline 36b34bf
+				nvidia,open-drain = <TEGRA_PIN_DISABLE>;
Jeremy Cline 36b34bf
+			};
Jeremy Cline 36b34bf
+			lcd_gpio1_pv3 {
Jeremy Cline 36b34bf
+				nvidia,pins = "lcd_gpio1_pv3";
Jeremy Cline 36b34bf
+				nvidia,function = "rsvd1";
Jeremy Cline 36b34bf
+				nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
Jeremy Cline 36b34bf
+				nvidia,tristate = <TEGRA_PIN_ENABLE>;
Jeremy Cline 36b34bf
+				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
Jeremy Cline 36b34bf
+				nvidia,open-drain = <TEGRA_PIN_DISABLE>;
Jeremy Cline 36b34bf
+			};
Jeremy Cline 36b34bf
+			lcd_gpio2_pv4 {
Jeremy Cline 36b34bf
+				nvidia,pins = "lcd_gpio2_pv4";
Jeremy Cline 36b34bf
+				nvidia,function = "pwm1";
Jeremy Cline 36b34bf
+				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
Jeremy Cline 36b34bf
+				nvidia,tristate = <TEGRA_PIN_DISABLE>;
Jeremy Cline 36b34bf
+				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
Jeremy Cline 36b34bf
+				nvidia,open-drain = <TEGRA_PIN_DISABLE>;
Jeremy Cline 36b34bf
+			};
Jeremy Cline 36b34bf
+			ap_ready_pv5 {
Jeremy Cline 36b34bf
+				nvidia,pins = "ap_ready_pv5";
Jeremy Cline 36b34bf
+				nvidia,function = "rsvd0";
Jeremy Cline 36b34bf
+				nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
Jeremy Cline 36b34bf
+				nvidia,tristate = <TEGRA_PIN_ENABLE>;
Jeremy Cline 36b34bf
+				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
Jeremy Cline 36b34bf
+				nvidia,open-drain = <TEGRA_PIN_DISABLE>;
Jeremy Cline 36b34bf
+			};
Jeremy Cline 36b34bf
+			touch_rst_pv6 {
Jeremy Cline 36b34bf
+				nvidia,pins = "touch_rst_pv6";
Jeremy Cline 36b34bf
+				nvidia,function = "rsvd0";
Jeremy Cline 36b34bf
+				nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
Jeremy Cline 36b34bf
+				nvidia,tristate = <TEGRA_PIN_ENABLE>;
Jeremy Cline 36b34bf
+				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
Jeremy Cline 36b34bf
+				nvidia,open-drain = <TEGRA_PIN_DISABLE>;
Jeremy Cline 36b34bf
+			};
Jeremy Cline 36b34bf
+			touch_clk_pv7 {
Jeremy Cline 36b34bf
+				nvidia,pins = "touch_clk_pv7";
Jeremy Cline 36b34bf
+				nvidia,function = "rsvd1";
Jeremy Cline 36b34bf
+				nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
Jeremy Cline 36b34bf
+				nvidia,tristate = <TEGRA_PIN_ENABLE>;
Jeremy Cline 36b34bf
+				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
Jeremy Cline 36b34bf
+				nvidia,open-drain = <TEGRA_PIN_DISABLE>;
Jeremy Cline 36b34bf
+			};
Jeremy Cline 36b34bf
+			modem_wake_ap_px0 {
Jeremy Cline 36b34bf
+				nvidia,pins = "modem_wake_ap_px0";
Jeremy Cline 36b34bf
+				nvidia,function = "rsvd0";
Jeremy Cline 36b34bf
+				nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
Jeremy Cline 36b34bf
+				nvidia,tristate = <TEGRA_PIN_ENABLE>;
Jeremy Cline 36b34bf
+				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
Jeremy Cline 36b34bf
+				nvidia,open-drain = <TEGRA_PIN_DISABLE>;
Jeremy Cline 36b34bf
+			};
Jeremy Cline 36b34bf
+			touch_int_px1 {
Jeremy Cline 36b34bf
+				nvidia,pins = "touch_int_px1";
Jeremy Cline 36b34bf
+				nvidia,function = "rsvd0";
Jeremy Cline 36b34bf
+				nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
Jeremy Cline 36b34bf
+				nvidia,tristate = <TEGRA_PIN_ENABLE>;
Jeremy Cline 36b34bf
+				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
Jeremy Cline 36b34bf
+				nvidia,open-drain = <TEGRA_PIN_DISABLE>;
Jeremy Cline 36b34bf
+			};
Jeremy Cline 36b34bf
+			motion_int_px2 {
Jeremy Cline 36b34bf
+				nvidia,pins = "motion_int_px2";
Jeremy Cline 36b34bf
+				nvidia,function = "rsvd0";
Jeremy Cline 36b34bf
+				nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
Jeremy Cline 36b34bf
+				nvidia,tristate = <TEGRA_PIN_ENABLE>;
Jeremy Cline 36b34bf
+				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
Jeremy Cline 36b34bf
+				nvidia,open-drain = <TEGRA_PIN_DISABLE>;
Jeremy Cline 36b34bf
+			};
Jeremy Cline 36b34bf
+			als_prox_int_px3 {
Jeremy Cline 36b34bf
+				nvidia,pins = "als_prox_int_px3";
Jeremy Cline 36b34bf
+				nvidia,pull = <TEGRA_PIN_PULL_UP>;
Jeremy Cline 36b34bf
+				nvidia,tristate = <TEGRA_PIN_DISABLE>;
Jeremy Cline 36b34bf
+				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
Jeremy Cline 36b34bf
+				nvidia,open-drain = <TEGRA_PIN_DISABLE>;
Jeremy Cline 36b34bf
+			};
Jeremy Cline 36b34bf
+			temp_alert_px4 {
Jeremy Cline 36b34bf
+				nvidia,pins = "temp_alert_px4";
Jeremy Cline 36b34bf
+				nvidia,pull = <TEGRA_PIN_PULL_UP>;
Jeremy Cline 36b34bf
+				nvidia,tristate = <TEGRA_PIN_DISABLE>;
Jeremy Cline 36b34bf
+				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
Jeremy Cline 36b34bf
+				nvidia,open-drain = <TEGRA_PIN_DISABLE>;
Jeremy Cline 36b34bf
+			};
Jeremy Cline 36b34bf
+			button_power_on_px5 {
Jeremy Cline 36b34bf
+				nvidia,pins = "button_power_on_px5";
Jeremy Cline 36b34bf
+				nvidia,pull = <TEGRA_PIN_PULL_UP>;
Jeremy Cline 36b34bf
+				nvidia,tristate = <TEGRA_PIN_DISABLE>;
Jeremy Cline 36b34bf
+				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
Jeremy Cline 36b34bf
+				nvidia,open-drain = <TEGRA_PIN_DISABLE>;
Jeremy Cline 36b34bf
+			};
Jeremy Cline 36b34bf
+			button_vol_up_px6 {
Jeremy Cline 36b34bf
+				nvidia,pins = "button_vol_up_px6";
Jeremy Cline 36b34bf
+				nvidia,pull = <TEGRA_PIN_PULL_UP>;
Jeremy Cline 36b34bf
+				nvidia,tristate = <TEGRA_PIN_DISABLE>;
Jeremy Cline 36b34bf
+				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
Jeremy Cline 36b34bf
+				nvidia,open-drain = <TEGRA_PIN_DISABLE>;
Jeremy Cline 36b34bf
+			};
Jeremy Cline 36b34bf
+			button_vol_down_px7 {
Jeremy Cline 36b34bf
+				nvidia,pins = "button_vol_down_px7";
Jeremy Cline 36b34bf
+				nvidia,function = "rsvd0";
Jeremy Cline 36b34bf
+				nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
Jeremy Cline 36b34bf
+				nvidia,tristate = <TEGRA_PIN_ENABLE>;
Jeremy Cline 36b34bf
+				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
Jeremy Cline 36b34bf
+				nvidia,open-drain = <TEGRA_PIN_DISABLE>;
Jeremy Cline 36b34bf
+			};
Jeremy Cline 36b34bf
+			button_slide_sw_py0 {
Jeremy Cline 36b34bf
+				nvidia,pins = "button_slide_sw_py0";
Jeremy Cline 36b34bf
+				nvidia,function = "rsvd0";
Jeremy Cline 36b34bf
+				nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
Jeremy Cline 36b34bf
+				nvidia,tristate = <TEGRA_PIN_ENABLE>;
Jeremy Cline 36b34bf
+				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
Jeremy Cline 36b34bf
+				nvidia,open-drain = <TEGRA_PIN_DISABLE>;
Jeremy Cline 36b34bf
+			};
Jeremy Cline 36b34bf
+			button_home_py1 {
Jeremy Cline 36b34bf
+				nvidia,pins = "button_home_py1";
Jeremy Cline 36b34bf
+				nvidia,pull = <TEGRA_PIN_PULL_UP>;
Jeremy Cline 36b34bf
+				nvidia,tristate = <TEGRA_PIN_DISABLE>;
Jeremy Cline 36b34bf
+				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
Jeremy Cline 36b34bf
+				nvidia,open-drain = <TEGRA_PIN_DISABLE>;
Jeremy Cline 36b34bf
+			};
Jeremy Cline 36b34bf
+			lcd_te_py2 {
Jeremy Cline 36b34bf
+				nvidia,pins = "lcd_te_py2";
Jeremy Cline 36b34bf
+				nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
Jeremy Cline 36b34bf
+				nvidia,tristate = <TEGRA_PIN_DISABLE>;
Jeremy Cline 36b34bf
+				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
Jeremy Cline 36b34bf
+				nvidia,open-drain = <TEGRA_PIN_DISABLE>;
Jeremy Cline 36b34bf
+			};
Jeremy Cline 36b34bf
+			pwr_i2c_scl_py3 {
Jeremy Cline 36b34bf
+				nvidia,pins = "pwr_i2c_scl_py3";
Jeremy Cline 36b34bf
+				nvidia,function = "i2cpmu";
Jeremy Cline 36b34bf
+				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
Jeremy Cline 36b34bf
+				nvidia,tristate = <TEGRA_PIN_DISABLE>;
Jeremy Cline 36b34bf
+				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
Jeremy Cline 36b34bf
+				nvidia,open-drain = <TEGRA_PIN_DISABLE>;
Jeremy Cline 36b34bf
+				nvidia,io-hv = <TEGRA_PIN_DISABLE>;
Jeremy Cline 36b34bf
+			};
Jeremy Cline 36b34bf
+			pwr_i2c_sda_py4 {
Jeremy Cline 36b34bf
+				nvidia,pins = "pwr_i2c_sda_py4";
Jeremy Cline 36b34bf
+				nvidia,function = "i2cpmu";
Jeremy Cline 36b34bf
+				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
Jeremy Cline 36b34bf
+				nvidia,tristate = <TEGRA_PIN_DISABLE>;
Jeremy Cline 36b34bf
+				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
Jeremy Cline 36b34bf
+				nvidia,open-drain = <TEGRA_PIN_DISABLE>;
Jeremy Cline 36b34bf
+				nvidia,io-hv = <TEGRA_PIN_DISABLE>;
Jeremy Cline 36b34bf
+			};
Jeremy Cline 36b34bf
+			clk_32k_out_py5 {
Jeremy Cline 36b34bf
+				nvidia,pins = "clk_32k_out_py5";
Jeremy Cline 36b34bf
+				nvidia,function = "rsvd2";
Jeremy Cline 36b34bf
+				nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
Jeremy Cline 36b34bf
+				nvidia,tristate = <TEGRA_PIN_ENABLE>;
Jeremy Cline 36b34bf
+				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
Jeremy Cline 36b34bf
+				nvidia,open-drain = <TEGRA_PIN_DISABLE>;
Jeremy Cline 36b34bf
+			};
Jeremy Cline 36b34bf
+			pz0 {
Jeremy Cline 36b34bf
+				nvidia,pins = "pz0";
Jeremy Cline 36b34bf
+				nvidia,pull = <TEGRA_PIN_PULL_UP>;
Jeremy Cline 36b34bf
+				nvidia,tristate = <TEGRA_PIN_DISABLE>;
Jeremy Cline 36b34bf
+				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
Jeremy Cline 36b34bf
+				nvidia,open-drain = <TEGRA_PIN_DISABLE>;
Jeremy Cline 36b34bf
+			};
Jeremy Cline 36b34bf
+			pz1 {
Jeremy Cline 36b34bf
+				nvidia,pins = "pz1";
Jeremy Cline 36b34bf
+				nvidia,function = "sdmmc1";
Jeremy Cline 36b34bf
+				nvidia,pull = <TEGRA_PIN_PULL_UP>;
Jeremy Cline 36b34bf
+				nvidia,tristate = <TEGRA_PIN_DISABLE>;
Jeremy Cline 36b34bf
+				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
Jeremy Cline 36b34bf
+				nvidia,open-drain = <TEGRA_PIN_DISABLE>;
Jeremy Cline 36b34bf
+			};
Jeremy Cline 36b34bf
+			pz2 {
Jeremy Cline 36b34bf
+				nvidia,pins = "pz2";
Jeremy Cline 36b34bf
+				nvidia,pull = <TEGRA_PIN_PULL_UP>;
Jeremy Cline 36b34bf
+				nvidia,tristate = <TEGRA_PIN_DISABLE>;
Jeremy Cline 36b34bf
+				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
Jeremy Cline 36b34bf
+				nvidia,open-drain = <TEGRA_PIN_DISABLE>;
Jeremy Cline 36b34bf
+			};
Jeremy Cline 36b34bf
+			pz3 {
Jeremy Cline 36b34bf
+				nvidia,pins = "pz3";
Jeremy Cline 36b34bf
+				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
Jeremy Cline 36b34bf
+				nvidia,tristate = <TEGRA_PIN_DISABLE>;
Jeremy Cline 36b34bf
+				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
Jeremy Cline 36b34bf
+				nvidia,open-drain = <TEGRA_PIN_DISABLE>;
Jeremy Cline 36b34bf
+			};
Jeremy Cline 36b34bf
+			pz4 {
Jeremy Cline 36b34bf
+				nvidia,pins = "pz4";
Jeremy Cline 36b34bf
+				nvidia,function = "rsvd1";
Jeremy Cline 36b34bf
+				nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
Jeremy Cline 36b34bf
+				nvidia,tristate = <TEGRA_PIN_ENABLE>;
Jeremy Cline 36b34bf
+				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
Jeremy Cline 36b34bf
+				nvidia,open-drain = <TEGRA_PIN_DISABLE>;
Jeremy Cline 36b34bf
+			};
Jeremy Cline 36b34bf
+			pz5 {
Jeremy Cline 36b34bf
+				nvidia,pins = "pz5";
Jeremy Cline 36b34bf
+				nvidia,function = "soc";
Jeremy Cline 36b34bf
+				nvidia,pull = <TEGRA_PIN_PULL_UP>;
Jeremy Cline 36b34bf
+				nvidia,tristate = <TEGRA_PIN_DISABLE>;
Jeremy Cline 36b34bf
+				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
Jeremy Cline 36b34bf
+				nvidia,open-drain = <TEGRA_PIN_DISABLE>;
Jeremy Cline 36b34bf
+			};
Jeremy Cline 36b34bf
+			dap2_fs_paa0 {
Jeremy Cline 36b34bf
+				nvidia,pins = "dap2_fs_paa0";
Jeremy Cline 36b34bf
+				nvidia,function = "i2s2";
Jeremy Cline 36b34bf
+				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
Jeremy Cline 36b34bf
+				nvidia,tristate = <TEGRA_PIN_DISABLE>;
Jeremy Cline 36b34bf
+				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
Jeremy Cline 36b34bf
+				nvidia,open-drain = <TEGRA_PIN_DISABLE>;
Jeremy Cline 36b34bf
+			};
Jeremy Cline 36b34bf
+			dap2_sclk_paa1 {
Jeremy Cline 36b34bf
+				nvidia,pins = "dap2_sclk_paa1";
Jeremy Cline 36b34bf
+				nvidia,function = "i2s2";
Jeremy Cline 36b34bf
+				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
Jeremy Cline 36b34bf
+				nvidia,tristate = <TEGRA_PIN_DISABLE>;
Jeremy Cline 36b34bf
+				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
Jeremy Cline 36b34bf
+				nvidia,open-drain = <TEGRA_PIN_DISABLE>;
Jeremy Cline 36b34bf
+			};
Jeremy Cline 36b34bf
+			dap2_din_paa2 {
Jeremy Cline 36b34bf
+				nvidia,pins = "dap2_din_paa2";
Jeremy Cline 36b34bf
+				nvidia,function = "i2s2";
Jeremy Cline 36b34bf
+				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
Jeremy Cline 36b34bf
+				nvidia,tristate = <TEGRA_PIN_DISABLE>;
Jeremy Cline 36b34bf
+				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
Jeremy Cline 36b34bf
+				nvidia,open-drain = <TEGRA_PIN_DISABLE>;
Jeremy Cline 36b34bf
+			};
Jeremy Cline 36b34bf
+			dap2_dout_paa3 {
Jeremy Cline 36b34bf
+				nvidia,pins = "dap2_dout_paa3";
Jeremy Cline 36b34bf
+				nvidia,function = "i2s2";
Jeremy Cline 36b34bf
+				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
Jeremy Cline 36b34bf
+				nvidia,tristate = <TEGRA_PIN_DISABLE>;
Jeremy Cline 36b34bf
+				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
Jeremy Cline 36b34bf
+				nvidia,open-drain = <TEGRA_PIN_DISABLE>;
Jeremy Cline 36b34bf
+			};
Jeremy Cline 36b34bf
+			aud_mclk_pbb0 {
Jeremy Cline 36b34bf
+				nvidia,pins = "aud_mclk_pbb0";
Jeremy Cline 36b34bf
+				nvidia,pull = <TEGRA_PIN_PULL_UP>;
Jeremy Cline 36b34bf
+				nvidia,tristate = <TEGRA_PIN_DISABLE>;
Jeremy Cline 36b34bf
+				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
Jeremy Cline 36b34bf
+				nvidia,open-drain = <TEGRA_PIN_DISABLE>;
Jeremy Cline 36b34bf
+			};
Jeremy Cline 36b34bf
+			dvfs_pwm_pbb1 {
Jeremy Cline 36b34bf
+				nvidia,pins = "dvfs_pwm_pbb1";
Jeremy Cline 36b34bf
+				nvidia,function = "cldvfs";
Jeremy Cline 36b34bf
+				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
Jeremy Cline 36b34bf
+				nvidia,tristate = <TEGRA_PIN_ENABLE>;
Jeremy Cline 36b34bf
+				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
Jeremy Cline 36b34bf
+				nvidia,open-drain = <TEGRA_PIN_DISABLE>;
Jeremy Cline 36b34bf
+			};
Jeremy Cline 36b34bf
+			dvfs_clk_pbb2 {
Jeremy Cline 36b34bf
+				nvidia,pins = "dvfs_clk_pbb2";
Jeremy Cline 36b34bf
+				nvidia,function = "rsvd0";
Jeremy Cline 36b34bf
+				nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
Jeremy Cline 36b34bf
+				nvidia,tristate = <TEGRA_PIN_ENABLE>;
Jeremy Cline 36b34bf
+				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
Jeremy Cline 36b34bf
+				nvidia,open-drain = <TEGRA_PIN_DISABLE>;
Jeremy Cline 36b34bf
+			};
Jeremy Cline 36b34bf
+			gpio_x1_aud_pbb3 {
Jeremy Cline 36b34bf
+				nvidia,pins = "gpio_x1_aud_pbb3";
Jeremy Cline 36b34bf
+				nvidia,function = "rsvd0";
Jeremy Cline 36b34bf
+				nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
Jeremy Cline 36b34bf
+				nvidia,tristate = <TEGRA_PIN_ENABLE>;
Jeremy Cline 36b34bf
+				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
Jeremy Cline 36b34bf
+				nvidia,open-drain = <TEGRA_PIN_DISABLE>;
Jeremy Cline 36b34bf
+			};
Jeremy Cline 36b34bf
+			gpio_x3_aud_pbb4 {
Jeremy Cline 36b34bf
+				nvidia,pins = "gpio_x3_aud_pbb4";
Jeremy Cline 36b34bf
+				nvidia,function = "rsvd0";
Jeremy Cline 36b34bf
+				nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
Jeremy Cline 36b34bf
+				nvidia,tristate = <TEGRA_PIN_ENABLE>;
Jeremy Cline 36b34bf
+				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
Jeremy Cline 36b34bf
+				nvidia,open-drain = <TEGRA_PIN_DISABLE>;
Jeremy Cline 36b34bf
+			};
Jeremy Cline 36b34bf
+			hdmi_cec_pcc0 {
Jeremy Cline 36b34bf
+				nvidia,pins = "hdmi_cec_pcc0";
Jeremy Cline 36b34bf
+				nvidia,function = "cec";
Jeremy Cline 36b34bf
+				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
Jeremy Cline 36b34bf
+				nvidia,tristate = <TEGRA_PIN_DISABLE>;
Jeremy Cline 36b34bf
+				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
Jeremy Cline 36b34bf
+				nvidia,open-drain = <TEGRA_PIN_DISABLE>;
Jeremy Cline 36b34bf
+				nvidia,io-hv = <TEGRA_PIN_ENABLE>;
Jeremy Cline 36b34bf
+			};
Jeremy Cline 36b34bf
+			hdmi_int_dp_hpd_pcc1 {
Jeremy Cline 36b34bf
+				nvidia,pins = "hdmi_int_dp_hpd_pcc1";
Jeremy Cline 36b34bf
+				nvidia,function = "dp";
Jeremy Cline 36b34bf
+				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
Jeremy Cline 36b34bf
+				nvidia,tristate = <TEGRA_PIN_DISABLE>;
Jeremy Cline 36b34bf
+				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
Jeremy Cline 36b34bf
+				nvidia,open-drain = <TEGRA_PIN_DISABLE>;
Jeremy Cline 36b34bf
+				nvidia,io-hv = <TEGRA_PIN_DISABLE>;
Jeremy Cline 36b34bf
+			};
Jeremy Cline 36b34bf
+			spdif_out_pcc2 {
Jeremy Cline 36b34bf
+				nvidia,pins = "spdif_out_pcc2";
Jeremy Cline 36b34bf
+				nvidia,function = "rsvd1";
Jeremy Cline 36b34bf
+				nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
Jeremy Cline 36b34bf
+				nvidia,tristate = <TEGRA_PIN_ENABLE>;
Jeremy Cline 36b34bf
+				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
Jeremy Cline 36b34bf
+				nvidia,open-drain = <TEGRA_PIN_DISABLE>;
Jeremy Cline 36b34bf
+			};
Jeremy Cline 36b34bf
+			spdif_in_pcc3 {
Jeremy Cline 36b34bf
+				nvidia,pins = "spdif_in_pcc3";
Jeremy Cline 36b34bf
+				nvidia,function = "rsvd1";
Jeremy Cline 36b34bf
+				nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
Jeremy Cline 36b34bf
+				nvidia,tristate = <TEGRA_PIN_ENABLE>;
Jeremy Cline 36b34bf
+				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
Jeremy Cline 36b34bf
+				nvidia,open-drain = <TEGRA_PIN_DISABLE>;
Jeremy Cline 36b34bf
+			};
Jeremy Cline 36b34bf
+			usb_vbus_en0_pcc4 {
Jeremy Cline 36b34bf
+				nvidia,pins = "usb_vbus_en0_pcc4";
Jeremy Cline 36b34bf
+				nvidia,pull = <TEGRA_PIN_PULL_UP>;
Jeremy Cline 36b34bf
+				nvidia,tristate = <TEGRA_PIN_DISABLE>;
Jeremy Cline 36b34bf
+				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
Jeremy Cline 36b34bf
+				nvidia,open-drain = <TEGRA_PIN_DISABLE>;
Jeremy Cline 36b34bf
+				nvidia,io-hv = <TEGRA_PIN_DISABLE>;
Jeremy Cline 36b34bf
+			};
Jeremy Cline 36b34bf
+			usb_vbus_en1_pcc5 {
Jeremy Cline 36b34bf
+				nvidia,pins = "usb_vbus_en1_pcc5";
Jeremy Cline 36b34bf
+				nvidia,function = "rsvd1";
Jeremy Cline 36b34bf
+				nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
Jeremy Cline 36b34bf
+				nvidia,tristate = <TEGRA_PIN_ENABLE>;
Jeremy Cline 36b34bf
+				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
Jeremy Cline 36b34bf
+				nvidia,open-drain = <TEGRA_PIN_DISABLE>;
Jeremy Cline 36b34bf
+				nvidia,io-hv = <TEGRA_PIN_DISABLE>;
Jeremy Cline 36b34bf
+			};
Jeremy Cline 36b34bf
+			dp_hpd0_pcc6 {
Jeremy Cline 36b34bf
+				nvidia,pins = "dp_hpd0_pcc6";
Jeremy Cline 36b34bf
+				nvidia,function = "dp";
Jeremy Cline 36b34bf
+				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
Jeremy Cline 36b34bf
+				nvidia,tristate = <TEGRA_PIN_DISABLE>;
Jeremy Cline 36b34bf
+				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
Jeremy Cline 36b34bf
+				nvidia,open-drain = <TEGRA_PIN_DISABLE>;
Jeremy Cline 36b34bf
+			};
Jeremy Cline 36b34bf
+			pcc7 {
Jeremy Cline 36b34bf
+				nvidia,pins = "pcc7";
Jeremy Cline 36b34bf
+				nvidia,function = "rsvd0";
Jeremy Cline 36b34bf
+				nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
Jeremy Cline 36b34bf
+				nvidia,tristate = <TEGRA_PIN_ENABLE>;
Jeremy Cline 36b34bf
+				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
Jeremy Cline 36b34bf
+				nvidia,open-drain = <TEGRA_PIN_DISABLE>;
Jeremy Cline 36b34bf
+				nvidia,io-hv = <TEGRA_PIN_DISABLE>;
Jeremy Cline 36b34bf
+			};
Jeremy Cline 36b34bf
+			spi2_cs1_pdd0 {
Jeremy Cline 36b34bf
+				nvidia,pins = "spi2_cs1_pdd0";
Jeremy Cline 36b34bf
+				nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
Jeremy Cline 36b34bf
+				nvidia,tristate = <TEGRA_PIN_DISABLE>;
Jeremy Cline 36b34bf
+				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
Jeremy Cline 36b34bf
+				nvidia,open-drain = <TEGRA_PIN_DISABLE>;
Jeremy Cline 36b34bf
+			};
Jeremy Cline 36b34bf
+			qspi_sck_pee0 {
Jeremy Cline 36b34bf
+				nvidia,pins = "qspi_sck_pee0";
Jeremy Cline 36b34bf
+				nvidia,function = "qspi";
Jeremy Cline 36b34bf
+				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
Jeremy Cline 36b34bf
+				nvidia,tristate = <TEGRA_PIN_DISABLE>;
Jeremy Cline 36b34bf
+				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
Jeremy Cline 36b34bf
+				nvidia,open-drain = <TEGRA_PIN_DISABLE>;
Jeremy Cline 36b34bf
+			};
Jeremy Cline 36b34bf
+			qspi_cs_n_pee1 {
Jeremy Cline 36b34bf
+				nvidia,pins = "qspi_cs_n_pee1";
Jeremy Cline 36b34bf
+				nvidia,function = "qspi";
Jeremy Cline 36b34bf
+				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
Jeremy Cline 36b34bf
+				nvidia,tristate = <TEGRA_PIN_DISABLE>;
Jeremy Cline 36b34bf
+				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
Jeremy Cline 36b34bf
+				nvidia,open-drain = <TEGRA_PIN_DISABLE>;
Jeremy Cline 36b34bf
+			};
Jeremy Cline 36b34bf
+			qspi_io0_pee2 {
Jeremy Cline 36b34bf
+				nvidia,pins = "qspi_io0_pee2";
Jeremy Cline 36b34bf
+				nvidia,function = "qspi";
Jeremy Cline 36b34bf
+				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
Jeremy Cline 36b34bf
+				nvidia,tristate = <TEGRA_PIN_DISABLE>;
Jeremy Cline 36b34bf
+				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
Jeremy Cline 36b34bf
+				nvidia,open-drain = <TEGRA_PIN_DISABLE>;
Jeremy Cline 36b34bf
+			};
Jeremy Cline 36b34bf
+			qspi_io1_pee3 {
Jeremy Cline 36b34bf
+				nvidia,pins = "qspi_io1_pee3";
Jeremy Cline 36b34bf
+				nvidia,function = "qspi";
Jeremy Cline 36b34bf
+				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
Jeremy Cline 36b34bf
+				nvidia,tristate = <TEGRA_PIN_DISABLE>;
Jeremy Cline 36b34bf
+				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
Jeremy Cline 36b34bf
+				nvidia,open-drain = <TEGRA_PIN_DISABLE>;
Jeremy Cline 36b34bf
+			};
Jeremy Cline 36b34bf
+			qspi_io2_pee4 {
Jeremy Cline 36b34bf
+				nvidia,pins = "qspi_io2_pee4";
Jeremy Cline 36b34bf
+				nvidia,function = "rsvd1";
Jeremy Cline 36b34bf
+				nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
Jeremy Cline 36b34bf
+				nvidia,tristate = <TEGRA_PIN_ENABLE>;
Jeremy Cline 36b34bf
+				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
Jeremy Cline 36b34bf
+				nvidia,open-drain = <TEGRA_PIN_DISABLE>;
Jeremy Cline 36b34bf
+			};
Jeremy Cline 36b34bf
+			qspi_io3_pee5 {
Jeremy Cline 36b34bf
+				nvidia,pins = "qspi_io3_pee5";
Jeremy Cline 36b34bf
+				nvidia,function = "rsvd1";
Jeremy Cline 36b34bf
+				nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
Jeremy Cline 36b34bf
+				nvidia,tristate = <TEGRA_PIN_ENABLE>;
Jeremy Cline 36b34bf
+				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
Jeremy Cline 36b34bf
+				nvidia,open-drain = <TEGRA_PIN_DISABLE>;
Jeremy Cline 36b34bf
+			};
Jeremy Cline 36b34bf
+			core_pwr_req {
Jeremy Cline 36b34bf
+				nvidia,pins = "core_pwr_req";
Jeremy Cline 36b34bf
+				nvidia,function = "core";
Jeremy Cline 36b34bf
+				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
Jeremy Cline 36b34bf
+				nvidia,tristate = <TEGRA_PIN_DISABLE>;
Jeremy Cline 36b34bf
+				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
Jeremy Cline 36b34bf
+				nvidia,open-drain = <TEGRA_PIN_DISABLE>;
Jeremy Cline 36b34bf
+			};
Jeremy Cline 36b34bf
+			cpu_pwr_req {
Jeremy Cline 36b34bf
+				nvidia,pins = "cpu_pwr_req";
Jeremy Cline 36b34bf
+				nvidia,function = "rsvd1";
Jeremy Cline 36b34bf
+				nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
Jeremy Cline 36b34bf
+				nvidia,tristate = <TEGRA_PIN_ENABLE>;
Jeremy Cline 36b34bf
+				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
Jeremy Cline 36b34bf
+				nvidia,open-drain = <TEGRA_PIN_DISABLE>;
Jeremy Cline 36b34bf
+			};
Jeremy Cline 36b34bf
+			pwr_int_n {
Jeremy Cline 36b34bf
+				nvidia,pins = "pwr_int_n";
Jeremy Cline 36b34bf
+				nvidia,function = "pmi";
Jeremy Cline 36b34bf
+				nvidia,pull = <TEGRA_PIN_PULL_UP>;
Jeremy Cline 36b34bf
+				nvidia,tristate = <TEGRA_PIN_DISABLE>;
Jeremy Cline 36b34bf
+				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
Jeremy Cline 36b34bf
+				nvidia,open-drain = <TEGRA_PIN_DISABLE>;
Jeremy Cline 36b34bf
+			};
Jeremy Cline 36b34bf
+			clk_32k_in {
Jeremy Cline 36b34bf
+				nvidia,pins = "clk_32k_in";
Jeremy Cline 36b34bf
+				nvidia,function = "clk";
Jeremy Cline 36b34bf
+				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
Jeremy Cline 36b34bf
+				nvidia,tristate = <TEGRA_PIN_DISABLE>;
Jeremy Cline 36b34bf
+				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
Jeremy Cline 36b34bf
+				nvidia,open-drain = <TEGRA_PIN_DISABLE>;
Jeremy Cline 36b34bf
+			};
Jeremy Cline 36b34bf
+			jtag_rtck {
Jeremy Cline 36b34bf
+				nvidia,pins = "jtag_rtck";
Jeremy Cline 36b34bf
+				nvidia,function = "jtag";
Jeremy Cline 36b34bf
+				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
Jeremy Cline 36b34bf
+				nvidia,tristate = <TEGRA_PIN_DISABLE>;
Jeremy Cline 36b34bf
+				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
Jeremy Cline 36b34bf
+				nvidia,open-drain = <TEGRA_PIN_DISABLE>;
Jeremy Cline 36b34bf
+			};
Jeremy Cline 36b34bf
+			clk_req {
Jeremy Cline 36b34bf
+				nvidia,pins = "clk_req";
Jeremy Cline 36b34bf
+				nvidia,function = "rsvd1";
Jeremy Cline 36b34bf
+				nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
Jeremy Cline 36b34bf
+				nvidia,tristate = <TEGRA_PIN_ENABLE>;
Jeremy Cline 36b34bf
+				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
Jeremy Cline 36b34bf
+				nvidia,open-drain = <TEGRA_PIN_DISABLE>;
Jeremy Cline 36b34bf
+			};
Jeremy Cline 36b34bf
+			shutdown {
Jeremy Cline 36b34bf
+				nvidia,pins = "shutdown";
Jeremy Cline 36b34bf
+				nvidia,function = "shutdown";
Jeremy Cline 36b34bf
+				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
Jeremy Cline 36b34bf
+				nvidia,tristate = <TEGRA_PIN_DISABLE>;
Jeremy Cline 36b34bf
+				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
Jeremy Cline 36b34bf
+				nvidia,open-drain = <TEGRA_PIN_DISABLE>;
Jeremy Cline 36b34bf
+			};
Jeremy Cline 36b34bf
+		};
Jeremy Cline 36b34bf
+	};
Jeremy Cline 36b34bf
+
Jeremy Cline 36b34bf
+	/* debug port */
Jeremy Cline 36b34bf
+	serial@70006000 {
Jeremy Cline 36b34bf
+		status = "okay";
Jeremy Cline 36b34bf
+	};
Jeremy Cline 36b34bf
+
Jeremy Cline 36b34bf
+	hdmi_ddc: i2c@7000c700 {
Jeremy Cline 36b34bf
+		status = "okay";
Jeremy Cline 36b34bf
+		clock-frequency = <100000>;
Jeremy Cline 36b34bf
+	};
Jeremy Cline 36b34bf
+
Jeremy Cline 36b34bf
+	i2c@7000d000 {
Jeremy Cline 36b34bf
+		status = "okay";
Jeremy Cline 36b34bf
+		clock-frequency = <400000>;
Jeremy Cline 36b34bf
+
Jeremy Cline 36b34bf
+		pmic: pmic@3c {
Jeremy Cline 36b34bf
+			compatible = "maxim,max77620";
Jeremy Cline 36b34bf
+			reg = <0x3c>;
Jeremy Cline 36b34bf
+			interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
Jeremy Cline 36b34bf
+
Jeremy Cline 36b34bf
+			#interrupt-cells = <2>;
Jeremy Cline 36b34bf
+			interrupt-controller;
Jeremy Cline 36b34bf
+
Jeremy Cline 36b34bf
+			#gpio-cells = <2>;
Jeremy Cline 36b34bf
+			gpio-controller;
Jeremy Cline 36b34bf
+
Jeremy Cline 36b34bf
+			pinctrl-names = "default";
Jeremy Cline 36b34bf
+			pinctrl-0 = <&max77620_default>;
Jeremy Cline 36b34bf
+
Jeremy Cline 36b34bf
+			max77620_default: pinmux {
Jeremy Cline 36b34bf
+				gpio0 {
Jeremy Cline 36b34bf
+					pins = "gpio0";
Jeremy Cline 36b34bf
+					function = "gpio";
Jeremy Cline 36b34bf
+				};
Jeremy Cline 36b34bf
+
Jeremy Cline 36b34bf
+				gpio1 {
Jeremy Cline 36b34bf
+					pins = "gpio1";
Jeremy Cline 36b34bf
+					function = "fps-out";
Jeremy Cline 36b34bf
+					drive-push-pull = <1>;
Jeremy Cline 36b34bf
+					maxim,active-fps-source = <MAX77620_FPS_SRC_NONE>;
Jeremy Cline 36b34bf
+					maxim,active-fps-power-up-slot = <0>;
Jeremy Cline 36b34bf
+					maxim,active-fps-power-down-slot = <7>;
Jeremy Cline 36b34bf
+				};
Jeremy Cline 36b34bf
+
Jeremy Cline 36b34bf
+				gpio2 {
Jeremy Cline 36b34bf
+					pins = "gpio2";
Jeremy Cline 36b34bf
+					function = "fps-out";
Jeremy Cline 36b34bf
+					drive-open-drain = <1>;
Jeremy Cline 36b34bf
+					maxim,active-fps-source = <MAX77620_FPS_SRC_0>;
Jeremy Cline 36b34bf
+					maxim,active-fps-power-up-slot = <0>;
Jeremy Cline 36b34bf
+					maxim,active-fps-power-down-slot = <7>;
Jeremy Cline 36b34bf
+				};
Jeremy Cline 36b34bf
+
Jeremy Cline 36b34bf
+				gpio3 {
Jeremy Cline 36b34bf
+					pins = "gpio3";
Jeremy Cline 36b34bf
+					function = "fps-out";
Jeremy Cline 36b34bf
+					drive-open-drain = <1>;
Jeremy Cline 36b34bf
+					maxim,active-fps-source = <MAX77620_FPS_SRC_0>;
Jeremy Cline 36b34bf
+					maxim,active-fps-power-up-slot = <4>;
Jeremy Cline 36b34bf
+					maxim,active-fps-power-down-slot = <3>;
Jeremy Cline 36b34bf
+				};
Jeremy Cline 36b34bf
+
Jeremy Cline 36b34bf
+				gpio4 {
Jeremy Cline 36b34bf
+					pins = "gpio4";
Jeremy Cline 36b34bf
+					function = "32k-out1";
Jeremy Cline 36b34bf
+				};
Jeremy Cline 36b34bf
+
Jeremy Cline 36b34bf
+				gpio5_6_7 {
Jeremy Cline 36b34bf
+					pins = "gpio5", "gpio6", "gpio7";
Jeremy Cline 36b34bf
+					function = "gpio";
Jeremy Cline 36b34bf
+					drive-push-pull = <1>;
Jeremy Cline 36b34bf
+				};
Jeremy Cline 36b34bf
+			};
Jeremy Cline 36b34bf
+
Jeremy Cline 36b34bf
+			fps {
Jeremy Cline 36b34bf
+				fps0 {
Jeremy Cline 36b34bf
+					maxim,fps-event-source = <MAX77620_FPS_EVENT_SRC_EN0>;
Jeremy Cline 36b34bf
+					maxim,suspend-fps-time-period-us = <5120>;
Jeremy Cline 36b34bf
+				};
Jeremy Cline 36b34bf
+
Jeremy Cline 36b34bf
+				fps1 {
Jeremy Cline 36b34bf
+					maxim,fps-event-source = <MAX77620_FPS_EVENT_SRC_EN1>;
Jeremy Cline 36b34bf
+					maxim,suspend-fps-time-period-us = <5120>;
Jeremy Cline 36b34bf
+				};
Jeremy Cline 36b34bf
+
Jeremy Cline 36b34bf
+				fps2 {
Jeremy Cline 36b34bf
+					maxim,fps-event-source = <MAX77620_FPS_EVENT_SRC_EN0>;
Jeremy Cline 36b34bf
+				};
Jeremy Cline 36b34bf
+			};
Jeremy Cline 36b34bf
+
Jeremy Cline 36b34bf
+			regulators {
Jeremy Cline 36b34bf
+				in-ldo0-1-supply = <&vdd_pre>;
Jeremy Cline 36b34bf
+				in-ldo2-supply = <&vdd_3v3_sys>;
Jeremy Cline 36b34bf
+				in-ldo3-5-supply = <&vdd_1v8>;
Jeremy Cline 36b34bf
+				in-ldo4-6-supply = <&vdd_5v0_sys>;
Jeremy Cline 36b34bf
+				in-ldo7-8-supply = <&vdd_pre>;
Jeremy Cline 36b34bf
+				in-sd0-supply = <&vdd_5v0_sys>;
Jeremy Cline 36b34bf
+				in-sd1-supply = <&vdd_5v0_sys>;
Jeremy Cline 36b34bf
+				in-sd2-supply = <&vdd_5v0_sys>;
Jeremy Cline 36b34bf
+				in-sd3-supply = <&vdd_5v0_sys>;
Jeremy Cline 36b34bf
+
Jeremy Cline 36b34bf
+				vdd_soc: sd0 {
Jeremy Cline 36b34bf
+					regulator-name = "VDD_SOC";
Jeremy Cline 36b34bf
+					regulator-min-microvolt = <1000000>;
Jeremy Cline 36b34bf
+					regulator-max-microvolt = <1170000>;
Jeremy Cline 36b34bf
+					regulator-enable-ramp-delay = <146>;
Jeremy Cline 36b34bf
+					regulator-disable-ramp-delay = <4080>;
Jeremy Cline 36b34bf
+					regulator-ramp-delay = <27500>;
Jeremy Cline 36b34bf
+					regulator-ramp-delay-scale = <300>;
Jeremy Cline 36b34bf
+					regulator-always-on;
Jeremy Cline 36b34bf
+					regulator-boot-on;
Jeremy Cline 36b34bf
+
Jeremy Cline 36b34bf
+					maxim,active-fps-source = <MAX77620_FPS_SRC_1>;
Jeremy Cline 36b34bf
+					maxim,active-fps-power-up-slot = <1>;
Jeremy Cline 36b34bf
+					maxim,active-fps-power-down-slot = <6>;
Jeremy Cline 36b34bf
+				};
Jeremy Cline 36b34bf
+
Jeremy Cline 36b34bf
+				vdd_ddr: sd1 {
Jeremy Cline 36b34bf
+					regulator-name = "VDD_DDR_1V1_PMIC";
Jeremy Cline 36b34bf
+					regulator-min-microvolt = <1150000>;
Jeremy Cline 36b34bf
+					regulator-max-microvolt = <1150000>;
Jeremy Cline 36b34bf
+					regulator-enable-ramp-delay = <176>;
Jeremy Cline 36b34bf
+					regulator-disable-ramp-delay = <145800>;
Jeremy Cline 36b34bf
+					regulator-ramp-delay = <27500>;
Jeremy Cline 36b34bf
+					regulator-ramp-delay-scale = <300>;
Jeremy Cline 36b34bf
+					regulator-always-on;
Jeremy Cline 36b34bf
+					regulator-boot-on;
Jeremy Cline 36b34bf
+
Jeremy Cline 36b34bf
+					maxim,active-fps-source = <MAX77620_FPS_SRC_0>;
Jeremy Cline 36b34bf
+					maxim,active-fps-power-up-slot = <5>;
Jeremy Cline 36b34bf
+					maxim,active-fps-power-down-slot = <2>;
Jeremy Cline 36b34bf
+				};
Jeremy Cline 36b34bf
+
Jeremy Cline 36b34bf
+				vdd_pre: sd2 {
Jeremy Cline 36b34bf
+					regulator-name = "VDD_PRE_REG_1V35";
Jeremy Cline 36b34bf
+					regulator-min-microvolt = <1350000>;
Jeremy Cline 36b34bf
+					regulator-max-microvolt = <1350000>;
Jeremy Cline 36b34bf
+					regulator-enable-ramp-delay = <176>;
Jeremy Cline 36b34bf
+					regulator-disable-ramp-delay = <32000>;
Jeremy Cline 36b34bf
+					regulator-ramp-delay = <27500>;
Jeremy Cline 36b34bf
+					regulator-ramp-delay-scale = <350>;
Jeremy Cline 36b34bf
+					regulator-always-on;
Jeremy Cline 36b34bf
+					regulator-boot-on;
Jeremy Cline 36b34bf
+
Jeremy Cline 36b34bf
+					maxim,active-fps-source = <MAX77620_FPS_SRC_1>;
Jeremy Cline 36b34bf
+					maxim,active-fps-power-up-slot = <2>;
Jeremy Cline 36b34bf
+					maxim,active-fps-power-down-slot = <5>;
Jeremy Cline 36b34bf
+				};
Jeremy Cline 36b34bf
+
Jeremy Cline 36b34bf
+				vdd_1v8: sd3 {
Jeremy Cline 36b34bf
+					regulator-name = "VDD_1V8";
Jeremy Cline 36b34bf
+					regulator-min-microvolt = <1800000>;
Jeremy Cline 36b34bf
+					regulator-max-microvolt = <1800000>;
Jeremy Cline 36b34bf
+					regulator-enable-ramp-delay = <242>;
Jeremy Cline 36b34bf
+					regulator-disable-ramp-delay = <118000>;
Jeremy Cline 36b34bf
+					regulator-ramp-delay = <27500>;
Jeremy Cline 36b34bf
+					regulator-ramp-delay-scale = <360>;
Jeremy Cline 36b34bf
+					regulator-always-on;
Jeremy Cline 36b34bf
+					regulator-boot-on;
Jeremy Cline 36b34bf
+
Jeremy Cline 36b34bf
+					maxim,active-fps-source = <MAX77620_FPS_SRC_0>;
Jeremy Cline 36b34bf
+					maxim,active-fps-power-up-slot = <3>;
Jeremy Cline 36b34bf
+					maxim,active-fps-power-down-slot = <4>;
Jeremy Cline 36b34bf
+				};
Jeremy Cline 36b34bf
+
Jeremy Cline 36b34bf
+				vdd_sys_1v2: ldo0 {
Jeremy Cline 36b34bf
+					regulator-name = "AVDD_SYS_1V2";
Jeremy Cline 36b34bf
+					regulator-min-microvolt = <1200000>;
Jeremy Cline 36b34bf
+					regulator-max-microvolt = <1200000>;
Jeremy Cline 36b34bf
+					regulator-enable-ramp-delay = <26>;
Jeremy Cline 36b34bf
+					regulator-disable-ramp-delay = <626>;
Jeremy Cline 36b34bf
+					regulator-ramp-delay = <100000>;
Jeremy Cline 36b34bf
+					regulator-ramp-delay-scale = <200>;
Jeremy Cline 36b34bf
+					regulator-always-on;
Jeremy Cline 36b34bf
+					regulator-boot-on;
Jeremy Cline 36b34bf
+
Jeremy Cline 36b34bf
+					maxim,active-fps-source = <MAX77620_FPS_SRC_NONE>;
Jeremy Cline 36b34bf
+					maxim,active-fps-power-up-slot = <0>;
Jeremy Cline 36b34bf
+					maxim,active-fps-power-down-slot = <7>;
Jeremy Cline 36b34bf
+				};
Jeremy Cline 36b34bf
+
Jeremy Cline 36b34bf
+				vdd_pex_1v05: ldo1 {
Jeremy Cline 36b34bf
+					regulator-name = "VDD_PEX_1V05";
Jeremy Cline 36b34bf
+					regulator-min-microvolt = <1050000>;
Jeremy Cline 36b34bf
+					regulator-max-microvolt = <1050000>;
Jeremy Cline 36b34bf
+					regulator-enable-ramp-delay = <22>;
Jeremy Cline 36b34bf
+					regulator-disable-ramp-delay = <650>;
Jeremy Cline 36b34bf
+					regulator-ramp-delay = <100000>;
Jeremy Cline 36b34bf
+					regulator-ramp-delay-scale = <200>;
Jeremy Cline 36b34bf
+
Jeremy Cline 36b34bf
+					maxim,active-fps-source = <MAX77620_FPS_SRC_NONE>;
Jeremy Cline 36b34bf
+					maxim,active-fps-power-up-slot = <0>;
Jeremy Cline 36b34bf
+					maxim,active-fps-power-down-slot = <7>;
Jeremy Cline 36b34bf
+				};
Jeremy Cline 36b34bf
+
Jeremy Cline 36b34bf
+				vddio_sdmmc: ldo2 {
Jeremy Cline 36b34bf
+					regulator-name = "VDDIO_SDMMC";
Jeremy Cline 36b34bf
+					regulator-min-microvolt = <1800000>;
Jeremy Cline 36b34bf
+					regulator-max-microvolt = <3300000>;
Jeremy Cline 36b34bf
+					regulator-enable-ramp-delay = <62>;
Jeremy Cline 36b34bf
+					regulator-disable-ramp-delay = <650>;
Jeremy Cline 36b34bf
+					regulator-ramp-delay = <100000>;
Jeremy Cline 36b34bf
+					regulator-ramp-delay-scale = <200>;
Jeremy Cline 36b34bf
+
Jeremy Cline 36b34bf
+					maxim,active-fps-source = <MAX77620_FPS_SRC_NONE>;
Jeremy Cline 36b34bf
+					maxim,active-fps-power-up-slot = <0>;
Jeremy Cline 36b34bf
+					maxim,active-fps-power-down-slot = <7>;
Jeremy Cline 36b34bf
+				};
Jeremy Cline 36b34bf
+
Jeremy Cline 36b34bf
+				ldo3 {
Jeremy Cline 36b34bf
+					status = "disabled";
Jeremy Cline 36b34bf
+				};
Jeremy Cline 36b34bf
+
Jeremy Cline 36b34bf
+				vdd_rtc: ldo4 {
Jeremy Cline 36b34bf
+					regulator-name = "VDD_RTC";
Jeremy Cline 36b34bf
+					regulator-min-microvolt = <850000>;
Jeremy Cline 36b34bf
+					regulator-max-microvolt = <1100000>;
Jeremy Cline 36b34bf
+					regulator-enable-ramp-delay = <22>;
Jeremy Cline 36b34bf
+					regulator-disable-ramp-delay = <610>;
Jeremy Cline 36b34bf
+					regulator-ramp-delay = <100000>;
Jeremy Cline 36b34bf
+					regulator-ramp-delay-scale = <200>;
Jeremy Cline 36b34bf
+					regulator-disable-active-discharge;
Jeremy Cline 36b34bf
+					regulator-always-on;
Jeremy Cline 36b34bf
+					regulator-boot-on;
Jeremy Cline 36b34bf
+
Jeremy Cline 36b34bf
+					maxim,active-fps-source = <MAX77620_FPS_SRC_0>;
Jeremy Cline 36b34bf
+					maxim,active-fps-power-up-slot = <1>;
Jeremy Cline 36b34bf
+					maxim,active-fps-power-down-slot = <6>;
Jeremy Cline 36b34bf
+				};
Jeremy Cline 36b34bf
+
Jeremy Cline 36b34bf
+				ldo5 {
Jeremy Cline 36b34bf
+					status = "disabled";
Jeremy Cline 36b34bf
+				};
Jeremy Cline 36b34bf
+
Jeremy Cline 36b34bf
+				ldo6 {
Jeremy Cline 36b34bf
+					status = "disabled";
Jeremy Cline 36b34bf
+				};
Jeremy Cline 36b34bf
+
Jeremy Cline 36b34bf
+				avdd_1v05_pll: ldo7 {
Jeremy Cline 36b34bf
+					regulator-name = "AVDD_1V05_PLL";
Jeremy Cline 36b34bf
+					regulator-min-microvolt = <1050000>;
Jeremy Cline 36b34bf
+					regulator-max-microvolt = <1050000>;
Jeremy Cline 36b34bf
+					regulator-enable-ramp-delay = <24>;
Jeremy Cline 36b34bf
+					regulator-disable-ramp-delay = <2768>;
Jeremy Cline 36b34bf
+					regulator-ramp-delay = <100000>;
Jeremy Cline 36b34bf
+					regulator-ramp-delay-scale = <200>;
Jeremy Cline 36b34bf
+
Jeremy Cline 36b34bf
+					maxim,active-fps-source = <MAX77620_FPS_SRC_1>;
Jeremy Cline 36b34bf
+					maxim,active-fps-power-up-slot = <3>;
Jeremy Cline 36b34bf
+					maxim,active-fps-power-down-slot = <4>;
Jeremy Cline 36b34bf
+				};
Jeremy Cline 36b34bf
+
Jeremy Cline 36b34bf
+				avdd_1v05: ldo8 {
Jeremy Cline 36b34bf
+					regulator-name = "AVDD_SATA_HDMI_DP_1V05";
Jeremy Cline 36b34bf
+					regulator-min-microvolt = <1050000>;
Jeremy Cline 36b34bf
+					regulator-max-microvolt = <1050000>;
Jeremy Cline 36b34bf
+					regulator-enable-ramp-delay = <22>;
Jeremy Cline 36b34bf
+					regulator-disable-ramp-delay = <1160>;
Jeremy Cline 36b34bf
+					regulator-ramp-delay = <100000>;
Jeremy Cline 36b34bf
+					regulator-ramp-delay-scale = <200>;
Jeremy Cline 36b34bf
+
Jeremy Cline 36b34bf
+					maxim,active-fps-source = <MAX77620_FPS_SRC_1>;
Jeremy Cline 36b34bf
+					maxim,active-fps-power-up-slot = <6>;
Jeremy Cline 36b34bf
+					maxim,active-fps-power-down-slot = <1>;
Jeremy Cline 36b34bf
+				};
Jeremy Cline 36b34bf
+			};
Jeremy Cline 36b34bf
+		};
Jeremy Cline 36b34bf
+	};
Jeremy Cline 36b34bf
+
Jeremy Cline 36b34bf
+	pmc@7000e400 {
Jeremy Cline 36b34bf
+		nvidia,invert-interrupt;
Jeremy Cline 36b34bf
+	};
Jeremy Cline 36b34bf
+
Jeremy Cline 36b34bf
+	hda@70030000 {
Jeremy Cline 36b34bf
+		status = "okay";
Jeremy Cline 36b34bf
+	};
Jeremy Cline 36b34bf
+
Jeremy Cline 36b34bf
+	usb@70090000 {
Jeremy Cline 36b34bf
+		phys = <&{/padctl@7009f000/pads/usb2/lanes/usb2-0}>,
Jeremy Cline 36b34bf
+		       <&{/padctl@7009f000/pads/usb2/lanes/usb2-1}>,
Jeremy Cline 36b34bf
+		       <&{/padctl@7009f000/pads/usb2/lanes/usb2-2}>,
Jeremy Cline 36b34bf
+		       <&{/padctl@7009f000/pads/pcie/lanes/pcie-6}>;
Jeremy Cline 36b34bf
+		phy-names = "usb2-0", "usb2-1", "usb2-2", "usb3-0";
Jeremy Cline 36b34bf
+
Jeremy Cline 36b34bf
+		avdd-usb-supply = <&vdd_3v3_sys>;
Jeremy Cline 36b34bf
+		dvddio-pex-supply = <&vdd_pex_1v05>;
Jeremy Cline 36b34bf
+		hvddio-pex-supply = <&vdd_1v8>;
Jeremy Cline 36b34bf
+
Jeremy Cline 36b34bf
+		status = "okay";
Jeremy Cline 36b34bf
+	};
Jeremy Cline 36b34bf
+
Jeremy Cline 36b34bf
+	padctl@7009f000 {
Jeremy Cline 36b34bf
+		status = "okay";
Jeremy Cline 36b34bf
+
Jeremy Cline 36b34bf
+		avdd-pll-utmip-supply = <&vdd_1v8>;
Jeremy Cline 36b34bf
+		avdd-pll-uerefe-supply = <&vdd_pex_1v05>;
Jeremy Cline 36b34bf
+		dvdd-pex-pll-supply = <&vdd_pex_1v05>;
Jeremy Cline 36b34bf
+		hvdd-pex-pll-e-supply = <&vdd_1v8>;
Jeremy Cline 36b34bf
+
Jeremy Cline 36b34bf
+		pads {
Jeremy Cline 36b34bf
+			usb2 {
Jeremy Cline 36b34bf
+				status = "okay";
Jeremy Cline 36b34bf
+
Jeremy Cline 36b34bf
+				lanes {
Jeremy Cline 36b34bf
+					usb2-0 {
Jeremy Cline 36b34bf
+						nvidia,function = "xusb";
Jeremy Cline 36b34bf
+						status = "okay";
Jeremy Cline 36b34bf
+					};
Jeremy Cline 36b34bf
+
Jeremy Cline 36b34bf
+					usb2-1 {
Jeremy Cline 36b34bf
+						nvidia,function = "xusb";
Jeremy Cline 36b34bf
+						status = "okay";
Jeremy Cline 36b34bf
+					};
Jeremy Cline 36b34bf
+
Jeremy Cline 36b34bf
+					usb2-2 {
Jeremy Cline 36b34bf
+						nvidia,function = "xusb";
Jeremy Cline 36b34bf
+						status = "okay";
Jeremy Cline 36b34bf
+					};
Jeremy Cline 36b34bf
+				};
Jeremy Cline 36b34bf
+			};
Jeremy Cline 36b34bf
+
Jeremy Cline 36b34bf
+			pcie {
Jeremy Cline 36b34bf
+				status = "okay";
Jeremy Cline 36b34bf
+
Jeremy Cline 36b34bf
+				lanes {
Jeremy Cline 36b34bf
+					pcie-0 {
Jeremy Cline 36b34bf
+						nvidia,function = "pcie-x1";
Jeremy Cline 36b34bf
+						status = "okay";
Jeremy Cline 36b34bf
+					};
Jeremy Cline 36b34bf
+
Jeremy Cline 36b34bf
+					pcie-1 {
Jeremy Cline 36b34bf
+						nvidia,function = "pcie-x4";
Jeremy Cline 36b34bf
+						status = "okay";
Jeremy Cline 36b34bf
+					};
Jeremy Cline 36b34bf
+
Jeremy Cline 36b34bf
+					pcie-2 {
Jeremy Cline 36b34bf
+						nvidia,function = "pcie-x4";
Jeremy Cline 36b34bf
+						status = "okay";
Jeremy Cline 36b34bf
+					};
Jeremy Cline 36b34bf
+
Jeremy Cline 36b34bf
+					pcie-3 {
Jeremy Cline 36b34bf
+						nvidia,function = "pcie-x4";
Jeremy Cline 36b34bf
+						status = "okay";
Jeremy Cline 36b34bf
+					};
Jeremy Cline 36b34bf
+
Jeremy Cline 36b34bf
+					pcie-4 {
Jeremy Cline 36b34bf
+						nvidia,function = "pcie-x4";
Jeremy Cline 36b34bf
+						status = "okay";
Jeremy Cline 36b34bf
+					};
Jeremy Cline 36b34bf
+
Jeremy Cline 36b34bf
+					pcie-5 {
Jeremy Cline 36b34bf
+						nvidia,function = "usb3-ss";
Jeremy Cline 36b34bf
+						status = "okay";
Jeremy Cline 36b34bf
+					};
Jeremy Cline 36b34bf
+
Jeremy Cline 36b34bf
+					pcie-6 {
Jeremy Cline 36b34bf
+						nvidia,function = "usb3-ss";
Jeremy Cline 36b34bf
+						status = "okay";
Jeremy Cline 36b34bf
+					};
Jeremy Cline 36b34bf
+				};
Jeremy Cline 36b34bf
+			};
Jeremy Cline 36b34bf
+		};
Jeremy Cline 36b34bf
+
Jeremy Cline 36b34bf
+		ports {
Jeremy Cline 36b34bf
+			usb2-0 {
Jeremy Cline 36b34bf
+				status = "okay";
Jeremy Cline 36b34bf
+				mode = "otg";
Jeremy Cline 36b34bf
+			};
Jeremy Cline 36b34bf
+
Jeremy Cline 36b34bf
+			usb2-1 {
Jeremy Cline 36b34bf
+				status = "okay";
Jeremy Cline 36b34bf
+				mode = "host";
Jeremy Cline 36b34bf
+			};
Jeremy Cline 36b34bf
+
Jeremy Cline 36b34bf
+			usb2-2 {
Jeremy Cline 36b34bf
+				status = "okay";
Jeremy Cline 36b34bf
+				mode = "host";
Jeremy Cline 36b34bf
+			};
Jeremy Cline 36b34bf
+
Jeremy Cline 36b34bf
+			usb3-0 {
Jeremy Cline 36b34bf
+				status = "okay";
Jeremy Cline 36b34bf
+				nvidia,usb2-companion = <1>;
Jeremy Cline 36b34bf
+				vbus-supply = <&vdd_hub_3v3>;
Jeremy Cline 36b34bf
+			};
Jeremy Cline 36b34bf
+		};
Jeremy Cline 36b34bf
+	};
Jeremy Cline 36b34bf
+
Jeremy Cline 36b34bf
+	sdhci@700b0000 {
Jeremy Cline 36b34bf
+		status = "okay";
Jeremy Cline 36b34bf
+		bus-width = <4>;
Jeremy Cline 36b34bf
+
Jeremy Cline 36b34bf
+		cd-gpios = <&gpio TEGRA_GPIO(Z, 1) GPIO_ACTIVE_LOW>;
Jeremy Cline 36b34bf
+
Jeremy Cline 36b34bf
+		vqmmc-supply = <&vddio_sdmmc>;
Jeremy Cline 36b34bf
+		vmmc-supply = <&vdd_3v3_sd>;
Jeremy Cline 36b34bf
+	};
Jeremy Cline 36b34bf
+
Jeremy Cline 36b34bf
+	clocks {
Jeremy Cline 36b34bf
+		compatible = "simple-bus";
Jeremy Cline 36b34bf
+		#address-cells = <1>;
Jeremy Cline 36b34bf
+		#size-cells = <0>;
Jeremy Cline 36b34bf
+
Jeremy Cline 36b34bf
+		clk32k_in: clock@0 {
Jeremy Cline 36b34bf
+			compatible = "fixed-clock";
Jeremy Cline 36b34bf
+			reg = <0>;
Jeremy Cline 36b34bf
+			#clock-cells = <0>;
Jeremy Cline 36b34bf
+			clock-frequency = <32768>;
Jeremy Cline 36b34bf
+		};
Jeremy Cline 36b34bf
+	};
Jeremy Cline 36b34bf
+
Jeremy Cline 36b34bf
+	cpus {
Jeremy Cline 36b34bf
+		cpu@0 {
Jeremy Cline 36b34bf
+			enable-method = "psci";
Jeremy Cline 36b34bf
+		};
Jeremy Cline 36b34bf
+
Jeremy Cline 36b34bf
+		cpu@1 {
Jeremy Cline 36b34bf
+			enable-method = "psci";
Jeremy Cline 36b34bf
+		};
Jeremy Cline 36b34bf
+
Jeremy Cline 36b34bf
+		cpu@2 {
Jeremy Cline 36b34bf
+			enable-method = "psci";
Jeremy Cline 36b34bf
+		};
Jeremy Cline 36b34bf
+
Jeremy Cline 36b34bf
+		cpu@3 {
Jeremy Cline 36b34bf
+			enable-method = "psci";
Jeremy Cline 36b34bf
+		};
Jeremy Cline 36b34bf
+	};
Jeremy Cline 36b34bf
+
Jeremy Cline 36b34bf
+	gpio-keys {
Jeremy Cline 36b34bf
+		compatible = "gpio-keys";
Jeremy Cline 36b34bf
+
Jeremy Cline 36b34bf
+		power {
Jeremy Cline 36b34bf
+			label = "Power";
Jeremy Cline 36b34bf
+			gpios = <&gpio TEGRA_GPIO(X, 5) GPIO_ACTIVE_LOW>;
Jeremy Cline 36b34bf
+			linux,input-type = <EV_KEY>;
Jeremy Cline 36b34bf
+			linux,code = <KEY_POWER>;
Jeremy Cline 36b34bf
+			debounce-interval = <30>;
Jeremy Cline 36b34bf
+			wakeup-event-action = <EV_ACT_ASSERTED>;
Jeremy Cline 36b34bf
+			wakeup-source;
Jeremy Cline 36b34bf
+		};
Jeremy Cline 36b34bf
+
Jeremy Cline 36b34bf
+		force-recovery {
Jeremy Cline 36b34bf
+			label = "Force Recovery";
Jeremy Cline 36b34bf
+			gpios = <&gpio TEGRA_GPIO(X, 6) GPIO_ACTIVE_LOW>;
Jeremy Cline 36b34bf
+			linux,input-type = <EV_KEY>;
Jeremy Cline 36b34bf
+			linux,code = <BTN_1>;
Jeremy Cline 36b34bf
+			debounce-interval = <30>;
Jeremy Cline 36b34bf
+		};
Jeremy Cline 36b34bf
+	};
Jeremy Cline 36b34bf
+
Jeremy Cline 36b34bf
+	psci {
Jeremy Cline 36b34bf
+		compatible = "arm,psci-1.0";
Jeremy Cline 36b34bf
+		method = "smc";
Jeremy Cline 36b34bf
+	};
Jeremy Cline 36b34bf
+
Jeremy Cline 36b34bf
+	regulators {
Jeremy Cline 36b34bf
+		compatible = "simple-bus";
Jeremy Cline 36b34bf
+		#address-cells = <1>;
Jeremy Cline 36b34bf
+		#size-cells = <0>;
Jeremy Cline 36b34bf
+
Jeremy Cline 36b34bf
+		vdd_5v0_sys: regulator@0 {
Jeremy Cline 36b34bf
+			compatible = "regulator-fixed";
Jeremy Cline 36b34bf
+			reg = <0>;
Jeremy Cline 36b34bf
+
Jeremy Cline 36b34bf
+			regulator-name = "VDD_5V0_SYS";
Jeremy Cline 36b34bf
+			regulator-min-microvolt = <5000000>;
Jeremy Cline 36b34bf
+			regulator-max-microvolt = <5000000>;
Jeremy Cline 36b34bf
+			regulator-always-on;
Jeremy Cline 36b34bf
+			regulator-boot-on;
Jeremy Cline 36b34bf
+		};
Jeremy Cline 36b34bf
+
Jeremy Cline 36b34bf
+		vdd_3v3_sys: regulator@1 {
Jeremy Cline 36b34bf
+			compatible = "regulator-fixed";
Jeremy Cline 36b34bf
+			reg = <1>;
Jeremy Cline 36b34bf
+			regulator-name = "VDD_3V3_SYS";
Jeremy Cline 36b34bf
+			regulator-min-microvolt = <3300000>;
Jeremy Cline 36b34bf
+			regulator-max-microvolt = <3300000>;
Jeremy Cline 36b34bf
+			regulator-enable-ramp-delay = <240>;
Jeremy Cline 36b34bf
+			regulator-disable-ramp-delay = <11340>;
Jeremy Cline 36b34bf
+			regulator-always-on;
Jeremy Cline 36b34bf
+			regulator-boot-on;
Jeremy Cline 36b34bf
+
Jeremy Cline 36b34bf
+			gpio = <&pmic 3 GPIO_ACTIVE_HIGH>;
Jeremy Cline 36b34bf
+			enable-active-high;
Jeremy Cline 36b34bf
+
Jeremy Cline 36b34bf
+			vin-supply = <&vdd_5v0_sys>;
Jeremy Cline 36b34bf
+		};
Jeremy Cline 36b34bf
+
Jeremy Cline 36b34bf
+		vdd_3v3_sd: regulator@2 {
Jeremy Cline 36b34bf
+			compatible = "regulator-fixed";
Jeremy Cline 36b34bf
+			reg = <2>;
Jeremy Cline 36b34bf
+
Jeremy Cline 36b34bf
+			regulator-name = "VDD_3V3_SD";
Jeremy Cline 36b34bf
+			regulator-min-microvolt = <3300000>;
Jeremy Cline 36b34bf
+			regulator-max-microvolt = <3300000>;
Jeremy Cline 36b34bf
+
Jeremy Cline 36b34bf
+			gpio = <&gpio TEGRA_GPIO(Z, 3) GPIO_ACTIVE_HIGH>;
Jeremy Cline 36b34bf
+			enable-active-high;
Jeremy Cline 36b34bf
+
Jeremy Cline 36b34bf
+			vin-supply = <&vdd_3v3_sys>;
Jeremy Cline 36b34bf
+		};
Jeremy Cline 36b34bf
+
Jeremy Cline 36b34bf
+		vdd_hdmi: regulator@3 {
Jeremy Cline 36b34bf
+			compatible = "regulator-fixed";
Jeremy Cline 36b34bf
+			reg = <3>;
Jeremy Cline 36b34bf
+
Jeremy Cline 36b34bf
+			regulator-name = "VDD_HDMI_5V0";
Jeremy Cline 36b34bf
+			regulator-min-microvolt = <5000000>;
Jeremy Cline 36b34bf
+			regulator-max-microvolt = <5000000>;
Jeremy Cline 36b34bf
+
Jeremy Cline 36b34bf
+			vin-supply = <&vdd_5v0_sys>;
Jeremy Cline 36b34bf
+		};
Jeremy Cline 36b34bf
+
Jeremy Cline 36b34bf
+		vdd_hub_3v3: regulator@4 {
Jeremy Cline 36b34bf
+			compatible = "regulator-fixed";
Jeremy Cline 36b34bf
+			reg = <4>;
Jeremy Cline 36b34bf
+
Jeremy Cline 36b34bf
+			regulator-name = "VDD_HUB_3V3";
Jeremy Cline 36b34bf
+			regulator-min-microvolt = <3300000>;
Jeremy Cline 36b34bf
+			regulator-max-microvolt = <3300000>;
Jeremy Cline 36b34bf
+
Jeremy Cline 36b34bf
+			gpio = <&gpio TEGRA_GPIO(A, 6) GPIO_ACTIVE_HIGH>;
Jeremy Cline 36b34bf
+			enable-active-high;
Jeremy Cline 36b34bf
+
Jeremy Cline 36b34bf
+			vin-supply = <&vdd_5v0_sys>;
Jeremy Cline 36b34bf
+		};
Jeremy Cline 36b34bf
+
Jeremy Cline 36b34bf
+		vdd_cpu: regulator@5 {
Jeremy Cline 36b34bf
+			compatible = "regulator-fixed";
Jeremy Cline 36b34bf
+			reg = <5>;
Jeremy Cline 36b34bf
+
Jeremy Cline 36b34bf
+			regulator-name = "VDD_CPU";
Jeremy Cline 36b34bf
+			regulator-min-microvolt = <5000000>;
Jeremy Cline 36b34bf
+			regulator-max-microvolt = <5000000>;
Jeremy Cline 36b34bf
+			regulator-always-on;
Jeremy Cline 36b34bf
+			regulator-boot-on;
Jeremy Cline 36b34bf
+
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+			gpio = <&pmic 5 GPIO_ACTIVE_HIGH>;
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+			enable-active-high;
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+
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+			vin-supply = <&vdd_5v0_sys>;
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+		};
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+
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+		vdd_gpu: regulator@6 {
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+			compatible = "regulator-fixed";
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+			reg = <6>;
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+
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+			regulator-name = "VDD_GPU";
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+			regulator-min-microvolt = <5000000>;
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+			regulator-max-microvolt = <5000000>;
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+			regulator-enable-ramp-delay = <250>;
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+
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+			gpio = <&pmic 6 GPIO_ACTIVE_HIGH>;
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+			enable-active-high;
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+
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+			vin-supply = <&vdd_5v0_sys>;
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+		};
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+	};
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+};