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upstream commit 944001201ca0196bcdb088129e5866a9f379d08c
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(plus some defines)
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[2.6.32 backport]
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diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
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index 0d05c6f..b87f65d 100644
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--- a/drivers/gpu/drm/i915/i915_gem.c
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+++ b/drivers/gpu/drm/i915/i915_gem.c
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@@ -4967,6 +4967,16 @@ i915_gem_load(struct drm_device *dev)
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 	list_add(&dev_priv->mm.shrink_list, &shrink_list);
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 	spin_unlock(&shrink_list_lock);
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+	/* On GEN3 we really need to make sure the ARB C3 LP bit is set */
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+	if (IS_GEN3(dev)) {
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+		u32 tmp = I915_READ(MI_ARB_STATE);
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+		if (!(tmp & MI_ARB_C3_LP_WRITE_ENABLE)) {
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+			/* arb state is a masked write, so set bit + bit in mask */
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+			tmp = MI_ARB_C3_LP_WRITE_ENABLE | (MI_ARB_C3_LP_WRITE_ENABLE << MI_ARB_MASK_SHIFT);
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+			I915_WRITE(MI_ARB_STATE, tmp);
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+		}
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+	}
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+
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 	/* Old X drivers will take 0-2 for front, back, depth buffers */
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 	dev_priv->fence_reg_start = 3;
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diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
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index 4cbc521..4543975 100644
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--- a/drivers/gpu/drm/i915/i915_reg.h
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+++ b/drivers/gpu/drm/i915/i915_reg.h
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@@ -357,6 +357,70 @@
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 #define LM_BURST_LENGTH     0x00000700
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 #define LM_FIFO_WATERMARK   0x0000001F
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 #define MI_ARB_STATE	0x020e4 /* 915+ only */
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+#define   MI_ARB_MASK_SHIFT	  16	/* shift for enable bits */
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+
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+/* Make render/texture TLB fetches lower priorty than associated data
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+ *   fetches. This is not turned on by default
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+ */
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+#define   MI_ARB_RENDER_TLB_LOW_PRIORITY	(1 << 15)
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+
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+/* Isoch request wait on GTT enable (Display A/B/C streams).
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+ * Make isoch requests stall on the TLB update. May cause
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+ * display underruns (test mode only)
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+ */
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+#define   MI_ARB_ISOCH_WAIT_GTT			(1 << 14)
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+
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+/* Block grant count for isoch requests when block count is
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+ * set to a finite value.
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+ */
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+#define   MI_ARB_BLOCK_GRANT_MASK		(3 << 12)
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+#define   MI_ARB_BLOCK_GRANT_8			(0 << 12)	/* for 3 display planes */
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+#define   MI_ARB_BLOCK_GRANT_4			(1 << 12)	/* for 2 display planes */
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+#define   MI_ARB_BLOCK_GRANT_2			(2 << 12)	/* for 1 display plane */
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+#define   MI_ARB_BLOCK_GRANT_0			(3 << 12)	/* don't use */
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+
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+/* Enable render writes to complete in C2/C3/C4 power states.
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+ * If this isn't enabled, render writes are prevented in low
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+ * power states. That seems bad to me.
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+ */
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+#define   MI_ARB_C3_LP_WRITE_ENABLE		(1 << 11)
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+
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+/* This acknowledges an async flip immediately instead
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+ * of waiting for 2TLB fetches.
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+ */
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+#define   MI_ARB_ASYNC_FLIP_ACK_IMMEDIATE	(1 << 10)
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+
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+/* Enables non-sequential data reads through arbiter
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+ */
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+#define   MI_ARB_DUAL_DATA_PHASE_DISABLE       	(1 << 9)
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+
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+/* Disable FSB snooping of cacheable write cycles from binner/render
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+ * command stream
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+ */
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+#define   MI_ARB_CACHE_SNOOP_DISABLE		(1 << 8)
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+
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+/* Arbiter time slice for non-isoch streams */
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+#define   MI_ARB_TIME_SLICE_MASK		(7 << 5)
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+#define   MI_ARB_TIME_SLICE_1			(0 << 5)
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+#define   MI_ARB_TIME_SLICE_2			(1 << 5)
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+#define   MI_ARB_TIME_SLICE_4			(2 << 5)
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+#define   MI_ARB_TIME_SLICE_6			(3 << 5)
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+#define   MI_ARB_TIME_SLICE_8			(4 << 5)
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+#define   MI_ARB_TIME_SLICE_10			(5 << 5)
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+#define   MI_ARB_TIME_SLICE_14			(6 << 5)
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+#define   MI_ARB_TIME_SLICE_16			(7 << 5)
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+
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+/* Low priority grace period page size */
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+#define   MI_ARB_LOW_PRIORITY_GRACE_4KB		(0 << 4)	/* default */
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+#define   MI_ARB_LOW_PRIORITY_GRACE_8KB		(1 << 4)
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+
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+/* Disable display A/B trickle feed */
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+#define   MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE	(1 << 2)
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+
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+/* Set display plane priority */
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+#define   MI_ARB_DISPLAY_PRIORITY_A_B		(0 << 0)	/* display A > display B */
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+#define   MI_ARB_DISPLAY_PRIORITY_B_A		(1 << 0)	/* display B > display A */
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+
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 #define CACHE_MODE_0	0x02120 /* 915+ only */
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 #define   CM0_MASK_SHIFT          16
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 #define   CM0_IZ_OPT_DISABLE      (1<<6)
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--- a/drivers/gpu/drm/i915/i915_drv.h
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+++ b/drivers/gpu/drm/i915/i915_drv.h
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@@ -1045,6 +1045,13 @@ extern int i915_wait_ring(struct drm_dev
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 #define IS_I9XX(dev)		(INTEL_INFO(dev)->is_i9xx)
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 #define IS_MOBILE(dev)		(INTEL_INFO(dev)->is_mobile)
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+#define IS_GEN3(dev)	(IS_I915G(dev) ||			\
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+			 IS_I915GM(dev) ||			\
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+			 IS_I945G(dev) ||			\
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+			 IS_I945GM(dev) ||			\
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+			 IS_G33(dev) || \
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+			 IS_PINEVIEW(dev))
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+
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 #define I915_NEED_GFX_HWS(dev)	(INTEL_INFO(dev)->need_gfx_hws)
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 /* With the 945 and later, Y tiling got adjusted so that it was 32 128-byte
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--