upstream commit 944001201ca0196bcdb088129e5866a9f379d08c

(plus some defines)

[2.6.32 backport]

diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c

index 0d05c6f..b87f65d 100644

--- a/drivers/gpu/drm/i915/i915_gem.c

+++ b/drivers/gpu/drm/i915/i915_gem.c

@@ -4967,6 +4967,16 @@ i915_gem_load(struct drm_device *dev)

 	list_add(&dev_priv->mm.shrink_list, &shrink_list);

 	spin_unlock(&shrink_list_lock);

+	/* On GEN3 we really need to make sure the ARB C3 LP bit is set */

+	if (IS_GEN3(dev)) {

+		u32 tmp = I915_READ(MI_ARB_STATE);

+		if (!(tmp & MI_ARB_C3_LP_WRITE_ENABLE)) {

+			/* arb state is a masked write, so set bit + bit in mask */

+			tmp = MI_ARB_C3_LP_WRITE_ENABLE | (MI_ARB_C3_LP_WRITE_ENABLE << MI_ARB_MASK_SHIFT);

+			I915_WRITE(MI_ARB_STATE, tmp);

+		}

+	}

+

 	/* Old X drivers will take 0-2 for front, back, depth buffers */

 	dev_priv->fence_reg_start = 3;

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h

index 4cbc521..4543975 100644

--- a/drivers/gpu/drm/i915/i915_reg.h

+++ b/drivers/gpu/drm/i915/i915_reg.h

@@ -357,6 +357,70 @@

 #define LM_BURST_LENGTH     0x00000700

 #define LM_FIFO_WATERMARK   0x0000001F

 #define MI_ARB_STATE	0x020e4 /* 915+ only */

+#define   MI_ARB_MASK_SHIFT	  16	/* shift for enable bits */

+

+/* Make render/texture TLB fetches lower priorty than associated data

+ *   fetches. This is not turned on by default

+ */

+#define   MI_ARB_RENDER_TLB_LOW_PRIORITY	(1 << 15)

+

+/* Isoch request wait on GTT enable (Display A/B/C streams).

+ * Make isoch requests stall on the TLB update. May cause

+ * display underruns (test mode only)

+ */

+#define   MI_ARB_ISOCH_WAIT_GTT			(1 << 14)

+

+/* Block grant count for isoch requests when block count is

+ * set to a finite value.

+ */

+#define   MI_ARB_BLOCK_GRANT_MASK		(3 << 12)

+#define   MI_ARB_BLOCK_GRANT_8			(0 << 12)	/* for 3 display planes */

+#define   MI_ARB_BLOCK_GRANT_4			(1 << 12)	/* for 2 display planes */

+#define   MI_ARB_BLOCK_GRANT_2			(2 << 12)	/* for 1 display plane */

+#define   MI_ARB_BLOCK_GRANT_0			(3 << 12)	/* don't use */

+

+/* Enable render writes to complete in C2/C3/C4 power states.

+ * If this isn't enabled, render writes are prevented in low

+ * power states. That seems bad to me.

+ */

+#define   MI_ARB_C3_LP_WRITE_ENABLE		(1 << 11)

+

+/* This acknowledges an async flip immediately instead

+ * of waiting for 2TLB fetches.

+ */

+#define   MI_ARB_ASYNC_FLIP_ACK_IMMEDIATE	(1 << 10)

+

+/* Enables non-sequential data reads through arbiter

+ */

+#define   MI_ARB_DUAL_DATA_PHASE_DISABLE       	(1 << 9)

+

+/* Disable FSB snooping of cacheable write cycles from binner/render

+ * command stream

+ */

+#define   MI_ARB_CACHE_SNOOP_DISABLE		(1 << 8)

+

+/* Arbiter time slice for non-isoch streams */

+#define   MI_ARB_TIME_SLICE_MASK		(7 << 5)

+#define   MI_ARB_TIME_SLICE_1			(0 << 5)

+#define   MI_ARB_TIME_SLICE_2			(1 << 5)

+#define   MI_ARB_TIME_SLICE_4			(2 << 5)

+#define   MI_ARB_TIME_SLICE_6			(3 << 5)

+#define   MI_ARB_TIME_SLICE_8			(4 << 5)

+#define   MI_ARB_TIME_SLICE_10			(5 << 5)

+#define   MI_ARB_TIME_SLICE_14			(6 << 5)

+#define   MI_ARB_TIME_SLICE_16			(7 << 5)

+

+/* Low priority grace period page size */

+#define   MI_ARB_LOW_PRIORITY_GRACE_4KB		(0 << 4)	/* default */

+#define   MI_ARB_LOW_PRIORITY_GRACE_8KB		(1 << 4)

+

+/* Disable display A/B trickle feed */

+#define   MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE	(1 << 2)

+

+/* Set display plane priority */

+#define   MI_ARB_DISPLAY_PRIORITY_A_B		(0 << 0)	/* display A > display B */

+#define   MI_ARB_DISPLAY_PRIORITY_B_A		(1 << 0)	/* display B > display A */

+

 #define CACHE_MODE_0	0x02120 /* 915+ only */

 #define   CM0_MASK_SHIFT          16

 #define   CM0_IZ_OPT_DISABLE      (1<<6)

--- a/drivers/gpu/drm/i915/i915_drv.h

+++ b/drivers/gpu/drm/i915/i915_drv.h

@@ -1045,6 +1045,13 @@ extern int i915_wait_ring(struct drm_dev

 #define IS_I9XX(dev)		(INTEL_INFO(dev)->is_i9xx)

 #define IS_MOBILE(dev)		(INTEL_INFO(dev)->is_mobile)

+#define IS_GEN3(dev)	(IS_I915G(dev) ||			\

+			 IS_I915GM(dev) ||			\

+			 IS_I945G(dev) ||			\

+			 IS_I945GM(dev) ||			\

+			 IS_G33(dev) || \

+			 IS_PINEVIEW(dev))

+

 #define I915_NEED_GFX_HWS(dev)	(INTEL_INFO(dev)->need_gfx_hws)

 /* With the 945 and later, Y tiling got adjusted so that it was 32 128-byte

--