Jesse Keating 2f82dd
diff --git a/drivers/gpu/drm/nouveau/nouveau_drv.h b/drivers/gpu/drm/nouveau/nouveau_drv.h
Jesse Keating 2f82dd
index 5445cef..1c15ef3 100644
Jesse Keating 2f82dd
--- a/drivers/gpu/drm/nouveau/nouveau_drv.h
Jesse Keating 2f82dd
+++ b/drivers/gpu/drm/nouveau/nouveau_drv.h
Jesse Keating 2f82dd
@@ -583,6 +583,7 @@ struct drm_nouveau_private {
Jesse Keating 2f82dd
 	uint64_t vm_end;
Jesse Keating 2f82dd
 	struct nouveau_gpuobj *vm_vram_pt[NV50_VM_VRAM_NR];
Jesse Keating 2f82dd
 	int vm_vram_pt_nr;
Jesse Keating 2f82dd
+	uint64_t vram_sys_base;
Jesse Keating 2f82dd
 
Jesse Keating 2f82dd
 	/* the mtrr covering the FB */
Jesse Keating 2f82dd
 	int fb_mtrr;
Jesse Keating 2f82dd
diff --git a/drivers/gpu/drm/nouveau/nouveau_mem.c b/drivers/gpu/drm/nouveau/nouveau_mem.c
Jesse Keating 2f82dd
index 8f3a12f..2dc09db 100644
Jesse Keating 2f82dd
--- a/drivers/gpu/drm/nouveau/nouveau_mem.c
Jesse Keating 2f82dd
+++ b/drivers/gpu/drm/nouveau/nouveau_mem.c
Jesse Keating 2f82dd
@@ -285,53 +285,50 @@ nv50_mem_vm_bind_linear(struct drm_device *dev, uint64_t virt, uint32_t size,
Jesse Keating 2f82dd
 			uint32_t flags, uint64_t phys)
Jesse Keating 2f82dd
 {
Jesse Keating 2f82dd
 	struct drm_nouveau_private *dev_priv = dev->dev_private;
Jesse Keating 2f82dd
-	struct nouveau_gpuobj **pgt;
Jesse Keating 2f82dd
-	unsigned psz, pfl, pages;
Jesse Keating 2f82dd
-
Jesse Keating 2f82dd
-	if (virt >= dev_priv->vm_gart_base &&
Jesse Keating 2f82dd
-	    (virt + size) < (dev_priv->vm_gart_base + dev_priv->vm_gart_size)) {
Jesse Keating 2f82dd
-		psz = 12;
Jesse Keating 2f82dd
-		pgt = &dev_priv->gart_info.sg_ctxdma;
Jesse Keating 2f82dd
-		pfl = 0x21;
Jesse Keating 2f82dd
-		virt -= dev_priv->vm_gart_base;
Jesse Keating 2f82dd
-	} else
Jesse Keating 2f82dd
-	if (virt >= dev_priv->vm_vram_base &&
Jesse Keating 2f82dd
-	    (virt + size) < (dev_priv->vm_vram_base + dev_priv->vm_vram_size)) {
Jesse Keating 2f82dd
-		psz = 16;
Jesse Keating 2f82dd
-		pgt = dev_priv->vm_vram_pt;
Jesse Keating 2f82dd
-		pfl = 0x01;
Jesse Keating 2f82dd
-		virt -= dev_priv->vm_vram_base;
Jesse Keating 2f82dd
-	} else {
Jesse Keating 2f82dd
-		NV_ERROR(dev, "Invalid address: 0x%16llx-0x%16llx\n",
Jesse Keating 2f82dd
-			 virt, virt + size - 1);
Jesse Keating 2f82dd
-		return -EINVAL;
Jesse Keating 2f82dd
-	}
Jesse Keating 2f82dd
+	struct nouveau_gpuobj *pgt;
Jesse Keating 2f82dd
+	unsigned block;
Jesse Keating 2f82dd
+	int i;
Jesse Keating 2f82dd
 
Jesse Keating 2f82dd
-	pages = size >> psz;
Jesse Keating 2f82dd
+	virt = ((virt - dev_priv->vm_vram_base) >> 16) << 1;
Jesse Keating 2f82dd
+	size = (size >> 16) << 1;
Jesse Keating 2f82dd
+
Jesse Keating 2f82dd
+	phys |= ((uint64_t)flags << 32);
Jesse Keating 2f82dd
+	phys |= 1;
Jesse Keating 2f82dd
+	if (dev_priv->vram_sys_base) {
Jesse Keating 2f82dd
+		phys += dev_priv->vram_sys_base;
Jesse Keating 2f82dd
+		phys |= 0x30;
Jesse Keating 2f82dd
+	}
Jesse Keating 2f82dd
 
Jesse Keating 2f82dd
 	dev_priv->engine.instmem.prepare_access(dev, true);
Jesse Keating 2f82dd
-	if (flags & 0x80000000) {
Jesse Keating 2f82dd
-		while (pages--) {
Jesse Keating 2f82dd
-			struct nouveau_gpuobj *pt = pgt[virt >> 29];
Jesse Keating 2f82dd
-			unsigned pte = ((virt & 0x1fffffffULL) >> psz) << 1;
Jesse Keating 2f82dd
+	while (size) {
Jesse Keating 2f82dd
+		unsigned offset_h = upper_32_bits(phys);
Jesse Keating 2f82dd
+		unsigned offset_l = lower_32_bits(phys);
Jesse Keating 2f82dd
+		unsigned pte, end;
Jesse Keating 2f82dd
+
Jesse Keating 2f82dd
+		for (i = 7; i >= 0; i--) {
Jesse Keating 2f82dd
+			block = 1 << (i + 1);
Jesse Keating 2f82dd
+			if (size >= block && !(virt & (block - 1)))
Jesse Keating 2f82dd
+				break;
Jesse Keating 2f82dd
+		}
Jesse Keating 2f82dd
+		offset_l |= (i << 7);
Jesse Keating 2f82dd
 
Jesse Keating 2f82dd
-			nv_wo32(dev, pt, pte++, 0x00000000);
Jesse Keating 2f82dd
-			nv_wo32(dev, pt, pte++, 0x00000000);
Jesse Keating 2f82dd
+		phys += block << 15;
Jesse Keating 2f82dd
+		size -= block;
Jesse Keating 2f82dd
 
Jesse Keating 2f82dd
-			virt += (1 << psz);
Jesse Keating 2f82dd
-		}
Jesse Keating 2f82dd
-	} else {
Jesse Keating 2f82dd
-		while (pages--) {
Jesse Keating 2f82dd
-			struct nouveau_gpuobj *pt = pgt[virt >> 29];
Jesse Keating 2f82dd
-			unsigned pte = ((virt & 0x1fffffffULL) >> psz) << 1;
Jesse Keating 2f82dd
-			unsigned offset_h = upper_32_bits(phys) & 0xff;
Jesse Keating 2f82dd
-			unsigned offset_l = lower_32_bits(phys);
Jesse Keating 2f82dd
+		while (block) {
Jesse Keating 2f82dd
+			pgt = dev_priv->vm_vram_pt[virt >> 14];
Jesse Keating 2f82dd
+			pte = virt & 0x3ffe;
Jesse Keating 2f82dd
 
Jesse Keating 2f82dd
-			nv_wo32(dev, pt, pte++, offset_l | pfl);
Jesse Keating 2f82dd
-			nv_wo32(dev, pt, pte++, offset_h | flags);
Jesse Keating 2f82dd
+			end = pte + block;
Jesse Keating 2f82dd
+			if (end > 16384)
Jesse Keating 2f82dd
+				end = 16384;
Jesse Keating 2f82dd
+			block -= (end - pte);
Jesse Keating 2f82dd
+			virt  += (end - pte);
Jesse Keating 2f82dd
 
Jesse Keating 2f82dd
-			phys += (1 << psz);
Jesse Keating 2f82dd
-			virt += (1 << psz);
Jesse Keating 2f82dd
+			while (pte < end) {
Jesse Keating 2f82dd
+				nv_wo32(dev, pgt, pte++, offset_l);
Jesse Keating 2f82dd
+				nv_wo32(dev, pgt, pte++, offset_h);
Jesse Keating 2f82dd
+			}
Jesse Keating 2f82dd
 		}
Jesse Keating 2f82dd
 	}
Jesse Keating 2f82dd
 	dev_priv->engine.instmem.finish_access(dev);
Jesse Keating 2f82dd
@@ -356,7 +353,41 @@ nv50_mem_vm_bind_linear(struct drm_device *dev, uint64_t virt, uint32_t size,
Jesse Keating 2f82dd
 void
Jesse Keating 2f82dd
 nv50_mem_vm_unbind(struct drm_device *dev, uint64_t virt, uint32_t size)
Jesse Keating 2f82dd
 {
Jesse Keating 2f82dd
-	nv50_mem_vm_bind_linear(dev, virt, size, 0x80000000, 0);
Jesse Keating 2f82dd
+	struct drm_nouveau_private *dev_priv = dev->dev_private;
Jesse Keating 2f82dd
+	struct nouveau_gpuobj *pgt;
Jesse Keating 2f82dd
+	unsigned pages, pte, end;
Jesse Keating 2f82dd
+
Jesse Keating 2f82dd
+	virt -= dev_priv->vm_vram_base;
Jesse Keating 2f82dd
+	pages = (size >> 16) << 1;
Jesse Keating 2f82dd
+
Jesse Keating 2f82dd
+	dev_priv->engine.instmem.prepare_access(dev, true);
Jesse Keating 2f82dd
+	while (pages) {
Jesse Keating 2f82dd
+		pgt = dev_priv->vm_vram_pt[virt >> 29];
Jesse Keating 2f82dd
+		pte = (virt & 0x1ffe0000ULL) >> 15;
Jesse Keating 2f82dd
+
Jesse Keating 2f82dd
+		end = pte + pages;
Jesse Keating 2f82dd
+		if (end > 16384)
Jesse Keating 2f82dd
+			end = 16384;
Jesse Keating 2f82dd
+		pages -= (end - pte);
Jesse Keating 2f82dd
+		virt  += (end - pte) << 15;
Jesse Keating 2f82dd
+
Jesse Keating 2f82dd
+		while (pte < end)
Jesse Keating 2f82dd
+			nv_wo32(dev, pgt, pte++, 0);
Jesse Keating 2f82dd
+	}
Jesse Keating 2f82dd
+	dev_priv->engine.instmem.finish_access(dev);
Jesse Keating 2f82dd
+
Jesse Keating 2f82dd
+	nv_wr32(dev, 0x100c80, 0x00050001);
Jesse Keating 2f82dd
+	if (!nv_wait(0x100c80, 0x00000001, 0x00000000)) {
Jesse Keating 2f82dd
+		NV_ERROR(dev, "timeout: (0x100c80 & 1) == 0 (2)\n");
Jesse Keating 2f82dd
+		NV_ERROR(dev, "0x100c80 = 0x%08x\n", nv_rd32(dev, 0x100c80));
Jesse Keating 2f82dd
+		return;
Jesse Keating 2f82dd
+	}
Jesse Keating 2f82dd
+
Jesse Keating 2f82dd
+	nv_wr32(dev, 0x100c80, 0x00000001);
Jesse Keating 2f82dd
+	if (!nv_wait(0x100c80, 0x00000001, 0x00000000)) {
Jesse Keating 2f82dd
+		NV_ERROR(dev, "timeout: (0x100c80 & 1) == 0 (2)\n");
Jesse Keating 2f82dd
+		NV_ERROR(dev, "0x100c80 = 0x%08x\n", nv_rd32(dev, 0x100c80));
Jesse Keating 2f82dd
+	}
Jesse Keating 2f82dd
 }
Jesse Keating 2f82dd
 
Jesse Keating 2f82dd
 /*
Jesse Keating 2f82dd
diff --git a/drivers/gpu/drm/nouveau/nv04_dac.c b/drivers/gpu/drm/nouveau/nv04_dac.c
Jesse Keating 2f82dd
index d0e038d..1d73b15 100644
Jesse Keating 2f82dd
--- a/drivers/gpu/drm/nouveau/nv04_dac.c
Jesse Keating 2f82dd
+++ b/drivers/gpu/drm/nouveau/nv04_dac.c
Jesse Keating 2f82dd
@@ -119,7 +119,7 @@ static enum drm_connector_status nv04_dac_detect(struct drm_encoder *encoder,
Jesse Keating 2f82dd
 						 struct drm_connector *connector)
Jesse Keating 2f82dd
 {
Jesse Keating 2f82dd
 	struct drm_device *dev = encoder->dev;
Jesse Keating 2f82dd
-	uint8_t saved_seq1, saved_pi, saved_rpc1;
Jesse Keating 2f82dd
+	uint8_t saved_seq1, saved_pi, saved_rpc1, saved_cr_mode;
Jesse Keating 2f82dd
 	uint8_t saved_palette0[3], saved_palette_mask;
Jesse Keating 2f82dd
 	uint32_t saved_rtest_ctrl, saved_rgen_ctrl;
Jesse Keating 2f82dd
 	int i;
Jesse Keating 2f82dd
@@ -135,6 +135,9 @@ static enum drm_connector_status nv04_dac_detect(struct drm_encoder *encoder,
Jesse Keating 2f82dd
 		/* only implemented for head A for now */
Jesse Keating 2f82dd
 		NVSetOwner(dev, 0);
Jesse Keating 2f82dd
 
Jesse Keating 2f82dd
+	saved_cr_mode = NVReadVgaCrtc(dev, 0, NV_CIO_CR_MODE_INDEX);
Jesse Keating 2f82dd
+	NVWriteVgaCrtc(dev, 0, NV_CIO_CR_MODE_INDEX, saved_cr_mode | 0x80);
Jesse Keating 2f82dd
+
Jesse Keating 2f82dd
 	saved_seq1 = NVReadVgaSeq(dev, 0, NV_VIO_SR_CLOCK_INDEX);
Jesse Keating 2f82dd
 	NVWriteVgaSeq(dev, 0, NV_VIO_SR_CLOCK_INDEX, saved_seq1 & ~0x20);
Jesse Keating 2f82dd
 
Jesse Keating 2f82dd
@@ -203,6 +206,7 @@ out:
Jesse Keating 2f82dd
 	NVWriteVgaCrtc(dev, 0, NV_CIO_CRE_PIXEL_INDEX, saved_pi);
Jesse Keating 2f82dd
 	NVWriteVgaCrtc(dev, 0, NV_CIO_CRE_RPC1_INDEX, saved_rpc1);
Jesse Keating 2f82dd
 	NVWriteVgaSeq(dev, 0, NV_VIO_SR_CLOCK_INDEX, saved_seq1);
Jesse Keating 2f82dd
+	NVWriteVgaCrtc(dev, 0, NV_CIO_CR_MODE_INDEX, saved_cr_mode);
Jesse Keating 2f82dd
 
Jesse Keating 2f82dd
 	if (blue == 0x18) {
Jesse Keating 2f82dd
 		NV_INFO(dev, "Load detected on head A\n");
Jesse Keating 2f82dd
diff --git a/drivers/gpu/drm/nouveau/nv50_instmem.c b/drivers/gpu/drm/nouveau/nv50_instmem.c
Jesse Keating 2f82dd
index 94400f7..f0dc4e3 100644
Jesse Keating 2f82dd
--- a/drivers/gpu/drm/nouveau/nv50_instmem.c
Jesse Keating 2f82dd
+++ b/drivers/gpu/drm/nouveau/nv50_instmem.c
Jesse Keating 2f82dd
@@ -76,6 +76,11 @@ nv50_instmem_init(struct drm_device *dev)
Jesse Keating 2f82dd
 	for (i = 0x1700; i <= 0x1710; i += 4)
Jesse Keating 2f82dd
 		priv->save1700[(i-0x1700)/4] = nv_rd32(dev, i);
Jesse Keating 2f82dd
 
Jesse Keating 2f82dd
+	if (dev_priv->chipset == 0xaa || dev_priv->chipset == 0xac)
Jesse Keating 2f82dd
+		dev_priv->vram_sys_base = nv_rd32(dev, 0x100e10) << 12;
Jesse Keating 2f82dd
+	else
Jesse Keating 2f82dd
+		dev_priv->vram_sys_base = 0;
Jesse Keating 2f82dd
+
Jesse Keating 2f82dd
 	/* Reserve the last MiB of VRAM, we should probably try to avoid
Jesse Keating 2f82dd
 	 * setting up the below tables over the top of the VBIOS image at
Jesse Keating 2f82dd
 	 * some point.
Jesse Keating 2f82dd
@@ -172,16 +177,28 @@ nv50_instmem_init(struct drm_device *dev)
Jesse Keating 2f82dd
 	 * We map the entire fake channel into the start of the PRAMIN BAR
Jesse Keating 2f82dd
 	 */
Jesse Keating 2f82dd
 	ret = nouveau_gpuobj_new_ref(dev, chan, NULL, 0, pt_size, 0x1000,
Jesse Keating 2f82dd
-							0, &priv->pramin_pt);
Jesse Keating 2f82dd
+				     0, &priv->pramin_pt);
Jesse Keating 2f82dd
 	if (ret)
Jesse Keating 2f82dd
 		return ret;
Jesse Keating 2f82dd
 
Jesse Keating 2f82dd
-	for (i = 0, v = c_offset; i < pt_size; i += 8, v += 0x1000) {
Jesse Keating 2f82dd
-		if (v < (c_offset + c_size))
Jesse Keating 2f82dd
-			BAR0_WI32(priv->pramin_pt->gpuobj, i + 0, v | 1);
Jesse Keating 2f82dd
-		else
Jesse Keating 2f82dd
-			BAR0_WI32(priv->pramin_pt->gpuobj, i + 0, 0x00000009);
Jesse Keating 2f82dd
+	v = c_offset | 1;
Jesse Keating 2f82dd
+	if (dev_priv->vram_sys_base) {
Jesse Keating 2f82dd
+		v += dev_priv->vram_sys_base;
Jesse Keating 2f82dd
+		v |= 0x30;
Jesse Keating 2f82dd
+	}
Jesse Keating 2f82dd
+
Jesse Keating 2f82dd
+	i = 0;
Jesse Keating 2f82dd
+	while (v < dev_priv->vram_sys_base + c_offset + c_size) {
Jesse Keating 2f82dd
+		BAR0_WI32(priv->pramin_pt->gpuobj, i + 0, v);
Jesse Keating 2f82dd
+		BAR0_WI32(priv->pramin_pt->gpuobj, i + 4, 0x00000000);
Jesse Keating 2f82dd
+		v += 0x1000;
Jesse Keating 2f82dd
+		i += 8;
Jesse Keating 2f82dd
+	}
Jesse Keating 2f82dd
+
Jesse Keating 2f82dd
+	while (i < pt_size) {
Jesse Keating 2f82dd
+		BAR0_WI32(priv->pramin_pt->gpuobj, i + 0, 0x00000000);
Jesse Keating 2f82dd
 		BAR0_WI32(priv->pramin_pt->gpuobj, i + 4, 0x00000000);
Jesse Keating 2f82dd
+		i += 8;
Jesse Keating 2f82dd
 	}
Jesse Keating 2f82dd
 
Jesse Keating 2f82dd
 	BAR0_WI32(chan->vm_pd, 0x00, priv->pramin_pt->instance | 0x63);
Jesse Keating 2f82dd
@@ -416,7 +433,9 @@ nv50_instmem_bind(struct drm_device *dev, struct nouveau_gpuobj *gpuobj)
Jesse Keating 2f82dd
 {
Jesse Keating 2f82dd
 	struct drm_nouveau_private *dev_priv = dev->dev_private;
Jesse Keating 2f82dd
 	struct nv50_instmem_priv *priv = dev_priv->engine.instmem.priv;
Jesse Keating 2f82dd
-	uint32_t pte, pte_end, vram;
Jesse Keating 2f82dd
+	struct nouveau_gpuobj *pramin_pt = priv->pramin_pt->gpuobj;
Jesse Keating 2f82dd
+	uint32_t pte, pte_end;
Jesse Keating 2f82dd
+	uint64_t vram;
Jesse Keating 2f82dd
 
Jesse Keating 2f82dd
 	if (!gpuobj->im_backing || !gpuobj->im_pramin || gpuobj->im_bound)
Jesse Keating 2f82dd
 		return -EINVAL;
Jesse Keating 2f82dd
@@ -424,20 +443,24 @@ nv50_instmem_bind(struct drm_device *dev, struct nouveau_gpuobj *gpuobj)
Jesse Keating 2f82dd
 	NV_DEBUG(dev, "st=0x%0llx sz=0x%0llx\n",
Jesse Keating 2f82dd
 		 gpuobj->im_pramin->start, gpuobj->im_pramin->size);
Jesse Keating 2f82dd
 
Jesse Keating 2f82dd
-	pte     = (gpuobj->im_pramin->start >> 12) << 3;
Jesse Keating 2f82dd
-	pte_end = ((gpuobj->im_pramin->size >> 12) << 3) + pte;
Jesse Keating 2f82dd
+	pte     = (gpuobj->im_pramin->start >> 12) << 1;
Jesse Keating 2f82dd
+	pte_end = ((gpuobj->im_pramin->size >> 12) << 1) + pte;
Jesse Keating 2f82dd
 	vram    = gpuobj->im_backing_start;
Jesse Keating 2f82dd
 
Jesse Keating 2f82dd
 	NV_DEBUG(dev, "pramin=0x%llx, pte=%d, pte_end=%d\n",
Jesse Keating 2f82dd
 		 gpuobj->im_pramin->start, pte, pte_end);
Jesse Keating 2f82dd
 	NV_DEBUG(dev, "first vram page: 0x%08x\n", gpuobj->im_backing_start);
Jesse Keating 2f82dd
 
Jesse Keating 2f82dd
+	vram |= 1;
Jesse Keating 2f82dd
+	if (dev_priv->vram_sys_base) {
Jesse Keating 2f82dd
+		vram += dev_priv->vram_sys_base;
Jesse Keating 2f82dd
+		vram |= 0x30;
Jesse Keating 2f82dd
+	}
Jesse Keating 2f82dd
+
Jesse Keating 2f82dd
 	dev_priv->engine.instmem.prepare_access(dev, true);
Jesse Keating 2f82dd
 	while (pte < pte_end) {
Jesse Keating 2f82dd
-		nv_wo32(dev, priv->pramin_pt->gpuobj, (pte + 0)/4, vram | 1);
Jesse Keating 2f82dd
-		nv_wo32(dev, priv->pramin_pt->gpuobj, (pte + 4)/4, 0x00000000);
Jesse Keating 2f82dd
-
Jesse Keating 2f82dd
-		pte += 8;
Jesse Keating 2f82dd
+		nv_wo32(dev, pramin_pt, pte++, lower_32_bits(vram));
Jesse Keating 2f82dd
+		nv_wo32(dev, pramin_pt, pte++, upper_32_bits(vram));
Jesse Keating 2f82dd
 		vram += NV50_INSTMEM_PAGE_SIZE;
Jesse Keating 2f82dd
 	}
Jesse Keating 2f82dd
 	dev_priv->engine.instmem.finish_access(dev);
Jesse Keating 2f82dd
@@ -470,14 +493,13 @@ nv50_instmem_unbind(struct drm_device *dev, struct nouveau_gpuobj *gpuobj)
Jesse Keating 2f82dd
 	if (gpuobj->im_bound == 0)
Jesse Keating 2f82dd
 		return -EINVAL;
Jesse Keating 2f82dd
 
Jesse Keating 2f82dd
-	pte     = (gpuobj->im_pramin->start >> 12) << 3;
Jesse Keating 2f82dd
-	pte_end = ((gpuobj->im_pramin->size >> 12) << 3) + pte;
Jesse Keating 2f82dd
+	pte     = (gpuobj->im_pramin->start >> 12) << 1;
Jesse Keating 2f82dd
+	pte_end = ((gpuobj->im_pramin->size >> 12) << 1) + pte;
Jesse Keating 2f82dd
 
Jesse Keating 2f82dd
 	dev_priv->engine.instmem.prepare_access(dev, true);
Jesse Keating 2f82dd
 	while (pte < pte_end) {
Jesse Keating 2f82dd
-		nv_wo32(dev, priv->pramin_pt->gpuobj, (pte + 0)/4, 0x00000009);
Jesse Keating 2f82dd
-		nv_wo32(dev, priv->pramin_pt->gpuobj, (pte + 4)/4, 0x00000000);
Jesse Keating 2f82dd
-		pte += 8;
Jesse Keating 2f82dd
+		nv_wo32(dev, priv->pramin_pt->gpuobj, pte++, 0x00000000);
Jesse Keating 2f82dd
+		nv_wo32(dev, priv->pramin_pt->gpuobj, pte++, 0x00000000);
Jesse Keating 2f82dd
 	}
Jesse Keating 2f82dd
 	dev_priv->engine.instmem.finish_access(dev);
Jesse Keating 2f82dd
Jesse Keating 2f82dd
diff --git a/drivers/gpu/drm/nouveau/nouveau_bios.c b/drivers/gpu/drm/nouveau/nouveau_bios.c
Jesse Keating 2f82dd
index bcf843f..71247da 100644
Jesse Keating 2f82dd
--- a/drivers/gpu/drm/nouveau/nouveau_bios.c
Jesse Keating 2f82dd
+++ b/drivers/gpu/drm/nouveau/nouveau_bios.c
Jesse Keating 2f82dd
@@ -3726,7 +3726,7 @@ nouveau_bios_dp_table(struct drm_device *dev, struct dcb_entry *dcbent,
Jesse Keating 2f82dd
 	}
Jesse Keating 2f82dd
 	table = &bios->data[bios->display.dp_table_ptr];
Jesse Keating 2f82dd
 
Jesse Keating 2f82dd
-	if (table[0] != 0x21) {
Jesse Keating 2f82dd
+	if (table[0] != 0x20 && table[0] != 0x21) {
Jesse Keating 2f82dd
 		NV_ERROR(dev, "DisplayPort table version 0x%02x unknown\n",
Jesse Keating 2f82dd
 			 table[0]);
Jesse Keating 2f82dd
 		return NULL;