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From 062c2e4363451d49ef840232fe65e8bff0dde2a5 Mon Sep 17 00:00:00 2001
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From: Alex Deucher <alexander.deucher@amd.com>
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Date: Fri, 27 Sep 2013 18:09:54 -0400
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Subject: [PATCH 1/4] drm/radeon: use 64-bit math to calculate CTS values for
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audio (v2)
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Avoid losing precision. See bug:
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https://bugs.freedesktop.org/show_bug.cgi?id=69675
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v2: fix math as per Anssi's comments.
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Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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---
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drivers/gpu/drm/radeon/r600_hdmi.c | 11 +++++++++--
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1 file changed, 9 insertions(+), 2 deletions(-)
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diff --git a/drivers/gpu/drm/radeon/r600_hdmi.c b/drivers/gpu/drm/radeon/r600_hdmi.c
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index b0fa600..49043a5 100644
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--- a/drivers/gpu/drm/radeon/r600_hdmi.c
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+++ b/drivers/gpu/drm/radeon/r600_hdmi.c
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@@ -75,8 +75,15 @@ static const struct radeon_hdmi_acr r600_hdmi_predefined_acr[] = {
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*/
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static void r600_hdmi_calc_cts(uint32_t clock, int *CTS, int N, int freq)
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{
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- if (*CTS == 0)
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- *CTS = clock * N / (128 * freq) * 1000;
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+ u64 n;
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+ u32 d;
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+
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+ if (*CTS == 0) {
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+ n = (u64)clock * (u64)N * 1000ULL;
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+ d = 128 * freq;
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+ do_div(n, d);
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+ *CTS = n;
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+ }
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DRM_DEBUG("Using ACR timing N=%d CTS=%d for frequency %d\n",
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N, *CTS, freq);
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}
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--
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1.8.3.1
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From e7d12c2f98ae1e68c7298e5028048d150fa553a1 Mon Sep 17 00:00:00 2001
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From: Alex Deucher <alexander.deucher@amd.com>
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Date: Fri, 27 Sep 2013 18:19:42 -0400
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Subject: [PATCH 2/4] drm/radeon: fix N/CTS clock matching for audio
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The drm code that calculates the 1001 clocks rounds up
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rather than truncating. This allows the table to match
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properly on those modes.
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See bug:
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https://bugs.freedesktop.org/show_bug.cgi?id=69675
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Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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---
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drivers/gpu/drm/radeon/r600_hdmi.c | 6 +++---
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1 file changed, 3 insertions(+), 3 deletions(-)
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diff --git a/drivers/gpu/drm/radeon/r600_hdmi.c b/drivers/gpu/drm/radeon/r600_hdmi.c
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index 49043a5..567703f 100644
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--- a/drivers/gpu/drm/radeon/r600_hdmi.c
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+++ b/drivers/gpu/drm/radeon/r600_hdmi.c
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@@ -57,15 +57,15 @@ enum r600_hdmi_iec_status_bits {
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static const struct radeon_hdmi_acr r600_hdmi_predefined_acr[] = {
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/* 32kHz 44.1kHz 48kHz */
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/* Clock N CTS N CTS N CTS */
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- { 25174, 4576, 28125, 7007, 31250, 6864, 28125 }, /* 25,20/1.001 MHz */
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+ { 25175, 4576, 28125, 7007, 31250, 6864, 28125 }, /* 25,20/1.001 MHz */
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{ 25200, 4096, 25200, 6272, 28000, 6144, 25200 }, /* 25.20 MHz */
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{ 27000, 4096, 27000, 6272, 30000, 6144, 27000 }, /* 27.00 MHz */
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{ 27027, 4096, 27027, 6272, 30030, 6144, 27027 }, /* 27.00*1.001 MHz */
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{ 54000, 4096, 54000, 6272, 60000, 6144, 54000 }, /* 54.00 MHz */
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{ 54054, 4096, 54054, 6272, 60060, 6144, 54054 }, /* 54.00*1.001 MHz */
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- { 74175, 11648, 210937, 17836, 234375, 11648, 140625 }, /* 74.25/1.001 MHz */
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+ { 74176, 11648, 210937, 17836, 234375, 11648, 140625 }, /* 74.25/1.001 MHz */
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{ 74250, 4096, 74250, 6272, 82500, 6144, 74250 }, /* 74.25 MHz */
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- { 148351, 11648, 421875, 8918, 234375, 5824, 140625 }, /* 148.50/1.001 MHz */
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+ { 148352, 11648, 421875, 8918, 234375, 5824, 140625 }, /* 148.50/1.001 MHz */
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{ 148500, 4096, 148500, 6272, 165000, 6144, 148500 }, /* 148.50 MHz */
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{ 0, 4096, 0, 6272, 0, 6144, 0 } /* Other */
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};
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--
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1.8.3.1
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From ee0fec312a1c4e26f255955da942562cd8908a4b Mon Sep 17 00:00:00 2001
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From: Alex Deucher <alexander.deucher@amd.com>
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Date: Fri, 27 Sep 2013 18:22:15 -0400
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Subject: [PATCH 3/4] drm/radeon: use hw generated CTS/N values for audio
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Use the hw generated values rather than calculating
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them in the driver. There may be some older r6xx
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asics where this doesn't work correctly. This remains
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to be seen.
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See bug:
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https://bugs.freedesktop.org/show_bug.cgi?id=69675
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Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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---
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drivers/gpu/drm/radeon/r600_hdmi.c | 3 +--
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1 file changed, 1 insertion(+), 2 deletions(-)
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diff --git a/drivers/gpu/drm/radeon/r600_hdmi.c b/drivers/gpu/drm/radeon/r600_hdmi.c
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index 567703f..e2ae1c2 100644
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--- a/drivers/gpu/drm/radeon/r600_hdmi.c
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+++ b/drivers/gpu/drm/radeon/r600_hdmi.c
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@@ -451,8 +451,7 @@ void r600_hdmi_setmode(struct drm_encoder *encoder, struct drm_display_mode *mod
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}
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WREG32(HDMI0_ACR_PACKET_CONTROL + offset,
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- HDMI0_ACR_AUTO_SEND | /* allow hw to sent ACR packets when required */
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- HDMI0_ACR_SOURCE); /* select SW CTS value */
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+ HDMI0_ACR_AUTO_SEND); /* allow hw to sent ACR packets when required */
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WREG32(HDMI0_VBI_PACKET_CONTROL + offset,
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HDMI0_NULL_SEND | /* send null packets when required */
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--
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1.8.3.1
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From b852c985010a77c850b7548d64bbb964ca462b02 Mon Sep 17 00:00:00 2001
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From: Alex Deucher <alexander.deucher@amd.com>
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Date: Thu, 10 Oct 2013 11:47:01 -0400
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Subject: [PATCH 4/4] drm/radeon: re-enable sw ACR support on pre-DCE4
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MIME-Version: 1.0
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Content-Type: text/plain; charset=UTF-8
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Content-Transfer-Encoding: 8bit
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HW ACR support may have issues on some older chips, so
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use SW ACR for now until we've tested further.
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Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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CC: Rafał Miłecki <zajec5@gmail.com>
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---
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drivers/gpu/drm/radeon/r600_hdmi.c | 1 +
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1 file changed, 1 insertion(+)
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diff --git a/drivers/gpu/drm/radeon/r600_hdmi.c b/drivers/gpu/drm/radeon/r600_hdmi.c
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index e2ae1c2..5b72931 100644
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--- a/drivers/gpu/drm/radeon/r600_hdmi.c
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+++ b/drivers/gpu/drm/radeon/r600_hdmi.c
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@@ -451,6 +451,7 @@ void r600_hdmi_setmode(struct drm_encoder *encoder, struct drm_display_mode *mod
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}
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WREG32(HDMI0_ACR_PACKET_CONTROL + offset,
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+ HDMI0_ACR_SOURCE | /* select SW CTS value - XXX verify that hw CTS works on all families */
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HDMI0_ACR_AUTO_SEND); /* allow hw to sent ACR packets when required */
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WREG32(HDMI0_VBI_PACKET_CONTROL + offset,
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--
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1.8.3.1
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