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From patchwork Tue Sep 12 20:02:54 2017
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Content-Type: text/plain; charset="utf-8"
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MIME-Version: 1.0
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Content-Transfer-Encoding: 7bit
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Subject: kvm: nVMX: Don't allow L2 to access the hardware CR8
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From: Jim Mattson <jmattson@google.com>
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X-Patchwork-Id: 9950035
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Message-Id: <20170912200254.111560-1-jmattson@google.com>
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To: kvm@vger.kernel.org, P J P <ppandit@redhat.com>,
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Paolo Bonzini <pbonzini@redhat.com>
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Cc: Jim Mattson <jmattson@google.com>
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Date: Tue, 12 Sep 2017 13:02:54 -0700
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If L1 does not specify the "use TPR shadow" VM-execution control in
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vmcs12, then L0 must specify the "CR8-load exiting" and "CR8-store
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exiting" VM-execution controls in vmcs02. Failure to do so will give
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the L2 VM unrestricted read/write access to the hardware CR8.
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This fixes CVE-2017-12154.
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Signed-off-by: Jim Mattson <jmattson@google.com>
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---
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arch/x86/kvm/vmx.c | 5 +++++
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1 file changed, 5 insertions(+)
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diff --git a/arch/x86/kvm/vmx.c b/arch/x86/kvm/vmx.c
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index c6efc1f88b25..885b7eed4320 100644
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--- a/arch/x86/kvm/vmx.c
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+++ b/arch/x86/kvm/vmx.c
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@@ -10525,6 +10525,11 @@ static int prepare_vmcs02(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12,
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if (exec_control & CPU_BASED_TPR_SHADOW) {
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vmcs_write64(VIRTUAL_APIC_PAGE_ADDR, -1ull);
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vmcs_write32(TPR_THRESHOLD, vmcs12->tpr_threshold);
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+ } else {
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+#ifdef CONFIG_X86_64
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+ exec_control |= CPU_BASED_CR8_LOAD_EXITING |
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+ CPU_BASED_CR8_STORE_EXITING;
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+#endif
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}
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/*
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