Jesse Keating 2f82dd
PCI: Use generic cacheline sizing instead of per-vendor tests.
Jesse Keating 2f82dd
Jesse Keating 2f82dd
Instead of the pci code needing to have code to determine the
Jesse Keating 2f82dd
cacheline size of each processor, use the data the cpu identification
Jesse Keating 2f82dd
code should have already determined during early boot.
Jesse Keating 2f82dd
Jesse Keating 2f82dd
I chose not to delete the existing code for the time being.
Jesse Keating 2f82dd
Instead I added some additional debug statements to be sure that it's
Jesse Keating 2f82dd
doing the right thing, and compares it against what the old code would
Jesse Keating 2f82dd
have done.  After this has been proven to be right in a release,
Jesse Keating 2f82dd
we can delete the paranoid checks, and all the old vendor checking code.
Jesse Keating 2f82dd
Jesse Keating 2f82dd
Signed-off-by: Dave Jones <davej@redhat.com>
Jesse Keating 2f82dd
Jesse Keating 2f82dd
diff --git a/arch/x86/pci/common.c b/arch/x86/pci/common.c
Jesse Keating 2f82dd
index 2202b62..f371fe8 100644
Jesse Keating 2f82dd
--- a/arch/x86/pci/common.c
Jesse Keating 2f82dd
+++ b/arch/x86/pci/common.c
Jesse Keating 2f82dd
@@ -432,6 +432,22 @@ int __init pcibios_init(void)
Jesse Keating 2f82dd
 	else if (c->x86 > 6 && c->x86_vendor == X86_VENDOR_INTEL)
Jesse Keating 2f82dd
 		pci_cache_line_size = 128 >> 2;	/* P4 */
Jesse Keating 2f82dd
 
Jesse Keating 2f82dd
+	if (c->x86_clflush_size != (pci_cache_line_size <<2))
Jesse Keating 2f82dd
+		printk(KERN_DEBUG "PCI: old code would have set cacheline "
Jesse Keating 2f82dd
+			"size to %d bytes, but clflush_size = %d\n",
Jesse Keating 2f82dd
+			pci_cache_line_size << 2,
Jesse Keating 2f82dd
+			c->x86_clflush_size);
Jesse Keating 2f82dd
+
Jesse Keating 2f82dd
+	/* Once we know this logic works, all the above code can be deleted. */
Jesse Keating 2f82dd
+	if (c->x86_clflush_size > 0) {
Jesse Keating 2f82dd
+		pci_cache_line_size = c->x86_clflush_size >> 2;
Jesse Keating 2f82dd
+		printk(KERN_DEBUG "PCI: pci_cache_line_size set to %d bytes\n",
Jesse Keating 2f82dd
+			pci_cache_line_size << 2);
Jesse Keating 2f82dd
+	} else {
Jesse Keating 2f82dd
+		pci_cache_line_size = 32 >> 2;
Jesse Keating 2f82dd
+		printk(KERN_DEBUG "PCI: Unknown cacheline size. Setting to 32 bytes\n");
Jesse Keating 2f82dd
+	}
Jesse Keating 2f82dd
+
Jesse Keating 2f82dd
 	pcibios_resource_survey();
Jesse Keating 2f82dd
 
Jesse Keating 2f82dd
 	if (pci_bf_sort >= pci_force_bf)