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From patchwork Thu Jul 13 12:07:44 2017
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Content-Type: text/plain; charset="utf-8"
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MIME-Version: 1.0
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Content-Transfer-Encoding: 7bit
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Subject: [RESEND,1/4] Docs: dt: document qcom iommu bindings
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From: Rob Clark <robdclark@gmail.com>
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X-Patchwork-Id: 9838369
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Message-Id: <20170713120747.20490-2-robdclark@gmail.com>
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To: iommu@lists.linux-foundation.org
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Cc: linux-arm-msm@vger.kernel.org, Archit Taneja <architt@codeaurora.org>,
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c6ca7ce |
Rob Herring <robh@kernel.org>, Will Deacon <will.deacon@arm.com>,
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c6ca7ce |
Sricharan <sricharan@codeaurora.org>,
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c6ca7ce |
Mark Rutland <mark.rutland@arm.com>, Robin Murphy <robin.murphy@arm.com>,
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c6ca7ce |
Rob Clark <robdclark@gmail.com>, devicetree@vger.kernel.org
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Date: Thu, 13 Jul 2017 08:07:44 -0400
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Cc: devicetree@vger.kernel.org
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Signed-off-by: Rob Clark <robdclark@gmail.com>
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Reviewed-by: Rob Herring <robh@kernel.org>
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---
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.../devicetree/bindings/iommu/qcom,iommu.txt | 121 +++++++++++++++++++++
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1 file changed, 121 insertions(+)
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create mode 100644 Documentation/devicetree/bindings/iommu/qcom,iommu.txt
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diff --git a/Documentation/devicetree/bindings/iommu/qcom,iommu.txt b/Documentation/devicetree/bindings/iommu/qcom,iommu.txt
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new file mode 100644
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index 000000000000..b2641ceb2b40
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--- /dev/null
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+++ b/Documentation/devicetree/bindings/iommu/qcom,iommu.txt
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@@ -0,0 +1,121 @@
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+* QCOM IOMMU v1 Implementation
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+
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+Qualcomm "B" family devices which are not compatible with arm-smmu have
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+a similar looking IOMMU but without access to the global register space,
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+and optionally requiring additional configuration to route context irqs
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+to non-secure vs secure interrupt line.
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+
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+** Required properties:
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+
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+- compatible : Should be one of:
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+
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+ "qcom,msm8916-iommu"
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+
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+ Followed by "qcom,msm-iommu-v1".
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+
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+- clock-names : Should be a pair of "iface" (required for IOMMUs
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+ register group access) and "bus" (required for
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+ the IOMMUs underlying bus access).
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+
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+- clocks : Phandles for respective clocks described by
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+ clock-names.
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+
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+- #address-cells : must be 1.
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+
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+- #size-cells : must be 1.
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+
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+- #iommu-cells : Must be 1. Index identifies the context-bank #.
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+
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+- ranges : Base address and size of the iommu context banks.
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+
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+- qcom,iommu-secure-id : secure-id.
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+
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+- List of sub-nodes, one per translation context bank. Each sub-node
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+ has the following required properties:
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+
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+ - compatible : Should be one of:
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+ - "qcom,msm-iommu-v1-ns" : non-secure context bank
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+ - "qcom,msm-iommu-v1-sec" : secure context bank
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+ - reg : Base address and size of context bank within the iommu
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+ - interrupts : The context fault irq.
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+
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+** Optional properties:
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+
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+- reg : Base address and size of the SMMU local base, should
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+ be only specified if the iommu requires configuration
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+ for routing of context bank irq's to secure vs non-
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+ secure lines. (Ie. if the iommu contains secure
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+ context banks)
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+
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+
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+** Examples:
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+
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+ apps_iommu: iommu@1e20000 {
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+ #address-cells = <1>;
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+ #size-cells = <1>;
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+ #iommu-cells = <1>;
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+ compatible = "qcom,msm8916-iommu", "qcom,msm-iommu-v1";
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+ ranges = <0 0x1e20000 0x40000>;
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+ reg = <0x1ef0000 0x3000>;
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+ clocks = <&gcc GCC_SMMU_CFG_CLK>,
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+ <&gcc GCC_APSS_TCU_CLK>;
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+ clock-names = "iface", "bus";
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+ qcom,iommu-secure-id = <17>;
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+
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+ // mdp_0:
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+ iommu-ctx@4000 {
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+ compatible = "qcom,msm-iommu-v1-ns";
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+ reg = <0x4000 0x1000>;
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+ interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
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+ };
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+
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+ // venus_ns:
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+ iommu-ctx@5000 {
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+ compatible = "qcom,msm-iommu-v1-sec";
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+ reg = <0x5000 0x1000>;
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+ interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
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+ };
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+ };
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+
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+ gpu_iommu: iommu@1f08000 {
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+ #address-cells = <1>;
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+ #size-cells = <1>;
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+ #iommu-cells = <1>;
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+ compatible = "qcom,msm8916-iommu", "qcom,msm-iommu-v1";
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+ ranges = <0 0x1f08000 0x10000>;
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+ clocks = <&gcc GCC_SMMU_CFG_CLK>,
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+ <&gcc GCC_GFX_TCU_CLK>;
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+ clock-names = "iface", "bus";
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+ qcom,iommu-secure-id = <18>;
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+
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+ // gfx3d_user:
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+ iommu-ctx@1000 {
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+ compatible = "qcom,msm-iommu-v1-ns";
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+ reg = <0x1000 0x1000>;
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+ interrupts = <GIC_SPI 241 IRQ_TYPE_LEVEL_HIGH>;
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+ };
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+
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+ // gfx3d_priv:
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+ iommu-ctx@2000 {
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+ compatible = "qcom,msm-iommu-v1-ns";
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+ reg = <0x2000 0x1000>;
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+ interrupts = <GIC_SPI 242 IRQ_TYPE_LEVEL_HIGH>;
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+ };
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+ };
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+
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+ ...
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+
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+ venus: video-codec@1d00000 {
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+ ...
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+ iommus = <&apps_iommu 5>;
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+ };
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+
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+ mdp: mdp@1a01000 {
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+ ...
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+ iommus = <&apps_iommu 4>;
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+ };
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+
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+ gpu@01c00000 {
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+ ...
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+ iommus = <&gpu_iommu 1>, <&gpu_iommu 2>;
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+ };
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c6ca7ce |
From patchwork Thu Jul 13 12:07:45 2017
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Content-Type: text/plain; charset="utf-8"
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c6ca7ce |
MIME-Version: 1.0
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Content-Transfer-Encoding: 7bit
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Subject: [RESEND,2/4] iommu: arm-smmu: split out register defines
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c6ca7ce |
From: Rob Clark <robdclark@gmail.com>
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c6ca7ce |
X-Patchwork-Id: 9838371
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c6ca7ce |
Message-Id: <20170713120747.20490-3-robdclark@gmail.com>
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c6ca7ce |
To: iommu@lists.linux-foundation.org
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Cc: linux-arm-msm@vger.kernel.org, Archit Taneja <architt@codeaurora.org>,
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c6ca7ce |
Rob Herring <robh@kernel.org>, Will Deacon <will.deacon@arm.com>,
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c6ca7ce |
Sricharan <sricharan@codeaurora.org>,
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c6ca7ce |
Mark Rutland <mark.rutland@arm.com>, Robin Murphy <robin.murphy@arm.com>,
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c6ca7ce |
Rob Clark <robdclark@gmail.com>
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Date: Thu, 13 Jul 2017 08:07:45 -0400
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c6ca7ce |
I want to re-use some of these for qcom_iommu, which has (roughly) the
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same context-bank registers.
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Signed-off-by: Rob Clark <robdclark@gmail.com>
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---
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drivers/iommu/arm-smmu-regs.h | 227 ++++++++++++++++++++++++++++++++++++++++++
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drivers/iommu/arm-smmu.c | 203 +------------------------------------
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2 files changed, 228 insertions(+), 202 deletions(-)
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create mode 100644 drivers/iommu/arm-smmu-regs.h
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diff --git a/drivers/iommu/arm-smmu-regs.h b/drivers/iommu/arm-smmu-regs.h
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new file mode 100644
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index 000000000000..87589c863068
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--- /dev/null
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+++ b/drivers/iommu/arm-smmu-regs.h
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@@ -0,0 +1,227 @@
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+/*
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+ * IOMMU API for ARM architected SMMU implementations.
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+ *
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+ * This program is free software; you can redistribute it and/or modify
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+ * it under the terms of the GNU General Public License version 2 as
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+ * published by the Free Software Foundation.
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+ *
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+ * This program is distributed in the hope that it will be useful,
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+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
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+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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+ * GNU General Public License for more details.
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+ *
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+ * You should have received a copy of the GNU General Public License
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+ * along with this program; if not, write to the Free Software
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+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
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+ *
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+ * Copyright (C) 2013 ARM Limited
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+ *
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+ * Author: Will Deacon <will.deacon@arm.com>
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+ */
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+
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+#ifndef _ARM_SMMU_REGS_H
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+#define _ARM_SMMU_REGS_H
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+
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+/* Configuration registers */
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+#define ARM_SMMU_GR0_sCR0 0x0
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+#define sCR0_CLIENTPD (1 << 0)
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+#define sCR0_GFRE (1 << 1)
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+#define sCR0_GFIE (1 << 2)
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+#define sCR0_EXIDENABLE (1 << 3)
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+#define sCR0_GCFGFRE (1 << 4)
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+#define sCR0_GCFGFIE (1 << 5)
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+#define sCR0_USFCFG (1 << 10)
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+#define sCR0_VMIDPNE (1 << 11)
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+#define sCR0_PTM (1 << 12)
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+#define sCR0_FB (1 << 13)
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+#define sCR0_VMID16EN (1 << 31)
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+#define sCR0_BSU_SHIFT 14
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+#define sCR0_BSU_MASK 0x3
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+
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+/* Auxiliary Configuration register */
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+#define ARM_SMMU_GR0_sACR 0x10
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+
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+/* Identification registers */
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+#define ARM_SMMU_GR0_ID0 0x20
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+#define ARM_SMMU_GR0_ID1 0x24
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+#define ARM_SMMU_GR0_ID2 0x28
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+#define ARM_SMMU_GR0_ID3 0x2c
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+#define ARM_SMMU_GR0_ID4 0x30
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+#define ARM_SMMU_GR0_ID5 0x34
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+#define ARM_SMMU_GR0_ID6 0x38
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+#define ARM_SMMU_GR0_ID7 0x3c
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+#define ARM_SMMU_GR0_sGFSR 0x48
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+#define ARM_SMMU_GR0_sGFSYNR0 0x50
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+#define ARM_SMMU_GR0_sGFSYNR1 0x54
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+#define ARM_SMMU_GR0_sGFSYNR2 0x58
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+
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+#define ID0_S1TS (1 << 30)
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+#define ID0_S2TS (1 << 29)
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+#define ID0_NTS (1 << 28)
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+#define ID0_SMS (1 << 27)
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+#define ID0_ATOSNS (1 << 26)
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+#define ID0_PTFS_NO_AARCH32 (1 << 25)
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+#define ID0_PTFS_NO_AARCH32S (1 << 24)
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+#define ID0_CTTW (1 << 14)
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+#define ID0_NUMIRPT_SHIFT 16
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+#define ID0_NUMIRPT_MASK 0xff
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+#define ID0_NUMSIDB_SHIFT 9
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+#define ID0_NUMSIDB_MASK 0xf
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+#define ID0_EXIDS (1 << 8)
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+#define ID0_NUMSMRG_SHIFT 0
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+#define ID0_NUMSMRG_MASK 0xff
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+
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+#define ID1_PAGESIZE (1 << 31)
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+#define ID1_NUMPAGENDXB_SHIFT 28
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+#define ID1_NUMPAGENDXB_MASK 7
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+#define ID1_NUMS2CB_SHIFT 16
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+#define ID1_NUMS2CB_MASK 0xff
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c6ca7ce |
+#define ID1_NUMCB_SHIFT 0
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c6ca7ce |
+#define ID1_NUMCB_MASK 0xff
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+
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c6ca7ce |
+#define ID2_OAS_SHIFT 4
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+#define ID2_OAS_MASK 0xf
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c6ca7ce |
+#define ID2_IAS_SHIFT 0
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c6ca7ce |
+#define ID2_IAS_MASK 0xf
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c6ca7ce |
+#define ID2_UBS_SHIFT 8
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|
c6ca7ce |
+#define ID2_UBS_MASK 0xf
|
|
|
c6ca7ce |
+#define ID2_PTFS_4K (1 << 12)
|
|
|
c6ca7ce |
+#define ID2_PTFS_16K (1 << 13)
|
|
|
c6ca7ce |
+#define ID2_PTFS_64K (1 << 14)
|
|
|
c6ca7ce |
+#define ID2_VMID16 (1 << 15)
|
|
|
c6ca7ce |
+
|
|
|
c6ca7ce |
+#define ID7_MAJOR_SHIFT 4
|
|
|
c6ca7ce |
+#define ID7_MAJOR_MASK 0xf
|
|
|
c6ca7ce |
+
|
|
|
c6ca7ce |
+/* Global TLB invalidation */
|
|
|
c6ca7ce |
+#define ARM_SMMU_GR0_TLBIVMID 0x64
|
|
|
c6ca7ce |
+#define ARM_SMMU_GR0_TLBIALLNSNH 0x68
|
|
|
c6ca7ce |
+#define ARM_SMMU_GR0_TLBIALLH 0x6c
|
|
|
c6ca7ce |
+#define ARM_SMMU_GR0_sTLBGSYNC 0x70
|
|
|
c6ca7ce |
+#define ARM_SMMU_GR0_sTLBGSTATUS 0x74
|
|
|
c6ca7ce |
+#define sTLBGSTATUS_GSACTIVE (1 << 0)
|
|
|
c6ca7ce |
+#define TLB_LOOP_TIMEOUT 1000000 /* 1s! */
|
|
|
c6ca7ce |
+#define TLB_SPIN_COUNT 10
|
|
|
c6ca7ce |
+
|
|
|
c6ca7ce |
+/* Stream mapping registers */
|
|
|
c6ca7ce |
+#define ARM_SMMU_GR0_SMR(n) (0x800 + ((n) << 2))
|
|
|
c6ca7ce |
+#define SMR_VALID (1 << 31)
|
|
|
c6ca7ce |
+#define SMR_MASK_SHIFT 16
|
|
|
c6ca7ce |
+#define SMR_ID_SHIFT 0
|
|
|
c6ca7ce |
+
|
|
|
c6ca7ce |
+#define ARM_SMMU_GR0_S2CR(n) (0xc00 + ((n) << 2))
|
|
|
c6ca7ce |
+#define S2CR_CBNDX_SHIFT 0
|
|
|
c6ca7ce |
+#define S2CR_CBNDX_MASK 0xff
|
|
|
c6ca7ce |
+#define S2CR_EXIDVALID (1 << 10)
|
|
|
c6ca7ce |
+#define S2CR_TYPE_SHIFT 16
|
|
|
c6ca7ce |
+#define S2CR_TYPE_MASK 0x3
|
|
|
c6ca7ce |
+enum arm_smmu_s2cr_type {
|
|
|
c6ca7ce |
+ S2CR_TYPE_TRANS,
|
|
|
c6ca7ce |
+ S2CR_TYPE_BYPASS,
|
|
|
c6ca7ce |
+ S2CR_TYPE_FAULT,
|
|
|
c6ca7ce |
+};
|
|
|
c6ca7ce |
+
|
|
|
c6ca7ce |
+#define S2CR_PRIVCFG_SHIFT 24
|
|
|
c6ca7ce |
+#define S2CR_PRIVCFG_MASK 0x3
|
|
|
c6ca7ce |
+enum arm_smmu_s2cr_privcfg {
|
|
|
c6ca7ce |
+ S2CR_PRIVCFG_DEFAULT,
|
|
|
c6ca7ce |
+ S2CR_PRIVCFG_DIPAN,
|
|
|
c6ca7ce |
+ S2CR_PRIVCFG_UNPRIV,
|
|
|
c6ca7ce |
+ S2CR_PRIVCFG_PRIV,
|
|
|
c6ca7ce |
+};
|
|
|
c6ca7ce |
+
|
|
|
c6ca7ce |
+/* Context bank attribute registers */
|
|
|
c6ca7ce |
+#define ARM_SMMU_GR1_CBAR(n) (0x0 + ((n) << 2))
|
|
|
c6ca7ce |
+#define CBAR_VMID_SHIFT 0
|
|
|
c6ca7ce |
+#define CBAR_VMID_MASK 0xff
|
|
|
c6ca7ce |
+#define CBAR_S1_BPSHCFG_SHIFT 8
|
|
|
c6ca7ce |
+#define CBAR_S1_BPSHCFG_MASK 3
|
|
|
c6ca7ce |
+#define CBAR_S1_BPSHCFG_NSH 3
|
|
|
c6ca7ce |
+#define CBAR_S1_MEMATTR_SHIFT 12
|
|
|
c6ca7ce |
+#define CBAR_S1_MEMATTR_MASK 0xf
|
|
|
c6ca7ce |
+#define CBAR_S1_MEMATTR_WB 0xf
|
|
|
c6ca7ce |
+#define CBAR_TYPE_SHIFT 16
|
|
|
c6ca7ce |
+#define CBAR_TYPE_MASK 0x3
|
|
|
c6ca7ce |
+#define CBAR_TYPE_S2_TRANS (0 << CBAR_TYPE_SHIFT)
|
|
|
c6ca7ce |
+#define CBAR_TYPE_S1_TRANS_S2_BYPASS (1 << CBAR_TYPE_SHIFT)
|
|
|
c6ca7ce |
+#define CBAR_TYPE_S1_TRANS_S2_FAULT (2 << CBAR_TYPE_SHIFT)
|
|
|
c6ca7ce |
+#define CBAR_TYPE_S1_TRANS_S2_TRANS (3 << CBAR_TYPE_SHIFT)
|
|
|
c6ca7ce |
+#define CBAR_IRPTNDX_SHIFT 24
|
|
|
c6ca7ce |
+#define CBAR_IRPTNDX_MASK 0xff
|
|
|
c6ca7ce |
+
|
|
|
c6ca7ce |
+#define ARM_SMMU_GR1_CBA2R(n) (0x800 + ((n) << 2))
|
|
|
c6ca7ce |
+#define CBA2R_RW64_32BIT (0 << 0)
|
|
|
c6ca7ce |
+#define CBA2R_RW64_64BIT (1 << 0)
|
|
|
c6ca7ce |
+#define CBA2R_VMID_SHIFT 16
|
|
|
c6ca7ce |
+#define CBA2R_VMID_MASK 0xffff
|
|
|
c6ca7ce |
+
|
|
|
c6ca7ce |
+#define ARM_SMMU_CB_SCTLR 0x0
|
|
|
c6ca7ce |
+#define ARM_SMMU_CB_ACTLR 0x4
|
|
|
c6ca7ce |
+#define ARM_SMMU_CB_RESUME 0x8
|
|
|
c6ca7ce |
+#define ARM_SMMU_CB_TTBCR2 0x10
|
|
|
c6ca7ce |
+#define ARM_SMMU_CB_TTBR0 0x20
|
|
|
c6ca7ce |
+#define ARM_SMMU_CB_TTBR1 0x28
|
|
|
c6ca7ce |
+#define ARM_SMMU_CB_TTBCR 0x30
|
|
|
c6ca7ce |
+#define ARM_SMMU_CB_CONTEXTIDR 0x34
|
|
|
c6ca7ce |
+#define ARM_SMMU_CB_S1_MAIR0 0x38
|
|
|
c6ca7ce |
+#define ARM_SMMU_CB_S1_MAIR1 0x3c
|
|
|
c6ca7ce |
+#define ARM_SMMU_CB_PAR 0x50
|
|
|
c6ca7ce |
+#define ARM_SMMU_CB_FSR 0x58
|
|
|
c6ca7ce |
+#define ARM_SMMU_CB_FAR 0x60
|
|
|
c6ca7ce |
+#define ARM_SMMU_CB_FSYNR0 0x68
|
|
|
c6ca7ce |
+#define ARM_SMMU_CB_S1_TLBIVA 0x600
|
|
|
c6ca7ce |
+#define ARM_SMMU_CB_S1_TLBIASID 0x610
|
|
|
c6ca7ce |
+#define ARM_SMMU_CB_S1_TLBIVAL 0x620
|
|
|
c6ca7ce |
+#define ARM_SMMU_CB_S2_TLBIIPAS2 0x630
|
|
|
c6ca7ce |
+#define ARM_SMMU_CB_S2_TLBIIPAS2L 0x638
|
|
|
c6ca7ce |
+#define ARM_SMMU_CB_TLBSYNC 0x7f0
|
|
|
c6ca7ce |
+#define ARM_SMMU_CB_TLBSTATUS 0x7f4
|
|
|
c6ca7ce |
+#define ARM_SMMU_CB_ATS1PR 0x800
|
|
|
c6ca7ce |
+#define ARM_SMMU_CB_ATSR 0x8f0
|
|
|
c6ca7ce |
+
|
|
|
c6ca7ce |
+#define SCTLR_S1_ASIDPNE (1 << 12)
|
|
|
c6ca7ce |
+#define SCTLR_CFCFG (1 << 7)
|
|
|
c6ca7ce |
+#define SCTLR_CFIE (1 << 6)
|
|
|
c6ca7ce |
+#define SCTLR_CFRE (1 << 5)
|
|
|
c6ca7ce |
+#define SCTLR_E (1 << 4)
|
|
|
c6ca7ce |
+#define SCTLR_AFE (1 << 2)
|
|
|
c6ca7ce |
+#define SCTLR_TRE (1 << 1)
|
|
|
c6ca7ce |
+#define SCTLR_M (1 << 0)
|
|
|
c6ca7ce |
+
|
|
|
c6ca7ce |
+#define ARM_MMU500_ACTLR_CPRE (1 << 1)
|
|
|
c6ca7ce |
+
|
|
|
c6ca7ce |
+#define ARM_MMU500_ACR_CACHE_LOCK (1 << 26)
|
|
|
c6ca7ce |
+#define ARM_MMU500_ACR_SMTNMB_TLBEN (1 << 8)
|
|
|
c6ca7ce |
+
|
|
|
c6ca7ce |
+#define CB_PAR_F (1 << 0)
|
|
|
c6ca7ce |
+
|
|
|
c6ca7ce |
+#define ATSR_ACTIVE (1 << 0)
|
|
|
c6ca7ce |
+
|
|
|
c6ca7ce |
+#define RESUME_RETRY (0 << 0)
|
|
|
c6ca7ce |
+#define RESUME_TERMINATE (1 << 0)
|
|
|
c6ca7ce |
+
|
|
|
c6ca7ce |
+#define TTBCR2_SEP_SHIFT 15
|
|
|
c6ca7ce |
+#define TTBCR2_SEP_UPSTREAM (0x7 << TTBCR2_SEP_SHIFT)
|
|
|
c6ca7ce |
+#define TTBCR2_AS (1 << 4)
|
|
|
c6ca7ce |
+
|
|
|
c6ca7ce |
+#define TTBRn_ASID_SHIFT 48
|
|
|
c6ca7ce |
+
|
|
|
c6ca7ce |
+#define FSR_MULTI (1 << 31)
|
|
|
c6ca7ce |
+#define FSR_SS (1 << 30)
|
|
|
c6ca7ce |
+#define FSR_UUT (1 << 8)
|
|
|
c6ca7ce |
+#define FSR_ASF (1 << 7)
|
|
|
c6ca7ce |
+#define FSR_TLBLKF (1 << 6)
|
|
|
c6ca7ce |
+#define FSR_TLBMCF (1 << 5)
|
|
|
c6ca7ce |
+#define FSR_EF (1 << 4)
|
|
|
c6ca7ce |
+#define FSR_PF (1 << 3)
|
|
|
c6ca7ce |
+#define FSR_AFF (1 << 2)
|
|
|
c6ca7ce |
+#define FSR_TF (1 << 1)
|
|
|
c6ca7ce |
+
|
|
|
c6ca7ce |
+#define FSR_IGN (FSR_AFF | FSR_ASF | \
|
|
|
c6ca7ce |
+ FSR_TLBMCF | FSR_TLBLKF)
|
|
|
c6ca7ce |
+#define FSR_FAULT (FSR_MULTI | FSR_SS | FSR_UUT | \
|
|
|
c6ca7ce |
+ FSR_EF | FSR_PF | FSR_TF | FSR_IGN)
|
|
|
c6ca7ce |
+
|
|
|
c6ca7ce |
+#define FSYNR0_WNR (1 << 4)
|
|
|
c6ca7ce |
+
|
|
|
c6ca7ce |
+#endif /* _ARM_SMMU_REGS_H */
|
|
|
c6ca7ce |
diff --git a/drivers/iommu/arm-smmu.c b/drivers/iommu/arm-smmu.c
|
|
|
c6ca7ce |
index 7ec30b08b3bd..ca9c20f915a8 100644
|
|
|
c6ca7ce |
--- a/drivers/iommu/arm-smmu.c
|
|
|
c6ca7ce |
+++ b/drivers/iommu/arm-smmu.c
|
|
|
c6ca7ce |
@@ -54,6 +54,7 @@
|
|
|
c6ca7ce |
#include <linux/amba/bus.h>
|
|
|
c6ca7ce |
|
|
|
c6ca7ce |
#include "io-pgtable.h"
|
|
|
c6ca7ce |
+#include "arm-smmu-regs.h"
|
|
|
c6ca7ce |
|
|
|
c6ca7ce |
/* Maximum number of context banks per SMMU */
|
|
|
c6ca7ce |
#define ARM_SMMU_MAX_CBS 128
|
|
|
c6ca7ce |
@@ -83,211 +84,9 @@
|
|
|
c6ca7ce |
#define smmu_write_atomic_lq writel_relaxed
|
|
|
c6ca7ce |
#endif
|
|
|
c6ca7ce |
|
|
|
c6ca7ce |
-/* Configuration registers */
|
|
|
c6ca7ce |
-#define ARM_SMMU_GR0_sCR0 0x0
|
|
|
c6ca7ce |
-#define sCR0_CLIENTPD (1 << 0)
|
|
|
c6ca7ce |
-#define sCR0_GFRE (1 << 1)
|
|
|
c6ca7ce |
-#define sCR0_GFIE (1 << 2)
|
|
|
c6ca7ce |
-#define sCR0_EXIDENABLE (1 << 3)
|
|
|
c6ca7ce |
-#define sCR0_GCFGFRE (1 << 4)
|
|
|
c6ca7ce |
-#define sCR0_GCFGFIE (1 << 5)
|
|
|
c6ca7ce |
-#define sCR0_USFCFG (1 << 10)
|
|
|
c6ca7ce |
-#define sCR0_VMIDPNE (1 << 11)
|
|
|
c6ca7ce |
-#define sCR0_PTM (1 << 12)
|
|
|
c6ca7ce |
-#define sCR0_FB (1 << 13)
|
|
|
c6ca7ce |
-#define sCR0_VMID16EN (1 << 31)
|
|
|
c6ca7ce |
-#define sCR0_BSU_SHIFT 14
|
|
|
c6ca7ce |
-#define sCR0_BSU_MASK 0x3
|
|
|
c6ca7ce |
-
|
|
|
c6ca7ce |
-/* Auxiliary Configuration register */
|
|
|
c6ca7ce |
-#define ARM_SMMU_GR0_sACR 0x10
|
|
|
c6ca7ce |
-
|
|
|
c6ca7ce |
-/* Identification registers */
|
|
|
c6ca7ce |
-#define ARM_SMMU_GR0_ID0 0x20
|
|
|
c6ca7ce |
-#define ARM_SMMU_GR0_ID1 0x24
|
|
|
c6ca7ce |
-#define ARM_SMMU_GR0_ID2 0x28
|
|
|
c6ca7ce |
-#define ARM_SMMU_GR0_ID3 0x2c
|
|
|
c6ca7ce |
-#define ARM_SMMU_GR0_ID4 0x30
|
|
|
c6ca7ce |
-#define ARM_SMMU_GR0_ID5 0x34
|
|
|
c6ca7ce |
-#define ARM_SMMU_GR0_ID6 0x38
|
|
|
c6ca7ce |
-#define ARM_SMMU_GR0_ID7 0x3c
|
|
|
c6ca7ce |
-#define ARM_SMMU_GR0_sGFSR 0x48
|
|
|
c6ca7ce |
-#define ARM_SMMU_GR0_sGFSYNR0 0x50
|
|
|
c6ca7ce |
-#define ARM_SMMU_GR0_sGFSYNR1 0x54
|
|
|
c6ca7ce |
-#define ARM_SMMU_GR0_sGFSYNR2 0x58
|
|
|
c6ca7ce |
-
|
|
|
c6ca7ce |
-#define ID0_S1TS (1 << 30)
|
|
|
c6ca7ce |
-#define ID0_S2TS (1 << 29)
|
|
|
c6ca7ce |
-#define ID0_NTS (1 << 28)
|
|
|
c6ca7ce |
-#define ID0_SMS (1 << 27)
|
|
|
c6ca7ce |
-#define ID0_ATOSNS (1 << 26)
|
|
|
c6ca7ce |
-#define ID0_PTFS_NO_AARCH32 (1 << 25)
|
|
|
c6ca7ce |
-#define ID0_PTFS_NO_AARCH32S (1 << 24)
|
|
|
c6ca7ce |
-#define ID0_CTTW (1 << 14)
|
|
|
c6ca7ce |
-#define ID0_NUMIRPT_SHIFT 16
|
|
|
c6ca7ce |
-#define ID0_NUMIRPT_MASK 0xff
|
|
|
c6ca7ce |
-#define ID0_NUMSIDB_SHIFT 9
|
|
|
c6ca7ce |
-#define ID0_NUMSIDB_MASK 0xf
|
|
|
c6ca7ce |
-#define ID0_EXIDS (1 << 8)
|
|
|
c6ca7ce |
-#define ID0_NUMSMRG_SHIFT 0
|
|
|
c6ca7ce |
-#define ID0_NUMSMRG_MASK 0xff
|
|
|
c6ca7ce |
-
|
|
|
c6ca7ce |
-#define ID1_PAGESIZE (1 << 31)
|
|
|
c6ca7ce |
-#define ID1_NUMPAGENDXB_SHIFT 28
|
|
|
c6ca7ce |
-#define ID1_NUMPAGENDXB_MASK 7
|
|
|
c6ca7ce |
-#define ID1_NUMS2CB_SHIFT 16
|
|
|
c6ca7ce |
-#define ID1_NUMS2CB_MASK 0xff
|
|
|
c6ca7ce |
-#define ID1_NUMCB_SHIFT 0
|
|
|
c6ca7ce |
-#define ID1_NUMCB_MASK 0xff
|
|
|
c6ca7ce |
-
|
|
|
c6ca7ce |
-#define ID2_OAS_SHIFT 4
|
|
|
c6ca7ce |
-#define ID2_OAS_MASK 0xf
|
|
|
c6ca7ce |
-#define ID2_IAS_SHIFT 0
|
|
|
c6ca7ce |
-#define ID2_IAS_MASK 0xf
|
|
|
c6ca7ce |
-#define ID2_UBS_SHIFT 8
|
|
|
c6ca7ce |
-#define ID2_UBS_MASK 0xf
|
|
|
c6ca7ce |
-#define ID2_PTFS_4K (1 << 12)
|
|
|
c6ca7ce |
-#define ID2_PTFS_16K (1 << 13)
|
|
|
c6ca7ce |
-#define ID2_PTFS_64K (1 << 14)
|
|
|
c6ca7ce |
-#define ID2_VMID16 (1 << 15)
|
|
|
c6ca7ce |
-
|
|
|
c6ca7ce |
-#define ID7_MAJOR_SHIFT 4
|
|
|
c6ca7ce |
-#define ID7_MAJOR_MASK 0xf
|
|
|
c6ca7ce |
-
|
|
|
c6ca7ce |
-/* Global TLB invalidation */
|
|
|
c6ca7ce |
-#define ARM_SMMU_GR0_TLBIVMID 0x64
|
|
|
c6ca7ce |
-#define ARM_SMMU_GR0_TLBIALLNSNH 0x68
|
|
|
c6ca7ce |
-#define ARM_SMMU_GR0_TLBIALLH 0x6c
|
|
|
c6ca7ce |
-#define ARM_SMMU_GR0_sTLBGSYNC 0x70
|
|
|
c6ca7ce |
-#define ARM_SMMU_GR0_sTLBGSTATUS 0x74
|
|
|
c6ca7ce |
-#define sTLBGSTATUS_GSACTIVE (1 << 0)
|
|
|
c6ca7ce |
-#define TLB_LOOP_TIMEOUT 1000000 /* 1s! */
|
|
|
c6ca7ce |
-#define TLB_SPIN_COUNT 10
|
|
|
c6ca7ce |
-
|
|
|
c6ca7ce |
-/* Stream mapping registers */
|
|
|
c6ca7ce |
-#define ARM_SMMU_GR0_SMR(n) (0x800 + ((n) << 2))
|
|
|
c6ca7ce |
-#define SMR_VALID (1 << 31)
|
|
|
c6ca7ce |
-#define SMR_MASK_SHIFT 16
|
|
|
c6ca7ce |
-#define SMR_ID_SHIFT 0
|
|
|
c6ca7ce |
-
|
|
|
c6ca7ce |
-#define ARM_SMMU_GR0_S2CR(n) (0xc00 + ((n) << 2))
|
|
|
c6ca7ce |
-#define S2CR_CBNDX_SHIFT 0
|
|
|
c6ca7ce |
-#define S2CR_CBNDX_MASK 0xff
|
|
|
c6ca7ce |
-#define S2CR_EXIDVALID (1 << 10)
|
|
|
c6ca7ce |
-#define S2CR_TYPE_SHIFT 16
|
|
|
c6ca7ce |
-#define S2CR_TYPE_MASK 0x3
|
|
|
c6ca7ce |
-enum arm_smmu_s2cr_type {
|
|
|
c6ca7ce |
- S2CR_TYPE_TRANS,
|
|
|
c6ca7ce |
- S2CR_TYPE_BYPASS,
|
|
|
c6ca7ce |
- S2CR_TYPE_FAULT,
|
|
|
c6ca7ce |
-};
|
|
|
c6ca7ce |
-
|
|
|
c6ca7ce |
-#define S2CR_PRIVCFG_SHIFT 24
|
|
|
c6ca7ce |
-#define S2CR_PRIVCFG_MASK 0x3
|
|
|
c6ca7ce |
-enum arm_smmu_s2cr_privcfg {
|
|
|
c6ca7ce |
- S2CR_PRIVCFG_DEFAULT,
|
|
|
c6ca7ce |
- S2CR_PRIVCFG_DIPAN,
|
|
|
c6ca7ce |
- S2CR_PRIVCFG_UNPRIV,
|
|
|
c6ca7ce |
- S2CR_PRIVCFG_PRIV,
|
|
|
c6ca7ce |
-};
|
|
|
c6ca7ce |
-
|
|
|
c6ca7ce |
-/* Context bank attribute registers */
|
|
|
c6ca7ce |
-#define ARM_SMMU_GR1_CBAR(n) (0x0 + ((n) << 2))
|
|
|
c6ca7ce |
-#define CBAR_VMID_SHIFT 0
|
|
|
c6ca7ce |
-#define CBAR_VMID_MASK 0xff
|
|
|
c6ca7ce |
-#define CBAR_S1_BPSHCFG_SHIFT 8
|
|
|
c6ca7ce |
-#define CBAR_S1_BPSHCFG_MASK 3
|
|
|
c6ca7ce |
-#define CBAR_S1_BPSHCFG_NSH 3
|
|
|
c6ca7ce |
-#define CBAR_S1_MEMATTR_SHIFT 12
|
|
|
c6ca7ce |
-#define CBAR_S1_MEMATTR_MASK 0xf
|
|
|
c6ca7ce |
-#define CBAR_S1_MEMATTR_WB 0xf
|
|
|
c6ca7ce |
-#define CBAR_TYPE_SHIFT 16
|
|
|
c6ca7ce |
-#define CBAR_TYPE_MASK 0x3
|
|
|
c6ca7ce |
-#define CBAR_TYPE_S2_TRANS (0 << CBAR_TYPE_SHIFT)
|
|
|
c6ca7ce |
-#define CBAR_TYPE_S1_TRANS_S2_BYPASS (1 << CBAR_TYPE_SHIFT)
|
|
|
c6ca7ce |
-#define CBAR_TYPE_S1_TRANS_S2_FAULT (2 << CBAR_TYPE_SHIFT)
|
|
|
c6ca7ce |
-#define CBAR_TYPE_S1_TRANS_S2_TRANS (3 << CBAR_TYPE_SHIFT)
|
|
|
c6ca7ce |
-#define CBAR_IRPTNDX_SHIFT 24
|
|
|
c6ca7ce |
-#define CBAR_IRPTNDX_MASK 0xff
|
|
|
c6ca7ce |
-
|
|
|
c6ca7ce |
-#define ARM_SMMU_GR1_CBA2R(n) (0x800 + ((n) << 2))
|
|
|
c6ca7ce |
-#define CBA2R_RW64_32BIT (0 << 0)
|
|
|
c6ca7ce |
-#define CBA2R_RW64_64BIT (1 << 0)
|
|
|
c6ca7ce |
-#define CBA2R_VMID_SHIFT 16
|
|
|
c6ca7ce |
-#define CBA2R_VMID_MASK 0xffff
|
|
|
c6ca7ce |
-
|
|
|
c6ca7ce |
/* Translation context bank */
|
|
|
c6ca7ce |
#define ARM_SMMU_CB(smmu, n) ((smmu)->cb_base + ((n) << (smmu)->pgshift))
|
|
|
c6ca7ce |
|
|
|
c6ca7ce |
-#define ARM_SMMU_CB_SCTLR 0x0
|
|
|
c6ca7ce |
-#define ARM_SMMU_CB_ACTLR 0x4
|
|
|
c6ca7ce |
-#define ARM_SMMU_CB_RESUME 0x8
|
|
|
c6ca7ce |
-#define ARM_SMMU_CB_TTBCR2 0x10
|
|
|
c6ca7ce |
-#define ARM_SMMU_CB_TTBR0 0x20
|
|
|
c6ca7ce |
-#define ARM_SMMU_CB_TTBR1 0x28
|
|
|
c6ca7ce |
-#define ARM_SMMU_CB_TTBCR 0x30
|
|
|
c6ca7ce |
-#define ARM_SMMU_CB_CONTEXTIDR 0x34
|
|
|
c6ca7ce |
-#define ARM_SMMU_CB_S1_MAIR0 0x38
|
|
|
c6ca7ce |
-#define ARM_SMMU_CB_S1_MAIR1 0x3c
|
|
|
c6ca7ce |
-#define ARM_SMMU_CB_PAR 0x50
|
|
|
c6ca7ce |
-#define ARM_SMMU_CB_FSR 0x58
|
|
|
c6ca7ce |
-#define ARM_SMMU_CB_FAR 0x60
|
|
|
c6ca7ce |
-#define ARM_SMMU_CB_FSYNR0 0x68
|
|
|
c6ca7ce |
-#define ARM_SMMU_CB_S1_TLBIVA 0x600
|
|
|
c6ca7ce |
-#define ARM_SMMU_CB_S1_TLBIASID 0x610
|
|
|
c6ca7ce |
-#define ARM_SMMU_CB_S1_TLBIVAL 0x620
|
|
|
c6ca7ce |
-#define ARM_SMMU_CB_S2_TLBIIPAS2 0x630
|
|
|
c6ca7ce |
-#define ARM_SMMU_CB_S2_TLBIIPAS2L 0x638
|
|
|
c6ca7ce |
-#define ARM_SMMU_CB_TLBSYNC 0x7f0
|
|
|
c6ca7ce |
-#define ARM_SMMU_CB_TLBSTATUS 0x7f4
|
|
|
c6ca7ce |
-#define ARM_SMMU_CB_ATS1PR 0x800
|
|
|
c6ca7ce |
-#define ARM_SMMU_CB_ATSR 0x8f0
|
|
|
c6ca7ce |
-
|
|
|
c6ca7ce |
-#define SCTLR_S1_ASIDPNE (1 << 12)
|
|
|
c6ca7ce |
-#define SCTLR_CFCFG (1 << 7)
|
|
|
c6ca7ce |
-#define SCTLR_CFIE (1 << 6)
|
|
|
c6ca7ce |
-#define SCTLR_CFRE (1 << 5)
|
|
|
c6ca7ce |
-#define SCTLR_E (1 << 4)
|
|
|
c6ca7ce |
-#define SCTLR_AFE (1 << 2)
|
|
|
c6ca7ce |
-#define SCTLR_TRE (1 << 1)
|
|
|
c6ca7ce |
-#define SCTLR_M (1 << 0)
|
|
|
c6ca7ce |
-
|
|
|
c6ca7ce |
-#define ARM_MMU500_ACTLR_CPRE (1 << 1)
|
|
|
c6ca7ce |
-
|
|
|
c6ca7ce |
-#define ARM_MMU500_ACR_CACHE_LOCK (1 << 26)
|
|
|
c6ca7ce |
-#define ARM_MMU500_ACR_SMTNMB_TLBEN (1 << 8)
|
|
|
c6ca7ce |
-
|
|
|
c6ca7ce |
-#define CB_PAR_F (1 << 0)
|
|
|
c6ca7ce |
-
|
|
|
c6ca7ce |
-#define ATSR_ACTIVE (1 << 0)
|
|
|
c6ca7ce |
-
|
|
|
c6ca7ce |
-#define RESUME_RETRY (0 << 0)
|
|
|
c6ca7ce |
-#define RESUME_TERMINATE (1 << 0)
|
|
|
c6ca7ce |
-
|
|
|
c6ca7ce |
-#define TTBCR2_SEP_SHIFT 15
|
|
|
c6ca7ce |
-#define TTBCR2_SEP_UPSTREAM (0x7 << TTBCR2_SEP_SHIFT)
|
|
|
c6ca7ce |
-#define TTBCR2_AS (1 << 4)
|
|
|
c6ca7ce |
-
|
|
|
c6ca7ce |
-#define TTBRn_ASID_SHIFT 48
|
|
|
c6ca7ce |
-
|
|
|
c6ca7ce |
-#define FSR_MULTI (1 << 31)
|
|
|
c6ca7ce |
-#define FSR_SS (1 << 30)
|
|
|
c6ca7ce |
-#define FSR_UUT (1 << 8)
|
|
|
c6ca7ce |
-#define FSR_ASF (1 << 7)
|
|
|
c6ca7ce |
-#define FSR_TLBLKF (1 << 6)
|
|
|
c6ca7ce |
-#define FSR_TLBMCF (1 << 5)
|
|
|
c6ca7ce |
-#define FSR_EF (1 << 4)
|
|
|
c6ca7ce |
-#define FSR_PF (1 << 3)
|
|
|
c6ca7ce |
-#define FSR_AFF (1 << 2)
|
|
|
c6ca7ce |
-#define FSR_TF (1 << 1)
|
|
|
c6ca7ce |
-
|
|
|
c6ca7ce |
-#define FSR_IGN (FSR_AFF | FSR_ASF | \
|
|
|
c6ca7ce |
- FSR_TLBMCF | FSR_TLBLKF)
|
|
|
c6ca7ce |
-#define FSR_FAULT (FSR_MULTI | FSR_SS | FSR_UUT | \
|
|
|
c6ca7ce |
- FSR_EF | FSR_PF | FSR_TF | FSR_IGN)
|
|
|
c6ca7ce |
-
|
|
|
c6ca7ce |
-#define FSYNR0_WNR (1 << 4)
|
|
|
c6ca7ce |
-
|
|
|
c6ca7ce |
#define MSI_IOVA_BASE 0x8000000
|
|
|
c6ca7ce |
#define MSI_IOVA_LENGTH 0x100000
|
|
|
c6ca7ce |
|
|
|
c6ca7ce |
From patchwork Thu Jul 13 12:07:46 2017
|
|
|
c6ca7ce |
Content-Type: text/plain; charset="utf-8"
|
|
|
c6ca7ce |
MIME-Version: 1.0
|
|
|
c6ca7ce |
Content-Transfer-Encoding: 7bit
|
|
|
c6ca7ce |
Subject: [RESEND,3/4] iommu: add qcom_iommu
|
|
|
c6ca7ce |
From: Rob Clark <robdclark@gmail.com>
|
|
|
c6ca7ce |
X-Patchwork-Id: 9838375
|
|
|
c6ca7ce |
Message-Id: <20170713120747.20490-4-robdclark@gmail.com>
|
|
|
c6ca7ce |
To: iommu@lists.linux-foundation.org
|
|
|
c6ca7ce |
Cc: linux-arm-msm@vger.kernel.org, Archit Taneja <architt@codeaurora.org>,
|
|
|
c6ca7ce |
Rob Herring <robh@kernel.org>, Will Deacon <will.deacon@arm.com>,
|
|
|
c6ca7ce |
Sricharan <sricharan@codeaurora.org>,
|
|
|
c6ca7ce |
Mark Rutland <mark.rutland@arm.com>, Robin Murphy <robin.murphy@arm.com>,
|
|
|
c6ca7ce |
Rob Clark <robdclark@gmail.com>
|
|
|
c6ca7ce |
Date: Thu, 13 Jul 2017 08:07:46 -0400
|
|
|
c6ca7ce |
|
|
|
c6ca7ce |
An iommu driver for Qualcomm "B" family devices which do implement the
|
|
|
c6ca7ce |
ARM SMMU spec, but not in a way that is compatible with how the arm-smmu
|
|
|
c6ca7ce |
driver is designed. It seems SMMU_SCR1.GASRAE=1 so the global register
|
|
|
c6ca7ce |
space is not accessible. This means it needs to get configuration from
|
|
|
c6ca7ce |
devicetree instead of setting it up dynamically.
|
|
|
c6ca7ce |
|
|
|
c6ca7ce |
In the end, other than register definitions, there is not much code to
|
|
|
c6ca7ce |
share with arm-smmu (other than what has already been refactored out
|
|
|
c6ca7ce |
into the pgtable helpers).
|
|
|
c6ca7ce |
|
|
|
c6ca7ce |
Signed-off-by: Rob Clark <robdclark@gmail.com>
|
|
|
c6ca7ce |
Tested-by: Riku Voipio <riku.voipio@linaro.org>
|
|
|
c6ca7ce |
---
|
|
|
c6ca7ce |
v1: original
|
|
|
c6ca7ce |
v2: bindings cleanups and kconfig issues that kbuild robot pointed out
|
|
|
c6ca7ce |
v3: fix issues pointed out by Rob H. and actually make device removal
|
|
|
c6ca7ce |
work
|
|
|
c6ca7ce |
v4: fix WARN_ON() splats reported by Archit
|
|
|
c6ca7ce |
v5: some fixes to build as a module.. note that it cannot actually
|
|
|
c6ca7ce |
be built as a module yet (at minimum a bunch of other iommu syms
|
|
|
c6ca7ce |
that are needed are not exported, but there may be more to it
|
|
|
c6ca7ce |
than that), but at least qcom_iommu is ready should it become
|
|
|
c6ca7ce |
possible to build iommu drivers as modules.
|
|
|
c6ca7ce |
v6: Add additional pm-runtime get/puts around paths that can hit
|
|
|
c6ca7ce |
TLB inv, to avoid unclocked register access if device using the
|
|
|
c6ca7ce |
iommu is not powered on. And pre-emptively clear interrupts
|
|
|
c6ca7ce |
before registering IRQ handler just in case the bootloader has
|
|
|
c6ca7ce |
left us a surpise.
|
|
|
c6ca7ce |
v7: Address review comments from Robin (don't associate iommu_group
|
|
|
c6ca7ce |
with context bank, table lookup instead of list to find context
|
|
|
c6ca7ce |
bank, etc)
|
|
|
c6ca7ce |
v8: Fix silly bug on detach. Actually Robin already pointed it out
|
|
|
c6ca7ce |
but I somehow overlooked that comment when preparing v7.
|
|
|
c6ca7ce |
|
|
|
c6ca7ce |
drivers/iommu/Kconfig | 10 +
|
|
|
c6ca7ce |
drivers/iommu/Makefile | 1 +
|
|
|
c6ca7ce |
drivers/iommu/qcom_iommu.c | 868 +++++++++++++++++++++++++++++++++++++++++++++
|
|
|
c6ca7ce |
3 files changed, 879 insertions(+)
|
|
|
c6ca7ce |
create mode 100644 drivers/iommu/qcom_iommu.c
|
|
|
c6ca7ce |
|
|
|
c6ca7ce |
diff --git a/drivers/iommu/Kconfig b/drivers/iommu/Kconfig
|
|
|
c6ca7ce |
index 6ee3a25ae731..aa4b62893fe1 100644
|
|
|
c6ca7ce |
--- a/drivers/iommu/Kconfig
|
|
|
c6ca7ce |
+++ b/drivers/iommu/Kconfig
|
|
|
c6ca7ce |
@@ -367,4 +367,14 @@ config MTK_IOMMU_V1
|
|
|
c6ca7ce |
|
|
|
c6ca7ce |
if unsure, say N here.
|
|
|
c6ca7ce |
|
|
|
c6ca7ce |
+config QCOM_IOMMU
|
|
|
c6ca7ce |
+ # Note: iommu drivers cannot (yet?) be built as modules
|
|
|
c6ca7ce |
+ bool "Qualcomm IOMMU Support"
|
|
|
c6ca7ce |
+ depends on ARCH_QCOM || COMPILE_TEST
|
|
|
c6ca7ce |
+ select IOMMU_API
|
|
|
c6ca7ce |
+ select IOMMU_IO_PGTABLE_LPAE
|
|
|
c6ca7ce |
+ select ARM_DMA_USE_IOMMU
|
|
|
c6ca7ce |
+ help
|
|
|
c6ca7ce |
+ Support for IOMMU on certain Qualcomm SoCs.
|
|
|
c6ca7ce |
+
|
|
|
c6ca7ce |
endif # IOMMU_SUPPORT
|
|
|
c6ca7ce |
diff --git a/drivers/iommu/Makefile b/drivers/iommu/Makefile
|
|
|
c6ca7ce |
index 195f7b997d8e..b910aea813a1 100644
|
|
|
c6ca7ce |
--- a/drivers/iommu/Makefile
|
|
|
c6ca7ce |
+++ b/drivers/iommu/Makefile
|
|
|
c6ca7ce |
@@ -27,3 +27,4 @@ obj-$(CONFIG_TEGRA_IOMMU_SMMU) += tegra-smmu.o
|
|
|
c6ca7ce |
obj-$(CONFIG_EXYNOS_IOMMU) += exynos-iommu.o
|
|
|
c6ca7ce |
obj-$(CONFIG_FSL_PAMU) += fsl_pamu.o fsl_pamu_domain.o
|
|
|
c6ca7ce |
obj-$(CONFIG_S390_IOMMU) += s390-iommu.o
|
|
|
c6ca7ce |
+obj-$(CONFIG_QCOM_IOMMU) += qcom_iommu.o
|
|
|
c6ca7ce |
diff --git a/drivers/iommu/qcom_iommu.c b/drivers/iommu/qcom_iommu.c
|
|
|
c6ca7ce |
new file mode 100644
|
|
|
c6ca7ce |
index 000000000000..860cad1cb167
|
|
|
c6ca7ce |
--- /dev/null
|
|
|
c6ca7ce |
+++ b/drivers/iommu/qcom_iommu.c
|
|
|
c6ca7ce |
@@ -0,0 +1,868 @@
|
|
|
c6ca7ce |
+/*
|
|
|
c6ca7ce |
+ * IOMMU API for QCOM secure IOMMUs. Somewhat based on arm-smmu.c
|
|
|
c6ca7ce |
+ *
|
|
|
c6ca7ce |
+ * This program is free software; you can redistribute it and/or modify
|
|
|
c6ca7ce |
+ * it under the terms of the GNU General Public License version 2 as
|
|
|
c6ca7ce |
+ * published by the Free Software Foundation.
|
|
|
c6ca7ce |
+ *
|
|
|
c6ca7ce |
+ * This program is distributed in the hope that it will be useful,
|
|
|
c6ca7ce |
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
|
|
|
c6ca7ce |
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
|
|
c6ca7ce |
+ * GNU General Public License for more details.
|
|
|
c6ca7ce |
+ *
|
|
|
c6ca7ce |
+ * You should have received a copy of the GNU General Public License
|
|
|
c6ca7ce |
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
|
|
|
c6ca7ce |
+ *
|
|
|
c6ca7ce |
+ * Copyright (C) 2013 ARM Limited
|
|
|
c6ca7ce |
+ * Copyright (C) 2017 Red Hat
|
|
|
c6ca7ce |
+ */
|
|
|
c6ca7ce |
+
|
|
|
c6ca7ce |
+#include <linux/atomic.h>
|
|
|
c6ca7ce |
+#include <linux/clk.h>
|
|
|
c6ca7ce |
+#include <linux/delay.h>
|
|
|
c6ca7ce |
+#include <linux/dma-iommu.h>
|
|
|
c6ca7ce |
+#include <linux/dma-mapping.h>
|
|
|
c6ca7ce |
+#include <linux/err.h>
|
|
|
c6ca7ce |
+#include <linux/interrupt.h>
|
|
|
c6ca7ce |
+#include <linux/io.h>
|
|
|
c6ca7ce |
+#include <linux/io-64-nonatomic-hi-lo.h>
|
|
|
c6ca7ce |
+#include <linux/iommu.h>
|
|
|
c6ca7ce |
+#include <linux/iopoll.h>
|
|
|
c6ca7ce |
+#include <linux/kconfig.h>
|
|
|
c6ca7ce |
+#include <linux/module.h>
|
|
|
c6ca7ce |
+#include <linux/mutex.h>
|
|
|
c6ca7ce |
+#include <linux/of.h>
|
|
|
c6ca7ce |
+#include <linux/of_address.h>
|
|
|
c6ca7ce |
+#include <linux/of_device.h>
|
|
|
c6ca7ce |
+#include <linux/of_iommu.h>
|
|
|
c6ca7ce |
+#include <linux/platform_device.h>
|
|
|
c6ca7ce |
+#include <linux/pm.h>
|
|
|
c6ca7ce |
+#include <linux/pm_runtime.h>
|
|
|
c6ca7ce |
+#include <linux/qcom_scm.h>
|
|
|
c6ca7ce |
+#include <linux/slab.h>
|
|
|
c6ca7ce |
+#include <linux/spinlock.h>
|
|
|
c6ca7ce |
+
|
|
|
c6ca7ce |
+#include "io-pgtable.h"
|
|
|
c6ca7ce |
+#include "arm-smmu-regs.h"
|
|
|
c6ca7ce |
+
|
|
|
c6ca7ce |
+#define SMMU_INTR_SEL_NS 0x2000
|
|
|
c6ca7ce |
+
|
|
|
c6ca7ce |
+struct qcom_iommu_ctx;
|
|
|
c6ca7ce |
+
|
|
|
c6ca7ce |
+struct qcom_iommu_dev {
|
|
|
c6ca7ce |
+ /* IOMMU core code handle */
|
|
|
c6ca7ce |
+ struct iommu_device iommu;
|
|
|
c6ca7ce |
+ struct device *dev;
|
|
|
c6ca7ce |
+ struct clk *iface_clk;
|
|
|
c6ca7ce |
+ struct clk *bus_clk;
|
|
|
c6ca7ce |
+ void __iomem *local_base;
|
|
|
c6ca7ce |
+ u32 sec_id;
|
|
|
c6ca7ce |
+ u8 num_ctxs;
|
|
|
c6ca7ce |
+ struct qcom_iommu_ctx *ctxs[0]; /* indexed by asid-1 */
|
|
|
c6ca7ce |
+};
|
|
|
c6ca7ce |
+
|
|
|
c6ca7ce |
+struct qcom_iommu_ctx {
|
|
|
c6ca7ce |
+ struct device *dev;
|
|
|
c6ca7ce |
+ void __iomem *base;
|
|
|
c6ca7ce |
+ bool secure_init;
|
|
|
c6ca7ce |
+ u8 asid; /* asid and ctx bank # are 1:1 */
|
|
|
c6ca7ce |
+};
|
|
|
c6ca7ce |
+
|
|
|
c6ca7ce |
+struct qcom_iommu_domain {
|
|
|
c6ca7ce |
+ struct io_pgtable_ops *pgtbl_ops;
|
|
|
c6ca7ce |
+ spinlock_t pgtbl_lock;
|
|
|
c6ca7ce |
+ struct mutex init_mutex; /* Protects iommu pointer */
|
|
|
c6ca7ce |
+ struct iommu_domain domain;
|
|
|
c6ca7ce |
+ struct qcom_iommu_dev *iommu;
|
|
|
c6ca7ce |
+};
|
|
|
c6ca7ce |
+
|
|
|
c6ca7ce |
+static struct qcom_iommu_domain *to_qcom_iommu_domain(struct iommu_domain *dom)
|
|
|
c6ca7ce |
+{
|
|
|
c6ca7ce |
+ return container_of(dom, struct qcom_iommu_domain, domain);
|
|
|
c6ca7ce |
+}
|
|
|
c6ca7ce |
+
|
|
|
c6ca7ce |
+static const struct iommu_ops qcom_iommu_ops;
|
|
|
c6ca7ce |
+
|
|
|
c6ca7ce |
+static struct qcom_iommu_dev * to_iommu(struct iommu_fwspec *fwspec)
|
|
|
c6ca7ce |
+{
|
|
|
c6ca7ce |
+ if (!fwspec || fwspec->ops != &qcom_iommu_ops)
|
|
|
c6ca7ce |
+ return NULL;
|
|
|
c6ca7ce |
+ return fwspec->iommu_priv;
|
|
|
c6ca7ce |
+}
|
|
|
c6ca7ce |
+
|
|
|
c6ca7ce |
+static struct qcom_iommu_ctx * to_ctx(struct iommu_fwspec *fwspec, unsigned asid)
|
|
|
c6ca7ce |
+{
|
|
|
c6ca7ce |
+ struct qcom_iommu_dev *qcom_iommu = to_iommu(fwspec);
|
|
|
c6ca7ce |
+ if (!qcom_iommu)
|
|
|
c6ca7ce |
+ return NULL;
|
|
|
c6ca7ce |
+ return qcom_iommu->ctxs[asid - 1];
|
|
|
c6ca7ce |
+}
|
|
|
c6ca7ce |
+
|
|
|
c6ca7ce |
+static inline void
|
|
|
c6ca7ce |
+iommu_writel(struct qcom_iommu_ctx *ctx, unsigned reg, u32 val)
|
|
|
c6ca7ce |
+{
|
|
|
c6ca7ce |
+ writel_relaxed(val, ctx->base + reg);
|
|
|
c6ca7ce |
+}
|
|
|
c6ca7ce |
+
|
|
|
c6ca7ce |
+static inline void
|
|
|
c6ca7ce |
+iommu_writeq(struct qcom_iommu_ctx *ctx, unsigned reg, u64 val)
|
|
|
c6ca7ce |
+{
|
|
|
c6ca7ce |
+ writeq_relaxed(val, ctx->base + reg);
|
|
|
c6ca7ce |
+}
|
|
|
c6ca7ce |
+
|
|
|
c6ca7ce |
+static inline u32
|
|
|
c6ca7ce |
+iommu_readl(struct qcom_iommu_ctx *ctx, unsigned reg)
|
|
|
c6ca7ce |
+{
|
|
|
c6ca7ce |
+ return readl_relaxed(ctx->base + reg);
|
|
|
c6ca7ce |
+}
|
|
|
c6ca7ce |
+
|
|
|
c6ca7ce |
+static inline u64
|
|
|
c6ca7ce |
+iommu_readq(struct qcom_iommu_ctx *ctx, unsigned reg)
|
|
|
c6ca7ce |
+{
|
|
|
c6ca7ce |
+ return readq_relaxed(ctx->base + reg);
|
|
|
c6ca7ce |
+}
|
|
|
c6ca7ce |
+
|
|
|
c6ca7ce |
+static void qcom_iommu_tlb_sync(void *cookie)
|
|
|
c6ca7ce |
+{
|
|
|
c6ca7ce |
+ struct iommu_fwspec *fwspec = cookie;
|
|
|
c6ca7ce |
+ unsigned i;
|
|
|
c6ca7ce |
+
|
|
|
c6ca7ce |
+ for (i = 0; i < fwspec->num_ids; i++) {
|
|
|
c6ca7ce |
+ struct qcom_iommu_ctx *ctx = to_ctx(fwspec, fwspec->ids[i]);
|
|
|
c6ca7ce |
+ unsigned int val, ret;
|
|
|
c6ca7ce |
+
|
|
|
c6ca7ce |
+ iommu_writel(ctx, ARM_SMMU_CB_TLBSYNC, 0);
|
|
|
c6ca7ce |
+
|
|
|
c6ca7ce |
+ ret = readl_poll_timeout(ctx->base + ARM_SMMU_CB_TLBSTATUS, val,
|
|
|
c6ca7ce |
+ (val & 0x1) == 0, 0, 5000000);
|
|
|
c6ca7ce |
+ if (ret)
|
|
|
c6ca7ce |
+ dev_err(ctx->dev, "timeout waiting for TLB SYNC\n");
|
|
|
c6ca7ce |
+ }
|
|
|
c6ca7ce |
+}
|
|
|
c6ca7ce |
+
|
|
|
c6ca7ce |
+static void qcom_iommu_tlb_inv_context(void *cookie)
|
|
|
c6ca7ce |
+{
|
|
|
c6ca7ce |
+ struct iommu_fwspec *fwspec = cookie;
|
|
|
c6ca7ce |
+ unsigned i;
|
|
|
c6ca7ce |
+
|
|
|
c6ca7ce |
+ for (i = 0; i < fwspec->num_ids; i++) {
|
|
|
c6ca7ce |
+ struct qcom_iommu_ctx *ctx = to_ctx(fwspec, fwspec->ids[i]);
|
|
|
c6ca7ce |
+ iommu_writel(ctx, ARM_SMMU_CB_S1_TLBIASID, ctx->asid);
|
|
|
c6ca7ce |
+ }
|
|
|
c6ca7ce |
+
|
|
|
c6ca7ce |
+ qcom_iommu_tlb_sync(cookie);
|
|
|
c6ca7ce |
+}
|
|
|
c6ca7ce |
+
|
|
|
c6ca7ce |
+static void qcom_iommu_tlb_inv_range_nosync(unsigned long iova, size_t size,
|
|
|
c6ca7ce |
+ size_t granule, bool leaf, void *cookie)
|
|
|
c6ca7ce |
+{
|
|
|
c6ca7ce |
+ struct iommu_fwspec *fwspec = cookie;
|
|
|
c6ca7ce |
+ unsigned i, reg;
|
|
|
c6ca7ce |
+
|
|
|
c6ca7ce |
+ reg = leaf ? ARM_SMMU_CB_S1_TLBIVAL : ARM_SMMU_CB_S1_TLBIVA;
|
|
|
c6ca7ce |
+
|
|
|
c6ca7ce |
+ for (i = 0; i < fwspec->num_ids; i++) {
|
|
|
c6ca7ce |
+ struct qcom_iommu_ctx *ctx = to_ctx(fwspec, fwspec->ids[i]);
|
|
|
c6ca7ce |
+ size_t s = size;
|
|
|
c6ca7ce |
+
|
|
|
c6ca7ce |
+ iova &= ~12UL;
|
|
|
c6ca7ce |
+ iova |= ctx->asid;
|
|
|
c6ca7ce |
+ do {
|
|
|
c6ca7ce |
+ iommu_writel(ctx, reg, iova);
|
|
|
c6ca7ce |
+ iova += granule;
|
|
|
c6ca7ce |
+ } while (s -= granule);
|
|
|
c6ca7ce |
+ }
|
|
|
c6ca7ce |
+}
|
|
|
c6ca7ce |
+
|
|
|
c6ca7ce |
+static const struct iommu_gather_ops qcom_gather_ops = {
|
|
|
c6ca7ce |
+ .tlb_flush_all = qcom_iommu_tlb_inv_context,
|
|
|
c6ca7ce |
+ .tlb_add_flush = qcom_iommu_tlb_inv_range_nosync,
|
|
|
c6ca7ce |
+ .tlb_sync = qcom_iommu_tlb_sync,
|
|
|
c6ca7ce |
+};
|
|
|
c6ca7ce |
+
|
|
|
c6ca7ce |
+static irqreturn_t qcom_iommu_fault(int irq, void *dev)
|
|
|
c6ca7ce |
+{
|
|
|
c6ca7ce |
+ struct qcom_iommu_ctx *ctx = dev;
|
|
|
c6ca7ce |
+ u32 fsr, fsynr;
|
|
|
c6ca7ce |
+ u64 iova;
|
|
|
c6ca7ce |
+
|
|
|
c6ca7ce |
+ fsr = iommu_readl(ctx, ARM_SMMU_CB_FSR);
|
|
|
c6ca7ce |
+
|
|
|
c6ca7ce |
+ if (!(fsr & FSR_FAULT))
|
|
|
c6ca7ce |
+ return IRQ_NONE;
|
|
|
c6ca7ce |
+
|
|
|
c6ca7ce |
+ fsynr = iommu_readl(ctx, ARM_SMMU_CB_FSYNR0);
|
|
|
c6ca7ce |
+ iova = iommu_readq(ctx, ARM_SMMU_CB_FAR);
|
|
|
c6ca7ce |
+
|
|
|
c6ca7ce |
+ dev_err_ratelimited(ctx->dev,
|
|
|
c6ca7ce |
+ "Unhandled context fault: fsr=0x%x, "
|
|
|
c6ca7ce |
+ "iova=0x%016llx, fsynr=0x%x, cb=%d\n",
|
|
|
c6ca7ce |
+ fsr, iova, fsynr, ctx->asid);
|
|
|
c6ca7ce |
+
|
|
|
c6ca7ce |
+ iommu_writel(ctx, ARM_SMMU_CB_FSR, fsr);
|
|
|
c6ca7ce |
+
|
|
|
c6ca7ce |
+ return IRQ_HANDLED;
|
|
|
c6ca7ce |
+}
|
|
|
c6ca7ce |
+
|
|
|
c6ca7ce |
+static int qcom_iommu_init_domain(struct iommu_domain *domain,
|
|
|
c6ca7ce |
+ struct qcom_iommu_dev *qcom_iommu,
|
|
|
c6ca7ce |
+ struct iommu_fwspec *fwspec)
|
|
|
c6ca7ce |
+{
|
|
|
c6ca7ce |
+ struct qcom_iommu_domain *qcom_domain = to_qcom_iommu_domain(domain);
|
|
|
c6ca7ce |
+ struct io_pgtable_ops *pgtbl_ops;
|
|
|
c6ca7ce |
+ struct io_pgtable_cfg pgtbl_cfg;
|
|
|
c6ca7ce |
+ int i, ret = 0;
|
|
|
c6ca7ce |
+ u32 reg;
|
|
|
c6ca7ce |
+
|
|
|
c6ca7ce |
+ mutex_lock(&qcom_domain->init_mutex);
|
|
|
c6ca7ce |
+ if (qcom_domain->iommu)
|
|
|
c6ca7ce |
+ goto out_unlock;
|
|
|
c6ca7ce |
+
|
|
|
c6ca7ce |
+ pgtbl_cfg = (struct io_pgtable_cfg) {
|
|
|
c6ca7ce |
+ .pgsize_bitmap = qcom_iommu_ops.pgsize_bitmap,
|
|
|
c6ca7ce |
+ .ias = 32,
|
|
|
c6ca7ce |
+ .oas = 40,
|
|
|
c6ca7ce |
+ .tlb = &qcom_gather_ops,
|
|
|
c6ca7ce |
+ .iommu_dev = qcom_iommu->dev,
|
|
|
c6ca7ce |
+ };
|
|
|
c6ca7ce |
+
|
|
|
c6ca7ce |
+ qcom_domain->iommu = qcom_iommu;
|
|
|
c6ca7ce |
+ pgtbl_ops = alloc_io_pgtable_ops(ARM_32_LPAE_S1, &pgtbl_cfg, fwspec);
|
|
|
c6ca7ce |
+ if (!pgtbl_ops) {
|
|
|
c6ca7ce |
+ dev_err(qcom_iommu->dev, "failed to allocate pagetable ops\n");
|
|
|
c6ca7ce |
+ ret = -ENOMEM;
|
|
|
c6ca7ce |
+ goto out_clear_iommu;
|
|
|
c6ca7ce |
+ }
|
|
|
c6ca7ce |
+
|
|
|
c6ca7ce |
+ /* Update the domain's page sizes to reflect the page table format */
|
|
|
c6ca7ce |
+ domain->pgsize_bitmap = pgtbl_cfg.pgsize_bitmap;
|
|
|
c6ca7ce |
+ domain->geometry.aperture_end = (1ULL << pgtbl_cfg.ias) - 1;
|
|
|
c6ca7ce |
+ domain->geometry.force_aperture = true;
|
|
|
c6ca7ce |
+
|
|
|
c6ca7ce |
+ for (i = 0; i < fwspec->num_ids; i++) {
|
|
|
c6ca7ce |
+ struct qcom_iommu_ctx *ctx = to_ctx(fwspec, fwspec->ids[i]);
|
|
|
c6ca7ce |
+
|
|
|
c6ca7ce |
+ if (!ctx->secure_init) {
|
|
|
c6ca7ce |
+ ret = qcom_scm_restore_sec_cfg(qcom_iommu->sec_id, ctx->asid);
|
|
|
c6ca7ce |
+ if (ret) {
|
|
|
c6ca7ce |
+ dev_err(qcom_iommu->dev, "secure init failed: %d\n", ret);
|
|
|
c6ca7ce |
+ goto out_clear_iommu;
|
|
|
c6ca7ce |
+ }
|
|
|
c6ca7ce |
+ ctx->secure_init = true;
|
|
|
c6ca7ce |
+ }
|
|
|
c6ca7ce |
+
|
|
|
c6ca7ce |
+ /* TTBRs */
|
|
|
c6ca7ce |
+ iommu_writeq(ctx, ARM_SMMU_CB_TTBR0,
|
|
|
c6ca7ce |
+ pgtbl_cfg.arm_lpae_s1_cfg.ttbr[0] |
|
|
|
c6ca7ce |
+ ((u64)ctx->asid << TTBRn_ASID_SHIFT));
|
|
|
c6ca7ce |
+ iommu_writeq(ctx, ARM_SMMU_CB_TTBR1,
|
|
|
c6ca7ce |
+ pgtbl_cfg.arm_lpae_s1_cfg.ttbr[1] |
|
|
|
c6ca7ce |
+ ((u64)ctx->asid << TTBRn_ASID_SHIFT));
|
|
|
c6ca7ce |
+
|
|
|
c6ca7ce |
+ /* TTBCR */
|
|
|
c6ca7ce |
+ iommu_writel(ctx, ARM_SMMU_CB_TTBCR2,
|
|
|
c6ca7ce |
+ (pgtbl_cfg.arm_lpae_s1_cfg.tcr >> 32) |
|
|
|
c6ca7ce |
+ TTBCR2_SEP_UPSTREAM);
|
|
|
c6ca7ce |
+ iommu_writel(ctx, ARM_SMMU_CB_TTBCR,
|
|
|
c6ca7ce |
+ pgtbl_cfg.arm_lpae_s1_cfg.tcr);
|
|
|
c6ca7ce |
+
|
|
|
c6ca7ce |
+ /* MAIRs (stage-1 only) */
|
|
|
c6ca7ce |
+ iommu_writel(ctx, ARM_SMMU_CB_S1_MAIR0,
|
|
|
c6ca7ce |
+ pgtbl_cfg.arm_lpae_s1_cfg.mair[0]);
|
|
|
c6ca7ce |
+ iommu_writel(ctx, ARM_SMMU_CB_S1_MAIR1,
|
|
|
c6ca7ce |
+ pgtbl_cfg.arm_lpae_s1_cfg.mair[1]);
|
|
|
c6ca7ce |
+
|
|
|
c6ca7ce |
+ /* SCTLR */
|
|
|
c6ca7ce |
+ reg = SCTLR_CFIE | SCTLR_CFRE | SCTLR_AFE | SCTLR_TRE |
|
|
|
c6ca7ce |
+ SCTLR_M | SCTLR_S1_ASIDPNE;
|
|
|
c6ca7ce |
+
|
|
|
c6ca7ce |
+ if (IS_ENABLED(CONFIG_BIG_ENDIAN))
|
|
|
c6ca7ce |
+ reg |= SCTLR_E;
|
|
|
c6ca7ce |
+
|
|
|
c6ca7ce |
+ iommu_writel(ctx, ARM_SMMU_CB_SCTLR, reg);
|
|
|
c6ca7ce |
+ }
|
|
|
c6ca7ce |
+
|
|
|
c6ca7ce |
+ mutex_unlock(&qcom_domain->init_mutex);
|
|
|
c6ca7ce |
+
|
|
|
c6ca7ce |
+ /* Publish page table ops for map/unmap */
|
|
|
c6ca7ce |
+ qcom_domain->pgtbl_ops = pgtbl_ops;
|
|
|
c6ca7ce |
+
|
|
|
c6ca7ce |
+ return 0;
|
|
|
c6ca7ce |
+
|
|
|
c6ca7ce |
+out_clear_iommu:
|
|
|
c6ca7ce |
+ qcom_domain->iommu = NULL;
|
|
|
c6ca7ce |
+out_unlock:
|
|
|
c6ca7ce |
+ mutex_unlock(&qcom_domain->init_mutex);
|
|
|
c6ca7ce |
+ return ret;
|
|
|
c6ca7ce |
+}
|
|
|
c6ca7ce |
+
|
|
|
c6ca7ce |
+static struct iommu_domain *qcom_iommu_domain_alloc(unsigned type)
|
|
|
c6ca7ce |
+{
|
|
|
c6ca7ce |
+ struct qcom_iommu_domain *qcom_domain;
|
|
|
c6ca7ce |
+
|
|
|
c6ca7ce |
+ if (type != IOMMU_DOMAIN_UNMANAGED && type != IOMMU_DOMAIN_DMA)
|
|
|
c6ca7ce |
+ return NULL;
|
|
|
c6ca7ce |
+ /*
|
|
|
c6ca7ce |
+ * Allocate the domain and initialise some of its data structures.
|
|
|
c6ca7ce |
+ * We can't really do anything meaningful until we've added a
|
|
|
c6ca7ce |
+ * master.
|
|
|
c6ca7ce |
+ */
|
|
|
c6ca7ce |
+ qcom_domain = kzalloc(sizeof(*qcom_domain), GFP_KERNEL);
|
|
|
c6ca7ce |
+ if (!qcom_domain)
|
|
|
c6ca7ce |
+ return NULL;
|
|
|
c6ca7ce |
+
|
|
|
c6ca7ce |
+ if (type == IOMMU_DOMAIN_DMA &&
|
|
|
c6ca7ce |
+ iommu_get_dma_cookie(&qcom_domain->domain)) {
|
|
|
c6ca7ce |
+ kfree(qcom_domain);
|
|
|
c6ca7ce |
+ return NULL;
|
|
|
c6ca7ce |
+ }
|
|
|
c6ca7ce |
+
|
|
|
c6ca7ce |
+ mutex_init(&qcom_domain->init_mutex);
|
|
|
c6ca7ce |
+ spin_lock_init(&qcom_domain->pgtbl_lock);
|
|
|
c6ca7ce |
+
|
|
|
c6ca7ce |
+ return &qcom_domain->domain;
|
|
|
c6ca7ce |
+}
|
|
|
c6ca7ce |
+
|
|
|
c6ca7ce |
+static void qcom_iommu_domain_free(struct iommu_domain *domain)
|
|
|
c6ca7ce |
+{
|
|
|
c6ca7ce |
+ struct qcom_iommu_domain *qcom_domain = to_qcom_iommu_domain(domain);
|
|
|
c6ca7ce |
+
|
|
|
c6ca7ce |
+ if (WARN_ON(qcom_domain->iommu)) /* forgot to detach? */
|
|
|
c6ca7ce |
+ return;
|
|
|
c6ca7ce |
+
|
|
|
c6ca7ce |
+ iommu_put_dma_cookie(domain);
|
|
|
c6ca7ce |
+
|
|
|
c6ca7ce |
+ /* NOTE: unmap can be called after client device is powered off,
|
|
|
c6ca7ce |
+ * for example, with GPUs or anything involving dma-buf. So we
|
|
|
c6ca7ce |
+ * cannot rely on the device_link. Make sure the IOMMU is on to
|
|
|
c6ca7ce |
+ * avoid unclocked accesses in the TLB inv path:
|
|
|
c6ca7ce |
+ */
|
|
|
c6ca7ce |
+ pm_runtime_get_sync(qcom_domain->iommu->dev);
|
|
|
c6ca7ce |
+
|
|
|
c6ca7ce |
+ free_io_pgtable_ops(qcom_domain->pgtbl_ops);
|
|
|
c6ca7ce |
+
|
|
|
c6ca7ce |
+ pm_runtime_put_sync(qcom_domain->iommu->dev);
|
|
|
c6ca7ce |
+
|
|
|
c6ca7ce |
+ kfree(qcom_domain);
|
|
|
c6ca7ce |
+}
|
|
|
c6ca7ce |
+
|
|
|
c6ca7ce |
+static int qcom_iommu_attach_dev(struct iommu_domain *domain, struct device *dev)
|
|
|
c6ca7ce |
+{
|
|
|
c6ca7ce |
+ struct qcom_iommu_dev *qcom_iommu = to_iommu(dev->iommu_fwspec);
|
|
|
c6ca7ce |
+ struct qcom_iommu_domain *qcom_domain = to_qcom_iommu_domain(domain);
|
|
|
c6ca7ce |
+ int ret;
|
|
|
c6ca7ce |
+
|
|
|
c6ca7ce |
+ if (!qcom_iommu) {
|
|
|
c6ca7ce |
+ dev_err(dev, "cannot attach to IOMMU, is it on the same bus?\n");
|
|
|
c6ca7ce |
+ return -ENXIO;
|
|
|
c6ca7ce |
+ }
|
|
|
c6ca7ce |
+
|
|
|
c6ca7ce |
+ /* Ensure that the domain is finalized */
|
|
|
c6ca7ce |
+ pm_runtime_get_sync(qcom_iommu->dev);
|
|
|
c6ca7ce |
+ ret = qcom_iommu_init_domain(domain, qcom_iommu, dev->iommu_fwspec);
|
|
|
c6ca7ce |
+ pm_runtime_put_sync(qcom_iommu->dev);
|
|
|
c6ca7ce |
+ if (ret < 0)
|
|
|
c6ca7ce |
+ return ret;
|
|
|
c6ca7ce |
+
|
|
|
c6ca7ce |
+ /*
|
|
|
c6ca7ce |
+ * Sanity check the domain. We don't support domains across
|
|
|
c6ca7ce |
+ * different IOMMUs.
|
|
|
c6ca7ce |
+ */
|
|
|
c6ca7ce |
+ if (qcom_domain->iommu != qcom_iommu) {
|
|
|
c6ca7ce |
+ dev_err(dev, "cannot attach to IOMMU %s while already "
|
|
|
c6ca7ce |
+ "attached to domain on IOMMU %s\n",
|
|
|
c6ca7ce |
+ dev_name(qcom_domain->iommu->dev),
|
|
|
c6ca7ce |
+ dev_name(qcom_iommu->dev));
|
|
|
c6ca7ce |
+ return -EINVAL;
|
|
|
c6ca7ce |
+ }
|
|
|
c6ca7ce |
+
|
|
|
c6ca7ce |
+ return 0;
|
|
|
c6ca7ce |
+}
|
|
|
c6ca7ce |
+
|
|
|
c6ca7ce |
+static void qcom_iommu_detach_dev(struct iommu_domain *domain, struct device *dev)
|
|
|
c6ca7ce |
+{
|
|
|
c6ca7ce |
+ struct iommu_fwspec *fwspec = dev->iommu_fwspec;
|
|
|
c6ca7ce |
+ struct qcom_iommu_dev *qcom_iommu = to_iommu(fwspec);
|
|
|
c6ca7ce |
+ struct qcom_iommu_domain *qcom_domain = to_qcom_iommu_domain(domain);
|
|
|
c6ca7ce |
+ unsigned i;
|
|
|
c6ca7ce |
+
|
|
|
c6ca7ce |
+ if (!qcom_domain->iommu)
|
|
|
c6ca7ce |
+ return;
|
|
|
c6ca7ce |
+
|
|
|
c6ca7ce |
+ pm_runtime_get_sync(qcom_iommu->dev);
|
|
|
c6ca7ce |
+ for (i = 0; i < fwspec->num_ids; i++) {
|
|
|
c6ca7ce |
+ struct qcom_iommu_ctx *ctx = to_ctx(fwspec, fwspec->ids[i]);
|
|
|
c6ca7ce |
+
|
|
|
c6ca7ce |
+ /* Disable the context bank: */
|
|
|
c6ca7ce |
+ iommu_writel(ctx, ARM_SMMU_CB_SCTLR, 0);
|
|
|
c6ca7ce |
+ }
|
|
|
c6ca7ce |
+ pm_runtime_put_sync(qcom_iommu->dev);
|
|
|
c6ca7ce |
+
|
|
|
c6ca7ce |
+ qcom_domain->iommu = NULL;
|
|
|
c6ca7ce |
+}
|
|
|
c6ca7ce |
+
|
|
|
c6ca7ce |
+static int qcom_iommu_map(struct iommu_domain *domain, unsigned long iova,
|
|
|
c6ca7ce |
+ phys_addr_t paddr, size_t size, int prot)
|
|
|
c6ca7ce |
+{
|
|
|
c6ca7ce |
+ int ret;
|
|
|
c6ca7ce |
+ unsigned long flags;
|
|
|
c6ca7ce |
+ struct qcom_iommu_domain *qcom_domain = to_qcom_iommu_domain(domain);
|
|
|
c6ca7ce |
+ struct io_pgtable_ops *ops = qcom_domain->pgtbl_ops;
|
|
|
c6ca7ce |
+
|
|
|
c6ca7ce |
+ if (!ops)
|
|
|
c6ca7ce |
+ return -ENODEV;
|
|
|
c6ca7ce |
+
|
|
|
c6ca7ce |
+ spin_lock_irqsave(&qcom_domain->pgtbl_lock, flags);
|
|
|
c6ca7ce |
+ ret = ops->map(ops, iova, paddr, size, prot);
|
|
|
c6ca7ce |
+ spin_unlock_irqrestore(&qcom_domain->pgtbl_lock, flags);
|
|
|
c6ca7ce |
+ return ret;
|
|
|
c6ca7ce |
+}
|
|
|
c6ca7ce |
+
|
|
|
c6ca7ce |
+static size_t qcom_iommu_unmap(struct iommu_domain *domain, unsigned long iova,
|
|
|
c6ca7ce |
+ size_t size)
|
|
|
c6ca7ce |
+{
|
|
|
c6ca7ce |
+ size_t ret;
|
|
|
c6ca7ce |
+ unsigned long flags;
|
|
|
c6ca7ce |
+ struct qcom_iommu_domain *qcom_domain = to_qcom_iommu_domain(domain);
|
|
|
c6ca7ce |
+ struct io_pgtable_ops *ops = qcom_domain->pgtbl_ops;
|
|
|
c6ca7ce |
+
|
|
|
c6ca7ce |
+ if (!ops)
|
|
|
c6ca7ce |
+ return 0;
|
|
|
c6ca7ce |
+
|
|
|
c6ca7ce |
+ /* NOTE: unmap can be called after client device is powered off,
|
|
|
c6ca7ce |
+ * for example, with GPUs or anything involving dma-buf. So we
|
|
|
c6ca7ce |
+ * cannot rely on the device_link. Make sure the IOMMU is on to
|
|
|
c6ca7ce |
+ * avoid unclocked accesses in the TLB inv path:
|
|
|
c6ca7ce |
+ */
|
|
|
c6ca7ce |
+ pm_runtime_get_sync(qcom_domain->iommu->dev);
|
|
|
c6ca7ce |
+ spin_lock_irqsave(&qcom_domain->pgtbl_lock, flags);
|
|
|
c6ca7ce |
+ ret = ops->unmap(ops, iova, size);
|
|
|
c6ca7ce |
+ spin_unlock_irqrestore(&qcom_domain->pgtbl_lock, flags);
|
|
|
c6ca7ce |
+ pm_runtime_put_sync(qcom_domain->iommu->dev);
|
|
|
c6ca7ce |
+
|
|
|
c6ca7ce |
+ return ret;
|
|
|
c6ca7ce |
+}
|
|
|
c6ca7ce |
+
|
|
|
c6ca7ce |
+static phys_addr_t qcom_iommu_iova_to_phys(struct iommu_domain *domain,
|
|
|
c6ca7ce |
+ dma_addr_t iova)
|
|
|
c6ca7ce |
+{
|
|
|
c6ca7ce |
+ phys_addr_t ret;
|
|
|
c6ca7ce |
+ unsigned long flags;
|
|
|
c6ca7ce |
+ struct qcom_iommu_domain *qcom_domain = to_qcom_iommu_domain(domain);
|
|
|
c6ca7ce |
+ struct io_pgtable_ops *ops = qcom_domain->pgtbl_ops;
|
|
|
c6ca7ce |
+
|
|
|
c6ca7ce |
+ if (!ops)
|
|
|
c6ca7ce |
+ return 0;
|
|
|
c6ca7ce |
+
|
|
|
c6ca7ce |
+ spin_lock_irqsave(&qcom_domain->pgtbl_lock, flags);
|
|
|
c6ca7ce |
+ ret = ops->iova_to_phys(ops, iova);
|
|
|
c6ca7ce |
+ spin_unlock_irqrestore(&qcom_domain->pgtbl_lock, flags);
|
|
|
c6ca7ce |
+
|
|
|
c6ca7ce |
+ return ret;
|
|
|
c6ca7ce |
+}
|
|
|
c6ca7ce |
+
|
|
|
c6ca7ce |
+static bool qcom_iommu_capable(enum iommu_cap cap)
|
|
|
c6ca7ce |
+{
|
|
|
c6ca7ce |
+ switch (cap) {
|
|
|
c6ca7ce |
+ case IOMMU_CAP_CACHE_COHERENCY:
|
|
|
c6ca7ce |
+ /*
|
|
|
c6ca7ce |
+ * Return true here as the SMMU can always send out coherent
|
|
|
c6ca7ce |
+ * requests.
|
|
|
c6ca7ce |
+ */
|
|
|
c6ca7ce |
+ return true;
|
|
|
c6ca7ce |
+ case IOMMU_CAP_NOEXEC:
|
|
|
c6ca7ce |
+ return true;
|
|
|
c6ca7ce |
+ default:
|
|
|
c6ca7ce |
+ return false;
|
|
|
c6ca7ce |
+ }
|
|
|
c6ca7ce |
+}
|
|
|
c6ca7ce |
+
|
|
|
c6ca7ce |
+static int qcom_iommu_add_device(struct device *dev)
|
|
|
c6ca7ce |
+{
|
|
|
c6ca7ce |
+ struct qcom_iommu_dev *qcom_iommu = to_iommu(dev->iommu_fwspec);
|
|
|
c6ca7ce |
+ struct iommu_group *group;
|
|
|
c6ca7ce |
+ struct device_link *link;
|
|
|
c6ca7ce |
+
|
|
|
c6ca7ce |
+ if (!qcom_iommu)
|
|
|
c6ca7ce |
+ return -ENODEV;
|
|
|
c6ca7ce |
+
|
|
|
c6ca7ce |
+ /*
|
|
|
c6ca7ce |
+ * Establish the link between iommu and master, so that the
|
|
|
c6ca7ce |
+ * iommu gets runtime enabled/disabled as per the master's
|
|
|
c6ca7ce |
+ * needs.
|
|
|
c6ca7ce |
+ */
|
|
|
c6ca7ce |
+ link = device_link_add(dev, qcom_iommu->dev, DL_FLAG_PM_RUNTIME);
|
|
|
c6ca7ce |
+ if (!link) {
|
|
|
c6ca7ce |
+ dev_err(qcom_iommu->dev, "Unable to create device link between %s and %s\n",
|
|
|
c6ca7ce |
+ dev_name(qcom_iommu->dev), dev_name(dev));
|
|
|
c6ca7ce |
+ return -ENODEV;
|
|
|
c6ca7ce |
+ }
|
|
|
c6ca7ce |
+
|
|
|
c6ca7ce |
+ group = iommu_group_get_for_dev(dev);
|
|
|
c6ca7ce |
+ if (IS_ERR_OR_NULL(group))
|
|
|
c6ca7ce |
+ return PTR_ERR_OR_ZERO(group);
|
|
|
c6ca7ce |
+
|
|
|
c6ca7ce |
+ iommu_group_put(group);
|
|
|
c6ca7ce |
+ iommu_device_link(&qcom_iommu->iommu, dev);
|
|
|
c6ca7ce |
+
|
|
|
c6ca7ce |
+ return 0;
|
|
|
c6ca7ce |
+}
|
|
|
c6ca7ce |
+
|
|
|
c6ca7ce |
+static void qcom_iommu_remove_device(struct device *dev)
|
|
|
c6ca7ce |
+{
|
|
|
c6ca7ce |
+ struct qcom_iommu_dev *qcom_iommu = to_iommu(dev->iommu_fwspec);
|
|
|
c6ca7ce |
+
|
|
|
c6ca7ce |
+ if (!qcom_iommu)
|
|
|
c6ca7ce |
+ return;
|
|
|
c6ca7ce |
+
|
|
|
c6ca7ce |
+ iommu_device_unlink(&qcom_iommu->iommu, dev);
|
|
|
c6ca7ce |
+ iommu_group_remove_device(dev);
|
|
|
c6ca7ce |
+ iommu_fwspec_free(dev);
|
|
|
c6ca7ce |
+}
|
|
|
c6ca7ce |
+
|
|
|
c6ca7ce |
+static int qcom_iommu_of_xlate(struct device *dev, struct of_phandle_args *args)
|
|
|
c6ca7ce |
+{
|
|
|
c6ca7ce |
+ struct qcom_iommu_dev *qcom_iommu;
|
|
|
c6ca7ce |
+ struct platform_device *iommu_pdev;
|
|
|
c6ca7ce |
+ unsigned asid = args->args[0];
|
|
|
c6ca7ce |
+
|
|
|
c6ca7ce |
+ if (args->args_count != 1) {
|
|
|
c6ca7ce |
+ dev_err(dev, "incorrect number of iommu params found for %s "
|
|
|
c6ca7ce |
+ "(found %d, expected 1)\n",
|
|
|
c6ca7ce |
+ args->np->full_name, args->args_count);
|
|
|
c6ca7ce |
+ return -EINVAL;
|
|
|
c6ca7ce |
+ }
|
|
|
c6ca7ce |
+
|
|
|
c6ca7ce |
+ iommu_pdev = of_find_device_by_node(args->np);
|
|
|
c6ca7ce |
+ if (WARN_ON(!iommu_pdev))
|
|
|
c6ca7ce |
+ return -EINVAL;
|
|
|
c6ca7ce |
+
|
|
|
c6ca7ce |
+ qcom_iommu = platform_get_drvdata(iommu_pdev);
|
|
|
c6ca7ce |
+
|
|
|
c6ca7ce |
+ /* make sure the asid specified in dt is valid, so we don't have
|
|
|
c6ca7ce |
+ * to sanity check this elsewhere, since 'asid - 1' is used to
|
|
|
c6ca7ce |
+ * index into qcom_iommu->ctxs:
|
|
|
c6ca7ce |
+ */
|
|
|
c6ca7ce |
+ if (WARN_ON(asid < 1) ||
|
|
|
c6ca7ce |
+ WARN_ON(asid > qcom_iommu->num_ctxs))
|
|
|
c6ca7ce |
+ return -EINVAL;
|
|
|
c6ca7ce |
+
|
|
|
c6ca7ce |
+ if (!dev->iommu_fwspec->iommu_priv) {
|
|
|
c6ca7ce |
+ dev->iommu_fwspec->iommu_priv = qcom_iommu;
|
|
|
c6ca7ce |
+ } else {
|
|
|
c6ca7ce |
+ /* make sure devices iommus dt node isn't referring to
|
|
|
c6ca7ce |
+ * multiple different iommu devices. Multiple context
|
|
|
c6ca7ce |
+ * banks are ok, but multiple devices are not:
|
|
|
c6ca7ce |
+ */
|
|
|
c6ca7ce |
+ if (WARN_ON(qcom_iommu != dev->iommu_fwspec->iommu_priv))
|
|
|
c6ca7ce |
+ return -EINVAL;
|
|
|
c6ca7ce |
+ }
|
|
|
c6ca7ce |
+
|
|
|
c6ca7ce |
+ return iommu_fwspec_add_ids(dev, &asid, 1);
|
|
|
c6ca7ce |
+}
|
|
|
c6ca7ce |
+
|
|
|
c6ca7ce |
+static const struct iommu_ops qcom_iommu_ops = {
|
|
|
c6ca7ce |
+ .capable = qcom_iommu_capable,
|
|
|
c6ca7ce |
+ .domain_alloc = qcom_iommu_domain_alloc,
|
|
|
c6ca7ce |
+ .domain_free = qcom_iommu_domain_free,
|
|
|
c6ca7ce |
+ .attach_dev = qcom_iommu_attach_dev,
|
|
|
c6ca7ce |
+ .detach_dev = qcom_iommu_detach_dev,
|
|
|
c6ca7ce |
+ .map = qcom_iommu_map,
|
|
|
c6ca7ce |
+ .unmap = qcom_iommu_unmap,
|
|
|
c6ca7ce |
+ .map_sg = default_iommu_map_sg,
|
|
|
c6ca7ce |
+ .iova_to_phys = qcom_iommu_iova_to_phys,
|
|
|
c6ca7ce |
+ .add_device = qcom_iommu_add_device,
|
|
|
c6ca7ce |
+ .remove_device = qcom_iommu_remove_device,
|
|
|
c6ca7ce |
+ .device_group = generic_device_group,
|
|
|
c6ca7ce |
+ .of_xlate = qcom_iommu_of_xlate,
|
|
|
c6ca7ce |
+ .pgsize_bitmap = SZ_4K | SZ_64K | SZ_1M | SZ_16M,
|
|
|
c6ca7ce |
+};
|
|
|
c6ca7ce |
+
|
|
|
c6ca7ce |
+static int qcom_iommu_enable_clocks(struct qcom_iommu_dev *qcom_iommu)
|
|
|
c6ca7ce |
+{
|
|
|
c6ca7ce |
+ int ret;
|
|
|
c6ca7ce |
+
|
|
|
c6ca7ce |
+ ret = clk_prepare_enable(qcom_iommu->iface_clk);
|
|
|
c6ca7ce |
+ if (ret) {
|
|
|
c6ca7ce |
+ dev_err(qcom_iommu->dev, "Couldn't enable iface_clk\n");
|
|
|
c6ca7ce |
+ return ret;
|
|
|
c6ca7ce |
+ }
|
|
|
c6ca7ce |
+
|
|
|
c6ca7ce |
+ ret = clk_prepare_enable(qcom_iommu->bus_clk);
|
|
|
c6ca7ce |
+ if (ret) {
|
|
|
c6ca7ce |
+ dev_err(qcom_iommu->dev, "Couldn't enable bus_clk\n");
|
|
|
c6ca7ce |
+ clk_disable_unprepare(qcom_iommu->iface_clk);
|
|
|
c6ca7ce |
+ return ret;
|
|
|
c6ca7ce |
+ }
|
|
|
c6ca7ce |
+
|
|
|
c6ca7ce |
+ return 0;
|
|
|
c6ca7ce |
+}
|
|
|
c6ca7ce |
+
|
|
|
c6ca7ce |
+static void qcom_iommu_disable_clocks(struct qcom_iommu_dev *qcom_iommu)
|
|
|
c6ca7ce |
+{
|
|
|
c6ca7ce |
+ clk_disable_unprepare(qcom_iommu->bus_clk);
|
|
|
c6ca7ce |
+ clk_disable_unprepare(qcom_iommu->iface_clk);
|
|
|
c6ca7ce |
+}
|
|
|
c6ca7ce |
+
|
|
|
c6ca7ce |
+static int get_asid(const struct device_node *np)
|
|
|
c6ca7ce |
+{
|
|
|
c6ca7ce |
+ u32 reg;
|
|
|
c6ca7ce |
+
|
|
|
c6ca7ce |
+ /* read the "reg" property directly to get the relative address
|
|
|
c6ca7ce |
+ * of the context bank, and calculate the asid from that:
|
|
|
c6ca7ce |
+ */
|
|
|
c6ca7ce |
+ if (of_property_read_u32_index(np, "reg", 0, ®))
|
|
|
c6ca7ce |
+ return -ENODEV;
|
|
|
c6ca7ce |
+
|
|
|
c6ca7ce |
+ return reg / 0x1000; /* context banks are 0x1000 apart */
|
|
|
c6ca7ce |
+}
|
|
|
c6ca7ce |
+
|
|
|
c6ca7ce |
+static int qcom_iommu_ctx_probe(struct platform_device *pdev)
|
|
|
c6ca7ce |
+{
|
|
|
c6ca7ce |
+ struct qcom_iommu_ctx *ctx;
|
|
|
c6ca7ce |
+ struct device *dev = &pdev->dev;
|
|
|
c6ca7ce |
+ struct qcom_iommu_dev *qcom_iommu = dev_get_drvdata(dev->parent);
|
|
|
c6ca7ce |
+ struct resource *res;
|
|
|
c6ca7ce |
+ int ret, irq;
|
|
|
c6ca7ce |
+
|
|
|
c6ca7ce |
+ ctx = devm_kzalloc(dev, sizeof(*ctx), GFP_KERNEL);
|
|
|
c6ca7ce |
+ if (!ctx)
|
|
|
c6ca7ce |
+ return -ENOMEM;
|
|
|
c6ca7ce |
+
|
|
|
c6ca7ce |
+ ctx->dev = dev;
|
|
|
c6ca7ce |
+ platform_set_drvdata(pdev, ctx);
|
|
|
c6ca7ce |
+
|
|
|
c6ca7ce |
+ res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
|
|
|
c6ca7ce |
+ ctx->base = devm_ioremap_resource(dev, res);
|
|
|
c6ca7ce |
+ if (IS_ERR(ctx->base))
|
|
|
c6ca7ce |
+ return PTR_ERR(ctx->base);
|
|
|
c6ca7ce |
+
|
|
|
c6ca7ce |
+ irq = platform_get_irq(pdev, 0);
|
|
|
c6ca7ce |
+ if (irq < 0) {
|
|
|
c6ca7ce |
+ dev_err(dev, "failed to get irq\n");
|
|
|
c6ca7ce |
+ return -ENODEV;
|
|
|
c6ca7ce |
+ }
|
|
|
c6ca7ce |
+
|
|
|
c6ca7ce |
+ /* clear IRQs before registering fault handler, just in case the
|
|
|
c6ca7ce |
+ * boot-loader left us a surprise:
|
|
|
c6ca7ce |
+ */
|
|
|
c6ca7ce |
+ iommu_writel(ctx, ARM_SMMU_CB_FSR, iommu_readl(ctx, ARM_SMMU_CB_FSR));
|
|
|
c6ca7ce |
+
|
|
|
c6ca7ce |
+ ret = devm_request_irq(dev, irq,
|
|
|
c6ca7ce |
+ qcom_iommu_fault,
|
|
|
c6ca7ce |
+ IRQF_SHARED,
|
|
|
c6ca7ce |
+ "qcom-iommu-fault",
|
|
|
c6ca7ce |
+ ctx);
|
|
|
c6ca7ce |
+ if (ret) {
|
|
|
c6ca7ce |
+ dev_err(dev, "failed to request IRQ %u\n", irq);
|
|
|
c6ca7ce |
+ return ret;
|
|
|
c6ca7ce |
+ }
|
|
|
c6ca7ce |
+
|
|
|
c6ca7ce |
+ ret = get_asid(dev->of_node);
|
|
|
c6ca7ce |
+ if (ret < 0) {
|
|
|
c6ca7ce |
+ dev_err(dev, "missing reg property\n");
|
|
|
c6ca7ce |
+ return ret;
|
|
|
c6ca7ce |
+ }
|
|
|
c6ca7ce |
+
|
|
|
c6ca7ce |
+ ctx->asid = ret;
|
|
|
c6ca7ce |
+
|
|
|
c6ca7ce |
+ dev_dbg(dev, "found asid %u\n", ctx->asid);
|
|
|
c6ca7ce |
+
|
|
|
c6ca7ce |
+ qcom_iommu->ctxs[ctx->asid - 1] = ctx;
|
|
|
c6ca7ce |
+
|
|
|
c6ca7ce |
+ return 0;
|
|
|
c6ca7ce |
+}
|
|
|
c6ca7ce |
+
|
|
|
c6ca7ce |
+static int qcom_iommu_ctx_remove(struct platform_device *pdev)
|
|
|
c6ca7ce |
+{
|
|
|
c6ca7ce |
+ struct qcom_iommu_dev *qcom_iommu = dev_get_drvdata(pdev->dev.parent);
|
|
|
c6ca7ce |
+ struct qcom_iommu_ctx *ctx = platform_get_drvdata(pdev);
|
|
|
c6ca7ce |
+
|
|
|
c6ca7ce |
+ platform_set_drvdata(pdev, NULL);
|
|
|
c6ca7ce |
+
|
|
|
c6ca7ce |
+ qcom_iommu->ctxs[ctx->asid - 1] = NULL;
|
|
|
c6ca7ce |
+
|
|
|
c6ca7ce |
+ return 0;
|
|
|
c6ca7ce |
+}
|
|
|
c6ca7ce |
+
|
|
|
c6ca7ce |
+static const struct of_device_id ctx_of_match[] = {
|
|
|
c6ca7ce |
+ { .compatible = "qcom,msm-iommu-v1-ns" },
|
|
|
c6ca7ce |
+ { .compatible = "qcom,msm-iommu-v1-sec" },
|
|
|
c6ca7ce |
+ { /* sentinel */ }
|
|
|
c6ca7ce |
+};
|
|
|
c6ca7ce |
+
|
|
|
c6ca7ce |
+static struct platform_driver qcom_iommu_ctx_driver = {
|
|
|
c6ca7ce |
+ .driver = {
|
|
|
c6ca7ce |
+ .name = "qcom-iommu-ctx",
|
|
|
c6ca7ce |
+ .of_match_table = of_match_ptr(ctx_of_match),
|
|
|
c6ca7ce |
+ },
|
|
|
c6ca7ce |
+ .probe = qcom_iommu_ctx_probe,
|
|
|
c6ca7ce |
+ .remove = qcom_iommu_ctx_remove,
|
|
|
c6ca7ce |
+};
|
|
|
c6ca7ce |
+
|
|
|
c6ca7ce |
+static int qcom_iommu_device_probe(struct platform_device *pdev)
|
|
|
c6ca7ce |
+{
|
|
|
c6ca7ce |
+ struct device_node *child;
|
|
|
c6ca7ce |
+ struct qcom_iommu_dev *qcom_iommu;
|
|
|
c6ca7ce |
+ struct device *dev = &pdev->dev;
|
|
|
c6ca7ce |
+ struct resource *res;
|
|
|
c6ca7ce |
+ int ret, sz, max_asid = 0;
|
|
|
c6ca7ce |
+
|
|
|
c6ca7ce |
+ /* find the max asid (which is 1:1 to ctx bank idx), so we know how
|
|
|
c6ca7ce |
+ * many child ctx devices we have:
|
|
|
c6ca7ce |
+ */
|
|
|
c6ca7ce |
+ for_each_child_of_node(dev->of_node, child)
|
|
|
c6ca7ce |
+ max_asid = max(max_asid, get_asid(child));
|
|
|
c6ca7ce |
+
|
|
|
c6ca7ce |
+ sz = sizeof(*qcom_iommu) + (max_asid * sizeof(qcom_iommu->ctxs[0]));
|
|
|
c6ca7ce |
+
|
|
|
c6ca7ce |
+ qcom_iommu = devm_kzalloc(dev, sz, GFP_KERNEL);
|
|
|
c6ca7ce |
+ if (!qcom_iommu)
|
|
|
c6ca7ce |
+ return -ENOMEM;
|
|
|
c6ca7ce |
+ qcom_iommu->num_ctxs = max_asid;
|
|
|
c6ca7ce |
+ qcom_iommu->dev = dev;
|
|
|
c6ca7ce |
+
|
|
|
c6ca7ce |
+ res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
|
|
|
c6ca7ce |
+ if (res)
|
|
|
c6ca7ce |
+ qcom_iommu->local_base = devm_ioremap_resource(dev, res);
|
|
|
c6ca7ce |
+
|
|
|
c6ca7ce |
+ qcom_iommu->iface_clk = devm_clk_get(dev, "iface");
|
|
|
c6ca7ce |
+ if (IS_ERR(qcom_iommu->iface_clk)) {
|
|
|
c6ca7ce |
+ dev_err(dev, "failed to get iface clock\n");
|
|
|
c6ca7ce |
+ return PTR_ERR(qcom_iommu->iface_clk);
|
|
|
c6ca7ce |
+ }
|
|
|
c6ca7ce |
+
|
|
|
c6ca7ce |
+ qcom_iommu->bus_clk = devm_clk_get(dev, "bus");
|
|
|
c6ca7ce |
+ if (IS_ERR(qcom_iommu->bus_clk)) {
|
|
|
c6ca7ce |
+ dev_err(dev, "failed to get bus clock\n");
|
|
|
c6ca7ce |
+ return PTR_ERR(qcom_iommu->bus_clk);
|
|
|
c6ca7ce |
+ }
|
|
|
c6ca7ce |
+
|
|
|
c6ca7ce |
+ if (of_property_read_u32(dev->of_node, "qcom,iommu-secure-id",
|
|
|
c6ca7ce |
+ &qcom_iommu->sec_id)) {
|
|
|
c6ca7ce |
+ dev_err(dev, "missing qcom,iommu-secure-id property\n");
|
|
|
c6ca7ce |
+ return -ENODEV;
|
|
|
c6ca7ce |
+ }
|
|
|
c6ca7ce |
+
|
|
|
c6ca7ce |
+ platform_set_drvdata(pdev, qcom_iommu);
|
|
|
c6ca7ce |
+
|
|
|
c6ca7ce |
+ pm_runtime_enable(dev);
|
|
|
c6ca7ce |
+
|
|
|
c6ca7ce |
+ /* register context bank devices, which are child nodes: */
|
|
|
c6ca7ce |
+ ret = devm_of_platform_populate(dev);
|
|
|
c6ca7ce |
+ if (ret) {
|
|
|
c6ca7ce |
+ dev_err(dev, "Failed to populate iommu contexts\n");
|
|
|
c6ca7ce |
+ return ret;
|
|
|
c6ca7ce |
+ }
|
|
|
c6ca7ce |
+
|
|
|
c6ca7ce |
+ ret = iommu_device_sysfs_add(&qcom_iommu->iommu, dev, NULL,
|
|
|
c6ca7ce |
+ dev_name(dev));
|
|
|
c6ca7ce |
+ if (ret) {
|
|
|
c6ca7ce |
+ dev_err(dev, "Failed to register iommu in sysfs\n");
|
|
|
c6ca7ce |
+ return ret;
|
|
|
c6ca7ce |
+ }
|
|
|
c6ca7ce |
+
|
|
|
c6ca7ce |
+ iommu_device_set_ops(&qcom_iommu->iommu, &qcom_iommu_ops);
|
|
|
c6ca7ce |
+ iommu_device_set_fwnode(&qcom_iommu->iommu, dev->fwnode);
|
|
|
c6ca7ce |
+
|
|
|
c6ca7ce |
+ ret = iommu_device_register(&qcom_iommu->iommu);
|
|
|
c6ca7ce |
+ if (ret) {
|
|
|
c6ca7ce |
+ dev_err(dev, "Failed to register iommu\n");
|
|
|
c6ca7ce |
+ return ret;
|
|
|
c6ca7ce |
+ }
|
|
|
c6ca7ce |
+
|
|
|
c6ca7ce |
+ bus_set_iommu(&platform_bus_type, &qcom_iommu_ops);
|
|
|
c6ca7ce |
+
|
|
|
c6ca7ce |
+ if (qcom_iommu->local_base) {
|
|
|
c6ca7ce |
+ pm_runtime_get_sync(dev);
|
|
|
c6ca7ce |
+ writel_relaxed(0xffffffff, qcom_iommu->local_base + SMMU_INTR_SEL_NS);
|
|
|
c6ca7ce |
+ pm_runtime_put_sync(dev);
|
|
|
c6ca7ce |
+ }
|
|
|
c6ca7ce |
+
|
|
|
c6ca7ce |
+ return 0;
|
|
|
c6ca7ce |
+}
|
|
|
c6ca7ce |
+
|
|
|
c6ca7ce |
+static int qcom_iommu_device_remove(struct platform_device *pdev)
|
|
|
c6ca7ce |
+{
|
|
|
c6ca7ce |
+ struct qcom_iommu_dev *qcom_iommu = platform_get_drvdata(pdev);
|
|
|
c6ca7ce |
+
|
|
|
c6ca7ce |
+ bus_set_iommu(&platform_bus_type, NULL);
|
|
|
c6ca7ce |
+
|
|
|
c6ca7ce |
+ pm_runtime_force_suspend(&pdev->dev);
|
|
|
c6ca7ce |
+ platform_set_drvdata(pdev, NULL);
|
|
|
c6ca7ce |
+ iommu_device_sysfs_remove(&qcom_iommu->iommu);
|
|
|
c6ca7ce |
+ iommu_device_unregister(&qcom_iommu->iommu);
|
|
|
c6ca7ce |
+
|
|
|
c6ca7ce |
+ return 0;
|
|
|
c6ca7ce |
+}
|
|
|
c6ca7ce |
+
|
|
|
c6ca7ce |
+#ifdef CONFIG_PM
|
|
|
c6ca7ce |
+static int qcom_iommu_resume(struct device *dev)
|
|
|
c6ca7ce |
+{
|
|
|
c6ca7ce |
+ struct platform_device *pdev = to_platform_device(dev);
|
|
|
c6ca7ce |
+ struct qcom_iommu_dev *qcom_iommu = platform_get_drvdata(pdev);
|
|
|
c6ca7ce |
+
|
|
|
c6ca7ce |
+ return qcom_iommu_enable_clocks(qcom_iommu);
|
|
|
c6ca7ce |
+}
|
|
|
c6ca7ce |
+
|
|
|
c6ca7ce |
+static int qcom_iommu_suspend(struct device *dev)
|
|
|
c6ca7ce |
+{
|
|
|
c6ca7ce |
+ struct platform_device *pdev = to_platform_device(dev);
|
|
|
c6ca7ce |
+ struct qcom_iommu_dev *qcom_iommu = platform_get_drvdata(pdev);
|
|
|
c6ca7ce |
+
|
|
|
c6ca7ce |
+ qcom_iommu_disable_clocks(qcom_iommu);
|
|
|
c6ca7ce |
+
|
|
|
c6ca7ce |
+ return 0;
|
|
|
c6ca7ce |
+}
|
|
|
c6ca7ce |
+#endif
|
|
|
c6ca7ce |
+
|
|
|
c6ca7ce |
+static const struct dev_pm_ops qcom_iommu_pm_ops = {
|
|
|
c6ca7ce |
+ SET_RUNTIME_PM_OPS(qcom_iommu_suspend, qcom_iommu_resume, NULL)
|
|
|
c6ca7ce |
+ SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend,
|
|
|
c6ca7ce |
+ pm_runtime_force_resume)
|
|
|
c6ca7ce |
+};
|
|
|
c6ca7ce |
+
|
|
|
c6ca7ce |
+static const struct of_device_id qcom_iommu_of_match[] = {
|
|
|
c6ca7ce |
+ { .compatible = "qcom,msm-iommu-v1" },
|
|
|
c6ca7ce |
+ { /* sentinel */ }
|
|
|
c6ca7ce |
+};
|
|
|
c6ca7ce |
+MODULE_DEVICE_TABLE(of, qcom_iommu_of_match);
|
|
|
c6ca7ce |
+
|
|
|
c6ca7ce |
+static struct platform_driver qcom_iommu_driver = {
|
|
|
c6ca7ce |
+ .driver = {
|
|
|
c6ca7ce |
+ .name = "qcom-iommu",
|
|
|
c6ca7ce |
+ .of_match_table = of_match_ptr(qcom_iommu_of_match),
|
|
|
c6ca7ce |
+ .pm = &qcom_iommu_pm_ops,
|
|
|
c6ca7ce |
+ },
|
|
|
c6ca7ce |
+ .probe = qcom_iommu_device_probe,
|
|
|
c6ca7ce |
+ .remove = qcom_iommu_device_remove,
|
|
|
c6ca7ce |
+};
|
|
|
c6ca7ce |
+
|
|
|
c6ca7ce |
+static int __init qcom_iommu_init(void)
|
|
|
c6ca7ce |
+{
|
|
|
c6ca7ce |
+ int ret;
|
|
|
c6ca7ce |
+
|
|
|
c6ca7ce |
+ ret = platform_driver_register(&qcom_iommu_ctx_driver);
|
|
|
c6ca7ce |
+ if (ret)
|
|
|
c6ca7ce |
+ return ret;
|
|
|
c6ca7ce |
+
|
|
|
c6ca7ce |
+ ret = platform_driver_register(&qcom_iommu_driver);
|
|
|
c6ca7ce |
+ if (ret)
|
|
|
c6ca7ce |
+ platform_driver_unregister(&qcom_iommu_ctx_driver);
|
|
|
c6ca7ce |
+
|
|
|
c6ca7ce |
+ return ret;
|
|
|
c6ca7ce |
+}
|
|
|
c6ca7ce |
+
|
|
|
c6ca7ce |
+static void __exit qcom_iommu_exit(void)
|
|
|
c6ca7ce |
+{
|
|
|
c6ca7ce |
+ platform_driver_unregister(&qcom_iommu_driver);
|
|
|
c6ca7ce |
+ platform_driver_unregister(&qcom_iommu_ctx_driver);
|
|
|
c6ca7ce |
+}
|
|
|
c6ca7ce |
+
|
|
|
c6ca7ce |
+module_init(qcom_iommu_init);
|
|
|
c6ca7ce |
+module_exit(qcom_iommu_exit);
|
|
|
c6ca7ce |
+
|
|
|
c6ca7ce |
+IOMMU_OF_DECLARE(qcom_iommu_dev, "qcom,msm-iommu-v1", NULL);
|
|
|
c6ca7ce |
+
|
|
|
c6ca7ce |
+MODULE_DESCRIPTION("IOMMU API for QCOM IOMMU v1 implementations");
|
|
|
c6ca7ce |
+MODULE_LICENSE("GPL v2");
|
|
|
c6ca7ce |
From patchwork Thu Jul 13 12:07:47 2017
|
|
|
c6ca7ce |
Content-Type: text/plain; charset="utf-8"
|
|
|
c6ca7ce |
MIME-Version: 1.0
|
|
|
c6ca7ce |
Content-Transfer-Encoding: 7bit
|
|
|
c6ca7ce |
Subject: [RESEND,4/4] iommu: qcom: initialize secure page table
|
|
|
c6ca7ce |
From: Rob Clark <robdclark@gmail.com>
|
|
|
c6ca7ce |
X-Patchwork-Id: 9838373
|
|
|
c6ca7ce |
Message-Id: <20170713120747.20490-5-robdclark@gmail.com>
|
|
|
c6ca7ce |
To: iommu@lists.linux-foundation.org
|
|
|
c6ca7ce |
Cc: linux-arm-msm@vger.kernel.org, Archit Taneja <architt@codeaurora.org>,
|
|
|
c6ca7ce |
Rob Herring <robh@kernel.org>, Will Deacon <will.deacon@arm.com>,
|
|
|
c6ca7ce |
Sricharan <sricharan@codeaurora.org>,
|
|
|
c6ca7ce |
Mark Rutland <mark.rutland@arm.com>, Robin Murphy <robin.murphy@arm.com>,
|
|
|
c6ca7ce |
Stanimir Varbanov <stanimir.varbanov@linaro.org>,
|
|
|
c6ca7ce |
Rob Clark <robdclark@gmail.com>
|
|
|
c6ca7ce |
Date: Thu, 13 Jul 2017 08:07:47 -0400
|
|
|
c6ca7ce |
|
|
|
c6ca7ce |
From: Stanimir Varbanov <stanimir.varbanov@linaro.org>
|
|
|
c6ca7ce |
|
|
|
c6ca7ce |
This basically gets the secure page table size, allocates memory for
|
|
|
c6ca7ce |
secure pagetables and passes the physical address to the trusted zone.
|
|
|
c6ca7ce |
|
|
|
c6ca7ce |
Signed-off-by: Stanimir Varbanov <stanimir.varbanov@linaro.org>
|
|
|
c6ca7ce |
Signed-off-by: Rob Clark <robdclark@gmail.com>
|
|
|
c6ca7ce |
---
|
|
|
c6ca7ce |
drivers/iommu/qcom_iommu.c | 64 ++++++++++++++++++++++++++++++++++++++++++++++
|
|
|
c6ca7ce |
1 file changed, 64 insertions(+)
|
|
|
c6ca7ce |
|
|
|
c6ca7ce |
diff --git a/drivers/iommu/qcom_iommu.c b/drivers/iommu/qcom_iommu.c
|
|
|
c6ca7ce |
index 860cad1cb167..48b62aa52787 100644
|
|
|
c6ca7ce |
--- a/drivers/iommu/qcom_iommu.c
|
|
|
c6ca7ce |
+++ b/drivers/iommu/qcom_iommu.c
|
|
|
c6ca7ce |
@@ -604,6 +604,51 @@ static void qcom_iommu_disable_clocks(struct qcom_iommu_dev *qcom_iommu)
|
|
|
c6ca7ce |
clk_disable_unprepare(qcom_iommu->iface_clk);
|
|
|
c6ca7ce |
}
|
|
|
c6ca7ce |
|
|
|
c6ca7ce |
+static int qcom_iommu_sec_ptbl_init(struct device *dev)
|
|
|
c6ca7ce |
+{
|
|
|
c6ca7ce |
+ size_t psize = 0;
|
|
|
c6ca7ce |
+ unsigned int spare = 0;
|
|
|
c6ca7ce |
+ void *cpu_addr;
|
|
|
c6ca7ce |
+ dma_addr_t paddr;
|
|
|
c6ca7ce |
+ unsigned long attrs;
|
|
|
c6ca7ce |
+ static bool allocated = false;
|
|
|
c6ca7ce |
+ int ret;
|
|
|
c6ca7ce |
+
|
|
|
c6ca7ce |
+ if (allocated)
|
|
|
c6ca7ce |
+ return 0;
|
|
|
c6ca7ce |
+
|
|
|
c6ca7ce |
+ ret = qcom_scm_iommu_secure_ptbl_size(spare, &psize);
|
|
|
c6ca7ce |
+ if (ret) {
|
|
|
c6ca7ce |
+ dev_err(dev, "failed to get iommu secure pgtable size (%d)\n",
|
|
|
c6ca7ce |
+ ret);
|
|
|
c6ca7ce |
+ return ret;
|
|
|
c6ca7ce |
+ }
|
|
|
c6ca7ce |
+
|
|
|
c6ca7ce |
+ dev_info(dev, "iommu sec: pgtable size: %zu\n", psize);
|
|
|
c6ca7ce |
+
|
|
|
c6ca7ce |
+ attrs = DMA_ATTR_NO_KERNEL_MAPPING;
|
|
|
c6ca7ce |
+
|
|
|
c6ca7ce |
+ cpu_addr = dma_alloc_attrs(dev, psize, &paddr, GFP_KERNEL, attrs);
|
|
|
c6ca7ce |
+ if (!cpu_addr) {
|
|
|
c6ca7ce |
+ dev_err(dev, "failed to allocate %zu bytes for pgtable\n",
|
|
|
c6ca7ce |
+ psize);
|
|
|
c6ca7ce |
+ return -ENOMEM;
|
|
|
c6ca7ce |
+ }
|
|
|
c6ca7ce |
+
|
|
|
c6ca7ce |
+ ret = qcom_scm_iommu_secure_ptbl_init(paddr, psize, spare);
|
|
|
c6ca7ce |
+ if (ret) {
|
|
|
c6ca7ce |
+ dev_err(dev, "failed to init iommu pgtable (%d)\n", ret);
|
|
|
c6ca7ce |
+ goto free_mem;
|
|
|
c6ca7ce |
+ }
|
|
|
c6ca7ce |
+
|
|
|
c6ca7ce |
+ allocated = true;
|
|
|
c6ca7ce |
+ return 0;
|
|
|
c6ca7ce |
+
|
|
|
c6ca7ce |
+free_mem:
|
|
|
c6ca7ce |
+ dma_free_attrs(dev, psize, cpu_addr, paddr, attrs);
|
|
|
c6ca7ce |
+ return ret;
|
|
|
c6ca7ce |
+}
|
|
|
c6ca7ce |
+
|
|
|
c6ca7ce |
static int get_asid(const struct device_node *np)
|
|
|
c6ca7ce |
{
|
|
|
c6ca7ce |
u32 reg;
|
|
|
c6ca7ce |
@@ -700,6 +745,17 @@ static struct platform_driver qcom_iommu_ctx_driver = {
|
|
|
c6ca7ce |
.remove = qcom_iommu_ctx_remove,
|
|
|
c6ca7ce |
};
|
|
|
c6ca7ce |
|
|
|
c6ca7ce |
+static bool qcom_iommu_has_secure_context(struct qcom_iommu_dev *qcom_iommu)
|
|
|
c6ca7ce |
+{
|
|
|
c6ca7ce |
+ struct device_node *child;
|
|
|
c6ca7ce |
+
|
|
|
c6ca7ce |
+ for_each_child_of_node(qcom_iommu->dev->of_node, child)
|
|
|
c6ca7ce |
+ if (of_device_is_compatible(child, "qcom,msm-iommu-v1-sec"))
|
|
|
c6ca7ce |
+ return true;
|
|
|
c6ca7ce |
+
|
|
|
c6ca7ce |
+ return false;
|
|
|
c6ca7ce |
+}
|
|
|
c6ca7ce |
+
|
|
|
c6ca7ce |
static int qcom_iommu_device_probe(struct platform_device *pdev)
|
|
|
c6ca7ce |
{
|
|
|
c6ca7ce |
struct device_node *child;
|
|
|
c6ca7ce |
@@ -744,6 +800,14 @@ static int qcom_iommu_device_probe(struct platform_device *pdev)
|
|
|
c6ca7ce |
return -ENODEV;
|
|
|
c6ca7ce |
}
|
|
|
c6ca7ce |
|
|
|
c6ca7ce |
+ if (qcom_iommu_has_secure_context(qcom_iommu)) {
|
|
|
c6ca7ce |
+ ret = qcom_iommu_sec_ptbl_init(dev);
|
|
|
c6ca7ce |
+ if (ret) {
|
|
|
c6ca7ce |
+ dev_err(dev, "cannot init secure pg table(%d)\n", ret);
|
|
|
c6ca7ce |
+ return ret;
|
|
|
c6ca7ce |
+ }
|
|
|
c6ca7ce |
+ }
|
|
|
c6ca7ce |
+
|
|
|
c6ca7ce |
platform_set_drvdata(pdev, qcom_iommu);
|
|
|
c6ca7ce |
|
|
|
c6ca7ce |
pm_runtime_enable(dev);
|
|
|
c6ca7ce |
From patchwork Mon Jun 12 12:43:15 2017
|
|
|
c6ca7ce |
Content-Type: text/plain; charset="utf-8"
|
|
|
c6ca7ce |
MIME-Version: 1.0
|
|
|
c6ca7ce |
Content-Transfer-Encoding: 7bit
|
|
|
c6ca7ce |
Subject: [1/3] ARM64: DT: add gpu for msm8916
|
|
|
c6ca7ce |
From: Rob Clark <robdclark@gmail.com>
|
|
|
c6ca7ce |
X-Patchwork-Id: 9781057
|
|
|
c6ca7ce |
Message-Id: <20170612124317.29313-1-robdclark@gmail.com>
|
|
|
c6ca7ce |
To: linux-arm-msm@vger.kernel.org
|
|
|
c6ca7ce |
Cc: Stephen Boyd <sboyd@codeaurora.org>, Andy Gross <agross@codeaurora.org>,
|
|
|
c6ca7ce |
Stanimir Varbanov <stanimir.varbanov@linaro.org>,
|
|
|
c6ca7ce |
Rob Clark <robdclark@gmail.com>
|
|
|
c6ca7ce |
Date: Mon, 12 Jun 2017 08:43:15 -0400
|
|
|
c6ca7ce |
|
|
|
c6ca7ce |
Signed-off-by: Rob Clark <robdclark@gmail.com>
|
|
|
c6ca7ce |
Reviewed-by: Stephen Boyd <sboyd@codeaurora.org>
|
|
|
c6ca7ce |
---
|
|
|
c6ca7ce |
arch/arm64/boot/dts/qcom/msm8916.dtsi | 35 +++++++++++++++++++++++++++++++++++
|
|
|
c6ca7ce |
1 file changed, 35 insertions(+)
|
|
|
c6ca7ce |
|
|
|
c6ca7ce |
diff --git a/arch/arm64/boot/dts/qcom/msm8916.dtsi b/arch/arm64/boot/dts/qcom/msm8916.dtsi
|
|
|
c6ca7ce |
index ab30939..24c24ab 100644
|
|
|
c6ca7ce |
--- a/arch/arm64/boot/dts/qcom/msm8916.dtsi
|
|
|
c6ca7ce |
+++ b/arch/arm64/boot/dts/qcom/msm8916.dtsi
|
|
|
c6ca7ce |
@@ -204,6 +204,17 @@
|
|
|
c6ca7ce |
|
|
|
c6ca7ce |
};
|
|
|
c6ca7ce |
|
|
|
c6ca7ce |
+ gpu_opp_table: opp_table {
|
|
|
c6ca7ce |
+ compatible = "operating-points-v2";
|
|
|
c6ca7ce |
+
|
|
|
c6ca7ce |
+ opp-400000000 {
|
|
|
c6ca7ce |
+ opp-hz = /bits/ 64 <400000000>;
|
|
|
c6ca7ce |
+ };
|
|
|
c6ca7ce |
+ opp-19200000 {
|
|
|
c6ca7ce |
+ opp-hz = /bits/ 64 <19200000>;
|
|
|
c6ca7ce |
+ };
|
|
|
c6ca7ce |
+ };
|
|
|
c6ca7ce |
+
|
|
|
c6ca7ce |
timer {
|
|
|
c6ca7ce |
compatible = "arm,armv8-timer";
|
|
|
c6ca7ce |
interrupts = <GIC_PPI 2 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
|
|
|
c6ca7ce |
@@ -698,6 +709,30 @@
|
|
|
c6ca7ce |
#thermal-sensor-cells = <1>;
|
|
|
c6ca7ce |
};
|
|
|
c6ca7ce |
|
|
|
c6ca7ce |
+ gpu@1c00000 {
|
|
|
c6ca7ce |
+ compatible = "qcom,adreno-306.0", "qcom,adreno";
|
|
|
c6ca7ce |
+ reg = <0x01c00000 0x20000>;
|
|
|
c6ca7ce |
+ reg-names = "kgsl_3d0_reg_memory";
|
|
|
c6ca7ce |
+ interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
|
|
|
c6ca7ce |
+ interrupt-names = "kgsl_3d0_irq";
|
|
|
c6ca7ce |
+ clock-names =
|
|
|
c6ca7ce |
+ "core",
|
|
|
c6ca7ce |
+ "iface",
|
|
|
c6ca7ce |
+ "mem",
|
|
|
c6ca7ce |
+ "mem_iface",
|
|
|
c6ca7ce |
+ "alt_mem_iface",
|
|
|
c6ca7ce |
+ "gfx3d";
|
|
|
c6ca7ce |
+ clocks =
|
|
|
c6ca7ce |
+ <&gcc GCC_OXILI_GFX3D_CLK>,
|
|
|
c6ca7ce |
+ <&gcc GCC_OXILI_AHB_CLK>,
|
|
|
c6ca7ce |
+ <&gcc GCC_OXILI_GMEM_CLK>,
|
|
|
c6ca7ce |
+ <&gcc GCC_BIMC_GFX_CLK>,
|
|
|
c6ca7ce |
+ <&gcc GCC_BIMC_GPU_CLK>,
|
|
|
c6ca7ce |
+ <&gcc GFX3D_CLK_SRC>;
|
|
|
c6ca7ce |
+ power-domains = <&gcc OXILI_GDSC>;
|
|
|
c6ca7ce |
+ operating-points-v2 = <&gpu_opp_table>;
|
|
|
c6ca7ce |
+ };
|
|
|
c6ca7ce |
+
|
|
|
c6ca7ce |
mdss: mdss@1a00000 {
|
|
|
c6ca7ce |
compatible = "qcom,mdss";
|
|
|
c6ca7ce |
reg = <0x1a00000 0x1000>,
|
|
|
c6ca7ce |
From patchwork Mon Jun 12 12:43:16 2017
|
|
|
c6ca7ce |
Content-Type: text/plain; charset="utf-8"
|
|
|
c6ca7ce |
MIME-Version: 1.0
|
|
|
c6ca7ce |
Content-Transfer-Encoding: 7bit
|
|
|
c6ca7ce |
Subject: [2/3] ARM64: DT: add video codec devicetree node
|
|
|
c6ca7ce |
From: Rob Clark <robdclark@gmail.com>
|
|
|
c6ca7ce |
X-Patchwork-Id: 9781059
|
|
|
c6ca7ce |
Message-Id: <20170612124317.29313-2-robdclark@gmail.com>
|
|
|
c6ca7ce |
To: linux-arm-msm@vger.kernel.org
|
|
|
c6ca7ce |
Cc: Stephen Boyd <sboyd@codeaurora.org>, Andy Gross <agross@codeaurora.org>,
|
|
|
c6ca7ce |
Stanimir Varbanov <stanimir.varbanov@linaro.org>,
|
|
|
c6ca7ce |
Rob Clark <robdclark@gmail.com>
|
|
|
c6ca7ce |
Date: Mon, 12 Jun 2017 08:43:16 -0400
|
|
|
c6ca7ce |
|
|
|
c6ca7ce |
From: Stanimir Varbanov <stanimir.varbanov@linaro.org>
|
|
|
c6ca7ce |
|
|
|
c6ca7ce |
Signed-off-by: Stanimir Varbanov <stanimir.varbanov@linaro.org>
|
|
|
c6ca7ce |
Signed-off-by: Rob Clark <robdclark@gmail.com>
|
|
|
c6ca7ce |
Reviewed-by: Stephen Boyd <sboyd@codeaurora.org>
|
|
|
c6ca7ce |
---
|
|
|
c6ca7ce |
arch/arm64/boot/dts/qcom/msm8916.dtsi | 28 ++++++++++++++++++++++++++++
|
|
|
c6ca7ce |
1 file changed, 28 insertions(+)
|
|
|
c6ca7ce |
|
|
|
c6ca7ce |
diff --git a/arch/arm64/boot/dts/qcom/msm8916.dtsi b/arch/arm64/boot/dts/qcom/msm8916.dtsi
|
|
|
c6ca7ce |
index 24c24ab..1dcd632 100644
|
|
|
c6ca7ce |
--- a/arch/arm64/boot/dts/qcom/msm8916.dtsi
|
|
|
c6ca7ce |
+++ b/arch/arm64/boot/dts/qcom/msm8916.dtsi
|
|
|
c6ca7ce |
@@ -88,6 +88,13 @@
|
|
|
c6ca7ce |
no-map;
|
|
|
c6ca7ce |
};
|
|
|
c6ca7ce |
|
|
|
c6ca7ce |
+ venus_mem: venus@89900000 {
|
|
|
c6ca7ce |
+ compatible = "shared-dma-pool";
|
|
|
c6ca7ce |
+ reg = <0x0 0x89900000 0x0 0x800000>;
|
|
|
c6ca7ce |
+ alignment = <0x1000>;
|
|
|
c6ca7ce |
+ no-map;
|
|
|
c6ca7ce |
+ };
|
|
|
c6ca7ce |
+
|
|
|
c6ca7ce |
mba_mem: mba@8ea00000 {
|
|
|
c6ca7ce |
no-map;
|
|
|
c6ca7ce |
reg = <0 0x8ea00000 0 0x100000>;
|
|
|
c6ca7ce |
@@ -1214,6 +1221,27 @@
|
|
|
c6ca7ce |
};
|
|
|
c6ca7ce |
};
|
|
|
c6ca7ce |
};
|
|
|
c6ca7ce |
+
|
|
|
c6ca7ce |
+ venus: video-codec@1d00000 {
|
|
|
c6ca7ce |
+ compatible = "qcom,msm8916-venus";
|
|
|
c6ca7ce |
+ reg = <0x01d00000 0xff000>;
|
|
|
c6ca7ce |
+ interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
|
|
|
c6ca7ce |
+ power-domains = <&gcc VENUS_GDSC>;
|
|
|
c6ca7ce |
+ clocks = <&gcc GCC_VENUS0_VCODEC0_CLK>,
|
|
|
c6ca7ce |
+ <&gcc GCC_VENUS0_AHB_CLK>,
|
|
|
c6ca7ce |
+ <&gcc GCC_VENUS0_AXI_CLK>;
|
|
|
c6ca7ce |
+ clock-names = "core", "iface", "bus";
|
|
|
c6ca7ce |
+ memory-region = <&venus_mem>;
|
|
|
c6ca7ce |
+ status = "okay";
|
|
|
c6ca7ce |
+
|
|
|
c6ca7ce |
+ video-decoder {
|
|
|
c6ca7ce |
+ compatible = "venus-decoder";
|
|
|
c6ca7ce |
+ };
|
|
|
c6ca7ce |
+
|
|
|
c6ca7ce |
+ video-encoder {
|
|
|
c6ca7ce |
+ compatible = "venus-encoder";
|
|
|
c6ca7ce |
+ };
|
|
|
c6ca7ce |
+ };
|
|
|
c6ca7ce |
};
|
|
|
c6ca7ce |
|
|
|
c6ca7ce |
smd {
|
|
|
c6ca7ce |
From patchwork Mon Jun 12 12:43:17 2017
|
|
|
c6ca7ce |
Content-Type: text/plain; charset="utf-8"
|
|
|
c6ca7ce |
MIME-Version: 1.0
|
|
|
c6ca7ce |
Content-Transfer-Encoding: 7bit
|
|
|
c6ca7ce |
Subject: [3/3] ARM64: DT: add iommu for msm8916
|
|
|
c6ca7ce |
From: Rob Clark <robdclark@gmail.com>
|
|
|
c6ca7ce |
X-Patchwork-Id: 9781061
|
|
|
c6ca7ce |
Message-Id: <20170612124317.29313-3-robdclark@gmail.com>
|
|
|
c6ca7ce |
To: linux-arm-msm@vger.kernel.org
|
|
|
c6ca7ce |
Cc: Stephen Boyd <sboyd@codeaurora.org>, Andy Gross <agross@codeaurora.org>,
|
|
|
c6ca7ce |
Stanimir Varbanov <stanimir.varbanov@linaro.org>,
|
|
|
c6ca7ce |
Rob Clark <robdclark@gmail.com>
|
|
|
c6ca7ce |
Date: Mon, 12 Jun 2017 08:43:17 -0400
|
|
|
c6ca7ce |
|
|
|
c6ca7ce |
Signed-off-by: Rob Clark <robdclark@gmail.com>
|
|
|
c6ca7ce |
Reviewed-by: Stephen Boyd <sboyd@codeaurora.org>
|
|
|
c6ca7ce |
---
|
|
|
c6ca7ce |
arch/arm64/boot/dts/qcom/msm8916.dtsi | 57 +++++++++++++++++++++++++++++++++++
|
|
|
c6ca7ce |
1 file changed, 57 insertions(+)
|
|
|
c6ca7ce |
|
|
|
c6ca7ce |
diff --git a/arch/arm64/boot/dts/qcom/msm8916.dtsi b/arch/arm64/boot/dts/qcom/msm8916.dtsi
|
|
|
c6ca7ce |
index 1dcd632..9a1d7ef 100644
|
|
|
c6ca7ce |
--- a/arch/arm64/boot/dts/qcom/msm8916.dtsi
|
|
|
c6ca7ce |
+++ b/arch/arm64/boot/dts/qcom/msm8916.dtsi
|
|
|
c6ca7ce |
@@ -716,6 +716,59 @@
|
|
|
c6ca7ce |
#thermal-sensor-cells = <1>;
|
|
|
c6ca7ce |
};
|
|
|
c6ca7ce |
|
|
|
c6ca7ce |
+ apps_iommu: iommu@1ef0000 {
|
|
|
c6ca7ce |
+ #address-cells = <1>;
|
|
|
c6ca7ce |
+ #size-cells = <1>;
|
|
|
c6ca7ce |
+ #iommu-cells = <1>;
|
|
|
c6ca7ce |
+ compatible = "qcom,msm8916-iommu", "qcom,msm-iommu-v1";
|
|
|
c6ca7ce |
+ ranges = <0 0x1e20000 0x40000>;
|
|
|
c6ca7ce |
+ reg = <0x1ef0000 0x3000>;
|
|
|
c6ca7ce |
+ clocks = <&gcc GCC_SMMU_CFG_CLK>,
|
|
|
c6ca7ce |
+ <&gcc GCC_APSS_TCU_CLK>;
|
|
|
c6ca7ce |
+ clock-names = "iface", "bus";
|
|
|
c6ca7ce |
+ qcom,iommu-secure-id = <17>;
|
|
|
c6ca7ce |
+
|
|
|
c6ca7ce |
+ // mdp_0:
|
|
|
c6ca7ce |
+ iommu-ctx@4000 {
|
|
|
c6ca7ce |
+ compatible = "qcom,msm-iommu-v1-ns";
|
|
|
c6ca7ce |
+ reg = <0x4000 0x1000>;
|
|
|
c6ca7ce |
+ interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
|
|
|
c6ca7ce |
+ };
|
|
|
c6ca7ce |
+
|
|
|
c6ca7ce |
+ // venus_ns:
|
|
|
c6ca7ce |
+ iommu-ctx@5000 {
|
|
|
c6ca7ce |
+ compatible = "qcom,msm-iommu-v1-sec";
|
|
|
c6ca7ce |
+ reg = <0x5000 0x1000>;
|
|
|
c6ca7ce |
+ interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
|
|
|
c6ca7ce |
+ };
|
|
|
c6ca7ce |
+ };
|
|
|
c6ca7ce |
+
|
|
|
c6ca7ce |
+ gpu_iommu: iommu@1f08000 {
|
|
|
c6ca7ce |
+ #address-cells = <1>;
|
|
|
c6ca7ce |
+ #size-cells = <1>;
|
|
|
c6ca7ce |
+ #iommu-cells = <1>;
|
|
|
c6ca7ce |
+ compatible = "qcom,msm8916-iommu", "qcom,msm-iommu-v1";
|
|
|
c6ca7ce |
+ ranges = <0 0x1f08000 0x10000>;
|
|
|
c6ca7ce |
+ clocks = <&gcc GCC_SMMU_CFG_CLK>,
|
|
|
c6ca7ce |
+ <&gcc GCC_GFX_TCU_CLK>;
|
|
|
c6ca7ce |
+ clock-names = "iface", "bus";
|
|
|
c6ca7ce |
+ qcom,iommu-secure-id = <18>;
|
|
|
c6ca7ce |
+
|
|
|
c6ca7ce |
+ // gfx3d_user:
|
|
|
c6ca7ce |
+ iommu-ctx@1000 {
|
|
|
c6ca7ce |
+ compatible = "qcom,msm-iommu-v1-ns";
|
|
|
c6ca7ce |
+ reg = <0x1000 0x1000>;
|
|
|
c6ca7ce |
+ interrupts = <GIC_SPI 241 IRQ_TYPE_LEVEL_HIGH>;
|
|
|
c6ca7ce |
+ };
|
|
|
c6ca7ce |
+
|
|
|
c6ca7ce |
+ // gfx3d_priv:
|
|
|
c6ca7ce |
+ iommu-ctx@2000 {
|
|
|
c6ca7ce |
+ compatible = "qcom,msm-iommu-v1-ns";
|
|
|
c6ca7ce |
+ reg = <0x2000 0x1000>;
|
|
|
c6ca7ce |
+ interrupts = <GIC_SPI 242 0>;
|
|
|
c6ca7ce |
+ };
|
|
|
c6ca7ce |
+ };
|
|
|
c6ca7ce |
+
|
|
|
c6ca7ce |
gpu@1c00000 {
|
|
|
c6ca7ce |
compatible = "qcom,adreno-306.0", "qcom,adreno";
|
|
|
c6ca7ce |
reg = <0x01c00000 0x20000>;
|
|
|
c6ca7ce |
@@ -738,6 +791,7 @@
|
|
|
c6ca7ce |
<&gcc GFX3D_CLK_SRC>;
|
|
|
c6ca7ce |
power-domains = <&gcc OXILI_GDSC>;
|
|
|
c6ca7ce |
operating-points-v2 = <&gpu_opp_table>;
|
|
|
c6ca7ce |
+ iommus = <&gpu_iommu 1>, <&gpu_iommu 2>;
|
|
|
c6ca7ce |
};
|
|
|
c6ca7ce |
|
|
|
c6ca7ce |
mdss: mdss@1a00000 {
|
|
|
c6ca7ce |
@@ -781,6 +835,8 @@
|
|
|
c6ca7ce |
"core_clk",
|
|
|
c6ca7ce |
"vsync_clk";
|
|
|
c6ca7ce |
|
|
|
c6ca7ce |
+ iommus = <&apps_iommu 4>;
|
|
|
c6ca7ce |
+
|
|
|
c6ca7ce |
ports {
|
|
|
c6ca7ce |
#address-cells = <1>;
|
|
|
c6ca7ce |
#size-cells = <0>;
|
|
|
c6ca7ce |
@@ -1231,6 +1287,7 @@
|
|
|
c6ca7ce |
<&gcc GCC_VENUS0_AHB_CLK>,
|
|
|
c6ca7ce |
<&gcc GCC_VENUS0_AXI_CLK>;
|
|
|
c6ca7ce |
clock-names = "core", "iface", "bus";
|
|
|
c6ca7ce |
+ iommus = <&apps_iommu 5>;
|
|
|
c6ca7ce |
memory-region = <&venus_mem>;
|
|
|
c6ca7ce |
status = "okay";
|
|
|
c6ca7ce |
|