From 6ba6704e2fe7401290bf0c12ac9e4459e5ded1d2 Mon Sep 17 00:00:00 2001 From: Justin M. Forbes Date: Dec 11 2012 14:38:46 +0000 Subject: Linux 3.6.10 --- diff --git a/8139cp-revert-set-ring-address-before-enabling-receiver.patch b/8139cp-revert-set-ring-address-before-enabling-receiver.patch new file mode 100644 index 0000000..07ae2c2 --- /dev/null +++ b/8139cp-revert-set-ring-address-before-enabling-receiver.patch @@ -0,0 +1,64 @@ +From b26623dab7eeb1e9f5898c7a49458789dd492f20 Mon Sep 17 00:00:00 2001 +From: Francois Romieu +Date: Wed, 21 Nov 2012 10:07:29 +0000 +Subject: 8139cp: revert "set ring address before enabling receiver" + +From: Francois Romieu + +commit b26623dab7eeb1e9f5898c7a49458789dd492f20 upstream. + +This patch reverts b01af4579ec41f48e9b9c774e70bd6474ad210db. + +The original patch was tested with emulated hardware. Real +hardware chokes. + +Fixes https://bugzilla.kernel.org/show_bug.cgi?id=47041 + +Signed-off-by: Francois Romieu +Acked-by: Jeff Garzik +Signed-off-by: David S. Miller +Signed-off-by: CAI Qian +Signed-off-by: Greg Kroah-Hartman + +--- + drivers/net/ethernet/realtek/8139cp.c | 22 +++++++++++----------- + 1 file changed, 11 insertions(+), 11 deletions(-) + +--- a/drivers/net/ethernet/realtek/8139cp.c ++++ b/drivers/net/ethernet/realtek/8139cp.c +@@ -979,17 +979,6 @@ static void cp_init_hw (struct cp_privat + cpw32_f (MAC0 + 0, le32_to_cpu (*(__le32 *) (dev->dev_addr + 0))); + cpw32_f (MAC0 + 4, le32_to_cpu (*(__le32 *) (dev->dev_addr + 4))); + +- cpw32_f(HiTxRingAddr, 0); +- cpw32_f(HiTxRingAddr + 4, 0); +- +- ring_dma = cp->ring_dma; +- cpw32_f(RxRingAddr, ring_dma & 0xffffffff); +- cpw32_f(RxRingAddr + 4, (ring_dma >> 16) >> 16); +- +- ring_dma += sizeof(struct cp_desc) * CP_RX_RING_SIZE; +- cpw32_f(TxRingAddr, ring_dma & 0xffffffff); +- cpw32_f(TxRingAddr + 4, (ring_dma >> 16) >> 16); +- + cp_start_hw(cp); + cpw8(TxThresh, 0x06); /* XXX convert magic num to a constant */ + +@@ -1003,6 +992,17 @@ static void cp_init_hw (struct cp_privat + + cpw8(Config5, cpr8(Config5) & PMEStatus); + ++ cpw32_f(HiTxRingAddr, 0); ++ cpw32_f(HiTxRingAddr + 4, 0); ++ ++ ring_dma = cp->ring_dma; ++ cpw32_f(RxRingAddr, ring_dma & 0xffffffff); ++ cpw32_f(RxRingAddr + 4, (ring_dma >> 16) >> 16); ++ ++ ring_dma += sizeof(struct cp_desc) * CP_RX_RING_SIZE; ++ cpw32_f(TxRingAddr, ring_dma & 0xffffffff); ++ cpw32_f(TxRingAddr + 4, (ring_dma >> 16) >> 16); ++ + cpw16(MultiIntr, 0); + + cpw8_f(Cfg9346, Cfg9346_Lock); diff --git a/kernel.spec b/kernel.spec index 70ac476..37761f2 100644 --- a/kernel.spec +++ b/kernel.spec @@ -54,7 +54,7 @@ Summary: The Linux kernel # For non-released -rc kernels, this will be appended after the rcX and # gitX tags, so a 3 here would become part of release "0.rcX.gitX.3" # -%global baserelease 2 +%global baserelease 1 %global fedora_build %{baserelease} # base_sublevel is the kernel version we're starting with and patching @@ -66,7 +66,7 @@ Summary: The Linux kernel %if 0%{?released_kernel} # Do we have a -stable update to apply? -%define stable_update 9 +%define stable_update 10 # Is it a -stable RC? %define stable_rc 0 # Set rpm version accordingly @@ -722,12 +722,10 @@ Patch21229: exec-use-eloop-for-max-recursion-depth.patch Patch21230: SCSI-mvsas-Fix-oops-when-ata-commond-timeout.patch #rhbz 851278 +Patch21231: 8139cp-revert-set-ring-address-before-enabling-receiver.patch Patch21232: 8139cp-set-ring-address-after-enabling-C-mode.patch Patch21233: 8139cp-re-enable-interrupts-after-tx-timeout.patch -#rhbz 855275 -Patch21235: radeon-evergreen-3.6.9-fixes.mbox - # END OF PATCH DEFINITIONS %endif @@ -1367,12 +1365,10 @@ ApplyPatch exec-use-eloop-for-max-recursion-depth.patch ApplyPatch SCSI-mvsas-Fix-oops-when-ata-commond-timeout.patch #rhbz 851278 +ApplyPatch 8139cp-revert-set-ring-address-before-enabling-receiver.patch -R ApplyPatch 8139cp-set-ring-address-after-enabling-C-mode.patch ApplyPatch 8139cp-re-enable-interrupts-after-tx-timeout.patch -#rhbz 855275 -ApplyPatch radeon-evergreen-3.6.9-fixes.mbox - # END OF PATCH APPLICATIONS %endif @@ -2073,6 +2069,9 @@ fi # and build. %changelog +* Tue Dec 11 2012 Justin M. Forbes 3.6.10-1 +- Linux 3.6.10 + * Mon Dec 03 2012 Josh Boyer - 3.6.9-2 - Backport 3 upstream fixes to resolve radeon schedule IB errors (rhbz 855275) diff --git a/radeon-evergreen-3.6.9-fixes.mbox b/radeon-evergreen-3.6.9-fixes.mbox deleted file mode 100644 index 96628fd..0000000 --- a/radeon-evergreen-3.6.9-fixes.mbox +++ /dev/null @@ -1,376 +0,0 @@ -From 8e502f50fdade16ab4540159218be5d81b678d11 Mon Sep 17 00:00:00 2001 -From: Alex Deucher -Date: Mon, 3 Dec 2012 18:12:05 -0500 -Subject: [PATCH 1/3] drm/radeon/dce4+: don't use radeon_crtc for vblank - callback - -Upstream commit 4a15903db02026728d0cf2755c6fabae16b8db6a - -This might be called before we've allocated the radeon_crtcs - -Signed-off-by: Alex Deucher ---- - drivers/gpu/drm/radeon/evergreen.c | 20 ++++++++++++++++---- - 1 file changed, 16 insertions(+), 4 deletions(-) - -diff --git a/drivers/gpu/drm/radeon/evergreen.c b/drivers/gpu/drm/radeon/evergreen.c -index e93b80a..0c79d9e 100644 ---- a/drivers/gpu/drm/radeon/evergreen.c -+++ b/drivers/gpu/drm/radeon/evergreen.c -@@ -37,6 +37,16 @@ - #define EVERGREEN_PFP_UCODE_SIZE 1120 - #define EVERGREEN_PM4_UCODE_SIZE 1376 - -+static const u32 crtc_offsets[6] = -+{ -+ EVERGREEN_CRTC0_REGISTER_OFFSET, -+ EVERGREEN_CRTC1_REGISTER_OFFSET, -+ EVERGREEN_CRTC2_REGISTER_OFFSET, -+ EVERGREEN_CRTC3_REGISTER_OFFSET, -+ EVERGREEN_CRTC4_REGISTER_OFFSET, -+ EVERGREEN_CRTC5_REGISTER_OFFSET -+}; -+ - static void evergreen_gpu_init(struct radeon_device *rdev); - void evergreen_fini(struct radeon_device *rdev); - void evergreen_pcie_gen2_enable(struct radeon_device *rdev); -@@ -109,17 +119,19 @@ void evergreen_fix_pci_max_read_req_size(struct radeon_device *rdev) - */ - void dce4_wait_for_vblank(struct radeon_device *rdev, int crtc) - { -- struct radeon_crtc *radeon_crtc = rdev->mode_info.crtcs[crtc]; - int i; - -- if (RREG32(EVERGREEN_CRTC_CONTROL + radeon_crtc->crtc_offset) & EVERGREEN_CRTC_MASTER_EN) { -+ if (crtc >= rdev->num_crtc) -+ return; -+ -+ if (RREG32(EVERGREEN_CRTC_CONTROL + crtc_offsets[crtc]) & EVERGREEN_CRTC_MASTER_EN) { - for (i = 0; i < rdev->usec_timeout; i++) { -- if (!(RREG32(EVERGREEN_CRTC_STATUS + radeon_crtc->crtc_offset) & EVERGREEN_CRTC_V_BLANK)) -+ if (!(RREG32(EVERGREEN_CRTC_STATUS + crtc_offsets[crtc]) & EVERGREEN_CRTC_V_BLANK)) - break; - udelay(1); - } - for (i = 0; i < rdev->usec_timeout; i++) { -- if (RREG32(EVERGREEN_CRTC_STATUS + radeon_crtc->crtc_offset) & EVERGREEN_CRTC_V_BLANK) -+ if (RREG32(EVERGREEN_CRTC_STATUS + crtc_offsets[crtc]) & EVERGREEN_CRTC_V_BLANK) - break; - udelay(1); - } --- -1.8.0 - - -From 027eb4090e4261a9b9f5cce47493657d12f2caf3 Mon Sep 17 00:00:00 2001 -From: Alex Deucher -Date: Mon, 3 Dec 2012 18:15:21 -0500 -Subject: [PATCH 2/3] drm/radeon: properly handle mc_stop/mc_resume on - evergreen+ (v2) - -Upstream commit 62444b7462a2b98bc78d68736c03a7c4e66ba7e2 - -- Stop the displays from accessing the FB -- Block CPU access -- Turn off MC client access - -This should fix issues some users have seen, especially -with UEFI, when changing the MC FB location that result -in hangs or display corruption. - -v2: fix crtc enabled check noticed by Luca Tettamanti - -Signed-off-by: Alex Deucher ---- - drivers/gpu/drm/radeon/evergreen.c | 169 +++++++++++++++------------------ - drivers/gpu/drm/radeon/evergreen_reg.h | 2 + - drivers/gpu/drm/radeon/evergreend.h | 7 ++ - drivers/gpu/drm/radeon/radeon_asic.h | 1 + - 4 files changed, 88 insertions(+), 91 deletions(-) - -diff --git a/drivers/gpu/drm/radeon/evergreen.c b/drivers/gpu/drm/radeon/evergreen.c -index 0c79d9e..10b34b8 100644 ---- a/drivers/gpu/drm/radeon/evergreen.c -+++ b/drivers/gpu/drm/radeon/evergreen.c -@@ -1241,116 +1241,103 @@ void evergreen_agp_enable(struct radeon_device *rdev) - - void evergreen_mc_stop(struct radeon_device *rdev, struct evergreen_mc_save *save) - { -+ u32 crtc_enabled, tmp, frame_count, blackout; -+ int i, j; -+ - save->vga_render_control = RREG32(VGA_RENDER_CONTROL); - save->vga_hdp_control = RREG32(VGA_HDP_CONTROL); - -- /* Stop all video */ -+ /* disable VGA render */ - WREG32(VGA_RENDER_CONTROL, 0); -- WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC0_REGISTER_OFFSET, 1); -- WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC1_REGISTER_OFFSET, 1); -- if (rdev->num_crtc >= 4) { -- WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC2_REGISTER_OFFSET, 1); -- WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC3_REGISTER_OFFSET, 1); -- } -- if (rdev->num_crtc >= 6) { -- WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC4_REGISTER_OFFSET, 1); -- WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC5_REGISTER_OFFSET, 1); -- } -- WREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET, 0); -- WREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET, 0); -- if (rdev->num_crtc >= 4) { -- WREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET, 0); -- WREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC3_REGISTER_OFFSET, 0); -- } -- if (rdev->num_crtc >= 6) { -- WREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC4_REGISTER_OFFSET, 0); -- WREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET, 0); -- } -- WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC0_REGISTER_OFFSET, 0); -- WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC1_REGISTER_OFFSET, 0); -- if (rdev->num_crtc >= 4) { -- WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC2_REGISTER_OFFSET, 0); -- WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC3_REGISTER_OFFSET, 0); -- } -- if (rdev->num_crtc >= 6) { -- WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC4_REGISTER_OFFSET, 0); -- WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC5_REGISTER_OFFSET, 0); -+ /* blank the display controllers */ -+ for (i = 0; i < rdev->num_crtc; i++) { -+ crtc_enabled = RREG32(EVERGREEN_CRTC_CONTROL + crtc_offsets[i]) & EVERGREEN_CRTC_MASTER_EN; -+ if (crtc_enabled) { -+ save->crtc_enabled[i] = true; -+ if (ASIC_IS_DCE6(rdev)) { -+ tmp = RREG32(EVERGREEN_CRTC_BLANK_CONTROL + crtc_offsets[i]); -+ if (!(tmp & EVERGREEN_CRTC_BLANK_DATA_EN)) { -+ radeon_wait_for_vblank(rdev, i); -+ tmp |= EVERGREEN_CRTC_BLANK_DATA_EN; -+ WREG32(EVERGREEN_CRTC_BLANK_CONTROL + crtc_offsets[i], tmp); -+ } -+ } else { -+ tmp = RREG32(EVERGREEN_CRTC_CONTROL + crtc_offsets[i]); -+ if (!(tmp & EVERGREEN_CRTC_DISP_READ_REQUEST_DISABLE)) { -+ radeon_wait_for_vblank(rdev, i); -+ tmp |= EVERGREEN_CRTC_DISP_READ_REQUEST_DISABLE; -+ WREG32(EVERGREEN_CRTC_CONTROL + crtc_offsets[i], tmp); -+ } -+ } -+ /* wait for the next frame */ -+ frame_count = radeon_get_vblank_counter(rdev, i); -+ for (j = 0; j < rdev->usec_timeout; j++) { -+ if (radeon_get_vblank_counter(rdev, i) != frame_count) -+ break; -+ udelay(1); -+ } -+ } - } - -- WREG32(D1VGA_CONTROL, 0); -- WREG32(D2VGA_CONTROL, 0); -- if (rdev->num_crtc >= 4) { -- WREG32(EVERGREEN_D3VGA_CONTROL, 0); -- WREG32(EVERGREEN_D4VGA_CONTROL, 0); -- } -- if (rdev->num_crtc >= 6) { -- WREG32(EVERGREEN_D5VGA_CONTROL, 0); -- WREG32(EVERGREEN_D6VGA_CONTROL, 0); -+ radeon_mc_wait_for_idle(rdev); -+ -+ blackout = RREG32(MC_SHARED_BLACKOUT_CNTL); -+ if ((blackout & BLACKOUT_MODE_MASK) != 1) { -+ /* Block CPU access */ -+ WREG32(BIF_FB_EN, 0); -+ /* blackout the MC */ -+ blackout &= ~BLACKOUT_MODE_MASK; -+ WREG32(MC_SHARED_BLACKOUT_CNTL, blackout | 1); - } - } - - void evergreen_mc_resume(struct radeon_device *rdev, struct evergreen_mc_save *save) - { -- WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH + EVERGREEN_CRTC0_REGISTER_OFFSET, -- upper_32_bits(rdev->mc.vram_start)); -- WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH + EVERGREEN_CRTC0_REGISTER_OFFSET, -- upper_32_bits(rdev->mc.vram_start)); -- WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS + EVERGREEN_CRTC0_REGISTER_OFFSET, -- (u32)rdev->mc.vram_start); -- WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS + EVERGREEN_CRTC0_REGISTER_OFFSET, -- (u32)rdev->mc.vram_start); -- -- WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH + EVERGREEN_CRTC1_REGISTER_OFFSET, -- upper_32_bits(rdev->mc.vram_start)); -- WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH + EVERGREEN_CRTC1_REGISTER_OFFSET, -- upper_32_bits(rdev->mc.vram_start)); -- WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS + EVERGREEN_CRTC1_REGISTER_OFFSET, -- (u32)rdev->mc.vram_start); -- WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS + EVERGREEN_CRTC1_REGISTER_OFFSET, -- (u32)rdev->mc.vram_start); -- -- if (rdev->num_crtc >= 4) { -- WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH + EVERGREEN_CRTC2_REGISTER_OFFSET, -- upper_32_bits(rdev->mc.vram_start)); -- WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH + EVERGREEN_CRTC2_REGISTER_OFFSET, -- upper_32_bits(rdev->mc.vram_start)); -- WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS + EVERGREEN_CRTC2_REGISTER_OFFSET, -- (u32)rdev->mc.vram_start); -- WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS + EVERGREEN_CRTC2_REGISTER_OFFSET, -- (u32)rdev->mc.vram_start); -- -- WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH + EVERGREEN_CRTC3_REGISTER_OFFSET, -- upper_32_bits(rdev->mc.vram_start)); -- WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH + EVERGREEN_CRTC3_REGISTER_OFFSET, -- upper_32_bits(rdev->mc.vram_start)); -- WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS + EVERGREEN_CRTC3_REGISTER_OFFSET, -- (u32)rdev->mc.vram_start); -- WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS + EVERGREEN_CRTC3_REGISTER_OFFSET, -- (u32)rdev->mc.vram_start); -- } -- if (rdev->num_crtc >= 6) { -- WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH + EVERGREEN_CRTC4_REGISTER_OFFSET, -- upper_32_bits(rdev->mc.vram_start)); -- WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH + EVERGREEN_CRTC4_REGISTER_OFFSET, -- upper_32_bits(rdev->mc.vram_start)); -- WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS + EVERGREEN_CRTC4_REGISTER_OFFSET, -- (u32)rdev->mc.vram_start); -- WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS + EVERGREEN_CRTC4_REGISTER_OFFSET, -- (u32)rdev->mc.vram_start); -+ u32 tmp, frame_count; -+ int i, j; - -- WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH + EVERGREEN_CRTC5_REGISTER_OFFSET, -+ /* update crtc base addresses */ -+ for (i = 0; i < rdev->num_crtc; i++) { -+ WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH + crtc_offsets[i], - upper_32_bits(rdev->mc.vram_start)); -- WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH + EVERGREEN_CRTC5_REGISTER_OFFSET, -+ WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH + crtc_offsets[i], - upper_32_bits(rdev->mc.vram_start)); -- WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS + EVERGREEN_CRTC5_REGISTER_OFFSET, -+ WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS + crtc_offsets[i], - (u32)rdev->mc.vram_start); -- WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS + EVERGREEN_CRTC5_REGISTER_OFFSET, -+ WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS + crtc_offsets[i], - (u32)rdev->mc.vram_start); - } -- - WREG32(EVERGREEN_VGA_MEMORY_BASE_ADDRESS_HIGH, upper_32_bits(rdev->mc.vram_start)); - WREG32(EVERGREEN_VGA_MEMORY_BASE_ADDRESS, (u32)rdev->mc.vram_start); -- /* Unlock host access */ -+ -+ /* unblackout the MC */ -+ tmp = RREG32(MC_SHARED_BLACKOUT_CNTL); -+ tmp &= ~BLACKOUT_MODE_MASK; -+ WREG32(MC_SHARED_BLACKOUT_CNTL, tmp); -+ /* allow CPU access */ -+ WREG32(BIF_FB_EN, FB_READ_EN | FB_WRITE_EN); -+ -+ for (i = 0; i < rdev->num_crtc; i++) { -+ if (save->crtc_enabled) { -+ if (ASIC_IS_DCE6(rdev)) { -+ tmp = RREG32(EVERGREEN_CRTC_BLANK_CONTROL + crtc_offsets[i]); -+ tmp |= EVERGREEN_CRTC_BLANK_DATA_EN; -+ WREG32(EVERGREEN_CRTC_BLANK_CONTROL + crtc_offsets[i], tmp); -+ } else { -+ tmp = RREG32(EVERGREEN_CRTC_CONTROL + crtc_offsets[i]); -+ tmp &= ~EVERGREEN_CRTC_DISP_READ_REQUEST_DISABLE; -+ WREG32(EVERGREEN_CRTC_CONTROL + crtc_offsets[i], tmp); -+ } -+ /* wait for the next frame */ -+ frame_count = radeon_get_vblank_counter(rdev, i); -+ for (j = 0; j < rdev->usec_timeout; j++) { -+ if (radeon_get_vblank_counter(rdev, i) != frame_count) -+ break; -+ udelay(1); -+ } -+ } -+ } -+ /* Unlock vga access */ - WREG32(VGA_HDP_CONTROL, save->vga_hdp_control); - mdelay(1); - WREG32(VGA_RENDER_CONTROL, save->vga_render_control); -diff --git a/drivers/gpu/drm/radeon/evergreen_reg.h b/drivers/gpu/drm/radeon/evergreen_reg.h -index 8beac10..034f4c2 100644 ---- a/drivers/gpu/drm/radeon/evergreen_reg.h -+++ b/drivers/gpu/drm/radeon/evergreen_reg.h -@@ -218,6 +218,8 @@ - #define EVERGREEN_CRTC_CONTROL 0x6e70 - # define EVERGREEN_CRTC_MASTER_EN (1 << 0) - # define EVERGREEN_CRTC_DISP_READ_REQUEST_DISABLE (1 << 24) -+#define EVERGREEN_CRTC_BLANK_CONTROL 0x6e74 -+# define EVERGREEN_CRTC_BLANK_DATA_EN (1 << 8) - #define EVERGREEN_CRTC_STATUS 0x6e8c - # define EVERGREEN_CRTC_V_BLANK (1 << 0) - #define EVERGREEN_CRTC_STATUS_POSITION 0x6e90 -diff --git a/drivers/gpu/drm/radeon/evergreend.h b/drivers/gpu/drm/radeon/evergreend.h -index 302af4f..2bc0f6a 100644 ---- a/drivers/gpu/drm/radeon/evergreend.h -+++ b/drivers/gpu/drm/radeon/evergreend.h -@@ -87,6 +87,10 @@ - - #define CONFIG_MEMSIZE 0x5428 - -+#define BIF_FB_EN 0x5490 -+#define FB_READ_EN (1 << 0) -+#define FB_WRITE_EN (1 << 1) -+ - #define CP_STRMOUT_CNTL 0x84FC - - #define CP_COHER_CNTL 0x85F0 -@@ -434,6 +438,9 @@ - #define NOOFCHAN_MASK 0x00003000 - #define MC_SHARED_CHREMAP 0x2008 - -+#define MC_SHARED_BLACKOUT_CNTL 0x20ac -+#define BLACKOUT_MODE_MASK 0x00000007 -+ - #define MC_ARB_RAMCFG 0x2760 - #define NOOFBANK_SHIFT 0 - #define NOOFBANK_MASK 0x00000003 -diff --git a/drivers/gpu/drm/radeon/radeon_asic.h b/drivers/gpu/drm/radeon/radeon_asic.h -index 18c38d1..132429e 100644 ---- a/drivers/gpu/drm/radeon/radeon_asic.h -+++ b/drivers/gpu/drm/radeon/radeon_asic.h -@@ -389,6 +389,7 @@ void r700_cp_fini(struct radeon_device *rdev); - struct evergreen_mc_save { - u32 vga_render_control; - u32 vga_hdp_control; -+ bool crtc_enabled[RADEON_MAX_CRTCS]; - }; - - void evergreen_pcie_gart_tlb_flush(struct radeon_device *rdev); --- -1.8.0 - - -From 5d46a79118cc6a8f5e30e39f19ad997bb2191b53 Mon Sep 17 00:00:00 2001 -From: Alex Deucher -Date: Mon, 3 Dec 2012 18:15:55 -0500 -Subject: [PATCH 3/3] drm/radeon: properly track the crtc not_enabled case - evergreen_mc_stop() - -Upstream commit 804cc4a0ad3a896ca295f771a28c6eb36ced7903 - -The save struct is not initialized previously so explicitly -mark the crtcs as not used when they are not in use. - -Signed-off-by: Alex Deucher -Cc: stable@vger.kernel.org ---- - drivers/gpu/drm/radeon/evergreen.c | 2 ++ - 1 file changed, 2 insertions(+) - -diff --git a/drivers/gpu/drm/radeon/evergreen.c b/drivers/gpu/drm/radeon/evergreen.c -index 10b34b8..5528fea 100644 ---- a/drivers/gpu/drm/radeon/evergreen.c -+++ b/drivers/gpu/drm/radeon/evergreen.c -@@ -1276,6 +1276,8 @@ void evergreen_mc_stop(struct radeon_device *rdev, struct evergreen_mc_save *sav - break; - udelay(1); - } -+ } else { -+ save->crtc_enabled[i] = false; - } - } - --- -1.8.0 - diff --git a/sources b/sources index 7369b36..eebf282 100644 --- a/sources +++ b/sources @@ -1,2 +1,2 @@ 1a1760420eac802c541a20ab51a093d1 linux-3.6.tar.xz -a7c656034599f90dcbc50895b69022aa patch-3.6.9.xz +406a52f90a2ddc78a3ecdf4fe46e7cf7 patch-3.6.10.xz