From aeb97b1a002bc08aca3b35c50f2336e3655c36ff Mon Sep 17 00:00:00 2001 From: Peter Robinson Date: Oct 22 2012 09:15:23 +0000 Subject: - Cleanup ARM patches - Add highbank sata patch - add patch to revert ARM misaligned access check to stop kernel OOPS --- diff --git a/arm-beagle-usb-init.patch b/arm-beagle-usb-init.patch deleted file mode 100644 index 3b488c8..0000000 --- a/arm-beagle-usb-init.patch +++ /dev/null @@ -1,132 +0,0 @@ -From: "Govindraj.R" - -All beagle boards rev > AX/BX have external usb hubs connected to ehci -interface, external hub/peripheral uses a nreset sequence for which -uart2_rx.gpio_147 pin in mux mode4(USB2HS_nRST) is used on all beagle -boards expect rev Ax/BX. -(Reference to all beagle boards rev schematics: -http://beagleboard.org/hardware/design) - -Initialising uart2 will lead to serial init taking over uart2_rx pin -so init uart2_rx pin mux only for Beagle AX/BX rev boards. -Dont init uart2 for all other boards allowing usb_ehci functionality. - -To initialise individual uart port by id utilise and modify the existing -available func. omap_serial_board_init. - -Cc: Tony Lindgren -Cc: Kevin Hilman -Cc: Koen Kooi -Tested-by: Peter Ujfalusi -Tested-by: Robert Nelson -Signed-off-by: Govindraj.R ---- - arch/arm/mach-omap2/board-omap3beagle.c | 6 +++- - arch/arm/mach-omap2/serial.c | 41 ++++++++++++++++------------- - arch/arm/plat-omap/include/plat/serial.h | 3 +- - 3 files changed, 30 insertions(+), 20 deletions(-) - -diff --git a/arch/arm/mach-omap2/board-omap3beagle.c b/arch/arm/mach-omap2/board-omap3beagle.c -index 7ffcd28..19d6fb5 100644 ---- a/arch/arm/mach-omap2/board-omap3beagle.c -+++ b/arch/arm/mach-omap2/board-omap3beagle.c -@@ -126,6 +126,7 @@ static void __init omap3_beagle_init_rev(void) - beagle_config.mmc1_gpio_wp = 29; - beagle_config.reset_gpio = 170; - beagle_config.usr_button_gpio = 7; -+ omap_serial_board_init(NULL, 1); - break; - case 6: - printk(KERN_INFO "OMAP3 Beagle Rev: C1/C2/C3\n"); -@@ -528,7 +529,10 @@ static void __init omap3_beagle_init(void) - platform_add_devices(omap3_beagle_devices, - ARRAY_SIZE(omap3_beagle_devices)); - omap_display_init(&beagle_dss_data); -- omap_serial_init(); -+ omap_serial_board_init(NULL, 0); -+ omap_serial_board_init(NULL, 2); -+ omap_serial_board_init(NULL, 3); -+ - omap_sdrc_init(mt46h32m32lf6_sdrc_params, - mt46h32m32lf6_sdrc_params); - -diff --git a/arch/arm/mach-omap2/serial.c b/arch/arm/mach-omap2/serial.c -index f590afc..e7c0462 100644 ---- a/arch/arm/mach-omap2/serial.c -+++ b/arch/arm/mach-omap2/serial.c -@@ -393,30 +393,32 @@ void __init omap_serial_init_port(struct omap_board_data *bdata, - /** - * omap_serial_board_init() - initialize all supported serial ports - * @info: platform specific data pointer -+ * @port_id: uart port number to be initialised - * -- * Initializes all available UARTs as serial ports. Platforms -+ * Initializes individual UARTs as serial ports. Platforms - * can call this function when they want to have default behaviour -- * for serial ports (e.g initialize them all as serial ports). -+ * for serial ports (e.g initialize individual serial ports based on port id). - */ --void __init omap_serial_board_init(struct omap_uart_port_info *info) -+void __init omap_serial_board_init(struct omap_uart_port_info *info, u8 port_id) - { - struct omap_uart_state *uart; - struct omap_board_data bdata; - -- list_for_each_entry(uart, &uart_list, node) { -- bdata.id = uart->num; -- bdata.flags = 0; -- bdata.pads = NULL; -- bdata.pads_cnt = 0; -- -- if (cpu_is_omap44xx() || cpu_is_omap34xx()) -- omap_serial_fill_default_pads(&bdata); -- -- if (!info) -- omap_serial_init_port(&bdata, NULL); -- else -- omap_serial_init_port(&bdata, &info[uart->num]); -- } -+ list_for_each_entry(uart, &uart_list, node) -+ if (uart->num == port_id) { -+ bdata.id = uart->num; -+ bdata.flags = 0; -+ bdata.pads = NULL; -+ bdata.pads_cnt = 0; -+ -+ if (!cpu_is_omap24xx()) -+ omap_serial_fill_default_pads(&bdata); -+ -+ if (!info) -+ omap_serial_init_port(&bdata, NULL); -+ else -+ omap_serial_init_port(&bdata, info); -+ } - } - - /** -@@ -428,5 +430,8 @@ void __init omap_serial_board_init(struct omap_uart_port_info *info) - */ - void __init omap_serial_init(void) - { -- omap_serial_board_init(NULL); -+ struct omap_uart_state *uart; -+ -+ list_for_each_entry(uart, &uart_list, node) -+ omap_serial_board_init(NULL, uart->num); - } -diff --git a/arch/arm/plat-omap/include/plat/serial.h b/arch/arm/plat-omap/include/plat/serial.h -index 198d1e6..043b251 100644 ---- a/arch/arm/plat-omap/include/plat/serial.h -+++ b/arch/arm/plat-omap/include/plat/serial.h -@@ -111,7 +111,8 @@ struct omap_uart_port_info; - struct omap_uart_port_info; - - extern void omap_serial_init(void); --extern void omap_serial_board_init(struct omap_uart_port_info *platform_data); -+extern void omap_serial_board_init(struct omap_uart_port_info *platform_data, -+ u8 port_id); - extern void omap_serial_init_port(struct omap_board_data *bdata, - struct omap_uart_port_info *platform_data); - #endif --- -1.7.5.4 diff --git a/arm-highbank-sata-fix.patch b/arm-highbank-sata-fix.patch new file mode 100644 index 0000000..fda7b21 --- /dev/null +++ b/arm-highbank-sata-fix.patch @@ -0,0 +1,599 @@ +From: Mark Langsdorf +Date: Thu, 6 Sep 2012 21:03:30 +0000 (-0500) +Subject: ata: add platform driver for Calxeda AHCI controller +X-Git-Tag: next-20121002~68^2~5 +X-Git-Url: http://git.kernel.org/?p=linux%2Fkernel%2Fgit%2Fnext%2Flinux-next.git;a=commitdiff_plain;h=8996b89d6bc98ae2f6d6e6e624a42a3f89d06949;hp=100f586bd0959fe0e52b8a0b8cb49a3df1c6b044 + +ata: add platform driver for Calxeda AHCI controller + +Calxeda highbank SATA phy has intermittent problems bringing up a link +with Gen3 drives. Retrying the phy hard reset can work-around this issue, +but each reset also disables spread spectrum support. The reset function +also needs to reprogram the phy to enable spread spectrum support. + +Create a new driver based on ahci_platform to support the Calxeda Highbank +SATA controller. + +Signed-off-by: Mark Langsdorf +Signed-off-by: Rob Herring +Signed-off-by: Jeff Garzik +--- + +diff --git a/Documentation/devicetree/bindings/arm/calxeda/combophy.txt b/Documentation/devicetree/bindings/arm/calxeda/combophy.txt +new file mode 100644 +index 0000000..6622bdb +--- /dev/null ++++ b/Documentation/devicetree/bindings/arm/calxeda/combophy.txt +@@ -0,0 +1,17 @@ ++Calxeda Highbank Combination Phys for SATA ++ ++Properties: ++- compatible : Should be "calxeda,hb-combophy" ++- #phy-cells: Should be 1. ++- reg : Address and size for Combination Phy registers. ++- phydev: device ID for programming the combophy. ++ ++Example: ++ ++ combophy5: combo-phy@fff5d000 { ++ compatible = "calxeda,hb-combophy"; ++ #phy-cells = <1>; ++ reg = <0xfff5d000 0x1000>; ++ phydev = <31>; ++ }; ++ +diff --git a/Documentation/devicetree/bindings/ata/ahci-platform.txt b/Documentation/devicetree/bindings/ata/ahci-platform.txt +index 8bb8a76..147c1f6 100644 +--- a/Documentation/devicetree/bindings/ata/ahci-platform.txt ++++ b/Documentation/devicetree/bindings/ata/ahci-platform.txt +@@ -8,9 +8,17 @@ Required properties: + - interrupts : + - reg : + ++Optional properties: ++- calxeda,port-phys: phandle-combophy and lane assignment, which maps each ++ SATA port to a combophy and a lane within that ++ combophy ++ + Example: + sata@ffe08000 { + compatible = "calxeda,hb-ahci"; + reg = <0xffe08000 0x1000>; + interrupts = <115>; ++ calxeda,port-phys = <&combophy5 0 &combophy0 0 &combophy0 1 ++ &combophy0 2 &combophy0 3>; ++ + }; +diff --git a/arch/arm/boot/dts/highbank.dts b/arch/arm/boot/dts/highbank.dts +index 9fecf1a..5204cf7 100644 +--- a/arch/arm/boot/dts/highbank.dts ++++ b/arch/arm/boot/dts/highbank.dts +@@ -121,6 +121,9 @@ + compatible = "calxeda,hb-ahci"; + reg = <0xffe08000 0x10000>; + interrupts = <0 83 4>; ++ calxeda,port-phys = <&combophy5 0 &combophy0 0 ++ &combophy0 1 &combophy0 2 ++ &combophy0 3>; + }; + + sdhci@ffe0e000 { +@@ -306,5 +309,19 @@ + reg = <0xfff51000 0x1000>; + interrupts = <0 80 4 0 81 4 0 82 4>; + }; ++ ++ combophy0: combo-phy@fff58000 { ++ compatible = "calxeda,hb-combophy"; ++ #phy-cells = <1>; ++ reg = <0xfff58000 0x1000>; ++ phydev = <5>; ++ }; ++ ++ combophy5: combo-phy@fff5d000 { ++ compatible = "calxeda,hb-combophy"; ++ #phy-cells = <1>; ++ reg = <0xfff5d000 0x1000>; ++ phydev = <31>; ++ }; + }; + }; +diff --git a/drivers/ata/Kconfig b/drivers/ata/Kconfig +index 27cecd3..e08d322 100644 +--- a/drivers/ata/Kconfig ++++ b/drivers/ata/Kconfig +@@ -214,6 +214,14 @@ config SATA_DWC_VDEBUG + help + This option enables the taskfile dumping and NCQ debugging. + ++config SATA_HIGHBANK ++ tristate "Calxeda Highbank SATA support" ++ help ++ This option enables support for the Calxeda Highbank SoC's ++ onboard SATA. ++ ++ If unsure, say N. ++ + config SATA_MV + tristate "Marvell SATA support" + help +diff --git a/drivers/ata/Makefile b/drivers/ata/Makefile +index a454a13..8b384f1 100644 +--- a/drivers/ata/Makefile ++++ b/drivers/ata/Makefile +@@ -9,6 +9,7 @@ obj-$(CONFIG_SATA_FSL) += sata_fsl.o + obj-$(CONFIG_SATA_INIC162X) += sata_inic162x.o + obj-$(CONFIG_SATA_SIL24) += sata_sil24.o + obj-$(CONFIG_SATA_DWC) += sata_dwc_460ex.o ++obj-$(CONFIG_SATA_HIGHBANK) += sata_highbank.o + + # SFF w/ custom DMA + obj-$(CONFIG_PDC_ADMA) += pdc_adma.o +diff --git a/drivers/ata/ahci_platform.c b/drivers/ata/ahci_platform.c +index 09728e0..dc187c7 100644 +--- a/drivers/ata/ahci_platform.c ++++ b/drivers/ata/ahci_platform.c +@@ -277,7 +277,6 @@ static int ahci_resume(struct device *dev) + SIMPLE_DEV_PM_OPS(ahci_pm_ops, ahci_suspend, ahci_resume); + + static const struct of_device_id ahci_of_match[] = { +- { .compatible = "calxeda,hb-ahci", }, + { .compatible = "snps,spear-ahci", }, + {}, + }; +diff --git a/drivers/ata/sata_highbank.c b/drivers/ata/sata_highbank.c +new file mode 100644 +index 0000000..0d7c4c2 +--- /dev/null ++++ b/drivers/ata/sata_highbank.c +@@ -0,0 +1,450 @@ ++/* ++ * Calxeda Highbank AHCI SATA platform driver ++ * Copyright 2012 Calxeda, Inc. ++ * ++ * based on the AHCI SATA platform driver by Jeff Garzik and Anton Vorontsov ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms and conditions of the GNU General Public License, ++ * version 2, as published by the Free Software Foundation. ++ * ++ * This program is distributed in the hope it will be useful, but WITHOUT ++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or ++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for ++ * more details. ++ * ++ * You should have received a copy of the GNU General Public License along with ++ * this program. If not, see . ++ */ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include "ahci.h" ++ ++#define CPHY_MAP(dev, addr) ((((dev) & 0x1f) << 7) | (((addr) >> 9) & 0x7f)) ++#define CPHY_ADDR(addr) (((addr) & 0x1ff) << 2) ++#define SERDES_CR_CTL 0x80a0 ++#define SERDES_CR_ADDR 0x80a1 ++#define SERDES_CR_DATA 0x80a2 ++#define CR_BUSY 0x0001 ++#define CR_START 0x0001 ++#define CR_WR_RDN 0x0002 ++#define CPHY_RX_INPUT_STS 0x2002 ++#define CPHY_SATA_OVERRIDE 0x4000 ++#define CPHY_OVERRIDE 0x2005 ++#define SPHY_LANE 0x100 ++#define SPHY_HALF_RATE 0x0001 ++#define CPHY_SATA_DPLL_MODE 0x0700 ++#define CPHY_SATA_DPLL_SHIFT 8 ++#define CPHY_SATA_DPLL_RESET (1 << 11) ++#define CPHY_PHY_COUNT 6 ++#define CPHY_LANE_COUNT 4 ++#define CPHY_PORT_COUNT (CPHY_PHY_COUNT * CPHY_LANE_COUNT) ++ ++static DEFINE_SPINLOCK(cphy_lock); ++/* Each of the 6 phys can have up to 4 sata ports attached to i. Map 0-based ++ * sata ports to their phys and then to their lanes within the phys ++ */ ++struct phy_lane_info { ++ void __iomem *phy_base; ++ u8 lane_mapping; ++ u8 phy_devs; ++}; ++static struct phy_lane_info port_data[CPHY_PORT_COUNT]; ++ ++static u32 __combo_phy_reg_read(u8 sata_port, u32 addr) ++{ ++ u32 data; ++ u8 dev = port_data[sata_port].phy_devs; ++ spin_lock(&cphy_lock); ++ writel(CPHY_MAP(dev, addr), port_data[sata_port].phy_base + 0x800); ++ data = readl(port_data[sata_port].phy_base + CPHY_ADDR(addr)); ++ spin_unlock(&cphy_lock); ++ return data; ++} ++ ++static void __combo_phy_reg_write(u8 sata_port, u32 addr, u32 data) ++{ ++ u8 dev = port_data[sata_port].phy_devs; ++ spin_lock(&cphy_lock); ++ writel(CPHY_MAP(dev, addr), port_data[sata_port].phy_base + 0x800); ++ writel(data, port_data[sata_port].phy_base + CPHY_ADDR(addr)); ++ spin_unlock(&cphy_lock); ++} ++ ++static void combo_phy_wait_for_ready(u8 sata_port) ++{ ++ while (__combo_phy_reg_read(sata_port, SERDES_CR_CTL) & CR_BUSY) ++ udelay(5); ++} ++ ++static u32 combo_phy_read(u8 sata_port, u32 addr) ++{ ++ combo_phy_wait_for_ready(sata_port); ++ __combo_phy_reg_write(sata_port, SERDES_CR_ADDR, addr); ++ __combo_phy_reg_write(sata_port, SERDES_CR_CTL, CR_START); ++ combo_phy_wait_for_ready(sata_port); ++ return __combo_phy_reg_read(sata_port, SERDES_CR_DATA); ++} ++ ++static void combo_phy_write(u8 sata_port, u32 addr, u32 data) ++{ ++ combo_phy_wait_for_ready(sata_port); ++ __combo_phy_reg_write(sata_port, SERDES_CR_ADDR, addr); ++ __combo_phy_reg_write(sata_port, SERDES_CR_DATA, data); ++ __combo_phy_reg_write(sata_port, SERDES_CR_CTL, CR_WR_RDN | CR_START); ++} ++ ++static void highbank_cphy_disable_overrides(u8 sata_port) ++{ ++ u8 lane = port_data[sata_port].lane_mapping; ++ u32 tmp; ++ if (unlikely(port_data[sata_port].phy_base == NULL)) ++ return; ++ tmp = combo_phy_read(sata_port, CPHY_RX_INPUT_STS + lane * SPHY_LANE); ++ tmp &= ~CPHY_SATA_OVERRIDE; ++ combo_phy_write(sata_port, CPHY_OVERRIDE + lane * SPHY_LANE, tmp); ++} ++ ++static void cphy_override_rx_mode(u8 sata_port, u32 val) ++{ ++ u8 lane = port_data[sata_port].lane_mapping; ++ u32 tmp; ++ tmp = combo_phy_read(sata_port, CPHY_RX_INPUT_STS + lane * SPHY_LANE); ++ tmp &= ~CPHY_SATA_OVERRIDE; ++ combo_phy_write(sata_port, CPHY_OVERRIDE + lane * SPHY_LANE, tmp); ++ ++ tmp |= CPHY_SATA_OVERRIDE; ++ combo_phy_write(sata_port, CPHY_OVERRIDE + lane * SPHY_LANE, tmp); ++ ++ tmp &= ~CPHY_SATA_DPLL_MODE; ++ tmp |= val << CPHY_SATA_DPLL_SHIFT; ++ combo_phy_write(sata_port, CPHY_OVERRIDE + lane * SPHY_LANE, tmp); ++ ++ tmp |= CPHY_SATA_DPLL_RESET; ++ combo_phy_write(sata_port, CPHY_OVERRIDE + lane * SPHY_LANE, tmp); ++ ++ tmp &= ~CPHY_SATA_DPLL_RESET; ++ combo_phy_write(sata_port, CPHY_OVERRIDE + lane * SPHY_LANE, tmp); ++ ++ msleep(15); ++} ++ ++static void highbank_cphy_override_lane(u8 sata_port) ++{ ++ u8 lane = port_data[sata_port].lane_mapping; ++ u32 tmp, k = 0; ++ ++ if (unlikely(port_data[sata_port].phy_base == NULL)) ++ return; ++ do { ++ tmp = combo_phy_read(sata_port, CPHY_RX_INPUT_STS + ++ lane * SPHY_LANE); ++ } while ((tmp & SPHY_HALF_RATE) && (k++ < 1000)); ++ cphy_override_rx_mode(sata_port, 3); ++} ++ ++static int highbank_initialize_phys(struct device *dev, void __iomem *addr) ++{ ++ struct device_node *sata_node = dev->of_node; ++ int phy_count = 0, phy, port = 0; ++ void __iomem *cphy_base[CPHY_PHY_COUNT]; ++ struct device_node *phy_nodes[CPHY_PHY_COUNT]; ++ memset(port_data, 0, sizeof(struct phy_lane_info) * CPHY_PORT_COUNT); ++ memset(phy_nodes, 0, sizeof(struct device_node*) * CPHY_PHY_COUNT); ++ ++ do { ++ u32 tmp; ++ struct of_phandle_args phy_data; ++ if (of_parse_phandle_with_args(sata_node, ++ "calxeda,port-phys", "#phy-cells", ++ port, &phy_data)) ++ break; ++ for (phy = 0; phy < phy_count; phy++) { ++ if (phy_nodes[phy] == phy_data.np) ++ break; ++ } ++ if (phy_nodes[phy] == NULL) { ++ phy_nodes[phy] = phy_data.np; ++ cphy_base[phy] = of_iomap(phy_nodes[phy], 0); ++ if (cphy_base[phy] == NULL) { ++ return 0; ++ } ++ phy_count += 1; ++ } ++ port_data[port].lane_mapping = phy_data.args[0]; ++ of_property_read_u32(phy_nodes[phy], "phydev", &tmp); ++ port_data[port].phy_devs = tmp; ++ port_data[port].phy_base = cphy_base[phy]; ++ of_node_put(phy_data.np); ++ port += 1; ++ } while (port < CPHY_PORT_COUNT); ++ return 0; ++} ++ ++static int ahci_highbank_hardreset(struct ata_link *link, unsigned int *class, ++ unsigned long deadline) ++{ ++ const unsigned long *timing = sata_ehc_deb_timing(&link->eh_context); ++ struct ata_port *ap = link->ap; ++ struct ahci_port_priv *pp = ap->private_data; ++ u8 *d2h_fis = pp->rx_fis + RX_FIS_D2H_REG; ++ struct ata_taskfile tf; ++ bool online; ++ u32 sstatus; ++ int rc; ++ int retry = 10; ++ ++ ahci_stop_engine(ap); ++ ++ /* clear D2H reception area to properly wait for D2H FIS */ ++ ata_tf_init(link->device, &tf); ++ tf.command = 0x80; ++ ata_tf_to_fis(&tf, 0, 0, d2h_fis); ++ ++ do { ++ highbank_cphy_disable_overrides(link->ap->port_no); ++ rc = sata_link_hardreset(link, timing, deadline, &online, NULL); ++ highbank_cphy_override_lane(link->ap->port_no); ++ ++ /* If the status is 1, we are connected, but the link did not ++ * come up. So retry resetting the link again. ++ */ ++ if (sata_scr_read(link, SCR_STATUS, &sstatus)) ++ break; ++ if (!(sstatus & 0x3)) ++ break; ++ } while (!online && retry--); ++ ++ ahci_start_engine(ap); ++ ++ if (online) ++ *class = ahci_dev_classify(ap); ++ ++ return rc; ++} ++ ++static struct ata_port_operations ahci_highbank_ops = { ++ .inherits = &ahci_ops, ++ .hardreset = ahci_highbank_hardreset, ++}; ++ ++static const struct ata_port_info ahci_highbank_port_info = { ++ .flags = AHCI_FLAG_COMMON, ++ .pio_mask = ATA_PIO4, ++ .udma_mask = ATA_UDMA6, ++ .port_ops = &ahci_highbank_ops, ++}; ++ ++static struct scsi_host_template ahci_highbank_platform_sht = { ++ AHCI_SHT("highbank-ahci"), ++}; ++ ++static const struct of_device_id ahci_of_match[] = { ++ { .compatible = "calxeda,hb-ahci" }, ++ {}, ++}; ++MODULE_DEVICE_TABLE(of, ahci_of_match); ++ ++static int __init ahci_highbank_probe(struct platform_device *pdev) ++{ ++ struct device *dev = &pdev->dev; ++ struct ahci_host_priv *hpriv; ++ struct ata_host *host; ++ struct resource *mem; ++ int irq; ++ int n_ports; ++ int i; ++ int rc; ++ struct ata_port_info pi = ahci_highbank_port_info; ++ const struct ata_port_info *ppi[] = { &pi, NULL }; ++ ++ mem = platform_get_resource(pdev, IORESOURCE_MEM, 0); ++ if (!mem) { ++ dev_err(dev, "no mmio space\n"); ++ return -EINVAL; ++ } ++ ++ irq = platform_get_irq(pdev, 0); ++ if (irq <= 0) { ++ dev_err(dev, "no irq\n"); ++ return -EINVAL; ++ } ++ ++ hpriv = devm_kzalloc(dev, sizeof(*hpriv), GFP_KERNEL); ++ if (!hpriv) { ++ dev_err(dev, "can't alloc ahci_host_priv\n"); ++ return -ENOMEM; ++ } ++ ++ hpriv->flags |= (unsigned long)pi.private_data; ++ ++ hpriv->mmio = devm_ioremap(dev, mem->start, resource_size(mem)); ++ if (!hpriv->mmio) { ++ dev_err(dev, "can't map %pR\n", mem); ++ return -ENOMEM; ++ } ++ ++ rc = highbank_initialize_phys(dev, hpriv->mmio); ++ if (rc) ++ return rc; ++ ++ ++ ahci_save_initial_config(dev, hpriv, 0, 0); ++ ++ /* prepare host */ ++ if (hpriv->cap & HOST_CAP_NCQ) ++ pi.flags |= ATA_FLAG_NCQ; ++ ++ if (hpriv->cap & HOST_CAP_PMP) ++ pi.flags |= ATA_FLAG_PMP; ++ ++ ahci_set_em_messages(hpriv, &pi); ++ ++ /* CAP.NP sometimes indicate the index of the last enabled ++ * port, at other times, that of the last possible port, so ++ * determining the maximum port number requires looking at ++ * both CAP.NP and port_map. ++ */ ++ n_ports = max(ahci_nr_ports(hpriv->cap), fls(hpriv->port_map)); ++ ++ host = ata_host_alloc_pinfo(dev, ppi, n_ports); ++ if (!host) { ++ rc = -ENOMEM; ++ goto err0; ++ } ++ ++ host->private_data = hpriv; ++ ++ if (!(hpriv->cap & HOST_CAP_SSS) || ahci_ignore_sss) ++ host->flags |= ATA_HOST_PARALLEL_SCAN; ++ ++ if (pi.flags & ATA_FLAG_EM) ++ ahci_reset_em(host); ++ ++ for (i = 0; i < host->n_ports; i++) { ++ struct ata_port *ap = host->ports[i]; ++ ++ ata_port_desc(ap, "mmio %pR", mem); ++ ata_port_desc(ap, "port 0x%x", 0x100 + ap->port_no * 0x80); ++ ++ /* set enclosure management message type */ ++ if (ap->flags & ATA_FLAG_EM) ++ ap->em_message_type = hpriv->em_msg_type; ++ ++ /* disabled/not-implemented port */ ++ if (!(hpriv->port_map & (1 << i))) ++ ap->ops = &ata_dummy_port_ops; ++ } ++ ++ rc = ahci_reset_controller(host); ++ if (rc) ++ goto err0; ++ ++ ahci_init_controller(host); ++ ahci_print_info(host, "platform"); ++ ++ rc = ata_host_activate(host, irq, ahci_interrupt, 0, ++ &ahci_highbank_platform_sht); ++ if (rc) ++ goto err0; ++ ++ return 0; ++err0: ++ return rc; ++} ++ ++static int __devexit ahci_highbank_remove(struct platform_device *pdev) ++{ ++ struct device *dev = &pdev->dev; ++ struct ata_host *host = dev_get_drvdata(dev); ++ ++ ata_host_detach(host); ++ ++ return 0; ++} ++ ++#ifdef CONFIG_PM ++static int ahci_highbank_suspend(struct device *dev) ++{ ++ struct ata_host *host = dev_get_drvdata(dev); ++ struct ahci_host_priv *hpriv = host->private_data; ++ void __iomem *mmio = hpriv->mmio; ++ u32 ctl; ++ int rc; ++ ++ if (hpriv->flags & AHCI_HFLAG_NO_SUSPEND) { ++ dev_err(dev, "firmware update required for suspend/resume\n"); ++ return -EIO; ++ } ++ ++ /* ++ * AHCI spec rev1.1 section 8.3.3: ++ * Software must disable interrupts prior to requesting a ++ * transition of the HBA to D3 state. ++ */ ++ ctl = readl(mmio + HOST_CTL); ++ ctl &= ~HOST_IRQ_EN; ++ writel(ctl, mmio + HOST_CTL); ++ readl(mmio + HOST_CTL); /* flush */ ++ ++ rc = ata_host_suspend(host, PMSG_SUSPEND); ++ if (rc) ++ return rc; ++ ++ return 0; ++} ++ ++static int ahci_highbank_resume(struct device *dev) ++{ ++ struct ata_host *host = dev_get_drvdata(dev); ++ int rc; ++ ++ if (dev->power.power_state.event == PM_EVENT_SUSPEND) { ++ rc = ahci_reset_controller(host); ++ if (rc) ++ return rc; ++ ++ ahci_init_controller(host); ++ } ++ ++ ata_host_resume(host); ++ ++ return 0; ++} ++#endif ++ ++SIMPLE_DEV_PM_OPS(ahci_highbank_pm_ops, ++ ahci_highbank_suspend, ahci_highbank_resume); ++ ++static struct platform_driver ahci_highbank_driver = { ++ .remove = __devexit_p(ahci_highbank_remove), ++ .driver = { ++ .name = "highbank-ahci", ++ .owner = THIS_MODULE, ++ .of_match_table = ahci_of_match, ++ .pm = &ahci_highbank_pm_ops, ++ }, ++ .probe = ahci_highbank_probe, ++}; ++ ++module_platform_driver(ahci_highbank_driver); ++ ++MODULE_DESCRIPTION("Calxeda Highbank AHCI SATA platform driver"); ++MODULE_AUTHOR("Mark Langsdorf "); ++MODULE_LICENSE("GPL"); ++MODULE_ALIAS("sata:highbank"); diff --git a/arm-linux-3.6-revert-missaligned-access-check-on-put_user.patch b/arm-linux-3.6-revert-missaligned-access-check-on-put_user.patch new file mode 100644 index 0000000..1558066 --- /dev/null +++ b/arm-linux-3.6-revert-missaligned-access-check-on-put_user.patch @@ -0,0 +1,83 @@ +commit dd945918f747f61eff384f5cb8889e524f60615a +Author: Jon Masters +Date: Fri Oct 5 22:32:29 2012 -0400 + + Revert "ARM: 7528/1: uaccess: annotate [__]{get,put}_user functions with might_fault()" + + This reverts commit ad72907acd2943304c292ae36960bb66e6dc23c9. + + Technically, the original commit is totally correct, however it exposes + a deep-rooted problem with missaligned accesses in e.g. the networking + stack and we need to revert this (sweep under rug) until we can get + a good solution in place upstream. The problem is that the compiler + believes the structs concerned are aligned (they are in the code), + however at runtime the IP structs are actually not aligned within + received network packets, and the fault handler is not guaranteed + to be entirely atomic and free of calls to the scheduler. + + Signed-off-by: Jon Masters + +diff --git a/arch/arm/include/asm/uaccess.h b/arch/arm/include/asm/uaccess.h +index 77bd79f..6f83ad6 100644 +--- a/arch/arm/include/asm/uaccess.h ++++ b/arch/arm/include/asm/uaccess.h +@@ -118,7 +118,7 @@ extern int __get_user_4(void *); + : "0" (__p), "r" (__l) \ + : __GUP_CLOBBER_##__s) + +-#define __get_user_check(x,p) \ ++#define get_user(x,p) \ + ({ \ + unsigned long __limit = current_thread_info()->addr_limit - 1; \ + register const typeof(*(p)) __user *__p asm("r0") = (p);\ +@@ -141,12 +141,6 @@ extern int __get_user_4(void *); + __e; \ + }) + +-#define get_user(x,p) \ +- ({ \ +- might_fault(); \ +- __get_user_check(x,p); \ +- }) +- + extern int __put_user_1(void *, unsigned int); + extern int __put_user_2(void *, unsigned int); + extern int __put_user_4(void *, unsigned int); +@@ -161,7 +155,7 @@ extern int __put_user_8(void *, unsigned long long); + : "0" (__p), "r" (__r2), "r" (__l) \ + : "ip", "lr", "cc") + +-#define __put_user_check(x,p) \ ++#define put_user(x,p) \ + ({ \ + unsigned long __limit = current_thread_info()->addr_limit - 1; \ + register const typeof(*(p)) __r2 asm("r2") = (x); \ +@@ -186,12 +180,6 @@ extern int __put_user_8(void *, unsigned long long); + __e; \ + }) + +-#define put_user(x,p) \ +- ({ \ +- might_fault(); \ +- __put_user_check(x,p); \ +- }) +- + #else /* CONFIG_MMU */ + + /* +@@ -245,7 +233,6 @@ do { \ + unsigned long __gu_addr = (unsigned long)(ptr); \ + unsigned long __gu_val; \ + __chk_user_ptr(ptr); \ +- might_fault(); \ + switch (sizeof(*(ptr))) { \ + case 1: __get_user_asm_byte(__gu_val,__gu_addr,err); break; \ + case 2: __get_user_asm_half(__gu_val,__gu_addr,err); break; \ +@@ -327,7 +314,6 @@ do { \ + unsigned long __pu_addr = (unsigned long)(ptr); \ + __typeof__(*(ptr)) __pu_val = (x); \ + __chk_user_ptr(ptr); \ +- might_fault(); \ + switch (sizeof(*(ptr))) { \ + case 1: __put_user_asm_byte(__pu_val,__pu_addr,err); break; \ + case 2: __put_user_asm_half(__pu_val,__pu_addr,err); break; \ diff --git a/arm-omap-drm-register.patch b/arm-omap-drm-register.patch deleted file mode 100644 index 9def1aa..0000000 --- a/arm-omap-drm-register.patch +++ /dev/null @@ -1,173 +0,0 @@ -Register OMAP DRM/KMS platform device. DMM is split into a -separate device using hwmod. - -Signed-off-by: Andy Gross ---- - arch/arm/mach-omap2/Makefile | 4 ++ - arch/arm/mach-omap2/drm.c | 61 ++++++++++++++++++++++++++++++++ - drivers/staging/omapdrm/omap_drv.h | 2 +- - drivers/staging/omapdrm/omap_priv.h | 55 ---------------------------- - include/linux/platform_data/omap_drm.h | 52 +++++++++++++++++++++++++++ - 5 files changed, 118 insertions(+), 56 deletions(-) - create mode 100644 arch/arm/mach-omap2/drm.c - delete mode 100644 drivers/staging/omapdrm/omap_priv.h - create mode 100644 include/linux/platform_data/omap_drm.h - -diff --git a/arch/arm/mach-omap2/Makefile b/arch/arm/mach-omap2/Makefile -index 49f92bc..c301ab7 100644 ---- a/arch/arm/mach-omap2/Makefile -+++ b/arch/arm/mach-omap2/Makefile -@@ -187,6 +187,10 @@ - obj-y += dsp.o - endif - -+ifneq ($(CONFIG_DRM_OMAP),) -+obj-y += drm.o -+endif -+ - # Specific board support - obj-$(CONFIG_MACH_OMAP_GENERIC) += board-generic.o - obj-$(CONFIG_MACH_OMAP_H4) += board-h4.o -diff --git a/arch/arm/mach-omap2/drm.c b/arch/arm/mach-omap2/drm.c -new file mode 100644 -index 0000000..72e0f01b ---- /dev/null -+++ b/arch/arm/mach-omap2/drm.c -@@ -0,0 +1,61 @@ -+/* -+ * DRM/KMS device registration for TI OMAP platforms -+ * -+ * Copyright (C) 2012 Texas Instruments -+ * Author: Rob Clark -+ * -+ * This program is free software; you can redistribute it and/or modify it -+ * under the terms of the GNU General Public License version 2 as published by -+ * the Free Software Foundation. -+ * -+ * This program is distributed in the hope that it will be useful, but WITHOUT -+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or -+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for -+ * more details. -+ * -+ * You should have received a copy of the GNU General Public License along with -+ * this program. If not, see . -+ */ -+ -+#include -+#include -+#include -+#include -+#include -+#include -+ -+#include -+#include -+ -+#if defined(CONFIG_DRM_OMAP) || (CONFIG_DRM_OMAP_MODULE) -+ -+static struct platform_device omap_drm_device = { -+ .dev = { -+ .coherent_dma_mask = DMA_BIT_MASK(32), -+ }, -+ .name = "omapdrm", -+ .id = 0, -+}; -+ -+static int __init omap_init_drm(void) -+{ -+ struct omap_hwmod *oh = NULL; -+ struct platform_device *pdev; -+ -+ /* lookup and populate the DMM information, if present - OMAP4+ */ -+ oh = omap_hwmod_lookup("dmm"); -+ -+ if (oh) { -+ pdev = omap_device_build(oh->name, -1, oh, NULL, 0, NULL, 0, -+ false); -+ WARN(IS_ERR(pdev), "Could not build omap_device for %s\n", -+ oh->name); -+ } -+ -+ return platform_device_register(&omap_drm_device); -+ -+} -+ -+arch_initcall(omap_init_drm); -+ -+#endif -diff --git a/drivers/staging/omapdrm/omap_drv.h -b/drivers/staging/omapdrm/omap_drv.h -index b7e0f07..96296e0 100644 ---- a/drivers/staging/omapdrm/omap_drv.h -+++ b/drivers/staging/omapdrm/omap_drv.h -@@ -25,8 +25,8 @@ - #include - #include - #include -+#include - #include "omap_drm.h" --#include "omap_priv.h" - - #define DBG(fmt, ...) DRM_DEBUG(fmt"\n", ##__VA_ARGS__) - #define VERB(fmt, ...) if (0) DRM_DEBUG(fmt, ##__VA_ARGS__) /* verbose debug */ -diff --git a/include/linux/platform_data/omap_drm.h -b/include/linux/platform_data/omap_drm.h -new file mode 100644 -index 0000000..3da73bd ---- /dev/null -+++ b/include/linux/platform_data/omap_drm.h -@@ -0,0 +1,52 @@ -+/* -+ * DRM/KMS platform data for TI OMAP platforms -+ * -+ * Copyright (C) 2012 Texas Instruments -+ * Author: Rob Clark -+ * -+ * This program is free software; you can redistribute it and/or modify it -+ * under the terms of the GNU General Public License version 2 as published by -+ * the Free Software Foundation. -+ * -+ * This program is distributed in the hope that it will be useful, but WITHOUT -+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or -+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for -+ * more details. -+ * -+ * You should have received a copy of the GNU General Public License along with -+ * this program. If not, see . -+ */ -+ -+#ifndef __PLATFORM_DATA_OMAP_DRM_H__ -+#define __PLATFORM_DATA_OMAP_DRM_H__ -+ -+/* -+ * Optional platform data to configure the default configuration of which -+ * pipes/overlays/CRTCs are used.. if this is not provided, then instead the -+ * first CONFIG_DRM_OMAP_NUM_CRTCS are used, and they are each connected to -+ * one manager, with priority given to managers that are connected to -+ * detected devices. Remaining overlays are used as video planes. This -+ * should be a good default behavior for most cases, but yet there still -+ * might be times when you wish to do something different. -+ */ -+struct omap_kms_platform_data { -+ /* overlays to use as CRTCs: */ -+ int ovl_cnt; -+ const int *ovl_ids; -+ -+ /* overlays to use as video planes: */ -+ int pln_cnt; -+ const int *pln_ids; -+ -+ int mgr_cnt; -+ const int *mgr_ids; -+ -+ int dev_cnt; -+ const char **dev_names; -+}; -+ -+struct omap_drm_platform_data { -+ struct omap_kms_platform_data *kms_pdata; -+}; -+ -+#endif /* __PLATFORM_DATA_OMAP_DRM_H__ */ --- -1.7.5.4 diff --git a/arm-omap-dt-compat.patch b/arm-omap-dt-compat.patch deleted file mode 100644 index 4046e93..0000000 --- a/arm-omap-dt-compat.patch +++ /dev/null @@ -1,42 +0,0 @@ -diff -up linux-2.6.39.armv7l/arch/arm/mach-omap2/board-omap3beagle.c.fdt linux-2.6.39.armv7l/arch/arm/mach-omap2/board-omap3beagle.c ---- linux-2.6.39.armv7l/arch/arm/mach-omap2/board-omap3beagle.c.fdt 2011-08-04 16:51:12.034188064 -0500 -+++ linux-2.6.39.armv7l/arch/arm/mach-omap2/board-omap3beagle.c 2011-08-04 22:13:52.801156923 -0500 -@@ -591,6 +591,11 @@ static void __init omap3_beagle_init(voi - beagle_opp_init(); - } - -+static const char *omap3_beagle_dt_match[] __initdata = { -+ "ti,omap3-beagle", -+ NULL -+}; -+ - MACHINE_START(OMAP3_BEAGLE, "OMAP3 Beagle Board") - /* Maintainer: Syed Mohammed Khasim - http://beagleboard.org */ - .boot_params = 0x80000100, -@@ -600,4 +605,5 @@ MACHINE_START(OMAP3_BEAGLE, "OMAP3 Beagl - .init_irq = omap3_beagle_init_irq, - .init_machine = omap3_beagle_init, - .timer = &omap3_secure_timer, -+ .dt_compat = omap3_beagle_dt_match, - MACHINE_END -diff -up linux-2.6.39.armv7l/arch/arm/mach-omap2/board-omap4panda.c.fdt linux-2.6.39.armv7l/arch/arm/mach-omap2/board-omap4panda.c ---- linux-2.6.39.armv7l/arch/arm/mach-omap2/board-omap4panda.c.fdt 2011-08-04 16:51:12.092169023 -0500 -+++ linux-2.6.39.armv7l/arch/arm/mach-omap2/board-omap4panda.c 2011-08-04 22:15:29.200157437 -0500 -@@ -708,6 +708,11 @@ static void __init omap4_panda_map_io(vo - omap44xx_map_common_io(); - } - -+static const char *omap4_panda_match[] __initdata = { -+ "ti,omap4-panda", -+ NULL, -+}; -+ - MACHINE_START(OMAP4_PANDA, "OMAP4 Panda board") - /* Maintainer: David Anders - Texas Instruments Inc */ - .boot_params = 0x80000100, -@@ -717,4 +722,5 @@ MACHINE_START(OMAP4_PANDA, "OMAP4 Panda - .init_irq = gic_init_irq, - .init_machine = omap4_panda_init, - .timer = &omap4_timer, -+ .dt_compat = omap4_panda_match, - MACHINE_END diff --git a/arm-smsc-support-reading-mac-address-from-device-tree.patch b/arm-smsc-support-reading-mac-address-from-device-tree.patch deleted file mode 100644 index a36c683..0000000 --- a/arm-smsc-support-reading-mac-address-from-device-tree.patch +++ /dev/null @@ -1,92 +0,0 @@ -From 0b608345e114681f66ca0a3cf9d9434728da62ce Mon Sep 17 00:00:00 2001 -From: Ken Cox -Date: Thu, 23 Jun 2011 10:36:43 -0500 -Subject: [PATCH] Support reading mac address from device tree. - -If CONFIG_OF is enabled, we will try to read the mac address from the device tree. This enables us the ability to have a "static" mac address on arm boards such as the pandaboard and beagleboard which generate random mac addresses. ---- - drivers/net/usb/smsc75xx.c | 17 +++++++++++++++++ - drivers/net/usb/smsc95xx.c | 18 +++++++++++++++++- - 2 files changed, 34 insertions(+), 1 deletions(-) - -diff --git a/drivers/net/usb/smsc75xx.c b/drivers/net/usb/smsc75xx.c -index 753ee6e..ac0a200 100644 ---- a/drivers/net/usb/smsc75xx.c -+++ b/drivers/net/usb/smsc75xx.c -@@ -29,6 +29,7 @@ - #include - #include - #include -+#include - #include "smsc75xx.h" - - #define SMSC_CHIPNAME "smsc75xx" -@@ -658,6 +659,22 @@ static int smsc75xx_ioctl(struct net_device *netdev, struct ifreq *rq, int cmd) - - static void smsc75xx_init_mac_address(struct usbnet *dev) - { -+ void *address; -+#ifdef CONFIG_OF -+ struct device_node *np; -+ -+ /* try the device tree */ -+ np = of_find_node_by_name(NULL, "smsc75xx"); -+ if (np) { -+ address = of_get_property(np, "local-mac-address", NULL); -+ if (address) { -+ memcpy(dev->net->dev_addr, address, ETH_ALEN); -+ netif_dbg(dev, ifup, dev->net, "MAC address read from device tree\n"); -+ return; -+ } -+ } -+#endif -+ - /* try reading mac address from EEPROM */ - if (smsc75xx_read_eeprom(dev, EEPROM_MAC_OFFSET, ETH_ALEN, - dev->net->dev_addr) == 0) { -diff --git a/drivers/net/usb/smsc95xx.c b/drivers/net/usb/smsc95xx.c -index bc86f4b..c83942d 100644 ---- a/drivers/net/usb/smsc95xx.c -+++ b/drivers/net/usb/smsc95xx.c -@@ -29,6 +29,7 @@ - #include - #include - #include -+#include - #include "smsc95xx.h" - - #define SMSC_CHIPNAME "smsc95xx" -@@ -639,6 +640,22 @@ static int smsc95xx_ioctl(struct net_device *netdev, struct ifreq *rq, int cmd) - - static void smsc95xx_init_mac_address(struct usbnet *dev) - { -+ void *address; -+#ifdef CONFIG_OF -+ struct device_node *np; -+ -+ /* try the device tree */ -+ np = of_find_node_by_name(NULL, "smsc95xx"); -+ if (np) { -+ address = of_get_property(np, "local-mac-address", NULL); -+ if (address) { -+ memcpy(dev->net->dev_addr, address, ETH_ALEN); -+ netif_dbg(dev, ifup, dev->net, "MAC address read from device tree\n"); -+ return; -+ } -+ } -+#endif -+ - /* try reading mac address from EEPROM */ - if (smsc95xx_read_eeprom(dev, EEPROM_MAC_OFFSET, ETH_ALEN, - dev->net->dev_addr) == 0) { -@@ -648,7 +665,6 @@ static void smsc95xx_init_mac_address(struct usbnet *dev) - return; - } - } -- - /* no eeprom, or eeprom values are invalid. generate random MAC */ - random_ether_addr(dev->net->dev_addr); - netif_dbg(dev, ifup, dev->net, "MAC address set to random_ether_addr\n"); --- -1.7.2.3 - diff --git a/config-arm-omap b/config-arm-omap index e1535a9..76fd19c 100644 --- a/config-arm-omap +++ b/config-arm-omap @@ -152,7 +152,7 @@ CONFIG_OMAP5_THERMAL=y CONFIG_WL_TI=y CONFIG_WLCORE_SDIO=m CONFIG_TI_ST=m -CONFIG_TI_CPSW=m +# CONFIG_TI_CPSW is not set CONFIG_GPIOLIB=y CONFIG_MTD_NAND_OMAP2=y CONFIG_MTD_NAND_OMAP_PREFETCH=y @@ -226,6 +226,7 @@ CONFIG_OMAP2_DSS_MIN_FCK_PER_PCK=1 CONFIG_OMAP2_DSS_SLEEP_BEFORE_RESET=y CONFIG_OMAP2_DSS_SLEEP_AFTER_VENC_RESET=y # CONFIG_FB_OMAP2 is not set +CONFIG_VIDEO_DM6446_CCDC=m CONFIG_PANEL_TFP410=m CONFIG_PANEL_PICODLP=m diff --git a/config-arm-tegra b/config-arm-tegra index 0857511..748edc5 100644 --- a/config-arm-tegra +++ b/config-arm-tegra @@ -15,7 +15,6 @@ CONFIG_MACH_SEABOARD=y CONFIG_MACH_TEGRA_DT=y CONFIG_MACH_TRIMSLICE=y CONFIG_MACH_WARIO=y -CONFIG_MACH_TEGRA_DT=y CONFIG_MACH_VENTANA=y CONFIG_TEGRA_DEBUG_UARTD=y diff --git a/config-generic b/config-generic index a0cff41..602ec29 100644 --- a/config-generic +++ b/config-generic @@ -472,6 +472,7 @@ CONFIG_SATA_ULI=m CONFIG_SATA_VIA=m CONFIG_SATA_VITESSE=m CONFIG_SATA_ACARD_AHCI=m +# CONFIG_SATA_HIGHBANK is not set # CONFIG_PATA_LEGACY is not set CONFIG_PATA_ACPI=m diff --git a/highbank-export-clock-functions.patch b/highbank-export-clock-functions.patch deleted file mode 100644 index f66754d..0000000 --- a/highbank-export-clock-functions.patch +++ /dev/null @@ -1,43 +0,0 @@ -From 81a06eed2491273b7d6d274ae4be1d333c100ab0 Mon Sep 17 00:00:00 2001 -From: Mark Langsdorf -Date: Mon, 12 Mar 2012 06:28:19 -0400 -Subject: [PATCH] highbank: export clock functions - -Signed-off-by: Mark Langsdorf ---- - arch/arm/mach-highbank/clock.c | 4 ++++ - 1 files changed, 4 insertions(+), 0 deletions(-) - -diff --git diff -up linux-3.2-rc4.orig/arch/arm/mach-highbank/clock.c diff -up linux-3.2-rc4/arch/arm/mach-highbank/clock.c -index c25a2ae..cdbc575 100644 ---- a/arch/arm/mach-highbank/clock.c -+++ b/arch/arm/mach-highbank/clock.c -@@ -27,14 +27,17 @@ int clk_enable(struct clk *clk) - { - return 0; - } -+EXPORT_SYMBOL_GPL(clk_enable); - - void clk_disable(struct clk *clk) - {} -+EXPORT_SYMBOL_GPL(clk_disable); - - unsigned long clk_get_rate(struct clk *clk) - { - return clk->rate; - } -+EXPORT_SYMBOL_GPL(clk_get_rate); - - long clk_round_rate(struct clk *clk, unsigned long rate) - { -@@ -45,6 +48,7 @@ int clk_set_rate(struct clk *clk, unsigned long rate) - { - return 0; - } -+EXPORT_SYMBOL_GPL(clk_set_rate); - - static struct clk eclk = { .rate = 200000000 }; - static struct clk pclk = { .rate = 150000000 }; --- -1.7.9.1 - diff --git a/kernel.spec b/kernel.spec index e77a252..7e51a19 100644 --- a/kernel.spec +++ b/kernel.spec @@ -712,10 +712,7 @@ Patch19001: i82975x-edac-fix.patch # ARM # Flattened devicetree support -Patch21000: arm-omap-dt-compat.patch -Patch21001: arm-smsc-support-reading-mac-address-from-device-tree.patch -# drm register derived from http://www.digipedia.pl/usenet/thread/19013/36923/ -#atch21002: arm-omap-drm-register.patch +Patch21003: arm-linux-3.6-revert-missaligned-access-check-on-put_user.patch # ARM tegra Patch21004: arm-tegra-nvec-kconfig.patch @@ -724,7 +721,7 @@ Patch21005: arm-tegra-usb-no-reset-linux33.patch # ARM highbank patches # Highbank clock functions need to be EXPORT for module builds -#atch21010: highbank-export-clock-functions.patch +Patch21010: arm-highbank-sata-fix.patch # ARM exynos4 Patch21020: arm-smdk310-regulator-fix.patch @@ -1321,12 +1318,10 @@ ApplyPatch vmbugon-warnon.patch # ARM # ApplyPatch linux-3.6-arm-build-fixup.patch -#pplyPatch arm-omap-dt-compat.patch -# ApplyPatch arm-smsc-support-reading-mac-address-from-device-tree.patch ApplyPatch arm-tegra-nvec-kconfig.patch ApplyPatch arm-tegra-usb-no-reset-linux33.patch -#pplyPatch arm-beagle-usb-init.patch -#pplyPatch arm-omap-drm-register.patch +ApplyPatch arm-highbank-sata-fix.patch +ApplyPatch arm-linux-3.6-revert-missaligned-access-check-on-put_user.patch ApplyPatch arm-smdk310-regulator-fix.patch ApplyPatch arm-origen-regulator-fix.patch @@ -2327,6 +2322,11 @@ fi # '-' | | # '-' %changelog +* Mon Oct 22 2012 Peter Robinson +- Cleanup ARM patches +- Add highbank sata patch +- add patch to revert ARM misaligned access check to stop kernel OOPS + * Thu Oct 18 2012 Josh Boyer - Patch to have mac80211 connect with HT20 if HT40 is not allowed (rhbz 866013) - Enable VFIO (rhbz 867152)