|
 |
699e7bb |
From 1a3f524e3c4da0393569f007ece81fe3ecb9352d Mon Sep 17 00:00:00 2001
|
|
|
699e7bb |
From: Guozhi Wei <carrot@google.com>
|
|
|
699e7bb |
Date: Thu, 15 Mar 2018 17:49:12 +0000
|
|
|
699e7bb |
Subject: [PATCH] [PPC] Avoid non-simple MVT in STBRX optimization
|
|
|
699e7bb |
|
|
|
699e7bb |
PR35402 triggered this case. It bswap and stores a 48bit value, current STBRX optimization transforms it into STBRX. Unfortunately 48bit is not a simple MVT, there is no PPC instruction to support it, and it can't be automatically expanded by llvm, so caused a crash.
|
|
|
699e7bb |
|
|
|
699e7bb |
This patch detects the non-simple MVT and returns early.
|
|
|
699e7bb |
|
|
|
699e7bb |
Differential Revision: https://reviews.llvm.org/D44500
|
|
|
699e7bb |
|
|
|
699e7bb |
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@327651 91177308-0d34-0410-b5e6-96231b3b80d8
|
|
|
699e7bb |
---
|
|
|
699e7bb |
lib/Target/PowerPC/PPCISelLowering.cpp | 6 +++++-
|
|
|
699e7bb |
test/CodeGen/PowerPC/pr35402.ll | 18 ++++++++++++++++++
|
|
|
699e7bb |
2 files changed, 23 insertions(+), 1 deletion(-)
|
|
|
699e7bb |
create mode 100644 test/CodeGen/PowerPC/pr35402.ll
|
|
|
699e7bb |
|
|
|
699e7bb |
diff --git a/lib/Target/PowerPC/PPCISelLowering.cpp b/lib/Target/PowerPC/PPCISelLowering.cpp
|
|
|
699e7bb |
index f9de65f..eeb1bf1 100644
|
|
|
699e7bb |
--- a/lib/Target/PowerPC/PPCISelLowering.cpp
|
|
|
699e7bb |
+++ b/lib/Target/PowerPC/PPCISelLowering.cpp
|
|
|
699e7bb |
@@ -12221,6 +12221,11 @@ SDValue PPCTargetLowering::PerformDAGCombine(SDNode *N,
|
|
|
699e7bb |
N->getOperand(1).getValueType() == MVT::i16 ||
|
|
|
699e7bb |
(Subtarget.hasLDBRX() && Subtarget.isPPC64() &&
|
|
|
699e7bb |
N->getOperand(1).getValueType() == MVT::i64))) {
|
|
|
699e7bb |
+ // STBRX can only handle simple types.
|
|
|
699e7bb |
+ EVT mVT = cast<StoreSDNode>(N)->getMemoryVT();
|
|
|
699e7bb |
+ if (mVT.isExtended())
|
|
|
699e7bb |
+ break;
|
|
|
699e7bb |
+
|
|
|
699e7bb |
SDValue BSwapOp = N->getOperand(1).getOperand(0);
|
|
|
699e7bb |
// Do an any-extend to 32-bits if this is a half-word input.
|
|
|
699e7bb |
if (BSwapOp.getValueType() == MVT::i16)
|
|
|
699e7bb |
@@ -12228,7 +12233,6 @@ SDValue PPCTargetLowering::PerformDAGCombine(SDNode *N,
|
|
|
699e7bb |
|
|
|
699e7bb |
// If the type of BSWAP operand is wider than stored memory width
|
|
|
699e7bb |
// it need to be shifted to the right side before STBRX.
|
|
|
699e7bb |
- EVT mVT = cast<StoreSDNode>(N)->getMemoryVT();
|
|
|
699e7bb |
if (Op1VT.bitsGT(mVT)) {
|
|
|
699e7bb |
int Shift = Op1VT.getSizeInBits() - mVT.getSizeInBits();
|
|
|
699e7bb |
BSwapOp = DAG.getNode(ISD::SRL, dl, Op1VT, BSwapOp,
|
|
|
699e7bb |
diff --git a/test/CodeGen/PowerPC/pr35402.ll b/test/CodeGen/PowerPC/pr35402.ll
|
|
|
699e7bb |
new file mode 100644
|
|
|
699e7bb |
index 0000000..06e6d96
|
|
|
699e7bb |
--- /dev/null
|
|
|
699e7bb |
+++ b/test/CodeGen/PowerPC/pr35402.ll
|
|
|
699e7bb |
@@ -0,0 +1,18 @@
|
|
|
699e7bb |
+; RUN: llc -O2 < %s | FileCheck %s
|
|
|
699e7bb |
+target triple = "powerpc64le-linux-gnu"
|
|
|
699e7bb |
+
|
|
|
699e7bb |
+define void @test(i8* %p, i64 %data) {
|
|
|
699e7bb |
+entry:
|
|
|
699e7bb |
+ %0 = tail call i64 @llvm.bswap.i64(i64 %data)
|
|
|
699e7bb |
+ %ptr = bitcast i8* %p to i48*
|
|
|
699e7bb |
+ %val = trunc i64 %0 to i48
|
|
|
699e7bb |
+ store i48 %val, i48* %ptr, align 1
|
|
|
699e7bb |
+ ret void
|
|
|
699e7bb |
+
|
|
|
699e7bb |
+; CHECK: sth
|
|
|
699e7bb |
+; CHECK: stw
|
|
|
699e7bb |
+; CHECK-NOT: stdbrx
|
|
|
699e7bb |
+
|
|
|
699e7bb |
+}
|
|
|
699e7bb |
+
|
|
|
699e7bb |
+declare i64 @llvm.bswap.i64(i64)
|
|
|
699e7bb |
--
|
|
|
699e7bb |
1.8.3.1
|
|
|
699e7bb |
|