ad05b5
diff -up openssl-1.0.1-beta2/engines/e_padlock.c.padlock64 openssl-1.0.1-beta2/engines/e_padlock.c
ad05b5
--- openssl-1.0.1-beta2/engines/e_padlock.c.padlock64	2011-06-21 18:42:15.000000000 +0200
ad05b5
+++ openssl-1.0.1-beta2/engines/e_padlock.c	2012-02-06 20:18:52.039537799 +0100
ad05b5
@@ -101,7 +101,10 @@
138493
    compiler choice is limited to GCC and Microsoft C. */
138493
 #undef COMPILE_HW_PADLOCK
138493
 #if !defined(I386_ONLY) && !defined(OPENSSL_NO_INLINE_ASM)
138493
-# if (defined(__GNUC__) && (defined(__i386__) || defined(__i386))) || \
138493
+# if (defined(__GNUC__) && __GNUC__>=2 && \
138493
+	(defined(__i386__) || defined(__i386) || \
138493
+	 defined(__x86_64__) || defined(__x86_64)) \
138493
+     ) || \
138493
      (defined(_MSC_VER) && defined(_M_IX86))
138493
 #  define COMPILE_HW_PADLOCK
138493
 # endif
ad05b5
@@ -137,7 +140,7 @@ void ENGINE_load_padlock (void)
138493
 # endif
138493
 #elif defined(__GNUC__)
138493
 # ifndef alloca
138493
-#  define alloca(s) __builtin_alloca(s)
138493
+#  define alloca(s) __builtin_alloca((s))
138493
 # endif
138493
 #endif
138493
 
ad05b5
@@ -304,6 +307,7 @@ static volatile struct padlock_cipher_da
138493
  * =======================================================
138493
  */
138493
 #if defined(__GNUC__) && __GNUC__>=2
138493
+#if defined(__i386__) || defined(__i386)
138493
 /*
138493
  * As for excessive "push %ebx"/"pop %ebx" found all over.
138493
  * When generating position-independent code GCC won't let
ad05b5
@@ -383,21 +387,6 @@ padlock_available(void)
138493
 	return padlock_use_ace + padlock_use_rng;
138493
 }
138493
 
138493
-#ifndef OPENSSL_NO_AES
138493
-/* Our own htonl()/ntohl() */
138493
-static inline void
138493
-padlock_bswapl(AES_KEY *ks)
138493
-{
138493
-	size_t i = sizeof(ks->rd_key)/sizeof(ks->rd_key[0]);
138493
-	unsigned int *key = ks->rd_key;
138493
-
138493
-	while (i--) {
138493
-		asm volatile ("bswapl %0" : "+r"(*key));
138493
-		key++;
138493
-	}
138493
-}
138493
-#endif
138493
-
138493
 /* Force key reload from memory to the CPU microcode.
138493
    Loading EFLAGS from the stack clears EFLAGS[30] 
138493
    which does the trick. */
ad05b5
@@ -455,12 +444,127 @@ static inline void *name(size_t cnt,		\
138493
 		: "edx", "cc", "memory");	\
138493
 	return iv;				\
138493
 }
138493
+#endif
138493
+
138493
+#elif defined(__x86_64__) || defined(__x86_64)
138493
+
138493
+/* Load supported features of the CPU to see if
138493
+   the PadLock is available. */
138493
+static int
138493
+padlock_available(void)
138493
+{
138493
+	char vendor_string[16];
138493
+	unsigned int eax, edx;
ad05b5
 
138493
+	/* Are we running on the Centaur (VIA) CPU? */
138493
+	eax = 0x00000000;
138493
+	vendor_string[12] = 0;
138493
+	asm volatile (
138493
+		"cpuid\n"
138493
+		"movl	%%ebx,(%1)\n"
138493
+		"movl	%%edx,4(%1)\n"
138493
+		"movl	%%ecx,8(%1)\n"
138493
+		: "+a"(eax) : "r"(vendor_string) : "rbx", "rcx", "rdx");
138493
+	if (strcmp(vendor_string, "CentaurHauls") != 0)
138493
+		return 0;
138493
+
138493
+	/* Check for Centaur Extended Feature Flags presence */
138493
+	eax = 0xC0000000;
138493
+	asm volatile ("cpuid"
138493
+		: "+a"(eax) : : "rbx", "rcx", "rdx");
138493
+	if (eax < 0xC0000001)
138493
+		return 0;
138493
+
138493
+	/* Read the Centaur Extended Feature Flags */
138493
+	eax = 0xC0000001;
138493
+	asm volatile ("cpuid"
138493
+		: "+a"(eax), "=d"(edx) : : "rbx", "rcx");
138493
+
138493
+	/* Fill up some flags */
138493
+	padlock_use_ace = ((edx & (0x3<<6)) == (0x3<<6));
138493
+	padlock_use_rng = ((edx & (0x3<<2)) == (0x3<<2));
138493
+
138493
+	return padlock_use_ace + padlock_use_rng;
138493
+}
ad05b5
+
138493
+/* Force key reload from memory to the CPU microcode.
138493
+   Loading EFLAGS from the stack clears EFLAGS[30] 
138493
+   which does the trick. */
138493
+static inline void
138493
+padlock_reload_key(void)
138493
+{
138493
+	asm volatile ("pushfq; popfq");
138493
+}
138493
+
138493
+#ifndef OPENSSL_NO_AES
138493
+/*
138493
+ * This is heuristic key context tracing. At first one
138493
+ * believes that one should use atomic swap instructions,
138493
+ * but it's not actually necessary. Point is that if
138493
+ * padlock_saved_context was changed by another thread
138493
+ * after we've read it and before we compare it with cdata,
138493
+ * our key *shall* be reloaded upon thread context switch
138493
+ * and we are therefore set in either case...
138493
+ */
138493
+static inline void
138493
+padlock_verify_context(struct padlock_cipher_data *cdata)
138493
+{
138493
+	asm volatile (
138493
+	"pushfq\n"
138493
+"	btl	$30,(%%rsp)\n"
138493
+"	jnc	1f\n"
138493
+"	cmpq	%2,%1\n"
138493
+"	je	1f\n"
138493
+"	popfq\n"
138493
+"	subq	$8,%%rsp\n"
138493
+"1:	addq	$8,%%rsp\n"
138493
+"	movq	%2,%0"
138493
+	:"+m"(padlock_saved_context)
138493
+	: "r"(padlock_saved_context), "r"(cdata) : "cc");
138493
+}
138493
+
138493
+/* Template for padlock_xcrypt_* modes */
138493
+/* BIG FAT WARNING: 
138493
+ * 	The offsets used with 'leal' instructions
138493
+ * 	describe items of the 'padlock_cipher_data'
138493
+ * 	structure.
138493
+ */
138493
+#define PADLOCK_XCRYPT_ASM(name,rep_xcrypt)	\
138493
+static inline void *name(size_t cnt,		\
138493
+	struct padlock_cipher_data *cdata,	\
138493
+	void *out, const void *inp) 		\
138493
+{	void *iv; 				\
138493
+	asm volatile ( "leaq	16(%0),%%rdx\n"	\
138493
+		"	leaq	32(%0),%%rbx\n"	\
138493
+			rep_xcrypt "\n"		\
138493
+		: "=a"(iv), "=c"(cnt), "=D"(out), "=S"(inp) \
138493
+		: "0"(cdata), "1"(cnt), "2"(out), "3"(inp)  \
138493
+		: "rbx", "rdx", "cc", "memory");	\
138493
+	return iv;				\
138493
+}
138493
+#endif
138493
+
138493
+#endif	/* cpu */
138493
+
138493
+#ifndef OPENSSL_NO_AES
138493
 /* Generate all functions with appropriate opcodes */
138493
 PADLOCK_XCRYPT_ASM(padlock_xcrypt_ecb, ".byte 0xf3,0x0f,0xa7,0xc8")	/* rep xcryptecb */
138493
 PADLOCK_XCRYPT_ASM(padlock_xcrypt_cbc, ".byte 0xf3,0x0f,0xa7,0xd0")	/* rep xcryptcbc */
138493
 PADLOCK_XCRYPT_ASM(padlock_xcrypt_cfb, ".byte 0xf3,0x0f,0xa7,0xe0")	/* rep xcryptcfb */
138493
 PADLOCK_XCRYPT_ASM(padlock_xcrypt_ofb, ".byte 0xf3,0x0f,0xa7,0xe8")	/* rep xcryptofb */
138493
+
138493
+/* Our own htonl()/ntohl() */
138493
+static inline void
138493
+padlock_bswapl(AES_KEY *ks)
138493
+{
138493
+	size_t i = sizeof(ks->rd_key)/sizeof(ks->rd_key[0]);
138493
+	unsigned int *key = ks->rd_key;
138493
+
138493
+	while (i--) {
138493
+		asm volatile ("bswapl %0" : "+r"(*key));
138493
+		key++;
138493
+	}
138493
+}
138493
 #endif
138493
 
138493
 /* The RNG call itself */
ad05b5
@@ -491,8 +595,8 @@ padlock_xstore(void *addr, unsigned int
138493
 static inline unsigned char *
138493
 padlock_memcpy(void *dst,const void *src,size_t n)
138493
 {
138493
-	long       *d=dst;
138493
-	const long *s=src;
138493
+	size_t       *d=dst;
138493
+	const size_t *s=src;
138493
 
138493
 	n /= sizeof(*d);
138493
 	do { *d++ = *s++; } while (--n);