From 6c054c1e5d881437cfd9f81a2296df65d4fc55fb Mon Sep 17 00:00:00 2001 From: Shakthi Kannan Date: Jun 20 2011 16:47:12 +0000 Subject: First package. --- diff --git a/.gitignore b/.gitignore index e69de29..e6f24eb 100644 --- a/.gitignore +++ b/.gitignore @@ -0,0 +1 @@ +/myhdl-0.7.tar.gz diff --git a/python-myhdl.spec b/python-myhdl.spec new file mode 100644 index 0000000..b65b109 --- /dev/null +++ b/python-myhdl.spec @@ -0,0 +1,47 @@ +%{!?python_sitelib: %global python_sitelib %(%{__python} -c "from distutils.sysconfig import get_python_lib; print get_python_lib()")} + +Name: python-myhdl +Version: 0.7 +Release: 1%{?dist} +Summary: A python hardware description and verification language + +Group: Applications/Engineering +License: LGPLv2+ +URL: http://myhdl.org +Source0: http://downloads.sourceforge.net/myhdl/myhdl-%{version}.tar.gz +BuildRoot: %{_tmppath}/%{name}-%{version}-%{release}-root-%(%{__id_u} -n) + +BuildArch: noarch +BuildRequires: python2-devel + +%description +%{name} is a Python hardware description and verification language that +helps you go from Python to silicon. MyHDL code can be converted to Verilog +and VHDL. It can also be used to convert signals, do co-simulation +with Verilog, generating test benches with test vectors for VHDL, Verilog and +supports viewing waveform by tracing signal changes in a VCD file. + +%prep +%setup -q -n myhdl-%{version} + +find -name '*.txt' | xargs chmod -x +find -name '*.py' | xargs sed -i '1s|^#!python|#!%{__python}|' + +%build +%{__python} setup.py build + +%install +rm -rf %{buildroot} +%{__python} setup.py install --skip-build --root %{buildroot} + +%clean +rm -rf %{buildroot} + +%files +%defattr(-,root,root,-) +%doc CHANGELOG.txt CHANGES.txt LICENSE.txt README.txt example +%{python_sitelib}/* + +%changelog +* Sun Jun 05 2011 Shakthi Kannan - 0.7-1 +- Initial package. diff --git a/sources b/sources index e69de29..30c3c0b 100644 --- a/sources +++ b/sources @@ -0,0 +1 @@ +0dad690fe165e4e8d4b42155b682fb63 myhdl-0.7.tar.gz