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From 37769d27270eff15d878a1c7df23407fc5f09b7f Mon Sep 17 00:00:00 2001
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From: Aurelien Jarno <aurelien@aurel32.net>
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Date: Sat, 7 Jan 2012 15:20:12 +0100
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Subject: [PATCH 19/25] target-sh4: ignore ocbp and ocbwb instructions
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ocbp and ocbwb controls the writeback of a cache line to memory. They
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are supposed to do nothing in case of a cache miss. Given QEMU only
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partially emulate caches, it is safe to ignore these instructions.
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This fixes a kernel oops when trying to access an rtl8139 NIC with
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recent versions.
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Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
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(cherry picked from commit 0cdb95549fedc73e13c147ab9dcabcc303426a07)
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---
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target-sh4/translate.c | 14 +++-----------
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1 files changed, 3 insertions(+), 11 deletions(-)
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diff --git a/target-sh4/translate.c b/target-sh4/translate.c
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index bad3577..e04a6e0 100644
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--- a/target-sh4/translate.c
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+++ b/target-sh4/translate.c
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@@ -1652,18 +1652,10 @@ static void _decode_opc(DisasContext * ctx)
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}
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return;
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case 0x00a3: /* ocbp @Rn */
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- {
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- TCGv dummy = tcg_temp_new();
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- tcg_gen_qemu_ld32s(dummy, REG(B11_8), ctx->memidx);
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- tcg_temp_free(dummy);
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- }
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- return;
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case 0x00b3: /* ocbwb @Rn */
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- {
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- TCGv dummy = tcg_temp_new();
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- tcg_gen_qemu_ld32s(dummy, REG(B11_8), ctx->memidx);
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- tcg_temp_free(dummy);
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- }
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+ /* These instructions are supposed to do nothing in case of
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+ a cache miss. Given that we only partially emulate caches
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+ it is safe to simply ignore them. */
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return;
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case 0x0083: /* pref @Rn */
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return;
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--
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1.7.7.5
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