|
 |
5544c1b |
From 1c596a9498830485a1b2f4a4445643a149179b99 Mon Sep 17 00:00:00 2001
|
|
|
5544c1b |
From: Max Filippov <jcmvbkbc@gmail.com>
|
|
|
5544c1b |
Date: Fri, 21 Sep 2012 02:59:49 +0400
|
|
|
5544c1b |
Subject: [PATCH] target-xtensa: fix extui shift amount
|
|
|
5544c1b |
|
|
|
5544c1b |
extui opcode only uses lowermost op1 bit for sa4.
|
|
|
5544c1b |
|
|
|
5544c1b |
Reported-by: malc <av1474@comtv.ru>
|
|
|
5544c1b |
Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
|
|
|
5544c1b |
Cc: qemu-stable <qemu-stable@nongnu.org>
|
|
|
5544c1b |
Signed-off-by: malc <av1474@comtv.ru>
|
|
|
5544c1b |
Signed-off-by: Michael Roth <mdroth@linux.vnet.ibm.com>
|
|
|
5544c1b |
---
|
|
|
5544c1b |
target-xtensa/translate.c | 24 +++++++++++++++++++++---
|
|
|
5544c1b |
1 file changed, 21 insertions(+), 3 deletions(-)
|
|
|
5544c1b |
|
|
|
5544c1b |
diff --git a/target-xtensa/translate.c b/target-xtensa/translate.c
|
|
|
5544c1b |
index 1900bd5..7a1c528 100644
|
|
|
5544c1b |
--- a/target-xtensa/translate.c
|
|
|
5544c1b |
+++ b/target-xtensa/translate.c
|
|
|
5544c1b |
@@ -1778,12 +1778,30 @@ static void disas_xtensa_insn(DisasContext *dc)
|
|
|
5544c1b |
case 5:
|
|
|
5544c1b |
gen_window_check2(dc, RRR_R, RRR_T);
|
|
|
5544c1b |
{
|
|
|
5544c1b |
- int shiftimm = RRR_S | (OP1 << 4);
|
|
|
5544c1b |
+ int shiftimm = RRR_S | ((OP1 & 1) << 4);
|
|
|
5544c1b |
int maskimm = (1 << (OP2 + 1)) - 1;
|
|
|
5544c1b |
|
|
|
5544c1b |
TCGv_i32 tmp = tcg_temp_new_i32();
|
|
|
5544c1b |
- tcg_gen_shri_i32(tmp, cpu_R[RRR_T], shiftimm);
|
|
|
5544c1b |
- tcg_gen_andi_i32(cpu_R[RRR_R], tmp, maskimm);
|
|
|
5544c1b |
+
|
|
|
5544c1b |
+ if (shiftimm) {
|
|
|
5544c1b |
+ tcg_gen_shri_i32(tmp, cpu_R[RRR_T], shiftimm);
|
|
|
5544c1b |
+ } else {
|
|
|
5544c1b |
+ tcg_gen_mov_i32(tmp, cpu_R[RRR_T]);
|
|
|
5544c1b |
+ }
|
|
|
5544c1b |
+
|
|
|
5544c1b |
+ switch (maskimm) {
|
|
|
5544c1b |
+ case 0xff:
|
|
|
5544c1b |
+ tcg_gen_ext8u_i32(cpu_R[RRR_R], tmp);
|
|
|
5544c1b |
+ break;
|
|
|
5544c1b |
+
|
|
|
5544c1b |
+ case 0xffff:
|
|
|
5544c1b |
+ tcg_gen_ext16u_i32(cpu_R[RRR_R], tmp);
|
|
|
5544c1b |
+ break;
|
|
|
5544c1b |
+
|
|
|
5544c1b |
+ default:
|
|
|
5544c1b |
+ tcg_gen_andi_i32(cpu_R[RRR_R], tmp, maskimm);
|
|
|
5544c1b |
+ break;
|
|
|
5544c1b |
+ }
|
|
|
5544c1b |
tcg_temp_free(tmp);
|
|
|
5544c1b |
}
|
|
|
5544c1b |
break;
|