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From fecc7bd255206876152baab622c61902133066bd Mon Sep 17 00:00:00 2001
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From: Richard Henderson <rth@twiddle.net>
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Date: Sat, 24 Mar 2012 22:11:25 +0100
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Subject: [PATCH] tcg-sparc: Support GUEST_BASE.
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Signed-off-by: Richard Henderson <rth@twiddle.net>
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Signed-off-by: Michael Roth <mdroth@linux.vnet.ibm.com>
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---
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configure | 2 ++
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tcg/sparc/tcg-target.c | 26 +++++++++++++++++++++++---
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tcg/sparc/tcg-target.h | 2 ++
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3 files changed, 27 insertions(+), 3 deletions(-)
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diff --git a/configure b/configure
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index 0590f16..9139b5c 100755
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--- a/configure
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+++ b/configure
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@@ -872,6 +872,7 @@ case "$cpu" in
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if test "$solaris" = "no" ; then
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QEMU_CFLAGS="-ffixed-g1 -ffixed-g6 $QEMU_CFLAGS"
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fi
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+ host_guest_base="yes"
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;;
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sparc64)
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LDFLAGS="-m64 $LDFLAGS"
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@@ -880,6 +881,7 @@ case "$cpu" in
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if test "$solaris" != "no" ; then
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QEMU_CFLAGS="-ffixed-g1 $QEMU_CFLAGS"
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fi
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+ host_guest_base="yes"
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;;
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s390)
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QEMU_CFLAGS="-m31 -march=z990 $QEMU_CFLAGS"
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diff --git a/tcg/sparc/tcg-target.c b/tcg/sparc/tcg-target.c
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index d89c19b..5acfeba 100644
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--- a/tcg/sparc/tcg-target.c
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+++ b/tcg/sparc/tcg-target.c
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@@ -59,6 +59,12 @@ static const char * const tcg_target_reg_names[TCG_TARGET_NB_REGS] = {
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};
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#endif
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+#ifdef CONFIG_USE_GUEST_BASE
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+# define TCG_GUEST_BASE_REG TCG_REG_I3
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+#else
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+# define TCG_GUEST_BASE_REG TCG_REG_G0
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+#endif
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+
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static const int tcg_target_reg_alloc_order[] = {
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TCG_REG_L0,
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TCG_REG_L1,
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@@ -680,6 +686,14 @@ static void tcg_target_qemu_prologue(TCGContext *s)
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tcg_out32(s, SAVE | INSN_RD(TCG_REG_O6) | INSN_RS1(TCG_REG_O6) |
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INSN_IMM13(-(TCG_TARGET_STACK_MINFRAME +
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CPU_TEMP_BUF_NLONGS * (int)sizeof(long))));
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+
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+#ifdef CONFIG_USE_GUEST_BASE
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+ if (GUEST_BASE != 0) {
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+ tcg_out_movi(s, TCG_TYPE_PTR, TCG_GUEST_BASE_REG, GUEST_BASE);
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+ tcg_regset_set_reg(s->reserved_regs, TCG_GUEST_BASE_REG);
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+ }
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+#endif
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+
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tcg_out32(s, JMPL | INSN_RD(TCG_REG_G0) | INSN_RS1(TCG_REG_I1) |
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INSN_RS2(TCG_REG_G0));
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tcg_out_mov(s, TCG_TYPE_PTR, TCG_AREG0, TCG_REG_I0);
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@@ -925,14 +939,18 @@ static void tcg_out_qemu_ld(TCGContext *s, const TCGArg *args, int sizeop)
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if (TCG_TARGET_REG_BITS == 32 && sizeop == 3) {
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int reg64 = (datalo < 16 ? datalo : TCG_REG_O0);
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- tcg_out_ldst_rr(s, reg64, addr_reg, TCG_REG_G0, qemu_ld_opc[sizeop]);
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+ tcg_out_ldst_rr(s, reg64, addr_reg,
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+ (GUEST_BASE ? TCG_GUEST_BASE_REG : TCG_REG_G0),
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+ qemu_ld_opc[sizeop]);
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tcg_out_arithi(s, datahi, reg64, 32, SHIFT_SRLX);
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if (reg64 != datalo) {
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tcg_out_mov(s, TCG_TYPE_I32, datalo, reg64);
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}
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} else {
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- tcg_out_ldst_rr(s, datalo, addr_reg, TCG_REG_G0, qemu_ld_opc[sizeop]);
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+ tcg_out_ldst_rr(s, datalo, addr_reg,
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+ (GUEST_BASE ? TCG_GUEST_BASE_REG : TCG_REG_G0),
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+ qemu_ld_opc[sizeop]);
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}
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#endif /* CONFIG_SOFTMMU */
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}
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@@ -1026,7 +1044,9 @@ static void tcg_out_qemu_st(TCGContext *s, const TCGArg *args, int sizeop)
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tcg_out_arith(s, TCG_REG_G1, TCG_REG_G1, TCG_REG_O2, ARITH_OR);
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datalo = TCG_REG_G1;
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}
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- tcg_out_ldst_rr(s, datalo, addr_reg, TCG_REG_G0, qemu_st_opc[sizeop]);
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+ tcg_out_ldst_rr(s, datalo, addr_reg,
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+ (GUEST_BASE ? TCG_GUEST_BASE_REG : TCG_REG_G0),
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+ qemu_st_opc[sizeop]);
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#endif /* CONFIG_SOFTMMU */
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}
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diff --git a/tcg/sparc/tcg-target.h b/tcg/sparc/tcg-target.h
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index adca1d2..99e9f57 100644
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--- a/tcg/sparc/tcg-target.h
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+++ b/tcg/sparc/tcg-target.h
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@@ -128,6 +128,8 @@ typedef enum {
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#define TCG_TARGET_HAS_movcond_i64 0
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#endif
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+#define TCG_TARGET_HAS_GUEST_BASE
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+
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#ifdef CONFIG_SOLARIS
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#define TCG_AREG0 TCG_REG_G2
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#elif HOST_LONG_BITS == 64
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--
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1.7.12.1
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