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From 2acbc7d596b022dca4fc147eb89e3d5f297acb1f Mon Sep 17 00:00:00 2001
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From: Stefan Weil <sw@weilnetz.de>
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Date: Tue, 18 Sep 2012 22:43:38 +0200
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Subject: [PATCH] tci: Fix for AREG0 free mode
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Support for helper functions with 5 arguments was missing
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in the code generator and in the interpreter.
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There is no need to pass the constant TCG_AREG0 from the
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code generator to the interpreter. Remove that code for
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the INDEX_op_qemu_st* opcodes.
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Signed-off-by: Stefan Weil <sw@weilnetz.de>
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Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
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Signed-off-by: Michael Roth <mdroth@linux.vnet.ibm.com>
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---
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tcg/tci/tcg-target.c | 10 +++++-----
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tci.c | 13 +++++++++----
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2 files changed, 14 insertions(+), 9 deletions(-)
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diff --git a/tcg/tci/tcg-target.c b/tcg/tci/tcg-target.c
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index 003244c..c8c2f1d 100644
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--- a/tcg/tci/tcg-target.c
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+++ b/tcg/tci/tcg-target.c
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@@ -300,7 +300,7 @@ static const int tcg_target_reg_alloc_order[] = {
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#endif
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};
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-#if MAX_OPC_PARAM_IARGS != 4
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+#if MAX_OPC_PARAM_IARGS != 5
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# error Fix needed, number of supported input arguments changed!
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#endif
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@@ -309,16 +309,18 @@ static const int tcg_target_call_iarg_regs[] = {
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TCG_REG_R1,
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TCG_REG_R2,
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TCG_REG_R3,
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-#if TCG_TARGET_REG_BITS == 32
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- /* 32 bit hosts need 2 * MAX_OPC_PARAM_IARGS registers. */
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#if 0 /* used for TCG_REG_CALL_STACK */
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TCG_REG_R4,
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#endif
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TCG_REG_R5,
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+#if TCG_TARGET_REG_BITS == 32
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+ /* 32 bit hosts need 2 * MAX_OPC_PARAM_IARGS registers. */
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TCG_REG_R6,
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TCG_REG_R7,
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#if TCG_TARGET_NB_REGS >= 16
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TCG_REG_R8,
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+ TCG_REG_R9,
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+ TCG_REG_R10,
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#else
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# error Too few input registers available
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#endif
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@@ -798,7 +800,6 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, const TCGArg *args,
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case INDEX_op_qemu_st8:
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case INDEX_op_qemu_st16:
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case INDEX_op_qemu_st32:
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- tcg_out_r(s, TCG_AREG0);
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tcg_out_r(s, *args++);
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tcg_out_r(s, *args++);
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#if TARGET_LONG_BITS > TCG_TARGET_REG_BITS
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@@ -809,7 +810,6 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, const TCGArg *args,
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#endif
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break;
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case INDEX_op_qemu_st64:
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- tcg_out_r(s, TCG_AREG0);
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tcg_out_r(s, *args++);
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#if TCG_TARGET_REG_BITS == 32
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tcg_out_r(s, *args++);
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diff --git a/tci.c b/tci.c
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index ce8a988..a4f7b78 100644
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--- a/tci.c
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+++ b/tci.c
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@@ -36,17 +36,19 @@
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tcg_abort(); \
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} while (0)
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-#if MAX_OPC_PARAM_IARGS != 4
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+#if MAX_OPC_PARAM_IARGS != 5
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# error Fix needed, number of supported input arguments changed!
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#endif
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#if TCG_TARGET_REG_BITS == 32
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typedef uint64_t (*helper_function)(tcg_target_ulong, tcg_target_ulong,
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tcg_target_ulong, tcg_target_ulong,
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tcg_target_ulong, tcg_target_ulong,
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+ tcg_target_ulong, tcg_target_ulong,
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tcg_target_ulong, tcg_target_ulong);
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#else
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typedef uint64_t (*helper_function)(tcg_target_ulong, tcg_target_ulong,
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- tcg_target_ulong, tcg_target_ulong);
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+ tcg_target_ulong, tcg_target_ulong,
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+ tcg_target_ulong);
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#endif
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/* TCI can optionally use a global register variable for env. */
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@@ -489,14 +491,17 @@ tcg_target_ulong tcg_qemu_tb_exec(CPUArchState *cpustate, uint8_t *tb_ptr)
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tci_read_reg(TCG_REG_R5),
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tci_read_reg(TCG_REG_R6),
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tci_read_reg(TCG_REG_R7),
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- tci_read_reg(TCG_REG_R8));
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+ tci_read_reg(TCG_REG_R8),
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+ tci_read_reg(TCG_REG_R9),
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+ tci_read_reg(TCG_REG_R10));
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tci_write_reg(TCG_REG_R0, tmp64);
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tci_write_reg(TCG_REG_R1, tmp64 >> 32);
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#else
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tmp64 = ((helper_function)t0)(tci_read_reg(TCG_REG_R0),
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tci_read_reg(TCG_REG_R1),
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tci_read_reg(TCG_REG_R2),
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- tci_read_reg(TCG_REG_R3));
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+ tci_read_reg(TCG_REG_R3),
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+ tci_read_reg(TCG_REG_R5));
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tci_write_reg(TCG_REG_R0, tmp64);
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#endif
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break;
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