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From 7700d225b357c66a6949834f069ea3949890119b Mon Sep 17 00:00:00 2001
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From: Christoffer Dall <christoffer.dall@linaro.org>
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Date: Mon, 18 Nov 2013 19:26:33 -0800
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Subject: [PATCH] arm_gic: Add GICC_APRn state to the GICState
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The GICC_APRn registers are not currently supported by the ARM GIC v2.0
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emulation. This patch adds the missing state.
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Note that we also change the number of APRs to use a define GIC_NR_APRS
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based on the maximum number of preemption levels. This patch also adds
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RAZ/WI accessors for the four registers on the emulated CPU interface.
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Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
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Signed-off-by: Christoffer Dall <christoffer.dall@linaro.org>
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Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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(cherry picked from commit a9d477c4e3d614409a48d12f34624c2dd9f1ec2d)
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---
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hw/intc/arm_gic.c | 5 +++++
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hw/intc/arm_gic_common.c | 5 +++--
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include/hw/intc/arm_gic_common.h | 19 +++++++++++++++++++
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3 files changed, 27 insertions(+), 2 deletions(-)
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diff --git a/hw/intc/arm_gic.c b/hw/intc/arm_gic.c
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index d31892d..9ca3f03 100644
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--- a/hw/intc/arm_gic.c
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+++ b/hw/intc/arm_gic.c
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@@ -678,6 +678,8 @@ static uint32_t gic_cpu_read(GICState *s, int cpu, int offset)
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return s->current_pending[cpu];
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case 0x1c: /* Aliased Binary Point */
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return s->abpr[cpu];
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+ case 0xd0: case 0xd4: case 0xd8: case 0xdc:
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+ return s->apr[(offset - 0xd0) / 4][cpu];
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default:
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qemu_log_mask(LOG_GUEST_ERROR,
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"gic_cpu_read: Bad offset %x\n", (int)offset);
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@@ -705,6 +707,9 @@ static void gic_cpu_write(GICState *s, int cpu, int offset, uint32_t value)
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s->abpr[cpu] = (value & 0x7);
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}
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break;
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+ case 0xd0: case 0xd4: case 0xd8: case 0xdc:
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+ qemu_log_mask(LOG_UNIMP, "Writing APR not implemented\n");
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+ break;
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default:
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qemu_log_mask(LOG_GUEST_ERROR,
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"gic_cpu_write: Bad offset %x\n", (int)offset);
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diff --git a/hw/intc/arm_gic_common.c b/hw/intc/arm_gic_common.c
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index 7966985..ec6286b 100644
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--- a/hw/intc/arm_gic_common.c
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+++ b/hw/intc/arm_gic_common.c
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@@ -58,8 +58,8 @@ static const VMStateDescription vmstate_gic_irq_state = {
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static const VMStateDescription vmstate_gic = {
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.name = "arm_gic",
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- .version_id = 6,
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- .minimum_version_id = 6,
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+ .version_id = 7,
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+ .minimum_version_id = 7,
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.pre_save = gic_pre_save,
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.post_load = gic_post_load,
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.fields = (VMStateField[]) {
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@@ -78,6 +78,7 @@ static const VMStateDescription vmstate_gic = {
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VMSTATE_UINT16_ARRAY(current_pending, GICState, GIC_NCPU),
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VMSTATE_UINT8_ARRAY(bpr, GICState, GIC_NCPU),
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VMSTATE_UINT8_ARRAY(abpr, GICState, GIC_NCPU),
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+ VMSTATE_UINT32_2DARRAY(apr, GICState, GIC_NR_APRS, GIC_NCPU),
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VMSTATE_END_OF_LIST()
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}
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};
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diff --git a/include/hw/intc/arm_gic_common.h b/include/hw/intc/arm_gic_common.h
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index 983c3cf..89384c2 100644
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--- a/include/hw/intc/arm_gic_common.h
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+++ b/include/hw/intc/arm_gic_common.h
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@@ -31,6 +31,9 @@
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/* Maximum number of possible CPU interfaces, determined by GIC architecture */
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#define GIC_NCPU 8
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+#define MAX_NR_GROUP_PRIO 128
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+#define GIC_NR_APRS (MAX_NR_GROUP_PRIO / 32)
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+
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typedef struct gic_irq_state {
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/* The enable bits are only banked for per-cpu interrupts. */
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uint8_t enabled;
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@@ -75,6 +78,22 @@ typedef struct GICState {
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uint8_t bpr[GIC_NCPU];
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uint8_t abpr[GIC_NCPU];
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+ /* The APR is implementation defined, so we choose a layout identical to
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+ * the KVM ABI layout for QEMU's implementation of the gic:
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+ * If an interrupt for preemption level X is active, then
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+ * APRn[X mod 32] == 0b1, where n = X / 32
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+ * otherwise the bit is clear.
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+ *
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+ * TODO: rewrite the interrupt acknowlege/complete routines to use
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+ * the APR registers to track the necessary information to update
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+ * s->running_priority[] on interrupt completion (ie completely remove
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+ * last_active[][] and running_irq[]). This will be necessary if we ever
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+ * want to support TCG<->KVM migration, or TCG guests which can
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+ * do power management involving powering down and restarting
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+ * the GIC.
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+ */
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+ uint32_t apr[GIC_NR_APRS][GIC_NCPU];
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+
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uint32_t num_cpu;
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MemoryRegion iomem; /* Distributor */
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