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From: Icenowy Zheng <icenowy@aosc.io>
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To: Simon Glass <sjg@chromium.org>, Kever Yang <kever.yang@rock-chips.com>,
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 Frank Wang <frank.wang@rock-chips.com>,
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 Jagan Teki <jagan@amarulasolutions.com>
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Cc: u-boot@lists.denx.de,
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	Icenowy Zheng <icenowy@aosc.io>
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Subject: [PATCH] phy: rockchip: inno-usb2: fix hang when multiple controllers
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 exit
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Date: Tue,  6 Apr 2021 23:10:59 +0800
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The OHCI and EHCI controllers are both bound to the same PHY. They will
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both do init and power_on operations when the controller is brought up
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and both do power_off and exit when the controller is stopped. However,
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the PHY uclass of U-Boot is not as sane as we thought -- they won't
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maintain a status mark for PHYs, and thus the functions of the PHYs
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could be called for multiple times. Calling init/power_on for multiple
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times have no severe problems, however calling power_off/exit for
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multiple times have a problem -- the first exit call will stop the PHY
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clock, and power_off/exit calls after it still trying to write to PHY
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registers. The write operation to PHY registers will fail because clock
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is already stopped.
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Adapt the count mechanism from phy-sun4i-usb to both init/exit and
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power_on/power_off functions to phy-rockchip-inno-usb2 to fix this
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problem. With this stopping USB controllers (manually or before booting
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a kernel) will work.
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Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
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Fixes: ac97a9ece14e ("phy: rockchip: Add Rockchip USB2PHY driver")
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---
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 drivers/phy/rockchip/phy-rockchip-inno-usb2.c | 21 +++++++++++++++++++
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 1 file changed, 21 insertions(+)
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diff --git a/drivers/phy/rockchip/phy-rockchip-inno-usb2.c b/drivers/phy/rockchip/phy-rockchip-inno-usb2.c
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index 62b8ba3a4a..be9cc99d90 100644
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--- a/drivers/phy/rockchip/phy-rockchip-inno-usb2.c
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+++ b/drivers/phy/rockchip/phy-rockchip-inno-usb2.c
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@@ -62,6 +62,8 @@ struct rockchip_usb2phy {
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 	void *reg_base;
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 	struct clk phyclk;
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 	const struct rockchip_usb2phy_cfg *phy_cfg;
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+	int init_count;
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+	int power_on_count;
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 };
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 static inline int property_enable(void *reg_base,
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@@ -92,6 +94,10 @@ static int rockchip_usb2phy_power_on(struct phy *phy)
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 	struct rockchip_usb2phy *priv = dev_get_priv(parent);
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 	const struct rockchip_usb2phy_port_cfg *port_cfg = us2phy_get_port(phy);
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+	priv->power_on_count++;
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+	if (priv->power_on_count != 1)
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+		return 0;
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+
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 	property_enable(priv->reg_base, &port_cfg->phy_sus, false);
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 	/* waiting for the utmi_clk to become stable */
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@@ -106,6 +112,10 @@ static int rockchip_usb2phy_power_off(struct phy *phy)
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 	struct rockchip_usb2phy *priv = dev_get_priv(parent);
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 	const struct rockchip_usb2phy_port_cfg *port_cfg = us2phy_get_port(phy);
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+	priv->power_on_count--;
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+	if (priv->power_on_count != 0)
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+		return 0;
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+
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 	property_enable(priv->reg_base, &port_cfg->phy_sus, true);
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 	return 0;
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@@ -118,6 +128,10 @@ static int rockchip_usb2phy_init(struct phy *phy)
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 	const struct rockchip_usb2phy_port_cfg *port_cfg = us2phy_get_port(phy);
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 	int ret;
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+	priv->init_count++;
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+	if (priv->init_count != 1)
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+		return 0;
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+
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 	ret = clk_enable(&priv->phyclk);
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 	if (ret) {
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 		dev_err(phy->dev, "failed to enable phyclk (ret=%d)\n", ret);
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@@ -140,6 +154,10 @@ static int rockchip_usb2phy_exit(struct phy *phy)
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 	struct udevice *parent = dev_get_parent(phy->dev);
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 	struct rockchip_usb2phy *priv = dev_get_priv(parent);
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+	priv->init_count--;
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+	if (priv->init_count != 0)
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+		return 0;
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+
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 	clk_disable(&priv->phyclk);
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 	return 0;
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@@ -212,6 +230,9 @@ static int rockchip_usb2phy_probe(struct udevice *dev)
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 		return ret;
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 	}
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+	priv->power_on_count = 0;
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+	priv->init_count = 0;
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+
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 	return 0;
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 }
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