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359979e |
From: Martijn Braam <martijn@brixit.nl>
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359979e |
Subject: [PATCH] rockchip: Add initial support for the PinePhone Pro
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359979e |
Date: Thu, 21 Oct 2021 19:18:43 +0200
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359979e |
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359979e |
This is a new device by PINE64 that's very similar to the Pinebook Pro
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359979e |
that's already supported.
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359979e |
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359979e |
Specification:
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359979e |
- Rockchip RK3399
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359979e |
- 4GB Dual-Channel LPDDR4
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359979e |
- 128GB eMMC
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- mSD card slot
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359979e |
- AP6255 for 802.11ac WiFi and Bluetooth
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359979e |
- 6 inch 720*1440 DSI display
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- Quectel EG25g usb modem
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- Type-C port with alt-mode display (DP 1.2) and PD charging.
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359979e |
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Signed-off-by: Martijn Braam <martijn@brixit.nl>
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---
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359979e |
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359979e |
arch/arm/dts/Makefile | 1 +
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359979e |
arch/arm/dts/rk3399-pinephone-pro-u-boot.dtsi | 44 ++
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359979e |
arch/arm/dts/rk3399-pinephone-pro.dts | 520 ++++++++++++++++++
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359979e |
arch/arm/mach-rockchip/rk3399/Kconfig | 8 +
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359979e |
board/pine64/pinephone-pro-rk3399/Kconfig | 15 +
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359979e |
board/pine64/pinephone-pro-rk3399/MAINTAINERS | 8 +
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359979e |
board/pine64/pinephone-pro-rk3399/Makefile | 1 +
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.../pinephone-pro-rk3399.c | 57 ++
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359979e |
configs/pinephone-pro-rk3399_defconfig | 92 ++++
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include/configs/pinephone-pro-rk3399.h | 23 +
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359979e |
10 files changed, 769 insertions(+)
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359979e |
create mode 100644 arch/arm/dts/rk3399-pinephone-pro-u-boot.dtsi
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359979e |
create mode 100644 arch/arm/dts/rk3399-pinephone-pro.dts
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359979e |
create mode 100644 board/pine64/pinephone-pro-rk3399/Kconfig
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359979e |
create mode 100644 board/pine64/pinephone-pro-rk3399/MAINTAINERS
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359979e |
create mode 100644 board/pine64/pinephone-pro-rk3399/Makefile
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359979e |
create mode 100644 board/pine64/pinephone-pro-rk3399/pinephone-pro-rk3399.c
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359979e |
create mode 100644 configs/pinephone-pro-rk3399_defconfig
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359979e |
create mode 100644 include/configs/pinephone-pro-rk3399.h
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359979e |
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
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359979e |
index ed3d360bb1..3206370226 100644
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359979e |
--- a/arch/arm/dts/Makefile
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359979e |
+++ b/arch/arm/dts/Makefile
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@@ -137,6 +137,7 @@ dtb-$(CONFIG_ROCKCHIP_RK3399) += \
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359979e |
rk3399-nanopi-r4s.dtb \
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359979e |
rk3399-orangepi.dtb \
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359979e |
rk3399-pinebook-pro.dtb \
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359979e |
+ rk3399-pinephone-pro.dtb \
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359979e |
rk3399-puma-haikou.dtb \
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359979e |
rk3399-roc-pc.dtb \
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359979e |
rk3399-roc-pc-mezzanine.dtb \
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diff --git a/arch/arm/dts/rk3399-pinephone-pro-u-boot.dtsi b/arch/arm/dts/rk3399-pinephone-pro-u-boot.dtsi
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359979e |
new file mode 100644
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359979e |
index 0000000000..9d44db5978
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359979e |
--- /dev/null
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359979e |
+++ b/arch/arm/dts/rk3399-pinephone-pro-u-boot.dtsi
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359979e |
@@ -0,0 +1,44 @@
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359979e |
+// SPDX-License-Identifier: GPL-2.0+
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+/*
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+ * Copyright (C) 2019 Peter Robinson <pbrobinson at gmail.com>
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359979e |
+ * Copyright (C) 2021 Martijn Braam <martijn at brixit.nl>
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359979e |
+ */
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+
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359979e |
+#include "rk3399-u-boot.dtsi"
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+#include "rk3399-sdram-lpddr4-100.dtsi"
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+
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+/ {
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+ aliases {
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+ spi0 = &spi;;
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+ };
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+
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+ chosen {
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+ u-boot,spl-boot-order = "same-as-spl", &sdhci, &sdmmc;
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+ };
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+
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359979e |
+ config {
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359979e |
+ u-boot,spl-payload-offset = <0x60000>; /* @ 384KB */
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359979e |
+ };
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359979e |
+};
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+
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359979e |
+&i2c0 {
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+ u-boot,dm-pre-reloc;
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359979e |
+};
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359979e |
+
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359979e |
+&rk818 {
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359979e |
+ u-boot,dm-pre-reloc;
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+};
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+
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+&rng {
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+ status = "okay";
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+};
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+
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+&sdhci {
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+ max-frequency = <25000000>;
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+ u-boot,dm-pre-reloc;
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359979e |
+};
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+
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+&sdmmc {
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+ max-frequency = <20000000>;
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359979e |
+ u-boot,dm-pre-reloc;
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359979e |
+};
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diff --git a/arch/arm/dts/rk3399-pinephone-pro.dts b/arch/arm/dts/rk3399-pinephone-pro.dts
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359979e |
new file mode 100644
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359979e |
index 0000000000..3fe1845ced
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359979e |
--- /dev/null
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359979e |
+++ b/arch/arm/dts/rk3399-pinephone-pro.dts
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359979e |
@@ -0,0 +1,520 @@
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+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
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+/*
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+ * Copyright (c) 2021 Martijn Braam <martijn@brixit.nl>
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+ */
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+
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+/dts-v1/;
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+#include "rk3399.dtsi"
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+#include "rk3399-opp.dtsi"
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+
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+/ {
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+ model = "Pine64 PinePhone Pro";
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+ compatible = "pine64,pinephone-pro", "rockchip,rk3399";
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+
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+ chosen {
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+ stdout-path = "serial2:1500000n8";
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+ };
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+
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+ sdio_pwrseq: sdio-pwrseq {
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+ compatible = "mmc-pwrseq-simple";
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+ pinctrl-names = "default";
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+ };
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+
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+ /* Power tree */
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+ /* Root power source */
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+ vcc_sysin: vcc-sysin {
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+ compatible = "regulator-fixed";
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+ regulator-name = "vcc_sysin";
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+ regulator-always-on;
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+ regulator-boot-on;
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+ };
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+
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359979e |
+ /* Main 3.3v supply */
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+ vcc3v3_sys: vcc3v3-sys {
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+ compatible = "regulator-fixed";
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+ regulator-name = "vcc3v3_sys";
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+ regulator-always-on;
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+ regulator-boot-on;
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+ regulator-min-microvolt = <3300000>;
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+ regulator-max-microvolt = <3300000>;
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+ vin-supply = <&vcc_sysin>;
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+
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+ regulator-state-mem {
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+ regulator-on-in-suspend;
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+ };
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+ };
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+};
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+
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+&cpu_l0 {
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+ cpu-supply = <&vdd_cpu_l>;
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+};
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+
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+&cpu_l1 {
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+ cpu-supply = <&vdd_cpu_l>;
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+};
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+
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+&cpu_l2 {
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+ cpu-supply = <&vdd_cpu_l>;
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+};
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+
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+&cpu_l3 {
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+ cpu-supply = <&vdd_cpu_l>;
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+};
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+
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+&cpu_b0 {
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+ cpu-supply = <&vdd_cpu_b>;
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+};
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+
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+&cpu_b1 {
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+ cpu-supply = <&vdd_cpu_b>;
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+};
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+
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+&emmc_phy {
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+ status = "okay";
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+};
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+
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+&gpu {
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+ mali-supply = <&vdd_gpu>;
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+ status = "okay";
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+};
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+
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+&i2c0 {
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+ clock-frequency = <400000>;
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+ i2c-scl-rising-time-ns = <168>;
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+ i2c-scl-falling-time-ns = <4>;
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+ status = "okay";
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+
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+ rk818: pmic@1c {
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+ compatible = "rockchip,rk818";
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+ reg = <0x1c>;
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+ interrupt-parent = <&gpio1>;
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+ interrupts = <RK_PC5 IRQ_TYPE_LEVEL_LOW>;
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+ #clock-cells = <1>;
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+ clock-output-names = "xin32k", "rk808-clkout2";
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+ pinctrl-names = "default";
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+ pinctrl-0 = <&pmic_int_l>;
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+ rockchip,system-power-controller;
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+ wakeup-source;
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+
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+ vcc1-supply = <&vcc_sysin>;
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+ vcc2-supply = <&vcc_sysin>;
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+ vcc3-supply = <&vcc_sysin>;
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+ vcc4-supply = <&vcc_sysin>;
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+ vcc6-supply = <&vcc_sysin>;
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+ vcc7-supply = <&vcc3v3_sys>;
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+ vcc8-supply = <&vcc_sysin>;
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+ vcc9-supply = <&vcc3v3_sys>;
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+
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+ regulators {
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+ vdd_cpu_l: DCDC_REG1 {
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+ regulator-name = "vdd_cpu_1";
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+ regulator-always-on;
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+ regulator-boot-on;
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+ regulator-min-microvolt = <750000>;
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+ regulator-max-microvolt = <1350000>;
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+ regulator-ramp-delay = <6001>;
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+ regulator-state-mem {
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+ regulator-off-in-suspend;
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+ };
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+ };
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+
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+ vdd_center: DCDC_REG2 {
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+ regulator-name = "vdd_center";
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+ regulator-always-on;
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+ regulator-boot-on;
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+ regulator-min-microvolt = <800000>;
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+ regulator-max-microvolt = <1350000>;
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+ regulator-ramp-delay = <6001>;
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+ regulator-state-mem {
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+ regulator-off-in-suspend;
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+ };
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+ };
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+
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+ vcc_ddr: DCDC_REG3 {
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+ regulator-name = "vcc_ddr";
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+ regulator-always-on;
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+ regulator-boot-on;
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+ regulator-state-mem {
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+ regulator-on-in-suspend;
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+ };
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+ };
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+
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+ vcc_1v8: DCDC_REG4 {
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+ regulator-name = "vcc_1v8";
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+ regulator-always-on;
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+ regulator-boot-on;
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+ regulator-min-microvolt = <1800000>;
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359979e |
+ regulator-max-microvolt = <1800000>;
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359979e |
+ regulator-state-mem {
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+ regulator-on-in-suspend;
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359979e |
+ regulator-suspend-microvolt = <1800000>;
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359979e |
+ };
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359979e |
+ };
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359979e |
+
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359979e |
+ vcca3v0_codec: LDO_REG1 {
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359979e |
+ regulator-name = "vcca3v0_codec";
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359979e |
+ regulator-always-on;
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359979e |
+ regulator-boot-on;
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359979e |
+ regulator-min-microvolt = <3000000>;
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359979e |
+ regulator-max-microvolt = <3000000>;
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359979e |
+ regulator-state-mem {
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359979e |
+ regulator-off-in-suspend;
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359979e |
+ };
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359979e |
+ };
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359979e |
+
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359979e |
+ vcc3v0_touch: LDO_REG2 {
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359979e |
+ regulator-name = "vcc3v0_touch";
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359979e |
+ regulator-always-on;
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359979e |
+ regulator-boot-on;
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359979e |
+ regulator-min-microvolt = <3000000>;
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359979e |
+ regulator-max-microvolt = <3000000>;
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359979e |
+ regulator-state-mem {
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+ regulator-off-in-suspend;
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359979e |
+ };
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359979e |
+ };
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359979e |
+
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359979e |
+ vcca1v8_codec: LDO_REG3 {
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359979e |
+ regulator-name = "vcca1v8_codec";
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359979e |
+ regulator-always-on;
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359979e |
+ regulator-boot-on;
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359979e |
+ regulator-min-microvolt = <1800000>;
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359979e |
+ regulator-max-microvolt = <1800000>;
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359979e |
+ regulator-state-mem {
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359979e |
+ regulator-off-in-suspend;
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359979e |
+ };
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359979e |
+ };
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359979e |
+
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359979e |
+ vcc_power_on: LDO_REG4 {
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|
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359979e |
+ regulator-name = "vcc_power_on";
|
|
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359979e |
+ regulator-always-on;
|
|
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359979e |
+ regulator-boot-on;
|
|
|
359979e |
+ regulator-min-microvolt = <3300000>;
|
|
|
359979e |
+ regulator-max-microvolt = <3300000>;
|
|
|
359979e |
+ regulator-state-mem {
|
|
|
359979e |
+ regulator-on-in-suspend;
|
|
|
359979e |
+ regulator-suspend-microvolt = <3300000>;
|
|
|
359979e |
+ };
|
|
|
359979e |
+ };
|
|
|
359979e |
+
|
|
|
359979e |
+ vcc_3v0: LDO_REG5 {
|
|
|
359979e |
+ regulator-name = "vcc_3v0";
|
|
|
359979e |
+ regulator-always-on;
|
|
|
359979e |
+ regulator-boot-on;
|
|
|
359979e |
+ regulator-min-microvolt = <3000000>;
|
|
|
359979e |
+ regulator-max-microvolt = <3000000>;
|
|
|
359979e |
+ regulator-state-mem {
|
|
|
359979e |
+ regulator-on-in-suspend;
|
|
|
359979e |
+ regulator-suspend-microvolt = <3000000>;
|
|
|
359979e |
+ };
|
|
|
359979e |
+ };
|
|
|
359979e |
+
|
|
|
359979e |
+ vcc_1v5: LDO_REG6 {
|
|
|
359979e |
+ regulator-name = "vcc_1v5";
|
|
|
359979e |
+ regulator-always-on;
|
|
|
359979e |
+ regulator-boot-on;
|
|
|
359979e |
+ regulator-min-microvolt = <1500000>;
|
|
|
359979e |
+ regulator-max-microvolt = <1500000>;
|
|
|
359979e |
+ regulator-state-mem {
|
|
|
359979e |
+ regulator-on-in-suspend;
|
|
|
359979e |
+ regulator-suspend-microvolt = <1500000>;
|
|
|
359979e |
+ };
|
|
|
359979e |
+ };
|
|
|
359979e |
+
|
|
|
359979e |
+ vcc1v8_dvp: LDO_REG7 {
|
|
|
359979e |
+ regulator-name = "vcc1v8_dvp";
|
|
|
359979e |
+ regulator-always-on;
|
|
|
359979e |
+ regulator-boot-on;
|
|
|
359979e |
+ regulator-min-microvolt = <1800000>;
|
|
|
359979e |
+ regulator-max-microvolt = <1800000>;
|
|
|
359979e |
+ regulator-state-mem {
|
|
|
359979e |
+ regulator-off-in-suspend;
|
|
|
359979e |
+ };
|
|
|
359979e |
+ };
|
|
|
359979e |
+
|
|
|
359979e |
+ vcc3v3_s3: LDO_REG8 {
|
|
|
359979e |
+ regulator-name = "vcc3v3_s3";
|
|
|
359979e |
+ regulator-always-on;
|
|
|
359979e |
+ regulator-boot-on;
|
|
|
359979e |
+ regulator-min-microvolt = <3300000>;
|
|
|
359979e |
+ regulator-max-microvolt = <3300000>;
|
|
|
359979e |
+ regulator-state-mem {
|
|
|
359979e |
+ regulator-off-in-suspend;
|
|
|
359979e |
+ };
|
|
|
359979e |
+ };
|
|
|
359979e |
+
|
|
|
359979e |
+ vcc_sd: LDO_REG9 {
|
|
|
359979e |
+ regulator-name = "vcc_sd";
|
|
|
359979e |
+ regulator-min-microvolt = <1800000>;
|
|
|
359979e |
+ regulator-max-microvolt = <3300000>;
|
|
|
359979e |
+ regulator-state-mem {
|
|
|
359979e |
+ regulator-on-in-suspend;
|
|
|
359979e |
+ regulator-suspend-microvolt = <3300000>;
|
|
|
359979e |
+ };
|
|
|
359979e |
+ };
|
|
|
359979e |
+
|
|
|
359979e |
+ vcc3v3_s0: SWITCH_REG {
|
|
|
359979e |
+ regulator-name = "vcc3v3_s0";
|
|
|
359979e |
+ regulator-always-on;
|
|
|
359979e |
+ regulator-boot-on;
|
|
|
359979e |
+ regulator-state-mem {
|
|
|
359979e |
+ regulator-on-in-suspend;
|
|
|
359979e |
+ };
|
|
|
359979e |
+ };
|
|
|
359979e |
+
|
|
|
359979e |
+ boost_otg: DCDC_BOOST {
|
|
|
359979e |
+ regulator-name = "boost_otg";
|
|
|
359979e |
+ regulator-always-on;
|
|
|
359979e |
+ regulator-boot-on;
|
|
|
359979e |
+ regulator-min-microvolt = <5000000>;
|
|
|
359979e |
+ regulator-max-microvolt = <5000000>;
|
|
|
359979e |
+ regulator-state-mem {
|
|
|
359979e |
+ regulator-on-in-suspend;
|
|
|
359979e |
+ regulator-suspend-microvolt = <5000000>;
|
|
|
359979e |
+ };
|
|
|
359979e |
+ };
|
|
|
359979e |
+
|
|
|
359979e |
+ otg_switch: OTG_SWITCH {
|
|
|
359979e |
+ regulator-name = "otg_switch";
|
|
|
359979e |
+ };
|
|
|
359979e |
+ };
|
|
|
359979e |
+ };
|
|
|
359979e |
+
|
|
|
359979e |
+ vdd_cpu_b: regulator@40 {
|
|
|
359979e |
+ compatible = "silergy,syr827";
|
|
|
359979e |
+ reg = <0x40>;
|
|
|
359979e |
+ fcs,suspend-voltage-selector = <1>;
|
|
|
359979e |
+ pinctrl-names = "default";
|
|
|
359979e |
+ pinctrl-0 = <&vsel1_pin>;
|
|
|
359979e |
+ regulator-name = "vdd_cpu_b";
|
|
|
359979e |
+ regulator-min-microvolt = <712500>;
|
|
|
359979e |
+ regulator-max-microvolt = <1500000>;
|
|
|
359979e |
+ regulator-ramp-delay = <1000>;
|
|
|
359979e |
+ regulator-always-on;
|
|
|
359979e |
+ regulator-boot-on;
|
|
|
359979e |
+
|
|
|
359979e |
+ regulator-state-mem {
|
|
|
359979e |
+ regulator-off-in-suspend;
|
|
|
359979e |
+ };
|
|
|
359979e |
+ };
|
|
|
359979e |
+
|
|
|
359979e |
+ vdd_gpu: regulator@41 {
|
|
|
359979e |
+ compatible = "silergy,syr828";
|
|
|
359979e |
+ reg = <0x41>;
|
|
|
359979e |
+ fcs,suspend-voltage-selector = <1>;
|
|
|
359979e |
+ pinctrl-names = "default";
|
|
|
359979e |
+ pinctrl-0 = <&vsel2_pin>;
|
|
|
359979e |
+ regulator-name = "vdd_gpu";
|
|
|
359979e |
+ regulator-min-microvolt = <712500>;
|
|
|
359979e |
+ regulator-max-microvolt = <1500000>;
|
|
|
359979e |
+ regulator-ramp-delay = <1000>;
|
|
|
359979e |
+ regulator-always-on;
|
|
|
359979e |
+ regulator-boot-on;
|
|
|
359979e |
+
|
|
|
359979e |
+ regulator-state-mem {
|
|
|
359979e |
+ regulator-off-in-suspend;
|
|
|
359979e |
+ };
|
|
|
359979e |
+ };
|
|
|
359979e |
+};
|
|
|
359979e |
+
|
|
|
359979e |
+&i2c1 {
|
|
|
359979e |
+ i2c-scl-rising-time-ns = <300>;
|
|
|
359979e |
+ i2c-scl-falling-time-ns = <15>;
|
|
|
359979e |
+ status = "okay";
|
|
|
359979e |
+};
|
|
|
359979e |
+
|
|
|
359979e |
+&i2c3 {
|
|
|
359979e |
+ i2c-scl-rising-time-ns = <450>;
|
|
|
359979e |
+ i2c-scl-falling-time-ns = <15>;
|
|
|
359979e |
+ status = "okay";
|
|
|
359979e |
+};
|
|
|
359979e |
+
|
|
|
359979e |
+&i2c4 {
|
|
|
359979e |
+ i2c-scl-rising-time-ns = <600>;
|
|
|
359979e |
+ i2c-scl-falling-time-ns = <20>;
|
|
|
359979e |
+ status = "okay";
|
|
|
359979e |
+
|
|
|
359979e |
+ fusb0: typec-portc@22 {
|
|
|
359979e |
+ compatible = "fcs,fusb302";
|
|
|
359979e |
+ reg = <0x22>;
|
|
|
359979e |
+ interrupt-parent = <&gpio1>;
|
|
|
359979e |
+ interrupts = <RK_PA2 IRQ_TYPE_LEVEL_LOW>;
|
|
|
359979e |
+ pinctrl-names = "default";
|
|
|
359979e |
+ pinctrl-0 = <&fusb0_int>;
|
|
|
359979e |
+ status = "okay";
|
|
|
359979e |
+ };
|
|
|
359979e |
+};
|
|
|
359979e |
+
|
|
|
359979e |
+&io_domains {
|
|
|
359979e |
+ status = "okay";
|
|
|
359979e |
+
|
|
|
359979e |
+ bt656-supply = <&vcc1v8_dvp>;
|
|
|
359979e |
+ audio-supply = <&vcca1v8_codec>;
|
|
|
359979e |
+ sdmmc-supply = <&vcc_sd>;
|
|
|
359979e |
+ gpio1830-supply = <&vcc_3v0>;
|
|
|
359979e |
+};
|
|
|
359979e |
+
|
|
|
359979e |
+&pmu_io_domains {
|
|
|
359979e |
+ pmu1830-supply = <&vcc_3v0>;
|
|
|
359979e |
+ status = "okay";
|
|
|
359979e |
+};
|
|
|
359979e |
+
|
|
|
359979e |
+&pinctrl {
|
|
|
359979e |
+ bt {
|
|
|
359979e |
+ bt_enable_h: bt-enable-h {
|
|
|
359979e |
+ rockchip,pins = <0 RK_PB1 RK_FUNC_GPIO &pcfg_pull_none>;
|
|
|
359979e |
+ };
|
|
|
359979e |
+
|
|
|
359979e |
+ bt_host_wake_l: bt-host-wake-l {
|
|
|
359979e |
+ rockchip,pins = <0 RK_PA4 RK_FUNC_GPIO &pcfg_pull_down>;
|
|
|
359979e |
+ };
|
|
|
359979e |
+
|
|
|
359979e |
+ bt_wake_l: bt-wake-l {
|
|
|
359979e |
+ rockchip,pins = <2 RK_PD3 RK_FUNC_GPIO &pcfg_pull_none>;
|
|
|
359979e |
+ };
|
|
|
359979e |
+ };
|
|
|
359979e |
+
|
|
|
359979e |
+ buttons {
|
|
|
359979e |
+ pwrbtn: pwrbtn {
|
|
|
359979e |
+ rockchip,pins = <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_up>;
|
|
|
359979e |
+ };
|
|
|
359979e |
+ };
|
|
|
359979e |
+
|
|
|
359979e |
+ fusb302x {
|
|
|
359979e |
+ fusb0_int: fusb0-int {
|
|
|
359979e |
+ rockchip,pins = <1 RK_PA2 RK_FUNC_GPIO &pcfg_pull_up>;
|
|
|
359979e |
+ };
|
|
|
359979e |
+ };
|
|
|
359979e |
+
|
|
|
359979e |
+ leds {
|
|
|
359979e |
+ work_led_pin: work-led-pin {
|
|
|
359979e |
+ rockchip,pins = <0 RK_PB3 RK_FUNC_GPIO &pcfg_pull_none>;
|
|
|
359979e |
+ };
|
|
|
359979e |
+
|
|
|
359979e |
+ diy_led_pin: diy-led-pin {
|
|
|
359979e |
+ rockchip,pins = <0 RK_PA2 RK_FUNC_GPIO &pcfg_pull_none>;
|
|
|
359979e |
+ };
|
|
|
359979e |
+ };
|
|
|
359979e |
+
|
|
|
359979e |
+ pcie {
|
|
|
359979e |
+ pcie_perst: pcie-perst {
|
|
|
359979e |
+ rockchip,pins = <2 RK_PD4 RK_FUNC_GPIO &pcfg_pull_none>;
|
|
|
359979e |
+ };
|
|
|
359979e |
+
|
|
|
359979e |
+ pcie_pwr_en: pcie-pwr-en {
|
|
|
359979e |
+ rockchip,pins = <1 RK_PD0 RK_FUNC_GPIO &pcfg_pull_none>;
|
|
|
359979e |
+ };
|
|
|
359979e |
+ };
|
|
|
359979e |
+
|
|
|
359979e |
+ pmic {
|
|
|
359979e |
+ pmic_int_l: pmic-int-l {
|
|
|
359979e |
+ rockchip,pins = <1 RK_PC5 RK_FUNC_GPIO &pcfg_pull_up>;
|
|
|
359979e |
+ };
|
|
|
359979e |
+
|
|
|
359979e |
+ vsel1_pin: vsel1-pin {
|
|
|
359979e |
+ rockchip,pins = <1 RK_PC1 RK_FUNC_GPIO &pcfg_pull_down>;
|
|
|
359979e |
+ };
|
|
|
359979e |
+
|
|
|
359979e |
+ vsel2_pin: vsel2-pin {
|
|
|
359979e |
+ rockchip,pins = <1 RK_PB6 RK_FUNC_GPIO &pcfg_pull_down>;
|
|
|
359979e |
+ };
|
|
|
359979e |
+ };
|
|
|
359979e |
+
|
|
|
359979e |
+ sdcard {
|
|
|
359979e |
+ sdmmc0_pwr_h: sdmmc0-pwr-h {
|
|
|
359979e |
+ rockchip,pins = <0 RK_PA1 RK_FUNC_GPIO &pcfg_pull_none>;
|
|
|
359979e |
+ };
|
|
|
359979e |
+
|
|
|
359979e |
+ };
|
|
|
359979e |
+
|
|
|
359979e |
+ sdio-pwrseq {
|
|
|
359979e |
+ wifi_enable_h: wifi-enable-h {
|
|
|
359979e |
+ rockchip,pins = <0 RK_PB2 RK_FUNC_GPIO &pcfg_pull_none>;
|
|
|
359979e |
+ };
|
|
|
359979e |
+ };
|
|
|
359979e |
+
|
|
|
359979e |
+ usb-typec {
|
|
|
359979e |
+ vcc5v0_typec_en: vcc5v0_typec_en {
|
|
|
359979e |
+ rockchip,pins = <1 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up>;
|
|
|
359979e |
+ };
|
|
|
359979e |
+ };
|
|
|
359979e |
+
|
|
|
359979e |
+ usb2 {
|
|
|
359979e |
+ vcc5v0_host_en: vcc5v0-host-en {
|
|
|
359979e |
+ rockchip,pins = <4 RK_PD2 RK_FUNC_GPIO &pcfg_pull_none>;
|
|
|
359979e |
+ };
|
|
|
359979e |
+ };
|
|
|
359979e |
+};
|
|
|
359979e |
+
|
|
|
359979e |
+&pwm0 {
|
|
|
359979e |
+ status = "okay";
|
|
|
359979e |
+};
|
|
|
359979e |
+
|
|
|
359979e |
+&pwm1 {
|
|
|
359979e |
+ status = "okay";
|
|
|
359979e |
+};
|
|
|
359979e |
+
|
|
|
359979e |
+&pwm2 {
|
|
|
359979e |
+ status = "okay";
|
|
|
359979e |
+};
|
|
|
359979e |
+
|
|
|
359979e |
+&sdio0 {
|
|
|
359979e |
+ bus-width = <4>;
|
|
|
359979e |
+ cap-sd-highspeed;
|
|
|
359979e |
+ cap-sdio-irq;
|
|
|
359979e |
+ disable-wp;
|
|
|
359979e |
+ keep-power-in-suspend;
|
|
|
359979e |
+ mmc-pwrseq = <&sdio_pwrseq>;
|
|
|
359979e |
+ non-removable;
|
|
|
359979e |
+ pinctrl-names = "default";
|
|
|
359979e |
+ pinctrl-0 = <&sdio0_bus4 &sdio0_cmd &sdio0_clk>;
|
|
|
359979e |
+ sd-uhs-sdr104;
|
|
|
359979e |
+ status = "okay";
|
|
|
359979e |
+};
|
|
|
359979e |
+
|
|
|
359979e |
+&sdmmc {
|
|
|
359979e |
+ bus-width = <4>;
|
|
|
359979e |
+ cap-sd-highspeed;
|
|
|
359979e |
+ cd-gpios = <&gpio0 7 GPIO_ACTIVE_LOW>;
|
|
|
359979e |
+ disable-wp;
|
|
|
359979e |
+ max-frequency = <150000000>;
|
|
|
359979e |
+ pinctrl-names = "default";
|
|
|
359979e |
+ pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_bus4>;
|
|
|
359979e |
+ vmmc-supply = <&vcc3v3_s3>;
|
|
|
359979e |
+ vqmmc-supply = <&vcc_1v8>;
|
|
|
359979e |
+ status = "okay";
|
|
|
359979e |
+};
|
|
|
359979e |
+
|
|
|
359979e |
+&sdhci {
|
|
|
359979e |
+ bus-width = <8>;
|
|
|
359979e |
+ mmc-hs200-1_8v;
|
|
|
359979e |
+ non-removable;
|
|
|
359979e |
+ status = "okay";
|
|
|
359979e |
+};
|
|
|
359979e |
+
|
|
|
359979e |
+&tsadc {
|
|
|
359979e |
+ /* tshut mode 0:CRU 1:GPIO */
|
|
|
359979e |
+ rockchip,hw-tshut-mode = <1>;
|
|
|
359979e |
+ /* tshut polarity 0:LOW 1:HIGH */
|
|
|
359979e |
+ rockchip,hw-tshut-polarity = <1>;
|
|
|
359979e |
+ status = "okay";
|
|
|
359979e |
+};
|
|
|
359979e |
+
|
|
|
359979e |
+&uart2 {
|
|
|
359979e |
+ status = "okay";
|
|
|
359979e |
+};
|
|
|
359979e |
+
|
|
|
359979e |
+&vopb {
|
|
|
359979e |
+ status = "okay";
|
|
|
359979e |
+};
|
|
|
359979e |
+
|
|
|
359979e |
+&vopb_mmu {
|
|
|
359979e |
+ status = "okay";
|
|
|
359979e |
+};
|
|
|
359979e |
+
|
|
|
359979e |
+&vopl {
|
|
|
359979e |
+ status = "okay";
|
|
|
359979e |
+};
|
|
|
359979e |
+
|
|
|
359979e |
+&vopl_mmu {
|
|
|
359979e |
+ status = "okay";
|
|
|
359979e |
+};
|
|
|
359979e |
diff --git a/arch/arm/mach-rockchip/rk3399/Kconfig b/arch/arm/mach-rockchip/rk3399/Kconfig
|
|
|
359979e |
index 17628f9171..3ba603ca80 100644
|
|
|
359979e |
--- a/arch/arm/mach-rockchip/rk3399/Kconfig
|
|
|
359979e |
+++ b/arch/arm/mach-rockchip/rk3399/Kconfig
|
|
|
359979e |
@@ -28,6 +28,13 @@ config TARGET_PINEBOOK_PRO_RK3399
|
|
|
359979e |
with 4Gb RAM, onboard eMMC, USB-C, a USB3 and USB2 port,
|
|
|
359979e |
1920*1080 screen and all the usual laptop features.
|
|
|
359979e |
|
|
|
359979e |
+config TARGET_PINEPHONE_PRO_RK3399
|
|
|
359979e |
+ bool "PinePhone Pro"
|
|
|
359979e |
+ help
|
|
|
359979e |
+ PinePhone Pro is a phone based on the Rockchip rk3399 SoC
|
|
|
359979e |
+ with 4Gb RAM, onboard eMMC, USB-C, a headphone jack,
|
|
|
359979e |
+ 720x1440 screen and an external Quectel USB modem.
|
|
|
359979e |
+
|
|
|
359979e |
config TARGET_PUMA_RK3399
|
|
|
359979e |
bool "Theobroma Systems RK3399-Q7 (Puma)"
|
|
|
359979e |
help
|
|
|
359979e |
@@ -154,6 +161,7 @@ endif # BOOTCOUNT_LIMIT
|
|
|
359979e |
source "board/firefly/roc-pc-rk3399/Kconfig"
|
|
|
359979e |
source "board/google/gru/Kconfig"
|
|
|
359979e |
source "board/pine64/pinebook-pro-rk3399/Kconfig"
|
|
|
359979e |
+source "board/pine64/pinephone-pro-rk3399/Kconfig"
|
|
|
359979e |
source "board/pine64/rockpro64_rk3399/Kconfig"
|
|
|
359979e |
source "board/rockchip/evb_rk3399/Kconfig"
|
|
|
359979e |
source "board/theobroma-systems/puma_rk3399/Kconfig"
|
|
|
359979e |
diff --git a/board/pine64/pinephone-pro-rk3399/Kconfig b/board/pine64/pinephone-pro-rk3399/Kconfig
|
|
|
359979e |
new file mode 100644
|
|
|
359979e |
index 0000000000..13d6465ae6
|
|
|
359979e |
--- /dev/null
|
|
|
359979e |
+++ b/board/pine64/pinephone-pro-rk3399/Kconfig
|
|
|
359979e |
@@ -0,0 +1,15 @@
|
|
|
359979e |
+if TARGET_PINEPHONE_PRO_RK3399
|
|
|
359979e |
+
|
|
|
359979e |
+config SYS_BOARD
|
|
|
359979e |
+ default "pinephone-pro-rk3399"
|
|
|
359979e |
+
|
|
|
359979e |
+config SYS_VENDOR
|
|
|
359979e |
+ default "pine64"
|
|
|
359979e |
+
|
|
|
359979e |
+config SYS_CONFIG_NAME
|
|
|
359979e |
+ default "pinephone-pro-rk3399"
|
|
|
359979e |
+
|
|
|
359979e |
+config BOARD_SPECIFIC_OPTIONS
|
|
|
359979e |
+ def_bool y
|
|
|
359979e |
+
|
|
|
359979e |
+endif
|
|
|
359979e |
diff --git a/board/pine64/pinephone-pro-rk3399/MAINTAINERS b/board/pine64/pinephone-pro-rk3399/MAINTAINERS
|
|
|
359979e |
new file mode 100644
|
|
|
359979e |
index 0000000000..9ca4fc4cbe
|
|
|
359979e |
--- /dev/null
|
|
|
359979e |
+++ b/board/pine64/pinephone-pro-rk3399/MAINTAINERS
|
|
|
359979e |
@@ -0,0 +1,8 @@
|
|
|
359979e |
+PINEPHONE_PRO
|
|
|
359979e |
+M: Martijn Braam <martijn@brixit.nl>
|
|
|
359979e |
+S: Maintained
|
|
|
359979e |
+F: board/pine64/rk3399-pinephone-pro/
|
|
|
359979e |
+F: include/configs/rk3399-pinephone-pro.h
|
|
|
359979e |
+F: arch/arm/dts/rk3399-pinephone-pro.dts
|
|
|
359979e |
+F: arch/arm/dts/rk3399-pinephone-pro-u-boot.dtsi
|
|
|
359979e |
+F: configs/pinephone-pro-rk3399_defconfig
|
|
|
359979e |
diff --git a/board/pine64/pinephone-pro-rk3399/Makefile b/board/pine64/pinephone-pro-rk3399/Makefile
|
|
|
359979e |
new file mode 100644
|
|
|
359979e |
index 0000000000..8d9203053e
|
|
|
359979e |
--- /dev/null
|
|
|
359979e |
+++ b/board/pine64/pinephone-pro-rk3399/Makefile
|
|
|
359979e |
@@ -0,0 +1 @@
|
|
|
359979e |
+obj-y += pinephone-pro-rk3399.o
|
|
|
359979e |
diff --git a/board/pine64/pinephone-pro-rk3399/pinephone-pro-rk3399.c b/board/pine64/pinephone-pro-rk3399/pinephone-pro-rk3399.c
|
|
|
359979e |
new file mode 100644
|
|
|
359979e |
index 0000000000..8efeb6ea3d
|
|
|
359979e |
--- /dev/null
|
|
|
359979e |
+++ b/board/pine64/pinephone-pro-rk3399/pinephone-pro-rk3399.c
|
|
|
359979e |
@@ -0,0 +1,57 @@
|
|
|
359979e |
+// SPDX-License-Identifier: GPL-2.0+
|
|
|
359979e |
+/*
|
|
|
359979e |
+ * (C) Copyright 2019 Vasily Khoruzhick <anarsoul@gmail.com>
|
|
|
359979e |
+ * (C) Copyright 2021 Martijn Braam <martijn@brixit.nl>
|
|
|
359979e |
+ */
|
|
|
359979e |
+
|
|
|
359979e |
+#include <common.h>
|
|
|
359979e |
+#include <dm.h>
|
|
|
359979e |
+#include <init.h>
|
|
|
359979e |
+#include <syscon.h>
|
|
|
359979e |
+#include <asm/io.h>
|
|
|
359979e |
+#include <asm/arch-rockchip/clock.h>
|
|
|
359979e |
+#include <asm/arch-rockchip/grf_rk3399.h>
|
|
|
359979e |
+#include <asm/arch-rockchip/hardware.h>
|
|
|
359979e |
+#include <asm/arch-rockchip/misc.h>
|
|
|
359979e |
+
|
|
|
359979e |
+#define GRF_IO_VSEL_BT565_SHIFT 0
|
|
|
359979e |
+#define PMUGRF_CON0_VSEL_SHIFT 8
|
|
|
359979e |
+
|
|
|
359979e |
+#ifdef CONFIG_MISC_INIT_R
|
|
|
359979e |
+static void setup_iodomain(void)
|
|
|
359979e |
+{
|
|
|
359979e |
+ struct rk3399_grf_regs *grf =
|
|
|
359979e |
+ syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
|
|
|
359979e |
+ struct rk3399_pmugrf_regs *pmugrf =
|
|
|
359979e |
+ syscon_get_first_range(ROCKCHIP_SYSCON_PMUGRF);
|
|
|
359979e |
+
|
|
|
359979e |
+ /* BT565 is in 1.8v domain */
|
|
|
359979e |
+ rk_setreg(&grf->io_vsel, 1 << GRF_IO_VSEL_BT565_SHIFT);
|
|
|
359979e |
+
|
|
|
359979e |
+ /* Set GPIO1 1.8v/3.0v source select to PMU1830_VOL */
|
|
|
359979e |
+ rk_setreg(&pmugrf->soc_con0, 1 << PMUGRF_CON0_VSEL_SHIFT);
|
|
|
359979e |
+}
|
|
|
359979e |
+
|
|
|
359979e |
+int misc_init_r(void)
|
|
|
359979e |
+{
|
|
|
359979e |
+ const u32 cpuid_offset = 0x7;
|
|
|
359979e |
+ const u32 cpuid_length = 0x10;
|
|
|
359979e |
+ u8 cpuid[cpuid_length];
|
|
|
359979e |
+ int ret;
|
|
|
359979e |
+
|
|
|
359979e |
+ setup_iodomain();
|
|
|
359979e |
+
|
|
|
359979e |
+ ret = rockchip_cpuid_from_efuse(cpuid_offset, cpuid_length, cpuid);
|
|
|
359979e |
+ if (ret)
|
|
|
359979e |
+ return ret;
|
|
|
359979e |
+
|
|
|
359979e |
+ ret = rockchip_cpuid_set(cpuid, cpuid_length);
|
|
|
359979e |
+ if (ret)
|
|
|
359979e |
+ return ret;
|
|
|
359979e |
+
|
|
|
359979e |
+ ret = rockchip_setup_macaddr();
|
|
|
359979e |
+
|
|
|
359979e |
+ return ret;
|
|
|
359979e |
+}
|
|
|
359979e |
+
|
|
|
359979e |
+#endif
|
|
|
359979e |
diff --git a/configs/pinephone-pro-rk3399_defconfig b/configs/pinephone-pro-rk3399_defconfig
|
|
|
359979e |
new file mode 100644
|
|
|
359979e |
index 0000000000..2cf80f7d35
|
|
|
359979e |
--- /dev/null
|
|
|
359979e |
+++ b/configs/pinephone-pro-rk3399_defconfig
|
|
|
359979e |
@@ -0,0 +1,92 @@
|
|
|
359979e |
+CONFIG_ARM=y
|
|
|
359979e |
+CONFIG_SKIP_LOWLEVEL_INIT=y
|
|
|
359979e |
+CONFIG_ARCH_ROCKCHIP=y
|
|
|
359979e |
+CONFIG_SYS_TEXT_BASE=0x00200000
|
|
|
359979e |
+CONFIG_NR_DRAM_BANKS=1
|
|
|
359979e |
+CONFIG_ENV_SIZE=0x8000
|
|
|
359979e |
+CONFIG_ROCKCHIP_RK3399=y
|
|
|
359979e |
+CONFIG_TARGET_PINEPHONE_PRO_RK3399=y
|
|
|
359979e |
+CONFIG_DEBUG_UART_BASE=0xFF1A0000
|
|
|
359979e |
+CONFIG_DEBUG_UART_CLOCK=24000000
|
|
|
359979e |
+CONFIG_SPL_SPI_FLASH_SUPPORT=y
|
|
|
359979e |
+CONFIG_SPL_SPI_SUPPORT=y
|
|
|
359979e |
+CONFIG_DEFAULT_DEVICE_TREE="rk3399-pinephone-pro"
|
|
|
359979e |
+CONFIG_DEBUG_UART=y
|
|
|
359979e |
+CONFIG_SYS_LOAD_ADDR=0x800800
|
|
|
359979e |
+CONFIG_BOOTDELAY=3
|
|
|
359979e |
+CONFIG_USE_PREBOOT=y
|
|
|
359979e |
+CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-pinephone-pro.dtb"
|
|
|
359979e |
+CONFIG_DISPLAY_BOARDINFO_LATE=y
|
|
|
359979e |
+CONFIG_MISC_INIT_R=y
|
|
|
359979e |
+# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
|
|
|
359979e |
+CONFIG_SPL_STACK_R=y
|
|
|
359979e |
+CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x10000
|
|
|
359979e |
+CONFIG_SPL_MTD_SUPPORT=y
|
|
|
359979e |
+CONFIG_SPL_SPI_LOAD=y
|
|
|
359979e |
+CONFIG_TPL=y
|
|
|
359979e |
+CONFIG_CMD_BOOTZ=y
|
|
|
359979e |
+CONFIG_CMD_GPIO=y
|
|
|
359979e |
+CONFIG_CMD_GPT=y
|
|
|
359979e |
+CONFIG_CMD_I2C=y
|
|
|
359979e |
+CONFIG_CMD_MMC=y
|
|
|
359979e |
+CONFIG_CMD_PCI=y
|
|
|
359979e |
+CONFIG_CMD_USB=y
|
|
|
359979e |
+# CONFIG_CMD_SETEXPR is not set
|
|
|
359979e |
+CONFIG_CMD_TIME=y
|
|
|
359979e |
+CONFIG_CMD_PMIC=y
|
|
|
359979e |
+CONFIG_CMD_REGULATOR=y
|
|
|
359979e |
+CONFIG_SPL_OF_CONTROL=y
|
|
|
359979e |
+CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents"
|
|
|
359979e |
+CONFIG_ENV_IS_IN_SPI_FLASH=y
|
|
|
359979e |
+CONFIG_SYS_RELOC_GD_ENV_ADDR=y
|
|
|
359979e |
+CONFIG_ROCKCHIP_GPIO=y
|
|
|
359979e |
+CONFIG_SYS_I2C_ROCKCHIP=y
|
|
|
359979e |
+CONFIG_DM_KEYBOARD=y
|
|
|
359979e |
+CONFIG_LED=y
|
|
|
359979e |
+CONFIG_LED_GPIO=y
|
|
|
359979e |
+CONFIG_MISC=y
|
|
|
359979e |
+CONFIG_ROCKCHIP_EFUSE=y
|
|
|
359979e |
+CONFIG_MMC_DW=y
|
|
|
359979e |
+CONFIG_MMC_DW_ROCKCHIP=y
|
|
|
359979e |
+CONFIG_MMC_SDHCI=y
|
|
|
359979e |
+CONFIG_MMC_SDHCI_SDMA=y
|
|
|
359979e |
+CONFIG_MMC_SDHCI_ROCKCHIP=y
|
|
|
359979e |
+CONFIG_SF_DEFAULT_SPEED=20000000
|
|
|
359979e |
+CONFIG_SPI_FLASH_GIGADEVICE=y
|
|
|
359979e |
+CONFIG_SPI_FLASH_WINBOND=y
|
|
|
359979e |
+CONFIG_DM_ETH=y
|
|
|
359979e |
+CONFIG_PHY_ROCKCHIP_INNO_USB2=y
|
|
|
359979e |
+CONFIG_PHY_ROCKCHIP_TYPEC=y
|
|
|
359979e |
+CONFIG_DM_PMIC_FAN53555=y
|
|
|
359979e |
+CONFIG_PMIC_RK8XX=y
|
|
|
359979e |
+CONFIG_REGULATOR_PWM=y
|
|
|
359979e |
+CONFIG_REGULATOR_RK8XX=y
|
|
|
359979e |
+CONFIG_PWM_ROCKCHIP=y
|
|
|
359979e |
+CONFIG_RAM_RK3399_LPDDR4=y
|
|
|
359979e |
+CONFIG_DM_RESET=y
|
|
|
359979e |
+CONFIG_DM_RNG=y
|
|
|
359979e |
+CONFIG_RNG_ROCKCHIP=y
|
|
|
359979e |
+CONFIG_BAUDRATE=1500000
|
|
|
359979e |
+CONFIG_DEBUG_UART_SHIFT=2
|
|
|
359979e |
+CONFIG_ROCKCHIP_SPI=y
|
|
|
359979e |
+CONFIG_SYSRESET=y
|
|
|
359979e |
+CONFIG_USB=y
|
|
|
359979e |
+CONFIG_USB_XHCI_HCD=y
|
|
|
359979e |
+CONFIG_USB_XHCI_DWC3=y
|
|
|
359979e |
+CONFIG_USB_EHCI_HCD=y
|
|
|
359979e |
+CONFIG_USB_EHCI_GENERIC=y
|
|
|
359979e |
+CONFIG_USB_OHCI_HCD=y
|
|
|
359979e |
+CONFIG_USB_OHCI_GENERIC=y
|
|
|
359979e |
+CONFIG_USB_DWC3=y
|
|
|
359979e |
+CONFIG_USB_DWC3_GENERIC=y
|
|
|
359979e |
+CONFIG_USB_KEYBOARD=y
|
|
|
359979e |
+CONFIG_SYS_USB_EVENT_POLL_VIA_INT_QUEUE=y
|
|
|
359979e |
+CONFIG_USB_HOST_ETHER=y
|
|
|
359979e |
+CONFIG_USB_ETHER_ASIX=y
|
|
|
359979e |
+CONFIG_USB_ETHER_RTL8152=y
|
|
|
359979e |
+CONFIG_DM_VIDEO=y
|
|
|
359979e |
+CONFIG_DISPLAY=y
|
|
|
359979e |
+CONFIG_VIDEO_ROCKCHIP=y
|
|
|
359979e |
+CONFIG_DISPLAY_ROCKCHIP_EDP=y
|
|
|
359979e |
+CONFIG_SPL_TINY_MEMSET=y
|
|
|
359979e |
+CONFIG_ERRNO_STR=y
|
|
|
359979e |
diff --git a/include/configs/pinephone-pro-rk3399.h b/include/configs/pinephone-pro-rk3399.h
|
|
|
359979e |
new file mode 100644
|
|
|
359979e |
index 0000000000..fefa793fdd
|
|
|
359979e |
--- /dev/null
|
|
|
359979e |
+++ b/include/configs/pinephone-pro-rk3399.h
|
|
|
359979e |
@@ -0,0 +1,23 @@
|
|
|
359979e |
+/* SPDX-License-Identifier: GPL-2.0+ */
|
|
|
359979e |
+/*
|
|
|
359979e |
+ * Copyright (C) 2016 Rockchip Electronics Co., Ltd
|
|
|
359979e |
+ * Copyright (C) 2020 Peter Robinson <pbrobinson at gmail.com>
|
|
|
359979e |
+ * Copyright (C) 2021 Martijn Braam <martijn@brixit.nl>
|
|
|
359979e |
+ */
|
|
|
359979e |
+
|
|
|
359979e |
+#ifndef __PINEPHONE_PRO_RK3399_H
|
|
|
359979e |
+#define __PINEPHONE_PRO_RK3399_H
|
|
|
359979e |
+
|
|
|
359979e |
+#define ROCKCHIP_DEVICE_SETTINGS \
|
|
|
359979e |
+ "stdin=serial,usbkbd\0" \
|
|
|
359979e |
+ "stdout=serial,vidconsole\0" \
|
|
|
359979e |
+ "stderr=serial,vidconsole\0"
|
|
|
359979e |
+
|
|
|
359979e |
+#include <configs/rk3399_common.h>
|
|
|
359979e |
+
|
|
|
359979e |
+#define SDRAM_BANK_SIZE (2UL << 30)
|
|
|
359979e |
+
|
|
|
359979e |
+#define CONFIG_USB_OHCI_NEW
|
|
|
359979e |
+#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 2
|
|
|
359979e |
+
|
|
|
359979e |
+#endif
|