From 85b5f80fcdf2a66970aa3c42800e2b9b9c355692 Mon Sep 17 00:00:00 2001 From: Peter Robinson Date: Jan 29 2020 09:07:19 +0000 Subject: v2020.04 rc1 --- diff --git a/Ethernet-support-for-Raspberry-Pi-4.patch b/Ethernet-support-for-Raspberry-Pi-4.patch new file mode 100644 index 0000000..799c8b6 --- /dev/null +++ b/Ethernet-support-for-Raspberry-Pi-4.patch @@ -0,0 +1,1097 @@ +From patchwork Fri Jan 17 01:20:45 2020 +Content-Type: text/plain; charset="utf-8" +MIME-Version: 1.0 +Content-Transfer-Encoding: 7bit +X-Patchwork-Submitter: Andre Przywara +X-Patchwork-Id: 1224574 +Return-Path: +X-Original-To: incoming@patchwork.ozlabs.org +Delivered-To: patchwork-incoming@bilbo.ozlabs.org +Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) + smtp.mailfrom=lists.denx.de (client-ip=85.214.62.61; + helo=phobos.denx.de; + envelope-from=u-boot-bounces@lists.denx.de; + receiver=) +Authentication-Results: ozlabs.org; + dmarc=none (p=none dis=none) header.from=arm.com +Received: from phobos.denx.de (phobos.denx.de [85.214.62.61]) + (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) + key-exchange X25519 server-signature RSA-PSS (4096 bits) + server-digest SHA256) (No client certificate requested) + by ozlabs.org (Postfix) with ESMTPS id 47zNYx20D9z9s1x + for ; + Fri, 17 Jan 2020 12:21:21 +1100 (AEDT) +Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) + by phobos.denx.de (Postfix) with ESMTP id 06756819DE; + Fri, 17 Jan 2020 02:21:12 +0100 (CET) +Authentication-Results: phobos.denx.de; + dmarc=none (p=none dis=none) header.from=arm.com +Authentication-Results: phobos.denx.de; + spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de +Received: by phobos.denx.de (Postfix, from userid 109) + id B04A3819F3; Fri, 17 Jan 2020 02:21:09 +0100 (CET) +X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on phobos.denx.de +X-Spam-Level: +X-Spam-Status: No, score=0.0 required=5.0 tests=SPF_HELO_NONE, URIBL_BLOCKED + autolearn=ham autolearn_force=no version=3.4.2 +Received: from foss.arm.com (foss.arm.com [217.140.110.172]) + by phobos.denx.de (Postfix) with ESMTP id C7E3E819C4 + for ; Fri, 17 Jan 2020 02:21:04 +0100 (CET) +Authentication-Results: phobos.denx.de; + dmarc=none (p=none dis=none) header.from=arm.com +Authentication-Results: phobos.denx.de; + spf=pass smtp.mailfrom=andre.przywara@arm.com +Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) + by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id AC38D11FB; + Thu, 16 Jan 2020 17:21:03 -0800 (PST) +Received: from localhost.localdomain (unknown [172.31.20.19]) + by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id + 28AF53F534; Thu, 16 Jan 2020 17:21:02 -0800 (PST) +From: Andre Przywara +To: Joe Hershberger , + Matthias Brugger +Subject: [PATCH v2 1/3] net: Add support for Broadcom GENETv5 Ethernet + controller +Date: Fri, 17 Jan 2020 01:20:45 +0000 +Message-Id: <20200117012047.31096-2-andre.przywara@arm.com> +X-Mailer: git-send-email 2.14.1 +In-Reply-To: <20200117012047.31096-1-andre.przywara@arm.com> +References: <20200117012047.31096-1-andre.przywara@arm.com> +X-BeenThere: u-boot@lists.denx.de +X-Mailman-Version: 2.1.26 +Precedence: list +List-Id: U-Boot discussion +List-Unsubscribe: , + +List-Archive: +List-Post: +List-Help: +List-Subscribe: , + +Cc: Sascha Dewald , u-boot@lists.denx.de, + LABBE Corentin +Errors-To: u-boot-bounces@lists.denx.de +Sender: "U-Boot" +X-Virus-Scanned: clamav-milter 0.101.4 at phobos.denx.de +X-Virus-Status: Clean + +From: Amit Singh Tomar + +The Broadcom GENET Ethernet MACs are used in several MIPS based SoCs +and in the Broadcom 2711/2838 SoC used on the Raspberry Pi 4. +There is no publicly available documentation, so this driver is based +on the Linux driver. Compared to that the queue management is +drastically simplified, also we only support version 5 of the IP and +RGMII connections between MAC and PHY, as used on the RPi4. + +Signed-off-by: Amit Singh Tomar +Reviewed-by: Andre Przywara +[Andre: heavy cleanup and a few fixes] +Signed-off-by: Andre Przywara +--- + drivers/net/Kconfig | 7 + + drivers/net/Makefile | 1 + + drivers/net/bcmgenet.c | 722 +++++++++++++++++++++++++++++++++++++++++++++++++ + 3 files changed, 730 insertions(+) + create mode 100644 drivers/net/bcmgenet.c + +diff --git a/drivers/net/Kconfig b/drivers/net/Kconfig +index 01d087f229..4d1013c984 100644 +--- a/drivers/net/Kconfig ++++ b/drivers/net/Kconfig +@@ -136,6 +136,13 @@ config BCM6368_ETH + help + This driver supports the BCM6368 Ethernet MAC. + ++config BCMGENET ++ bool "BCMGENET V5 support" ++ depends on DM_ETH ++ select PHYLIB ++ help ++ This driver supports the BCMGENET Ethernet MAC. ++ + config DWC_ETH_QOS + bool "Synopsys DWC Ethernet QOS device support" + depends on DM_ETH +diff --git a/drivers/net/Makefile b/drivers/net/Makefile +index 30991834ec..6e0a68834d 100644 +--- a/drivers/net/Makefile ++++ b/drivers/net/Makefile +@@ -8,6 +8,7 @@ obj-$(CONFIG_AG7XXX) += ag7xxx.o + obj-$(CONFIG_ARMADA100_FEC) += armada100_fec.o + obj-$(CONFIG_BCM6348_ETH) += bcm6348-eth.o + obj-$(CONFIG_BCM6368_ETH) += bcm6368-eth.o ++obj-$(CONFIG_BCMGENET) += bcmgenet.o + obj-$(CONFIG_DRIVER_AT91EMAC) += at91_emac.o + obj-$(CONFIG_DRIVER_AX88180) += ax88180.o + obj-$(CONFIG_BCM_SF2_ETH) += bcm-sf2-eth.o +diff --git a/drivers/net/bcmgenet.c b/drivers/net/bcmgenet.c +new file mode 100644 +index 0000000000..4f8f190071 +--- /dev/null ++++ b/drivers/net/bcmgenet.c +@@ -0,0 +1,722 @@ ++// SPDX-License-Identifier: GPL-2.0+ ++/* ++ * Copyright (C) 2019 Amit Singh Tomar ++ * ++ * Driver for Broadcom GENETv5 Ethernet controller (as found on the RPi4) ++ * This driver is based on the Linux driver: ++ * drivers/net/ethernet/broadcom/genet/bcmgenet.c ++ * which is: Copyright (c) 2014-2017 Broadcom ++ * ++ * The hardware supports multiple queues (16 priority queues and one ++ * default queue), both for RX and TX. There are 256 DMA descriptors (both ++ * for TX and RX), and they live in MMIO registers. The hardware allows ++ * assigning descriptor ranges to queues, but we choose the most simple setup: ++ * All 256 descriptors are assigned to the default queue (#16). ++ * Also the Linux driver supports multiple generations of the MAC, whereas ++ * we only support v5, as used in the Raspberry Pi 4. ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++/* Register definitions derived from Linux source */ ++#define SYS_REV_CTRL 0x00 ++ ++#define SYS_PORT_CTRL 0x04 ++#define PORT_MODE_EXT_GPHY 3 ++ ++#define GENET_SYS_OFF 0x0000 ++#define SYS_RBUF_FLUSH_CTRL (GENET_SYS_OFF + 0x08) ++#define SYS_TBUF_FLUSH_CTRL (GENET_SYS_OFF + 0x0c) ++ ++#define GENET_EXT_OFF 0x0080 ++#define EXT_RGMII_OOB_CTRL (GENET_EXT_OFF + 0x0c) ++#define RGMII_LINK BIT(4) ++#define OOB_DISABLE BIT(5) ++#define RGMII_MODE_EN BIT(6) ++#define ID_MODE_DIS BIT(16) ++ ++#define GENET_RBUF_OFF 0x0300 ++#define RBUF_TBUF_SIZE_CTRL (GENET_RBUF_OFF + 0xb4) ++#define RBUF_CTRL (GENET_RBUF_OFF + 0x00) ++#define RBUF_ALIGN_2B BIT(1) ++ ++#define GENET_UMAC_OFF 0x0800 ++#define UMAC_MIB_CTRL (GENET_UMAC_OFF + 0x580) ++#define UMAC_MAX_FRAME_LEN (GENET_UMAC_OFF + 0x014) ++#define UMAC_MAC0 (GENET_UMAC_OFF + 0x00c) ++#define UMAC_MAC1 (GENET_UMAC_OFF + 0x010) ++#define UMAC_CMD (GENET_UMAC_OFF + 0x008) ++#define MDIO_CMD (GENET_UMAC_OFF + 0x614) ++#define UMAC_TX_FLUSH (GENET_UMAC_OFF + 0x334) ++#define MDIO_START_BUSY BIT(29) ++#define MDIO_READ_FAIL BIT(28) ++#define MDIO_RD (2 << 26) ++#define MDIO_WR BIT(26) ++#define MDIO_PMD_SHIFT 21 ++#define MDIO_PMD_MASK 0x1f ++#define MDIO_REG_SHIFT 16 ++#define MDIO_REG_MASK 0x1f ++ ++#define CMD_TX_EN BIT(0) ++#define CMD_RX_EN BIT(1) ++#define UMAC_SPEED_10 0 ++#define UMAC_SPEED_100 1 ++#define UMAC_SPEED_1000 2 ++#define UMAC_SPEED_2500 3 ++#define CMD_SPEED_SHIFT 2 ++#define CMD_SPEED_MASK 3 ++#define CMD_SW_RESET BIT(13) ++#define CMD_LCL_LOOP_EN BIT(15) ++#define CMD_TX_EN BIT(0) ++#define CMD_RX_EN BIT(1) ++ ++#define MIB_RESET_RX BIT(0) ++#define MIB_RESET_RUNT BIT(1) ++#define MIB_RESET_TX BIT(2) ++ ++/* total number of Buffer Descriptors, same for Rx/Tx */ ++#define TOTAL_DESCS 256 ++#define RX_DESCS TOTAL_DESCS ++#define TX_DESCS TOTAL_DESCS ++ ++#define DEFAULT_Q 0x10 ++ ++/* Body(1500) + EH_SIZE(14) + VLANTAG(4) + BRCMTAG(6) + FCS(4) = 1528. ++ * 1536 is multiple of 256 bytes ++ */ ++#define ENET_BRCM_TAG_LEN 6 ++#define ENET_PAD 8 ++#define ENET_MAX_MTU_SIZE (ETH_DATA_LEN + ETH_HLEN + \ ++ VLAN_HLEN + ENET_BRCM_TAG_LEN + \ ++ ETH_FCS_LEN + ENET_PAD) ++ ++/* Tx/Rx Dma Descriptor common bits */ ++#define DMA_EN BIT(0) ++#define DMA_RING_BUF_EN_SHIFT 0x01 ++#define DMA_RING_BUF_EN_MASK 0xffff ++#define DMA_BUFLENGTH_MASK 0x0fff ++#define DMA_BUFLENGTH_SHIFT 16 ++#define DMA_RING_SIZE_SHIFT 16 ++#define DMA_OWN 0x8000 ++#define DMA_EOP 0x4000 ++#define DMA_SOP 0x2000 ++#define DMA_WRAP 0x1000 ++#define DMA_MAX_BURST_LENGTH 0x8 ++/* Tx specific DMA descriptor bits */ ++#define DMA_TX_UNDERRUN 0x0200 ++#define DMA_TX_APPEND_CRC 0x0040 ++#define DMA_TX_OW_CRC 0x0020 ++#define DMA_TX_DO_CSUM 0x0010 ++#define DMA_TX_QTAG_SHIFT 7 ++ ++/* DMA rings size */ ++#define DMA_RING_SIZE 0x40 ++#define DMA_RINGS_SIZE (DMA_RING_SIZE * (DEFAULT_Q + 1)) ++ ++/* DMA descriptor */ ++#define DMA_DESC_LENGTH_STATUS 0x00 ++#define DMA_DESC_ADDRESS_LO 0x04 ++#define DMA_DESC_ADDRESS_HI 0x08 ++#define DMA_DESC_SIZE 12 ++ ++#define GENET_RX_OFF 0x2000 ++#define GENET_RDMA_REG_OFF \ ++ (GENET_RX_OFF + TOTAL_DESCS * DMA_DESC_SIZE) ++#define GENET_TX_OFF 0x4000 ++#define GENET_TDMA_REG_OFF \ ++ (GENET_TX_OFF + TOTAL_DESCS * DMA_DESC_SIZE) ++ ++#define DMA_FC_THRESH_HI (RX_DESCS >> 4) ++#define DMA_FC_THRESH_LO 5 ++#define DMA_FC_THRESH_VALUE ((DMA_FC_THRESH_LO << 16) | \ ++ DMA_FC_THRESH_HI) ++ ++#define DMA_XOFF_THRESHOLD_SHIFT 16 ++ ++#define TDMA_RING_REG_BASE \ ++ (GENET_TDMA_REG_OFF + DEFAULT_Q * DMA_RING_SIZE) ++#define TDMA_READ_PTR (TDMA_RING_REG_BASE + 0x00) ++#define TDMA_CONS_INDEX (TDMA_RING_REG_BASE + 0x08) ++#define TDMA_PROD_INDEX (TDMA_RING_REG_BASE + 0x0c) ++#define DMA_RING_BUF_SIZE 0x10 ++#define DMA_START_ADDR 0x14 ++#define DMA_END_ADDR 0x1c ++#define DMA_MBUF_DONE_THRESH 0x24 ++#define TDMA_FLOW_PERIOD (TDMA_RING_REG_BASE + 0x28) ++#define TDMA_WRITE_PTR (TDMA_RING_REG_BASE + 0x2c) ++ ++#define RDMA_RING_REG_BASE \ ++ (GENET_RDMA_REG_OFF + DEFAULT_Q * DMA_RING_SIZE) ++#define RDMA_WRITE_PTR (RDMA_RING_REG_BASE + 0x00) ++#define RDMA_PROD_INDEX (RDMA_RING_REG_BASE + 0x08) ++#define RDMA_CONS_INDEX (RDMA_RING_REG_BASE + 0x0c) ++#define RDMA_XON_XOFF_THRESH (RDMA_RING_REG_BASE + 0x28) ++#define RDMA_READ_PTR (RDMA_RING_REG_BASE + 0x2c) ++ ++#define TDMA_REG_BASE (GENET_TDMA_REG_OFF + DMA_RINGS_SIZE) ++#define RDMA_REG_BASE (GENET_RDMA_REG_OFF + DMA_RINGS_SIZE) ++#define DMA_RING_CFG 0x00 ++#define DMA_CTRL 0x04 ++#define DMA_SCB_BURST_SIZE 0x0c ++ ++#define RX_BUF_LENGTH 2048 ++#define RX_TOTAL_BUFSIZE (RX_BUF_LENGTH * RX_DESCS) ++#define RX_BUF_OFFSET 2 ++ ++struct bcmgenet_eth_priv { ++ char rxbuffer[RX_TOTAL_BUFSIZE] __aligned(ARCH_DMA_MINALIGN); ++ void *mac_reg; ++ void *tx_desc_base; ++ void *rx_desc_base; ++ int tx_index; ++ int rx_index; ++ int c_index; ++ int phyaddr; ++ u32 interface; ++ u32 speed; ++ struct phy_device *phydev; ++ struct mii_dev *bus; ++}; ++ ++static void bcmgenet_umac_reset(struct bcmgenet_eth_priv *priv) ++{ ++ u32 reg; ++ ++ reg = readl(priv->mac_reg + SYS_RBUF_FLUSH_CTRL); ++ reg |= BIT(1); ++ writel(reg, (priv->mac_reg + SYS_RBUF_FLUSH_CTRL)); ++ udelay(10); ++ ++ reg &= ~BIT(1); ++ writel(reg, (priv->mac_reg + SYS_RBUF_FLUSH_CTRL)); ++ udelay(10); ++ ++ writel(0, (priv->mac_reg + SYS_RBUF_FLUSH_CTRL)); ++ udelay(10); ++ ++ writel(0, priv->mac_reg + UMAC_CMD); ++ ++ writel(CMD_SW_RESET | CMD_LCL_LOOP_EN, priv->mac_reg + UMAC_CMD); ++ udelay(2); ++ writel(0, priv->mac_reg + UMAC_CMD); ++ ++ /* clear tx/rx counter */ ++ writel(MIB_RESET_RX | MIB_RESET_TX | MIB_RESET_RUNT, ++ priv->mac_reg + UMAC_MIB_CTRL); ++ writel(0, priv->mac_reg + UMAC_MIB_CTRL); ++ ++ writel(ENET_MAX_MTU_SIZE, priv->mac_reg + UMAC_MAX_FRAME_LEN); ++ ++ /* init rx registers, enable ip header optimization */ ++ reg = readl(priv->mac_reg + RBUF_CTRL); ++ reg |= RBUF_ALIGN_2B; ++ writel(reg, (priv->mac_reg + RBUF_CTRL)); ++ ++ writel(1, (priv->mac_reg + RBUF_TBUF_SIZE_CTRL)); ++} ++ ++static int bcmgenet_gmac_write_hwaddr(struct udevice *dev) ++{ ++ struct bcmgenet_eth_priv *priv = dev_get_priv(dev); ++ struct eth_pdata *pdata = dev_get_platdata(dev); ++ uchar *addr = pdata->enetaddr; ++ u32 reg; ++ ++ reg = addr[0] << 24 | addr[1] << 16 | addr[2] << 8 | addr[3]; ++ writel_relaxed(reg, priv->mac_reg + UMAC_MAC0); ++ ++ reg = addr[4] << 8 | addr[5]; ++ writel_relaxed(reg, priv->mac_reg + UMAC_MAC1); ++ ++ return 0; ++} ++ ++static void bcmgenet_disable_dma(struct bcmgenet_eth_priv *priv) ++{ ++ clrbits_32(priv->mac_reg + TDMA_REG_BASE + DMA_CTRL, DMA_EN); ++ clrbits_32(priv->mac_reg + RDMA_REG_BASE + DMA_CTRL, DMA_EN); ++ ++ writel(1, priv->mac_reg + UMAC_TX_FLUSH); ++ udelay(10); ++ writel(0, priv->mac_reg + UMAC_TX_FLUSH); ++} ++ ++static void bcmgenet_enable_dma(struct bcmgenet_eth_priv *priv) ++{ ++ u32 dma_ctrl = (1 << (DEFAULT_Q + DMA_RING_BUF_EN_SHIFT)) | DMA_EN; ++ ++ writel(dma_ctrl, priv->mac_reg + TDMA_REG_BASE + DMA_CTRL); ++ ++ setbits_32(priv->mac_reg + RDMA_REG_BASE + DMA_CTRL, dma_ctrl); ++} ++ ++static int bcmgenet_gmac_eth_send(struct udevice *dev, void *packet, int length) ++{ ++ struct bcmgenet_eth_priv *priv = dev_get_priv(dev); ++ void *desc_base = priv->tx_desc_base + priv->tx_index * DMA_DESC_SIZE; ++ u32 len_stat = length << DMA_BUFLENGTH_SHIFT; ++ ulong packet_aligned = rounddown((ulong)packet, ARCH_DMA_MINALIGN); ++ u32 prod_index, cons; ++ u32 tries = 100; ++ ++ prod_index = readl(priv->mac_reg + TDMA_PROD_INDEX); ++ ++ /* There is actually no reason for the rounding here, but the ARMv7 ++ * implementation of flush_dcache_range() checks for aligned ++ * boundaries of the flushed range. ++ * Adjust them here to pass that check and avoid misleading messages. ++ */ ++ flush_dcache_range(packet_aligned, ++ packet_aligned + roundup(length, ARCH_DMA_MINALIGN)); ++ ++ len_stat |= 0x3F << DMA_TX_QTAG_SHIFT; ++ len_stat |= DMA_TX_APPEND_CRC | DMA_SOP | DMA_EOP; ++ ++ /* Set-up packet for transmission */ ++ writel(lower_32_bits((ulong)packet), (desc_base + DMA_DESC_ADDRESS_LO)); ++ writel(upper_32_bits((ulong)packet), (desc_base + DMA_DESC_ADDRESS_HI)); ++ writel(len_stat, (desc_base + DMA_DESC_LENGTH_STATUS)); ++ ++ /* Increment index and start transmission */ ++ if (++priv->tx_index >= TX_DESCS) ++ priv->tx_index = 0; ++ ++ prod_index++; ++ ++ /* Start Transmisson */ ++ writel(prod_index, priv->mac_reg + TDMA_PROD_INDEX); ++ ++ do { ++ cons = readl(priv->mac_reg + TDMA_CONS_INDEX); ++ } while ((cons & 0xffff) < prod_index && --tries); ++ if (!tries) ++ return -ETIMEDOUT; ++ ++ return 0; ++} ++ ++/* Check whether all cache lines affected by an invalidate are within ++ * the buffer, to make sure we don't accidentally lose unrelated dirty ++ * data stored nearby. ++ * Alignment of the buffer start address will be checked in the implementation ++ * of invalidate_dcache_range(). ++ */ ++static void invalidate_dcache_check(unsigned long addr, size_t size, ++ size_t buffer_size) ++{ ++ size_t inval_size = roundup(size, ARCH_DMA_MINALIGN); ++ ++ if (unlikely(inval_size > buffer_size)) ++ printf("WARNING: Cache invalidate area exceeds buffer size\n"); ++ ++ invalidate_dcache_range(addr, addr + inval_size); ++} ++ ++static int bcmgenet_gmac_eth_recv(struct udevice *dev, ++ int flags, uchar **packetp) ++{ ++ struct bcmgenet_eth_priv *priv = dev_get_priv(dev); ++ void *desc_base = priv->rx_desc_base + priv->rx_index * DMA_DESC_SIZE; ++ u32 prod_index = readl(priv->mac_reg + RDMA_PROD_INDEX); ++ u32 length, addr; ++ ++ if (prod_index == priv->c_index) ++ return -EAGAIN; ++ ++ length = readl(desc_base + DMA_DESC_LENGTH_STATUS); ++ length = (length >> DMA_BUFLENGTH_SHIFT) & DMA_BUFLENGTH_MASK; ++ addr = readl(desc_base + DMA_DESC_ADDRESS_LO); ++ ++ invalidate_dcache_check(addr, length, RX_BUF_LENGTH); ++ ++ /* To cater for the IP header alignment the hardware does. ++ * This would actually not be needed if we don't program ++ * RBUF_ALIGN_2B ++ */ ++ *packetp = (uchar *)(ulong)addr + RX_BUF_OFFSET; ++ ++ return length - RX_BUF_OFFSET; ++} ++ ++static int bcmgenet_gmac_free_pkt(struct udevice *dev, uchar *packet, ++ int length) ++{ ++ struct bcmgenet_eth_priv *priv = dev_get_priv(dev); ++ ++ /* Tell the MAC we have consumed that last receive buffer. */ ++ priv->c_index = (priv->c_index + 1) & 0xFFFF; ++ writel(priv->c_index, priv->mac_reg + RDMA_CONS_INDEX); ++ ++ /* Forward our descriptor pointer, wrapping around if needed. */ ++ if (++priv->rx_index >= RX_DESCS) ++ priv->rx_index = 0; ++ ++ return 0; ++} ++ ++static void rx_descs_init(struct bcmgenet_eth_priv *priv) ++{ ++ char *rxbuffs = &priv->rxbuffer[0]; ++ u32 len_stat, i; ++ void *desc_base = priv->rx_desc_base; ++ ++ priv->c_index = 0; ++ ++ len_stat = (RX_BUF_LENGTH << DMA_BUFLENGTH_SHIFT) | DMA_OWN; ++ ++ for (i = 0; i < RX_DESCS; i++) { ++ writel(lower_32_bits((uintptr_t)&rxbuffs[i * RX_BUF_LENGTH]), ++ desc_base + i * DMA_DESC_SIZE + DMA_DESC_ADDRESS_LO); ++ writel(upper_32_bits((uintptr_t)&rxbuffs[i * RX_BUF_LENGTH]), ++ desc_base + i * DMA_DESC_SIZE + DMA_DESC_ADDRESS_HI); ++ writel(len_stat, ++ desc_base + i * DMA_DESC_SIZE + DMA_DESC_LENGTH_STATUS); ++ } ++} ++ ++static void rx_ring_init(struct bcmgenet_eth_priv *priv) ++{ ++ writel(DMA_MAX_BURST_LENGTH, ++ priv->mac_reg + RDMA_REG_BASE + DMA_SCB_BURST_SIZE); ++ ++ writel(0x0, priv->mac_reg + RDMA_RING_REG_BASE + DMA_START_ADDR); ++ writel(0x0, priv->mac_reg + RDMA_READ_PTR); ++ writel(0x0, priv->mac_reg + RDMA_WRITE_PTR); ++ writel(RX_DESCS * DMA_DESC_SIZE / 4 - 1, ++ priv->mac_reg + RDMA_RING_REG_BASE + DMA_END_ADDR); ++ ++ writel(0x0, priv->mac_reg + RDMA_PROD_INDEX); ++ writel(0x0, priv->mac_reg + RDMA_CONS_INDEX); ++ writel((RX_DESCS << DMA_RING_SIZE_SHIFT) | RX_BUF_LENGTH, ++ priv->mac_reg + RDMA_RING_REG_BASE + DMA_RING_BUF_SIZE); ++ writel(DMA_FC_THRESH_VALUE, priv->mac_reg + RDMA_XON_XOFF_THRESH); ++ writel(1 << DEFAULT_Q, priv->mac_reg + RDMA_REG_BASE + DMA_RING_CFG); ++} ++ ++static void tx_ring_init(struct bcmgenet_eth_priv *priv) ++{ ++ writel(DMA_MAX_BURST_LENGTH, ++ priv->mac_reg + TDMA_REG_BASE + DMA_SCB_BURST_SIZE); ++ ++ writel(0x0, priv->mac_reg + TDMA_RING_REG_BASE + DMA_START_ADDR); ++ writel(0x0, priv->mac_reg + TDMA_READ_PTR); ++ writel(0x0, priv->mac_reg + TDMA_WRITE_PTR); ++ writel(TX_DESCS * DMA_DESC_SIZE / 4 - 1, ++ priv->mac_reg + TDMA_RING_REG_BASE + DMA_END_ADDR); ++ writel(0x0, priv->mac_reg + TDMA_PROD_INDEX); ++ writel(0x0, priv->mac_reg + TDMA_CONS_INDEX); ++ writel(0x1, priv->mac_reg + TDMA_RING_REG_BASE + DMA_MBUF_DONE_THRESH); ++ writel(0x0, priv->mac_reg + TDMA_FLOW_PERIOD); ++ writel((TX_DESCS << DMA_RING_SIZE_SHIFT) | RX_BUF_LENGTH, ++ priv->mac_reg + TDMA_RING_REG_BASE + DMA_RING_BUF_SIZE); ++ ++ writel(1 << DEFAULT_Q, priv->mac_reg + TDMA_REG_BASE + DMA_RING_CFG); ++} ++ ++static int bcmgenet_adjust_link(struct bcmgenet_eth_priv *priv) ++{ ++ struct phy_device *phy_dev = priv->phydev; ++ u32 speed; ++ ++ switch (phy_dev->speed) { ++ case SPEED_1000: ++ speed = UMAC_SPEED_1000; ++ break; ++ case SPEED_100: ++ speed = UMAC_SPEED_100; ++ break; ++ case SPEED_10: ++ speed = UMAC_SPEED_10; ++ break; ++ default: ++ printf("bcmgenet: Unsupported PHY speed: %d\n", phy_dev->speed); ++ return -EINVAL; ++ } ++ ++ clrsetbits_32(priv->mac_reg + EXT_RGMII_OOB_CTRL, OOB_DISABLE, ++ RGMII_LINK | RGMII_MODE_EN | ID_MODE_DIS); ++ ++ writel(speed << CMD_SPEED_SHIFT, (priv->mac_reg + UMAC_CMD)); ++ ++ return 0; ++} ++ ++static int bcmgenet_gmac_eth_start(struct udevice *dev) ++{ ++ struct bcmgenet_eth_priv *priv = dev_get_priv(dev); ++ int ret; ++ ++ priv->tx_desc_base = priv->mac_reg + GENET_TX_OFF; ++ priv->rx_desc_base = priv->mac_reg + GENET_RX_OFF; ++ priv->tx_index = 0x0; ++ priv->rx_index = 0x0; ++ ++ bcmgenet_umac_reset(priv); ++ ++ bcmgenet_gmac_write_hwaddr(dev); ++ ++ /* Disable RX/TX DMA and flush TX queues */ ++ bcmgenet_disable_dma(priv); ++ ++ rx_ring_init(priv); ++ rx_descs_init(priv); ++ ++ tx_ring_init(priv); ++ ++ /* Enable RX/TX DMA */ ++ bcmgenet_enable_dma(priv); ++ ++ /* read PHY properties over the wire from generic PHY set-up */ ++ ret = phy_startup(priv->phydev); ++ if (ret) { ++ printf("bcmgenet: PHY startup failed: %d\n", ret); ++ return ret; ++ } ++ ++ /* Update MAC registers based on PHY property */ ++ ret = bcmgenet_adjust_link(priv); ++ if (ret) { ++ printf("bcmgenet: adjust PHY link failed: %d\n", ret); ++ return ret; ++ } ++ ++ /* Enable Rx/Tx */ ++ setbits_32(priv->mac_reg + UMAC_CMD, CMD_TX_EN | CMD_RX_EN); ++ ++ return 0; ++} ++ ++static int bcmgenet_phy_init(struct bcmgenet_eth_priv *priv, void *dev) ++{ ++ struct phy_device *phydev; ++ int ret; ++ ++ phydev = phy_connect(priv->bus, priv->phyaddr, dev, priv->interface); ++ if (!phydev) ++ return -ENODEV; ++ ++ phydev->supported &= PHY_GBIT_FEATURES; ++ if (priv->speed) { ++ ret = phy_set_supported(priv->phydev, priv->speed); ++ if (ret) ++ return ret; ++ } ++ phydev->advertising = phydev->supported; ++ ++ phy_connect_dev(phydev, dev); ++ ++ priv->phydev = phydev; ++ phy_config(priv->phydev); ++ ++ return 0; ++} ++ ++static void bcmgenet_mdio_start(struct bcmgenet_eth_priv *priv) ++{ ++ setbits_32(priv->mac_reg + MDIO_CMD, MDIO_START_BUSY); ++} ++ ++static int bcmgenet_mdio_write(struct mii_dev *bus, int addr, int devad, ++ int reg, u16 value) ++{ ++ struct udevice *dev = bus->priv; ++ struct bcmgenet_eth_priv *priv = dev_get_priv(dev); ++ u32 val; ++ ++ /* Prepare the read operation */ ++ val = MDIO_WR | (addr << MDIO_PMD_SHIFT) | ++ (reg << MDIO_REG_SHIFT) | (0xffff & value); ++ writel_relaxed(val, priv->mac_reg + MDIO_CMD); ++ ++ /* Start MDIO transaction */ ++ bcmgenet_mdio_start(priv); ++ ++ return wait_for_bit_32(priv->mac_reg + MDIO_CMD, ++ MDIO_START_BUSY, false, 20, true); ++} ++ ++static int bcmgenet_mdio_read(struct mii_dev *bus, int addr, int devad, int reg) ++{ ++ struct udevice *dev = bus->priv; ++ struct bcmgenet_eth_priv *priv = dev_get_priv(dev); ++ u32 val; ++ int ret; ++ ++ /* Prepare the read operation */ ++ val = MDIO_RD | (addr << MDIO_PMD_SHIFT) | (reg << MDIO_REG_SHIFT); ++ writel_relaxed(val, priv->mac_reg + MDIO_CMD); ++ ++ /* Start MDIO transaction */ ++ bcmgenet_mdio_start(priv); ++ ++ ret = wait_for_bit_32(priv->mac_reg + MDIO_CMD, ++ MDIO_START_BUSY, false, 20, true); ++ if (ret) ++ return ret; ++ ++ val = readl_relaxed(priv->mac_reg + MDIO_CMD); ++ ++ return val & 0xffff; ++} ++ ++static int bcmgenet_mdio_init(const char *name, struct udevice *priv) ++{ ++ struct mii_dev *bus = mdio_alloc(); ++ ++ if (!bus) { ++ debug("Failed to allocate MDIO bus\n"); ++ return -ENOMEM; ++ } ++ ++ bus->read = bcmgenet_mdio_read; ++ bus->write = bcmgenet_mdio_write; ++ snprintf(bus->name, sizeof(bus->name), name); ++ bus->priv = (void *)priv; ++ ++ return mdio_register(bus); ++} ++ ++/* We only support RGMII (as used on the RPi4). */ ++static int bcmgenet_interface_set(struct bcmgenet_eth_priv *priv) ++{ ++ phy_interface_t phy_mode = priv->interface; ++ ++ switch (phy_mode) { ++ case PHY_INTERFACE_MODE_RGMII: ++ case PHY_INTERFACE_MODE_RGMII_RXID: ++ writel(PORT_MODE_EXT_GPHY, priv->mac_reg + SYS_PORT_CTRL); ++ break; ++ default: ++ printf("unknown phy mode: %d\n", priv->interface); ++ return -EINVAL; ++ } ++ ++ return 0; ++} ++ ++static int bcmgenet_eth_probe(struct udevice *dev) ++{ ++ struct eth_pdata *pdata = dev_get_platdata(dev); ++ struct bcmgenet_eth_priv *priv = dev_get_priv(dev); ++ ofnode mdio_node; ++ const char *name; ++ u32 reg; ++ int ret; ++ u8 major; ++ ++ priv->mac_reg = map_physmem(pdata->iobase, SZ_64K, MAP_NOCACHE); ++ priv->interface = pdata->phy_interface; ++ priv->speed = pdata->max_speed; ++ ++ /* Read GENET HW version */ ++ reg = readl_relaxed(priv->mac_reg + SYS_REV_CTRL); ++ major = (reg >> 24) & 0x0f; ++ if (major != 6) { ++ if (major == 5) ++ major = 4; ++ else if (major == 0) ++ major = 1; ++ ++ printf("Unsupported GENETv%d.%d\n", major, (reg >> 16) & 0x0f); ++ return -ENODEV; ++ } ++ ++ ret = bcmgenet_interface_set(priv); ++ if (ret) ++ return ret; ++ ++ mdio_node = dev_read_first_subnode(dev); ++ name = ofnode_get_name(mdio_node); ++ ++ ret = bcmgenet_mdio_init(name, dev); ++ if (ret) ++ return ret; ++ ++ priv->bus = miiphy_get_dev_by_name(name); ++ ++ return bcmgenet_phy_init(priv, dev); ++} ++ ++static void bcmgenet_gmac_eth_stop(struct udevice *dev) ++{ ++ struct bcmgenet_eth_priv *priv = dev_get_priv(dev); ++ ++ clrbits_32(priv->mac_reg + UMAC_CMD, CMD_TX_EN | CMD_RX_EN); ++ clrbits_32(priv->mac_reg + TDMA_REG_BASE + DMA_CTRL, ++ 1 << (DEFAULT_Q + DMA_RING_BUF_EN_SHIFT) | DMA_EN); ++} ++ ++static const struct eth_ops bcmgenet_gmac_eth_ops = { ++ .start = bcmgenet_gmac_eth_start, ++ .write_hwaddr = bcmgenet_gmac_write_hwaddr, ++ .send = bcmgenet_gmac_eth_send, ++ .recv = bcmgenet_gmac_eth_recv, ++ .free_pkt = bcmgenet_gmac_free_pkt, ++ .stop = bcmgenet_gmac_eth_stop, ++}; ++ ++static int bcmgenet_eth_ofdata_to_platdata(struct udevice *dev) ++{ ++ struct eth_pdata *pdata = dev_get_platdata(dev); ++ struct bcmgenet_eth_priv *priv = dev_get_priv(dev); ++ struct ofnode_phandle_args phy_node; ++ const char *phy_mode; ++ int ret; ++ ++ pdata->iobase = dev_read_addr(dev); ++ ++ /* Get phy mode from DT */ ++ pdata->phy_interface = -1; ++ phy_mode = dev_read_string(dev, "phy-mode"); ++ if (phy_mode) ++ pdata->phy_interface = phy_get_interface_by_name(phy_mode); ++ if (pdata->phy_interface == -1) { ++ debug("%s: Invalid PHY interface '%s'\n", __func__, phy_mode); ++ return -EINVAL; ++ } ++ ++ ret = dev_read_phandle_with_args(dev, "phy-handle", NULL, 0, 0, ++ &phy_node); ++ if (!ret) { ++ ofnode_read_s32(phy_node.node, "reg", &priv->phyaddr); ++ ofnode_read_s32(phy_node.node, "max-speed", &pdata->max_speed); ++ } ++ ++ return 0; ++} ++ ++/* The BCM2711 implementation has a limited burst length compared to a generic ++ * GENETv5 version, but we go with that shorter value (8) in both cases, for ++ * the sake of simplicity. ++ */ ++static const struct udevice_id bcmgenet_eth_ids[] = { ++ {.compatible = "brcm,genet-v5"}, ++ {.compatible = "brcm,bcm2711-genet-v5"}, ++ {} ++}; ++ ++U_BOOT_DRIVER(eth_bcmgenet) = { ++ .name = "eth_bcmgenet", ++ .id = UCLASS_ETH, ++ .of_match = bcmgenet_eth_ids, ++ .ofdata_to_platdata = bcmgenet_eth_ofdata_to_platdata, ++ .probe = bcmgenet_eth_probe, ++ .ops = &bcmgenet_gmac_eth_ops, ++ .priv_auto_alloc_size = sizeof(struct bcmgenet_eth_priv), ++ .platdata_auto_alloc_size = sizeof(struct eth_pdata), ++ .flags = DM_FLAG_ALLOC_PRIV_DMA, ++}; + +From patchwork Fri Jan 17 01:20:46 2020 +Content-Type: text/plain; charset="utf-8" +MIME-Version: 1.0 +Content-Transfer-Encoding: 7bit +X-Patchwork-Submitter: Andre Przywara +X-Patchwork-Id: 1224577 +Return-Path: +X-Original-To: incoming@patchwork.ozlabs.org +Delivered-To: patchwork-incoming@bilbo.ozlabs.org +Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) + smtp.mailfrom=lists.denx.de (client-ip=85.214.62.61; + helo=phobos.denx.de; + envelope-from=u-boot-bounces@lists.denx.de; + receiver=) +Authentication-Results: ozlabs.org; + dmarc=none (p=none dis=none) header.from=arm.com +Received: from phobos.denx.de (phobos.denx.de [85.214.62.61]) + (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) + key-exchange X25519 server-signature RSA-PSS (4096 bits)) + (No client certificate requested) + by ozlabs.org (Postfix) with ESMTPS id 47zNZQ66yWz9s1x + for ; + Fri, 17 Jan 2020 12:21:50 +1100 (AEDT) +Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) + by phobos.denx.de (Postfix) with ESMTP id CC16E81A1E; + Fri, 17 Jan 2020 02:21:18 +0100 (CET) +Authentication-Results: phobos.denx.de; + dmarc=none (p=none dis=none) header.from=arm.com +Authentication-Results: phobos.denx.de; + spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de +Received: by phobos.denx.de (Postfix, from userid 109) + id 1F1A7819EB; Fri, 17 Jan 2020 02:21:13 +0100 (CET) +X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on phobos.denx.de +X-Spam-Level: +X-Spam-Status: No, score=0.0 required=5.0 tests=SPF_HELO_NONE, URIBL_BLOCKED + autolearn=ham autolearn_force=no version=3.4.2 +Received: from foss.arm.com (foss.arm.com [217.140.110.172]) + by phobos.denx.de (Postfix) with ESMTP id 7315B819D9 + for ; Fri, 17 Jan 2020 02:21:06 +0100 (CET) +Authentication-Results: phobos.denx.de; + dmarc=none (p=none dis=none) header.from=arm.com +Authentication-Results: phobos.denx.de; + spf=pass smtp.mailfrom=andre.przywara@arm.com +Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) + by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 52F10113E; + Thu, 16 Jan 2020 17:21:05 -0800 (PST) +Received: from localhost.localdomain (unknown [172.31.20.19]) + by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id + E28533F534; Thu, 16 Jan 2020 17:21:03 -0800 (PST) +From: Andre Przywara +To: Joe Hershberger , + Matthias Brugger +Subject: [PATCH v2 2/3] rpi4: Update memory map to accommodate scb devices +Date: Fri, 17 Jan 2020 01:20:46 +0000 +Message-Id: <20200117012047.31096-3-andre.przywara@arm.com> +X-Mailer: git-send-email 2.14.1 +In-Reply-To: <20200117012047.31096-1-andre.przywara@arm.com> +References: <20200117012047.31096-1-andre.przywara@arm.com> +X-BeenThere: u-boot@lists.denx.de +X-Mailman-Version: 2.1.26 +Precedence: list +List-Id: U-Boot discussion +List-Unsubscribe: , + +List-Archive: +List-Post: +List-Help: +List-Subscribe: , + +Cc: Sascha Dewald , u-boot@lists.denx.de, + LABBE Corentin +Errors-To: u-boot-bounces@lists.denx.de +Sender: "U-Boot" +X-Virus-Scanned: clamav-milter 0.101.4 at phobos.denx.de +X-Virus-Status: Clean + +From: Amit Singh Tomar + +Some of the devices(for instance, pcie and gnet controller) sitting on +SCB bus falls behind/below the memory range that we currenty have. + +This patch updates the memory range to map those devices correctly. + +Signed-off-by: Amit Singh Tomar +Reviewed-by: Andre Przywara +Signed-off-by: Andre Przywara +--- + arch/arm/mach-bcm283x/init.c | 6 +++--- + 1 file changed, 3 insertions(+), 3 deletions(-) + +diff --git a/arch/arm/mach-bcm283x/init.c b/arch/arm/mach-bcm283x/init.c +index 3b5f45b431..9966d6c833 100644 +--- a/arch/arm/mach-bcm283x/init.c ++++ b/arch/arm/mach-bcm283x/init.c +@@ -42,9 +42,9 @@ static struct mm_region bcm2711_mem_map[] = { + .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | + PTE_BLOCK_INNER_SHARE + }, { +- .virt = 0xfe000000UL, +- .phys = 0xfe000000UL, +- .size = 0x01800000UL, ++ .virt = 0xfc000000UL, ++ .phys = 0xfc000000UL, ++ .size = 0x03800000UL, + .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | + PTE_BLOCK_NON_SHARE | + PTE_BLOCK_PXN | PTE_BLOCK_UXN + +From patchwork Fri Jan 17 01:20:47 2020 +Content-Type: text/plain; charset="utf-8" +MIME-Version: 1.0 +Content-Transfer-Encoding: 7bit +X-Patchwork-Submitter: Andre Przywara +X-Patchwork-Id: 1224576 +Return-Path: +X-Original-To: incoming@patchwork.ozlabs.org +Delivered-To: patchwork-incoming@bilbo.ozlabs.org +Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) + smtp.mailfrom=lists.denx.de + (client-ip=2a01:238:438b:c500:173d:9f52:ddab:ee01; + helo=phobos.denx.de; + envelope-from=u-boot-bounces@lists.denx.de; + receiver=) +Authentication-Results: ozlabs.org; + dmarc=none (p=none dis=none) header.from=arm.com +Received: from phobos.denx.de (phobos.denx.de + [IPv6:2a01:238:438b:c500:173d:9f52:ddab:ee01]) + (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) + key-exchange X25519 server-signature RSA-PSS (4096 bits)) + (No client certificate requested) + by ozlabs.org (Postfix) with ESMTPS id 47zNZD44jHz9s1x + for ; + Fri, 17 Jan 2020 12:21:40 +1100 (AEDT) +Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) + by phobos.denx.de (Postfix) with ESMTP id 4B69B81A0E; + Fri, 17 Jan 2020 02:21:16 +0100 (CET) +Authentication-Results: phobos.denx.de; + dmarc=none (p=none dis=none) header.from=arm.com +Authentication-Results: phobos.denx.de; + spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de +Received: by phobos.denx.de (Postfix, from userid 109) + id 8833A819EB; Fri, 17 Jan 2020 02:21:12 +0100 (CET) +X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on phobos.denx.de +X-Spam-Level: +X-Spam-Status: No, score=0.0 required=5.0 tests=SPF_HELO_NONE, URIBL_BLOCKED + autolearn=ham autolearn_force=no version=3.4.2 +Received: from foss.arm.com (foss.arm.com [217.140.110.172]) + by phobos.denx.de (Postfix) with ESMTP id 4813C819EB + for ; Fri, 17 Jan 2020 02:21:07 +0100 (CET) +Authentication-Results: phobos.denx.de; + dmarc=none (p=none dis=none) header.from=arm.com +Authentication-Results: phobos.denx.de; + spf=pass smtp.mailfrom=andre.przywara@arm.com +Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) + by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id EE23A11FB; + Thu, 16 Jan 2020 17:21:06 -0800 (PST) +Received: from localhost.localdomain (unknown [172.31.20.19]) + by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id + 88DE23F534; Thu, 16 Jan 2020 17:21:05 -0800 (PST) +From: Andre Przywara +To: Joe Hershberger , + Matthias Brugger +Subject: [PATCH v2 3/3] rpi4: Enable GENET Ethernet controller +Date: Fri, 17 Jan 2020 01:20:47 +0000 +Message-Id: <20200117012047.31096-4-andre.przywara@arm.com> +X-Mailer: git-send-email 2.14.1 +In-Reply-To: <20200117012047.31096-1-andre.przywara@arm.com> +References: <20200117012047.31096-1-andre.przywara@arm.com> +X-BeenThere: u-boot@lists.denx.de +X-Mailman-Version: 2.1.26 +Precedence: list +List-Id: U-Boot discussion +List-Unsubscribe: , + +List-Archive: +List-Post: +List-Help: +List-Subscribe: , + +Cc: Sascha Dewald , u-boot@lists.denx.de, + LABBE Corentin +Errors-To: u-boot-bounces@lists.denx.de +Sender: "U-Boot" +X-Virus-Scanned: clamav-milter 0.101.4 at phobos.denx.de +X-Virus-Status: Clean + +From: Amit Singh Tomar + +The Raspberry Pi 4 SoC features an integrated Gigabit Ethernet +controller, connected as a platform device. + +Enable the new driver in the three applicable defconfigs, to allow +TFTP booting on the board. + +Signed-off-by: Amit Singh Tomar +[Andre: Add joined and 32-bit configs] +Signed-off-by: Andre Przywara +--- + configs/rpi_4_32b_defconfig | 2 ++ + configs/rpi_4_defconfig | 2 ++ + configs/rpi_arm64_defconfig | 1 + + 3 files changed, 5 insertions(+) + +diff --git a/configs/rpi_4_32b_defconfig b/configs/rpi_4_32b_defconfig +index 00f80f71ad..e7ea88bd4b 100644 +--- a/configs/rpi_4_32b_defconfig ++++ b/configs/rpi_4_32b_defconfig +@@ -24,6 +24,8 @@ CONFIG_DM_KEYBOARD=y + CONFIG_DM_MMC=y + CONFIG_MMC_SDHCI=y + CONFIG_MMC_SDHCI_BCM2835=y ++CONFIG_DM_ETH=y ++CONFIG_BCMGENET=y + CONFIG_PINCTRL=y + # CONFIG_PINCTRL_GENERIC is not set + # CONFIG_REQUIRE_SERIAL_CONSOLE is not set +diff --git a/configs/rpi_4_defconfig b/configs/rpi_4_defconfig +index 8cf1bb81ff..b0f9cf1c0e 100644 +--- a/configs/rpi_4_defconfig ++++ b/configs/rpi_4_defconfig +@@ -24,6 +24,8 @@ CONFIG_DM_KEYBOARD=y + CONFIG_DM_MMC=y + CONFIG_MMC_SDHCI=y + CONFIG_MMC_SDHCI_BCM2835=y ++CONFIG_DM_ETH=y ++CONFIG_BCMGENET=y + CONFIG_PINCTRL=y + # CONFIG_PINCTRL_GENERIC is not set + # CONFIG_REQUIRE_SERIAL_CONSOLE is not set +diff --git a/configs/rpi_arm64_defconfig b/configs/rpi_arm64_defconfig +index 10fbe0db92..00b3096481 100644 +--- a/configs/rpi_arm64_defconfig ++++ b/configs/rpi_arm64_defconfig +@@ -36,6 +36,7 @@ CONFIG_USB_KEYBOARD=y + CONFIG_USB_HOST_ETHER=y + CONFIG_USB_ETHER_LAN78XX=y + CONFIG_USB_ETHER_SMSC95XX=y ++CONFIG_BCMGENET=y + CONFIG_DM_VIDEO=y + CONFIG_VIDEO_BPP32=y + CONFIG_SYS_WHITE_ON_BLACK=y diff --git a/sources b/sources index 03c2370..0a45ad1 100644 --- a/sources +++ b/sources @@ -1 +1 @@ -SHA512 (u-boot-2020.01.tar.bz2) = 073d4e0234095c1bda1ffa7a648972aa4530d106ee1a73035e0501b1aba2951653582c8b7bcf338d4e95012fa67e75f97b7e1fbac5cc764d609b671ef29617f7 +SHA512 (u-boot-2020.04-rc1.tar.bz2) = 06c6974a7d04258d6c05bb43ae8e03dbea5f290f07ed457be01927f68d825a80825e0157fa4a7df6e47a035f119075779c059d23c2d4545ec72212f1c22d3cbf diff --git a/uboot-tools.spec b/uboot-tools.spec index ea84748..519e577 100644 --- a/uboot-tools.spec +++ b/uboot-tools.spec @@ -1,8 +1,8 @@ -#global candidate rc5 +%global candidate rc1 Name: uboot-tools -Version: 2020.01 -Release: 1%{?candidate:.%{candidate}}%{?dist} +Version: 2020.04 +Release: 0.1%{?candidate:.%{candidate}}%{?dist} Summary: U-Boot utilities License: GPLv2+ BSD LGPL-2.1+ LGPL-2.0+ URL: http://www.denx.de/wiki/U-Boot @@ -26,9 +26,7 @@ Patch5: rpi-Enable-using-the-DT-provided-by-the-Raspberry-Pi.patch Patch6: dragonboard-fixes.patch Patch7: ARM-tegra-Add-NVIDIA-Jetson-Nano.patch Patch8: arm-tegra-defaine-fdtfile-for-all-devices.patch -Patch9: zynqmp-Add-support-for-u-boot.itb-generation-with-ATF.patch -Patch10: zynqmp-Do-not-assing-MIO34-that-early-on-zcu100.patch -Patch11: wandboard-Fix-the-DM_PMIC-conversion.patch +Patch12: Ethernet-support-for-Raspberry-Pi-4.patch BuildRequires: bc BuildRequires: dtc @@ -250,6 +248,9 @@ cp -p board/warp7/README builds/docs/README.warp7 %endif %changelog +* Wed Jan 29 2020 Peter Robinson 2020.04-0.1-rc1 +- 2020.04 RC1 + * Tue Jan 7 2020 Peter Robinson 2020.01-1 - 2020.01 diff --git a/wandboard-Fix-the-DM_PMIC-conversion.patch b/wandboard-Fix-the-DM_PMIC-conversion.patch deleted file mode 100644 index fba0474..0000000 --- a/wandboard-Fix-the-DM_PMIC-conversion.patch +++ /dev/null @@ -1,298 +0,0 @@ -From patchwork Tue Dec 10 09:32:59 2019 -Content-Type: text/plain; charset="utf-8" -MIME-Version: 1.0 -Content-Transfer-Encoding: 7bit -X-Patchwork-Submitter: Fabio Estevam -X-Patchwork-Id: 1206991 -X-Patchwork-Delegate: sbabic@denx.de -Return-Path: -X-Original-To: incoming@patchwork.ozlabs.org -Delivered-To: patchwork-incoming@bilbo.ozlabs.org -Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) - smtp.mailfrom=lists.denx.de - (client-ip=2a01:238:438b:c500:173d:9f52:ddab:ee01; - helo=phobos.denx.de; - envelope-from=u-boot-bounces@lists.denx.de; - receiver=) -Authentication-Results: ozlabs.org; - dmarc=fail (p=none dis=none) header.from=gmail.com -Authentication-Results: ozlabs.org; - dkim=fail reason="signature verification failed" (2048-bit key; - unprotected) header.d=gmail.com header.i=@gmail.com - header.b="cvQwwEgd"; dkim-atps=neutral -Received: from phobos.denx.de (phobos.denx.de - [IPv6:2a01:238:438b:c500:173d:9f52:ddab:ee01]) - (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) - key-exchange X25519 server-signature RSA-PSS (4096 bits) - server-digest SHA256) (No client certificate requested) - by ozlabs.org (Postfix) with ESMTPS id 47XFH65yXWz9sR0 - for ; - Tue, 10 Dec 2019 20:33:22 +1100 (AEDT) -Received: from phobos.denx.de (localhost [IPv6:::1]) - by phobos.denx.de (Postfix) with ESMTP id D7B2E815E1; - Tue, 10 Dec 2019 10:33:15 +0100 (CET) -Authentication-Results: phobos.denx.de; - dmarc=fail (p=none dis=none) header.from=gmail.com -Authentication-Results: phobos.denx.de; - spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de -Authentication-Results: phobos.denx.de; - dkim=fail reason="signature verification failed" (2048-bit key; - unprotected) header.d=gmail.com header.i=@gmail.com - header.b="cvQwwEgd"; dkim-atps=neutral -Received: by phobos.denx.de (Postfix, from userid 109) - id 4752C8074A; Tue, 10 Dec 2019 10:33:14 +0100 (CET) -X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on phobos.denx.de -X-Spam-Level: -X-Spam-Status: No, score=-0.1 required=5.0 tests=DKIM_SIGNED,DKIM_VALID, - DKIM_VALID_AU,FREEMAIL_FROM,SPF_HELO_NONE autolearn=ham - autolearn_force=no version=3.4.2 -Received: from mail-vs1-xe44.google.com (mail-vs1-xe44.google.com - [IPv6:2607:f8b0:4864:20::e44]) - (using TLSv1.3 with cipher TLS_AES_128_GCM_SHA256 (128/128 bits)) - (No client certificate requested) - by phobos.denx.de (Postfix) with ESMTPS id 937E28074A - for ; Tue, 10 Dec 2019 10:33:11 +0100 (CET) -Authentication-Results: phobos.denx.de; - dmarc=pass (p=none dis=none) header.from=gmail.com -Authentication-Results: phobos.denx.de; - spf=pass smtp.mailfrom=festevam@gmail.com -Received: by mail-vs1-xe44.google.com with SMTP id x4so12516773vsx.10 - for ; Tue, 10 Dec 2019 01:33:11 -0800 (PST) -DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; - h=from:to:cc:subject:date:message-id; - bh=mpTV9oyDpdcbibHXq3CRpa1/KhlaRlmW+uWx2mbu2C0=; - b=cvQwwEgdb0cUfPdifzUOq/iEL9XwLazg63lgVN27j8pQhuqD4CnxE7P4E1kAmm4GrL - ioli46uO/Zn7MutAHpZh141SUmltl5XyJkK/xfwHSYwTpWLiwGzieEfLxpOTOCmJDolI - W5wZbT1C04618Y3UCGlEZ9L7ETfaYqT7cOEjUBpSsArGNViCrIToVeVW+z8oTAsT51XE - CrVdNSDOXV3jRQzBEC1l+eZD5hAXFVPHY6sErfv+y8b94/la+HA5yaRmlVg30fosnxxq - BcbV0kO/8Kl1VgIOnxr4pVy+NsG8sFJ5zjQgsaGGFVwL9xx1Z8my0q0JlKFOs63K8GD+ - 1Yuw== -X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; - d=1e100.net; s=20161025; - h=x-gm-message-state:from:to:cc:subject:date:message-id; - bh=mpTV9oyDpdcbibHXq3CRpa1/KhlaRlmW+uWx2mbu2C0=; - b=M1zPCQgH6lX7Ng689GJcnZQWOuEhk0MKOHRBbE702r7lq579f9ACwlpW4sAmLS/gqs - BTRpErFG2yHcK95YAJOjx+QeT5weQJShAp1r7sLKIqBoxxi9oYzMYt+vO4oYENcsOdoL - fxbXhR9mT2GVpedrncf3P4Js8xMU/Og14n63mRSCzjI0z9kmFpjlIbhFEAoXIeYYrUTO - JF/fjPHdOAyuFSG2r0JSuyh2ewrHBhqmpdc09iJalFiYzd2fMWiK4z4FDopwmSzW2+LQ - qFXPcppjuUWNSFf/WVdxN4a1pXzmCvlyo+wUVCinBll219AvEmP5UQwfGVfv4g2qOGJ2 - +uaw== -X-Gm-Message-State: APjAAAWEqUYJ4RzYMv6viS7n184rIuw6EoDe0lHixKjw8y7hOeos8Jwk - j+sKufWbN2myuE6gHKRWXTM= -X-Google-Smtp-Source: APXvYqxvZbxUyC1WljEkppgxN57/lcAdqYBto/WMiBhA6sqkc/bvP209jENc0g48Nw4H6RjWmlXc8w== -X-Received: by 2002:a67:ff85:: with SMTP id v5mr23836021vsq.42.1575970390329; - Tue, 10 Dec 2019 01:33:10 -0800 (PST) -Received: from fabio-Latitude-E5450.nxp.com ([2804:14c:482:5bb::1]) - by smtp.gmail.com with ESMTPSA id - k192sm1820253vke.40.2019.12.10.01.33.07 - (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); - Tue, 10 Dec 2019 01:33:09 -0800 (PST) -From: Fabio Estevam -To: sbabic@denx.de -Subject: [PATCH v3 1/2] wandboard: Fix the DM_PMIC conversion -Date: Tue, 10 Dec 2019 06:32:59 -0300 -Message-Id: <20191210093300.31692-1-festevam@gmail.com> -X-Mailer: git-send-email 2.17.1 -X-BeenThere: u-boot@lists.denx.de -X-Mailman-Version: 2.1.26 -Precedence: list -List-Id: U-Boot discussion -List-Unsubscribe: , - -List-Archive: -List-Post: -List-Help: -List-Subscribe: , - -Cc: u-boot@lists.denx.de, uboot-imx@nxp.com, trini@konsulko.com -Errors-To: u-boot-bounces@lists.denx.de -Sender: "U-Boot" -X-Virus-Scanned: clamav-milter 0.101.4 at phobos.denx.de -X-Virus-Status: Clean - -Commit ec837c82d709 ("imx6: wandboard: convert to DM_PMIC") -caused the following pmic_get() error: - -CPU: Freescale i.MX6QP rev1.0 at 792 MHz -Reset cause: POR -DRAM: 2 GiB -PMIC: pmic_get() ret -19 -... - -and since the PMIC presence is used to determine the board D1 revision, -the following error is seen when booting a board rev D1: - -WARNING: Could not determine dtb to use - -and the kernel does not boot at all. - -Fix the regression by passing "pfuze100@8" as the correct parameter -to the pmic_get() function in the DM case. - -Fixes: ec837c82d709 ("imx6: wandboard: convert to DM_PMIC") -Signed-off-by: Fabio Estevam ---- -Changes since v2: -- None - - board/wandboard/wandboard.c | 2 +- - 1 file changed, 1 insertion(+), 1 deletion(-) - -diff --git a/board/wandboard/wandboard.c b/board/wandboard/wandboard.c -index 6c1e4ef27d..b2f961a7f0 100644 ---- a/board/wandboard/wandboard.c -+++ b/board/wandboard/wandboard.c -@@ -363,7 +363,7 @@ int power_init_board(void) - - puts("PMIC: "); - -- ret = pmic_get("pfuze100", &dev); -+ ret = pmic_get("pfuze100@8", &dev); - if (ret < 0) { - printf("pmic_get() ret %d\n", ret); - return 0; - -From patchwork Tue Dec 10 09:33:00 2019 -Content-Type: text/plain; charset="utf-8" -MIME-Version: 1.0 -Content-Transfer-Encoding: 7bit -X-Patchwork-Submitter: Fabio Estevam -X-Patchwork-Id: 1206992 -X-Patchwork-Delegate: sbabic@denx.de -Return-Path: -X-Original-To: incoming@patchwork.ozlabs.org -Delivered-To: patchwork-incoming@bilbo.ozlabs.org -Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) - smtp.mailfrom=lists.denx.de - (client-ip=2a01:238:438b:c500:173d:9f52:ddab:ee01; - helo=phobos.denx.de; - envelope-from=u-boot-bounces@lists.denx.de; - receiver=) -Authentication-Results: ozlabs.org; - dmarc=fail (p=none dis=none) header.from=gmail.com -Authentication-Results: ozlabs.org; - dkim=fail reason="signature verification failed" (2048-bit key; - unprotected) header.d=gmail.com header.i=@gmail.com - header.b="YrPr8jxV"; dkim-atps=neutral -Received: from phobos.denx.de (phobos.denx.de - [IPv6:2a01:238:438b:c500:173d:9f52:ddab:ee01]) - (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) - key-exchange X25519 server-signature RSA-PSS (4096 bits)) - (No client certificate requested) - by ozlabs.org (Postfix) with ESMTPS id 47XFHB3qzgz9sR0 - for ; - Tue, 10 Dec 2019 20:33:26 +1100 (AEDT) -Received: from phobos.denx.de (localhost [IPv6:::1]) - by phobos.denx.de (Postfix) with ESMTP id BC5CA81644; - Tue, 10 Dec 2019 10:33:19 +0100 (CET) -Authentication-Results: phobos.denx.de; - dmarc=fail (p=none dis=none) header.from=gmail.com -Authentication-Results: phobos.denx.de; - spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de -Authentication-Results: phobos.denx.de; - dkim=fail reason="signature verification failed" (2048-bit key; - unprotected) header.d=gmail.com header.i=@gmail.com - header.b="YrPr8jxV"; dkim-atps=neutral -Received: by phobos.denx.de (Postfix, from userid 109) - id C408A8163A; Tue, 10 Dec 2019 10:33:17 +0100 (CET) -X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on phobos.denx.de -X-Spam-Level: -X-Spam-Status: No, score=-0.1 required=5.0 tests=DKIM_SIGNED,DKIM_VALID, - DKIM_VALID_AU,FREEMAIL_FROM,SPF_HELO_NONE autolearn=ham - autolearn_force=no version=3.4.2 -Received: from mail-vs1-xe43.google.com (mail-vs1-xe43.google.com - [IPv6:2607:f8b0:4864:20::e43]) - (using TLSv1.3 with cipher TLS_AES_128_GCM_SHA256 (128/128 bits)) - (No client certificate requested) - by phobos.denx.de (Postfix) with ESMTPS id E87DF8074A - for ; Tue, 10 Dec 2019 10:33:14 +0100 (CET) -Authentication-Results: phobos.denx.de; - dmarc=pass (p=none dis=none) header.from=gmail.com -Authentication-Results: phobos.denx.de; - spf=pass smtp.mailfrom=festevam@gmail.com -Received: by mail-vs1-xe43.google.com with SMTP id p21so12536232vsq.6 - for ; Tue, 10 Dec 2019 01:33:14 -0800 (PST) -DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; - h=from:to:cc:subject:date:message-id:in-reply-to:references; - bh=fFiExeVHQEMtju9XljEZntJtMc/qzkpL8xAT5PDzV60=; - b=YrPr8jxVxXbzcZcfasnoGn8a6WeAPvhbfZ0+ZEqRpLUxnVpM4LQsPdTrMiyHGUO6TJ - 7jdurrMAwK0N4MygABLhGjjU4DExjGT3XpwTf1cqWdK7FLmO7sjWeOIrV+gAvUqqPZgJ - 7AAoPDQx3eV3owS87svBd7wDi1M8nJGyuNDh/HSyBFHiwSyV142Tdq17Fjp9qFX1LhMc - TjGHMtLNLH2XhClWrKZz+10pQRN0kzdI2Xxai73zFprKsp3MfDww35YX8J9LY9F5/s43 - mKHgO4EECxOhts/c6xnDIqjl6O9JIajFH9G9azxjZq6/yjbgowe4LEQrlas9y0JKA3s/ - GK/g== -X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; - d=1e100.net; s=20161025; - h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to - :references; - bh=fFiExeVHQEMtju9XljEZntJtMc/qzkpL8xAT5PDzV60=; - b=s0vxHMIufABFR1mGa7wa9NVYGHlj3GR65sLCrAX28gyg6ztQ4dlECQ0CTO3HHnoVoo - v6fosk95hoaXI75Bj08HKgCns6k+nvnrIfV/e22t8vPFtQz0CuJy7B9ti1CHMc1OXK79 - pMvHWoFRXele0KgexW0JS5XomOBmcd7eE25j9awGzpeRS5LFOvoGhSXb1ktBPga3EYBp - qJ5lSA/TWesX7MH3DhzHP5g4GXvtsMTSPPJ8DFI+rvnMBIcDpbeLsGkZAmxFIZCiI33e - ieKIJyCdPEgBA+hz7RK3Hi7sQWdKgZILDsVuT9mUQlHgQWsohpnuCvZYdCOAFIHAI/RK - lbjg== -X-Gm-Message-State: APjAAAV3AN3eAp5IKWxxBay0ZTJknz5Mc1WZ+95+Xsnj5JpxngNPrUWg - El3hLQb+aMhCtHfAe1nVWSc= -X-Google-Smtp-Source: APXvYqzYkDB7SE8lunA3rRIRTpj90F7DGCbF2B95IgKftA+fSdoxrEfuAazokN+CbP57SXacBYGCSA== -X-Received: by 2002:a67:f84e:: with SMTP id - b14mr23964564vsp.126.1575970393704; - Tue, 10 Dec 2019 01:33:13 -0800 (PST) -Received: from fabio-Latitude-E5450.nxp.com ([2804:14c:482:5bb::1]) - by smtp.gmail.com with ESMTPSA id - k192sm1820253vke.40.2019.12.10.01.33.10 - (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); - Tue, 10 Dec 2019 01:33:13 -0800 (PST) -From: Fabio Estevam -To: sbabic@denx.de -Subject: [PATCH v3 2/2] wandboard: Remove repeated PMIC string -Date: Tue, 10 Dec 2019 06:33:00 -0300 -Message-Id: <20191210093300.31692-2-festevam@gmail.com> -X-Mailer: git-send-email 2.17.1 -In-Reply-To: <20191210093300.31692-1-festevam@gmail.com> -References: <20191210093300.31692-1-festevam@gmail.com> -X-BeenThere: u-boot@lists.denx.de -X-Mailman-Version: 2.1.26 -Precedence: list -List-Id: U-Boot discussion -List-Unsubscribe: , - -List-Archive: -List-Post: -List-Help: -List-Subscribe: , - -Cc: u-boot@lists.denx.de, uboot-imx@nxp.com, trini@konsulko.com -Errors-To: u-boot-bounces@lists.denx.de -Sender: "U-Boot" -X-Virus-Scanned: clamav-milter 0.101.4 at phobos.denx.de -X-Virus-Status: Clean - -After the conversion to DM_PMIC the following output is seen: - -PMIC: PMIC: PFUZE100 ID=0x10 - -Remove the unnecessary PMIC string from the board file to -avoid the repetead string. - -Signed-off-by: Fabio Estevam ---- -Changes since v2: -- None - - board/wandboard/wandboard.c | 2 -- - 1 file changed, 2 deletions(-) - -diff --git a/board/wandboard/wandboard.c b/board/wandboard/wandboard.c -index 7209cc8211..e386ad2cc1 100644 ---- a/board/wandboard/wandboard.c -+++ b/board/wandboard/wandboard.c -@@ -361,8 +361,6 @@ int power_init_board(void) - struct udevice *dev; - int reg, ret; - -- puts("PMIC: "); -- - ret = pmic_get("pfuze100@8", &dev); - if (ret < 0) { - printf("pmic_get() ret %d\n", ret); diff --git a/zynqmp-Add-support-for-u-boot.itb-generation-with-ATF.patch b/zynqmp-Add-support-for-u-boot.itb-generation-with-ATF.patch deleted file mode 100644 index 98039d4..0000000 --- a/zynqmp-Add-support-for-u-boot.itb-generation-with-ATF.patch +++ /dev/null @@ -1,286 +0,0 @@ -From patchwork Thu Dec 5 08:46:57 2019 -Content-Type: text/plain; charset="utf-8" -MIME-Version: 1.0 -Content-Transfer-Encoding: 7bit -X-Patchwork-Submitter: Michal Simek -X-Patchwork-Id: 1204536 -Return-Path: -X-Original-To: incoming@patchwork.ozlabs.org -Delivered-To: patchwork-incoming@bilbo.ozlabs.org -Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) - smtp.mailfrom=lists.denx.de (client-ip=85.214.62.61; - helo=phobos.denx.de; - envelope-from=u-boot-bounces@lists.denx.de; - receiver=) -Authentication-Results: ozlabs.org; - dmarc=none (p=none dis=none) header.from=xilinx.com -Authentication-Results: ozlabs.org; - dkim=fail reason="signature verification failed" (2048-bit key; - unprotected) header.d=monstr-eu.20150623.gappssmtp.com - header.i=@monstr-eu.20150623.gappssmtp.com - header.b="F7yFmrcr"; dkim-atps=neutral -Received: from phobos.denx.de (phobos.denx.de [85.214.62.61]) - (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) - key-exchange X25519 server-signature RSA-PSS (4096 bits)) - (No client certificate requested) - by ozlabs.org (Postfix) with ESMTPS id 47T8mj1rxFz9sPT - for ; - Thu, 5 Dec 2019 19:59:49 +1100 (AEDT) -Received: by phobos.denx.de (Postfix, from userid 109) - id DC15F81730; Thu, 5 Dec 2019 09:59:15 +0100 (CET) -X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on mail.denx.de -X-Spam-Level: -X-Spam-Status: No, score=-0.8 required=5.0 tests=DKIM_INVALID,DKIM_SIGNED, - MAILING_LIST_MULTI,RCVD_IN_MSPIKE_H2,SPF_HELO_NONE,SPF_PASS, - URIBL_BLOCKED autolearn=unavailable autolearn_force=no version=3.4.2 -Received: from phobos.denx.de (localhost [IPv6:::1]) - by phobos.denx.de (Postfix) with ESMTP id AD3C281702; - Thu, 5 Dec 2019 09:47:37 +0100 (CET) -Authentication-Results: mail.denx.de; - dmarc=none (p=none dis=none) header.from=xilinx.com -Authentication-Results: mail.denx.de; - spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de -Authentication-Results: mail.denx.de; - dkim=fail reason="signature verification failed" (2048-bit key; - unprotected) header.d=monstr-eu.20150623.gappssmtp.com - header.i=@monstr-eu.20150623.gappssmtp.com - header.b="F7yFmrcr"; dkim-atps=neutral -Received: by phobos.denx.de (Postfix, from userid 109) - id EFEE0816D6; Thu, 5 Dec 2019 09:47:35 +0100 (CET) -Received: from mail-wm1-f68.google.com (mail-wm1-f68.google.com - [209.85.128.68]) - (using TLSv1.3 with cipher TLS_AES_128_GCM_SHA256 (128/128 bits)) - (No client certificate requested) - by phobos.denx.de (Postfix) with ESMTPS id 13F3481702 - for ; Thu, 5 Dec 2019 09:47:05 +0100 (CET) -Authentication-Results: mail.denx.de; - dmarc=none (p=none dis=none) header.from=xilinx.com -Authentication-Results: mail.denx.de; spf=none smtp.mailfrom=monstr@monstr.eu -Received: by mail-wm1-f68.google.com with SMTP id p9so2672948wmc.2 - for ; Thu, 05 Dec 2019 00:47:05 -0800 (PST) -DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; - d=monstr-eu.20150623.gappssmtp.com; s=20150623; - h=sender:from:to:cc:subject:date:message-id:mime-version - :content-transfer-encoding; - bh=zKC9njDJvxTe218gXlGDt/iSWcQwlzyEn/MHFrB1GUk=; - b=F7yFmrcrJYGseyeuyhzqQujaDM8FvSqw3O1Pfmlh+SK6+tZ7BLQ6+XIDpi5DQAIzHs - 9Oe0co+RlaN+ypuEKw69o+zmaAHwbQoupL2LBoVJkAcVDseWpjatJtapzpyfUVqhfUaw - XRFXuVzSyRx64eELCzcR7Hl5ioK9Q7Y/tjvV07IHac4Uc8N0N/LS66Rj/49Reo4DGIhT - ThR6PDhriY0ANIDa8KnxQpQBiMuSuC4lTz3BuDMM/7LbS4r7Yy89EC+4wwXE4ZzXYAsO - Kykj/rvg7d+BW8O1g3bxbDQVy/5IVDqslArlUH6xZpNOKDxwfLAvkAIvQiV/YJlNC1hQ - f+OQ== -X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; - d=1e100.net; s=20161025; - h=x-gm-message-state:sender:from:to:cc:subject:date:message-id - :mime-version:content-transfer-encoding; - bh=zKC9njDJvxTe218gXlGDt/iSWcQwlzyEn/MHFrB1GUk=; - b=W2HsrghOni524RBbGxTnERtM2TNSUjmMhNi98cPFIy39d+LzzF1vxLBvF16jtovKsF - DVYBg8lVrIEeaD1/XjcNmN7mk4LdWuwBnhUpAEVSQ3ccrxqMGSAud4vaduMo2czlBNWq - m85KtYJctifHGMThcX9fwwr3+VmZIZ46ZUyXVuGSEqr7lZK/Nrnn7dH+v5hfYR60KhtI - 1yxf6vkuoC+Z89WfQGiM2JMCnlmVy7ety6+s6b1PYRyf1FQbt4MmZ4ywRAfSuAtY4NUD - XmDp+8lDrpa08LjlJxBbKqeKS+Eeh2pKDkOwInuxWiLDOgZ7fAT3LG5Uq+1GDGbNfKs9 - xtlA== -X-Gm-Message-State: APjAAAUFPoTdro6+fDkKW4xky4+l2r/NtdDEuEaU72qNICk1Wlu+706B - tYlmosjzcX01d6VDfvz1eDIGZy20ca8= -X-Google-Smtp-Source: APXvYqzdmCVgU6CmN6exvPPKe9MZLPRPrinxyPtHvAnw7yyB3wd7uJyGYyFkZXVKepilUtZDhUtjHg== -X-Received: by 2002:a7b:cc0c:: with SMTP id f12mr3835348wmh.5.1575535624294; - Thu, 05 Dec 2019 00:47:04 -0800 (PST) -Received: from localhost (nat-35.starnet.cz. [178.255.168.35]) - by smtp.gmail.com with ESMTPSA id - a7sm11805025wrr.50.2019.12.05.00.47.03 - (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); - Thu, 05 Dec 2019 00:47:03 -0800 (PST) -From: Michal Simek -To: u-boot@lists.denx.de, - git@xilinx.com, - pbrobinson@gmail.com -Subject: [PATCH v2] arm64: zynqmp: Add support for u-boot.itb generation with - ATF -Date: Thu, 5 Dec 2019 09:46:57 +0100 -Message-Id: <311b20ae349e6a93714c227df5907667d1cb9463.1575535613.git.michal.simek@xilinx.com> -X-Mailer: git-send-email 2.24.0 -MIME-Version: 1.0 -X-BeenThere: u-boot@lists.denx.de -X-Mailman-Version: 2.1.26 -Precedence: list -List-Id: U-Boot discussion -List-Unsubscribe: , - -List-Archive: -List-Post: -List-Help: -List-Subscribe: , - -Cc: Marek Vasut , Stefan Roese -Errors-To: u-boot-bounces@lists.denx.de -Sender: "U-Boot" -X-Virus-Scanned: clamav-milter 0.101.4 at mail.denx.de -X-Virus-Status: Clean - -Follow i.MX, Sunxi, RISC-V and Rockchip to generate u-boot.itb which -includes U-Boot proper, ATF and DTBs in FIT format. ZynqMP supports FIT for -quite a long time but with using out of tree solution. The patch is filling -this gap. - -Tested on zcu102, zcu104 and zcu100/Ultra96. - -zcu100/Ultra96 v2.2 ATF build by: -make DEBUG=0 ZYNQMP_CONSOLE=cadence1 RESET_TO_BL31=1 PLAT=zynqmp bl31 - -Signed-off-by: Michal Simek ---- - -Changes in v2: -- Exchange u-boot/atf in config section -- Use default ATF baseaddr from mainline -- Update commit message - - Kconfig | 3 +- - arch/arm/mach-zynqmp/mkimage_fit_atf.sh | 99 +++++++++++++++++++++++++ - include/configs/xilinx_zynqmp.h | 6 +- - 3 files changed, 106 insertions(+), 2 deletions(-) - create mode 100755 arch/arm/mach-zynqmp/mkimage_fit_atf.sh - -diff --git a/Kconfig b/Kconfig -index e22417ec4471..7efafffec0a4 100644 ---- a/Kconfig -+++ b/Kconfig -@@ -253,7 +253,7 @@ config BUILD_TARGET - default "u-boot-spl.kwb" if ARCH_MVEBU && SPL - default "u-boot-elf.srec" if RCAR_GEN3 - default "u-boot.itb" if SPL_LOAD_FIT && (ARCH_ROCKCHIP || \ -- ARCH_SUNXI || RISCV) -+ ARCH_SUNXI || RISCV || ARCH_ZYNQMP) - default "u-boot.kwb" if KIRKWOOD - default "u-boot-with-spl.bin" if ARCH_AT91 && SPL_NAND_SUPPORT - default "u-boot-with-spl.imx" if ARCH_MX6 && SPL -@@ -481,6 +481,7 @@ config SPL_FIT_GENERATOR - depends on SPL_FIT - default "board/sunxi/mksunxi_fit_atf.sh" if SPL_LOAD_FIT && ARCH_SUNXI - default "arch/arm/mach-rockchip/make_fit_atf.py" if SPL_LOAD_FIT && ARCH_ROCKCHIP -+ default "arch/arm/mach-zynqmp/mkimage_fit_atf.sh" if SPL_LOAD_FIT && ARCH_ZYNQMP - default "arch/riscv/lib/mkimage_fit_opensbi.sh" if SPL_LOAD_FIT && RISCV - help - Specifies a (platform specific) script file to generate the FIT -diff --git a/arch/arm/mach-zynqmp/mkimage_fit_atf.sh b/arch/arm/mach-zynqmp/mkimage_fit_atf.sh -new file mode 100755 -index 000000000000..c50aba45ca5c ---- /dev/null -+++ b/arch/arm/mach-zynqmp/mkimage_fit_atf.sh -@@ -0,0 +1,99 @@ -+#!/bin/sh -+# SPDX-License-Identifier: GPL-2.0+ -+# -+# script to generate FIT image source for Xilinx ZynqMP boards with -+# ARM Trusted Firmware and multiple device trees (given on the command line) -+# -+# usage: $0 [ [&2 -+else -+ echo "$BL31 size: " >&2 -+ ls -lct $BL31 | awk '{print $5}' >&2 -+fi -+ -+ -+ -+cat << __HEADER_EOF -+/dts-v1/; -+ -+/ { -+ description = "Configuration to load ATF before U-Boot"; -+ -+ images { -+ uboot { -+ description = "U-Boot (64-bit)"; -+ data = /incbin/("$BL33"); -+ type = "firmware"; -+ os = "u-boot"; -+ arch = "arm64"; -+ compression = "none"; -+ load = <$BL33_LOAD_ADDR>; -+ hash { -+ algo = "md5"; -+ }; -+ }; -+ atf { -+ description = "ARM Trusted Firmware"; -+ data = /incbin/("$BL31"); -+ type = "firmware"; -+ os = "arm-trusted-firmware"; -+ arch = "arm64"; -+ compression = "none"; -+ load = <$ATF_LOAD_ADDR>; -+ entry = <$ATF_LOAD_ADDR>; -+ hash { -+ algo = "md5"; -+ }; -+ }; -+__HEADER_EOF -+ -+cnt=1 -+for dtname in $* -+do -+ cat << __FDT_IMAGE_EOF -+ fdt_$cnt { -+ description = "$(basename $dtname .dtb)"; -+ data = /incbin/("$dtname"); -+ type = "flat_dt"; -+ arch = "arm64"; -+ compression = "none"; -+ hash { -+ algo = "md5"; -+ }; -+ }; -+__FDT_IMAGE_EOF -+cnt=$((cnt+1)) -+done -+ -+cat << __CONF_HEADER_EOF -+ }; -+ configurations { -+ default = "config_1"; -+ -+__CONF_HEADER_EOF -+ -+cnt=1 -+for dtname in $* -+do -+cat << __CONF_SECTION1_EOF -+ config_$cnt { -+ description = "$(basename $dtname .dtb)"; -+ firmware = "atf"; -+ loadables = "uboot"; -+ fdt = "fdt_$cnt"; -+ }; -+__CONF_SECTION1_EOF -+cnt=$((cnt+1)) -+done -+ -+cat << __ITS_EOF -+ }; -+}; -+__ITS_EOF -diff --git a/include/configs/xilinx_zynqmp.h b/include/configs/xilinx_zynqmp.h -index ee1ceebf1291..e7eb8dbfcb45 100644 ---- a/include/configs/xilinx_zynqmp.h -+++ b/include/configs/xilinx_zynqmp.h -@@ -243,7 +243,11 @@ - # define CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTOR 0 /* unused */ - # define CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTORS 0 /* unused */ - # define CONFIG_SYS_MMCSD_RAW_MODE_KERNEL_SECTOR 0 /* unused */ --# define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img" -+# if defined(CONFIG_SPL_LOAD_FIT) -+# define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.itb" -+# else -+# define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img" -+# endif - #endif - - #if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_DFU) diff --git a/zynqmp-Do-not-assing-MIO34-that-early-on-zcu100.patch b/zynqmp-Do-not-assing-MIO34-that-early-on-zcu100.patch deleted file mode 100644 index 83cc155..0000000 --- a/zynqmp-Do-not-assing-MIO34-that-early-on-zcu100.patch +++ /dev/null @@ -1,199 +0,0 @@ -From patchwork Tue Dec 3 15:33:26 2019 -Content-Type: text/plain; charset="utf-8" -MIME-Version: 1.0 -Content-Transfer-Encoding: 7bit -X-Patchwork-Submitter: Michal Simek -X-Patchwork-Id: 1203761 -Return-Path: -X-Original-To: incoming@patchwork.ozlabs.org -Delivered-To: patchwork-incoming@bilbo.ozlabs.org -Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) - smtp.mailfrom=lists.denx.de (client-ip=85.214.62.61; - helo=phobos.denx.de; - envelope-from=u-boot-bounces@lists.denx.de; - receiver=) -Authentication-Results: ozlabs.org; - dmarc=none (p=none dis=none) header.from=xilinx.com -Authentication-Results: ozlabs.org; - dkim=fail reason="signature verification failed" (2048-bit key; - unprotected) header.d=monstr-eu.20150623.gappssmtp.com - header.i=@monstr-eu.20150623.gappssmtp.com - header.b="xsfGCcKd"; dkim-atps=neutral -Received: from phobos.denx.de (phobos.denx.de [85.214.62.61]) - (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) - key-exchange X25519 server-signature RSA-PSS (4096 bits)) - (No client certificate requested) - by ozlabs.org (Postfix) with ESMTPS id 47S60l4q2Xz9sP6 - for ; - Wed, 4 Dec 2019 02:51:35 +1100 (AEDT) -Received: by phobos.denx.de (Postfix, from userid 109) - id 918E181706; Tue, 3 Dec 2019 16:51:32 +0100 (CET) -X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on mail.denx.de -X-Spam-Level: -X-Spam-Status: No, score=-0.9 required=5.0 tests=DKIM_INVALID,DKIM_SIGNED, - MAILING_LIST_MULTI,RCVD_IN_MSPIKE_H2,SPF_HELO_NONE,SPF_PASS, - URIBL_BLOCKED autolearn=unavailable autolearn_force=no version=3.4.2 -Received: from phobos.denx.de (localhost [IPv6:::1]) - by phobos.denx.de (Postfix) with ESMTP id CFCEB81715; - Tue, 3 Dec 2019 16:34:34 +0100 (CET) -Authentication-Results: mail.denx.de; - dmarc=none (p=none dis=none) header.from=xilinx.com -Authentication-Results: mail.denx.de; - spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de -Authentication-Results: mail.denx.de; - dkim=fail reason="signature verification failed" (2048-bit key; - unprotected) header.d=monstr-eu.20150623.gappssmtp.com - header.i=@monstr-eu.20150623.gappssmtp.com - header.b="xsfGCcKd"; dkim-atps=neutral -Received: by phobos.denx.de (Postfix, from userid 109) - id 71E9081740; Tue, 3 Dec 2019 16:34:33 +0100 (CET) -Received: from mail-wr1-f68.google.com (mail-wr1-f68.google.com - [209.85.221.68]) - (using TLSv1.3 with cipher TLS_AES_128_GCM_SHA256 (128/128 bits)) - (No client certificate requested) - by phobos.denx.de (Postfix) with ESMTPS id 3B4538173D - for ; Tue, 3 Dec 2019 16:33:29 +0100 (CET) -Authentication-Results: mail.denx.de; - dmarc=none (p=none dis=none) header.from=xilinx.com -Authentication-Results: mail.denx.de; spf=none smtp.mailfrom=monstr@monstr.eu -Received: by mail-wr1-f68.google.com with SMTP id y11so4206551wrt.6 - for ; Tue, 03 Dec 2019 07:33:29 -0800 (PST) -DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; - d=monstr-eu.20150623.gappssmtp.com; s=20150623; - h=sender:from:to:subject:date:message-id:mime-version - :content-transfer-encoding; - bh=FY3wavUSlq3LqJpduWDlDfRQ23fa0sS7k2hYmp1W4v4=; - b=xsfGCcKdlKNSq7/5D1KjuXn2SIyh08im6EI3N/tLYCXIe2AMeGGcrFJgXbwKrFcmW5 - cJ3I6vxbLI6lLb9+Y1Qn3I86If7jjs3FMfcwupdbEevBO178wLgaSTVGTkJZx6nLP38s - vyzBYOZ7rDRdARwPKqUaEjNBnjXj6cLSF6vSlcOYsClRq5AOQjtmMjCg5Spnh3vL6C6S - Uw7A4ec8egIepK0I8wWcVKDCrz7BzKzPkMkA8TwrM9MyudwHdyLkSOv/K1drj9r7Bxle - ++0OBo+6nbg4VSJrS3J1BOqSVTru8AQmqlEklfil0A8vfrKUF9BAV0z6yrU6oDOvxmb7 - oBGQ== -X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; - d=1e100.net; s=20161025; - h=x-gm-message-state:sender:from:to:subject:date:message-id - :mime-version:content-transfer-encoding; - bh=FY3wavUSlq3LqJpduWDlDfRQ23fa0sS7k2hYmp1W4v4=; - b=HFOn3PHDfuhrO27I3b9eZtbbFdyMus2JuR88KxfnfeovLmu3VzD2GO2k1v0bbfJrFJ - 3FUyyRMSjuTa8/xEaL/XB7Abmtw35VxtO9rcxq4Xbb5d8zi8tQVrpX63zzQZE1+hGfp1 - Zc0EL6lV2d1U2XkHCiPrSDySeUrfGohM7pNRrdLk0x5+dlsHuaX5r2PGWfnzkIsT9xhj - +hPttUIHpgVXxS6xId42gcSLku1BHdCebYIs8ro3A4Ewu2xCdqyjLBctfWKtCcyvt3AY - 1a/nuS9rgJ3nlFwxKtv340qv/UCp/3W0U3JbYG6Cnc6DvKq72eOPuqnPnyjDa1VQAlZA - q6gA== -X-Gm-Message-State: APjAAAV9fDxe7+YuhbTRQ7FQZxhVH1IaMTTvFGz12nutmEBO1FHu5PVR - RmfQmTY6L3fXPK4lQ+WtrOep+s2H8w4Weg== -X-Google-Smtp-Source: APXvYqxj+/69azSDe/nIwdR/hsgHatKZBL8p8CGOPp1Hku4BlIp/V3L90lAwr5VQJtUY+c5KmukFLQ== -X-Received: by 2002:adf:dc86:: with SMTP id r6mr6287782wrj.68.1575387208549; - Tue, 03 Dec 2019 07:33:28 -0800 (PST) -Received: from localhost (nat-35.starnet.cz. [178.255.168.35]) - by smtp.gmail.com with ESMTPSA id - h17sm4245700wrs.18.2019.12.03.07.33.27 - (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); - Tue, 03 Dec 2019 07:33:27 -0800 (PST) -From: Michal Simek -To: u-boot@lists.denx.de, - git@xilinx.com, - pbrobinson@gmail.com -Subject: [PATCH v2] arm64: zynqmp: Do not assing MIO34 that early on zcu100 -Date: Tue, 3 Dec 2019 16:33:26 +0100 -Message-Id: <175608f69633f3876bebdde1c2f7b9cf54b61716.1575387200.git.michal.simek@xilinx.com> -X-Mailer: git-send-email 2.24.0 -MIME-Version: 1.0 -X-BeenThere: u-boot@lists.denx.de -X-Mailman-Version: 2.1.26 -Precedence: list -List-Id: U-Boot discussion -List-Unsubscribe: , - -List-Archive: -List-Post: -List-Help: -List-Subscribe: , - -Errors-To: u-boot-bounces@lists.denx.de -Sender: "U-Boot" -X-Virus-Scanned: clamav-milter 0.101.4 at mail.denx.de -X-Virus-Status: Clean - -MIO34 is connected to POWER_KILL signal. When MIO configuration is done in -psu_init() and this pin is assigned to PMU but PMU configuration is not -loaded yet. PMU gpio output is high that means board is powered off -immediately. -The patch is fixing this sequence that MIO34 stays assing to ps gpio IP. -PMU config is loaded in SPL and then pin assigned to PMU through -psu_post_config_data(). - -Signed-off-by: Michal Simek ---- - -Changes in v2: -- add missing declaration in header - - arch/arm/mach-zynqmp/include/mach/psu_init_gpl.h | 1 + - arch/arm/mach-zynqmp/psu_spl_init.c | 9 +++++++++ - arch/arm/mach-zynqmp/spl.c | 1 + - board/xilinx/zynqmp/zynqmp-zcu100-revC/psu_init_gpl.c | 7 ++++++- - 4 files changed, 17 insertions(+), 1 deletion(-) - -diff --git a/arch/arm/mach-zynqmp/include/mach/psu_init_gpl.h b/arch/arm/mach-zynqmp/include/mach/psu_init_gpl.h -index 15e54c049387..e37acda2f89e 100644 ---- a/arch/arm/mach-zynqmp/include/mach/psu_init_gpl.h -+++ b/arch/arm/mach-zynqmp/include/mach/psu_init_gpl.h -@@ -21,5 +21,6 @@ void prog_reg(unsigned long addr, unsigned long mask, - unsigned long shift, unsigned long value); - - int psu_init(void); -+unsigned long psu_post_config_data(void); - - #endif /* _PSU_INIT_GPL_H_ */ -diff --git a/arch/arm/mach-zynqmp/psu_spl_init.c b/arch/arm/mach-zynqmp/psu_spl_init.c -index b357de32358c..b6abdfd608ee 100644 ---- a/arch/arm/mach-zynqmp/psu_spl_init.c -+++ b/arch/arm/mach-zynqmp/psu_spl_init.c -@@ -77,3 +77,12 @@ __weak int psu_init(void) - */ - return -1; - } -+ -+__weak unsigned long psu_post_config_data(void) -+{ -+ /* -+ * This function is overridden by the one in -+ * board/xilinx/zynqmp/(platform)/psu_init_gpl.c, if it exists. -+ */ -+ return 0; -+} -diff --git a/arch/arm/mach-zynqmp/spl.c b/arch/arm/mach-zynqmp/spl.c -index 6ba42bb42f62..6551b33f42d0 100644 ---- a/arch/arm/mach-zynqmp/spl.c -+++ b/arch/arm/mach-zynqmp/spl.c -@@ -60,6 +60,7 @@ void spl_board_init(void) - preloader_console_init(); - ps_mode_reset(MODE_RESET); - board_init(); -+ psu_post_config_data(); - } - #endif - -diff --git a/board/xilinx/zynqmp/zynqmp-zcu100-revC/psu_init_gpl.c b/board/xilinx/zynqmp/zynqmp-zcu100-revC/psu_init_gpl.c -index e1fdabaeb9d1..585b3afc218a 100644 ---- a/board/xilinx/zynqmp/zynqmp-zcu100-revC/psu_init_gpl.c -+++ b/board/xilinx/zynqmp/zynqmp-zcu100-revC/psu_init_gpl.c -@@ -409,7 +409,6 @@ static unsigned long psu_mio_init_data(void) - psu_mask_write(0xFF18007C, 0x000000FEU, 0x00000000U); - psu_mask_write(0xFF180080, 0x000000FEU, 0x00000008U); - psu_mask_write(0xFF180084, 0x000000FEU, 0x00000008U); -- psu_mask_write(0xFF180088, 0x000000FEU, 0x00000008U); - psu_mask_write(0xFF18008C, 0x000000FEU, 0x00000000U); - psu_mask_write(0xFF180090, 0x000000FEU, 0x00000000U); - psu_mask_write(0xFF180094, 0x000000FEU, 0x00000000U); -@@ -990,3 +989,9 @@ int psu_init(void) - return 1; - return 0; - } -+ -+unsigned long psu_post_config_data(void) -+{ -+ psu_mask_write(0xFF180088, 0x000000FEU, 0x00000008U); -+ return 0; -+}