|
 |
4d6e2c0 |
From: Andrew Cooper <andrew.cooper3@citrix.com>
|
|
|
4d6e2c0 |
Subject: x86/entry: Introduce EFRAME_* constants
|
|
|
4d6e2c0 |
|
|
|
4d6e2c0 |
restore_all_guest() does a lot of manipulation of the stack after popping the
|
|
|
4d6e2c0 |
GPRs, and uses raw %rsp displacements to do so. Also, almost all entrypaths
|
|
|
4d6e2c0 |
use raw %rsp displacements prior to pushing GPRs.
|
|
|
4d6e2c0 |
|
|
|
4d6e2c0 |
Provide better mnemonics, to aid readability and reduce the chance of errors
|
|
|
4d6e2c0 |
when editing.
|
|
|
4d6e2c0 |
|
|
|
4d6e2c0 |
No functional change. The resulting binary is identical.
|
|
|
4d6e2c0 |
|
|
|
4d6e2c0 |
Signed-off-by: Andrew Cooper <andrew.cooper3@citrix.com>
|
|
|
4d6e2c0 |
Reviewed-by: Jan Beulich <jbeulich@suse.com>
|
|
|
4d6e2c0 |
(cherry picked from commit 37541208f119a9c552c6c6c3246ea61be0d44035)
|
|
|
4d6e2c0 |
|
|
|
4d6e2c0 |
diff --git a/xen/arch/x86/x86_64/asm-offsets.c b/xen/arch/x86/x86_64/asm-offsets.c
|
|
|
4d6e2c0 |
index 57b73a4e6214..2fc4d9130a4d 100644
|
|
|
4d6e2c0 |
--- a/xen/arch/x86/x86_64/asm-offsets.c
|
|
|
4d6e2c0 |
+++ b/xen/arch/x86/x86_64/asm-offsets.c
|
|
|
4d6e2c0 |
@@ -51,6 +51,23 @@ void __dummy__(void)
|
|
|
4d6e2c0 |
OFFSET(UREGS_kernel_sizeof, struct cpu_user_regs, es);
|
|
|
4d6e2c0 |
BLANK();
|
|
|
4d6e2c0 |
|
|
|
4d6e2c0 |
+ /*
|
|
|
4d6e2c0 |
+ * EFRAME_* is for the entry/exit logic where %rsp is pointing at
|
|
|
4d6e2c0 |
+ * UREGS_error_code and GPRs are still/already guest values.
|
|
|
4d6e2c0 |
+ */
|
|
|
4d6e2c0 |
+#define OFFSET_EF(sym, mem) \
|
|
|
4d6e2c0 |
+ DEFINE(sym, offsetof(struct cpu_user_regs, mem) - \
|
|
|
4d6e2c0 |
+ offsetof(struct cpu_user_regs, error_code))
|
|
|
4d6e2c0 |
+
|
|
|
4d6e2c0 |
+ OFFSET_EF(EFRAME_entry_vector, entry_vector);
|
|
|
4d6e2c0 |
+ OFFSET_EF(EFRAME_rip, rip);
|
|
|
4d6e2c0 |
+ OFFSET_EF(EFRAME_cs, cs);
|
|
|
4d6e2c0 |
+ OFFSET_EF(EFRAME_eflags, eflags);
|
|
|
4d6e2c0 |
+ OFFSET_EF(EFRAME_rsp, rsp);
|
|
|
4d6e2c0 |
+ BLANK();
|
|
|
4d6e2c0 |
+
|
|
|
4d6e2c0 |
+#undef OFFSET_EF
|
|
|
4d6e2c0 |
+
|
|
|
4d6e2c0 |
OFFSET(VCPU_processor, struct vcpu, processor);
|
|
|
4d6e2c0 |
OFFSET(VCPU_domain, struct vcpu, domain);
|
|
|
4d6e2c0 |
OFFSET(VCPU_vcpu_info, struct vcpu, vcpu_info_area.map);
|
|
|
4d6e2c0 |
diff --git a/xen/arch/x86/x86_64/compat/entry.S b/xen/arch/x86/x86_64/compat/entry.S
|
|
|
4d6e2c0 |
index fcc3a721f147..cb473f08eebd 100644
|
|
|
4d6e2c0 |
--- a/xen/arch/x86/x86_64/compat/entry.S
|
|
|
4d6e2c0 |
+++ b/xen/arch/x86/x86_64/compat/entry.S
|
|
|
4d6e2c0 |
@@ -15,7 +15,7 @@ ENTRY(entry_int82)
|
|
|
4d6e2c0 |
ENDBR64
|
|
|
4d6e2c0 |
ALTERNATIVE "", clac, X86_FEATURE_XEN_SMAP
|
|
|
4d6e2c0 |
pushq $0
|
|
|
4d6e2c0 |
- movl $HYPERCALL_VECTOR, 4(%rsp)
|
|
|
4d6e2c0 |
+ movl $HYPERCALL_VECTOR, EFRAME_entry_vector(%rsp)
|
|
|
4d6e2c0 |
SAVE_ALL compat=1 /* DPL1 gate, restricted to 32bit PV guests only. */
|
|
|
4d6e2c0 |
|
|
|
4d6e2c0 |
SPEC_CTRL_ENTRY_FROM_PV /* Req: %rsp=regs/cpuinfo, %rdx=0, Clob: acd */
|
|
|
4d6e2c0 |
diff --git a/xen/arch/x86/x86_64/entry.S b/xen/arch/x86/x86_64/entry.S
|
|
|
4d6e2c0 |
index 9a7b129aa7e4..968da9d727b1 100644
|
|
|
4d6e2c0 |
--- a/xen/arch/x86/x86_64/entry.S
|
|
|
4d6e2c0 |
+++ b/xen/arch/x86/x86_64/entry.S
|
|
|
4d6e2c0 |
@@ -190,15 +190,15 @@ restore_all_guest:
|
|
|
4d6e2c0 |
SPEC_CTRL_EXIT_TO_PV /* Req: a=spec_ctrl %rsp=regs/cpuinfo, Clob: cd */
|
|
|
4d6e2c0 |
|
|
|
4d6e2c0 |
RESTORE_ALL
|
|
|
4d6e2c0 |
- testw $TRAP_syscall,4(%rsp)
|
|
|
4d6e2c0 |
+ testw $TRAP_syscall, EFRAME_entry_vector(%rsp)
|
|
|
4d6e2c0 |
jz iret_exit_to_guest
|
|
|
4d6e2c0 |
|
|
|
4d6e2c0 |
- movq 24(%rsp),%r11 # RFLAGS
|
|
|
4d6e2c0 |
+ mov EFRAME_eflags(%rsp), %r11
|
|
|
4d6e2c0 |
andq $~(X86_EFLAGS_IOPL | X86_EFLAGS_VM), %r11
|
|
|
4d6e2c0 |
orq $X86_EFLAGS_IF,%r11
|
|
|
4d6e2c0 |
|
|
|
4d6e2c0 |
/* Don't use SYSRET path if the return address is not canonical. */
|
|
|
4d6e2c0 |
- movq 8(%rsp),%rcx
|
|
|
4d6e2c0 |
+ mov EFRAME_rip(%rsp), %rcx
|
|
|
4d6e2c0 |
sarq $47,%rcx
|
|
|
4d6e2c0 |
incl %ecx
|
|
|
4d6e2c0 |
cmpl $1,%ecx
|
|
|
4d6e2c0 |
@@ -213,20 +213,20 @@ restore_all_guest:
|
|
|
4d6e2c0 |
ALTERNATIVE "", rag_clrssbsy, X86_FEATURE_XEN_SHSTK
|
|
|
4d6e2c0 |
#endif
|
|
|
4d6e2c0 |
|
|
|
4d6e2c0 |
- movq 8(%rsp), %rcx # RIP
|
|
|
4d6e2c0 |
- cmpw $FLAT_USER_CS32,16(%rsp)# CS
|
|
|
4d6e2c0 |
- movq 32(%rsp),%rsp # RSP
|
|
|
4d6e2c0 |
+ mov EFRAME_rip(%rsp), %rcx
|
|
|
4d6e2c0 |
+ cmpw $FLAT_USER_CS32, EFRAME_cs(%rsp)
|
|
|
4d6e2c0 |
+ mov EFRAME_rsp(%rsp), %rsp
|
|
|
4d6e2c0 |
je 1f
|
|
|
4d6e2c0 |
sysretq
|
|
|
4d6e2c0 |
1: sysretl
|
|
|
4d6e2c0 |
|
|
|
4d6e2c0 |
ALIGN
|
|
|
4d6e2c0 |
.Lrestore_rcx_iret_exit_to_guest:
|
|
|
4d6e2c0 |
- movq 8(%rsp), %rcx # RIP
|
|
|
4d6e2c0 |
+ mov EFRAME_rip(%rsp), %rcx
|
|
|
4d6e2c0 |
/* No special register assumptions. */
|
|
|
4d6e2c0 |
iret_exit_to_guest:
|
|
|
4d6e2c0 |
- andl $~(X86_EFLAGS_IOPL | X86_EFLAGS_VM), 24(%rsp)
|
|
|
4d6e2c0 |
- orl $X86_EFLAGS_IF,24(%rsp)
|
|
|
4d6e2c0 |
+ andl $~(X86_EFLAGS_IOPL | X86_EFLAGS_VM), EFRAME_eflags(%rsp)
|
|
|
4d6e2c0 |
+ orl $X86_EFLAGS_IF, EFRAME_eflags(%rsp)
|
|
|
4d6e2c0 |
addq $8,%rsp
|
|
|
4d6e2c0 |
.Lft0: iretq
|
|
|
4d6e2c0 |
_ASM_PRE_EXTABLE(.Lft0, handle_exception)
|
|
|
4d6e2c0 |
@@ -257,7 +257,7 @@ ENTRY(lstar_enter)
|
|
|
4d6e2c0 |
pushq $FLAT_KERNEL_CS64
|
|
|
4d6e2c0 |
pushq %rcx
|
|
|
4d6e2c0 |
pushq $0
|
|
|
4d6e2c0 |
- movl $TRAP_syscall, 4(%rsp)
|
|
|
4d6e2c0 |
+ movl $TRAP_syscall, EFRAME_entry_vector(%rsp)
|
|
|
4d6e2c0 |
SAVE_ALL
|
|
|
4d6e2c0 |
|
|
|
4d6e2c0 |
SPEC_CTRL_ENTRY_FROM_PV /* Req: %rsp=regs/cpuinfo, %rdx=0, Clob: acd */
|
|
|
4d6e2c0 |
@@ -294,7 +294,7 @@ ENTRY(cstar_enter)
|
|
|
4d6e2c0 |
pushq $FLAT_USER_CS32
|
|
|
4d6e2c0 |
pushq %rcx
|
|
|
4d6e2c0 |
pushq $0
|
|
|
4d6e2c0 |
- movl $TRAP_syscall, 4(%rsp)
|
|
|
4d6e2c0 |
+ movl $TRAP_syscall, EFRAME_entry_vector(%rsp)
|
|
|
4d6e2c0 |
SAVE_ALL
|
|
|
4d6e2c0 |
|
|
|
4d6e2c0 |
SPEC_CTRL_ENTRY_FROM_PV /* Req: %rsp=regs/cpuinfo, %rdx=0, Clob: acd */
|
|
|
4d6e2c0 |
@@ -335,7 +335,7 @@ GLOBAL(sysenter_eflags_saved)
|
|
|
4d6e2c0 |
pushq $3 /* ring 3 null cs */
|
|
|
4d6e2c0 |
pushq $0 /* null rip */
|
|
|
4d6e2c0 |
pushq $0
|
|
|
4d6e2c0 |
- movl $TRAP_syscall, 4(%rsp)
|
|
|
4d6e2c0 |
+ movl $TRAP_syscall, EFRAME_entry_vector(%rsp)
|
|
|
4d6e2c0 |
SAVE_ALL
|
|
|
4d6e2c0 |
|
|
|
4d6e2c0 |
SPEC_CTRL_ENTRY_FROM_PV /* Req: %rsp=regs/cpuinfo, %rdx=0, Clob: acd */
|
|
|
4d6e2c0 |
@@ -389,7 +389,7 @@ ENTRY(int80_direct_trap)
|
|
|
4d6e2c0 |
ENDBR64
|
|
|
4d6e2c0 |
ALTERNATIVE "", clac, X86_FEATURE_XEN_SMAP
|
|
|
4d6e2c0 |
pushq $0
|
|
|
4d6e2c0 |
- movl $0x80, 4(%rsp)
|
|
|
4d6e2c0 |
+ movl $0x80, EFRAME_entry_vector(%rsp)
|
|
|
4d6e2c0 |
SAVE_ALL
|
|
|
4d6e2c0 |
|
|
|
4d6e2c0 |
SPEC_CTRL_ENTRY_FROM_PV /* Req: %rsp=regs/cpuinfo, %rdx=0, Clob: acd */
|
|
|
4d6e2c0 |
@@ -649,7 +649,7 @@ ret_from_intr:
|
|
|
4d6e2c0 |
.section .init.text, "ax", @progbits
|
|
|
4d6e2c0 |
ENTRY(early_page_fault)
|
|
|
4d6e2c0 |
ENDBR64
|
|
|
4d6e2c0 |
- movl $X86_EXC_PF, 4(%rsp)
|
|
|
4d6e2c0 |
+ movl $X86_EXC_PF, EFRAME_entry_vector(%rsp)
|
|
|
4d6e2c0 |
SAVE_ALL
|
|
|
4d6e2c0 |
movq %rsp, %rdi
|
|
|
4d6e2c0 |
call do_early_page_fault
|
|
|
4d6e2c0 |
@@ -716,7 +716,7 @@ ENTRY(common_interrupt)
|
|
|
4d6e2c0 |
|
|
|
4d6e2c0 |
ENTRY(entry_PF)
|
|
|
4d6e2c0 |
ENDBR64
|
|
|
4d6e2c0 |
- movl $X86_EXC_PF, 4(%rsp)
|
|
|
4d6e2c0 |
+ movl $X86_EXC_PF, EFRAME_entry_vector(%rsp)
|
|
|
4d6e2c0 |
/* No special register assumptions. */
|
|
|
4d6e2c0 |
GLOBAL(handle_exception)
|
|
|
4d6e2c0 |
ALTERNATIVE "", clac, X86_FEATURE_XEN_SMAP
|
|
|
4d6e2c0 |
@@ -890,90 +890,90 @@ FATAL_exception_with_ints_disabled:
|
|
|
4d6e2c0 |
ENTRY(entry_DE)
|
|
|
4d6e2c0 |
ENDBR64
|
|
|
4d6e2c0 |
pushq $0
|
|
|
4d6e2c0 |
- movl $X86_EXC_DE, 4(%rsp)
|
|
|
4d6e2c0 |
+ movl $X86_EXC_DE, EFRAME_entry_vector(%rsp)
|
|
|
4d6e2c0 |
jmp handle_exception
|
|
|
4d6e2c0 |
|
|
|
4d6e2c0 |
ENTRY(entry_MF)
|
|
|
4d6e2c0 |
ENDBR64
|
|
|
4d6e2c0 |
pushq $0
|
|
|
4d6e2c0 |
- movl $X86_EXC_MF, 4(%rsp)
|
|
|
4d6e2c0 |
+ movl $X86_EXC_MF, EFRAME_entry_vector(%rsp)
|
|
|
4d6e2c0 |
jmp handle_exception
|
|
|
4d6e2c0 |
|
|
|
4d6e2c0 |
ENTRY(entry_XM)
|
|
|
4d6e2c0 |
ENDBR64
|
|
|
4d6e2c0 |
pushq $0
|
|
|
4d6e2c0 |
- movl $X86_EXC_XM, 4(%rsp)
|
|
|
4d6e2c0 |
+ movl $X86_EXC_XM, EFRAME_entry_vector(%rsp)
|
|
|
4d6e2c0 |
jmp handle_exception
|
|
|
4d6e2c0 |
|
|
|
4d6e2c0 |
ENTRY(entry_NM)
|
|
|
4d6e2c0 |
ENDBR64
|
|
|
4d6e2c0 |
pushq $0
|
|
|
4d6e2c0 |
- movl $X86_EXC_NM, 4(%rsp)
|
|
|
4d6e2c0 |
+ movl $X86_EXC_NM, EFRAME_entry_vector(%rsp)
|
|
|
4d6e2c0 |
jmp handle_exception
|
|
|
4d6e2c0 |
|
|
|
4d6e2c0 |
ENTRY(entry_DB)
|
|
|
4d6e2c0 |
ENDBR64
|
|
|
4d6e2c0 |
pushq $0
|
|
|
4d6e2c0 |
- movl $X86_EXC_DB, 4(%rsp)
|
|
|
4d6e2c0 |
+ movl $X86_EXC_DB, EFRAME_entry_vector(%rsp)
|
|
|
4d6e2c0 |
jmp handle_ist_exception
|
|
|
4d6e2c0 |
|
|
|
4d6e2c0 |
ENTRY(entry_BP)
|
|
|
4d6e2c0 |
ENDBR64
|
|
|
4d6e2c0 |
pushq $0
|
|
|
4d6e2c0 |
- movl $X86_EXC_BP, 4(%rsp)
|
|
|
4d6e2c0 |
+ movl $X86_EXC_BP, EFRAME_entry_vector(%rsp)
|
|
|
4d6e2c0 |
jmp handle_exception
|
|
|
4d6e2c0 |
|
|
|
4d6e2c0 |
ENTRY(entry_OF)
|
|
|
4d6e2c0 |
ENDBR64
|
|
|
4d6e2c0 |
pushq $0
|
|
|
4d6e2c0 |
- movl $X86_EXC_OF, 4(%rsp)
|
|
|
4d6e2c0 |
+ movl $X86_EXC_OF, EFRAME_entry_vector(%rsp)
|
|
|
4d6e2c0 |
jmp handle_exception
|
|
|
4d6e2c0 |
|
|
|
4d6e2c0 |
ENTRY(entry_BR)
|
|
|
4d6e2c0 |
ENDBR64
|
|
|
4d6e2c0 |
pushq $0
|
|
|
4d6e2c0 |
- movl $X86_EXC_BR, 4(%rsp)
|
|
|
4d6e2c0 |
+ movl $X86_EXC_BR, EFRAME_entry_vector(%rsp)
|
|
|
4d6e2c0 |
jmp handle_exception
|
|
|
4d6e2c0 |
|
|
|
4d6e2c0 |
ENTRY(entry_UD)
|
|
|
4d6e2c0 |
ENDBR64
|
|
|
4d6e2c0 |
pushq $0
|
|
|
4d6e2c0 |
- movl $X86_EXC_UD, 4(%rsp)
|
|
|
4d6e2c0 |
+ movl $X86_EXC_UD, EFRAME_entry_vector(%rsp)
|
|
|
4d6e2c0 |
jmp handle_exception
|
|
|
4d6e2c0 |
|
|
|
4d6e2c0 |
ENTRY(entry_TS)
|
|
|
4d6e2c0 |
ENDBR64
|
|
|
4d6e2c0 |
- movl $X86_EXC_TS, 4(%rsp)
|
|
|
4d6e2c0 |
+ movl $X86_EXC_TS, EFRAME_entry_vector(%rsp)
|
|
|
4d6e2c0 |
jmp handle_exception
|
|
|
4d6e2c0 |
|
|
|
4d6e2c0 |
ENTRY(entry_NP)
|
|
|
4d6e2c0 |
ENDBR64
|
|
|
4d6e2c0 |
- movl $X86_EXC_NP, 4(%rsp)
|
|
|
4d6e2c0 |
+ movl $X86_EXC_NP, EFRAME_entry_vector(%rsp)
|
|
|
4d6e2c0 |
jmp handle_exception
|
|
|
4d6e2c0 |
|
|
|
4d6e2c0 |
ENTRY(entry_SS)
|
|
|
4d6e2c0 |
ENDBR64
|
|
|
4d6e2c0 |
- movl $X86_EXC_SS, 4(%rsp)
|
|
|
4d6e2c0 |
+ movl $X86_EXC_SS, EFRAME_entry_vector(%rsp)
|
|
|
4d6e2c0 |
jmp handle_exception
|
|
|
4d6e2c0 |
|
|
|
4d6e2c0 |
ENTRY(entry_GP)
|
|
|
4d6e2c0 |
ENDBR64
|
|
|
4d6e2c0 |
- movl $X86_EXC_GP, 4(%rsp)
|
|
|
4d6e2c0 |
+ movl $X86_EXC_GP, EFRAME_entry_vector(%rsp)
|
|
|
4d6e2c0 |
jmp handle_exception
|
|
|
4d6e2c0 |
|
|
|
4d6e2c0 |
ENTRY(entry_AC)
|
|
|
4d6e2c0 |
ENDBR64
|
|
|
4d6e2c0 |
- movl $X86_EXC_AC, 4(%rsp)
|
|
|
4d6e2c0 |
+ movl $X86_EXC_AC, EFRAME_entry_vector(%rsp)
|
|
|
4d6e2c0 |
jmp handle_exception
|
|
|
4d6e2c0 |
|
|
|
4d6e2c0 |
ENTRY(entry_CP)
|
|
|
4d6e2c0 |
ENDBR64
|
|
|
4d6e2c0 |
- movl $X86_EXC_CP, 4(%rsp)
|
|
|
4d6e2c0 |
+ movl $X86_EXC_CP, EFRAME_entry_vector(%rsp)
|
|
|
4d6e2c0 |
jmp handle_exception
|
|
|
4d6e2c0 |
|
|
|
4d6e2c0 |
ENTRY(entry_DF)
|
|
|
4d6e2c0 |
ENDBR64
|
|
|
4d6e2c0 |
- movl $X86_EXC_DF, 4(%rsp)
|
|
|
4d6e2c0 |
+ movl $X86_EXC_DF, EFRAME_entry_vector(%rsp)
|
|
|
4d6e2c0 |
/* Set AC to reduce chance of further SMAP faults */
|
|
|
4d6e2c0 |
ALTERNATIVE "", stac, X86_FEATURE_XEN_SMAP
|
|
|
4d6e2c0 |
SAVE_ALL
|
|
|
4d6e2c0 |
@@ -998,7 +998,7 @@ ENTRY(entry_DF)
|
|
|
4d6e2c0 |
ENTRY(entry_NMI)
|
|
|
4d6e2c0 |
ENDBR64
|
|
|
4d6e2c0 |
pushq $0
|
|
|
4d6e2c0 |
- movl $X86_EXC_NMI, 4(%rsp)
|
|
|
4d6e2c0 |
+ movl $X86_EXC_NMI, EFRAME_entry_vector(%rsp)
|
|
|
4d6e2c0 |
handle_ist_exception:
|
|
|
4d6e2c0 |
ALTERNATIVE "", clac, X86_FEATURE_XEN_SMAP
|
|
|
4d6e2c0 |
SAVE_ALL
|
|
|
4d6e2c0 |
@@ -1130,7 +1130,7 @@ handle_ist_exception:
|
|
|
4d6e2c0 |
ENTRY(entry_MC)
|
|
|
4d6e2c0 |
ENDBR64
|
|
|
4d6e2c0 |
pushq $0
|
|
|
4d6e2c0 |
- movl $X86_EXC_MC, 4(%rsp)
|
|
|
4d6e2c0 |
+ movl $X86_EXC_MC, EFRAME_entry_vector(%rsp)
|
|
|
4d6e2c0 |
jmp handle_ist_exception
|
|
|
4d6e2c0 |
|
|
|
4d6e2c0 |
/* No op trap handler. Required for kexec crash path. */
|
|
|
4d6e2c0 |
@@ -1167,7 +1167,7 @@ autogen_stubs: /* Automatically generated stubs. */
|
|
|
4d6e2c0 |
1:
|
|
|
4d6e2c0 |
ENDBR64
|
|
|
4d6e2c0 |
pushq $0
|
|
|
4d6e2c0 |
- movb $vec,4(%rsp)
|
|
|
4d6e2c0 |
+ movb $vec, EFRAME_entry_vector(%rsp)
|
|
|
4d6e2c0 |
jmp common_interrupt
|
|
|
4d6e2c0 |
|
|
|
4d6e2c0 |
entrypoint 1b
|
|
|
4d6e2c0 |
@@ -1181,7 +1181,7 @@ autogen_stubs: /* Automatically generated stubs. */
|
|
|
4d6e2c0 |
test $8,%spl /* 64bit exception frames are 16 byte aligned, but the word */
|
|
|
4d6e2c0 |
jz 2f /* size is 8 bytes. Check whether the processor gave us an */
|
|
|
4d6e2c0 |
pushq $0 /* error code, and insert an empty one if not. */
|
|
|
4d6e2c0 |
-2: movb $vec,4(%rsp)
|
|
|
4d6e2c0 |
+2: movb $vec, EFRAME_entry_vector(%rsp)
|
|
|
4d6e2c0 |
jmp handle_exception
|
|
|
4d6e2c0 |
|
|
|
4d6e2c0 |
entrypoint 1b
|