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commit 8ea75b268f11794f4a7e7bac52cb256490ed3fd2
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Author: Dave Airlie <airlied@linux.ie>
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Date:   Tue Feb 26 16:29:19 2008 +1000
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fb7d64
    regs: fix spelling properly
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commit f2816064a6c2c4c35ccba74b9aa80547e25c012e
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Author: Dave Airlie <airlied@linux.ie>
fb7d64
Date:   Tue Feb 26 16:28:24 2008 +1000
fb7d64
fb7d64
    regs: fix spelling mistake
fb7d64
    
fb7d64
    pointed out by plaes on irc
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fb7d64
commit 9d2ca30b90607085578dde1f314db663bd5f82ec
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Author: Alex Deucher <alex@samba.(none)>
fb7d64
Date:   Mon Feb 25 17:34:00 2008 -0500
fb7d64
fb7d64
    R300/R500: clean up magic numbers in render code
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commit 153ad6fcf704cbf9f811d9986cd4baf04e82c9d2
fb7d64
Author: Dave Airlie <airlied@linux.ie>
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Date:   Mon Feb 25 07:10:48 2008 +1000
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    fixup check for EXA composite pointed out by Alan Swanson
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commit 85e470e64f629de72e361c77770e2e29998d1bf4
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Merge: 27ddb39... 1b84c76...
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Author: Alex Deucher <alex@samba.(none)>
fb7d64
Date:   Sun Feb 24 05:37:22 2008 -0500
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fb7d64
    Merge master and fix conflicts
fb7d64
    
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    Merge branch 'master' of ssh://agd5f@git.freedesktop.org/git/xorg/driver/xf86-video-ati
fb7d64
    
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    Conflicts:
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    	src/radeon_commonfuncs.c
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commit 27ddb39b12a0b54e099fd5274c4c91f08e2d2822
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Author: Alex Deucher <alex@samba.(none)>
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Date:   Sun Feb 24 05:30:11 2008 -0500
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fb7d64
    R300: clean up magic numbers in RADEONInit3DEngine
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commit d4c20f33ad6a1f88615cd7e09ad3638896873f9e
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Author: Alex Deucher <alex@samba.(none)>
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Date:   Sun Feb 24 04:46:10 2008 -0500
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    R300: replace magic numbers in cache flush
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commit e52f1c8d2647b81d891ec0728dd582941a76c83f
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Author: Alex Deucher <alex@samba.(none)>
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Date:   Sun Feb 24 04:43:18 2008 -0500
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    R300: fill in some more 3D bitfields
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commit 1b84c76f27c8d24cb42beae26abf000721901c1c
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Author: Dave Airlie <airlied@redhat.com>
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Date:   Sun Feb 24 19:20:36 2008 +1100
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    rs690: initial textured video support
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commit 68158124366db883a901e960fe5f05f8df5efa42
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Author: Dave Airlie <airlied@redhat.com>
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Date:   Tue Feb 19 19:51:18 2008 +1100
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    rs690: initial rs690 rotate
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    suffers same problem as r500 with clipping
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commit e614bb6965588bf09dcb87f5e08e67120ec9847f
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Author: Dave Airlie <airlied@redhat.com>
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Date:   Sun Feb 24 01:46:05 2008 -0500
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    r500: convert fragprog to use register values
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commit 6ce9ee47c75620b2e5d211c5d59d17271a6a7b19
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Author: Dave Airlie <airlied@redhat.com>
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Date:   Sat Feb 23 22:49:34 2008 -0500
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    r500: add textured video Xv adapter support
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commit 9aaf8b33b22b6ba112869558ae54e021b9487ad2
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Author: Dave Airlie <airlied@redhat.com>
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Date:   Sat Feb 23 22:16:25 2008 -0500
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    r500: initial rotate support - not fully working yet.
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    Just an example of how to setup and run the r500 3D engine for rotation.
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    this rotates for me but I get some strange clipping on the bottom of my screen
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commit 05dc3e4fc19d056ce99a7b110665adab2ca1ea21
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Author: Adam Jackson <ajax@redhat.com>
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Date:   Sat Feb 23 20:29:51 2008 -0500
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    Clarify R500 US setup.
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commit 080606ad528972623e1ed1124d8efe7705a73446
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Author: Adam Jackson <ajax@redhat.com>
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Date:   Sat Feb 23 20:21:17 2008 -0500
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    Add the R500 US index/data pair.
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commit edfb3b6bbf0ee17ace8e6ba704a6f54e249fec63
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Author: Alex Deucher <alex@samba.(none)>
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Date:   Sat Feb 23 19:59:33 2008 -0500
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    RADEON: no textured video yet on XPRESS chips
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    Still need to sort out the VAP and PVS stuff
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commit 4146bfe5d00e40a86d17826fac50d04b2469621d
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Author: Alex Deucher <alex@samba.(none)>
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Date:   Sat Feb 23 19:21:52 2008 -0500
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    R500: fix typo in new r5xx regs
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commit d9be9f34b0d3313e7b22b2a8bb0a8924ad3116bf
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Author: Alex Deucher <alex@samba.(none)>
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Date:   Sat Feb 23 19:06:30 2008 -0500
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    RADEON: add textured video support for r1xx-r4xx radeons
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    Based on the kdrive ati video code by Eric Anholt.
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    R3xx/R4xx still have some clipping issues in certain situations
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commit 9dc4acad79196e9d5d94dd710773bfa83456d47f
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Author: Alex Deucher <alex@cube.(none)>
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Date:   Sat Feb 23 18:29:00 2008 -0500
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    RS6xx: gpio entry for DDIA varies depending on the number of DFP ports
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commit ed0a93edf28155308e7ab9d8705581bb38455ea0
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Author: Adam Jackson <ajax@redhat.com>
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Date:   Sat Feb 23 15:02:17 2008 -0500
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    Fix R500_US_CONFIG.
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commit bc2bd6f841b51aeed3b6b4a47dbe758c200bc5a6
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Author: Adam Jackson <ajax@redhat.com>
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Date:   Sat Feb 23 14:34:18 2008 -0500
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    Add R500 unified shader register block.
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commit a7b5c3bb74fc4de5e38a75ac31656445ce823464
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Author: Alex Deucher <alex@cube.(none)>
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Date:   Fri Feb 22 19:35:11 2008 -0500
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    RS6xx: fix DDC on DDIA output (usually HDMI port)
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commit 3327a681e21101cc6f6e162f4e29f9937b69ccc3
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Author: Alex Deucher <alex@cube.(none)>
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Date:   Fri Feb 22 17:05:56 2008 -0500
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    ATOM: properly set up DDIA output on RS6xx boards
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commit 1d0e9ab8b9451101b1b91943546f6c5833c21b3f
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Author: Michel Dänzer <michel@tungstengraphics.com>
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Date:   Wed Feb 20 10:21:49 2008 +0100
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    radeon: Fix typo flagged by gcc -Wall.
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commit b5bd442b60dbc72fe4c1e928ab864aeb0fd7a3cb
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Author: Alex Deucher <alex@botch2.(none)>
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Date:   Tue Feb 19 20:47:40 2008 -0500
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    R100: fix render accel for transforms
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    Not sure why we had a separate broken path for r100 vertex
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    submission.
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commit a0a73208a21546ac120fb9a463261836c9ea7b55
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Author: Alex Deucher <alex@botch2.(none)>
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Date:   Tue Feb 19 20:11:19 2008 -0500
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    RADEON: restore clock gating and CP clock errata on VT switch
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    This may help people with hangs on resume
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commit b77e2aff7453a9f370beba37ca3c25b92b3f97ff
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Author: Alex Deucher <alex@botch2.(none)>
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Date:   Tue Feb 19 19:55:41 2008 -0500
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    RADEON: fix DDC types 5 and 6
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commit af82172a82f2bdf96e571def659a1c70f92dfdbf
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Author: Alex Deucher <alex@botch2.(none)>
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Date:   Tue Feb 19 19:39:35 2008 -0500
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    RADEON: update man page with supported chips
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diff --git a/man/radeon.man b/man/radeon.man
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index b4ade32..86be965 100644
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--- a/man/radeon.man
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+++ b/man/radeon.man
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@@ -53,7 +53,7 @@ Radeon 9100 IGP
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 Radeon 9200 IGP
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 .TP 12
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 .B RS400
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-Radeon XPRESS 200/200M IGP (2d only)
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+Radeon XPRESS 200/200M IGP
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 .TP 12
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 .B RV280
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 Radeon 9200PRO/9200/9200SE, M9+
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@@ -90,6 +90,30 @@ Radeon X800, M28 PCIE
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 .TP 12
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 .B R480/R481
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 Radeon X850 PCIE/AGP
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+.TP 12
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+.B RV515
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+Radeon X1300/X1400/X1500
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+.TP 12
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+.B R520
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+Radeon X1800
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+.TP 12
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+.B RV530/RV560
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+Radeon X1600/X1650/X1700
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+.TP 12
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+.B RV570/R580
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+Radeon X1900/X1950
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+.TP 12
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+.B RS600/RS690
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+Radeon X1200
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+.TP 12
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+.B R600
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+Radeon HD 2900
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+.TP 12
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+.B RV610/RV630
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+Radeon HD 2400/2600
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+.TP 12
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+.B RV670
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+Radeon HD 3850/3870
fb7d64
 
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 .SH CONFIGURATION DETAILS
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 Please refer to __xconfigfile__(__filemansuffix__) for general configuration
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diff --git a/src/Makefile.am b/src/Makefile.am
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index a146df3..e0799a5 100644
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--- a/src/Makefile.am
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+++ b/src/Makefile.am
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@@ -114,6 +114,7 @@ radeon_drv_la_SOURCES = \
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 	radeon_driver.c radeon_video.c radeon_bios.c radeon_mm_i2c.c \
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 	radeon_vip.c radeon_misc.c radeon_probe.c \
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 	legacy_crtc.c legacy_output.c \
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+	radeon_textured_video.c \
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 	radeon_crtc.c radeon_output.c radeon_modes.c radeon_tv.c \
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 	$(RADEON_ATOMBIOS_SOURCES) radeon_atombios.c radeon_atomwrapper.c \
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 	$(RADEON_DRI_SRCS) $(RADEON_EXA_SOURCES) atombios_output.c atombios_crtc.c
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diff --git a/src/atombios_output.c b/src/atombios_output.c
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index 6c638b1..07d212f 100644
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--- a/src/atombios_output.c
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+++ b/src/atombios_output.c
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@@ -235,6 +235,35 @@ atombios_external_tmds_setup(xf86OutputPtr output, DisplayModePtr mode)
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 }
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 static int
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+atombios_ddia_setup(xf86OutputPtr output, DisplayModePtr mode)
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+{
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+    RADEONInfoPtr info       = RADEONPTR(output->scrn);
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+    DVO_ENCODER_CONTROL_PS_ALLOCATION disp_data;
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+    AtomBiosArgRec data;
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+    unsigned char *space;
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+
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+    disp_data.sDVOEncoder.ucAction = ATOM_ENABLE;
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+    disp_data.sDVOEncoder.usPixelClock = mode->Clock / 10;
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+
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+    if (mode->Clock > 165000)
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+	disp_data.sDVOEncoder.usDevAttr.sDigAttrib.ucAttribute = PANEL_ENCODER_MISC_DUAL;
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+    else
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+	disp_data.sDVOEncoder.usDevAttr.sDigAttrib.ucAttribute = 0;
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+
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+    data.exec.index = GetIndexIntoMasterTable(COMMAND, DVOEncoderControl);
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+    data.exec.dataSpace = (void *)&space;
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+    data.exec.pspace = &disp_data;
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+
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+    if (RHDAtomBiosFunc(info->atomBIOS->scrnIndex, info->atomBIOS, ATOMBIOS_EXEC, &data) == ATOM_SUCCESS) {
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+	ErrorF("DDIA setup success\n");
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+	return ATOM_SUCCESS;
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+    }
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+
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+    ErrorF("DDIA setup failed\n");
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+    return ATOM_NOT_IMPLEMENTED;
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+}
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+
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+static int
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 atombios_output_tmds1_setup(xf86OutputPtr output, DisplayModePtr mode)
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 {
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     RADEONInfoPtr info       = RADEONPTR(output->scrn);
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@@ -536,6 +565,7 @@ atombios_output_mode_set(xf86OutputPtr output,
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 			 DisplayModePtr adjusted_mode)
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 {
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     RADEONOutputPrivatePtr radeon_output = output->driver_private;
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+    RADEONInfoPtr info       = RADEONPTR(output->scrn);
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     atombios_output_scaler_setup(output, mode);
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     atombios_set_output_crtc_source(output);
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@@ -551,9 +581,12 @@ atombios_output_mode_set(xf86OutputPtr output,
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     } else if (radeon_output->MonType == MT_DFP) {
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        if (radeon_output->devices & ATOM_DEVICE_DFP1_SUPPORT)
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 	   atombios_output_tmds1_setup(output, adjusted_mode);
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-       else if (radeon_output->devices & ATOM_DEVICE_DFP2_SUPPORT)
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-	   atombios_external_tmds_setup(output, adjusted_mode);
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-       else if (radeon_output->devices & ATOM_DEVICE_DFP3_SUPPORT)
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+       else if (radeon_output->devices & ATOM_DEVICE_DFP2_SUPPORT) {
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+	   if (info->IsIGP)
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+	       atombios_ddia_setup(output, adjusted_mode);
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+	   else
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+	       atombios_external_tmds_setup(output, adjusted_mode);
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+       } else if (radeon_output->devices & ATOM_DEVICE_DFP3_SUPPORT)
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 	   atombios_output_tmds2_setup(output, adjusted_mode);
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     } else if (radeon_output->MonType == MT_LCD) {
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 	if (radeon_output->devices & ATOM_DEVICE_LCD1_SUPPORT)
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diff --git a/src/radeon.h b/src/radeon.h
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index 7d63f28..aba3c0f 100644
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--- a/src/radeon.h
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+++ b/src/radeon.h
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@@ -184,6 +184,8 @@ typedef enum {
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 				   * for something else.
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 				   */
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+#define xFixedToFloat(f) (((float) (f)) / 65536)
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+
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 #define RADEON_LOGLEVEL_DEBUG 4
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 /* for Xv, outputs */
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diff --git a/src/radeon_atombios.c b/src/radeon_atombios.c
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index ddd332f..88c220b 100644
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--- a/src/radeon_atombios.c
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+++ b/src/radeon_atombios.c
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@@ -1759,7 +1759,15 @@ RADEONGetATOMConnectorInfoFromBIOSConnectorTable (ScrnInfoPtr pScrn)
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 	    (i == ATOM_DEVICE_TV2_INDEX) ||
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 	    (i == ATOM_DEVICE_CV_INDEX))
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 	    info->BiosConnector[i].ddc_i2c.valid = FALSE;
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-	else
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+	else if ((i == ATOM_DEVICE_DFP3_INDEX) && info->IsIGP) {
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+	    /* DDIA port uses non-standard gpio entry */
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+	    if (info->BiosConnector[ATOM_DEVICE_DFP2_INDEX].valid)
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+		info->BiosConnector[i].ddc_i2c =
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+		    RADEONLookupGPIOLineForDDC(pScrn, ci.sucI2cId.sbfAccess.bfI2C_LineMux + 2);
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+	    else
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+		info->BiosConnector[i].ddc_i2c =
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+		    RADEONLookupGPIOLineForDDC(pScrn, ci.sucI2cId.sbfAccess.bfI2C_LineMux + 1);
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+	} else
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 	    info->BiosConnector[i].ddc_i2c =
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 		RADEONLookupGPIOLineForDDC(pScrn, ci.sucI2cId.sbfAccess.bfI2C_LineMux);
fb7d64
 
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@@ -1772,7 +1780,7 @@ RADEONGetATOMConnectorInfoFromBIOSConnectorTable (ScrnInfoPtr pScrn)
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 		info->BiosConnector[i].TMDSType = TMDS_EXT;
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 	} else if (i == ATOM_DEVICE_DFP3_INDEX) {
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 	    if (info->IsIGP)
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-		info->BiosConnector[i].TMDSType = TMDS_EXT;
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+		info->BiosConnector[i].TMDSType = TMDS_DDIA;
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 	    else
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 		info->BiosConnector[i].TMDSType = TMDS_LVTMA;
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 	} else
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diff --git a/src/radeon_commonfuncs.c b/src/radeon_commonfuncs.c
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index 8c4b598..af06735 100644
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--- a/src/radeon_commonfuncs.c
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+++ b/src/radeon_commonfuncs.c
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@@ -57,138 +57,153 @@ static void FUNC_NAME(RADEONInit3DEngine)(ScrnInfoPtr pScrn)
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     info->texW[0] = info->texH[0] = info->texW[1] = info->texH[1] = 1;
fb7d64
 
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-    if (IS_R300_VARIANT) {
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+    if (IS_R300_VARIANT || IS_AVIVO_VARIANT || info->ChipFamily == CHIP_FAMILY_RS690) {
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 	BEGIN_ACCEL(3);
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-	OUT_ACCEL_REG(R300_RB3D_DSTCACHE_CTLSTAT, 0xA);
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-	OUT_ACCEL_REG(R300_RB3D_ZCACHE_CTLSTAT, 0x3);
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-	OUT_ACCEL_REG(R300_WAIT_UNTIL, 0x30000);
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+	OUT_ACCEL_REG(R300_RB3D_DSTCACHE_CTLSTAT, R300_DC_FLUSH_3D | R300_DC_FREE_3D);
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+	OUT_ACCEL_REG(R300_RB3D_ZCACHE_CTLSTAT, R300_ZC_FLUSH | R300_ZC_FREE);
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+	OUT_ACCEL_REG(R300_WAIT_UNTIL, R300_WAIT_2D_IDLECLEAN | R300_WAIT_3D_IDLECLEAN);
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 	FINISH_ACCEL();
fb7d64
 
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 	BEGIN_ACCEL(3);
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-	OUT_ACCEL_REG(R300_GB_TILE_CONFIG, 0x10011);
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-	OUT_ACCEL_REG(R300_GB_SELECT,0x0);
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-	OUT_ACCEL_REG(R300_GB_ENABLE, 0x0);
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+	OUT_ACCEL_REG(R300_GB_TILE_CONFIG, (R300_ENABLE_TILING |
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+					    R300_TILE_SIZE_16 |
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+					    R300_SUBPIXEL_1_16));
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+	OUT_ACCEL_REG(R300_GB_SELECT, 0);
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+	OUT_ACCEL_REG(R300_GB_ENABLE, 0);
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 	FINISH_ACCEL();
fb7d64
 
fb7d64
 	BEGIN_ACCEL(3);
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-	OUT_ACCEL_REG(R300_RB3D_DSTCACHE_CTLSTAT, 0xA);
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-	OUT_ACCEL_REG(R300_RB3D_ZCACHE_CTLSTAT, 0x3);
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-	OUT_ACCEL_REG(R300_WAIT_UNTIL, 0x30000);
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+	OUT_ACCEL_REG(R300_RB3D_DSTCACHE_CTLSTAT, R300_DC_FLUSH_3D | R300_DC_FREE_3D);
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+	OUT_ACCEL_REG(R300_RB3D_ZCACHE_CTLSTAT, R300_ZC_FLUSH | R300_ZC_FREE);
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+	OUT_ACCEL_REG(R300_WAIT_UNTIL, R300_WAIT_2D_IDLECLEAN | R300_WAIT_3D_IDLECLEAN);
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 	FINISH_ACCEL();
fb7d64
 
fb7d64
 	BEGIN_ACCEL(5);
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-	OUT_ACCEL_REG(R300_GB_AA_CONFIG, 0x0);
fb7d64
-	OUT_ACCEL_REG(R300_RB3D_DSTCACHE_CTLSTAT, 0xA);
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-	OUT_ACCEL_REG(R300_RB3D_ZCACHE_CTLSTAT, 0x3);
fb7d64
-	OUT_ACCEL_REG(R300_GB_MSPOS0, 0x78888888);
fb7d64
-	OUT_ACCEL_REG(R300_GB_MSPOS1, 0x08888888);
fb7d64
+	OUT_ACCEL_REG(R300_GB_AA_CONFIG, 0);
fb7d64
+	OUT_ACCEL_REG(R300_RB3D_DSTCACHE_CTLSTAT, R300_DC_FLUSH_3D | R300_DC_FREE_3D);
fb7d64
+	OUT_ACCEL_REG(R300_RB3D_ZCACHE_CTLSTAT, R300_ZC_FLUSH | R300_ZC_FREE);
fb7d64
+	OUT_ACCEL_REG(R300_GB_MSPOS0, ((8 << R300_MS_X0_SHIFT) |
fb7d64
+				       (8 << R300_MS_Y0_SHIFT) |
fb7d64
+				       (8 << R300_MS_X1_SHIFT) |
fb7d64
+				       (8 << R300_MS_Y1_SHIFT) |
fb7d64
+				       (8 << R300_MS_X2_SHIFT) |
fb7d64
+				       (8 << R300_MS_Y2_SHIFT) |
fb7d64
+				       (8 << R300_MSBD0_Y_SHIFT) |
fb7d64
+				       (7 << R300_MSBD0_X_SHIFT)));
fb7d64
+	OUT_ACCEL_REG(R300_GB_MSPOS1, ((8 << R300_MS_X3_SHIFT) |
fb7d64
+				       (8 << R300_MS_Y3_SHIFT) |
fb7d64
+				       (8 << R300_MS_X4_SHIFT) |
fb7d64
+				       (8 << R300_MS_Y4_SHIFT) |
fb7d64
+				       (8 << R300_MS_X5_SHIFT) |
fb7d64
+				       (8 << R300_MS_Y5_SHIFT) |
fb7d64
+				       (8 << R300_MSBD1_SHIFT)));
fb7d64
 	FINISH_ACCEL();
fb7d64
 
fb7d64
 	BEGIN_ACCEL(4);
fb7d64
-	OUT_ACCEL_REG(R300_GA_POLY_MODE, 0x120);
fb7d64
-	OUT_ACCEL_REG(R300_GA_ROUND_MODE, 0x5);
fb7d64
-	OUT_ACCEL_REG(R300_GA_COLOR_CONTROL, 0xAAAA);
fb7d64
-	OUT_ACCEL_REG(R300_GA_OFFSET, 0x0);
fb7d64
+	OUT_ACCEL_REG(R300_GA_POLY_MODE, R300_FRONT_PTYPE_TRIANGE | R300_BACK_PTYPE_TRIANGE);
fb7d64
+	OUT_ACCEL_REG(R300_GA_ROUND_MODE, (R300_GEOMETRY_ROUND_NEAREST |
fb7d64
+					   R300_COLOR_ROUND_NEAREST));
fb7d64
+	OUT_ACCEL_REG(R300_GA_COLOR_CONTROL, (R300_RGB0_SHADING_GOURAUD |
fb7d64
+					      R300_ALPHA0_SHADING_GOURAUD |
fb7d64
+					      R300_RGB1_SHADING_GOURAUD |
fb7d64
+					      R300_ALPHA1_SHADING_GOURAUD |
fb7d64
+					      R300_RGB2_SHADING_GOURAUD |
fb7d64
+					      R300_ALPHA2_SHADING_GOURAUD |
fb7d64
+					      R300_RGB3_SHADING_GOURAUD |
fb7d64
+					      R300_ALPHA3_SHADING_GOURAUD));
fb7d64
+	OUT_ACCEL_REG(R300_GA_OFFSET, 0);
fb7d64
 	FINISH_ACCEL();
fb7d64
 
fb7d64
-	BEGIN_ACCEL(26);
fb7d64
-	OUT_ACCEL_REG(R300_VAP_CNTL_STATUS, 0x0);
fb7d64
-	OUT_ACCEL_REG(R300_VAP_PVS_STATE_FLUSH_REG, 0x0);
fb7d64
-	OUT_ACCEL_REG(R300_VAP_CNTL, 0x300456);
fb7d64
-	OUT_ACCEL_REG(R300_VAP_VTE_CNTL, 0x300);
fb7d64
-	OUT_ACCEL_REG(R300_VAP_PSC_SGN_NORM_CNTL, 0x0);
fb7d64
-	OUT_ACCEL_REG(R300_VAP_PROG_STREAM_CNTL_0, 0x4a014001);
fb7d64
-	OUT_ACCEL_REG(R300_VAP_PROG_STREAM_CNTL_1, 0x6b01);
fb7d64
-	OUT_ACCEL_REG(R300_VAP_PROG_STREAM_CNTL_EXT_0, 0xf688f688);
fb7d64
-	OUT_ACCEL_REG(R300_VAP_PROG_STREAM_CNTL_EXT_1, 0xf688);
fb7d64
-	OUT_ACCEL_REG(R300_VAP_PVS_CODE_CNTL_0, 0x100400);
fb7d64
-	OUT_ACCEL_REG(R300_VAP_PVS_CODE_CNTL_1, 0x1);
fb7d64
-	OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_INDX_REG, 0);
fb7d64
-	OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_DATA_REG,0x00f00203);
fb7d64
-	OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_DATA_REG,0x00d10001);
fb7d64
-	OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_DATA_REG,0x01248001);
fb7d64
-	OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_DATA_REG,0x01248001);
fb7d64
-	OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_DATA_REG,0x00f02203);
fb7d64
-	OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_DATA_REG,0x00d10141);
fb7d64
-	OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_DATA_REG,0x01248141);
fb7d64
-	OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_DATA_REG,0x01248141);
fb7d64
-
fb7d64
-	OUT_ACCEL_REG(R300_VAP_PVS_FLOW_CNTL_OPC, 0x0);
fb7d64
-	OUT_ACCEL_REG(R300_VAP_OUT_VTX_FMT_0, 0x1);
fb7d64
-	OUT_ACCEL_REG(R300_VAP_OUT_VTX_FMT_1, (0x2 << 3) | 0x2);
fb7d64
-
fb7d64
-	OUT_ACCEL_REG(R300_VAP_GB_VERT_CLIP_ADJ, 0x3f800000);
fb7d64
-	OUT_ACCEL_REG(R300_VAP_GB_VERT_DISC_ADJ, 0x3f800000);
fb7d64
-	OUT_ACCEL_REG(R300_VAP_GB_HORZ_CLIP_ADJ, 0x3f800000);
fb7d64
-	OUT_ACCEL_REG(R300_VAP_GB_HORZ_DISC_ADJ, 0x3f800000);
fb7d64
-	OUT_ACCEL_REG(R300_VAP_CLIP_CNTL, 0x10000);
fb7d64
-	FINISH_ACCEL();
fb7d64
-
fb7d64
-	BEGIN_ACCEL(7);
fb7d64
-	OUT_ACCEL_REG(R300_SU_TEX_WRAP, 0x0);
fb7d64
-	OUT_ACCEL_REG(R300_SU_POLY_OFFSET_ENABLE, 0x0);
fb7d64
-	OUT_ACCEL_REG(R300_SU_CULL_MODE, 0x4);
fb7d64
+	BEGIN_ACCEL(5);
fb7d64
+	OUT_ACCEL_REG(R300_SU_TEX_WRAP, 0);
fb7d64
+	OUT_ACCEL_REG(R300_SU_POLY_OFFSET_ENABLE, 0);
fb7d64
+	OUT_ACCEL_REG(R300_SU_CULL_MODE, R300_FACE_NEG);
fb7d64
 	OUT_ACCEL_REG(R300_SU_DEPTH_SCALE, 0x4b7fffff);
fb7d64
-	OUT_ACCEL_REG(R300_SU_DEPTH_OFFSET, 0x0);
fb7d64
-	OUT_ACCEL_REG(R300_RS_COUNT, 0x40002);
fb7d64
-	OUT_ACCEL_REG(R300_RS_IP_0, 0x1610000);
fb7d64
+	OUT_ACCEL_REG(R300_SU_DEPTH_OFFSET, 0);
fb7d64
 	FINISH_ACCEL();
fb7d64
 
fb7d64
 	BEGIN_ACCEL(5);
fb7d64
-	OUT_ACCEL_REG(R300_US_W_FMT, 0x0);
fb7d64
-	OUT_ACCEL_REG(R300_US_OUT_FMT_1, 0x1B0F);
fb7d64
-	OUT_ACCEL_REG(R300_US_OUT_FMT_2, 0x1B0F);
fb7d64
-	OUT_ACCEL_REG(R300_US_OUT_FMT_3, 0x1B0F);
fb7d64
-	OUT_ACCEL_REG(R300_US_OUT_FMT_0, 0x1B01);
fb7d64
+	OUT_ACCEL_REG(R300_US_W_FMT, 0);
fb7d64
+	OUT_ACCEL_REG(R300_US_OUT_FMT_1, (R300_OUT_FMT_UNUSED |
fb7d64
+					  R300_OUT_FMT_C0_SEL_BLUE |
fb7d64
+					  R300_OUT_FMT_C1_SEL_GREEN |
fb7d64
+					  R300_OUT_FMT_C2_SEL_RED |
fb7d64
+					  R300_OUT_FMT_C3_SEL_ALPHA));
fb7d64
+	OUT_ACCEL_REG(R300_US_OUT_FMT_2, (R300_OUT_FMT_UNUSED |
fb7d64
+					  R300_OUT_FMT_C0_SEL_BLUE |
fb7d64
+					  R300_OUT_FMT_C1_SEL_GREEN |
fb7d64
+					  R300_OUT_FMT_C2_SEL_RED |
fb7d64
+					  R300_OUT_FMT_C3_SEL_ALPHA));
fb7d64
+	OUT_ACCEL_REG(R300_US_OUT_FMT_3, (R300_OUT_FMT_UNUSED |
fb7d64
+					  R300_OUT_FMT_C0_SEL_BLUE |
fb7d64
+					  R300_OUT_FMT_C1_SEL_GREEN |
fb7d64
+					  R300_OUT_FMT_C2_SEL_RED |
fb7d64
+					  R300_OUT_FMT_C3_SEL_ALPHA));
fb7d64
+	OUT_ACCEL_REG(R300_US_OUT_FMT_0, (R300_OUT_FMT_C4_10 |
fb7d64
+					  R300_OUT_FMT_C0_SEL_BLUE |
fb7d64
+					  R300_OUT_FMT_C1_SEL_GREEN |
fb7d64
+					  R300_OUT_FMT_C2_SEL_RED |
fb7d64
+					  R300_OUT_FMT_C3_SEL_ALPHA));
fb7d64
 	FINISH_ACCEL();
fb7d64
 
fb7d64
-	BEGIN_ACCEL(2);
fb7d64
-	OUT_ACCEL_REG(R300_RS_INST_COUNT, 0xC0);
fb7d64
-	OUT_ACCEL_REG(R300_RS_INST_0, 0x8);
fb7d64
-	FINISH_ACCEL();
fb7d64
 
fb7d64
 	BEGIN_ACCEL(3);
fb7d64
-	OUT_ACCEL_REG(R300_FG_DEPTH_SRC, 0x0);
fb7d64
-	OUT_ACCEL_REG(R300_FG_FOG_BLEND, 0x0);
fb7d64
-	OUT_ACCEL_REG(R300_FG_ALPHA_FUNC, 0x0);
fb7d64
+	OUT_ACCEL_REG(R300_FG_DEPTH_SRC, 0);
fb7d64
+	OUT_ACCEL_REG(R300_FG_FOG_BLEND, 0);
fb7d64
+	OUT_ACCEL_REG(R300_FG_ALPHA_FUNC, 0);
fb7d64
 	FINISH_ACCEL();
fb7d64
 
fb7d64
 	BEGIN_ACCEL(12);
fb7d64
-	OUT_ACCEL_REG(R300_RB3D_ZSTENCILCNTL, 0x0);
fb7d64
-	OUT_ACCEL_REG(R300_RB3D_ZCACHE_CTLSTAT, 0x3);
fb7d64
-	OUT_ACCEL_REG(R300_RB3D_BW_CNTL, 0x0);
fb7d64
-	OUT_ACCEL_REG(R300_RB3D_ZCNTL, 0x0);
fb7d64
-	OUT_ACCEL_REG(R300_RB3D_ZTOP, 0x0);
fb7d64
-	OUT_ACCEL_REG(R300_RB3D_ROPCNTL, 0x0);
fb7d64
-
fb7d64
-	OUT_ACCEL_REG(R300_RB3D_AARESOLVE_CTL, 0x0);
fb7d64
-	OUT_ACCEL_REG(R300_RB3D_COLOR_CHANNEL_MASK, 0xf);
fb7d64
-	OUT_ACCEL_REG(R300_RB3D_DSTCACHE_CTLSTAT, 0xA);
fb7d64
-	OUT_ACCEL_REG(R300_RB3D_CCTL, 0x0);
fb7d64
-	OUT_ACCEL_REG(R300_RB3D_DITHER_CTL, 0x0);
fb7d64
-	OUT_ACCEL_REG(R300_RB3D_DSTCACHE_CTLSTAT, 0xA);
fb7d64
+	OUT_ACCEL_REG(R300_RB3D_ZSTENCILCNTL, 0);
fb7d64
+	OUT_ACCEL_REG(R300_RB3D_ZCACHE_CTLSTAT, R300_ZC_FLUSH | R300_ZC_FREE);
fb7d64
+	OUT_ACCEL_REG(R300_RB3D_BW_CNTL, 0);
fb7d64
+	OUT_ACCEL_REG(R300_RB3D_ZCNTL, 0);
fb7d64
+	OUT_ACCEL_REG(R300_RB3D_ZTOP, 0);
fb7d64
+	OUT_ACCEL_REG(R300_RB3D_ROPCNTL, 0);
fb7d64
+
fb7d64
+	OUT_ACCEL_REG(R300_RB3D_AARESOLVE_CTL, 0);
fb7d64
+	OUT_ACCEL_REG(R300_RB3D_COLOR_CHANNEL_MASK, (R300_BLUE_MASK_EN |
fb7d64
+						     R300_GREEN_MASK_EN |
fb7d64
+						     R300_RED_MASK_EN |
fb7d64
+						     R300_ALPHA_MASK_EN));
fb7d64
+	OUT_ACCEL_REG(R300_RB3D_DSTCACHE_CTLSTAT, R300_DC_FLUSH_3D | R300_DC_FREE_3D);
fb7d64
+	OUT_ACCEL_REG(R300_RB3D_CCTL, 0);
fb7d64
+	OUT_ACCEL_REG(R300_RB3D_DITHER_CTL, 0);
fb7d64
+	OUT_ACCEL_REG(R300_RB3D_DSTCACHE_CTLSTAT, R300_DC_FLUSH_3D | R300_DC_FREE_3D);
fb7d64
 	FINISH_ACCEL();
fb7d64
 
fb7d64
 	BEGIN_ACCEL(7);
fb7d64
 	OUT_ACCEL_REG(R300_SC_EDGERULE, 0xA5294A5);
fb7d64
-	OUT_ACCEL_REG(R300_SC_SCISSOR0, 0x0);
fb7d64
-	OUT_ACCEL_REG(R300_SC_SCISSOR1, 0x3ffffff);
fb7d64
-	OUT_ACCEL_REG(R300_SC_CLIP_0_A, 0x880440);
fb7d64
-	OUT_ACCEL_REG(R300_SC_CLIP_0_B, 0xff0ff0);
fb7d64
+	OUT_ACCEL_REG(R300_SC_SCISSOR0, ((0 << R300_SCISSOR_X_SHIFT) |
fb7d64
+					 (0 << R300_SCISSOR_Y_SHIFT)));
fb7d64
+	OUT_ACCEL_REG(R300_SC_SCISSOR1, ((8191 << R300_SCISSOR_X_SHIFT) |
fb7d64
+					 (8191 << R300_SCISSOR_Y_SHIFT)));
fb7d64
+
fb7d64
+	if (IS_R300_VARIANT || (info->ChipFamily == CHIP_FAMILY_RS690)) {
fb7d64
+	    OUT_ACCEL_REG(R300_SC_CLIP_0_A, ((1088 << R300_CLIP_X_SHIFT) |
fb7d64
+					     (1088 << R300_CLIP_Y_SHIFT)));
fb7d64
+	    OUT_ACCEL_REG(R300_SC_CLIP_0_B, ((4080 << R300_CLIP_X_SHIFT) |
fb7d64
+					     (2040 << R300_CLIP_Y_SHIFT)));
fb7d64
+	} else {
fb7d64
+	    OUT_ACCEL_REG(R300_SC_CLIP_0_A, ((0 << R300_CLIP_X_SHIFT) |
fb7d64
+					     (0 << R300_CLIP_Y_SHIFT)));
fb7d64
+	    OUT_ACCEL_REG(R300_SC_CLIP_0_B, ((4080 << R300_CLIP_X_SHIFT) |
fb7d64
+					     (2040 << R300_CLIP_Y_SHIFT)));
fb7d64
+	}
fb7d64
 	OUT_ACCEL_REG(R300_SC_CLIP_RULE, 0xAAAA);
fb7d64
 	OUT_ACCEL_REG(R300_SC_SCREENDOOR, 0xffffff);
fb7d64
 	FINISH_ACCEL();
fb7d64
-    } else if ((info->ChipFamily == CHIP_FAMILY_RV250) || 
fb7d64
-	       (info->ChipFamily == CHIP_FAMILY_RV280) || 
fb7d64
-	       (info->ChipFamily == CHIP_FAMILY_RS300) || 
fb7d64
+    } else if ((info->ChipFamily == CHIP_FAMILY_RV250) ||
fb7d64
+	       (info->ChipFamily == CHIP_FAMILY_RV280) ||
fb7d64
+	       (info->ChipFamily == CHIP_FAMILY_RS300) ||
fb7d64
 	       (info->ChipFamily == CHIP_FAMILY_R200)) {
fb7d64
 
fb7d64
 	BEGIN_ACCEL(7);
fb7d64
-        if (info->ChipFamily == CHIP_FAMILY_RS300) {
fb7d64
-            OUT_ACCEL_REG(R200_SE_VAP_CNTL_STATUS, RADEON_TCL_BYPASS);
fb7d64
-        } else {
fb7d64
-            OUT_ACCEL_REG(R200_SE_VAP_CNTL_STATUS, 0);
fb7d64
-        }
fb7d64
+	if (info->ChipFamily == CHIP_FAMILY_RS300) {
fb7d64
+	    OUT_ACCEL_REG(R200_SE_VAP_CNTL_STATUS, RADEON_TCL_BYPASS);
fb7d64
+	} else {
fb7d64
+	    OUT_ACCEL_REG(R200_SE_VAP_CNTL_STATUS, 0);
fb7d64
+	}
fb7d64
 	OUT_ACCEL_REG(R200_PP_CNTL_X, 0);
fb7d64
 	OUT_ACCEL_REG(R200_PP_TXMULTI_CTL_0, 0);
fb7d64
 	OUT_ACCEL_REG(R200_SE_VTX_STATE_CNTL, 0);
fb7d64
@@ -199,11 +214,11 @@ static void FUNC_NAME(RADEONInit3DEngine)(ScrnInfoPtr pScrn)
fb7d64
 	FINISH_ACCEL();
fb7d64
     } else {
fb7d64
 	BEGIN_ACCEL(2);
fb7d64
-        if ((info->ChipFamily == CHIP_FAMILY_RADEON) ||
fb7d64
-            (info->ChipFamily == CHIP_FAMILY_RV200))
fb7d64
-            OUT_ACCEL_REG(RADEON_SE_CNTL_STATUS, 0);
fb7d64
-        else
fb7d64
-            OUT_ACCEL_REG(RADEON_SE_CNTL_STATUS, RADEON_TCL_BYPASS);
fb7d64
+	if ((info->ChipFamily == CHIP_FAMILY_RADEON) ||
fb7d64
+	    (info->ChipFamily == CHIP_FAMILY_RV200))
fb7d64
+	    OUT_ACCEL_REG(RADEON_SE_CNTL_STATUS, 0);
fb7d64
+	else
fb7d64
+	    OUT_ACCEL_REG(RADEON_SE_CNTL_STATUS, RADEON_TCL_BYPASS);
fb7d64
 	OUT_ACCEL_REG(RADEON_SE_COORD_FMT,
fb7d64
 	    RADEON_VTX_XY_PRE_MULT_1_OVER_W0 |
fb7d64
 	    RADEON_VTX_ST0_NONPARAMETRIC |
fb7d64
@@ -217,12 +232,12 @@ static void FUNC_NAME(RADEONInit3DEngine)(ScrnInfoPtr pScrn)
fb7d64
     OUT_ACCEL_REG(RADEON_RE_WIDTH_HEIGHT, 0x07ff07ff);
fb7d64
     OUT_ACCEL_REG(RADEON_AUX_SC_CNTL, 0);
fb7d64
     OUT_ACCEL_REG(RADEON_RB3D_PLANEMASK, 0xffffffff);
fb7d64
-    OUT_ACCEL_REG(RADEON_SE_CNTL, RADEON_DIFFUSE_SHADE_GOURAUD |
fb7d64
-				  RADEON_BFACE_SOLID | 
fb7d64
-				  RADEON_FFACE_SOLID |
fb7d64
-				  RADEON_VTX_PIX_CENTER_OGL |
fb7d64
-				  RADEON_ROUND_MODE_ROUND |
fb7d64
-				  RADEON_ROUND_PREC_4TH_PIX);
fb7d64
+    OUT_ACCEL_REG(RADEON_SE_CNTL, (RADEON_DIFFUSE_SHADE_GOURAUD |
fb7d64
+				   RADEON_BFACE_SOLID |
fb7d64
+				   RADEON_FFACE_SOLID |
fb7d64
+				   RADEON_VTX_PIX_CENTER_OGL |
fb7d64
+				   RADEON_ROUND_MODE_ROUND |
fb7d64
+				   RADEON_ROUND_PREC_4TH_PIX));
fb7d64
     FINISH_ACCEL();
fb7d64
 }
fb7d64
 
fb7d64
diff --git a/src/radeon_driver.c b/src/radeon_driver.c
fb7d64
index 9c5fce6..5cf8d51 100644
fb7d64
--- a/src/radeon_driver.c
fb7d64
+++ b/src/radeon_driver.c
fb7d64
@@ -3485,7 +3485,7 @@ Bool RADEONScreenInit(int scrnIndex, ScreenPtr pScreen,
fb7d64
     RADEONDGAInit(pScreen);
fb7d64
 
fb7d64
     /* Init Xv */
fb7d64
-    if (!IS_AVIVO_VARIANT) {
fb7d64
+    if (info->ChipFamily < CHIP_FAMILY_R600) {
fb7d64
 	xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG,
fb7d64
 		       "Initializing Xv\n");
fb7d64
 	RADEONInitVideo(pScreen);
fb7d64
@@ -4906,6 +4906,17 @@ Bool RADEONEnterVT(int scrnIndex, int flags)
fb7d64
     /* Makes sure the engine is idle before doing anything */
fb7d64
     RADEONWaitForIdleMMIO(pScrn);
fb7d64
 
fb7d64
+    if (info->IsMobility && !IS_AVIVO_VARIANT) {
fb7d64
+        if (xf86ReturnOptValBool(info->Options, OPTION_DYNAMIC_CLOCKS, FALSE)) {
fb7d64
+	    RADEONSetDynamicClock(pScrn, 1);
fb7d64
+        } else {
fb7d64
+	    RADEONSetDynamicClock(pScrn, 0);
fb7d64
+        }
fb7d64
+    }
fb7d64
+
fb7d64
+    if (IS_R300_VARIANT || IS_RV100_VARIANT)
fb7d64
+	RADEONForceSomeClocks(pScrn);
fb7d64
+
fb7d64
     pScrn->vtSema = TRUE;
fb7d64
     for (i = 0; i < xf86_config->num_crtc; i++) {
fb7d64
 	xf86CrtcPtr	crtc = xf86_config->crtc[i];
fb7d64
diff --git a/src/radeon_exa.c b/src/radeon_exa.c
fb7d64
index 3b0c734..4ea451d 100644
fb7d64
--- a/src/radeon_exa.c
fb7d64
+++ b/src/radeon_exa.c
fb7d64
@@ -120,8 +120,6 @@ RADEONPow2(int num)
fb7d64
     return pot;
fb7d64
 }
fb7d64
 
fb7d64
-
fb7d64
-
fb7d64
 static __inline__ CARD32 F_TO_DW(float val)
fb7d64
 {
fb7d64
     union {
fb7d64
diff --git a/src/radeon_exa_funcs.c b/src/radeon_exa_funcs.c
fb7d64
index 20b96a5..10221c0 100644
fb7d64
--- a/src/radeon_exa_funcs.c
fb7d64
+++ b/src/radeon_exa_funcs.c
fb7d64
@@ -533,11 +533,11 @@ Bool FUNC_NAME(RADEONDrawInit)(ScreenPtr pScreen)
fb7d64
 
fb7d64
 #ifdef RENDER
fb7d64
     if (info->RenderAccel) {
fb7d64
-	if ((info->ChipFamily >= CHIP_FAMILY_RV515) ||
fb7d64
+	if ((info->ChipFamily >= CHIP_FAMILY_R600) ||
fb7d64
 	    (info->ChipFamily == CHIP_FAMILY_RS400))
fb7d64
 		xf86DrvMsg(pScrn->scrnIndex, X_INFO, "Render acceleration "
fb7d64
 			       "unsupported on XPRESS, R500 and newer cards.\n");
fb7d64
-	else if (IS_R300_VARIANT) {
fb7d64
+	else if (IS_R300_VARIANT || (IS_AVIVO_VARIANT && info->ChipFamily <= CHIP_FAMILY_RS690)) {
fb7d64
 		xf86DrvMsg(pScrn->scrnIndex, X_INFO, "Render acceleration "
fb7d64
 			       "enabled for R300 type cards.\n");
fb7d64
 		info->exa->CheckComposite = R300CheckComposite;
fb7d64
diff --git a/src/radeon_exa_render.c b/src/radeon_exa_render.c
fb7d64
index 6003587..b00c013 100644
fb7d64
--- a/src/radeon_exa_render.c
fb7d64
+++ b/src/radeon_exa_render.c
fb7d64
@@ -937,6 +937,7 @@ static Bool FUNC_NAME(R300PrepareComposite)(int op, PicturePtr pSrcPicture,
fb7d64
     CARD32 txenable, colorpitch;
fb7d64
     CARD32 blendcntl;
fb7d64
     int pixel_shift;
fb7d64
+    int has_tcl = (info->ChipFamily != CHIP_FAMILY_RS690 && info->ChipFamily != CHIP_FAMILY_RS400);
fb7d64
     ACCEL_PREAMBLE();
fb7d64
 
fb7d64
     TRACE;
fb7d64
@@ -975,22 +976,216 @@ static Bool FUNC_NAME(R300PrepareComposite)(int op, PicturePtr pSrcPicture,
fb7d64
 
fb7d64
     RADEON_SWITCH_TO_3D();
fb7d64
 
fb7d64
-    /* setup pixel shader */
fb7d64
-    BEGIN_ACCEL(12);
fb7d64
-    OUT_ACCEL_REG(R300_US_CONFIG, 0x8);
fb7d64
-    OUT_ACCEL_REG(R300_US_PIXSIZE, 0x0);
fb7d64
-    OUT_ACCEL_REG(R300_US_CODE_OFFSET, 0x40040);
fb7d64
-    OUT_ACCEL_REG(R300_US_CODE_ADDR_0, 0x0);
fb7d64
-    OUT_ACCEL_REG(R300_US_CODE_ADDR_1, 0x0);
fb7d64
-    OUT_ACCEL_REG(R300_US_CODE_ADDR_2, 0x0);
fb7d64
-    OUT_ACCEL_REG(R300_US_CODE_ADDR_3, 0x400000);
fb7d64
-    OUT_ACCEL_REG(R300_US_TEX_INST_0, 0x8000);
fb7d64
-    OUT_ACCEL_REG(R300_US_ALU_RGB_ADDR_0, 0x1f800000);
fb7d64
-    OUT_ACCEL_REG(R300_US_ALU_RGB_INST_0, 0x50a80);
fb7d64
-    OUT_ACCEL_REG(R300_US_ALU_ALPHA_ADDR_0, 0x1800000);
fb7d64
-    OUT_ACCEL_REG(R300_US_ALU_ALPHA_INST_0, 0x00040889);
fb7d64
+    /* setup the VAP */
fb7d64
+
fb7d64
+    if (has_tcl) {
fb7d64
+	BEGIN_ACCEL(28);
fb7d64
+	OUT_ACCEL_REG(R300_VAP_CNTL_STATUS, 0);
fb7d64
+	OUT_ACCEL_REG(R300_VAP_PVS_STATE_FLUSH_REG, 0);
fb7d64
+	OUT_ACCEL_REG(R300_VAP_CNTL, ((6 << R300_PVS_NUM_SLOTS_SHIFT) |
fb7d64
+				      (5 << R300_PVS_NUM_CNTLRS_SHIFT) |
fb7d64
+				      (4 << R300_PVS_NUM_FPUS_SHIFT) |
fb7d64
+				      (12 << R300_VF_MAX_VTX_NUM_SHIFT)));
fb7d64
+    } else {
fb7d64
+	BEGIN_ACCEL(10);
fb7d64
+	OUT_ACCEL_REG(R300_VAP_CNTL_STATUS, R300_PVS_BYPASS);
fb7d64
+	OUT_ACCEL_REG(R300_VAP_CNTL, ((10 << R300_PVS_NUM_SLOTS_SHIFT) |
fb7d64
+				      (5 << R300_PVS_NUM_CNTLRS_SHIFT) |
fb7d64
+				      (4 << R300_PVS_NUM_FPUS_SHIFT) |
fb7d64
+				      (5 << R300_VF_MAX_VTX_NUM_SHIFT)));
fb7d64
+    }
fb7d64
+
fb7d64
+    OUT_ACCEL_REG(R300_VAP_VTE_CNTL, R300_VTX_XY_FMT | R300_VTX_Z_FMT);
fb7d64
+    OUT_ACCEL_REG(R300_VAP_PSC_SGN_NORM_CNTL, 0);
fb7d64
+
fb7d64
+    if (has_tcl) {
fb7d64
+	OUT_ACCEL_REG(R300_VAP_PROG_STREAM_CNTL_0,
fb7d64
+		      ((R300_DATA_TYPE_FLOAT_2 << R300_DATA_TYPE_0_SHIFT) |
fb7d64
+		       (0 << R300_SKIP_DWORDS_0_SHIFT) |
fb7d64
+		       (0 << R300_DST_VEC_LOC_0_SHIFT) |
fb7d64
+		       R300_SIGNED_0 |
fb7d64
+		       (R300_DATA_TYPE_FLOAT_2 << R300_DATA_TYPE_1_SHIFT) |
fb7d64
+		       (0 << R300_SKIP_DWORDS_1_SHIFT) |
fb7d64
+		       (10 << R300_DST_VEC_LOC_1_SHIFT) |
fb7d64
+		       R300_SIGNED_1));
fb7d64
+	OUT_ACCEL_REG(R300_VAP_PROG_STREAM_CNTL_1,
fb7d64
+		      ((R300_DATA_TYPE_FLOAT_2 << R300_DATA_TYPE_2_SHIFT) |
fb7d64
+		       (0 << R300_SKIP_DWORDS_2_SHIFT) |
fb7d64
+		       (11 << R300_DST_VEC_LOC_2_SHIFT) |
fb7d64
+		       R300_LAST_VEC_2 |
fb7d64
+		       R300_SIGNED_2));
fb7d64
+	OUT_ACCEL_REG(R300_VAP_PROG_STREAM_CNTL_EXT_0,
fb7d64
+		      ((R300_SWIZZLE_SELECT_X << R300_SWIZZLE_SELECT_X_0_SHIFT) |
fb7d64
+		       (R300_SWIZZLE_SELECT_Y << R300_SWIZZLE_SELECT_Y_0_SHIFT) |
fb7d64
+		       (R300_SWIZZLE_SELECT_Z << R300_SWIZZLE_SELECT_Z_0_SHIFT) |
fb7d64
+		       (R300_SWIZZLE_SELECT_W << R300_SWIZZLE_SELECT_W_0_SHIFT) |
fb7d64
+		       ((R300_WRITE_ENA_X | R300_WRITE_ENA_Y | R300_WRITE_ENA_Z | R300_WRITE_ENA_W)
fb7d64
+			<< R300_WRITE_ENA_0_SHIFT) |
fb7d64
+		       (R300_SWIZZLE_SELECT_X << R300_SWIZZLE_SELECT_X_1_SHIFT) |
fb7d64
+		       (R300_SWIZZLE_SELECT_Y << R300_SWIZZLE_SELECT_Y_1_SHIFT) |
fb7d64
+		       (R300_SWIZZLE_SELECT_Z << R300_SWIZZLE_SELECT_Z_1_SHIFT) |
fb7d64
+		       (R300_SWIZZLE_SELECT_W << R300_SWIZZLE_SELECT_W_1_SHIFT) |
fb7d64
+		       ((R300_WRITE_ENA_X | R300_WRITE_ENA_Y | R300_WRITE_ENA_Z | R300_WRITE_ENA_W)
fb7d64
+			<< R300_WRITE_ENA_1_SHIFT)));
fb7d64
+	OUT_ACCEL_REG(R300_VAP_PROG_STREAM_CNTL_EXT_1,
fb7d64
+		      ((R300_SWIZZLE_SELECT_X << R300_SWIZZLE_SELECT_X_2_SHIFT) |
fb7d64
+		       (R300_SWIZZLE_SELECT_Y << R300_SWIZZLE_SELECT_Y_2_SHIFT) |
fb7d64
+		       (R300_SWIZZLE_SELECT_Z << R300_SWIZZLE_SELECT_Z_2_SHIFT) |
fb7d64
+		       (R300_SWIZZLE_SELECT_W << R300_SWIZZLE_SELECT_W_2_SHIFT) |
fb7d64
+		       ((R300_WRITE_ENA_X | R300_WRITE_ENA_Y | R300_WRITE_ENA_Z | R300_WRITE_ENA_W)
fb7d64
+			<< R300_WRITE_ENA_2_SHIFT)));
fb7d64
+    } else {
fb7d64
+	OUT_ACCEL_REG(R300_VAP_PROG_STREAM_CNTL_0,
fb7d64
+		      ((R300_DATA_TYPE_FLOAT_2 << R300_DATA_TYPE_0_SHIFT) |
fb7d64
+		       (0 << R300_SKIP_DWORDS_0_SHIFT) |
fb7d64
+		       (0 << R300_DST_VEC_LOC_0_SHIFT) |
fb7d64
+		       R300_SIGNED_0 |
fb7d64
+		       (R300_DATA_TYPE_FLOAT_2 << R300_DATA_TYPE_1_SHIFT) |
fb7d64
+		       (0 << R300_SKIP_DWORDS_1_SHIFT) |
fb7d64
+		       (6 << R300_DST_VEC_LOC_1_SHIFT) |
fb7d64
+		       R300_SIGNED_1));
fb7d64
+	OUT_ACCEL_REG(R300_VAP_PROG_STREAM_CNTL_1,
fb7d64
+		      ((R300_DATA_TYPE_FLOAT_2 << R300_DATA_TYPE_2_SHIFT) |
fb7d64
+		       (0 << R300_SKIP_DWORDS_2_SHIFT) |
fb7d64
+		       (7 << R300_DST_VEC_LOC_2_SHIFT) |
fb7d64
+		       R300_LAST_VEC_2 |
fb7d64
+		       R300_SIGNED_2));
fb7d64
+	OUT_ACCEL_REG(R300_VAP_PROG_STREAM_CNTL_EXT_0,
fb7d64
+		      ((R300_SWIZZLE_SELECT_X << R300_SWIZZLE_SELECT_X_0_SHIFT) |
fb7d64
+		       (R300_SWIZZLE_SELECT_Y << R300_SWIZZLE_SELECT_Y_0_SHIFT) |
fb7d64
+		       (R300_SWIZZLE_SELECT_FP_ZERO << R300_SWIZZLE_SELECT_Z_0_SHIFT) |
fb7d64
+		       (R300_SWIZZLE_SELECT_FP_ONE << R300_SWIZZLE_SELECT_W_0_SHIFT) |
fb7d64
+		       ((R300_WRITE_ENA_X | R300_WRITE_ENA_Y)
fb7d64
+			<< R300_WRITE_ENA_0_SHIFT) |
fb7d64
+		       (R300_SWIZZLE_SELECT_X << R300_SWIZZLE_SELECT_X_1_SHIFT) |
fb7d64
+		       (R300_SWIZZLE_SELECT_Y << R300_SWIZZLE_SELECT_Y_1_SHIFT) |
fb7d64
+		       (R300_SWIZZLE_SELECT_FP_ZERO << R300_SWIZZLE_SELECT_Z_1_SHIFT) |
fb7d64
+		       (R300_SWIZZLE_SELECT_FP_ONE << R300_SWIZZLE_SELECT_W_1_SHIFT) |
fb7d64
+		       ((R300_WRITE_ENA_X | R300_WRITE_ENA_Y)
fb7d64
+			<< R300_WRITE_ENA_1_SHIFT)));
fb7d64
+	OUT_ACCEL_REG(R300_VAP_PROG_STREAM_CNTL_EXT_1,
fb7d64
+		      ((R300_SWIZZLE_SELECT_X << R300_SWIZZLE_SELECT_X_2_SHIFT) |
fb7d64
+		       (R300_SWIZZLE_SELECT_Y << R300_SWIZZLE_SELECT_Y_2_SHIFT) |
fb7d64
+		       (R300_SWIZZLE_SELECT_FP_ZERO << R300_SWIZZLE_SELECT_Z_2_SHIFT) |
fb7d64
+		       (R300_SWIZZLE_SELECT_FP_ONE << R300_SWIZZLE_SELECT_W_2_SHIFT) |
fb7d64
+		       ((R300_WRITE_ENA_X | R300_WRITE_ENA_Y)
fb7d64
+			<< R300_WRITE_ENA_2_SHIFT)));
fb7d64
+    }
fb7d64
+
fb7d64
+    /* setup the vertex shader */
fb7d64
+    if (has_tcl) {
fb7d64
+	OUT_ACCEL_REG(R300_VAP_PVS_CODE_CNTL_0,
fb7d64
+		      ((0 << R300_PVS_FIRST_INST_SHIFT) |
fb7d64
+		       (1 << R300_PVS_XYZW_VALID_INST_SHIFT) |
fb7d64
+		       (1 << R300_PVS_LAST_INST_SHIFT)));
fb7d64
+	OUT_ACCEL_REG(R300_VAP_PVS_CODE_CNTL_1,
fb7d64
+		      (1 << R300_PVS_LAST_VTX_SRC_INST_SHIFT));
fb7d64
+	OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_INDX_REG, 0);
fb7d64
+	OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_DATA_REG,0x00f00203);
fb7d64
+	OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_DATA_REG,0x00d10001);
fb7d64
+	OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_DATA_REG,0x01248001);
fb7d64
+	OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_DATA_REG,0x01248001);
fb7d64
+	OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_DATA_REG,0x00f02203);
fb7d64
+	OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_DATA_REG,0x00d10141);
fb7d64
+	OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_DATA_REG,0x01248141);
fb7d64
+	OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_DATA_REG,0x01248141);
fb7d64
+
fb7d64
+	OUT_ACCEL_REG(R300_VAP_PVS_FLOW_CNTL_OPC, 0);
fb7d64
+
fb7d64
+	OUT_ACCEL_REG(R300_VAP_GB_VERT_CLIP_ADJ, 0x3f800000);
fb7d64
+	OUT_ACCEL_REG(R300_VAP_GB_VERT_DISC_ADJ, 0x3f800000);
fb7d64
+	OUT_ACCEL_REG(R300_VAP_GB_HORZ_CLIP_ADJ, 0x3f800000);
fb7d64
+	OUT_ACCEL_REG(R300_VAP_GB_HORZ_DISC_ADJ, 0x3f800000);
fb7d64
+	OUT_ACCEL_REG(R300_VAP_CLIP_CNTL, R300_CLIP_DISABLE);
fb7d64
+    }
fb7d64
+    OUT_ACCEL_REG(R300_VAP_OUT_VTX_FMT_0, R300_VTX_POS_PRESENT);
fb7d64
+    OUT_ACCEL_REG(R300_VAP_OUT_VTX_FMT_1,
fb7d64
+		  ((2 << R300_TEX_0_COMP_CNT_SHIFT) |
fb7d64
+		   (2 << R300_TEX_1_COMP_CNT_SHIFT)));
fb7d64
+
fb7d64
     FINISH_ACCEL();
fb7d64
 
fb7d64
+    /* setup pixel shader */
fb7d64
+    if (IS_R300_VARIANT || info->ChipFamily == CHIP_FAMILY_RS690) {
fb7d64
+      BEGIN_ACCEL(16);
fb7d64
+      OUT_ACCEL_REG(R300_RS_COUNT,
fb7d64
+		    ((2 << R300_RS_COUNT_IT_COUNT_SHIFT) |
fb7d64
+		     R300_RS_COUNT_HIRES_EN));
fb7d64
+      OUT_ACCEL_REG(R300_RS_IP_0, 0x1610000);
fb7d64
+      OUT_ACCEL_REG(R300_RS_INST_COUNT, R300_TX_OFFSET_RS(6));
fb7d64
+      OUT_ACCEL_REG(R300_RS_INST_0, R300_RS_INST_TEX_CN_WRITE);
fb7d64
+      OUT_ACCEL_REG(R300_US_CONFIG, (0 << R300_NLEVEL_SHIFT) | R300_FIRST_TEX);
fb7d64
+      OUT_ACCEL_REG(R300_US_PIXSIZE, 0);
fb7d64
+      OUT_ACCEL_REG(R300_US_CODE_OFFSET,
fb7d64
+		    (R300_ALU_CODE_OFFSET(0) |
fb7d64
+		     R300_ALU_CODE_SIZE(1) |
fb7d64
+		     R300_TEX_CODE_OFFSET(0) |
fb7d64
+		     R300_TEX_CODE_SIZE(1)));
fb7d64
+      OUT_ACCEL_REG(R300_US_CODE_ADDR_0, 0);
fb7d64
+      OUT_ACCEL_REG(R300_US_CODE_ADDR_1, 0);
fb7d64
+      OUT_ACCEL_REG(R300_US_CODE_ADDR_2, 0);
fb7d64
+      OUT_ACCEL_REG(R300_US_CODE_ADDR_3, 0x400000);
fb7d64
+      OUT_ACCEL_REG(R300_US_TEX_INST_0, 0x8000);
fb7d64
+      OUT_ACCEL_REG(R300_US_ALU_RGB_ADDR_0, 0x1f800000);
fb7d64
+      OUT_ACCEL_REG(R300_US_ALU_RGB_INST_0, 0x50a80);
fb7d64
+      OUT_ACCEL_REG(R300_US_ALU_ALPHA_ADDR_0, 0x1800000);
fb7d64
+      OUT_ACCEL_REG(R300_US_ALU_ALPHA_INST_0, 0x00040889);
fb7d64
+      FINISH_ACCEL();
fb7d64
+    } else {
fb7d64
+      BEGIN_ACCEL(23);
fb7d64
+      OUT_ACCEL_REG(R300_RS_COUNT,
fb7d64
+		    ((2 << R300_RS_COUNT_IT_COUNT_SHIFT) |
fb7d64
+		     R300_RS_COUNT_HIRES_EN));
fb7d64
+      OUT_ACCEL_REG(R500_RS_IP_0, (0 << R500_RS_IP_TEX_PTR_S_SHIFT) | (1 << R500_RS_IP_TEX_PTR_T_SHIFT) |
fb7d64
+		    (R500_RS_IP_PTR_K0 << R500_RS_IP_TEX_PTR_R_SHIFT) | (R500_RS_IP_PTR_K1 << R500_RS_IP_TEX_PTR_Q_SHIFT));
fb7d64
+
fb7d64
+      OUT_ACCEL_REG(R300_RS_INST_COUNT, 0);
fb7d64
+      OUT_ACCEL_REG(R500_RS_INST_0, R500_RS_INST_TEX_CN_WRITE);
fb7d64
+      OUT_ACCEL_REG(R300_US_CONFIG, R500_ZERO_TIMES_ANYTHING_EQUALS_ZERO);
fb7d64
+      OUT_ACCEL_REG(R300_US_PIXSIZE, 0);
fb7d64
+      OUT_ACCEL_REG(R500_US_FC_CTRL, 0);
fb7d64
+      OUT_ACCEL_REG(R500_US_CODE_ADDR, R500_US_CODE_START_ADDR(0) | R500_US_CODE_END_ADDR(1));
fb7d64
+      OUT_ACCEL_REG(R500_US_CODE_RANGE, R500_US_CODE_RANGE_ADDR(0) | R500_US_CODE_RANGE_SIZE(1));
fb7d64
+      OUT_ACCEL_REG(R500_US_CODE_OFFSET, 0);
fb7d64
+      OUT_ACCEL_REG(R500_GA_US_VECTOR_INDEX, 0);
fb7d64
+      // 7807
fb7d64
+      OUT_ACCEL_REG(R500_GA_US_VECTOR_DATA, R500_INST_TYPE_TEX | R500_INST_TEX_SEM_WAIT | 
fb7d64
+		    R500_INST_RGB_WMASK_R | R500_INST_RGB_WMASK_G | R500_INST_RGB_WMASK_B | R500_INST_ALPHA_WMASK);
fb7d64
+      
fb7d64
+      OUT_ACCEL_REG(R500_GA_US_VECTOR_DATA, R500_TEX_ID(0) | R500_TEX_INST_LD | R500_TEX_SEM_ACQUIRE |
fb7d64
+		    R500_TEX_IGNORE_UNCOVERED);
fb7d64
+
fb7d64
+      OUT_ACCEL_REG(R500_GA_US_VECTOR_DATA, R500_TEX_SRC_ADDR(0) | R500_TEX_SRC_S_SWIZ_R | R500_TEX_SRC_T_SWIZ_G |
fb7d64
+		    R500_TEX_DST_ADDR(0) | R500_TEX_DST_R_SWIZ_R | R500_TEX_DST_G_SWIZ_G | R500_TEX_DST_B_SWIZ_B |
fb7d64
+		    R500_TEX_DST_A_SWIZ_A);
fb7d64
+      OUT_ACCEL_REG(R500_GA_US_VECTOR_DATA, 0x00000000); // TEX_ADDR_DXDY
fb7d64
+      OUT_ACCEL_REG(R500_GA_US_VECTOR_DATA, 0x00000000); // mbz
fb7d64
+      OUT_ACCEL_REG(R500_GA_US_VECTOR_DATA, 0x00000000); // mbz
fb7d64
+
fb7d64
+      // 0x78105
fb7d64
+      OUT_ACCEL_REG(R500_GA_US_VECTOR_DATA, R500_INST_TYPE_OUT | R500_INST_TEX_SEM_WAIT | R500_INST_LAST |
fb7d64
+		    R500_INST_RGB_OMASK_R | R500_INST_RGB_OMASK_G | R500_INST_RGB_OMASK_B | R500_INST_ALPHA_OMASK);
fb7d64
+
fb7d64
+      OUT_ACCEL_REG(R500_GA_US_VECTOR_DATA, R500_RGB_ADDR0(0) | R500_RGB_ADDR1(0) | R500_RGB_ADDR1_CONST |
fb7d64
+		    R500_RGB_ADDR2(0) | R500_RGB_ADDR2_CONST | R500_RGB_SRCP_OP_1_MINUS_2RGB0); //0x10040000
fb7d64
+      OUT_ACCEL_REG(R500_GA_US_VECTOR_DATA, R500_ALPHA_ADDR0(0) | R500_ALPHA_ADDR1(0) | R500_ALPHA_ADDR1_CONST |
fb7d64
+		    R500_ALPHA_ADDR2(0) | R500_ALPHA_ADDR2_CONST | R500_ALPHA_SRCP_OP_1_MINUS_2A0); //0x10040000
fb7d64
+
fb7d64
+      OUT_ACCEL_REG(R500_GA_US_VECTOR_DATA,
fb7d64
+		    R500_ALU_RGB_SEL_A_SRC0 |
fb7d64
+		    R500_ALU_RGB_R_SWIZ_A_R | R500_ALU_RGB_G_SWIZ_A_G | R500_ALU_RGB_B_SWIZ_A_B |
fb7d64
+		    R500_ALU_RGB_SEL_B_SRC0 |
fb7d64
+		    R500_ALU_RGB_R_SWIZ_B_1 | R500_ALU_RGB_B_SWIZ_B_1 | R500_ALU_RGB_G_SWIZ_B_1);//0x00db0220
fb7d64
+
fb7d64
+      OUT_ACCEL_REG(R500_GA_US_VECTOR_DATA, R500_ALPHA_OP_MAD | 
fb7d64
+		    R500_ALPHA_SWIZ_A_A | R500_ALPHA_SWIZ_B_1);//0x00c0c000)
fb7d64
+
fb7d64
+      OUT_ACCEL_REG(R500_GA_US_VECTOR_DATA, R500_ALU_RGBA_OP_MAD |
fb7d64
+		    R500_ALU_RGBA_R_SWIZ_0 | R500_ALU_RGBA_G_SWIZ_0 | R500_ALU_RGBA_B_SWIZ_0 |
fb7d64
+		    R500_ALU_RGBA_A_SWIZ_0);//0x20490000
fb7d64
+      FINISH_ACCEL();
fb7d64
+    }
fb7d64
+
fb7d64
     BEGIN_ACCEL(6);
fb7d64
     OUT_ACCEL_REG(R300_TX_INVALTAGS, 0x0);
fb7d64
     OUT_ACCEL_REG(R300_TX_ENABLE, txenable);
fb7d64
@@ -1000,7 +1195,7 @@ static Bool FUNC_NAME(R300PrepareComposite)(int op, PicturePtr pSrcPicture,
fb7d64
 
fb7d64
     blendcntl = RADEONGetBlendCntl(op, pMaskPicture, pDstPicture->format);
fb7d64
     OUT_ACCEL_REG(R300_RB3D_BLENDCNTL, blendcntl);
fb7d64
-    OUT_ACCEL_REG(R300_RB3D_ABLENDCNTL, 0x0);
fb7d64
+    OUT_ACCEL_REG(R300_RB3D_ABLENDCNTL, 0);
fb7d64
 
fb7d64
 #if 0
fb7d64
     /* IN operator: Multiply src by mask components or mask alpha.
fb7d64
@@ -1094,8 +1289,6 @@ static inline void transformPoint(PictTransform *transform, xPointFixed *point)
fb7d64
 }
fb7d64
 #endif
fb7d64
 
fb7d64
-#define xFixedToFloat(f) (((float) (f)) / 65536)
fb7d64
-
fb7d64
 static void FUNC_NAME(RadeonComposite)(PixmapPtr pDst,
fb7d64
 				     int srcX, int srcY,
fb7d64
 				     int maskX, int maskY,
fb7d64
@@ -1103,7 +1296,6 @@ static void FUNC_NAME(RadeonComposite)(PixmapPtr pDst,
fb7d64
 				     int w, int h)
fb7d64
 {
fb7d64
     RINFO_FROM_SCREEN(pDst->drawable.pScreen);
fb7d64
-    int srcXend, srcYend, maskXend, maskYend;
fb7d64
     int vtx_count;
fb7d64
     xPointFixed srcTopLeft, srcTopRight, srcBottomLeft, srcBottomRight;
fb7d64
     xPointFixed maskTopLeft, maskTopRight, maskBottomLeft, maskBottomRight;
fb7d64
@@ -1114,11 +1306,6 @@ static void FUNC_NAME(RadeonComposite)(PixmapPtr pDst,
fb7d64
     /* ErrorF("RadeonComposite (%d,%d) (%d,%d) (%d,%d) (%d,%d)\n",
fb7d64
        srcX, srcY, maskX, maskY,dstX, dstY, w, h); */
fb7d64
 
fb7d64
-    srcXend = srcX + w;
fb7d64
-    srcYend = srcY + h;
fb7d64
-    maskXend = maskX + w;
fb7d64
-    maskYend = maskY + h;
fb7d64
-
fb7d64
     srcTopLeft.x     = IntToxFixed(srcX);
fb7d64
     srcTopLeft.y     = IntToxFixed(srcY);
fb7d64
     srcTopRight.x    = IntToxFixed(srcX + w);
fb7d64
@@ -1152,7 +1339,7 @@ static void FUNC_NAME(RadeonComposite)(PixmapPtr pDst,
fb7d64
 
fb7d64
     vtx_count = VTX_COUNT;
fb7d64
 
fb7d64
-    if (IS_R300_VARIANT) {
fb7d64
+    if (IS_R300_VARIANT || IS_AVIVO_VARIANT) {
fb7d64
 	BEGIN_ACCEL(1);
fb7d64
 	OUT_ACCEL_REG(R300_VAP_VTX_SIZE, vtx_count);
fb7d64
 	FINISH_ACCEL();
fb7d64
@@ -1172,7 +1359,7 @@ static void FUNC_NAME(RadeonComposite)(PixmapPtr pDst,
fb7d64
 		 RADEON_CP_VC_CNTL_VTX_FMT_RADEON_MODE |
fb7d64
 		 (4 << RADEON_CP_VC_CNTL_NUM_SHIFT));
fb7d64
     } else {
fb7d64
-	if (IS_R300_VARIANT)
fb7d64
+	if (IS_R300_VARIANT || IS_AVIVO_VARIANT)
fb7d64
 	    BEGIN_RING(4 * vtx_count + 6);
fb7d64
 	else
fb7d64
 	    BEGIN_RING(4 * vtx_count + 2);
fb7d64
@@ -1185,7 +1372,7 @@ static void FUNC_NAME(RadeonComposite)(PixmapPtr pDst,
fb7d64
     }
fb7d64
 
fb7d64
 #else /* ACCEL_CP */
fb7d64
-    if (IS_R300_VARIANT)
fb7d64
+    if (IS_R300_VARIANT || IS_AVIVO_VARIANT)
fb7d64
 	BEGIN_ACCEL(3 + vtx_count * 4);
fb7d64
     else
fb7d64
 	BEGIN_ACCEL(1 + vtx_count * 4);
fb7d64
@@ -1202,29 +1389,21 @@ static void FUNC_NAME(RadeonComposite)(PixmapPtr pDst,
fb7d64
     }
fb7d64
 #endif
fb7d64
 
fb7d64
-    if (info->texW[0] == 1 && info->texH[0] == 1 &&
fb7d64
-	info->texW[1] == 1 && info->texH[1] == 1) {
fb7d64
-	VTX_OUT(dstX,     dstY,       srcX,     srcY,	  maskX,    maskY);
fb7d64
-	VTX_OUT(dstX,     dstY + h,   srcX,     srcYend,  maskX,    maskYend);
fb7d64
-	VTX_OUT(dstX + w, dstY + h,   srcXend,  srcYend,  maskXend, maskYend);
fb7d64
-	VTX_OUT(dstX + w, dstY,	      srcXend,  srcY,     maskXend, maskY);
fb7d64
-    } else {
fb7d64
-	VTX_OUT((float)dstX,                                      (float)dstY,
fb7d64
-	        xFixedToFloat(srcTopLeft.x) / info->texW[0],      xFixedToFloat(srcTopLeft.y) / info->texH[0],
fb7d64
-	        xFixedToFloat(maskTopLeft.x) / info->texW[1],     xFixedToFloat(maskTopLeft.y) / info->texH[1]);
fb7d64
-	VTX_OUT((float)dstX,                                      (float)(dstY + h),
fb7d64
-	        xFixedToFloat(srcBottomLeft.x) / info->texW[0],   xFixedToFloat(srcBottomLeft.y) / info->texH[0],
fb7d64
-	        xFixedToFloat(maskBottomLeft.x) / info->texW[1],  xFixedToFloat(maskBottomLeft.y) / info->texH[1]);
fb7d64
-	VTX_OUT((float)(dstX + w),                                (float)(dstY + h),
fb7d64
-	        xFixedToFloat(srcBottomRight.x) / info->texW[0],  xFixedToFloat(srcBottomRight.y) / info->texH[0],
fb7d64
-	        xFixedToFloat(maskBottomRight.x) / info->texW[1], xFixedToFloat(maskBottomRight.y) / info->texH[1]);
fb7d64
-	VTX_OUT((float)(dstX + w),                                (float)dstY,
fb7d64
-	        xFixedToFloat(srcTopRight.x) / info->texW[0],     xFixedToFloat(srcTopRight.y) / info->texH[0],
fb7d64
-	        xFixedToFloat(maskTopRight.x) / info->texW[1],    xFixedToFloat(maskTopRight.y) / info->texH[1]);
fb7d64
-    }
fb7d64
-
fb7d64
-    if (IS_R300_VARIANT) {
fb7d64
-	OUT_ACCEL_REG(R300_RB3D_DSTCACHE_CTLSTAT, 0xA);
fb7d64
+    VTX_OUT((float)dstX,                                      (float)dstY,
fb7d64
+	    xFixedToFloat(srcTopLeft.x) / info->texW[0],      xFixedToFloat(srcTopLeft.y) / info->texH[0],
fb7d64
+	    xFixedToFloat(maskTopLeft.x) / info->texW[1],     xFixedToFloat(maskTopLeft.y) / info->texH[1]);
fb7d64
+    VTX_OUT((float)dstX,                                      (float)(dstY + h),
fb7d64
+	    xFixedToFloat(srcBottomLeft.x) / info->texW[0],   xFixedToFloat(srcBottomLeft.y) / info->texH[0],
fb7d64
+	    xFixedToFloat(maskBottomLeft.x) / info->texW[1],  xFixedToFloat(maskBottomLeft.y) / info->texH[1]);
fb7d64
+    VTX_OUT((float)(dstX + w),                                (float)(dstY + h),
fb7d64
+	    xFixedToFloat(srcBottomRight.x) / info->texW[0],  xFixedToFloat(srcBottomRight.y) / info->texH[0],
fb7d64
+	    xFixedToFloat(maskBottomRight.x) / info->texW[1], xFixedToFloat(maskBottomRight.y) / info->texH[1]);
fb7d64
+    VTX_OUT((float)(dstX + w),                                (float)dstY,
fb7d64
+	    xFixedToFloat(srcTopRight.x) / info->texW[0],     xFixedToFloat(srcTopRight.y) / info->texH[0],
fb7d64
+	    xFixedToFloat(maskTopRight.x) / info->texW[1],    xFixedToFloat(maskTopRight.y) / info->texH[1]);
fb7d64
+
fb7d64
+    if (IS_R300_VARIANT || IS_AVIVO_VARIANT) {
fb7d64
+	OUT_ACCEL_REG(R300_RB3D_DSTCACHE_CTLSTAT, R300_DC_FLUSH_3D | R300_DC_FREE_3D);
fb7d64
 	OUT_ACCEL_REG(RADEON_WAIT_UNTIL, RADEON_WAIT_3D_IDLECLEAN);
fb7d64
     }
fb7d64
 
fb7d64
@@ -1237,7 +1416,6 @@ static void FUNC_NAME(RadeonComposite)(PixmapPtr pDst,
fb7d64
     LEAVE_DRAW(0);
fb7d64
 }
fb7d64
 #undef VTX_OUT
fb7d64
-#undef VTX_OUT4
fb7d64
 
fb7d64
 #ifdef ONLY_ONCE
fb7d64
 static void RadeonDoneComposite(PixmapPtr pDst)
fb7d64
@@ -1248,3 +1426,4 @@ static void RadeonDoneComposite(PixmapPtr pDst)
fb7d64
 #endif /* ONLY_ONCE */
fb7d64
 
fb7d64
 #undef ONLY_ONCE
fb7d64
+#undef FUNC_NAME
fb7d64
diff --git a/src/radeon_output.c b/src/radeon_output.c
fb7d64
index aceb3d8..62cc5d4 100644
fb7d64
--- a/src/radeon_output.c
fb7d64
+++ b/src/radeon_output.c
fb7d64
@@ -74,11 +74,12 @@ const RADEONMonitorType MonTypeID[10] = {
fb7d64
   MT_DP
fb7d64
 };
fb7d64
 
fb7d64
-const char *TMDSTypeName[4] = {
fb7d64
+const char *TMDSTypeName[5] = {
fb7d64
   "None",
fb7d64
   "Internal",
fb7d64
   "External",
fb7d64
   "LVTMA",
fb7d64
+  "DDIA"
fb7d64
 };
fb7d64
 
fb7d64
 const char *DACTypeName[4] = {
fb7d64
@@ -393,7 +394,7 @@ void RADEONConnectorFindMonitor(ScrnInfoPtr pScrn, xf86OutputPtr output)
fb7d64
     /* panel is probably busted or not connected */
fb7d64
     if ((radeon_output->MonType == MT_LCD) &&
fb7d64
 	((radeon_output->PanelXRes == 0) || (radeon_output->PanelYRes == 0)))
fb7d64
-	radeon_output->MonType == MT_NONE;
fb7d64
+	radeon_output->MonType = MT_NONE;
fb7d64
 
fb7d64
     if (output->MonInfo) {
fb7d64
 	xf86DrvMsg(pScrn->scrnIndex, X_INFO, "EDID data from the display on output: %s ----------------------\n",
fb7d64
@@ -1754,12 +1755,23 @@ legacy_setup_i2c_bus(int ddc_line)
fb7d64
     i2c.put_data_mask = RADEON_GPIO_EN_0;
fb7d64
     i2c.get_clk_mask = RADEON_GPIO_Y_1;
fb7d64
     i2c.get_data_mask = RADEON_GPIO_Y_0;
fb7d64
-    i2c.mask_clk_reg = ddc_line;
fb7d64
-    i2c.mask_data_reg = ddc_line;
fb7d64
-    i2c.put_clk_reg = ddc_line;
fb7d64
-    i2c.put_data_reg = ddc_line;
fb7d64
-    i2c.get_clk_reg = ddc_line;
fb7d64
-    i2c.get_data_reg = ddc_line;
fb7d64
+    if ((ddc_line == RADEON_LCD_GPIO_MASK) ||
fb7d64
+	(ddc_line == RADEON_MDGPIO_EN_REG)) {
fb7d64
+	i2c.mask_clk_reg = ddc_line;
fb7d64
+	i2c.mask_data_reg = ddc_line;
fb7d64
+	i2c.put_clk_reg = ddc_line;
fb7d64
+	i2c.put_data_reg = ddc_line;
fb7d64
+	i2c.get_clk_reg = ddc_line + 4;
fb7d64
+	i2c.get_data_reg = ddc_line + 4;
fb7d64
+    } else {
fb7d64
+	i2c.mask_clk_reg = ddc_line;
fb7d64
+	i2c.mask_data_reg = ddc_line;
fb7d64
+	i2c.put_clk_reg = ddc_line;
fb7d64
+	i2c.put_data_reg = ddc_line;
fb7d64
+	i2c.get_clk_reg = ddc_line;
fb7d64
+	i2c.get_data_reg = ddc_line;
fb7d64
+    }
fb7d64
+
fb7d64
     if (ddc_line)
fb7d64
 	i2c.valid = TRUE;
fb7d64
     else
fb7d64
diff --git a/src/radeon_probe.h b/src/radeon_probe.h
fb7d64
index a3cf1fc..9c1bdc5 100644
fb7d64
--- a/src/radeon_probe.h
fb7d64
+++ b/src/radeon_probe.h
fb7d64
@@ -103,7 +103,8 @@ typedef enum
fb7d64
     TMDS_NONE    = 0,
fb7d64
     TMDS_INT     = 1,
fb7d64
     TMDS_EXT     = 2,
fb7d64
-    TMDS_LVTMA   = 3
fb7d64
+    TMDS_LVTMA   = 3,
fb7d64
+    TMDS_DDIA    = 4
fb7d64
 } RADEONTmdsType;
fb7d64
 
fb7d64
 typedef enum
fb7d64
diff --git a/src/radeon_reg.h b/src/radeon_reg.h
fb7d64
index 61cdb15..893fca4 100644
fb7d64
--- a/src/radeon_reg.h
fb7d64
+++ b/src/radeon_reg.h
fb7d64
@@ -3819,50 +3819,225 @@
fb7d64
 #define R600_BIOS_7_SCRATCH               0x1740
fb7d64
 
fb7d64
 #define R300_GB_TILE_CONFIG				0x4018
fb7d64
+#       define R300_ENABLE_TILING                       (1 << 1)
fb7d64
+#       define R300_TILE_SIZE_8                         (0 << 4)
fb7d64
+#       define R300_TILE_SIZE_16                        (1 << 4)
fb7d64
+#       define R300_TILE_SIZE_32                        (2 << 4)
fb7d64
+#       define R300_SUBPIXEL_1_12                       (0 << 16)
fb7d64
+#       define R300_SUBPIXEL_1_16                       (1 << 16)
fb7d64
 #define R300_GB_SELECT				        0x401c
fb7d64
 #define R300_GB_ENABLE				        0x4008
fb7d64
 #define R300_GB_AA_CONFIG				0x4020
fb7d64
 #define R300_GB_MSPOS0				        0x4010
fb7d64
+#       define R300_MS_X0_SHIFT                         0
fb7d64
+#       define R300_MS_Y0_SHIFT                         4
fb7d64
+#       define R300_MS_X1_SHIFT                         8
fb7d64
+#       define R300_MS_Y1_SHIFT                         12
fb7d64
+#       define R300_MS_X2_SHIFT                         16
fb7d64
+#       define R300_MS_Y2_SHIFT                         20
fb7d64
+#       define R300_MSBD0_Y_SHIFT                       24
fb7d64
+#       define R300_MSBD0_X_SHIFT                       28
fb7d64
 #define R300_GB_MSPOS1				        0x4014
fb7d64
+#       define R300_MS_X3_SHIFT                         0
fb7d64
+#       define R300_MS_Y3_SHIFT                         4
fb7d64
+#       define R300_MS_X4_SHIFT                         8
fb7d64
+#       define R300_MS_Y4_SHIFT                         12
fb7d64
+#       define R300_MS_X5_SHIFT                         16
fb7d64
+#       define R300_MS_Y5_SHIFT                         20
fb7d64
+#       define R300_MSBD1_SHIFT                         24
fb7d64
 
fb7d64
 #define R300_GA_POLY_MODE				0x4288
fb7d64
+#       define R300_FRONT_PTYPE_POINT                   (0 << 4)
fb7d64
+#       define R300_FRONT_PTYPE_LINE                    (1 << 4)
fb7d64
+#       define R300_FRONT_PTYPE_TRIANGE                 (2 << 4)
fb7d64
+#       define R300_BACK_PTYPE_POINT                    (0 << 7)
fb7d64
+#       define R300_BACK_PTYPE_LINE                     (1 << 7)
fb7d64
+#       define R300_BACK_PTYPE_TRIANGE                  (2 << 7)
fb7d64
 #define R300_GA_ROUND_MODE				0x428c
fb7d64
+#       define R300_GEOMETRY_ROUND_TRUNC                (0 << 0)
fb7d64
+#       define R300_GEOMETRY_ROUND_NEAREST              (1 << 0)
fb7d64
+#       define R300_COLOR_ROUND_TRUNC                   (0 << 2)
fb7d64
+#       define R300_COLOR_ROUND_NEAREST                 (1 << 2)
fb7d64
 #define R300_GA_COLOR_CONTROL			        0x4278
fb7d64
+#       define R300_RGB0_SHADING_SOLID                  (0 << 0)
fb7d64
+#       define R300_RGB0_SHADING_FLAT                   (1 << 0)
fb7d64
+#       define R300_RGB0_SHADING_GOURAUD                (2 << 0)
fb7d64
+#       define R300_ALPHA0_SHADING_SOLID                (0 << 2)
fb7d64
+#       define R300_ALPHA0_SHADING_FLAT                 (1 << 2)
fb7d64
+#       define R300_ALPHA0_SHADING_GOURAUD              (2 << 2)
fb7d64
+#       define R300_RGB1_SHADING_SOLID                  (0 << 4)
fb7d64
+#       define R300_RGB1_SHADING_FLAT                   (1 << 4)
fb7d64
+#       define R300_RGB1_SHADING_GOURAUD                (2 << 4)
fb7d64
+#       define R300_ALPHA1_SHADING_SOLID                (0 << 6)
fb7d64
+#       define R300_ALPHA1_SHADING_FLAT                 (1 << 6)
fb7d64
+#       define R300_ALPHA1_SHADING_GOURAUD              (2 << 6)
fb7d64
+#       define R300_RGB2_SHADING_SOLID                  (0 << 8)
fb7d64
+#       define R300_RGB2_SHADING_FLAT                   (1 << 8)
fb7d64
+#       define R300_RGB2_SHADING_GOURAUD                (2 << 8)
fb7d64
+#       define R300_ALPHA2_SHADING_SOLID                (0 << 10)
fb7d64
+#       define R300_ALPHA2_SHADING_FLAT                 (1 << 10)
fb7d64
+#       define R300_ALPHA2_SHADING_GOURAUD              (2 << 10)
fb7d64
+#       define R300_RGB3_SHADING_SOLID                  (0 << 12)
fb7d64
+#       define R300_RGB3_SHADING_FLAT                   (1 << 12)
fb7d64
+#       define R300_RGB3_SHADING_GOURAUD                (2 << 12)
fb7d64
+#       define R300_ALPHA3_SHADING_SOLID                (0 << 14)
fb7d64
+#       define R300_ALPHA3_SHADING_FLAT                 (1 << 14)
fb7d64
+#       define R300_ALPHA3_SHADING_GOURAUD              (2 << 14)
fb7d64
 #define R300_GA_OFFSET				        0x4290
fb7d64
 
fb7d64
 #define R300_VAP_CNTL_STATUS				0x2140
fb7d64
+#       define R300_PVS_BYPASS                          (1 << 8)
fb7d64
 #define R300_VAP_PVS_STATE_FLUSH_REG		        0x2284
fb7d64
 #define R300_VAP_CNTL				        0x2080
fb7d64
+#       define R300_PVS_NUM_SLOTS_SHIFT                 0
fb7d64
+#       define R300_PVS_NUM_CNTLRS_SHIFT                4
fb7d64
+#       define R300_PVS_NUM_FPUS_SHIFT                  8
fb7d64
+#       define R300_VF_MAX_VTX_NUM_SHIFT                18
fb7d64
+#       define R300_GL_CLIP_SPACE_DEF                   (0 << 22)
fb7d64
+#       define R300_DX_CLIP_SPACE_DEF                   (1 << 22)
fb7d64
 #define R300_VAP_VTE_CNTL				0x20B0
fb7d64
+#       define R300_VPORT_X_SCALE_ENA                   (1 << 0)
fb7d64
+#       define R300_VPORT_X_OFFSET_ENA                  (1 << 1)
fb7d64
+#       define R300_VPORT_Y_SCALE_ENA                   (1 << 2)
fb7d64
+#       define R300_VPORT_Y_OFFSET_ENA                  (1 << 3)
fb7d64
+#       define R300_VPORT_Z_SCALE_ENA                   (1 << 4)
fb7d64
+#       define R300_VPORT_Z_OFFSET_ENA                  (1 << 5)
fb7d64
+#       define R300_VTX_XY_FMT                          (1 << 8)
fb7d64
+#       define R300_VTX_Z_FMT                           (1 << 9)
fb7d64
+#       define R300_VTX_W0_FMT                          (1 << 10)
fb7d64
 #define R300_VAP_PSC_SGN_NORM_CNTL		        0x21DC
fb7d64
 #define R300_VAP_PROG_STREAM_CNTL_0		        0x2150
fb7d64
+#       define R300_DATA_TYPE_0_SHIFT                   0
fb7d64
+#       define R300_DATA_TYPE_FLOAT_1                   0
fb7d64
+#       define R300_DATA_TYPE_FLOAT_2                   1
fb7d64
+#       define R300_DATA_TYPE_FLOAT_3                   2
fb7d64
+#       define R300_DATA_TYPE_FLOAT_4                   3
fb7d64
+#       define R300_DATA_TYPE_BYTE                      4
fb7d64
+#       define R300_DATA_TYPE_D3DCOLOR                  5
fb7d64
+#       define R300_DATA_TYPE_SHORT_2                   6
fb7d64
+#       define R300_DATA_TYPE_SHORT_4                   7
fb7d64
+#       define R300_DATA_TYPE_VECTOR_3_TTT              8
fb7d64
+#       define R300_DATA_TYPE_VECTOR_3_EET              9
fb7d64
+#       define R300_SKIP_DWORDS_0_SHIFT                 4
fb7d64
+#       define R300_DST_VEC_LOC_0_SHIFT                 8
fb7d64
+#       define R300_LAST_VEC_0                          (1 << 13)
fb7d64
+#       define R300_SIGNED_0                            (1 << 14)
fb7d64
+#       define R300_NORMALIZE_0                         (1 << 15)
fb7d64
+#       define R300_DATA_TYPE_1_SHIFT                   16
fb7d64
+#       define R300_SKIP_DWORDS_1_SHIFT                 20
fb7d64
+#       define R300_DST_VEC_LOC_1_SHIFT                 24
fb7d64
+#       define R300_LAST_VEC_1                          (1 << 29)
fb7d64
+#       define R300_SIGNED_1                            (1 << 30)
fb7d64
+#       define R300_NORMALIZE_1                         (1 << 31)
fb7d64
 #define R300_VAP_PROG_STREAM_CNTL_1		        0x2154
fb7d64
+#       define R300_DATA_TYPE_2_SHIFT                   0
fb7d64
+#       define R300_SKIP_DWORDS_2_SHIFT                 4
fb7d64
+#       define R300_DST_VEC_LOC_2_SHIFT                 8
fb7d64
+#       define R300_LAST_VEC_2                          (1 << 13)
fb7d64
+#       define R300_SIGNED_2                            (1 << 14)
fb7d64
+#       define R300_NORMALIZE_2                         (1 << 15)
fb7d64
+#       define R300_DATA_TYPE_3_SHIFT                   16
fb7d64
+#       define R300_SKIP_DWORDS_3_SHIFT                 20
fb7d64
+#       define R300_DST_VEC_LOC_3_SHIFT                 24
fb7d64
+#       define R300_LAST_VEC_3                          (1 << 29)
fb7d64
+#       define R300_SIGNED_3                            (1 << 30)
fb7d64
+#       define R300_NORMALIZE_3                         (1 << 31)
fb7d64
 #define R300_VAP_PROG_STREAM_CNTL_EXT_0	                0x21e0
fb7d64
+#       define R300_SWIZZLE_SELECT_X_0_SHIFT            0
fb7d64
+#       define R300_SWIZZLE_SELECT_Y_0_SHIFT            3
fb7d64
+#       define R300_SWIZZLE_SELECT_Z_0_SHIFT            6
fb7d64
+#       define R300_SWIZZLE_SELECT_W_0_SHIFT            9
fb7d64
+#       define R300_SWIZZLE_SELECT_X                    0
fb7d64
+#       define R300_SWIZZLE_SELECT_Y                    1
fb7d64
+#       define R300_SWIZZLE_SELECT_Z                    2
fb7d64
+#       define R300_SWIZZLE_SELECT_W                    3
fb7d64
+#       define R300_SWIZZLE_SELECT_FP_ZERO              4
fb7d64
+#       define R300_SWIZZLE_SELECT_FP_ONE               5
fb7d64
+#       define R300_WRITE_ENA_0_SHIFT                   12
fb7d64
+#       define R300_WRITE_ENA_X                         1
fb7d64
+#       define R300_WRITE_ENA_Y                         2
fb7d64
+#       define R300_WRITE_ENA_Z                         4
fb7d64
+#       define R300_WRITE_ENA_W                         8
fb7d64
+#       define R300_SWIZZLE_SELECT_X_1_SHIFT            16
fb7d64
+#       define R300_SWIZZLE_SELECT_Y_1_SHIFT            19
fb7d64
+#       define R300_SWIZZLE_SELECT_Z_1_SHIFT            22
fb7d64
+#       define R300_SWIZZLE_SELECT_W_1_SHIFT            25
fb7d64
+#       define R300_WRITE_ENA_1_SHIFT                   28
fb7d64
 #define R300_VAP_PROG_STREAM_CNTL_EXT_1	                0x21e4
fb7d64
+#       define R300_SWIZZLE_SELECT_X_2_SHIFT            0
fb7d64
+#       define R300_SWIZZLE_SELECT_Y_2_SHIFT            3
fb7d64
+#       define R300_SWIZZLE_SELECT_Z_2_SHIFT            6
fb7d64
+#       define R300_SWIZZLE_SELECT_W_2_SHIFT            9
fb7d64
+#       define R300_WRITE_ENA_2_SHIFT                   12
fb7d64
+#       define R300_SWIZZLE_SELECT_X_3_SHIFT            16
fb7d64
+#       define R300_SWIZZLE_SELECT_Y_3_SHIFT            19
fb7d64
+#       define R300_SWIZZLE_SELECT_Z_3_SHIFT            22
fb7d64
+#       define R300_SWIZZLE_SELECT_W_3_SHIFT            25
fb7d64
+#       define R300_WRITE_ENA_3_SHIFT                   28
fb7d64
 #define R300_VAP_PVS_CODE_CNTL_0			0x22D0
fb7d64
+#       define R300_PVS_FIRST_INST_SHIFT                0
fb7d64
+#       define R300_PVS_XYZW_VALID_INST_SHIFT           10
fb7d64
+#       define R300_PVS_LAST_INST_SHIFT                 20
fb7d64
 #define R300_VAP_PVS_CODE_CNTL_1			0x22D8
fb7d64
+#       define R300_PVS_LAST_VTX_SRC_INST_SHIFT         0
fb7d64
 #define R300_VAP_PVS_VECTOR_INDX_REG		        0x2200
fb7d64
 #define R300_VAP_PVS_VECTOR_DATA_REG		        0x2204
fb7d64
 #define R300_VAP_PVS_FLOW_CNTL_OPC		        0x22DC
fb7d64
 #define R300_VAP_OUT_VTX_FMT_0			        0x2090
fb7d64
+#       define R300_VTX_POS_PRESENT                     (1 << 0)
fb7d64
+#       define R300_VTX_COLOR_0_PRESENT                 (1 << 1)
fb7d64
+#       define R300_VTX_COLOR_1_PRESENT                 (1 << 2)
fb7d64
+#       define R300_VTX_COLOR_2_PRESENT                 (1 << 3)
fb7d64
+#       define R300_VTX_COLOR_3_PRESENT                 (1 << 4)
fb7d64
+#       define R300_VTX_PT_SIZE_PRESENT                 (1 << 16)
fb7d64
 #define R300_VAP_OUT_VTX_FMT_1			        0x2094
fb7d64
+#       define R300_TEX_0_COMP_CNT_SHIFT                0
fb7d64
+#       define R300_TEX_1_COMP_CNT_SHIFT                3
fb7d64
+#       define R300_TEX_2_COMP_CNT_SHIFT                6
fb7d64
+#       define R300_TEX_3_COMP_CNT_SHIFT                9
fb7d64
+#       define R300_TEX_4_COMP_CNT_SHIFT                12
fb7d64
+#       define R300_TEX_5_COMP_CNT_SHIFT                15
fb7d64
+#       define R300_TEX_6_COMP_CNT_SHIFT                18
fb7d64
+#       define R300_TEX_7_COMP_CNT_SHIFT                21
fb7d64
 #define R300_VAP_VTX_SIZE				0x20b4
fb7d64
 #define R300_VAP_GB_VERT_CLIP_ADJ		        0x2220
fb7d64
 #define R300_VAP_GB_VERT_DISC_ADJ		        0x2224
fb7d64
 #define R300_VAP_GB_HORZ_CLIP_ADJ		        0x2228
fb7d64
 #define R300_VAP_GB_HORZ_DISC_ADJ		        0x222c
fb7d64
 #define R300_VAP_CLIP_CNTL				0x221c
fb7d64
+#       define R300_UCP_ENA_0                           (1 << 0)
fb7d64
+#       define R300_UCP_ENA_1                           (1 << 1)
fb7d64
+#       define R300_UCP_ENA_2                           (1 << 2)
fb7d64
+#       define R300_UCP_ENA_3                           (1 << 3)
fb7d64
+#       define R300_UCP_ENA_4                           (1 << 4)
fb7d64
+#       define R300_UCP_ENA_5                           (1 << 5)
fb7d64
+#       define R300_PS_UCP_MODE_SHIFT                   14
fb7d64
+#       define R300_CLIP_DISABLE                        (1 << 16)
fb7d64
+#       define R300_UCP_CULL_ONLY_ENA                   (1 << 17)
fb7d64
+#       define R300_BOUNDARY_EDGE_FLAG_ENA              (1 << 18)
fb7d64
 
fb7d64
 #define R300_SU_TEX_WRAP				0x42a0
fb7d64
 #define R300_SU_POLY_OFFSET_ENABLE		        0x42b4
fb7d64
 #define R300_SU_CULL_MODE				0x42b8
fb7d64
+#       define R300_CULL_FRONT                          (1 << 0)
fb7d64
+#       define R300_CULL_BACK                           (1 << 1)
fb7d64
+#       define R300_FACE_POS                            (0 << 2)
fb7d64
+#       define R300_FACE_NEG                            (1 << 2)
fb7d64
 #define R300_SU_DEPTH_SCALE				0x42c0
fb7d64
 #define R300_SU_DEPTH_OFFSET			        0x42c4
fb7d64
 
fb7d64
 #define R300_RS_COUNT				        0x4300
fb7d64
+#	define R300_RS_COUNT_IT_COUNT_SHIFT		0
fb7d64
+#	define R300_RS_COUNT_IC_COUNT_SHIFT		7
fb7d64
+#	define R300_RS_COUNT_HIRES_EN			(1 << 18)
fb7d64
+
fb7d64
 #define R300_RS_IP_0				        0x4310
fb7d64
 #define R300_RS_INST_COUNT				0x4304
fb7d64
+#	define R300_INST_COUNT_RS(x)		        (x << 0)
fb7d64
+#	define R300_RS_W_EN			        (1 << 4)
fb7d64
+#	define R300_TX_OFFSET_RS(x)		        (x << 5)
fb7d64
 #define R300_RS_INST_0				        0x4330
fb7d64
+#       define R300_RS_INST_TEX_CN_WRITE		(1 << 3)
fb7d64
 
fb7d64
 #define R300_TX_INVALTAGS				0x4100
fb7d64
 #define R300_TX_FILTER0_0				0x4400
fb7d64
@@ -3901,6 +4076,8 @@
fb7d64
 #	define R300_TX_FORMAT_A8R8G8B8	    	    0x13     /* no swizzle */
fb7d64
 #	define R300_TX_FORMAT_B8G8_B8G8	    	    0x14     /* no swizzle */
fb7d64
 #	define R300_TX_FORMAT_G8R8_G8B8	    	    0x15     /* no swizzle */
fb7d64
+#	define R300_TX_FORMAT_VYUY422	    	    0x14     /* no swizzle */
fb7d64
+#	define R300_TX_FORMAT_YVYU422	    	    0x15     /* no swizzle */
fb7d64
 #	define R300_TX_FORMAT_X24_Y8	    	    0x1e
fb7d64
 #	define R300_TX_FORMAT_X32	    	    0x1e
fb7d64
 	/* Floating point formats */
fb7d64
@@ -3945,6 +4122,10 @@
fb7d64
 		| (R300_TX_FORMAT_##FMT)				\
fb7d64
 		)
fb7d64
 
fb7d64
+#       define R300_TX_FORMAT_YUV_TO_RGB_CLAMP         (1 << 22)
fb7d64
+#       define R300_TX_FORMAT_YUV_TO_RGB_NO_CLAMP      (2 << 22)
fb7d64
+#       define R300_TX_FORMAT_SWAP_YUV                 (1 << 24)
fb7d64
+
fb7d64
 #define R300_TX_FORMAT2_0				0x4500
fb7d64
 #define R300_TX_OFFSET_0				0x4540
fb7d64
 #       define R300_ENDIAN_SWAP_16_BIT                  (1 << 0)
fb7d64
@@ -3961,9 +4142,53 @@
fb7d64
 #define R300_US_OUT_FMT_2				0x46ac
fb7d64
 #define R300_US_OUT_FMT_3				0x46b0
fb7d64
 #define R300_US_OUT_FMT_0				0x46a4
fb7d64
+#       define R300_OUT_FMT_C4_8                        (0 << 0)
fb7d64
+#       define R300_OUT_FMT_C4_10                       (1 << 0)
fb7d64
+#       define R300_OUT_FMT_C4_10_GAMMA                 (2 << 0)
fb7d64
+#       define R300_OUT_FMT_C_16                        (3 << 0)
fb7d64
+#       define R300_OUT_FMT_C2_16                       (4 << 0)
fb7d64
+#       define R300_OUT_FMT_C4_16                       (5 << 0)
fb7d64
+#       define R300_OUT_FMT_C_16_MPEG                   (6 << 0)
fb7d64
+#       define R300_OUT_FMT_C2_16_MPEG                  (7 << 0)
fb7d64
+#       define R300_OUT_FMT_C2_4                        (8 << 0)
fb7d64
+#       define R300_OUT_FMT_C_3_3_2                     (9 << 0)
fb7d64
+#       define R300_OUT_FMT_C_6_5_6                     (10 << 0)
fb7d64
+#       define R300_OUT_FMT_C_11_11_10                  (11 << 0)
fb7d64
+#       define R300_OUT_FMT_C_10_11_11                  (12 << 0)
fb7d64
+#       define R300_OUT_FMT_C_2_10_10_10                (13 << 0)
fb7d64
+#       define R300_OUT_FMT_UNUSED                      (15 << 0)
fb7d64
+#       define R300_OUT_FMT_C_16_FP                     (16 << 0)
fb7d64
+#       define R300_OUT_FMT_C2_16_FP                    (17 << 0)
fb7d64
+#       define R300_OUT_FMT_C4_16_FP                    (18 << 0)
fb7d64
+#       define R300_OUT_FMT_C_32_FP                     (19 << 0)
fb7d64
+#       define R300_OUT_FMT_C2_32_FP                    (20 << 0)
fb7d64
+#       define R300_OUT_FMT_C4_32_FP                    (21 << 0)
fb7d64
+#       define R300_OUT_FMT_C0_SEL_ALPHA                (0 << 8)
fb7d64
+#       define R300_OUT_FMT_C0_SEL_RED                  (1 << 8)
fb7d64
+#       define R300_OUT_FMT_C0_SEL_GREEN                (2 << 8)
fb7d64
+#       define R300_OUT_FMT_C0_SEL_BLUE                 (3 << 8)
fb7d64
+#       define R300_OUT_FMT_C1_SEL_ALPHA                (0 << 10)
fb7d64
+#       define R300_OUT_FMT_C1_SEL_RED                  (1 << 10)
fb7d64
+#       define R300_OUT_FMT_C1_SEL_GREEN                (2 << 10)
fb7d64
+#       define R300_OUT_FMT_C1_SEL_BLUE                 (3 << 10)
fb7d64
+#       define R300_OUT_FMT_C2_SEL_ALPHA                (0 << 12)
fb7d64
+#       define R300_OUT_FMT_C2_SEL_RED                  (1 << 12)
fb7d64
+#       define R300_OUT_FMT_C2_SEL_GREEN                (2 << 12)
fb7d64
+#       define R300_OUT_FMT_C2_SEL_BLUE                 (3 << 12)
fb7d64
+#       define R300_OUT_FMT_C3_SEL_ALPHA                (0 << 14)
fb7d64
+#       define R300_OUT_FMT_C3_SEL_RED                  (1 << 14)
fb7d64
+#       define R300_OUT_FMT_C3_SEL_GREEN                (2 << 14)
fb7d64
+#       define R300_OUT_FMT_C3_SEL_BLUE                 (3 << 14)
fb7d64
 #define R300_US_CONFIG				        0x4600
fb7d64
+#       define R300_NLEVEL_SHIFT                        0
fb7d64
+#       define R300_FIRST_TEX                           (1 << 3)
fb7d64
+#       define R500_ZERO_TIMES_ANYTHING_EQUALS_ZERO     (1 << 1)
fb7d64
 #define R300_US_PIXSIZE				        0x4604
fb7d64
 #define R300_US_CODE_OFFSET				0x4608
fb7d64
+#       define R300_ALU_CODE_OFFSET(x)                  (x << 0)
fb7d64
+#       define R300_ALU_CODE_SIZE(x)                    (x << 6)
fb7d64
+#       define R300_TEX_CODE_OFFSET(x)                  (x << 13)
fb7d64
+#       define R300_TEX_CODE_SIZE(x)                    (x << 18)
fb7d64
 #define R300_US_CODE_ADDR_0				0x4610
fb7d64
 #define R300_US_CODE_ADDR_1				0x4614
fb7d64
 #define R300_US_CODE_ADDR_2				0x4618
fb7d64
@@ -3979,8 +4204,14 @@
fb7d64
 #define R300_FG_ALPHA_FUNC				0x4bd4
fb7d64
 
fb7d64
 #define R300_RB3D_DSTCACHE_CTLSTAT		        0x4e4c
fb7d64
+#       define R300_DC_FLUSH_3D                         (2 << 0)
fb7d64
+#       define R300_DC_FREE_3D                          (2 << 2)
fb7d64
 #define R300_RB3D_ZCACHE_CTLSTAT			0x4f18
fb7d64
+#       define R300_ZC_FLUSH                            (1 << 0)
fb7d64
+#       define R300_ZC_FREE                             (1 << 1)
fb7d64
 #define R300_WAIT_UNTIL				        0x1720
fb7d64
+#       define R300_WAIT_2D_IDLECLEAN                   (1 << 16)
fb7d64
+#       define R300_WAIT_3D_IDLECLEAN                   (1 << 17)
fb7d64
 #define R300_RB3D_ZSTENCILCNTL			        0x4f04
fb7d64
 #define R300_RB3D_ZCACHE_CTLSTAT		        0x4f18
fb7d64
 #define R300_RB3D_BW_CNTL				0x4f1c
fb7d64
@@ -4009,6 +4240,10 @@
fb7d64
 
fb7d64
 #define R300_RB3D_AARESOLVE_CTL			        0x4e88
fb7d64
 #define R300_RB3D_COLOR_CHANNEL_MASK	                0x4e0c
fb7d64
+#       define R300_BLUE_MASK_EN                        (1 << 0)
fb7d64
+#       define R300_GREEN_MASK_EN                       (1 << 1)
fb7d64
+#       define R300_RED_MASK_EN                         (1 << 2)
fb7d64
+#       define R300_ALPHA_MASK_EN                       (1 << 3)
fb7d64
 #define R300_RB3D_COLOR_CLEAR_VALUE                     0x4e14
fb7d64
 #define R300_RB3D_DSTCACHE_CTLSTAT		        0x4e4c
fb7d64
 #define R300_RB3D_CCTL				        0x4e00
fb7d64
@@ -4017,9 +4252,524 @@
fb7d64
 #define R300_SC_EDGERULE				0x43a8
fb7d64
 #define R300_SC_SCISSOR0				0x43e0
fb7d64
 #define R300_SC_SCISSOR1				0x43e4
fb7d64
+#       define R300_SCISSOR_X_SHIFT                     0
fb7d64
+#       define R300_SCISSOR_Y_SHIFT                     13
fb7d64
 #define R300_SC_CLIP_0_A				0x43b0
fb7d64
 #define R300_SC_CLIP_0_B				0x43b4
fb7d64
+#       define R300_CLIP_X_SHIFT                        0
fb7d64
+#       define R300_CLIP_Y_SHIFT                        13
fb7d64
 #define R300_SC_CLIP_RULE				0x43d0
fb7d64
 #define R300_SC_SCREENDOOR				0x43e8
fb7d64
 
fb7d64
+/* R500 US has to be loaded through an index/data pair */
fb7d64
+#define R500_GA_US_VECTOR_INDEX				0x4250
fb7d64
+#   define R500_US_VECTOR_INDEX(x)			(x << 0)
fb7d64
+#   define R500_US_VECTOR_TYPE_INST			(0 << 16)
fb7d64
+#   define R500_US_VECTOR_TYPE_CONST			(1 << 16)
fb7d64
+#   define R500_US_VECTOR_CLAMP				(1 << 17)
fb7d64
+#define R500_GA_US_VECTOR_DATA				0x4254
fb7d64
+
fb7d64
+/*
fb7d64
+ * The R500 unified shader (US) registers come in banks of 512 each, one
fb7d64
+ * for each instruction slot in the shader.  You can't touch them directly.
fb7d64
+ * R500_US_VECTOR_INDEX() sets the base instruction to modify; successive
fb7d64
+ * writes to R500_GA_US_VECTOR_DATA autoincrement the index after the
fb7d64
+ * instruction is fully specified.
fb7d64
+ */
fb7d64
+#define R500_US_ALU_ALPHA_INST_0			0xa800
fb7d64
+#   define R500_ALPHA_OP_MAD				0
fb7d64
+#   define R500_ALPHA_OP_DP				1
fb7d64
+#   define R500_ALPHA_OP_MIN				2
fb7d64
+#   define R500_ALPHA_OP_MAX				3
fb7d64
+/* #define R500_ALPHA_OP_RESERVED			4 */
fb7d64
+#   define R500_ALPHA_OP_CND				5
fb7d64
+#   define R500_ALPHA_OP_CMP				6
fb7d64
+#   define R500_ALPHA_OP_FRC				7
fb7d64
+#   define R500_ALPHA_OP_EX2				8
fb7d64
+#   define R500_ALPHA_OP_LN2				9
fb7d64
+#   define R500_ALPHA_OP_RCP				10
fb7d64
+#   define R500_ALPHA_OP_RSQ				11
fb7d64
+#   define R500_ALPHA_OP_SIN				12
fb7d64
+#   define R500_ALPHA_OP_COS				13
fb7d64
+#   define R500_ALPHA_OP_MDH				14
fb7d64
+#   define R500_ALPHA_OP_MDV				15
fb7d64
+#   define R500_ALPHA_ADDRD(x)				(x << 4)
fb7d64
+#   define R500_ALPHA_ADDRD_REL				(1 << 11)
fb7d64
+#   define R500_ALPHA_SEL_A_SRC0			(0 << 12)
fb7d64
+#   define R500_ALPHA_SEL_A_SRC1			(1 << 12)
fb7d64
+#   define R500_ALPHA_SEL_A_SRC2			(2 << 12)
fb7d64
+#   define R500_ALPHA_SEL_A_SRCP			(3 << 12)
fb7d64
+#   define R500_ALPHA_SWIZ_A_R				(0 << 14)
fb7d64
+#   define R500_ALPHA_SWIZ_A_G				(1 << 14)
fb7d64
+#   define R500_ALPHA_SWIZ_A_B				(2 << 14)
fb7d64
+#   define R500_ALPHA_SWIZ_A_A				(3 << 14)
fb7d64
+#   define R500_ALPHA_SWIZ_A_0				(4 << 14)
fb7d64
+#   define R500_ALPHA_SWIZ_A_HALF			(5 << 14)
fb7d64
+#   define R500_ALPHA_SWIZ_A_1				(6 << 14)
fb7d64
+/* #define R500_ALPHA_SWIZ_A_UNUSED			(7 << 14) */
fb7d64
+#   define R500_ALPHA_MOD_A_NOP				(0 << 17)
fb7d64
+#   define R500_ALPHA_MOD_A_NEG				(1 << 17)
fb7d64
+#   define R500_ALPHA_MOD_A_ABS				(2 << 17)
fb7d64
+#   define R500_ALPHA_MOD_A_NAB				(3 << 17)
fb7d64
+#   define R500_ALPHA_SEL_B_SRC0			(0 << 19)
fb7d64
+#   define R500_ALPHA_SEL_B_SRC1			(1 << 19)
fb7d64
+#   define R500_ALPHA_SEL_B_SRC2			(2 << 19)
fb7d64
+#   define R500_ALPHA_SEL_B_SRCP			(3 << 19)
fb7d64
+#   define R500_ALPHA_SWIZ_B_R				(0 << 21)
fb7d64
+#   define R500_ALPHA_SWIZ_B_G				(1 << 21)
fb7d64
+#   define R500_ALPHA_SWIZ_B_B				(2 << 21)
fb7d64
+#   define R500_ALPHA_SWIZ_B_A				(3 << 21)
fb7d64
+#   define R500_ALPHA_SWIZ_B_0				(4 << 21)
fb7d64
+#   define R500_ALPHA_SWIZ_B_HALF			(5 << 21)
fb7d64
+#   define R500_ALPHA_SWIZ_B_1				(6 << 21)
fb7d64
+/* #define R500_ALPHA_SWIZ_B_UNUSED			(7 << 21) */
fb7d64
+#   define R500_ALPHA_MOD_B_NOP				(0 << 24)
fb7d64
+#   define R500_ALPHA_MOD_B_NEG				(1 << 24)
fb7d64
+#   define R500_ALPHA_MOD_B_ABS				(2 << 24)
fb7d64
+#   define R500_ALPHA_MOD_B_NAB				(3 << 24)
fb7d64
+#   define R500_ALPHA_OMOD_IDENTITY			(0 << 26)
fb7d64
+#   define R500_ALPHA_OMOD_MUL_2			(1 << 26)
fb7d64
+#   define R500_ALPHA_OMOD_MUL_4			(2 << 26)
fb7d64
+#   define R500_ALPHA_OMOD_MUL_8			(3 << 26)
fb7d64
+#   define R500_ALPHA_OMOD_DIV_2			(4 << 26)
fb7d64
+#   define R500_ALPHA_OMOD_DIV_4			(5 << 26)
fb7d64
+#   define R500_ALPHA_OMOD_DIV_8			(6 << 26)
fb7d64
+#   define R500_ALPHA_OMOD_DISABLE			(7 << 26)
fb7d64
+#   define R500_ALPHA_TARGET(x)				(x << 29)
fb7d64
+#   define R500_ALPHA_W_OMASK				(1 << 31)
fb7d64
+#define R500_US_ALU_ALPHA_ADDR_0			0x9800
fb7d64
+#   define R500_ALPHA_ADDR0(x)				(x << 0)
fb7d64
+#   define R500_ALPHA_ADDR0_CONST			(1 << 8)
fb7d64
+#   define R500_ALPHA_ADDR0_REL				(1 << 9)
fb7d64
+#   define R500_ALPHA_ADDR1(x)				(x << 10)
fb7d64
+#   define R500_ALPHA_ADDR1_CONST			(1 << 18)
fb7d64
+#   define R500_ALPHA_ADDR1_REL				(1 << 19)
fb7d64
+#   define R500_ALPHA_ADDR2(x)				(x << 20)
fb7d64
+#   define R500_ALPHA_ADDR2_CONST			(1 << 28)
fb7d64
+#   define R500_ALPHA_ADDR2_REL				(1 << 29)
fb7d64
+#   define R500_ALPHA_SRCP_OP_1_MINUS_2A0		(0 << 30)
fb7d64
+#   define R500_ALPHA_SRCP_OP_A1_MINUS_A0		(1 << 30)
fb7d64
+#   define R500_ALPHA_SRCP_OP_A1_PLUS_A0		(2 << 30)
fb7d64
+#   define R500_ALPHA_SRCP_OP_1_PLUS_A0			(3 << 30)
fb7d64
+#define R500_US_ALU_RGBA_INST_0				0xb000
fb7d64
+#   define R500_ALU_RGBA_OP_MAD				(0 << 0)
fb7d64
+#   define R500_ALU_RGBA_OP_DP3				(1 << 0)
fb7d64
+#   define R500_ALU_RGBA_OP_DP4				(2 << 0)
fb7d64
+#   define R500_ALU_RGBA_OP_D2A				(3 << 0)
fb7d64
+#   define R500_ALU_RGBA_OP_MIN				(4 << 0)
fb7d64
+#   define R500_ALU_RGBA_OP_MAX				(5 << 0)
fb7d64
+/* #define R500_ALU_RGBA_OP_RESERVED			(6 << 0) */
fb7d64
+#   define R500_ALU_RGBA_OP_CND				(7 << 0)
fb7d64
+#   define R500_ALU_RGBA_OP_CMP				(8 << 0)
fb7d64
+#   define R500_ALU_RGBA_OP_FRC				(9 << 0)
fb7d64
+#   define R500_ALU_RGBA_OP_SOP				(10 << 0)
fb7d64
+#   define R500_ALU_RGBA_OP_MDH				(11 << 0)
fb7d64
+#   define R500_ALU_RGBA_OP_MDV				(12 << 0)
fb7d64
+#   define R500_ALU_RGBA_ADDRD(x)			(x << 4)
fb7d64
+#   define R500_ALU_RGBA_ADDRD_REL			(1 << 11)
fb7d64
+#   define R500_ALU_RGBA_SEL_C_SRC0			(0 << 12)
fb7d64
+#   define R500_ALU_RGBA_SEL_C_SRC1			(1 << 12)
fb7d64
+#   define R500_ALU_RGBA_SEL_C_SRC2			(2 << 12)
fb7d64
+#   define R500_ALU_RGBA_SEL_C_SRCP			(3 << 12)
fb7d64
+#   define R500_ALU_RGBA_R_SWIZ_R			(0 << 14)
fb7d64
+#   define R500_ALU_RGBA_R_SWIZ_G			(1 << 14)
fb7d64
+#   define R500_ALU_RGBA_R_SWIZ_B			(2 << 14)
fb7d64
+#   define R500_ALU_RGBA_R_SWIZ_A			(3 << 14)
fb7d64
+#   define R500_ALU_RGBA_R_SWIZ_0			(4 << 14)
fb7d64
+#   define R500_ALU_RGBA_R_SWIZ_HALF			(5 << 14)
fb7d64
+#   define R500_ALU_RGBA_R_SWIZ_1			(6 << 14)
fb7d64
+/* #define R500_ALU_RGBA_R_SWIZ_UNUSED			(7 << 14) */
fb7d64
+#   define R500_ALU_RGBA_G_SWIZ_R			(0 << 17)
fb7d64
+#   define R500_ALU_RGBA_G_SWIZ_G			(1 << 17)
fb7d64
+#   define R500_ALU_RGBA_G_SWIZ_B			(2 << 17)
fb7d64
+#   define R500_ALU_RGBA_G_SWIZ_A			(3 << 17)
fb7d64
+#   define R500_ALU_RGBA_G_SWIZ_0			(4 << 17)
fb7d64
+#   define R500_ALU_RGBA_G_SWIZ_HALF			(5 << 17)
fb7d64
+#   define R500_ALU_RGBA_G_SWIZ_1			(6 << 17)
fb7d64
+/* #define R500_ALU_RGBA_G_SWIZ_UNUSED			(7 << 17) */
fb7d64
+#   define R500_ALU_RGBA_B_SWIZ_R			(0 << 20)
fb7d64
+#   define R500_ALU_RGBA_B_SWIZ_G			(1 << 20)
fb7d64
+#   define R500_ALU_RGBA_B_SWIZ_B			(2 << 20)
fb7d64
+#   define R500_ALU_RGBA_B_SWIZ_A			(3 << 20)
fb7d64
+#   define R500_ALU_RGBA_B_SWIZ_0			(4 << 20)
fb7d64
+#   define R500_ALU_RGBA_B_SWIZ_HALF			(5 << 20)
fb7d64
+#   define R500_ALU_RGBA_B_SWIZ_1			(6 << 20)
fb7d64
+/* #define R500_ALU_RGBA_B_SWIZ_UNUSED			(7 << 20) */
fb7d64
+#   define R500_ALU_RGBA_MOD_C_NOP			(0 << 23)
fb7d64
+#   define R500_ALU_RGBA_MOD_C_NEG			(1 << 23)
fb7d64
+#   define R500_ALU_RGBA_MOD_C_ABS			(2 << 23)
fb7d64
+#   define R500_ALU_RGBA_MOD_C_NAB			(3 << 23)
fb7d64
+#   define R500_ALU_RGBA_ALPHA_SEL_C_SRC0		(0 << 25)
fb7d64
+#   define R500_ALU_RGBA_ALPHA_SEL_C_SRC1		(1 << 25)
fb7d64
+#   define R500_ALU_RGBA_ALPHA_SEL_C_SRC2		(2 << 25)
fb7d64
+#   define R500_ALU_RGBA_ALPHA_SEL_C_SRCP		(3 << 25)
fb7d64
+#   define R500_ALU_RGBA_A_SWIZ_R			(0 << 27)
fb7d64
+#   define R500_ALU_RGBA_A_SWIZ_G			(1 << 27)
fb7d64
+#   define R500_ALU_RGBA_A_SWIZ_B			(2 << 27)
fb7d64
+#   define R500_ALU_RGBA_A_SWIZ_A			(3 << 27)
fb7d64
+#   define R500_ALU_RGBA_A_SWIZ_0			(4 << 27)
fb7d64
+#   define R500_ALU_RGBA_A_SWIZ_HALF			(5 << 27)
fb7d64
+#   define R500_ALU_RGBA_A_SWIZ_1			(6 << 27)
fb7d64
+/* #define R500_ALU_RGBA_A_SWIZ_UNUSED			(7 << 27) */
fb7d64
+#   define R500_ALU_RGBA_ALPHA_MOD_C_NOP		(0 << 30)
fb7d64
+#   define R500_ALU_RGBA_ALPHA_MOD_C_NEG		(1 << 30)
fb7d64
+#   define R500_ALU_RGBA_ALPHA_MOD_C_ABS		(2 << 30)
fb7d64
+#   define R500_ALU_RGBA_ALPHA_MOD_C_NAB		(3 << 30)
fb7d64
+#define R500_US_ALU_RGB_INST_0				0xa000
fb7d64
+#   define R500_ALU_RGB_SEL_A_SRC0			(0 << 0)
fb7d64
+#   define R500_ALU_RGB_SEL_A_SRC1			(1 << 0)
fb7d64
+#   define R500_ALU_RGB_SEL_A_SRC2			(2 << 0)
fb7d64
+#   define R500_ALU_RGB_SEL_A_SRCP			(3 << 0)
fb7d64
+#   define R500_ALU_RGB_R_SWIZ_A_R			(0 << 2)
fb7d64
+#   define R500_ALU_RGB_R_SWIZ_A_G			(1 << 2)
fb7d64
+#   define R500_ALU_RGB_R_SWIZ_A_B			(2 << 2)
fb7d64
+#   define R500_ALU_RGB_R_SWIZ_A_A			(3 << 2)
fb7d64
+#   define R500_ALU_RGB_R_SWIZ_A_0			(4 << 2)
fb7d64
+#   define R500_ALU_RGB_R_SWIZ_A_HALF			(5 << 2)
fb7d64
+#   define R500_ALU_RGB_R_SWIZ_A_1			(6 << 2)
fb7d64
+/* #define R500_ALU_RGB_R_SWIZ_A_UNUSED			(7 << 2) */
fb7d64
+#   define R500_ALU_RGB_G_SWIZ_A_R			(0 << 5)
fb7d64
+#   define R500_ALU_RGB_G_SWIZ_A_G			(1 << 5)
fb7d64
+#   define R500_ALU_RGB_G_SWIZ_A_B			(2 << 5)
fb7d64
+#   define R500_ALU_RGB_G_SWIZ_A_A			(3 << 5)
fb7d64
+#   define R500_ALU_RGB_G_SWIZ_A_0			(4 << 5)
fb7d64
+#   define R500_ALU_RGB_G_SWIZ_A_HALF			(5 << 5)
fb7d64
+#   define R500_ALU_RGB_G_SWIZ_A_1			(6 << 5)
fb7d64
+/* #define R500_ALU_RGB_G_SWIZ_A_UNUSED			(7 << 5) */
fb7d64
+#   define R500_ALU_RGB_B_SWIZ_A_R			(0 << 8)
fb7d64
+#   define R500_ALU_RGB_B_SWIZ_A_G			(1 << 8)
fb7d64
+#   define R500_ALU_RGB_B_SWIZ_A_B			(2 << 8)
fb7d64
+#   define R500_ALU_RGB_B_SWIZ_A_A			(3 << 8)
fb7d64
+#   define R500_ALU_RGB_B_SWIZ_A_0			(4 << 8)
fb7d64
+#   define R500_ALU_RGB_B_SWIZ_A_HALF			(5 << 8)
fb7d64
+#   define R500_ALU_RGB_B_SWIZ_A_1			(6 << 8)
fb7d64
+/* #define R500_ALU_RGB_B_SWIZ_A_UNUSED			(7 << 8) */
fb7d64
+#   define R500_ALU_RGB_MOD_A_NOP			(0 << 11)
fb7d64
+#   define R500_ALU_RGB_MOD_A_NEG			(1 << 11)
fb7d64
+#   define R500_ALU_RGB_MOD_A_ABS			(2 << 11)
fb7d64
+#   define R500_ALU_RGB_MOD_A_NAB			(3 << 11)
fb7d64
+#   define R500_ALU_RGB_SEL_B_SRC0			(0 << 13)
fb7d64
+#   define R500_ALU_RGB_SEL_B_SRC1			(1 << 13)
fb7d64
+#   define R500_ALU_RGB_SEL_B_SRC2			(2 << 13)
fb7d64
+#   define R500_ALU_RGB_SEL_B_SRCP			(3 << 13)
fb7d64
+#   define R500_ALU_RGB_R_SWIZ_B_R			(0 << 15)
fb7d64
+#   define R500_ALU_RGB_R_SWIZ_B_G			(1 << 15)
fb7d64
+#   define R500_ALU_RGB_R_SWIZ_B_B			(2 << 15)
fb7d64
+#   define R500_ALU_RGB_R_SWIZ_B_A			(3 << 15)
fb7d64
+#   define R500_ALU_RGB_R_SWIZ_B_0			(4 << 15)
fb7d64
+#   define R500_ALU_RGB_R_SWIZ_B_HALF			(5 << 15)
fb7d64
+#   define R500_ALU_RGB_R_SWIZ_B_1			(6 << 15)
fb7d64
+/* #define R500_ALU_RGB_R_SWIZ_B_UNUSED			(7 << 15) */
fb7d64
+#   define R500_ALU_RGB_G_SWIZ_B_R			(0 << 18)
fb7d64
+#   define R500_ALU_RGB_G_SWIZ_B_G			(1 << 18)
fb7d64
+#   define R500_ALU_RGB_G_SWIZ_B_B			(2 << 18)
fb7d64
+#   define R500_ALU_RGB_G_SWIZ_B_A			(3 << 18)
fb7d64
+#   define R500_ALU_RGB_G_SWIZ_B_0			(4 << 18)
fb7d64
+#   define R500_ALU_RGB_G_SWIZ_B_HALF			(5 << 18)
fb7d64
+#   define R500_ALU_RGB_G_SWIZ_B_1			(6 << 18)
fb7d64
+/* #define R500_ALU_RGB_G_SWIZ_B_UNUSED			(7 << 18) */
fb7d64
+#   define R500_ALU_RGB_B_SWIZ_B_R			(0 << 21)
fb7d64
+#   define R500_ALU_RGB_B_SWIZ_B_G			(1 << 21)
fb7d64
+#   define R500_ALU_RGB_B_SWIZ_B_B			(2 << 21)
fb7d64
+#   define R500_ALU_RGB_B_SWIZ_B_A			(3 << 21)
fb7d64
+#   define R500_ALU_RGB_B_SWIZ_B_0			(4 << 21)
fb7d64
+#   define R500_ALU_RGB_B_SWIZ_B_HALF			(5 << 21)
fb7d64
+#   define R500_ALU_RGB_B_SWIZ_B_1			(6 << 21)
fb7d64
+/* #define R500_ALU_RGB_B_SWIZ_B_UNUSED			(7 << 21) */
fb7d64
+#   define R500_ALU_RGB_MOD_B_NOP			(0 << 24)
fb7d64
+#   define R500_ALU_RGB_MOD_B_NEG			(1 << 24)
fb7d64
+#   define R500_ALU_RGB_MOD_B_ABS			(2 << 24)
fb7d64
+#   define R500_ALU_RGB_MOD_B_NAB			(3 << 24)
fb7d64
+#   define R500_ALU_RGB_OMOD_IDENTITY			(0 << 26)
fb7d64
+#   define R500_ALU_RGB_OMOD_MUL_2			(1 << 26)
fb7d64
+#   define R500_ALU_RGB_OMOD_MUL_4			(2 << 26)
fb7d64
+#   define R500_ALU_RGB_OMOD_MUL_8			(3 << 26)
fb7d64
+#   define R500_ALU_RGB_OMOD_DIV_2			(4 << 26)
fb7d64
+#   define R500_ALU_RGB_OMOD_DIV_4			(5 << 26)
fb7d64
+#   define R500_ALU_RGB_OMOD_DIV_8			(6 << 26)
fb7d64
+#   define R500_ALU_RGB_OMOD_DISABLE			(7 << 26)
fb7d64
+#   define R500_ALU_RGB_TARGET(x)			(x << 29)
fb7d64
+#   define R500_ALU_RGB_WMASK				(1 << 31)
fb7d64
+#define R500_US_ALU_RGB_ADDR_0				0x9000
fb7d64
+#   define R500_RGB_ADDR0(x)				(x << 0)
fb7d64
+#   define R500_RGB_ADDR0_CONST				(1 << 8)
fb7d64
+#   define R500_RGB_ADDR0_REL				(1 << 9)
fb7d64
+#   define R500_RGB_ADDR1(x)				(x << 10)
fb7d64
+#   define R500_RGB_ADDR1_CONST				(1 << 18)
fb7d64
+#   define R500_RGB_ADDR1_REL				(1 << 19)
fb7d64
+#   define R500_RGB_ADDR2(x)				(x << 20)
fb7d64
+#   define R500_RGB_ADDR2_CONST				(1 << 28)
fb7d64
+#   define R500_RGB_ADDR2_REL				(1 << 29)
fb7d64
+#   define R500_RGB_SRCP_OP_1_MINUS_2RGB0		(0 << 30)
fb7d64
+#   define R500_RGB_SRCP_OP_RGB1_MINUS_RGB0		(1 << 30)
fb7d64
+#   define R500_RGB_SRCP_OP_RGB1_PLUS_RGB0		(2 << 30)
fb7d64
+#   define R500_RGB_SRCP_OP_1_PLUS_RGB0			(3 << 30)
fb7d64
+#define R500_US_CMN_INST_0				0xb800
fb7d64
+#   define R500_INST_TYPE_ALU				(0 << 0)
fb7d64
+#   define R500_INST_TYPE_OUT				(1 << 0)
fb7d64
+#   define R500_INST_TYPE_FC				(2 << 0)
fb7d64
+#   define R500_INST_TYPE_TEX				(3 << 0)
fb7d64
+#   define R500_INST_TEX_SEM_WAIT			(1 << 2)
fb7d64
+#   define R500_INST_RGB_PRED_SEL_NONE			(0 << 3)
fb7d64
+#   define R500_INST_RGB_PRED_SEL_RGBA			(1 << 3)
fb7d64
+#   define R500_INST_RGB_PRED_SEL_RRRR			(2 << 3)
fb7d64
+#   define R500_INST_RGB_PRED_SEL_GGGG			(3 << 3)
fb7d64
+#   define R500_INST_RGB_PRED_SEL_BBBB			(4 << 3)
fb7d64
+#   define R500_INST_RGB_PRED_SEL_AAAA			(5 << 3)
fb7d64
+#   define R500_INST_RGB_PRED_INV			(1 << 6)
fb7d64
+#   define R500_INST_WRITE_INACTIVE			(1 << 7)
fb7d64
+#   define R500_INST_LAST				(1 << 8)
fb7d64
+#   define R500_INST_NOP				(1 << 9)
fb7d64
+#   define R500_INST_ALU_WAIT				(1 << 10)
fb7d64
+#   define R500_INST_RGB_WMASK_R			(1 << 11)
fb7d64
+#   define R500_INST_RGB_WMASK_G			(1 << 12)
fb7d64
+#   define R500_INST_RGB_WMASK_B			(1 << 13)
fb7d64
+#   define R500_INST_ALPHA_WMASK			(1 << 14)
fb7d64
+#   define R500_INST_RGB_OMASK_R			(1 << 15)
fb7d64
+#   define R500_INST_RGB_OMASK_G			(1 << 16)
fb7d64
+#   define R500_INST_RGB_OMASK_B			(1 << 17)
fb7d64
+#   define R500_INST_ALPHA_OMASK			(1 << 18)
fb7d64
+#   define R500_INST_RGB_CLAMP				(1 << 19)
fb7d64
+#   define R500_INST_ALPHA_CLAMP			(1 << 20)
fb7d64
+#   define R500_INST_ALU_RESULT_SEL			(1 << 21)
fb7d64
+#   define R500_INST_ALPHA_PRED_INV			(1 << 22)
fb7d64
+#   define R500_INST_ALU_RESULT_OP_EQ			(0 << 23)
fb7d64
+#   define R500_INST_ALU_RESULT_OP_LT			(1 << 23)
fb7d64
+#   define R500_INST_ALU_RESULT_OP_GE			(2 << 23)
fb7d64
+#   define R500_INST_ALU_RESULT_OP_NE			(3 << 23)
fb7d64
+#   define R500_INST_ALPHA_PRED_SEL_NONE		(0 << 25)
fb7d64
+#   define R500_INST_ALPHA_PRED_SEL_RGBA		(1 << 25)
fb7d64
+#   define R500_INST_ALPHA_PRED_SEL_RRRR		(2 << 25)
fb7d64
+#   define R500_INST_ALPHA_PRED_SEL_GGGG		(3 << 25)
fb7d64
+#   define R500_INST_ALPHA_PRED_SEL_BBBB		(4 << 25)
fb7d64
+#   define R500_INST_ALPHA_PRED_SEL_AAAA		(5 << 25)
fb7d64
+/* XXX next four are kind of guessed */
fb7d64
+#   define R500_INST_STAT_WE_R				(1 << 28)
fb7d64
+#   define R500_INST_STAT_WE_G				(1 << 29)
fb7d64
+#   define R500_INST_STAT_WE_B				(1 << 30)
fb7d64
+#   define R500_INST_STAT_WE_A				(1 << 31)
fb7d64
+/* note that these are 8 bit lengths, despite the offsets, at least for R500 */
fb7d64
+#define R500_US_CODE_ADDR				0x4630
fb7d64
+#   define R500_US_CODE_START_ADDR(x)			(x << 0)
fb7d64
+#   define R500_US_CODE_END_ADDR(x)			(x << 16)
fb7d64
+#define R500_US_CODE_OFFSET				0x4638
fb7d64
+#   define R500_US_CODE_OFFSET_ADDR(x)			(x << 0)
fb7d64
+#define R500_US_CODE_RANGE				0x4634
fb7d64
+#   define R500_US_CODE_RANGE_ADDR(x)			(x << 0)
fb7d64
+#   define R500_US_CODE_RANGE_SIZE(x)			(x << 16)
fb7d64
+#define R500_US_CONFIG					0x4600
fb7d64
+#   define R500_ZERO_TIMES_ANYTHING_EQUALS_ZERO		(1 << 1)
fb7d64
+#define R500_US_FC_ADDR_0				0xa000
fb7d64
+#   define R500_FC_BOOL_ADDR(x)				(x << 0)
fb7d64
+#   define R500_FC_INT_ADDR(x)				(x << 8)
fb7d64
+#   define R500_FC_JUMP_ADDR(x)				(x << 16)
fb7d64
+#   define R500_FC_JUMP_GLOBAL				(1 << 31)
fb7d64
+#define R500_US_FC_BOOL_CONST				0x4620
fb7d64
+#   define R500_FC_KBOOL(x)				(x)
fb7d64
+#define R500_US_FC_CTRL					0x4624
fb7d64
+#   define R500_FC_TEST_EN				(1 << 30)
fb7d64
+#   define R500_FC_FULL_FC_EN				(1 << 31)
fb7d64
+#define R500_US_FC_INST_0				0x9800
fb7d64
+#   define R500_FC_OP_JUMP				(0 << 0)
fb7d64
+#   define R500_FC_OP_LOOP				(1 << 0)
fb7d64
+#   define R500_FC_OP_ENDLOOP				(2 << 0)
fb7d64
+#   define R500_FC_OP_REP				(3 << 0)
fb7d64
+#   define R500_FC_OP_ENDREP				(4 << 0)
fb7d64
+#   define R500_FC_OP_BREAKLOOP				(5 << 0)
fb7d64
+#   define R500_FC_OP_BREAKREP				(6 << 0)
fb7d64
+#   define R500_FC_OP_CONTINUE				(7 << 0)
fb7d64
+#   define R500_FC_B_ELSE				(1 << 4)
fb7d64
+#   define R500_FC_JUMP_ANY				(1 << 5)
fb7d64
+#   define R500_FC_A_OP_NONE				(0 << 6)
fb7d64
+#   define R500_FC_A_OP_POP				(1 << 6)
fb7d64
+#   define R500_FC_A_OP_PUSH				(2 << 6)
fb7d64
+#   define R500_FC_JUMP_FUNC(x)				(x << 8)
fb7d64
+#   define R500_FC_B_POP_CNT(x)				(x << 16)
fb7d64
+#   define R500_FC_B_OP0_NONE				(0 << 24)
fb7d64
+#   define R500_FC_B_OP0_DECR				(1 << 24)
fb7d64
+#   define R500_FC_B_OP0_INCR				(2 << 24)
fb7d64
+#   define R500_FC_B_OP1_DECR				(0 << 26)
fb7d64
+#   define R500_FC_B_OP1_NONE				(1 << 26)
fb7d64
+#   define R500_FC_B_OP1_INCR				(2 << 26)
fb7d64
+#   define R500_FC_IGNORE_UNCOVERED			(1 << 28)
fb7d64
+#define R500_US_FC_INT_CONST_0				0x4c00
fb7d64
+#   define R500_FC_INT_CONST_KR(x)			(x << 0)
fb7d64
+#   define R500_FC_INT_CONST_KG(x)			(x << 8)
fb7d64
+#   define R500_FC_INT_CONST_KB(x)			(x << 16)
fb7d64
+/* _0 through _15 */
fb7d64
+#define R500_US_FORMAT0_0				0x4640
fb7d64
+#   define R500_FORMAT_TXWIDTH(x)			(x << 0)
fb7d64
+#   define R500_FORMAT_TXHEIGHT(x)			(x << 11)
fb7d64
+#   define R500_FORMAT_TXDEPTH(x)			(x << 22)
fb7d64
+/* _0 through _3 */
fb7d64
+#define R500_US_OUT_FMT_0				0x46a4
fb7d64
+#   define R500_OUT_FMT_C4_8				(0 << 0)
fb7d64
+#   define R500_OUT_FMT_C4_10				(1 << 0)
fb7d64
+#   define R500_OUT_FMT_C4_10_GAMMA			(2 << 0)
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+#   define R500_OUT_FMT_C_16				(3 << 0)
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+#   define R500_OUT_FMT_C2_16				(4 << 0)
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+#   define R500_OUT_FMT_C4_16				(5 << 0)
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+#   define R500_OUT_FMT_C_16_MPEG			(6 << 0)
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+#   define R500_OUT_FMT_C2_16_MPEG			(7 << 0)
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+#   define R500_OUT_FMT_C2_4				(8 << 0)
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+#   define R500_OUT_FMT_C_3_3_2				(9 << 0)
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+#   define R500_OUT_FMT_C_6_5_6				(10 << 0)
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+#   define R500_OUT_FMT_C_11_11_10			(11 << 0)
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+#   define R500_OUT_FMT_C_10_11_11			(12 << 0)
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+#   define R500_OUT_FMT_C_2_10_10_10			(13 << 0)
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+/* #define R500_OUT_FMT_RESERVED			(14 << 0) */
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+#   define R500_OUT_FMT_UNUSED				(15 << 0)
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+#   define R500_OUT_FMT_C_16_FP				(16 << 0)
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+#   define R500_OUT_FMT_C2_16_FP			(17 << 0)
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+#   define R500_OUT_FMT_C4_16_FP			(18 << 0)
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+#   define R500_OUT_FMT_C_32_FP				(19 << 0)
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+#   define R500_OUT_FMT_C2_32_FP			(20 << 0)
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+#   define R500_OUT_FMT_C4_32_FP			(21 << 0)
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+#   define R500_C0_SEL_A				(0 << 8)
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+#   define R500_C0_SEL_R				(1 << 8)
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+#   define R500_C0_SEL_G				(2 << 8)
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+#   define R500_C0_SEL_B				(3 << 8)
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+#   define R500_C1_SEL_A				(0 << 10)
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+#   define R500_C1_SEL_R				(1 << 10)
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+#   define R500_C1_SEL_G				(2 << 10)
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+#   define R500_C1_SEL_B				(3 << 10)
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+#   define R500_C2_SEL_A				(0 << 12)
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+#   define R500_C2_SEL_R				(1 << 12)
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+#   define R500_C2_SEL_G				(2 << 12)
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+#   define R500_C2_SEL_B				(3 << 12)
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+#   define R500_C3_SEL_A				(0 << 14)
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+#   define R500_C3_SEL_R				(1 << 14)
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+#   define R500_C3_SEL_G				(2 << 14)
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+#   define R500_C3_SEL_B				(3 << 14)
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+#   define R500_OUT_SIGN(x)				(x << 16)
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+#   define R500_ROUND_ADJ				(1 << 20)
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+#define R500_US_PIXSIZE					0x4604
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+#   define R500_PIX_SIZE(x)				(x)
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+#define R500_US_TEX_ADDR_0				0x9800
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+#   define R500_TEX_SRC_ADDR(x)				(x << 0)
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+#   define R500_TEX_SRC_ADDR_REL			(1 << 7)
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+#   define R500_TEX_SRC_S_SWIZ_R			(0 << 8)
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+#   define R500_TEX_SRC_S_SWIZ_G			(1 << 8)
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+#   define R500_TEX_SRC_S_SWIZ_B			(2 << 8)
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+#   define R500_TEX_SRC_S_SWIZ_A			(3 << 8)
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+#   define R500_TEX_SRC_T_SWIZ_R			(0 << 10)
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+#   define R500_TEX_SRC_T_SWIZ_G			(1 << 10)
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+#   define R500_TEX_SRC_T_SWIZ_B			(2 << 10)
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+#   define R500_TEX_SRC_T_SWIZ_A			(3 << 10)
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+#   define R500_TEX_SRC_R_SWIZ_R			(0 << 12)
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+#   define R500_TEX_SRC_R_SWIZ_G			(1 << 12)
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+#   define R500_TEX_SRC_R_SWIZ_B			(2 << 12)
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+#   define R500_TEX_SRC_R_SWIZ_A			(3 << 12)
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+#   define R500_TEX_SRC_Q_SWIZ_R			(0 << 14)
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+#   define R500_TEX_SRC_Q_SWIZ_G			(1 << 14)
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+#   define R500_TEX_SRC_Q_SWIZ_B			(2 << 14)
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+#   define R500_TEX_SRC_Q_SWIZ_A			(3 << 14)
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+#   define R500_TEX_DST_ADDR(x)				(x << 16)
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+#   define R500_TEX_DST_ADDR_REL			(1 << 23)
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+#   define R500_TEX_DST_R_SWIZ_R			(0 << 24)
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+#   define R500_TEX_DST_R_SWIZ_G			(1 << 24)
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+#   define R500_TEX_DST_R_SWIZ_B			(2 << 24)
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+#   define R500_TEX_DST_R_SWIZ_A			(3 << 24)
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+#   define R500_TEX_DST_G_SWIZ_R			(0 << 26)
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+#   define R500_TEX_DST_G_SWIZ_G			(1 << 26)
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+#   define R500_TEX_DST_G_SWIZ_B			(2 << 26)
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+#   define R500_TEX_DST_G_SWIZ_A			(3 << 26)
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+#   define R500_TEX_DST_B_SWIZ_R			(0 << 28)
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+#   define R500_TEX_DST_B_SWIZ_G			(1 << 28)
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+#   define R500_TEX_DST_B_SWIZ_B			(2 << 28)
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+#   define R500_TEX_DST_B_SWIZ_A			(3 << 28)
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+#   define R500_TEX_DST_A_SWIZ_R			(0 << 30)
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+#   define R500_TEX_DST_A_SWIZ_G			(1 << 30)
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+#   define R500_TEX_DST_A_SWIZ_B			(2 << 30)
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+#   define R500_TEX_DST_A_SWIZ_A			(3 << 30)
fb7d64
+#define R500_US_TEX_ADDR_DXDY_0				0xa000
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+#   define R500_DX_ADDR(x)				(x << 0)
fb7d64
+#   define R500_DX_ADDR_REL				(1 << 7)
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+#   define R500_DX_S_SWIZ_R				(0 << 8)
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+#   define R500_DX_S_SWIZ_G				(1 << 8)
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+#   define R500_DX_S_SWIZ_B				(2 << 8)
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+#   define R500_DX_S_SWIZ_A				(3 << 8)
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+#   define R500_DX_T_SWIZ_R				(0 << 10)
fb7d64
+#   define R500_DX_T_SWIZ_G				(1 << 10)
fb7d64
+#   define R500_DX_T_SWIZ_B				(2 << 10)
fb7d64
+#   define R500_DX_T_SWIZ_A				(3 << 10)
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+#   define R500_DX_R_SWIZ_R				(0 << 12)
fb7d64
+#   define R500_DX_R_SWIZ_G				(1 << 12)
fb7d64
+#   define R500_DX_R_SWIZ_B				(2 << 12)
fb7d64
+#   define R500_DX_R_SWIZ_A				(3 << 12)
fb7d64
+#   define R500_DX_Q_SWIZ_R				(0 << 14)
fb7d64
+#   define R500_DX_Q_SWIZ_G				(1 << 14)
fb7d64
+#   define R500_DX_Q_SWIZ_B				(2 << 14)
fb7d64
+#   define R500_DX_Q_SWIZ_A				(3 << 14)
fb7d64
+#   define R500_DY_ADDR(x)				(x << 16)
fb7d64
+#   define R500_DY_ADDR_REL				(1 << 17)
fb7d64
+#   define R500_DY_S_SWIZ_R				(0 << 24)
fb7d64
+#   define R500_DY_S_SWIZ_G				(1 << 24)
fb7d64
+#   define R500_DY_S_SWIZ_B				(2 << 24)
fb7d64
+#   define R500_DY_S_SWIZ_A				(3 << 24)
fb7d64
+#   define R500_DY_T_SWIZ_R				(0 << 26)
fb7d64
+#   define R500_DY_T_SWIZ_G				(1 << 26)
fb7d64
+#   define R500_DY_T_SWIZ_B				(2 << 26)
fb7d64
+#   define R500_DY_T_SWIZ_A				(3 << 26)
fb7d64
+#   define R500_DY_R_SWIZ_R				(0 << 28)
fb7d64
+#   define R500_DY_R_SWIZ_G				(1 << 28)
fb7d64
+#   define R500_DY_R_SWIZ_B				(2 << 28)
fb7d64
+#   define R500_DY_R_SWIZ_A				(3 << 28)
fb7d64
+#   define R500_DY_Q_SWIZ_R				(0 << 30)
fb7d64
+#   define R500_DY_Q_SWIZ_G				(1 << 30)
fb7d64
+#   define R500_DY_Q_SWIZ_B				(2 << 30)
fb7d64
+#   define R500_DY_Q_SWIZ_A				(3 << 30)
fb7d64
+#define R500_US_TEX_INST_0				0x9000
fb7d64
+#   define R500_TEX_ID(x)				(x << 16)
fb7d64
+#   define R500_TEX_INST_NOP				(0 << 22)
fb7d64
+#   define R500_TEX_INST_LD				(1 << 22)
fb7d64
+#   define R500_TEX_INST_TEXKILL			(2 << 22)
fb7d64
+#   define R500_TEX_INST_PROJ				(3 << 22)
fb7d64
+#   define R500_TEX_INST_LODBIAS			(4 << 22)
fb7d64
+#   define R500_TEX_INST_LOD				(5 << 22)
fb7d64
+#   define R500_TEX_INST_DXDY				(6 << 22)
fb7d64
+#   define R500_TEX_SEM_ACQUIRE				(1 << 25)
fb7d64
+#   define R500_TEX_IGNORE_UNCOVERED			(1 << 26)
fb7d64
+#   define R500_TEX_UNSCALED				(1 << 27)
fb7d64
+#define R500_US_W_FMT					0x46b4
fb7d64
+#   define R500_W_FMT_W0				(0 << 0)
fb7d64
+#   define R500_W_FMT_W24				(1 << 0)
fb7d64
+#   define R500_W_FMT_W24FP				(2 << 0)
fb7d64
+#   define R500_W_SRC_US				(0 << 2)
fb7d64
+#   define R500_W_SRC_RAS				(1 << 2)
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+
fb7d64
+#define R500_GA_US_VECTOR_INDEX 0x4250
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+#define R500_GA_US_VECTOR_DATA 0x4254
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+
fb7d64
+#define R500_RS_INST_0					0x4320
fb7d64
+#define R500_RS_INST_TEX_ID_SHIFT			0
fb7d64
+#define R500_RS_INST_TEX_CN_WRITE			(1 << 4)
fb7d64
+#define R500_RS_INST_TEX_ADDR_SHIFT			5
fb7d64
+#define R500_RS_INST_COL_ID_SHIFT			12
fb7d64
+#define R500_RS_INST_COL_CN_NO_WRITE			(0 << 16)
fb7d64
+#define R500_RS_INST_COL_CN_WRITE			(1 << 16)
fb7d64
+#define R500_RS_INST_COL_CN_WRITE_FBUFFER		(2 << 16)
fb7d64
+#define R500_RS_INST_COL_CN_WRITE_BACKFACE		(3 << 16)
fb7d64
+#define R500_RS_INST_COL_COL_ADDR_SHIFT			18
fb7d64
+#define R500_RS_INST_TEX_ADJ				(1 << 25)
fb7d64
+#define R500_RS_INST_W_CN				(1 << 26)
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+
fb7d64
+#define R500_US_FC_CTRL					0x4624
fb7d64
+#define R500_US_CODE_ADDR				0x4630
fb7d64
+#define R500_US_CODE_RANGE 				0x4634
fb7d64
+#define R500_US_CODE_OFFSET 				0x4638
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+
fb7d64
+#define R500_RS_IP_0					0x4074
fb7d64
+#define R500_RS_IP_PTR_K0				62
fb7d64
+#define R500_RS_IP_PTR_K1 				63
fb7d64
+#define R500_RS_IP_TEX_PTR_S_SHIFT 			0
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+#define R500_RS_IP_TEX_PTR_T_SHIFT 			6
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+#define R500_RS_IP_TEX_PTR_R_SHIFT 			12
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+#define R500_RS_IP_TEX_PTR_Q_SHIFT 			18