commit ce4fa1cedec0cf56b9979dfaa12a8d3a7c643df4
Author: Arkadiusz Miskiewicz <arekm@maven.pl>
Date: Tue Dec 18 15:34:14 2007 -0500
RADEON: fix fd leak in lid detect code
commit 20568f66f9a9a60a33bd9a69ccc14a891c656836
Author: Arkadiusz Miskiewicz <arekm@maven.pl>
Date: Tue Dec 18 15:32:10 2007 -0500
RADEON: more cleanups and warning fixes
commit 1496194200adbcb044ec3977367a0908262e389c
Author: Arkadiusz Miskiewicz <arekm@maven.pl>
Date: Tue Dec 18 15:29:53 2007 -0500
RADEON: driver cleanups, warning fixes
commit 44d07c4ccce9acb5bd21a17acb082e91f7225764
Author: Alex Deucher <alex@t41p.hsd1.va.comcast.net>
Date: Mon Dec 17 18:56:12 2007 -0500
RADEON: typo from last commit
commit 4da3782239921eb377216d4de4a9cc5bb55e0e8a
Author: Alex Deucher <alex@t41p.hsd1.va.comcast.net>
Date: Mon Dec 17 18:51:31 2007 -0500
RADEON: add output enable masks
add output enable masks for outputs that drive
more than one connector. Make sure we don't turn off
an output that's driving another connector.
commit 5c5d2d19b2b032a06dd333b4ecc029aac342fb93
Author: Alex Deucher <alex@t41p.hsd1.va.comcast.net>
Date: Mon Dec 17 18:15:55 2007 -0500
RADEON: whitespace clean-ups
commit 9f1d8220315c8894a17f2cc328025dc682b0c6e0
Author: Alex Deucher <alex@t41p.hsd1.va.comcast.net>
Date: Mon Dec 17 18:04:05 2007 -0500
RADEON: more PLL fixes
- reduce the calculation accuracy
- certain LVDS panels seem to only like certain ref_divs
- add pll flags to handle special cases
- adjust the pll limits on legacy cards
commit 4747c1f3cd4167b6a51d4864a297719ea48b9346
Author: Alex Deucher <alex@t41p.hsd1.va.comcast.net>
Date: Sun Dec 16 14:07:29 2007 -0500
RADEON: Make sure LVDS_EN bit is set when enabling LVDS
commit b653e5a628bfa4dfb168e96f93f41eb910f409fb
Author: Michel Dänzer <michel@tungstengraphics.com>
Date: Sat Dec 15 00:50:10 2007 +0100
radeon: Default to 1x again with non-v3 AGP cards.
Seems more reliable in general than what was set up by firmware - fingers
crossed...
commit 6229825fa5d6715569098afbb21a40f7a2e7e6be
Author: Michel Dänzer <michel@tungstengraphics.com>
Date: Sat Dec 15 00:48:26 2007 +0100
radeon: Warning fixes.
The lid detection code probably wouldn't work on other non-x86 platforms
though...
commit 818ccf0fd4b5879171c5f20526d5a58638f8fde5
Author: Fredrik Höglund <fredrik@kde.org>
Date: Fri Dec 14 23:56:12 2007 +0100
RADEON: Fix the vertex coordinates for transformed pictures
This partially fixes transformed pictures on R100/R200 based
cards. The texture still doesn't appear to be clamped correctly,
but since that doesn't matter for rotations at perpendicular
angles, I'm committing this now so randr rotation and reflection
will work properly.
commit 3cfbcf4cafbdfdb33411d16e51fb1f77cd0f93dd
Author: Alex Deucher <alex@t41p.hsd1.va.comcast.net>
Date: Fri Dec 14 17:11:00 2007 -0500
RADEON: Fix PLL set up on certain notebooks
Some LVDS panels require specific PLL dividers as
specified in the bios tables. Make sure to use them
if the output is LVDS.
commit a84d446fd301d456bcea8f7abdc52e5a30776412
Author: Alex Deucher <alex@botch2.(none)>
Date: Fri Dec 14 02:17:14 2007 -0500
RADEON: select fb_div0 for LVDS on RV410 (x700) mobility
Fixes bug 8038
I wonder if desktop RV410 need a similar fix.
If your x700 laptop panel has problems after this let me know.
commit 6ccf5b33d27218ae1c45ab93c122438ed536d8ba
Author: Alex Deucher <alex@botch2.(none)>
Date: Wed Dec 12 20:12:06 2007 -0500
RADEON: only enable vblanks if we want them
should fix bug 13610
commit 1668f2056f56370f1b5681c13f1e14904e301216
Author: Alex Deucher <alex@t41p.hsd1.va.comcast.net>
Date: Wed Dec 12 19:39:08 2007 -0500
RADEON: use /proc/acpi to determine lid status
Linux only
commit 33a39947f7f79533cd90007a17d57b20126642c6
Author: Alex Deucher <alex@t41p.hsd1.va.comcast.net>
Date: Wed Dec 12 18:50:18 2007 -0500
RADEON: fix cursors when using rotation
allocate separate cursor buffers for each crtc
commit 9e5efdecd12092031a4aebce58747cb4a6f48f28
Author: Arkadiusz Miskiewicz <arekm@maven.pl>
Date: Tue Dec 11 23:53:03 2007 -0500
sparse fixes and cleanups from arekm
commit f3d2ec3a5ae61215c792018320158750e7aa937c
Author: Alex Deucher <alex@botch2.(none)>
Date: Tue Dec 11 11:57:27 2007 -0500
RADEON: rewrite PLL computation
Algorithm adapted from BeOS radeon driver with some tweaks by me.
Actually calulate and use the reference divider rather than using the bios default.
Also, always calculate the PLL, rather than falling back to bios dividers.
This should fix bugs 12913, 13590, 13533, possibly others.
commit 9b125312ab6edc585e4f5931a6a6de81e13b6acc
Author: Alex Deucher <alex@t41p.hsd1.va.comcast.net>
Date: Mon Dec 10 13:53:15 2007 -0500
RADEON: only update crtc values when RMX is active
commit 3a161e1b5d80361e318ced8da5c19e797749d693
Author: Alex Deucher <alex@botch2.(none)>
Date: Mon Dec 10 00:57:26 2007 -0500
RADEON: bios PLL cleanup
commit 5896ca4097d439f59f90f397939132c061c3c364
Author: LisaWu <liswu@ati.com>
Date: Fri Dec 7 09:45:05 2007 +0100
radeon: Use %u instead of %d for unsigned value.
commit df44f8380268c27d3978c4e91d736f093322b8b8
Author: Michel Dänzer <michel@tungstengraphics.com>
Date: Fri Dec 7 09:41:47 2007 +0100
radeon: Use gettimeofday instead of xf86getsecs.
commit 64ab1cdf343a9a69e7e9e64f0bba77c54a94e9d0
Author: James Cloos <cloos@jhcloos.com>
Date: Thu Dec 6 15:51:12 2007 -0500
Add missing PHONY line for automatic ChangeLog generation
commit 21ed435398e4a398dd8a0a5d7c1d4cc45e916332
Author: Alex Deucher <alex@t41p.hsd1.va.comcast.net>
Date: Tue Dec 4 17:08:58 2007 -0500
RADEON: add MacModel imac-g5-isight for iMac G5 iSight
Thanks to Étienne Bersac for helping to figure this out.
commit 54bfd522405d9fdfb69d3a59e111ac3d63483dbb
Author: Étienne Bersac <bersace03@laposte.net>
Date: Tue Dec 4 14:22:42 2007 -0500
RADEON: fix typo
commit 5022d006cfc06ca0395981526b2c2c94c6878567
Author: Michel Dänzer <michel@tungstengraphics.com>
Date: Sun Dec 2 17:27:33 2007 +0100
radeon: Further XVideo fixes.
* Make sure pitch constraints are always met for DMA upload blits.
* RGB24 is not affected by endianness.
commit 6ed55b70b23dfdc7b41103ea59c1df2bda5e41e6
Author: Kusanagi Kouichi <slash@ma.neweb.ne.jp>
Date: Sun Dec 2 17:18:46 2007 +0100
radeon: Fix crash with XVideo 24bit RGB images.
See https://bugs.freedesktop.org/show_bug.cgi?id=13274 .
commit a697b590899bb7704ec4d7ae9a9c3cbbfcaef382
Author: Michel Dänzer <michel@tungstengraphics.com>
Date: Sun Dec 2 17:11:20 2007 +0100
Fix build against xserver master.
(DE)ALLOCATE_LOCAL are gone.
commit 00b4480aa2c5d7f751e34fc964f431b90b14c8d2
Author: Alex Deucher <alex@t41p.hsd1.va.comcast.net>
Date: Sat Dec 1 14:18:40 2007 -0500
RADEON: add options for force TV out as detected and to set TV standard
Also fix a typo in internal tv-out parsing
commit 0175b79987ef4d7b0ce8238c3bdde989e504516a
Author: Alex Deucher <alex@botch2.(none)>
Date: Fri Nov 30 15:37:42 2007 -0500
RADEON: rework MacModel option
this brings in some previous research from Michel Dänzer,
Sjoerd Simons, and myself. Hopefully, the driver will pick
the correct MacModel in more cases. This also changes the
default connector table for desktop Macs to dual DVI rather
than DVI+VGA as that seems to be the case more often than not.
External TMDS chips are handled separately now as well.
Eventually we should add an option to allow the user to specify
what external TMDS chip they need, but we don't have enough info
yet, so we'll rely on OF to init the external chip in most cases
for now.
commit 9840a0fd4fc8c980533fcd4a02c55cd0d5634b6d
Author: Alex Deucher <alex@botch2.(none)>
Date: Thu Nov 29 13:27:37 2007 -0500
RADEON: add MacModel "mini-internal" for minis with internal TMDS
Some macs (minis and powerbooks) use internal tmds, others use external tmds
and not just for dual-link TMDS, it shows up with single-link as well.
Unforunately, there doesn't seem to be any good way to figure it out.
commit 6f080d00e6f4f84d5e0d6b4eff302bf42c230e81
Author: Arkadiusz Miskiewicz <arekm@maven.pl>
Date: Mon Nov 26 12:43:30 2007 -0500
RADEON: fix backlight control on some laptops
It seems the bios scratch regs are involved in backlight control
on some laptops. This patch fixes the problematic laptops and doesn't
seem to break the previous bios lid and output control fixes.
commit dcf22aed87366f4625fb5042cb84fecccd9ceece
Author: Alex Deucher <alex@botch2.(none)>
Date: Mon Nov 26 11:10:03 2007 -0500
RADEON: only return status unknown for XPRESS chips
this seems to cause more issues than it attempted to fix
so limit it to XPRESS chips for now.
commit 206e280f02324641b4fe5a1986e26adf0e021fd4
Author: Alex Deucher <alex@botch2.(none)>
Date: Mon Nov 26 09:39:27 2007 -0500
RADEON: fix typo in man page
commit 197a62704742a4a19736c2637ac92d1dc5ab34ed
Author: Adam Jackson <ajackson@redhat.com>
Date: Thu Nov 22 20:26:23 2007 +1000
radeon: fix openoffice/render bug on r100 chips
commit 64010fc4eae8359c01e430f64252931242c91435
Author: Dave Airlie <airlied@linux.ie>
Date: Thu Nov 22 20:25:31 2007 +1000
Revert "Disable RENDER acceleration by default on some RV200 chips."
This reverts commit 145da701bf4fb9c0ad9f95620b20914ae0126852.
pull in fix from ajax next commit
commit 145da701bf4fb9c0ad9f95620b20914ae0126852
Author: Stefan Dirsch <sndirsch@suse.de>
Date: Thu Nov 22 08:38:09 2007 +0100
Disable RENDER acceleration by default on some RV200 chips.
Novell Bug #341699: Render acceleration is known to be broken
on at least "Radeon 7500 QW" and "Radeon Mobility M7 LW".
commit e810c3ae9908cd57e95b1b091cded87cbfc12fdc
Author: Roland Scheidegger <sroland@tungstengraphics.com>
Date: Thu Nov 22 02:37:55 2007 +0100
really do not set up surface regs for depth buf on r100-class igps (bug #13080)
fix the if condition testing for these chips...
commit c8872603454e6a4ffed9fc7d9adc2c364a429608
Author: Dave Airlie <airlied@clockmaker.usersys.redhat.com>
Date: Tue Nov 20 22:33:39 2007 +1000
radeon: restructure pci ids to avoid effort later
This uses a single file with all the pciids and parameters for radeon
family and setup in it. I don't run the perl script at build time to avoid
a perl dependency on build but adding pci ids should be done via the csv file
with openoffice or gnumeric if possible.
commit 49055d8aff91ff12186feaf5343c8fd2f96bcba0
Author: Alex Deucher <alex@t41p.hsd1.va.comcast.net>
Date: Thu Nov 15 22:56:09 2007 -0500
RADEON: set proper defaults for tv dac BGADJ/DACADJ
we should get these values from the bios tables, but for now use
some reasonable defaults. This should fix the washed out color
problems on bugs 1082 and 12844.
commit 821acf38b716ab87c3d07263d6e4a139fe54803f
Author: Alex Deucher <alex@t41p.hsd1.va.comcast.net>
Date: Thu Nov 15 22:28:42 2007 -0500
RADEON: Make sure we set the MT properly for connected status unknown
commit a94123f33ec6584fbdfc4b9ecd543d1357de8814
Author: Alex Deucher <alex@t41p.hsd1.va.comcast.net>
Date: Thu Nov 15 22:19:54 2007 -0500
Revert "Portability fix from netbsd"
This reverts commit c9264aa53bf1470ad9104d1e7c4a8ce13c49c270.
This breaks damage support. See bug 13244
commit e9d721c31372db045550f9562534b28f16121bb9
Author: Roland Scheidegger <sroland@tungstengraphics.com>
Date: Tue Nov 13 23:42:42 2007 +0100
ignore sometime bogus agp_mode bit from chip (bug #13190)
bit is wrong on at least X700 cards with rialto pcie-agp bridge chip,
should be safe to use just the bit from the bridge hopefully to make
agp setup work on these cards and not adversely affect others.
diff --git a/Makefile.am b/Makefile.am
index 2ae4852..ea2e4a3 100644
--- a/Makefile.am
+++ b/Makefile.am
@@ -33,6 +33,8 @@ endif
EXTRA_DIST = README.ati README.r128 README.ati.sgml README.r128.sgml ChangeLog
CLEANFILES = ChangeLog
+.PHONY: ChangeLog
+
ChangeLog:
(GIT_DIR=$(top_srcdir)/.git git-log > .changelog.tmp && mv .changelog.tmp ChangeLog; rm -f .changelog.tmp) || (touch ChangeLog; echo 'git directory not found: installing possibly empty changelog.' >&2)
diff --git a/configure.ac b/configure.ac
index 450d951..1570e54 100644
--- a/configure.ac
+++ b/configure.ac
@@ -58,7 +58,7 @@ AC_ARG_ENABLE(dri, AC_HELP_STRING([--disable-dri],
AC_ARG_ENABLE(exa,
AC_HELP_STRING([--disable-exa],
- [Disable EXA support [[default enabled]]]),
+ [Disable EXA support [[default=enabled]]]),
[EXA="$enableval"],
[EXA=yes])
@@ -79,7 +79,7 @@ sdkdir=$(pkg-config --variable=sdkdir xorg-server)
# Checks for header files.
AC_HEADER_STDC
-if test "x$DRI" = xauto; then
+if test "$DRI" != no; then
AC_CHECK_FILE([${sdkdir}/dri.h],
[have_dri_h="yes"], [have_dri_h="no"])
AC_CHECK_FILE([${sdkdir}/sarea.h],
diff --git a/man/radeon.man b/man/radeon.man
index 5d31eb1..3c4df23 100644
--- a/man/radeon.man
+++ b/man/radeon.man
@@ -383,14 +383,14 @@ case. This is only useful for LVDS panels (laptop internal panels).
The default is
.B on.
.TP
-.BI "Option \*TVDACLoadDetect\*q \*q" boolean \*q
+.BI "Option \*qTVDACLoadDetect\*q \*q" boolean \*q
Enable load detection on the TV DAC. The TV DAC is used to drive both
TV-OUT and analog monitors. Load detection is often unreliable in the
TV DAC so it is disabled by default.
The default is
.B off.
.TP
-.BI "Option \*DefaultTMDSPLL\*q \*q" boolean \*q
+.BI "Option \*qDefaultTMDSPLL\*q \*q" boolean \*q
Use the default driver provided TMDS PLL values rather than the ones
provided by the bios. This option has no effect on Mac cards. Enable
this option if you are having problems with a DVI monitor using the
@@ -414,20 +414,59 @@ The default is
.TP
.BI "Option \*qMacModel\*q \*q" string \*q
.br
-Used to specify Mac models for connector tables and quirks. Only valid
- on PowerPC.
+Used to specify Mac models for connector tables and quirks. If you have
+a powerbook or mini with DVI that does not work properly, try the alternate
+ options as Apple does not seem to provide a good way of knowing whether
+ they use internal or external TMDS for DVI. Only valid on PowerPC.
.br
ibook \-\- ibooks
.br
-powerbook-duallink \-\- Powerbooks with external DVI
+powerbook-external \-\- Powerbooks with external DVI
.br
-powerbook \-\- Powerbooks with integrated DVI
+powerbook-internal \-\- Powerbooks with integrated DVI
.br
-mini \-\- Mac Mini
+powerbook-vga \-\- Powerbooks with VGA rather than DVI
+.br
+powerbook-duallink \-\- powerbook-external alias
+.br
+powerbook \-\- powerbook-internal alias
+.br
+mini-external \-\- Mac Mini with external DVI
+.br
+mini-internal \-\- Mac Mini with integrated DVI
+.br
+mini \-\- mini-external alias
+.br
+imac-g5-isight \-\- iMac G5 iSight
+.br
+The default value is
+.B undefined.
+.TP
+.BI "Option \*qTVStandard\*q \*q" string \*q
+.br
+Used to specify the default TV standard if you want to use something other than
+the bios default. Valid options are:
+.br
+ntsc
+.br
+pal
+.br
+pal-m
+.br
+pal-60
+.br
+ntsc-j
+.br
+scart-pal
.br
The default value is
.B undefined.
.TP
+.BI "Option \*qForceTVOut\*q \*q" boolean \*q
+Enable this option to force TV Out to always be detected as attached.
+The default is
+.B off
+.TP
.SH SEE ALSO
__xservername__(__appmansuffix__), __xconfigfile__(__filemansuffix__), xorgconfig(__appmansuffix__), Xserver(__appmansuffix__), X(__miscmansuffix__)
diff --git a/src/Makefile.am b/src/Makefile.am
index ff1e225..5152577 100644
--- a/src/Makefile.am
+++ b/src/Makefile.am
@@ -171,7 +171,6 @@ EXTRA_DIST = \
r128_reg.h \
r128_sarea.h \
r128_version.h \
- radeon_chipset.h \
radeon_common.h \
radeon_commonfuncs.c \
radeon_dri.h \
@@ -191,4 +190,10 @@ EXTRA_DIST = \
theatre.h \
theatre_reg.h \
atipciids.h \
- atipcirename.h
+ atipcirename.h \
+ ati_pciids_gen.h \
+ radeon_chipinfo_gen.h \
+ radeon_chipset_gen.h \
+ radeon_pci_chipset_gen.h \
+ pcidb/ati_pciids.csv \
+ pcidb/parse_pci_ids.pl
diff --git a/src/ati_pciids_gen.h b/src/ati_pciids_gen.h
new file mode 100644
index 0000000..ad54f64
--- /dev/null
+++ b/src/ati_pciids_gen.h
@@ -0,0 +1,219 @@
+#define PCI_CHIP_RV380_3150 0x3150
+#define PCI_CHIP_RV380_3152 0x3152
+#define PCI_CHIP_RV380_3154 0x3154
+#define PCI_CHIP_RV380_3E50 0x3E50
+#define PCI_CHIP_RV380_3E54 0x3E54
+#define PCI_CHIP_RS100_4136 0x4136
+#define PCI_CHIP_RS200_4137 0x4137
+#define PCI_CHIP_R300_AD 0x4144
+#define PCI_CHIP_R300_AE 0x4145
+#define PCI_CHIP_R300_AF 0x4146
+#define PCI_CHIP_R300_AG 0x4147
+#define PCI_CHIP_R350_AH 0x4148
+#define PCI_CHIP_R350_AI 0x4149
+#define PCI_CHIP_R350_AJ 0x414A
+#define PCI_CHIP_R350_AK 0x414B
+#define PCI_CHIP_RV350_AP 0x4150
+#define PCI_CHIP_RV350_AQ 0x4151
+#define PCI_CHIP_RV360_AR 0x4152
+#define PCI_CHIP_RV350_AS 0x4153
+#define PCI_CHIP_RV350_AT 0x4154
+#define PCI_CHIP_RV350_4155 0x4155
+#define PCI_CHIP_RV350_AV 0x4156
+#define PCI_CHIP_MACH32 0x4158
+#define PCI_CHIP_RS250_4237 0x4237
+#define PCI_CHIP_R200_BB 0x4242
+#define PCI_CHIP_R200_BC 0x4243
+#define PCI_CHIP_RS100_4336 0x4336
+#define PCI_CHIP_RS200_4337 0x4337
+#define PCI_CHIP_MACH64CT 0x4354
+#define PCI_CHIP_MACH64CX 0x4358
+#define PCI_CHIP_RS250_4437 0x4437
+#define PCI_CHIP_MACH64ET 0x4554
+#define PCI_CHIP_MACH64GB 0x4742
+#define PCI_CHIP_MACH64GD 0x4744
+#define PCI_CHIP_MACH64GI 0x4749
+#define PCI_CHIP_MACH64GL 0x474C
+#define PCI_CHIP_MACH64GM 0x474D
+#define PCI_CHIP_MACH64GN 0x474E
+#define PCI_CHIP_MACH64GO 0x474F
+#define PCI_CHIP_MACH64GP 0x4750
+#define PCI_CHIP_MACH64GQ 0x4751
+#define PCI_CHIP_MACH64GR 0x4752
+#define PCI_CHIP_MACH64GS 0x4753
+#define PCI_CHIP_MACH64GT 0x4754
+#define PCI_CHIP_MACH64GU 0x4755
+#define PCI_CHIP_MACH64GV 0x4756
+#define PCI_CHIP_MACH64GW 0x4757
+#define PCI_CHIP_MACH64GX 0x4758
+#define PCI_CHIP_MACH64GY 0x4759
+#define PCI_CHIP_MACH64GZ 0x475A
+#define PCI_CHIP_RV250_If 0x4966
+#define PCI_CHIP_RV250_Ig 0x4967
+#define PCI_CHIP_R420_JH 0x4A48
+#define PCI_CHIP_R420_JI 0x4A49
+#define PCI_CHIP_R420_JJ 0x4A4A
+#define PCI_CHIP_R420_JK 0x4A4B
+#define PCI_CHIP_R420_JL 0x4A4C
+#define PCI_CHIP_R420_JM 0x4A4D
+#define PCI_CHIP_R420_JN 0x4A4E
+#define PCI_CHIP_R420_4A4F 0x4A4F
+#define PCI_CHIP_R420_JP 0x4A50
+#define PCI_CHIP_R481_4B49 0x4B49
+#define PCI_CHIP_R481_4B4A 0x4B4A
+#define PCI_CHIP_R481_4B4B 0x4B4B
+#define PCI_CHIP_R481_4B4C 0x4B4C
+#define PCI_CHIP_MACH64LB 0x4C42
+#define PCI_CHIP_MACH64LD 0x4C44
+#define PCI_CHIP_RAGE128LE 0x4C45
+#define PCI_CHIP_RAGE128LF 0x4C46
+#define PCI_CHIP_MACH64LG 0x4C47
+#define PCI_CHIP_MACH64LI 0x4C49
+#define PCI_CHIP_MACH64LM 0x4C4D
+#define PCI_CHIP_MACH64LN 0x4C4E
+#define PCI_CHIP_MACH64LP 0x4C50
+#define PCI_CHIP_MACH64LQ 0x4C51
+#define PCI_CHIP_MACH64LR 0x4C52
+#define PCI_CHIP_MACH64LS 0x4C53
+#define PCI_CHIP_RADEON_LW 0x4C57
+#define PCI_CHIP_RADEON_LX 0x4C58
+#define PCI_CHIP_RADEON_LY 0x4C59
+#define PCI_CHIP_RADEON_LZ 0x4C5A
+#define PCI_CHIP_RV250_Ld 0x4C64
+#define PCI_CHIP_RV250_Lf 0x4C66
+#define PCI_CHIP_RV250_Lg 0x4C67
+#define PCI_CHIP_RAGE128MF 0x4D46
+#define PCI_CHIP_RAGE128ML 0x4D4C
+#define PCI_CHIP_R300_ND 0x4E44
+#define PCI_CHIP_R300_NE 0x4E45
+#define PCI_CHIP_R300_NF 0x4E46
+#define PCI_CHIP_R300_NG 0x4E47
+#define PCI_CHIP_R350_NH 0x4E48
+#define PCI_CHIP_R350_NI 0x4E49
+#define PCI_CHIP_R360_NJ 0x4E4A
+#define PCI_CHIP_R350_NK 0x4E4B
+#define PCI_CHIP_RV350_NP 0x4E50
+#define PCI_CHIP_RV350_NQ 0x4E51
+#define PCI_CHIP_RV350_NR 0x4E52
+#define PCI_CHIP_RV350_NS 0x4E53
+#define PCI_CHIP_RV350_NT 0x4E54
+#define PCI_CHIP_RV350_NV 0x4E56
+#define PCI_CHIP_RAGE128PA 0x5041
+#define PCI_CHIP_RAGE128PB 0x5042
+#define PCI_CHIP_RAGE128PC 0x5043
+#define PCI_CHIP_RAGE128PD 0x5044
+#define PCI_CHIP_RAGE128PE 0x5045
+#define PCI_CHIP_RAGE128PF 0x5046
+#define PCI_CHIP_RAGE128PG 0x5047
+#define PCI_CHIP_RAGE128PH 0x5048
+#define PCI_CHIP_RAGE128PI 0x5049
+#define PCI_CHIP_RAGE128PJ 0x504A
+#define PCI_CHIP_RAGE128PK 0x504B
+#define PCI_CHIP_RAGE128PL 0x504C
+#define PCI_CHIP_RAGE128PM 0x504D
+#define PCI_CHIP_RAGE128PN 0x504E
+#define PCI_CHIP_RAGE128PO 0x504F
+#define PCI_CHIP_RAGE128PP 0x5050
+#define PCI_CHIP_RAGE128PQ 0x5051
+#define PCI_CHIP_RAGE128PR 0x5052
+#define PCI_CHIP_RAGE128PS 0x5053
+#define PCI_CHIP_RAGE128PT 0x5054
+#define PCI_CHIP_RAGE128PU 0x5055
+#define PCI_CHIP_RAGE128PV 0x5056
+#define PCI_CHIP_RAGE128PW 0x5057
+#define PCI_CHIP_RAGE128PX 0x5058
+#define PCI_CHIP_RADEON_QD 0x5144
+#define PCI_CHIP_RADEON_QE 0x5145
+#define PCI_CHIP_RADEON_QF 0x5146
+#define PCI_CHIP_RADEON_QG 0x5147
+#define PCI_CHIP_R200_QH 0x5148
+#define PCI_CHIP_R200_QL 0x514C
+#define PCI_CHIP_R200_QM 0x514D
+#define PCI_CHIP_RV200_QW 0x5157
+#define PCI_CHIP_RV200_QX 0x5158
+#define PCI_CHIP_RV100_QY 0x5159
+#define PCI_CHIP_RV100_QZ 0x515A
+#define PCI_CHIP_RN50_515E 0x515E
+#define PCI_CHIP_RAGE128RE 0x5245
+#define PCI_CHIP_RAGE128RF 0x5246
+#define PCI_CHIP_RAGE128RG 0x5247
+#define PCI_CHIP_RAGE128RK 0x524B
+#define PCI_CHIP_RAGE128RL 0x524C
+#define PCI_CHIP_RAGE128SE 0x5345
+#define PCI_CHIP_RAGE128SF 0x5346
+#define PCI_CHIP_RAGE128SG 0x5347
+#define PCI_CHIP_RAGE128SH 0x5348
+#define PCI_CHIP_RAGE128SK 0x534B
+#define PCI_CHIP_RAGE128SL 0x534C
+#define PCI_CHIP_RAGE128SM 0x534D
+#define PCI_CHIP_RAGE128SN 0x534E
+#define PCI_CHIP_RAGE128TF 0x5446
+#define PCI_CHIP_RAGE128TL 0x544C
+#define PCI_CHIP_RAGE128TR 0x5452
+#define PCI_CHIP_RAGE128TS 0x5453
+#define PCI_CHIP_RAGE128TT 0x5454
+#define PCI_CHIP_RAGE128TU 0x5455
+#define PCI_CHIP_RV370_5460 0x5460
+#define PCI_CHIP_RV370_5462 0x5462
+#define PCI_CHIP_RV370_5464 0x5464
+#define PCI_CHIP_R423_UH 0x5548
+#define PCI_CHIP_R423_UI 0x5549
+#define PCI_CHIP_R423_UJ 0x554A
+#define PCI_CHIP_R423_UK 0x554B
+#define PCI_CHIP_R430_554C 0x554C
+#define PCI_CHIP_R430_554D 0x554D
+#define PCI_CHIP_R430_554E 0x554E
+#define PCI_CHIP_R430_554F 0x554F
+#define PCI_CHIP_R423_5550 0x5550
+#define PCI_CHIP_R423_UQ 0x5551
+#define PCI_CHIP_R423_UR 0x5552
+#define PCI_CHIP_R423_UT 0x5554
+#define PCI_CHIP_RV410_564A 0x564A
+#define PCI_CHIP_RV410_564B 0x564B
+#define PCI_CHIP_RV410_564F 0x564F
+#define PCI_CHIP_RV410_5652 0x5652
+#define PCI_CHIP_RV410_5653 0x5653
+#define PCI_CHIP_MACH64VT 0x5654
+#define PCI_CHIP_MACH64VU 0x5655
+#define PCI_CHIP_MACH64VV 0x5656
+#define PCI_CHIP_RS300_5834 0x5834
+#define PCI_CHIP_RS300_5835 0x5835
+#define PCI_CHIP_RS480_5954 0x5954
+#define PCI_CHIP_RS480_5955 0x5955
+#define PCI_CHIP_RV280_5960 0x5960
+#define PCI_CHIP_RV280_5961 0x5961
+#define PCI_CHIP_RV280_5962 0x5962
+#define PCI_CHIP_RV280_5964 0x5964
+#define PCI_CHIP_RV280_5965 0x5965
+#define PCI_CHIP_RN50_5969 0x5969
+#define PCI_CHIP_RS482_5974 0x5974
+#define PCI_CHIP_RS485_5975 0x5975
+#define PCI_CHIP_RS400_5A41 0x5A41
+#define PCI_CHIP_RS400_5A42 0x5A42
+#define PCI_CHIP_RC410_5A61 0x5A61
+#define PCI_CHIP_RC410_5A62 0x5A62
+#define PCI_CHIP_RV370_5B60 0x5B60
+#define PCI_CHIP_RV370_5B62 0x5B62
+#define PCI_CHIP_RV370_5B63 0x5B63
+#define PCI_CHIP_RV370_5B64 0x5B64
+#define PCI_CHIP_RV370_5B65 0x5B65
+#define PCI_CHIP_RV280_5C61 0x5C61
+#define PCI_CHIP_RV280_5C63 0x5C63
+#define PCI_CHIP_R430_5D48 0x5D48
+#define PCI_CHIP_R430_5D49 0x5D49
+#define PCI_CHIP_R430_5D4A 0x5D4A
+#define PCI_CHIP_R480_5D4C 0x5D4C
+#define PCI_CHIP_R480_5D4D 0x5D4D
+#define PCI_CHIP_R480_5D4E 0x5D4E
+#define PCI_CHIP_R480_5D4F 0x5D4F
+#define PCI_CHIP_R480_5D50 0x5D50
+#define PCI_CHIP_R480_5D52 0x5D52
+#define PCI_CHIP_R423_5D57 0x5D57
+#define PCI_CHIP_RV410_5E48 0x5E48
+#define PCI_CHIP_RV410_5E4A 0x5E4A
+#define PCI_CHIP_RV410_5E4B 0x5E4B
+#define PCI_CHIP_RV410_5E4C 0x5E4C
+#define PCI_CHIP_RV410_5E4D 0x5E4D
+#define PCI_CHIP_RV410_5E4F 0x5E4F
+#define PCI_CHIP_RS350_7834 0x7834
+#define PCI_CHIP_RS350_7835 0x7835
diff --git a/src/atidri.c b/src/atidri.c
index bc862a8..0da1bc5 100644
--- a/src/atidri.c
+++ b/src/atidri.c
@@ -553,11 +553,11 @@ static void ATIDRIMoveBuffers( WindowPtr pWin, DDXPointRec ptOldOrg,
if (nbox > 1) {
/* Keep ordering in each band, reverse order of bands */
- pboxNew1 = (BoxPtr)ALLOCATE_LOCAL(sizeof(BoxRec)*nbox);
+ pboxNew1 = (BoxPtr)xalloc(sizeof(BoxRec)*nbox);
if (!pboxNew1) return;
- pptNew1 = (DDXPointPtr)ALLOCATE_LOCAL(sizeof(DDXPointRec)*nbox);
+ pptNew1 = (DDXPointPtr)xalloc(sizeof(DDXPointRec)*nbox);
if (!pptNew1) {
- DEALLOCATE_LOCAL(pboxNew1);
+ xfree(pboxNew1);
return;
}
pboxBase = pboxNext = pbox+nbox-1;
@@ -588,13 +588,13 @@ static void ATIDRIMoveBuffers( WindowPtr pWin, DDXPointRec ptOldOrg,
if (nbox > 1) {
/* reverse order of rects in each band */
- pboxNew2 = (BoxPtr)ALLOCATE_LOCAL(sizeof(BoxRec)*nbox);
- pptNew2 = (DDXPointPtr)ALLOCATE_LOCAL(sizeof(DDXPointRec)*nbox);
+ pboxNew2 = (BoxPtr)xalloc(sizeof(BoxRec)*nbox);
+ pptNew2 = (DDXPointPtr)xalloc(sizeof(DDXPointRec)*nbox);
if (!pboxNew2 || !pptNew2) {
- DEALLOCATE_LOCAL(pptNew2);
- DEALLOCATE_LOCAL(pboxNew2);
- DEALLOCATE_LOCAL(pptNew1);
- DEALLOCATE_LOCAL(pboxNew1);
+ xfree(pptNew2);
+ xfree(pboxNew2);
+ xfree(pptNew1);
+ xfree(pboxNew1);
return;
}
pboxBase = pboxNext = pbox;
@@ -665,10 +665,10 @@ static void ATIDRIMoveBuffers( WindowPtr pWin, DDXPointRec ptOldOrg,
outf(SRC_OFF_PITCH, pATI->NewHW.dst_off_pitch);
outf(DST_OFF_PITCH, pATI->NewHW.src_off_pitch);
- DEALLOCATE_LOCAL(pptNew2);
- DEALLOCATE_LOCAL(pboxNew2);
- DEALLOCATE_LOCAL(pptNew1);
- DEALLOCATE_LOCAL(pboxNew1);
+ xfree(pptNew2);
+ xfree(pboxNew2);
+ xfree(pptNew1);
+ xfree(pboxNew1);
ATIDRIMarkSyncInt(pScreenInfo);
#endif
diff --git a/src/atipciids.h b/src/atipciids.h
index 2aa8a3e..f24f8fb 100644
--- a/src/atipciids.h
+++ b/src/atipciids.h
@@ -38,253 +38,7 @@
#define PCI_VENDOR_AMD 0x1022
#define PCI_VENDOR_DELL 0x1028
-/* ATI */
-#define PCI_CHIP_RV380_3150 0x3150
-#define PCI_CHIP_RV380_3151 0x3151
-#define PCI_CHIP_RV380_3152 0x3152
-#define PCI_CHIP_RV380_3153 0x3153
-#define PCI_CHIP_RV380_3154 0x3154
-#define PCI_CHIP_RV380_3156 0x3156
-#define PCI_CHIP_RV380_3E50 0x3E50
-#define PCI_CHIP_RV380_3E51 0x3E51
-#define PCI_CHIP_RV380_3E52 0x3E52
-#define PCI_CHIP_RV380_3E53 0x3E53
-#define PCI_CHIP_RV380_3E54 0x3E54
-#define PCI_CHIP_RV380_3E56 0x3E56
-#define PCI_CHIP_RS100_4136 0x4136
-#define PCI_CHIP_RS200_4137 0x4137
-#define PCI_CHIP_R300_AD 0x4144
-#define PCI_CHIP_R300_AE 0x4145
-#define PCI_CHIP_R300_AF 0x4146
-#define PCI_CHIP_R300_AG 0x4147
-#define PCI_CHIP_R350_AH 0x4148
-#define PCI_CHIP_R350_AI 0x4149
-#define PCI_CHIP_R350_AJ 0x414A
-#define PCI_CHIP_R350_AK 0x414B
-#define PCI_CHIP_RV350_AP 0x4150
-#define PCI_CHIP_RV350_AQ 0x4151
-#define PCI_CHIP_RV360_AR 0x4152
-#define PCI_CHIP_RV350_AS 0x4153
-#define PCI_CHIP_RV350_AT 0x4154
-#define PCI_CHIP_RV350_4155 0x4155
-#define PCI_CHIP_RV350_AV 0x4156
-#define PCI_CHIP_MACH32 0x4158
-#define PCI_CHIP_RS250_4237 0x4237
-#define PCI_CHIP_R200_BB 0x4242
-#define PCI_CHIP_R200_BC 0x4243
-#define PCI_CHIP_RS100_4336 0x4336
-#define PCI_CHIP_RS200_4337 0x4337
-#define PCI_CHIP_MACH64CT 0x4354
-#define PCI_CHIP_MACH64CX 0x4358
-#define PCI_CHIP_RS250_4437 0x4437
-#define PCI_CHIP_MACH64ET 0x4554
-#define PCI_CHIP_MACH64GB 0x4742
-#define PCI_CHIP_MACH64GD 0x4744
-#define PCI_CHIP_MACH64GI 0x4749
-#define PCI_CHIP_MACH64GL 0x474C
-#define PCI_CHIP_MACH64GM 0x474D
-#define PCI_CHIP_MACH64GN 0x474E
-#define PCI_CHIP_MACH64GO 0x474F
-#define PCI_CHIP_MACH64GP 0x4750
-#define PCI_CHIP_MACH64GQ 0x4751
-#define PCI_CHIP_MACH64GR 0x4752
-#define PCI_CHIP_MACH64GS 0x4753
-#define PCI_CHIP_MACH64GT 0x4754
-#define PCI_CHIP_MACH64GU 0x4755
-#define PCI_CHIP_MACH64GV 0x4756
-#define PCI_CHIP_MACH64GW 0x4757
-#define PCI_CHIP_MACH64GX 0x4758
-#define PCI_CHIP_MACH64GY 0x4759
-#define PCI_CHIP_MACH64GZ 0x475A
-#define PCI_CHIP_RV250_Id 0x4964
-#define PCI_CHIP_RV250_Ie 0x4965
-#define PCI_CHIP_RV250_If 0x4966
-#define PCI_CHIP_RV250_Ig 0x4967
-#define PCI_CHIP_R420_JH 0x4A48
-#define PCI_CHIP_R420_JI 0x4A49
-#define PCI_CHIP_R420_JJ 0x4A4A
-#define PCI_CHIP_R420_JK 0x4A4B
-#define PCI_CHIP_R420_JL 0x4A4C
-#define PCI_CHIP_R420_JM 0x4A4D
-#define PCI_CHIP_R420_JN 0x4A4E
-#define PCI_CHIP_R420_4A4F 0x4A4F
-#define PCI_CHIP_R420_JP 0x4A50
-#define PCI_CHIP_R420_4A54 0x4A54
-#define PCI_CHIP_R481_4B49 0x4B49
-#define PCI_CHIP_R481_4B4A 0x4B4A
-#define PCI_CHIP_R481_4B4B 0x4B4B
-#define PCI_CHIP_R481_4B4C 0x4B4C
-#define PCI_CHIP_MACH64LB 0x4C42
-#define PCI_CHIP_MACH64LD 0x4C44
-#define PCI_CHIP_RAGE128LE 0x4C45
-#define PCI_CHIP_RAGE128LF 0x4C46
-#define PCI_CHIP_MACH64LG 0x4C47
-#define PCI_CHIP_MACH64LI 0x4C49
-#define PCI_CHIP_MACH64LM 0x4C4D
-#define PCI_CHIP_MACH64LN 0x4C4E
-#define PCI_CHIP_MACH64LP 0x4C50
-#define PCI_CHIP_MACH64LQ 0x4C51
-#define PCI_CHIP_MACH64LR 0x4C52
-#define PCI_CHIP_MACH64LS 0x4C53
-#define PCI_CHIP_RADEON_LW 0x4C57
-#define PCI_CHIP_RADEON_LX 0x4C58
-#define PCI_CHIP_RADEON_LY 0x4C59
-#define PCI_CHIP_RADEON_LZ 0x4C5A
-#define PCI_CHIP_RV250_Ld 0x4C64
-#define PCI_CHIP_RV250_Le 0x4C65
-#define PCI_CHIP_RV250_Lf 0x4C66
-#define PCI_CHIP_RV250_Lg 0x4C67
-#define PCI_CHIP_RV250_Ln 0x4C6E
-#define PCI_CHIP_RAGE128MF 0x4D46
-#define PCI_CHIP_RAGE128ML 0x4D4C
-#define PCI_CHIP_R300_ND 0x4E44
-#define PCI_CHIP_R300_NE 0x4E45
-#define PCI_CHIP_R300_NF 0x4E46
-#define PCI_CHIP_R300_NG 0x4E47
-#define PCI_CHIP_R350_NH 0x4E48
-#define PCI_CHIP_R350_NI 0x4E49
-#define PCI_CHIP_R360_NJ 0x4E4A
-#define PCI_CHIP_R350_NK 0x4E4B
-#define PCI_CHIP_RV350_NP 0x4E50
-#define PCI_CHIP_RV350_NQ 0x4E51
-#define PCI_CHIP_RV350_NR 0x4E52
-#define PCI_CHIP_RV350_NS 0x4E53
-#define PCI_CHIP_RV350_NT 0x4E54
-#define PCI_CHIP_RV350_NV 0x4E56
-#define PCI_CHIP_RAGE128PA 0x5041
-#define PCI_CHIP_RAGE128PB 0x5042
-#define PCI_CHIP_RAGE128PC 0x5043
-#define PCI_CHIP_RAGE128PD 0x5044
-#define PCI_CHIP_RAGE128PE 0x5045
-#define PCI_CHIP_RAGE128PF 0x5046
-#define PCI_CHIP_RAGE128PG 0x5047
-#define PCI_CHIP_RAGE128PH 0x5048
-#define PCI_CHIP_RAGE128PI 0x5049
-#define PCI_CHIP_RAGE128PJ 0x504A
-#define PCI_CHIP_RAGE128PK 0x504B
-#define PCI_CHIP_RAGE128PL 0x504C
-#define PCI_CHIP_RAGE128PM 0x504D
-#define PCI_CHIP_RAGE128PN 0x504E
-#define PCI_CHIP_RAGE128PO 0x504F
-#define PCI_CHIP_RAGE128PP 0x5050
-#define PCI_CHIP_RAGE128PQ 0x5051
-#define PCI_CHIP_RAGE128PR 0x5052
-#define PCI_CHIP_RAGE128PS 0x5053
-#define PCI_CHIP_RAGE128PT 0x5054
-#define PCI_CHIP_RAGE128PU 0x5055
-#define PCI_CHIP_RAGE128PV 0x5056
-#define PCI_CHIP_RAGE128PW 0x5057
-#define PCI_CHIP_RAGE128PX 0x5058
-#define PCI_CHIP_RADEON_QD 0x5144
-#define PCI_CHIP_RADEON_QE 0x5145
-#define PCI_CHIP_RADEON_QF 0x5146
-#define PCI_CHIP_RADEON_QG 0x5147
-#define PCI_CHIP_R200_QH 0x5148
-#define PCI_CHIP_R200_QI 0x5149
-#define PCI_CHIP_R200_QJ 0x514A
-#define PCI_CHIP_R200_QK 0x514B
-#define PCI_CHIP_R200_QL 0x514C
-#define PCI_CHIP_R200_QM 0x514D
-#define PCI_CHIP_R200_QN 0x514E
-#define PCI_CHIP_R200_QO 0x514F
-#define PCI_CHIP_RV200_QW 0x5157
-#define PCI_CHIP_RV200_QX 0x5158
-#define PCI_CHIP_RV100_QY 0x5159
-#define PCI_CHIP_RV100_QZ 0x515A
-#define PCI_CHIP_RN50_515E 0x515E
-#define PCI_CHIP_RAGE128RE 0x5245
-#define PCI_CHIP_RAGE128RF 0x5246
-#define PCI_CHIP_RAGE128RG 0x5247
-#define PCI_CHIP_RAGE128RK 0x524B
-#define PCI_CHIP_RAGE128RL 0x524C
-#define PCI_CHIP_RAGE128SE 0x5345
-#define PCI_CHIP_RAGE128SF 0x5346
-#define PCI_CHIP_RAGE128SG 0x5347
-#define PCI_CHIP_RAGE128SH 0x5348
-#define PCI_CHIP_RAGE128SK 0x534B
-#define PCI_CHIP_RAGE128SL 0x534C
-#define PCI_CHIP_RAGE128SM 0x534D
-#define PCI_CHIP_RAGE128SN 0x534E
-#define PCI_CHIP_RAGE128TF 0x5446
-#define PCI_CHIP_RAGE128TL 0x544C
-#define PCI_CHIP_RAGE128TR 0x5452
-#define PCI_CHIP_RAGE128TS 0x5453
-#define PCI_CHIP_RAGE128TT 0x5454
-#define PCI_CHIP_RAGE128TU 0x5455
-#define PCI_CHIP_RV370_5460 0x5460
-#define PCI_CHIP_RV370_5461 0x5461
-#define PCI_CHIP_RV370_5462 0x5462
-#define PCI_CHIP_RV370_5463 0x5463
-#define PCI_CHIP_RV370_5464 0x5464
-#define PCI_CHIP_RV370_5465 0x5465
-#define PCI_CHIP_RV370_5466 0x5466
-#define PCI_CHIP_RV370_5467 0x5467
-#define PCI_CHIP_R423_UH 0x5548
-#define PCI_CHIP_R423_UI 0x5549
-#define PCI_CHIP_R423_UJ 0x554A
-#define PCI_CHIP_R423_UK 0x554B
-#define PCI_CHIP_R430_554C 0x554C
-#define PCI_CHIP_R430_554D 0x554D
-#define PCI_CHIP_R430_554E 0x554E
-#define PCI_CHIP_R430_554F 0x554F
-#define PCI_CHIP_R423_5550 0x5550
-#define PCI_CHIP_R423_UQ 0x5551
-#define PCI_CHIP_R423_UR 0x5552
-#define PCI_CHIP_R423_UT 0x5554
-#define PCI_CHIP_RV410_564A 0x564A
-#define PCI_CHIP_RV410_564B 0x564B
-#define PCI_CHIP_RV410_564F 0x564F
-#define PCI_CHIP_RV410_5652 0x5652
-#define PCI_CHIP_RV410_5653 0x5653
-#define PCI_CHIP_MACH64VT 0x5654
-#define PCI_CHIP_MACH64VU 0x5655
-#define PCI_CHIP_MACH64VV 0x5656
-#define PCI_CHIP_RS300_5834 0x5834
-#define PCI_CHIP_RS300_5835 0x5835
-#define PCI_CHIP_RS300_5836 0x5836
-#define PCI_CHIP_RS300_5837 0x5837
-#define PCI_CHIP_RS480_5954 0x5954
-#define PCI_CHIP_RS480_5955 0x5955
-#define PCI_CHIP_RV280_5960 0x5960
-#define PCI_CHIP_RV280_5961 0x5961
-#define PCI_CHIP_RV280_5962 0x5962
-#define PCI_CHIP_RV280_5964 0x5964
-#define PCI_CHIP_RV280_5965 0x5965
-#define PCI_CHIP_RN50_5969 0x5969
-#define PCI_CHIP_RS482_5974 0x5974
-#define PCI_CHIP_RS485_5975 0x5975
-#define PCI_CHIP_RS400_5A41 0x5A41
-#define PCI_CHIP_RS400_5A42 0x5A42
-#define PCI_CHIP_RC410_5A61 0x5A61
-#define PCI_CHIP_RC410_5A62 0x5A62
-#define PCI_CHIP_RV370_5B60 0x5B60
-#define PCI_CHIP_RV370_5B61 0x5B61
-#define PCI_CHIP_RV370_5B62 0x5B62
-#define PCI_CHIP_RV370_5B63 0x5B63
-#define PCI_CHIP_RV370_5B64 0x5B64
-#define PCI_CHIP_RV370_5B65 0x5B65
-#define PCI_CHIP_RV370_5B66 0x5B66
-#define PCI_CHIP_RV370_5B67 0x5B67
-#define PCI_CHIP_RV280_5C61 0x5C61
-#define PCI_CHIP_RV280_5C63 0x5C63
-#define PCI_CHIP_R430_5D48 0x5D48
-#define PCI_CHIP_R430_5D49 0x5D49
-#define PCI_CHIP_R430_5D4A 0x5D4A
-#define PCI_CHIP_R480_5D4C 0x5D4C
-#define PCI_CHIP_R480_5D4D 0x5D4D
-#define PCI_CHIP_R480_5D4E 0x5D4E
-#define PCI_CHIP_R480_5D4F 0x5D4F
-#define PCI_CHIP_R480_5D50 0x5D50
-#define PCI_CHIP_R480_5D52 0x5D52
-#define PCI_CHIP_R423_5D57 0x5D57
-#define PCI_CHIP_RV410_5E48 0x5E48
-#define PCI_CHIP_RV410_5E4A 0x5E4A
-#define PCI_CHIP_RV410_5E4B 0x5E4B
-#define PCI_CHIP_RV410_5E4C 0x5E4C
-#define PCI_CHIP_RV410_5E4D 0x5E4D
-#define PCI_CHIP_RV410_5E4F 0x5E4F
-#define PCI_CHIP_RS350_7834 0x7834
-#define PCI_CHIP_RS350_7835 0x7835
+#include "ati_pciids_gen.h"
/* Misc */
#define PCI_CHIP_AMD761 0x700E
diff --git a/src/atividmem.c b/src/atividmem.c
index 8910c73..986ac0f 100644
--- a/src/atividmem.c
+++ b/src/atividmem.c
@@ -103,14 +103,12 @@ ATIUnmapLinear
ATIPtr pATI
)
{
- pciVideoPtr pVideo = pATI->PCIInfo;
-
if (pATI->pMemory)
{
#ifndef XSERVER_LIBPCIACCESS
xf86UnMapVidMem(iScreen, pATI->pMemory, pATI->LinearSize);
#else
- pci_device_unmap_range(pVideo, pATI->pMemory, pATI->LinearSize);
+ pci_device_unmap_range(pATI->PCIInfo, pATI->pMemory, pATI->LinearSize);
#endif
#if X_BYTE_ORDER != X_LITTLE_ENDIAN
@@ -120,7 +118,7 @@ ATIUnmapLinear
#ifndef XSERVER_LIBPCIACCESS
xf86UnMapVidMem(iScreen, pATI->pMemoryLE, pATI->LinearSize);
#else
- pci_device_unmap_range(pVideo, pATI->pMemoryLE, pATI->LinearSize);
+ pci_device_unmap_range(pATI->PCIInfo, pATI->pMemoryLE, pATI->LinearSize);
#endif
}
@@ -143,14 +141,12 @@ ATIUnmapMMIO
ATIPtr pATI
)
{
- pciVideoPtr pVideo = pATI->PCIInfo;
-
if (pATI->pMMIO)
{
#ifndef XSERVER_LIBPCIACCESS
xf86UnMapVidMem(iScreen, pATI->pMMIO, getpagesize());
#else
- pci_device_unmap_range(pVideo, pATI->pMMIO, getpagesize());
+ pci_device_unmap_range(pATI->PCIInfo, pATI->pMMIO, getpagesize());
#endif
}
@@ -169,14 +165,12 @@ ATIUnmapCursor
ATIPtr pATI
)
{
- pciVideoPtr pVideo = pATI->PCIInfo;
-
if (pATI->pCursorPage)
{
#ifndef XSERVER_LIBPCIACCESS
xf86UnMapVidMem(iScreen, pATI->pCursorPage, getpagesize());
#else
- pci_device_unmap_range(pVideo, pATI->pCursorPage, getpagesize());
+ pci_device_unmap_range(pATI->PCIInfo, pATI->pCursorPage, getpagesize());
#endif
}
diff --git a/src/pcidb/ati_pciids.csv b/src/pcidb/ati_pciids.csv
new file mode 100644
index 0000000..f201cc4
--- /dev/null
+++ b/src/pcidb/ati_pciids.csv
@@ -0,0 +1,220 @@
+"#pciid","define","family","mobility","igp","nocrtc2","Nointtvout","singledac","name"
+"0x3150","RV380_3150","RV380",1,,,,,"ATI Radeon Mobility X600 (M24) 3150 (PCIE)"
+"0x3152","RV380_3152","RV380",1,,,,,"ATI Radeon Mobility X300 (M24) 3152 (PCIE)"
+"0x3154","RV380_3154","RV380",1,,,,,"ATI FireGL M24 GL 3154 (PCIE)"
+"0x3E50","RV380_3E50","RV380",,,,,,"ATI Radeon X600 (RV380) 3E50 (PCIE)"
+"0x3E54","RV380_3E54","RV380",,,,,,"ATI FireGL V3200 (RV380) 3E54 (PCIE)"
+"0x4136","RS100_4136","RS100",,1,,,,"ATI Radeon IGP320 (A3) 4136"
+"0x4137","RS200_4137","RS200",,1,,,,"ATI Radeon IGP330/340/350 (A4) 4137"
+"0x4144","R300_AD","R300",,,,,,"ATI Radeon 9500 AD (AGP)"
+"0x4145","R300_AE","R300",,,,,,"ATI Radeon 9500 AE (AGP)"
+"0x4146","R300_AF","R300",,,,,,"ATI Radeon 9600TX AF (AGP)"
+"0x4147","R300_AG","R300",,,,,,"ATI FireGL Z1 AG (AGP)"
+"0x4148","R350_AH","R350",,,,,,"ATI Radeon 9800SE AH (AGP)"
+"0x4149","R350_AI","R350",,,,,,"ATI Radeon 9800 AI (AGP)"
+"0x414A","R350_AJ","R350",,,,,,"ATI Radeon 9800 AJ (AGP)"
+"0x414B","R350_AK","R350",,,,,,"ATI FireGL X2 AK (AGP)"
+"0x4150","RV350_AP","RV350",,,,,,"ATI Radeon 9600 AP (AGP)"
+"0x4151","RV350_AQ","RV350",,,,,,"ATI Radeon 9600SE AQ (AGP)"
+"0x4152","RV360_AR","RV350",,,,,,"ATI Radeon 9600XT AR (AGP)"
+"0x4153","RV350_AS","RV350",,,,,,"ATI Radeon 9600 AS (AGP)"
+"0x4154","RV350_AT","RV350",,,,,,"ATI FireGL T2 AT (AGP)"
+"0x4155","RV350_4155","RV350",,,,,,"ATI Radeon 9650"
+"0x4156","RV350_AV","RV350",,,,,,"ATI FireGL RV360 AV (AGP)"
+"0x4158","MACH32","MACH32",,,,,,
+"0x4237","RS250_4237","RS200",,1,,,,"ATI Radeon 7000 IGP (A4+) 4237"
+"0x4242","R200_BB","R200",,,,1,,"ATI Radeon 8500 AIW BB (AGP)"
+"0x4243","R200_BC","R200",,,,1,,"ATI Radeon 8500 AIW BC (AGP)"
+"0x4336","RS100_4336","RS100",1,1,,,,"ATI Radeon IGP320M (U1) 4336"
+"0x4337","RS200_4337","RS200",1,1,,,,"ATI Radeon IGP330M/340M/350M (U2) 4337"
+"0x4354","MACH64CT","MACH64",,,,,,
+"0x4358","MACH64CX","MACH64",,,,,,
+"0x4437","RS250_4437","RS200",1,1,,,,"ATI Radeon Mobility 7000 IGP 4437"
+"0x4554","MACH64ET","MACH64",,,,,,
+"0x4742","MACH64GB","MACH64",,,,,,
+"0x4744","MACH64GD","MACH64",,,,,,
+"0x4749","MACH64GI","MACH64",,,,,,
+"0x474C","MACH64GL","MACH64",,,,,,
+"0x474D","MACH64GM","MACH64",,,,,,
+"0x474E","MACH64GN","MACH64",,,,,,
+"0x474F","MACH64GO","MACH64",,,,,,
+"0x4750","MACH64GP","MACH64",,,,,,
+"0x4751","MACH64GQ","MACH64",,,,,,
+"0x4752","MACH64GR","MACH64",,,,,,
+"0x4753","MACH64GS","MACH64",,,,,,
+"0x4754","MACH64GT","MACH64",,,,,,
+"0x4755","MACH64GU","MACH64",,,,,,
+"0x4756","MACH64GV","MACH64",,,,,,
+"0x4757","MACH64GW","MACH64",,,,,,
+"0x4758","MACH64GX","MACH64",,,,,,
+"0x4759","MACH64GY","MACH64",,,,,,
+"0x475A","MACH64GZ","MACH64",,,,,,
+"0x4966","RV250_If","RV250",,,,,,"ATI Radeon 9000/PRO If (AGP/PCI)"
+"0x4967","RV250_Ig","RV250",,,,,,"ATI Radeon 9000 Ig (AGP/PCI)"
+"0x4A48","R420_JH","R420",,,,,,"ATI Radeon X800 (R420) JH (AGP)"
+"0x4A49","R420_JI","R420",,,,,,"ATI Radeon X800PRO (R420) JI (AGP)"
+"0x4A4A","R420_JJ","R420",,,,,,"ATI Radeon X800SE (R420) JJ (AGP)"
+"0x4A4B","R420_JK","R420",,,,,,"ATI Radeon X800 (R420) JK (AGP)"
+"0x4A4C","R420_JL","R420",,,,,,"ATI Radeon X800 (R420) JL (AGP)"
+"0x4A4D","R420_JM","R420",,,,,,"ATI FireGL X3 (R420) JM (AGP)"
+"0x4A4E","R420_JN","R420",1,,,,,"ATI Radeon Mobility 9800 (M18) JN (AGP)"
+"0x4A4F","R420_4A4F","R420",,,,,,"ATI Radeon X800 SE (R420) (AGP)"
+"0x4A50","R420_JP","R420",,,,,,"ATI Radeon X800XT (R420) JP (AGP)"
+"0x4B49","R481_4B49","R420",,,,,,"ATI Radeon X850 XT (R480) (AGP)"
+"0x4B4A","R481_4B4A","R420",,,,,,"ATI Radeon X850 SE (R480) (AGP)"
+"0x4B4B","R481_4B4B","R420",,,,,,"ATI Radeon X850 PRO (R480) (AGP)"
+"0x4B4C","R481_4B4C","R420",,,,,,"ATI Radeon X850 XT PE (R480) (AGP)"
+"0x4C42","MACH64LB","MACH64",,,,,,
+"0x4C44","MACH64LD","MACH64",,,,,,
+"0x4C45","RAGE128LE","R128",,,,,,
+"0x4C46","RAGE128LF","R128",,,,,,
+"0x4C47","MACH64LG","MACH64",,,,,,
+"0x4C49","MACH64LI","MACH64",,,,,,
+"0x4C4D","MACH64LM","MACH64",,,,,,
+"0x4C4E","MACH64LN","MACH64",,,,,,
+"0x4C50","MACH64LP","MACH64",,,,,,
+"0x4C51","MACH64LQ","MACH64",,,,,,
+"0x4C52","MACH64LR","MACH64",,,,,,
+"0x4C53","MACH64LS","MACH64",,,,,,
+"0x4C57","RADEON_LW","RV200",1,,,,,"ATI Radeon Mobility M7 LW (AGP)"
+"0x4C58","RADEON_LX","RV200",1,,,,,"ATI Mobility FireGL 7800 M7 LX (AGP)"
+"0x4C59","RADEON_LY","RV100",1,,,,,"ATI Radeon Mobility M6 LY (AGP)"
+"0x4C5A","RADEON_LZ","RV100",1,,,,,"ATI Radeon Mobility M6 LZ (AGP)"
+"0x4C64","RV250_Ld","RV250",1,,,,,"ATI FireGL Mobility 9000 (M9) Ld (AGP)"
+"0x4C66","RV250_Lf","RV250",1,,,,,"ATI Radeon Mobility 9000 (M9) Lf (AGP)"
+"0x4C67","RV250_Lg","RV250",1,,,,,"ATI Radeon Mobility 9000 (M9) Lg (AGP)"
+"0x4D46","RAGE128MF","R128",,,,,,
+"0x4D4C","RAGE128ML","R128",,,,,,
+"0x4E44","R300_ND","R300",,,,,,"ATI Radeon 9700 Pro ND (AGP)"
+"0x4E45","R300_NE","R300",,,,,,"ATI Radeon 9700/9500Pro NE (AGP)"
+"0x4E46","R300_NF","R300",,,,,,"ATI Radeon 9600TX NF (AGP)"
+"0x4E47","R300_NG","R300",,,,,,"ATI FireGL X1 NG (AGP)"
+"0x4E48","R350_NH","R350",,,,,,"ATI Radeon 9800PRO NH (AGP)"
+"0x4E49","R350_NI","R350",,,,,,"ATI Radeon 9800 NI (AGP)"
+"0x4E4A","R360_NJ","R350",,,,,,"ATI FireGL X2 NK (AGP)"
+"0x4E4B","R350_NK","R350",,,,,,"ATI Radeon 9800XT NJ (AGP)"
+"0x4E50","RV350_NP","RV350",1,,,,,"ATI Radeon Mobility 9600/9700 (M10/M11) NP (AGP)"
+"0x4E51","RV350_NQ","RV350",1,,,,,"ATI Radeon Mobility 9600 (M10) NQ (AGP)"
+"0x4E52","RV350_NR","RV350",1,,,,,"ATI Radeon Mobility 9600 (M11) NR (AGP)"
+"0x4E53","RV350_NS","RV350",1,,,,,"ATI Radeon Mobility 9600 (M10) NS (AGP)"
+"0x4E54","RV350_NT","RV350",1,,,,,"ATI FireGL Mobility T2 (M10) NT (AGP)"
+"0x4E56","RV350_NV","RV350",1,,,,,"ATI FireGL Mobility T2e (M11) NV (AGP)"
+"0x5041","RAGE128PA","R128",,,,,,
+"0x5042","RAGE128PB","R128",,,,,,
+"0x5043","RAGE128PC","R128",,,,,,
+"0x5044","RAGE128PD","R128",,,,,,
+"0x5045","RAGE128PE","R128",,,,,,
+"0x5046","RAGE128PF","R128",,,,,,
+"0x5047","RAGE128PG","R128",,,,,,
+"0x5048","RAGE128PH","R128",,,,,,
+"0x5049","RAGE128PI","R128",,,,,,
+"0x504A","RAGE128PJ","R128",,,,,,
+"0x504B","RAGE128PK","R128",,,,,,
+"0x504C","RAGE128PL","R128",,,,,,
+"0x504D","RAGE128PM","R128",,,,,,
+"0x504E","RAGE128PN","R128",,,,,,
+"0x504F","RAGE128PO","R128",,,,,,
+"0x5050","RAGE128PP","R128",,,,,,
+"0x5051","RAGE128PQ","R128",,,,,,
+"0x5052","RAGE128PR","R128",,,,,,
+"0x5053","RAGE128PS","R128",,,,,,
+"0x5054","RAGE128PT","R128",,,,,,
+"0x5055","RAGE128PU","R128",,,,,,
+"0x5056","RAGE128PV","R128",,,,,,
+"0x5057","RAGE128PW","R128",,,,,,
+"0x5058","RAGE128PX","R128",,,,,,
+"0x5144","RADEON_QD","RADEON",,,1,1,,"ATI Radeon QD (AGP)"
+"0x5145","RADEON_QE","RADEON",,,1,1,,"ATI Radeon QE (AGP)"
+"0x5146","RADEON_QF","RADEON",,,1,1,,"ATI Radeon QF (AGP)"
+"0x5147","RADEON_QG","RADEON",,,1,1,,"ATI Radeon QG (AGP)"
+"0x5148","R200_QH","R200",,,,1,,"ATI FireGL 8700/8800 QH (AGP)"
+"0x514C","R200_QL","R200",,,,1,,"ATI Radeon 8500 QL (AGP)"
+"0x514D","R200_QM","R200",,,,1,,"ATI Radeon 9100 QM (AGP)"
+"0x5157","RV200_QW","RV200",,,,,,"ATI Radeon 7500 QW (AGP/PCI)"
+"0x5158","RV200_QX","RV200",,,,,,"ATI Radeon 7500 QX (AGP/PCI)"
+"0x5159","RV100_QY","RV100",,,,,,"ATI Radeon VE/7000 QY (AGP/PCI)"
+"0x515A","RV100_QZ","RV100",,,,,,"ATI Radeon VE/7000 QZ (AGP/PCI)"
+"0x515E","RN50_515E","RV100",,,1,,,"ATI ES1000 515E (PCI)"
+"0x5245","RAGE128RE","R128",,,,,,
+"0x5246","RAGE128RF","R128",,,,,,
+"0x5247","RAGE128RG","R128",,,,,,
+"0x524B","RAGE128RK","R128",,,,,,
+"0x524C","RAGE128RL","R128",,,,,,
+"0x5345","RAGE128SE","R128",,,,,,
+"0x5346","RAGE128SF","R128",,,,,,
+"0x5347","RAGE128SG","R128",,,,,,
+"0x5348","RAGE128SH","R128",,,,,,
+"0x534B","RAGE128SK","R128",,,,,,
+"0x534C","RAGE128SL","R128",,,,,,
+"0x534D","RAGE128SM","R128",,,,,,
+"0x534E","RAGE128SN","R128",,,,,,
+"0x5446","RAGE128TF","R128",,,,,,
+"0x544C","RAGE128TL","R128",,,,,,
+"0x5452","RAGE128TR","R128",,,,,,
+"0x5453","RAGE128TS","R128",,,,,,
+"0x5454","RAGE128TT","R128",,,,,,
+"0x5455","RAGE128TU","R128",,,,,,
+"0x5460","RV370_5460","RV380",1,,,,,"ATI Radeon Mobility X300 (M22) 5460 (PCIE)"
+"0x5462","RV370_5462","RV380",1,,,,,"ATI Radeon Mobility X600 SE (M24C) 5462 (PCIE)"
+"0x5464","RV370_5464","RV380",1,,,,,"ATI FireGL M22 GL 5464 (PCIE)"
+"0x5548","R423_UH","R420",,,,,,"ATI Radeon X800 (R423) UH (PCIE)"
+"0x5549","R423_UI","R420",,,,,,"ATI Radeon X800PRO (R423) UI (PCIE)"
+"0x554A","R423_UJ","R420",,,,,,"ATI Radeon X800LE (R423) UJ (PCIE)"
+"0x554B","R423_UK","R420",,,,,,"ATI Radeon X800SE (R423) UK (PCIE)"
+"0x554C","R430_554C","R420",,,,,,"ATI Radeon X800 XTP (R430) (PCIE)"
+"0x554D","R430_554D","R420",,,,,,"ATI Radeon X800 XL (R430) (PCIE)"
+"0x554E","R430_554E","R420",,,,,,"ATI Radeon X800 SE (R430) (PCIE)"
+"0x554F","R430_554F","R420",,,,,,"ATI Radeon X800 (R430) (PCIE)"
+"0x5550","R423_5550","R420",,,,,,"ATI FireGL V7100 (R423) (PCIE)"
+"0x5551","R423_UQ","R420",,,,,,"ATI FireGL V5100 (R423) UQ (PCIE)"
+"0x5552","R423_UR","R420",,,,,,"ATI FireGL unknown (R423) UR (PCIE)"
+"0x5554","R423_UT","R420",,,,,,"ATI FireGL unknown (R423) UT (PCIE)"
+"0x564A","RV410_564A","RV410",1,,,,,"ATI Mobility FireGL V5000 (M26) (PCIE)"
+"0x564B","RV410_564B","RV410",1,,,,,"ATI Mobility FireGL V5000 (M26) (PCIE)"
+"0x564F","RV410_564F","RV410",1,,,,,"ATI Mobility Radeon X700 XL (M26) (PCIE)"
+"0x5652","RV410_5652","RV410",1,,,,,"ATI Mobility Radeon X700 (M26) (PCIE)"
+"0x5653","RV410_5653","RV410",1,,,,,"ATI Mobility Radeon X700 (M26) (PCIE)"
+"0x5654","MACH64VT","MACH64",,,,,,
+"0x5655","MACH64VU","MACH64",,,,,,
+"0x5656","MACH64VV","MACH64",,,,,,
+"0x5834","RS300_5834","RS300",,1,,,1,"ATI Radeon 9100 IGP (A5) 5834"
+"0x5835","RS300_5835","RS300",1,1,,,1,"ATI Radeon Mobility 9100 IGP (U3) 5835"
+"0x5954","RS480_5954","RS400",,1,,,1,"ATI Radeon XPRESS 200 5954 (PCIE)"
+"0x5955","RS480_5955","RS400",1,1,,,1,"ATI Radeon XPRESS 200M 5955 (PCIE)"
+"0x5960","RV280_5960","RV280",,,,,,"ATI Radeon 9250 5960 (AGP)"
+"0x5961","RV280_5961","RV280",,,,,,"ATI Radeon 9200 5961 (AGP)"
+"0x5962","RV280_5962","RV280",,,,,,"ATI Radeon 9200 5962 (AGP)"
+"0x5964","RV280_5964","RV280",,,,,,"ATI Radeon 9200SE 5964 (AGP)"
+"0x5965","RV280_5965","RV280",,,,,,"ATI FireMV 2200 (PCI)"
+"0x5969","RN50_5969","RV100",,,1,,,"ATI ES1000 5969 (PCI)"
+"0x5974","RS482_5974","RS400",,1,,,1,"ATI Radeon XPRESS 200 5974 (PCIE)"
+"0x5975","RS485_5975","RS400",1,1,,,1,"ATI Radeon XPRESS 200M 5975 (PCIE)"
+"0x5A41","RS400_5A41","RS400",,1,,,1,"ATI Radeon XPRESS 200 5A41 (PCIE)"
+"0x5A42","RS400_5A42","RS400",1,1,,,1,"ATI Radeon XPRESS 200M 5A42 (PCIE)"
+"0x5A61","RC410_5A61","RS400",,1,,,1,"ATI Radeon XPRESS 200 5A61 (PCIE)"
+"0x5A62","RC410_5A62","RS400",1,1,,,1,"ATI Radeon XPRESS 200M 5A62 (PCIE)"
+"0x5B60","RV370_5B60","RV380",,,,,,"ATI Radeon X300 (RV370) 5B60 (PCIE)"
+"0x5B62","RV370_5B62","RV380",,,,,,"ATI Radeon X600 (RV370) 5B62 (PCIE)"
+"0x5B63","RV370_5B63","RV380",,,,,,"ATI Radeon X550 (RV370) 5B63 (PCIE)"
+"0x5B64","RV370_5B64","RV380",,,,,,"ATI FireGL V3100 (RV370) 5B64 (PCIE)"
+"0x5B65","RV370_5B65","RV380",,,,,,"ATI FireMV 2200 PCIE (RV370) 5B65 (PCIE)"
+"0x5C61","RV280_5C61","RV280",1,,,,,"ATI Radeon Mobility 9200 (M9+) 5C61 (AGP)"
+"0x5C63","RV280_5C63","RV280",1,,,,,"ATI Radeon Mobility 9200 (M9+) 5C63 (AGP)"
+"0x5D48","R430_5D48","R420",1,,,,,"ATI Mobility Radeon X800 XT (M28) (PCIE)"
+"0x5D49","R430_5D49","R420",1,,,,,"ATI Mobility FireGL V5100 (M28) (PCIE)"
+"0x5D4A","R430_5D4A","R420",1,,,,,"ATI Mobility Radeon X800 (M28) (PCIE)"
+"0x5D4C","R480_5D4C","R420",,,,,,"ATI Radeon X850 5D4C (PCIE)"
+"0x5D4D","R480_5D4D","R420",,,,,,"ATI Radeon X850 XT PE (R480) (PCIE)"
+"0x5D4E","R480_5D4E","R420",,,,,,"ATI Radeon X850 SE (R480) (PCIE)"
+"0x5D4F","R480_5D4F","R420",,,,,,"ATI Radeon X850 PRO (R480) (PCIE)"
+"0x5D50","R480_5D50","R420",,,,,,"ATI unknown Radeon / FireGL (R480) 5D50 (PCIE)"
+"0x5D52","R480_5D52","R420",,,,,,"ATI Radeon X850 XT (R480) (PCIE)"
+"0x5D57","R423_5D57","R420",,,,,,"ATI Radeon X800XT (R423) 5D57 (PCIE)"
+"0x5E48","RV410_5E48","RV410",,,,,,"ATI FireGL V5000 (RV410) (PCIE)"
+"0x5E4A","RV410_5E4A","RV410",,,,,,"ATI Radeon X700 XT (RV410) (PCIE)"
+"0x5E4B","RV410_5E4B","RV410",,,,,,"ATI Radeon X700 PRO (RV410) (PCIE)"
+"0x5E4C","RV410_5E4C","RV410",,,,,,"ATI Radeon X700 SE (RV410) (PCIE)"
+"0x5E4D","RV410_5E4D","RV410",,,,,,"ATI Radeon X700 (RV410) (PCIE)"
+"0x5E4F","RV410_5E4F","RV410",,,,,,"ATI Radeon X700 SE (RV410) (PCIE)"
+"0x7834","RS350_7834","RS300",,1,,,,"ATI Radeon 9100 PRO IGP 7834"
+"0x7835","RS350_7835","RS300",1,1,,,,"ATI Radeon Mobility 9200 IGP 7835"
diff --git a/src/pcidb/parse_pci_ids.pl b/src/pcidb/parse_pci_ids.pl
new file mode 100755
index 0000000..e6eac76
--- /dev/null
+++ b/src/pcidb/parse_pci_ids.pl
@@ -0,0 +1,94 @@
+#!/usr/bin/perl
+#
+# Copyright 2007 Red Hat Inc.
+# This crappy script written by Dave Airlie to avoid hassle of adding
+# ids in every place.
+#
+use strict;
+use warnings;
+use Text::CSV_XS;
+
+my $file = $ARGV[0];
+
+my $atioutfile = 'ati_pciids_gen.h';
+my $radeonpcichipsetfile = 'radeon_pci_chipset_gen.h';
+my $radeonchipsetfile = 'radeon_chipset_gen.h';
+my $radeonchipinfofile = 'radeon_chipinfo_gen.h';
+
+my $csv = Text::CSV_XS->new();
+
+open (CSV, "<", $file) or die $!;
+
+open (ATIOUT, ">", $atioutfile) or die;
+open (PCICHIPSET, ">", $radeonpcichipsetfile) or die;
+open (RADEONCHIPSET, ">", $radeonchipsetfile) or die;
+open (RADEONCHIPINFO, ">", $radeonchipinfofile) or die;
+
+print RADEONCHIPSET "/* This file is autogenerated please do not edit */\n";
+print RADEONCHIPSET "static SymTabRec RADEONChipsets[] = {\n";
+print PCICHIPSET "/* This file is autogenerated please do not edit */\n";
+print PCICHIPSET "PciChipsets RADEONPciChipsets[] = {\n";
+print RADEONCHIPINFO "/* This file is autogenerated please do not edit */\n";
+print RADEONCHIPINFO "RADEONCardInfo RADEONCards[] = {\n";
+while (<CSV>) {
+ if ($csv->parse($_)) {
+ my @columns = $csv->fields();
+
+ if ((substr($columns[0], 0, 1) ne "#")) {
+
+ print ATIOUT "#define PCI_CHIP_$columns[1] $columns[0]\n";
+
+ if (($columns[2] ne "R128") && ($columns[2] ne "MACH64") && ($columns[2] ne "MACH32")) {
+ print PCICHIPSET " { PCI_CHIP_$columns[1], PCI_CHIP_$columns[1], RES_SHARED_VGA },\n";
+
+ print RADEONCHIPSET " { PCI_CHIP_$columns[1], \"$columns[8]\" },\n";
+
+ print RADEONCHIPINFO " { $columns[0], CHIP_FAMILY_$columns[2], ";
+
+ if ($columns[3] eq "1") {
+ print RADEONCHIPINFO "1, ";
+ } else {
+ print RADEONCHIPINFO "0, ";
+ }
+
+ if ($columns[4] eq "1") {
+ print RADEONCHIPINFO "1, ";
+ } else {
+ print RADEONCHIPINFO "0, ";
+ }
+
+ if ($columns[5] eq "1") {
+ print RADEONCHIPINFO "1, ";
+ } else {
+ print RADEONCHIPINFO "0, ";
+ }
+
+ if ($columns[6] eq "1") {
+ print RADEONCHIPINFO "1, ";
+ } else {
+ print RADEONCHIPINFO "0, ";
+ }
+
+ if ($columns[7] eq "1") {
+ print RADEONCHIPINFO "1 ";
+ } else {
+ print RADEONCHIPINFO "0 ";
+ }
+
+ print RADEONCHIPINFO "},\n";
+ }
+ }
+ } else {
+ my $err = $csv->error_input;
+ print "Failed to parse line: $err";
+ }
+}
+
+print RADEONCHIPINFO "};\n";
+print RADEONCHIPSET " { -1, NULL }\n};\n";
+print PCICHIPSET " { -1, -1, RES_UNDEFINED }\n};\n";
+close CSV;
+close ATIOUT;
+close PCICHIPSET;
+close RADEONCHIPSET;
+close RADEONCHIPINFO;
diff --git a/src/r128_dri.c b/src/r128_dri.c
index fc91421..edb77ba 100644
--- a/src/r128_dri.c
+++ b/src/r128_dri.c
@@ -80,9 +80,9 @@ static Bool R128InitVisualConfigs(ScreenPtr pScreen)
ScrnInfoPtr pScrn = xf86Screens[pScreen->myNum];
R128InfoPtr info = R128PTR(pScrn);
int numConfigs = 0;
- __GLXvisualConfig *pConfigs = 0;
- R128ConfigPrivPtr pR128Configs = 0;
- R128ConfigPrivPtr *pR128ConfigPtrs = 0;
+ __GLXvisualConfig *pConfigs = NULL;
+ R128ConfigPrivPtr pR128Configs = NULL;
+ R128ConfigPrivPtr *pR128ConfigPtrs = NULL;
int i, accum, stencil, db;
switch (info->CurrentLayout.pixel_code) {
diff --git a/src/r128_probe.c b/src/r128_probe.c
index b2298df..0be21e8 100644
--- a/src/r128_probe.c
+++ b/src/r128_probe.c
@@ -193,7 +193,7 @@ R128Probe(DriverPtr drv, int flags)
pScrn = NULL;
if((pScrn = xf86ConfigPciEntity(pScrn, 0, usedChips[i],
- R128PciChipsets, 0, 0, 0, 0, 0)))
+ R128PciChipsets, NULL, NULL, NULL, NULL, NULL)))
{
pScrn->driverVersion = R128_VERSION_CURRENT;
pScrn->driverName = R128_DRIVER_NAME;
diff --git a/src/radeon.h b/src/radeon.h
index 532f04c..03db360 100644
--- a/src/radeon.h
+++ b/src/radeon.h
@@ -158,7 +158,9 @@ typedef enum {
OPTION_MAC_MODEL,
#endif
OPTION_DEFAULT_TMDS_PLL,
- OPTION_TVDAC_LOAD_DETECT
+ OPTION_TVDAC_LOAD_DETECT,
+ OPTION_FORCE_TVOUT,
+ OPTION_TVSTD
} RADEONOpts;
@@ -286,6 +288,7 @@ typedef struct {
CARD32 dot_clock_freq;
CARD32 pll_output_freq;
int feedback_div;
+ int reference_div;
int post_div;
/* PLL registers */
@@ -298,6 +301,7 @@ typedef struct {
CARD32 dot_clock_freq_2;
CARD32 pll_output_freq_2;
int feedback_div_2;
+ int reference_div_2;
int post_div_2;
/* PLL2 registers */
@@ -362,12 +366,24 @@ typedef struct {
} RADEONSaveRec, *RADEONSavePtr;
+#define RADEON_PLL_USE_BIOS_DIVS (1 << 0)
+#define RADEON_PLL_NO_ODD_POST_DIV (1 << 1)
+#define RADEON_PLL_USE_REF_DIV (1 << 2)
+
typedef struct {
CARD16 reference_freq;
CARD16 reference_div;
CARD32 min_pll_freq;
CARD32 max_pll_freq;
CARD16 xclk;
+
+ CARD32 min_ref_div;
+ CARD32 max_ref_div;
+ CARD32 min_feedback_div;
+ CARD32 max_feedback_div;
+ CARD32 pll_in_min;
+ CARD32 pll_in_max;
+ CARD32 best_vco;
} RADEONPLLRec, *RADEONPLLPtr;
typedef struct {
@@ -428,12 +444,22 @@ typedef enum {
CHIP_ERRATA_PLL_DELAY = 0x00000004
} RADEONErrata;
+typedef enum {
+ RADEON_DVOCHIP_NONE,
+ RADEON_SIL_164,
+ RADEON_SIL_1178
+} RADEONExtTMDSChip;
+
#if defined(__powerpc__)
typedef enum {
- RADEON_MAC_IBOOK = 0x00000001,
- RADEON_MAC_POWERBOOK_DL = 0x00000002,
- RADEON_MAC_POWERBOOK = 0x00000004,
- RADEON_MAC_MINI = 0x00000008
+ RADEON_MAC_NONE,
+ RADEON_MAC_IBOOK,
+ RADEON_MAC_POWERBOOK_EXTERNAL,
+ RADEON_MAC_POWERBOOK_INTERNAL,
+ RADEON_MAC_POWERBOOK_VGA,
+ RADEON_MAC_MINI_EXTERNAL,
+ RADEON_MAC_MINI_INTERNAL,
+ RADEON_MAC_IMAC_G5_ISIGHT
} RADEONMacModel;
#endif
@@ -444,6 +470,16 @@ typedef enum {
} RADEONCardType;
typedef struct {
+ CARD32 pci_device_id;
+ RADEONChipFamily chip_family;
+ int mobility;
+ int igp;
+ int nocrtc2;
+ int nointtvout;
+ int singledac;
+} RADEONCardInfo;
+
+typedef struct {
EntityInfoPtr pEnt;
pciVideoPtr PciInfo;
PCITAG PciTag;
@@ -525,10 +561,6 @@ typedef struct {
#endif
Bool accelOn;
xf86CursorInfoPtr cursor;
- CARD32 cursor_offset;
-#ifdef USE_XAA
- unsigned long cursor_end;
-#endif
Bool allowColorTiling;
Bool tilingEnabled; /* mirror of sarea->tiling_enabled */
#ifdef ARGB_CURSOR
@@ -816,6 +848,15 @@ typedef struct {
#if defined(__powerpc__)
RADEONMacModel MacModel;
#endif
+ RADEONExtTMDSChip ext_tmds_chip;
+
+ /* output enable masks for outputs shared across connectors */
+ int output_crt1;
+ int output_crt2;
+ int output_dfp1;
+ int output_dfp2;
+ int output_lcd1;
+ int output_tv1;
Rotation rotation;
void (*PointerMoved)(int, int, int);
diff --git a/src/radeon_accel.c b/src/radeon_accel.c
index 6028aff..ed7d1e9 100644
--- a/src/radeon_accel.c
+++ b/src/radeon_accel.c
@@ -136,8 +136,8 @@ void RADEONWaitForFifoFunction(ScrnInfoPtr pScrn, int entries)
}
xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG,
"FIFO timed out: %u entries, stat=0x%08x\n",
- INREG(RADEON_RBBM_STATUS) & RADEON_RBBM_FIFOCNT_MASK,
- INREG(RADEON_RBBM_STATUS));
+ (unsigned int)INREG(RADEON_RBBM_STATUS) & RADEON_RBBM_FIFOCNT_MASK,
+ (unsigned int)INREG(RADEON_RBBM_STATUS));
xf86DrvMsg(pScrn->scrnIndex, X_ERROR,
"FIFO timed out, resetting engine...\n");
RADEONEngineReset(pScrn);
@@ -168,7 +168,7 @@ void RADEONEngineFlush(ScrnInfoPtr pScrn)
if (i == RADEON_TIMEOUT) {
xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG,
"DC flush timeout: %x\n",
- INREG(RADEON_RB3D_DSTCACHE_CTLSTAT));
+ (unsigned int)INREG(RADEON_RB3D_DSTCACHE_CTLSTAT));
}
}
diff --git a/src/radeon_bios.c b/src/radeon_bios.c
index 1b46746..d150c4b 100644
--- a/src/radeon_bios.c
+++ b/src/radeon_bios.c
@@ -48,13 +48,12 @@ Bool RADEONGetBIOSInfo(ScrnInfoPtr pScrn, xf86Int10InfoPtr pInt10)
int tmp;
unsigned short dptr;
- if (!(info->VBIOS = xalloc(
#ifdef XSERVER_LIBPCIACCESS
- info->PciInfo->rom_size
+ info->VBIOS = xalloc(info->PciInfo->rom_size);
#else
- RADEON_VBIOS_SIZE
+ info->VBIOS = xalloc(RADEON_VBIOS_SIZE);
#endif
- ))) {
+ if (!info->VBIOS) {
xf86DrvMsg(pScrn->scrnIndex, X_ERROR,
"Cannot allocate space for hold Video BIOS!\n");
return FALSE;
@@ -469,15 +468,6 @@ Bool RADEONGetClockInfoFromBIOS (ScrnInfoPtr pScrn)
info->sclk = RADEON_BIOS32(pll_info_block + 8) / 100.0;
info->mclk = RADEON_BIOS32(pll_info_block + 12) / 100.0;
- if (info->sclk == 0) info->sclk = 200;
- if (info->mclk == 0) info->mclk = 200;
-
- xf86DrvMsg(pScrn->scrnIndex, X_INFO, "ref_freq: %d, min_pll: %u, "
- "max_pll: %u, xclk: %d, sclk: %f, mclk: %f\n",
- pll->reference_freq, (unsigned)pll->min_pll_freq,
- (unsigned)pll->max_pll_freq, pll->xclk, info->sclk,
- info->mclk);
-
} else {
pll_info_block = RADEON_BIOS16 (info->ROMHeaderStart + 0x30);
@@ -490,8 +480,17 @@ Bool RADEONGetClockInfoFromBIOS (ScrnInfoPtr pScrn)
info->sclk = RADEON_BIOS16(pll_info_block + 8) / 100.0;
info->mclk = RADEON_BIOS16(pll_info_block + 10) / 100.0;
}
+
+ if (info->sclk == 0) info->sclk = 200;
+ if (info->mclk == 0) info->mclk = 200;
}
+ xf86DrvMsg(pScrn->scrnIndex, X_INFO, "ref_freq: %d, min_pll: %u, "
+ "max_pll: %u, xclk: %d, sclk: %f, mclk: %f\n",
+ pll->reference_freq, (unsigned)pll->min_pll_freq,
+ (unsigned)pll->max_pll_freq, pll->xclk, info->sclk,
+ info->mclk);
+
return TRUE;
}
diff --git a/src/radeon_chipinfo_gen.h b/src/radeon_chipinfo_gen.h
new file mode 100644
index 0000000..a12b225
--- /dev/null
+++ b/src/radeon_chipinfo_gen.h
@@ -0,0 +1,140 @@
+/* This file is autogenerated please do not edit */
+RADEONCardInfo RADEONCards[] = {
+ { 0x3150, CHIP_FAMILY_RV380, 1, 0, 0, 0, 0 },
+ { 0x3152, CHIP_FAMILY_RV380, 1, 0, 0, 0, 0 },
+ { 0x3154, CHIP_FAMILY_RV380, 1, 0, 0, 0, 0 },
+ { 0x3E50, CHIP_FAMILY_RV380, 0, 0, 0, 0, 0 },
+ { 0x3E54, CHIP_FAMILY_RV380, 0, 0, 0, 0, 0 },
+ { 0x4136, CHIP_FAMILY_RS100, 0, 1, 0, 0, 0 },
+ { 0x4137, CHIP_FAMILY_RS200, 0, 1, 0, 0, 0 },
+ { 0x4144, CHIP_FAMILY_R300, 0, 0, 0, 0, 0 },
+ { 0x4145, CHIP_FAMILY_R300, 0, 0, 0, 0, 0 },
+ { 0x4146, CHIP_FAMILY_R300, 0, 0, 0, 0, 0 },
+ { 0x4147, CHIP_FAMILY_R300, 0, 0, 0, 0, 0 },
+ { 0x4148, CHIP_FAMILY_R350, 0, 0, 0, 0, 0 },
+ { 0x4149, CHIP_FAMILY_R350, 0, 0, 0, 0, 0 },
+ { 0x414A, CHIP_FAMILY_R350, 0, 0, 0, 0, 0 },
+ { 0x414B, CHIP_FAMILY_R350, 0, 0, 0, 0, 0 },
+ { 0x4150, CHIP_FAMILY_RV350, 0, 0, 0, 0, 0 },
+ { 0x4151, CHIP_FAMILY_RV350, 0, 0, 0, 0, 0 },
+ { 0x4152, CHIP_FAMILY_RV350, 0, 0, 0, 0, 0 },
+ { 0x4153, CHIP_FAMILY_RV350, 0, 0, 0, 0, 0 },
+ { 0x4154, CHIP_FAMILY_RV350, 0, 0, 0, 0, 0 },
+ { 0x4155, CHIP_FAMILY_RV350, 0, 0, 0, 0, 0 },
+ { 0x4156, CHIP_FAMILY_RV350, 0, 0, 0, 0, 0 },
+ { 0x4237, CHIP_FAMILY_RS200, 0, 1, 0, 0, 0 },
+ { 0x4242, CHIP_FAMILY_R200, 0, 0, 0, 1, 0 },
+ { 0x4243, CHIP_FAMILY_R200, 0, 0, 0, 1, 0 },
+ { 0x4336, CHIP_FAMILY_RS100, 1, 1, 0, 0, 0 },
+ { 0x4337, CHIP_FAMILY_RS200, 1, 1, 0, 0, 0 },
+ { 0x4437, CHIP_FAMILY_RS200, 1, 1, 0, 0, 0 },
+ { 0x4966, CHIP_FAMILY_RV250, 0, 0, 0, 0, 0 },
+ { 0x4967, CHIP_FAMILY_RV250, 0, 0, 0, 0, 0 },
+ { 0x4A48, CHIP_FAMILY_R420, 0, 0, 0, 0, 0 },
+ { 0x4A49, CHIP_FAMILY_R420, 0, 0, 0, 0, 0 },
+ { 0x4A4A, CHIP_FAMILY_R420, 0, 0, 0, 0, 0 },
+ { 0x4A4B, CHIP_FAMILY_R420, 0, 0, 0, 0, 0 },
+ { 0x4A4C, CHIP_FAMILY_R420, 0, 0, 0, 0, 0 },
+ { 0x4A4D, CHIP_FAMILY_R420, 0, 0, 0, 0, 0 },
+ { 0x4A4E, CHIP_FAMILY_R420, 1, 0, 0, 0, 0 },
+ { 0x4A4F, CHIP_FAMILY_R420, 0, 0, 0, 0, 0 },
+ { 0x4A50, CHIP_FAMILY_R420, 0, 0, 0, 0, 0 },
+ { 0x4B49, CHIP_FAMILY_R420, 0, 0, 0, 0, 0 },
+ { 0x4B4A, CHIP_FAMILY_R420, 0, 0, 0, 0, 0 },
+ { 0x4B4B, CHIP_FAMILY_R420, 0, 0, 0, 0, 0 },
+ { 0x4B4C, CHIP_FAMILY_R420, 0, 0, 0, 0, 0 },
+ { 0x4C57, CHIP_FAMILY_RV200, 1, 0, 0, 0, 0 },
+ { 0x4C58, CHIP_FAMILY_RV200, 1, 0, 0, 0, 0 },
+ { 0x4C59, CHIP_FAMILY_RV100, 1, 0, 0, 0, 0 },
+ { 0x4C5A, CHIP_FAMILY_RV100, 1, 0, 0, 0, 0 },
+ { 0x4C64, CHIP_FAMILY_RV250, 1, 0, 0, 0, 0 },
+ { 0x4C66, CHIP_FAMILY_RV250, 1, 0, 0, 0, 0 },
+ { 0x4C67, CHIP_FAMILY_RV250, 1, 0, 0, 0, 0 },
+ { 0x4E44, CHIP_FAMILY_R300, 0, 0, 0, 0, 0 },
+ { 0x4E45, CHIP_FAMILY_R300, 0, 0, 0, 0, 0 },
+ { 0x4E46, CHIP_FAMILY_R300, 0, 0, 0, 0, 0 },
+ { 0x4E47, CHIP_FAMILY_R300, 0, 0, 0, 0, 0 },
+ { 0x4E48, CHIP_FAMILY_R350, 0, 0, 0, 0, 0 },
+ { 0x4E49, CHIP_FAMILY_R350, 0, 0, 0, 0, 0 },
+ { 0x4E4A, CHIP_FAMILY_R350, 0, 0, 0, 0, 0 },
+ { 0x4E4B, CHIP_FAMILY_R350, 0, 0, 0, 0, 0 },
+ { 0x4E50, CHIP_FAMILY_RV350, 1, 0, 0, 0, 0 },
+ { 0x4E51, CHIP_FAMILY_RV350, 1, 0, 0, 0, 0 },
+ { 0x4E52, CHIP_FAMILY_RV350, 1, 0, 0, 0, 0 },
+ { 0x4E53, CHIP_FAMILY_RV350, 1, 0, 0, 0, 0 },
+ { 0x4E54, CHIP_FAMILY_RV350, 1, 0, 0, 0, 0 },
+ { 0x4E56, CHIP_FAMILY_RV350, 1, 0, 0, 0, 0 },
+ { 0x5144, CHIP_FAMILY_RADEON, 0, 0, 1, 1, 0 },
+ { 0x5145, CHIP_FAMILY_RADEON, 0, 0, 1, 1, 0 },
+ { 0x5146, CHIP_FAMILY_RADEON, 0, 0, 1, 1, 0 },
+ { 0x5147, CHIP_FAMILY_RADEON, 0, 0, 1, 1, 0 },
+ { 0x5148, CHIP_FAMILY_R200, 0, 0, 0, 1, 0 },
+ { 0x514C, CHIP_FAMILY_R200, 0, 0, 0, 1, 0 },
+ { 0x514D, CHIP_FAMILY_R200, 0, 0, 0, 1, 0 },
+ { 0x5157, CHIP_FAMILY_RV200, 0, 0, 0, 0, 0 },
+ { 0x5158, CHIP_FAMILY_RV200, 0, 0, 0, 0, 0 },
+ { 0x5159, CHIP_FAMILY_RV100, 0, 0, 0, 0, 0 },
+ { 0x515A, CHIP_FAMILY_RV100, 0, 0, 0, 0, 0 },
+ { 0x515E, CHIP_FAMILY_RV100, 0, 0, 1, 0, 0 },
+ { 0x5460, CHIP_FAMILY_RV380, 1, 0, 0, 0, 0 },
+ { 0x5462, CHIP_FAMILY_RV380, 1, 0, 0, 0, 0 },
+ { 0x5464, CHIP_FAMILY_RV380, 1, 0, 0, 0, 0 },
+ { 0x5548, CHIP_FAMILY_R420, 0, 0, 0, 0, 0 },
+ { 0x5549, CHIP_FAMILY_R420, 0, 0, 0, 0, 0 },
+ { 0x554A, CHIP_FAMILY_R420, 0, 0, 0, 0, 0 },
+ { 0x554B, CHIP_FAMILY_R420, 0, 0, 0, 0, 0 },
+ { 0x554C, CHIP_FAMILY_R420, 0, 0, 0, 0, 0 },
+ { 0x554D, CHIP_FAMILY_R420, 0, 0, 0, 0, 0 },
+ { 0x554E, CHIP_FAMILY_R420, 0, 0, 0, 0, 0 },
+ { 0x554F, CHIP_FAMILY_R420, 0, 0, 0, 0, 0 },
+ { 0x5550, CHIP_FAMILY_R420, 0, 0, 0, 0, 0 },
+ { 0x5551, CHIP_FAMILY_R420, 0, 0, 0, 0, 0 },
+ { 0x5552, CHIP_FAMILY_R420, 0, 0, 0, 0, 0 },
+ { 0x5554, CHIP_FAMILY_R420, 0, 0, 0, 0, 0 },
+ { 0x564A, CHIP_FAMILY_RV410, 1, 0, 0, 0, 0 },
+ { 0x564B, CHIP_FAMILY_RV410, 1, 0, 0, 0, 0 },
+ { 0x564F, CHIP_FAMILY_RV410, 1, 0, 0, 0, 0 },
+ { 0x5652, CHIP_FAMILY_RV410, 1, 0, 0, 0, 0 },
+ { 0x5653, CHIP_FAMILY_RV410, 1, 0, 0, 0, 0 },
+ { 0x5834, CHIP_FAMILY_RS300, 0, 1, 0, 0, 1 },
+ { 0x5835, CHIP_FAMILY_RS300, 1, 1, 0, 0, 1 },
+ { 0x5954, CHIP_FAMILY_RS400, 0, 1, 0, 0, 1 },
+ { 0x5955, CHIP_FAMILY_RS400, 1, 1, 0, 0, 1 },
+ { 0x5960, CHIP_FAMILY_RV280, 0, 0, 0, 0, 0 },
+ { 0x5961, CHIP_FAMILY_RV280, 0, 0, 0, 0, 0 },
+ { 0x5962, CHIP_FAMILY_RV280, 0, 0, 0, 0, 0 },
+ { 0x5964, CHIP_FAMILY_RV280, 0, 0, 0, 0, 0 },
+ { 0x5965, CHIP_FAMILY_RV280, 0, 0, 0, 0, 0 },
+ { 0x5969, CHIP_FAMILY_RV100, 0, 0, 1, 0, 0 },
+ { 0x5974, CHIP_FAMILY_RS400, 0, 1, 0, 0, 1 },
+ { 0x5975, CHIP_FAMILY_RS400, 1, 1, 0, 0, 1 },
+ { 0x5A41, CHIP_FAMILY_RS400, 0, 1, 0, 0, 1 },
+ { 0x5A42, CHIP_FAMILY_RS400, 1, 1, 0, 0, 1 },
+ { 0x5A61, CHIP_FAMILY_RS400, 0, 1, 0, 0, 1 },
+ { 0x5A62, CHIP_FAMILY_RS400, 1, 1, 0, 0, 1 },
+ { 0x5B60, CHIP_FAMILY_RV380, 0, 0, 0, 0, 0 },
+ { 0x5B62, CHIP_FAMILY_RV380, 0, 0, 0, 0, 0 },
+ { 0x5B63, CHIP_FAMILY_RV380, 0, 0, 0, 0, 0 },
+ { 0x5B64, CHIP_FAMILY_RV380, 0, 0, 0, 0, 0 },
+ { 0x5B65, CHIP_FAMILY_RV380, 0, 0, 0, 0, 0 },
+ { 0x5C61, CHIP_FAMILY_RV280, 1, 0, 0, 0, 0 },
+ { 0x5C63, CHIP_FAMILY_RV280, 1, 0, 0, 0, 0 },
+ { 0x5D48, CHIP_FAMILY_R420, 1, 0, 0, 0, 0 },
+ { 0x5D49, CHIP_FAMILY_R420, 1, 0, 0, 0, 0 },
+ { 0x5D4A, CHIP_FAMILY_R420, 1, 0, 0, 0, 0 },
+ { 0x5D4C, CHIP_FAMILY_R420, 0, 0, 0, 0, 0 },
+ { 0x5D4D, CHIP_FAMILY_R420, 0, 0, 0, 0, 0 },
+ { 0x5D4E, CHIP_FAMILY_R420, 0, 0, 0, 0, 0 },
+ { 0x5D4F, CHIP_FAMILY_R420, 0, 0, 0, 0, 0 },
+ { 0x5D50, CHIP_FAMILY_R420, 0, 0, 0, 0, 0 },
+ { 0x5D52, CHIP_FAMILY_R420, 0, 0, 0, 0, 0 },
+ { 0x5D57, CHIP_FAMILY_R420, 0, 0, 0, 0, 0 },
+ { 0x5E48, CHIP_FAMILY_RV410, 0, 0, 0, 0, 0 },
+ { 0x5E4A, CHIP_FAMILY_RV410, 0, 0, 0, 0, 0 },
+ { 0x5E4B, CHIP_FAMILY_RV410, 0, 0, 0, 0, 0 },
+ { 0x5E4C, CHIP_FAMILY_RV410, 0, 0, 0, 0, 0 },
+ { 0x5E4D, CHIP_FAMILY_RV410, 0, 0, 0, 0, 0 },
+ { 0x5E4F, CHIP_FAMILY_RV410, 0, 0, 0, 0, 0 },
+ { 0x7834, CHIP_FAMILY_RS300, 0, 1, 0, 0, 0 },
+ { 0x7835, CHIP_FAMILY_RS300, 1, 1, 0, 0, 0 },
+};
diff --git a/src/radeon_chipset.h b/src/radeon_chipset.h
deleted file mode 100644
index 890babd..0000000
--- a/src/radeon_chipset.h
+++ /dev/null
@@ -1,142 +0,0 @@
-static SymTabRec RADEONChipsets[] = {
- { PCI_CHIP_RADEON_QD, "ATI Radeon QD (AGP)" },
- { PCI_CHIP_RADEON_QE, "ATI Radeon QE (AGP)" },
- { PCI_CHIP_RADEON_QF, "ATI Radeon QF (AGP)" },
- { PCI_CHIP_RADEON_QG, "ATI Radeon QG (AGP)" },
- { PCI_CHIP_RV100_QY, "ATI Radeon VE/7000 QY (AGP/PCI)" },
- { PCI_CHIP_RV100_QZ, "ATI Radeon VE/7000 QZ (AGP/PCI)" },
- { PCI_CHIP_RN50_515E, "ATI ES1000 515E (PCI)" },
- { PCI_CHIP_RN50_5969, "ATI ES1000 5969 (PCI)" },
- { PCI_CHIP_RADEON_LW, "ATI Radeon Mobility M7 LW (AGP)" },
- { PCI_CHIP_RADEON_LX, "ATI Mobility FireGL 7800 M7 LX (AGP)" },
- { PCI_CHIP_RADEON_LY, "ATI Radeon Mobility M6 LY (AGP)" },
- { PCI_CHIP_RADEON_LZ, "ATI Radeon Mobility M6 LZ (AGP)" },
- { PCI_CHIP_RS100_4136, "ATI Radeon IGP320 (A3) 4136" },
- { PCI_CHIP_RS100_4336, "ATI Radeon IGP320M (U1) 4336" },
- { PCI_CHIP_RS200_4137, "ATI Radeon IGP330/340/350 (A4) 4137" },
- { PCI_CHIP_RS200_4337, "ATI Radeon IGP330M/340M/350M (U2) 4337" },
- { PCI_CHIP_RS250_4237, "ATI Radeon 7000 IGP (A4+) 4237" },
- { PCI_CHIP_RS250_4437, "ATI Radeon Mobility 7000 IGP 4437" },
- { PCI_CHIP_R200_QH, "ATI FireGL 8700/8800 QH (AGP)" },
- { PCI_CHIP_R200_QL, "ATI Radeon 8500 QL (AGP)" },
- { PCI_CHIP_R200_QM, "ATI Radeon 9100 QM (AGP)" },
- { PCI_CHIP_R200_BB, "ATI Radeon 8500 AIW BB (AGP)" },
- { PCI_CHIP_R200_BC, "ATI Radeon 8500 AIW BC (AGP)" },
- { PCI_CHIP_RV200_QW, "ATI Radeon 7500 QW (AGP/PCI)" },
- { PCI_CHIP_RV200_QX, "ATI Radeon 7500 QX (AGP/PCI)" },
- { PCI_CHIP_RV250_If, "ATI Radeon 9000/PRO If (AGP/PCI)" },
- { PCI_CHIP_RV250_Ig, "ATI Radeon 9000 Ig (AGP/PCI)" },
- { PCI_CHIP_RV250_Ld, "ATI FireGL Mobility 9000 (M9) Ld (AGP)" },
- { PCI_CHIP_RV250_Lf, "ATI Radeon Mobility 9000 (M9) Lf (AGP)" },
- { PCI_CHIP_RV250_Lg, "ATI Radeon Mobility 9000 (M9) Lg (AGP)" },
- { PCI_CHIP_RS300_5834, "ATI Radeon 9100 IGP (A5) 5834" },
- { PCI_CHIP_RS300_5835, "ATI Radeon Mobility 9100 IGP (U3) 5835" },
- { PCI_CHIP_RS350_7834, "ATI Radeon 9100 PRO IGP 7834" },
- { PCI_CHIP_RS350_7835, "ATI Radeon Mobility 9200 IGP 7835" },
- { PCI_CHIP_RV280_5960, "ATI Radeon 9250 5960 (AGP)" },
- { PCI_CHIP_RV280_5961, "ATI Radeon 9200 5961 (AGP)" },
- { PCI_CHIP_RV280_5962, "ATI Radeon 9200 5962 (AGP)" },
- { PCI_CHIP_RV280_5964, "ATI Radeon 9200SE 5964 (AGP)" },
- { PCI_CHIP_RV280_5965, "ATI FireMV 2200 (PCI)" },
- { PCI_CHIP_RV280_5C61, "ATI Radeon Mobility 9200 (M9+) 5C61 (AGP)" },
- { PCI_CHIP_RV280_5C63, "ATI Radeon Mobility 9200 (M9+) 5C63 (AGP)" },
- { PCI_CHIP_R300_AD, "ATI Radeon 9500 AD (AGP)" },
- { PCI_CHIP_R300_AE, "ATI Radeon 9500 AE (AGP)" },
- { PCI_CHIP_R300_AF, "ATI Radeon 9600TX AF (AGP)" },
- { PCI_CHIP_R300_AG, "ATI FireGL Z1 AG (AGP)" },
- { PCI_CHIP_R300_ND, "ATI Radeon 9700 Pro ND (AGP)" },
- { PCI_CHIP_R300_NE, "ATI Radeon 9700/9500Pro NE (AGP)" },
- { PCI_CHIP_R300_NF, "ATI Radeon 9600TX NF (AGP)" },
- { PCI_CHIP_R300_NG, "ATI FireGL X1 NG (AGP)" },
- { PCI_CHIP_RV350_AP, "ATI Radeon 9600 AP (AGP)" },
- { PCI_CHIP_RV350_AQ, "ATI Radeon 9600SE AQ (AGP)" },
- { PCI_CHIP_RV360_AR, "ATI Radeon 9600XT AR (AGP)" },
- { PCI_CHIP_RV350_AS, "ATI Radeon 9600 AS (AGP)" },
- { PCI_CHIP_RV350_AT, "ATI FireGL T2 AT (AGP)" },
- { PCI_CHIP_RV350_AV, "ATI FireGL RV360 AV (AGP)" },
- { PCI_CHIP_RV350_NP, "ATI Radeon Mobility 9600/9700 (M10/M11) NP (AGP)" },
- { PCI_CHIP_RV350_NQ, "ATI Radeon Mobility 9600 (M10) NQ (AGP)" },
- { PCI_CHIP_RV350_NR, "ATI Radeon Mobility 9600 (M11) NR (AGP)" },
- { PCI_CHIP_RV350_NS, "ATI Radeon Mobility 9600 (M10) NS (AGP)" },
- { PCI_CHIP_RV350_NT, "ATI FireGL Mobility T2 (M10) NT (AGP)" },
- { PCI_CHIP_RV350_NV, "ATI FireGL Mobility T2e (M11) NV (AGP)" },
- { PCI_CHIP_RV350_4155, "ATI Radeon 9650" },
- { PCI_CHIP_R350_AH, "ATI Radeon 9800SE AH (AGP)" },
- { PCI_CHIP_R350_AI, "ATI Radeon 9800 AI (AGP)" },
- { PCI_CHIP_R350_AJ, "ATI Radeon 9800 AJ (AGP)" },
- { PCI_CHIP_R350_AK, "ATI FireGL X2 AK (AGP)" },
- { PCI_CHIP_R350_NH, "ATI Radeon 9800PRO NH (AGP)" },
- { PCI_CHIP_R350_NI, "ATI Radeon 9800 NI (AGP)" },
- { PCI_CHIP_R350_NK, "ATI FireGL X2 NK (AGP)" },
- { PCI_CHIP_R360_NJ, "ATI Radeon 9800XT NJ (AGP)" },
- { PCI_CHIP_RV380_3E50, "ATI Radeon X600 (RV380) 3E50 (PCIE)" },
- { PCI_CHIP_RV380_3E54, "ATI FireGL V3200 (RV380) 3E54 (PCIE)" },
- { PCI_CHIP_RV380_3150, "ATI Radeon Mobility X600 (M24) 3150 (PCIE)" },
- { PCI_CHIP_RV380_3152, "ATI Radeon Mobility X300 (M24) 3152 (PCIE)" },
- { PCI_CHIP_RV380_3154, "ATI FireGL M24 GL 3154 (PCIE)" },
- { PCI_CHIP_RV370_5B60, "ATI Radeon X300 (RV370) 5B60 (PCIE)" },
- { PCI_CHIP_RV370_5B62, "ATI Radeon X600 (RV370) 5B62 (PCIE)" },
- { PCI_CHIP_RV370_5B63, "ATI Radeon X550 (RV370) 5B63 (PCIE)" },
- { PCI_CHIP_RV370_5B64, "ATI FireGL V3100 (RV370) 5B64 (PCIE)" },
- { PCI_CHIP_RV370_5B65, "ATI FireMV 2200 PCIE (RV370) 5B65 (PCIE)" },
- { PCI_CHIP_RV370_5460, "ATI Radeon Mobility X300 (M22) 5460 (PCIE)" },
- { PCI_CHIP_RV370_5462, "ATI Radeon Mobility X600 SE (M24C) 5462 (PCIE)" },
- { PCI_CHIP_RV370_5464, "ATI FireGL M22 GL 5464 (PCIE)" },
- { PCI_CHIP_RS400_5A41, "ATI Radeon XPRESS 200 5A41 (PCIE)" },
- { PCI_CHIP_RS400_5A42, "ATI Radeon XPRESS 200M 5A42 (PCIE)" },
- { PCI_CHIP_RC410_5A61, "ATI Radeon XPRESS 200 5A61 (PCIE)" },
- { PCI_CHIP_RC410_5A62, "ATI Radeon XPRESS 200M 5A62 (PCIE)" },
- { PCI_CHIP_RS480_5954, "ATI Radeon XPRESS 200 5954 (PCIE)" },
- { PCI_CHIP_RS480_5955, "ATI Radeon XPRESS 200M 5955 (PCIE)" },
- { PCI_CHIP_RS482_5974, "ATI Radeon XPRESS 200 5974 (PCIE)" },
- { PCI_CHIP_RS485_5975, "ATI Radeon XPRESS 200M 5975 (PCIE)" },
- { PCI_CHIP_RV410_5E48, "ATI FireGL V5000 (RV410) (PCIE)" },
- { PCI_CHIP_RV410_564A, "ATI Mobility FireGL V5000 (M26) (PCIE)" },
- { PCI_CHIP_RV410_564B, "ATI Mobility FireGL V5000 (M26) (PCIE)" },
- { PCI_CHIP_RV410_564F, "ATI Mobility Radeon X700 XL (M26) (PCIE)" },
- { PCI_CHIP_RV410_5652, "ATI Mobility Radeon X700 (M26) (PCIE)" },
- { PCI_CHIP_RV410_5653, "ATI Mobility Radeon X700 (M26) (PCIE)" },
- { PCI_CHIP_RV410_5E4B, "ATI Radeon X700 PRO (RV410) (PCIE)" },
- { PCI_CHIP_RV410_5E4A, "ATI Radeon X700 XT (RV410) (PCIE)" },
- { PCI_CHIP_RV410_5E4D, "ATI Radeon X700 (RV410) (PCIE)" },
- { PCI_CHIP_RV410_5E4C, "ATI Radeon X700 SE (RV410) (PCIE)" },
- { PCI_CHIP_RV410_5E4F, "ATI Radeon X700 SE (RV410) (PCIE)" },
- { PCI_CHIP_R420_JH, "ATI Radeon X800 (R420) JH (AGP)" },
- { PCI_CHIP_R420_JI, "ATI Radeon X800PRO (R420) JI (AGP)" },
- { PCI_CHIP_R420_JJ, "ATI Radeon X800SE (R420) JJ (AGP)" },
- { PCI_CHIP_R420_JK, "ATI Radeon X800 (R420) JK (AGP)" },
- { PCI_CHIP_R420_JL, "ATI Radeon X800 (R420) JL (AGP)" },
- { PCI_CHIP_R420_JM, "ATI FireGL X3 (R420) JM (AGP)" },
- { PCI_CHIP_R420_JN, "ATI Radeon Mobility 9800 (M18) JN (AGP)" },
- { PCI_CHIP_R420_JP, "ATI Radeon X800XT (R420) JP (AGP)" },
- { PCI_CHIP_R420_4A4F, "ATI Radeon X800 SE (R420) (AGP)" },
- { PCI_CHIP_R420_4A54, "ATI Radeon AIW X800 VE (R420) JT (AGP)" },
- { PCI_CHIP_R423_UH, "ATI Radeon X800 (R423) UH (PCIE)" },
- { PCI_CHIP_R423_UI, "ATI Radeon X800PRO (R423) UI (PCIE)" },
- { PCI_CHIP_R423_UJ, "ATI Radeon X800LE (R423) UJ (PCIE)" },
- { PCI_CHIP_R423_UK, "ATI Radeon X800SE (R423) UK (PCIE)" },
- { PCI_CHIP_R423_UQ, "ATI FireGL V5100 (R423) UQ (PCIE)" },
- { PCI_CHIP_R423_UR, "ATI FireGL unknown (R423) UR (PCIE)" },
- { PCI_CHIP_R423_UT, "ATI FireGL unknown (R423) UT (PCIE)" },
- { PCI_CHIP_R423_5D57, "ATI Radeon X800XT (R423) 5D57 (PCIE)" },
- { PCI_CHIP_R423_5550, "ATI FireGL V7100 (R423) (PCIE)" },
- { PCI_CHIP_R430_5D49, "ATI Mobility FireGL V5100 (M28) (PCIE)" },
- { PCI_CHIP_R430_5D4A, "ATI Mobility Radeon X800 (M28) (PCIE)" },
- { PCI_CHIP_R430_5D48, "ATI Mobility Radeon X800 XT (M28) (PCIE)" },
- { PCI_CHIP_R430_554F, "ATI Radeon X800 (R430) (PCIE)" },
- { PCI_CHIP_R430_554D, "ATI Radeon X800 XL (R430) (PCIE)" },
- { PCI_CHIP_R430_554E, "ATI Radeon X800 SE (R430) (PCIE)" },
- { PCI_CHIP_R430_554C, "ATI Radeon X800 XTP (R430) (PCIE)" },
- { PCI_CHIP_R480_5D4C, "ATI Radeon X850 5D4C (PCIE)" },
- { PCI_CHIP_R480_5D50, "ATI unknown Radeon / FireGL (R480) 5D50 (PCIE)" },
- { PCI_CHIP_R480_5D4E, "ATI Radeon X850 SE (R480) (PCIE)" },
- { PCI_CHIP_R480_5D4F, "ATI Radeon X850 PRO (R480) (PCIE)" },
- { PCI_CHIP_R480_5D52, "ATI Radeon X850 XT (R480) (PCIE)" },
- { PCI_CHIP_R480_5D4D, "ATI Radeon X850 XT PE (R480) (PCIE)" },
- { PCI_CHIP_R481_4B4B, "ATI Radeon X850 PRO (R480) (AGP)" },
- { PCI_CHIP_R481_4B4A, "ATI Radeon X850 SE (R480) (AGP)" },
- { PCI_CHIP_R481_4B49, "ATI Radeon X850 XT (R480) (AGP)" },
- { PCI_CHIP_R481_4B4C, "ATI Radeon X850 XT PE (R480) (AGP)" },
-
- { -1, NULL }
-};
diff --git a/src/radeon_chipset_gen.h b/src/radeon_chipset_gen.h
new file mode 100644
index 0000000..0a7a9c1
--- /dev/null
+++ b/src/radeon_chipset_gen.h
@@ -0,0 +1,141 @@
+/* This file is autogenerated please do not edit */
+static SymTabRec RADEONChipsets[] = {
+ { PCI_CHIP_RV380_3150, "ATI Radeon Mobility X600 (M24) 3150 (PCIE)" },
+ { PCI_CHIP_RV380_3152, "ATI Radeon Mobility X300 (M24) 3152 (PCIE)" },
+ { PCI_CHIP_RV380_3154, "ATI FireGL M24 GL 3154 (PCIE)" },
+ { PCI_CHIP_RV380_3E50, "ATI Radeon X600 (RV380) 3E50 (PCIE)" },
+ { PCI_CHIP_RV380_3E54, "ATI FireGL V3200 (RV380) 3E54 (PCIE)" },
+ { PCI_CHIP_RS100_4136, "ATI Radeon IGP320 (A3) 4136" },
+ { PCI_CHIP_RS200_4137, "ATI Radeon IGP330/340/350 (A4) 4137" },
+ { PCI_CHIP_R300_AD, "ATI Radeon 9500 AD (AGP)" },
+ { PCI_CHIP_R300_AE, "ATI Radeon 9500 AE (AGP)" },
+ { PCI_CHIP_R300_AF, "ATI Radeon 9600TX AF (AGP)" },
+ { PCI_CHIP_R300_AG, "ATI FireGL Z1 AG (AGP)" },
+ { PCI_CHIP_R350_AH, "ATI Radeon 9800SE AH (AGP)" },
+ { PCI_CHIP_R350_AI, "ATI Radeon 9800 AI (AGP)" },
+ { PCI_CHIP_R350_AJ, "ATI Radeon 9800 AJ (AGP)" },
+ { PCI_CHIP_R350_AK, "ATI FireGL X2 AK (AGP)" },
+ { PCI_CHIP_RV350_AP, "ATI Radeon 9600 AP (AGP)" },
+ { PCI_CHIP_RV350_AQ, "ATI Radeon 9600SE AQ (AGP)" },
+ { PCI_CHIP_RV360_AR, "ATI Radeon 9600XT AR (AGP)" },
+ { PCI_CHIP_RV350_AS, "ATI Radeon 9600 AS (AGP)" },
+ { PCI_CHIP_RV350_AT, "ATI FireGL T2 AT (AGP)" },
+ { PCI_CHIP_RV350_4155, "ATI Radeon 9650" },
+ { PCI_CHIP_RV350_AV, "ATI FireGL RV360 AV (AGP)" },
+ { PCI_CHIP_RS250_4237, "ATI Radeon 7000 IGP (A4+) 4237" },
+ { PCI_CHIP_R200_BB, "ATI Radeon 8500 AIW BB (AGP)" },
+ { PCI_CHIP_R200_BC, "ATI Radeon 8500 AIW BC (AGP)" },
+ { PCI_CHIP_RS100_4336, "ATI Radeon IGP320M (U1) 4336" },
+ { PCI_CHIP_RS200_4337, "ATI Radeon IGP330M/340M/350M (U2) 4337" },
+ { PCI_CHIP_RS250_4437, "ATI Radeon Mobility 7000 IGP 4437" },
+ { PCI_CHIP_RV250_If, "ATI Radeon 9000/PRO If (AGP/PCI)" },
+ { PCI_CHIP_RV250_Ig, "ATI Radeon 9000 Ig (AGP/PCI)" },
+ { PCI_CHIP_R420_JH, "ATI Radeon X800 (R420) JH (AGP)" },
+ { PCI_CHIP_R420_JI, "ATI Radeon X800PRO (R420) JI (AGP)" },
+ { PCI_CHIP_R420_JJ, "ATI Radeon X800SE (R420) JJ (AGP)" },
+ { PCI_CHIP_R420_JK, "ATI Radeon X800 (R420) JK (AGP)" },
+ { PCI_CHIP_R420_JL, "ATI Radeon X800 (R420) JL (AGP)" },
+ { PCI_CHIP_R420_JM, "ATI FireGL X3 (R420) JM (AGP)" },
+ { PCI_CHIP_R420_JN, "ATI Radeon Mobility 9800 (M18) JN (AGP)" },
+ { PCI_CHIP_R420_4A4F, "ATI Radeon X800 SE (R420) (AGP)" },
+ { PCI_CHIP_R420_JP, "ATI Radeon X800XT (R420) JP (AGP)" },
+ { PCI_CHIP_R481_4B49, "ATI Radeon X850 XT (R480) (AGP)" },
+ { PCI_CHIP_R481_4B4A, "ATI Radeon X850 SE (R480) (AGP)" },
+ { PCI_CHIP_R481_4B4B, "ATI Radeon X850 PRO (R480) (AGP)" },
+ { PCI_CHIP_R481_4B4C, "ATI Radeon X850 XT PE (R480) (AGP)" },
+ { PCI_CHIP_RADEON_LW, "ATI Radeon Mobility M7 LW (AGP)" },
+ { PCI_CHIP_RADEON_LX, "ATI Mobility FireGL 7800 M7 LX (AGP)" },
+ { PCI_CHIP_RADEON_LY, "ATI Radeon Mobility M6 LY (AGP)" },
+ { PCI_CHIP_RADEON_LZ, "ATI Radeon Mobility M6 LZ (AGP)" },
+ { PCI_CHIP_RV250_Ld, "ATI FireGL Mobility 9000 (M9) Ld (AGP)" },
+ { PCI_CHIP_RV250_Lf, "ATI Radeon Mobility 9000 (M9) Lf (AGP)" },
+ { PCI_CHIP_RV250_Lg, "ATI Radeon Mobility 9000 (M9) Lg (AGP)" },
+ { PCI_CHIP_R300_ND, "ATI Radeon 9700 Pro ND (AGP)" },
+ { PCI_CHIP_R300_NE, "ATI Radeon 9700/9500Pro NE (AGP)" },
+ { PCI_CHIP_R300_NF, "ATI Radeon 9600TX NF (AGP)" },
+ { PCI_CHIP_R300_NG, "ATI FireGL X1 NG (AGP)" },
+ { PCI_CHIP_R350_NH, "ATI Radeon 9800PRO NH (AGP)" },
+ { PCI_CHIP_R350_NI, "ATI Radeon 9800 NI (AGP)" },
+ { PCI_CHIP_R360_NJ, "ATI FireGL X2 NK (AGP)" },
+ { PCI_CHIP_R350_NK, "ATI Radeon 9800XT NJ (AGP)" },
+ { PCI_CHIP_RV350_NP, "ATI Radeon Mobility 9600/9700 (M10/M11) NP (AGP)" },
+ { PCI_CHIP_RV350_NQ, "ATI Radeon Mobility 9600 (M10) NQ (AGP)" },
+ { PCI_CHIP_RV350_NR, "ATI Radeon Mobility 9600 (M11) NR (AGP)" },
+ { PCI_CHIP_RV350_NS, "ATI Radeon Mobility 9600 (M10) NS (AGP)" },
+ { PCI_CHIP_RV350_NT, "ATI FireGL Mobility T2 (M10) NT (AGP)" },
+ { PCI_CHIP_RV350_NV, "ATI FireGL Mobility T2e (M11) NV (AGP)" },
+ { PCI_CHIP_RADEON_QD, "ATI Radeon QD (AGP)" },
+ { PCI_CHIP_RADEON_QE, "ATI Radeon QE (AGP)" },
+ { PCI_CHIP_RADEON_QF, "ATI Radeon QF (AGP)" },
+ { PCI_CHIP_RADEON_QG, "ATI Radeon QG (AGP)" },
+ { PCI_CHIP_R200_QH, "ATI FireGL 8700/8800 QH (AGP)" },
+ { PCI_CHIP_R200_QL, "ATI Radeon 8500 QL (AGP)" },
+ { PCI_CHIP_R200_QM, "ATI Radeon 9100 QM (AGP)" },
+ { PCI_CHIP_RV200_QW, "ATI Radeon 7500 QW (AGP/PCI)" },
+ { PCI_CHIP_RV200_QX, "ATI Radeon 7500 QX (AGP/PCI)" },
+ { PCI_CHIP_RV100_QY, "ATI Radeon VE/7000 QY (AGP/PCI)" },
+ { PCI_CHIP_RV100_QZ, "ATI Radeon VE/7000 QZ (AGP/PCI)" },
+ { PCI_CHIP_RN50_515E, "ATI ES1000 515E (PCI)" },
+ { PCI_CHIP_RV370_5460, "ATI Radeon Mobility X300 (M22) 5460 (PCIE)" },
+ { PCI_CHIP_RV370_5462, "ATI Radeon Mobility X600 SE (M24C) 5462 (PCIE)" },
+ { PCI_CHIP_RV370_5464, "ATI FireGL M22 GL 5464 (PCIE)" },
+ { PCI_CHIP_R423_UH, "ATI Radeon X800 (R423) UH (PCIE)" },
+ { PCI_CHIP_R423_UI, "ATI Radeon X800PRO (R423) UI (PCIE)" },
+ { PCI_CHIP_R423_UJ, "ATI Radeon X800LE (R423) UJ (PCIE)" },
+ { PCI_CHIP_R423_UK, "ATI Radeon X800SE (R423) UK (PCIE)" },
+ { PCI_CHIP_R430_554C, "ATI Radeon X800 XTP (R430) (PCIE)" },
+ { PCI_CHIP_R430_554D, "ATI Radeon X800 XL (R430) (PCIE)" },
+ { PCI_CHIP_R430_554E, "ATI Radeon X800 SE (R430) (PCIE)" },
+ { PCI_CHIP_R430_554F, "ATI Radeon X800 (R430) (PCIE)" },
+ { PCI_CHIP_R423_5550, "ATI FireGL V7100 (R423) (PCIE)" },
+ { PCI_CHIP_R423_UQ, "ATI FireGL V5100 (R423) UQ (PCIE)" },
+ { PCI_CHIP_R423_UR, "ATI FireGL unknown (R423) UR (PCIE)" },
+ { PCI_CHIP_R423_UT, "ATI FireGL unknown (R423) UT (PCIE)" },
+ { PCI_CHIP_RV410_564A, "ATI Mobility FireGL V5000 (M26) (PCIE)" },
+ { PCI_CHIP_RV410_564B, "ATI Mobility FireGL V5000 (M26) (PCIE)" },
+ { PCI_CHIP_RV410_564F, "ATI Mobility Radeon X700 XL (M26) (PCIE)" },
+ { PCI_CHIP_RV410_5652, "ATI Mobility Radeon X700 (M26) (PCIE)" },
+ { PCI_CHIP_RV410_5653, "ATI Mobility Radeon X700 (M26) (PCIE)" },
+ { PCI_CHIP_RS300_5834, "ATI Radeon 9100 IGP (A5) 5834" },
+ { PCI_CHIP_RS300_5835, "ATI Radeon Mobility 9100 IGP (U3) 5835" },
+ { PCI_CHIP_RS480_5954, "ATI Radeon XPRESS 200 5954 (PCIE)" },
+ { PCI_CHIP_RS480_5955, "ATI Radeon XPRESS 200M 5955 (PCIE)" },
+ { PCI_CHIP_RV280_5960, "ATI Radeon 9250 5960 (AGP)" },
+ { PCI_CHIP_RV280_5961, "ATI Radeon 9200 5961 (AGP)" },
+ { PCI_CHIP_RV280_5962, "ATI Radeon 9200 5962 (AGP)" },
+ { PCI_CHIP_RV280_5964, "ATI Radeon 9200SE 5964 (AGP)" },
+ { PCI_CHIP_RV280_5965, "ATI FireMV 2200 (PCI)" },
+ { PCI_CHIP_RN50_5969, "ATI ES1000 5969 (PCI)" },
+ { PCI_CHIP_RS482_5974, "ATI Radeon XPRESS 200 5974 (PCIE)" },
+ { PCI_CHIP_RS485_5975, "ATI Radeon XPRESS 200M 5975 (PCIE)" },
+ { PCI_CHIP_RS400_5A41, "ATI Radeon XPRESS 200 5A41 (PCIE)" },
+ { PCI_CHIP_RS400_5A42, "ATI Radeon XPRESS 200M 5A42 (PCIE)" },
+ { PCI_CHIP_RC410_5A61, "ATI Radeon XPRESS 200 5A61 (PCIE)" },
+ { PCI_CHIP_RC410_5A62, "ATI Radeon XPRESS 200M 5A62 (PCIE)" },
+ { PCI_CHIP_RV370_5B60, "ATI Radeon X300 (RV370) 5B60 (PCIE)" },
+ { PCI_CHIP_RV370_5B62, "ATI Radeon X600 (RV370) 5B62 (PCIE)" },
+ { PCI_CHIP_RV370_5B63, "ATI Radeon X550 (RV370) 5B63 (PCIE)" },
+ { PCI_CHIP_RV370_5B64, "ATI FireGL V3100 (RV370) 5B64 (PCIE)" },
+ { PCI_CHIP_RV370_5B65, "ATI FireMV 2200 PCIE (RV370) 5B65 (PCIE)" },
+ { PCI_CHIP_RV280_5C61, "ATI Radeon Mobility 9200 (M9+) 5C61 (AGP)" },
+ { PCI_CHIP_RV280_5C63, "ATI Radeon Mobility 9200 (M9+) 5C63 (AGP)" },
+ { PCI_CHIP_R430_5D48, "ATI Mobility Radeon X800 XT (M28) (PCIE)" },
+ { PCI_CHIP_R430_5D49, "ATI Mobility FireGL V5100 (M28) (PCIE)" },
+ { PCI_CHIP_R430_5D4A, "ATI Mobility Radeon X800 (M28) (PCIE)" },
+ { PCI_CHIP_R480_5D4C, "ATI Radeon X850 5D4C (PCIE)" },
+ { PCI_CHIP_R480_5D4D, "ATI Radeon X850 XT PE (R480) (PCIE)" },
+ { PCI_CHIP_R480_5D4E, "ATI Radeon X850 SE (R480) (PCIE)" },
+ { PCI_CHIP_R480_5D4F, "ATI Radeon X850 PRO (R480) (PCIE)" },
+ { PCI_CHIP_R480_5D50, "ATI unknown Radeon / FireGL (R480) 5D50 (PCIE)" },
+ { PCI_CHIP_R480_5D52, "ATI Radeon X850 XT (R480) (PCIE)" },
+ { PCI_CHIP_R423_5D57, "ATI Radeon X800XT (R423) 5D57 (PCIE)" },
+ { PCI_CHIP_RV410_5E48, "ATI FireGL V5000 (RV410) (PCIE)" },
+ { PCI_CHIP_RV410_5E4A, "ATI Radeon X700 XT (RV410) (PCIE)" },
+ { PCI_CHIP_RV410_5E4B, "ATI Radeon X700 PRO (RV410) (PCIE)" },
+ { PCI_CHIP_RV410_5E4C, "ATI Radeon X700 SE (RV410) (PCIE)" },
+ { PCI_CHIP_RV410_5E4D, "ATI Radeon X700 (RV410) (PCIE)" },
+ { PCI_CHIP_RV410_5E4F, "ATI Radeon X700 SE (RV410) (PCIE)" },
+ { PCI_CHIP_RS350_7834, "ATI Radeon 9100 PRO IGP 7834" },
+ { PCI_CHIP_RS350_7835, "ATI Radeon Mobility 9200 IGP 7835" },
+ { -1, NULL }
+};
diff --git a/src/radeon_commonfuncs.c b/src/radeon_commonfuncs.c
index 6a999af..a1802f8 100644
--- a/src/radeon_commonfuncs.c
+++ b/src/radeon_commonfuncs.c
@@ -174,8 +174,8 @@ void FUNC_NAME(RADEONWaitForIdle)(ScrnInfoPtr pScrn)
}
xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG,
"Idle timed out: %u entries, stat=0x%08x\n",
- INREG(RADEON_RBBM_STATUS) & RADEON_RBBM_FIFOCNT_MASK,
- INREG(RADEON_RBBM_STATUS));
+ (unsigned int)INREG(RADEON_RBBM_STATUS) & RADEON_RBBM_FIFOCNT_MASK,
+ (unsigned int)INREG(RADEON_RBBM_STATUS));
xf86DrvMsg(pScrn->scrnIndex, X_ERROR,
"Idle timed out, resetting engine...\n");
RADEONEngineReset(pScrn);
diff --git a/src/radeon_crtc.c b/src/radeon_crtc.c
index de24273..07857dd 100644
--- a/src/radeon_crtc.c
+++ b/src/radeon_crtc.c
@@ -145,15 +145,13 @@ RADEONInitCommonRegisters(RADEONSavePtr save, RADEONInfoPtr info)
static void
RADEONInitSurfaceCntl(xf86CrtcPtr crtc, RADEONSavePtr save)
{
- ScrnInfoPtr pScrn = crtc->scrn;
-
save->surface_cntl = 0;
#if X_BYTE_ORDER == X_BIG_ENDIAN
/* We must set both apertures as they can be both used to map the entire
* video memory. -BenH.
*/
- switch (pScrn->bitsPerPixel) {
+ switch (crtc->scrn->bitsPerPixel) {
case 16:
save->surface_cntl |= RADEON_NONSURF_AP0_SWP_16BPP;
save->surface_cntl |= RADEON_NONSURF_AP1_SWP_16BPP;
@@ -606,19 +604,108 @@ RADEONInitCrtc2Registers(xf86CrtcPtr crtc, RADEONSavePtr save,
}
-/* Compute n/d with rounding */
static int RADEONDiv(int n, int d)
{
return (n + (d / 2)) / d;
}
+static void
+RADEONComputePLL(RADEONPLLPtr pll,
+ unsigned long freq,
+ CARD32 *chosen_dot_clock_freq,
+ CARD32 *chosen_feedback_div,
+ CARD32 *chosen_reference_div,
+ CARD32 *chosen_post_div,
+ int flags)
+{
+ int post_divs[] = {1, 2, 4, 8, 3, 6, 12, 0};
+
+ int i;
+
+ CARD32 min_ref_div = pll->min_ref_div;
+ CARD32 max_ref_div = pll->max_ref_div;
+ CARD32 best_vco = pll->best_vco;
+ CARD32 best_post_div = 1;
+ CARD32 best_ref_div = 1;
+ CARD32 best_feedback_div = 1;
+ CARD32 best_freq = 1;
+ CARD32 best_error = 0xffffffff;
+ CARD32 best_vco_diff = 1;
+
+ freq = freq / 10;
+
+ ErrorF("freq: %lu\n", freq);
+
+ if (flags & RADEON_PLL_USE_REF_DIV)
+ min_ref_div = max_ref_div = pll->reference_div;
+
+ for (i = 0; post_divs[i]; i++) {
+ int post_div = post_divs[i];
+ CARD32 ref_div;
+ CARD32 vco = freq * post_div;
+
+ if ((flags & RADEON_PLL_NO_ODD_POST_DIV) && (post_div & 1))
+ continue;
+
+ if (vco < pll->min_pll_freq || vco > pll->max_pll_freq)
+ continue;
+
+ for (ref_div = min_ref_div; ref_div <= max_ref_div; ++ref_div) {
+ CARD32 feedback_div, current_freq, error, vco_diff;
+ CARD32 pll_in = pll->reference_freq / ref_div;
+
+ if (pll_in < pll->pll_in_min || pll_in > pll->pll_in_max)
+ continue;
+
+ feedback_div = RADEONDiv(freq * ref_div * post_div,
+ pll->reference_freq);
+
+ if (feedback_div < pll->min_feedback_div || feedback_div > pll->max_feedback_div)
+ continue;
+
+ current_freq = RADEONDiv(pll->reference_freq * feedback_div,
+ ref_div * post_div);
+
+ error = abs(current_freq - freq);
+ vco_diff = abs(vco - best_vco);
+
+ if ((best_vco == 0 && error < best_error) ||
+ (best_vco != 0 &&
+ (error < best_error - 1000 ||
+ (abs(error - best_error) < 100 && vco_diff < best_vco_diff )))) {
+ best_post_div = post_div;
+ best_ref_div = ref_div;
+ best_feedback_div = feedback_div;
+ best_freq = current_freq;
+ best_error = error;
+ best_vco_diff = vco_diff;
+ }
+ }
+ }
+
+ ErrorF("best_freq: %u\n", (unsigned)best_freq);
+ ErrorF("best_feedback_div: %u\n", (unsigned)best_feedback_div);
+ ErrorF("best_ref_div: %u\n", (unsigned)best_ref_div);
+ ErrorF("best_post_div: %u\n", (unsigned)best_post_div);
+
+ *chosen_dot_clock_freq = best_freq;
+ *chosen_feedback_div = best_feedback_div;
+ *chosen_reference_div = best_ref_div;
+ *chosen_post_div = best_post_div;
+
+}
+
/* Define PLL registers for requested video mode */
static void
-RADEONInitPLLRegisters(ScrnInfoPtr pScrn, RADEONInfoPtr info,
- RADEONSavePtr save, RADEONPLLPtr pll,
- double dot_clock)
+RADEONInitPLLRegisters(ScrnInfoPtr pScrn, RADEONSavePtr save,
+ RADEONPLLPtr pll, DisplayModePtr mode,
+ int flags)
{
- unsigned long freq = dot_clock * 100;
+ RADEONInfoPtr info = RADEONPTR(pScrn);
+ CARD32 feedback_div = 0;
+ CARD32 reference_div = 0;
+ CARD32 post_divider = 0;
+ CARD32 freq = 0;
struct {
int divider;
@@ -640,21 +727,19 @@ RADEONInitPLLRegisters(ScrnInfoPtr pScrn, RADEONInfoPtr info,
{ 0, 0 }
};
- if (info->UseBiosDividers) {
+
+ if ((flags & RADEON_PLL_USE_BIOS_DIVS) && info->UseBiosDividers) {
save->ppll_ref_div = info->RefDivider;
save->ppll_div_3 = info->FeedbackDivider | (info->PostDivider << 16);
save->htotal_cntl = 0;
return;
}
- if (freq > pll->max_pll_freq) freq = pll->max_pll_freq;
- if (freq * 12 < pll->min_pll_freq) freq = pll->min_pll_freq / 12;
+ RADEONComputePLL(pll, mode->Clock, &freq, &feedback_div, &reference_div, &post_divider, flags);
for (post_div = &post_divs[0]; post_div->divider; ++post_div) {
- save->pll_output_freq = post_div->divider * freq;
-
- if (save->pll_output_freq >= pll->min_pll_freq
- && save->pll_output_freq <= pll->max_pll_freq) break;
+ if (post_div->divider == post_divider)
+ break;
}
if (!post_div->divider) {
@@ -663,19 +748,19 @@ RADEONInitPLLRegisters(ScrnInfoPtr pScrn, RADEONInfoPtr info,
}
save->dot_clock_freq = freq;
- save->feedback_div = RADEONDiv(pll->reference_div
- * save->pll_output_freq,
- pll->reference_freq);
- save->post_div = post_div->divider;
+ save->feedback_div = feedback_div;
+ save->reference_div = reference_div;
+ save->post_div = post_divider;
xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG,
- "dc=%u, of=%u, fd=%d, pd=%d\n",
+ "dc=%u, of=%u, fd=%d, rd=%d, pd=%d\n",
(unsigned)save->dot_clock_freq,
(unsigned)save->pll_output_freq,
save->feedback_div,
+ save->reference_div,
save->post_div);
- save->ppll_ref_div = pll->reference_div;
+ save->ppll_ref_div = save->reference_div;
#if defined(__powerpc__)
/* apparently programming this otherwise causes a hang??? */
@@ -685,21 +770,24 @@ RADEONInitPLLRegisters(ScrnInfoPtr pScrn, RADEONInfoPtr info,
#endif
save->ppll_div_3 = (save->feedback_div | (post_div->bitvalue << 16));
- save->htotal_cntl = 0;
+ save->htotal_cntl = mode->HTotal & 0x7;
- save->vclk_ecp_cntl = (info->SavedReg.vclk_ecp_cntl &
- ~RADEON_VCLK_SRC_SEL_MASK) | RADEON_VCLK_SRC_SEL_PPLLCLK;
+ save->vclk_ecp_cntl = (info->SavedReg.vclk_ecp_cntl &
+ ~RADEON_VCLK_SRC_SEL_MASK) | RADEON_VCLK_SRC_SEL_PPLLCLK;
}
/* Define PLL2 registers for requested video mode */
static void
RADEONInitPLL2Registers(ScrnInfoPtr pScrn, RADEONSavePtr save,
- RADEONPLLPtr pll, double dot_clock,
- int no_odd_postdiv)
+ RADEONPLLPtr pll, DisplayModePtr mode,
+ int flags)
{
- RADEONInfoPtr info = RADEONPTR(pScrn);
- unsigned long freq = dot_clock * 100;
+ RADEONInfoPtr info = RADEONPTR(pScrn);
+ CARD32 feedback_div = 0;
+ CARD32 reference_div = 0;
+ CARD32 post_divider = 0;
+ CARD32 freq = 0;
struct {
int divider;
@@ -720,18 +808,18 @@ RADEONInitPLL2Registers(ScrnInfoPtr pScrn, RADEONSavePtr save,
{ 0, 0 }
};
- if (freq > pll->max_pll_freq) freq = pll->max_pll_freq;
- if (freq * 12 < pll->min_pll_freq) freq = pll->min_pll_freq / 12;
+ if ((flags & RADEON_PLL_USE_BIOS_DIVS) && info->UseBiosDividers) {
+ save->p2pll_ref_div = info->RefDivider;
+ save->p2pll_div_0 = info->FeedbackDivider | (info->PostDivider << 16);
+ save->htotal_cntl2 = 0;
+ return;
+ }
+
+ RADEONComputePLL(pll, mode->Clock, &freq, &feedback_div, &reference_div, &post_divider, flags);
for (post_div = &post_divs[0]; post_div->divider; ++post_div) {
- /* Odd post divider value don't work properly on the second digital
- * output
- */
- if (no_odd_postdiv && (post_div->divider & 1))
- continue;
- save->pll_output_freq_2 = post_div->divider * freq;
- if (save->pll_output_freq_2 >= pll->min_pll_freq
- && save->pll_output_freq_2 <= pll->max_pll_freq) break;
+ if (post_div->divider == post_divider)
+ break;
}
if (!post_div->divider) {
@@ -740,26 +828,28 @@ RADEONInitPLL2Registers(ScrnInfoPtr pScrn, RADEONSavePtr save,
}
save->dot_clock_freq_2 = freq;
- save->feedback_div_2 = RADEONDiv(pll->reference_div
- * save->pll_output_freq_2,
- pll->reference_freq);
- save->post_div_2 = post_div->divider;
+ save->feedback_div_2 = feedback_div;
+ save->reference_div_2 = reference_div;
+ save->post_div_2 = post_divider;
xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG,
- "dc=%u, of=%u, fd=%d, pd=%d\n",
+ "dc=%u, of=%u, fd=%d, rd=%d, pd=%d\n",
(unsigned)save->dot_clock_freq_2,
(unsigned)save->pll_output_freq_2,
save->feedback_div_2,
+ save->reference_div_2,
save->post_div_2);
- save->p2pll_ref_div = pll->reference_div;
+ save->p2pll_ref_div = save->reference_div_2;
+
save->p2pll_div_0 = (save->feedback_div_2 |
(post_div->bitvalue << 16));
- save->htotal_cntl2 = 0;
- save->pixclks_cntl = ((info->SavedReg.pixclks_cntl &
- ~(RADEON_PIX2CLK_SRC_SEL_MASK)) |
- RADEON_PIX2CLK_SRC_SEL_P2PLLCLK);
+ save->htotal_cntl2 = mode->HTotal & 0x7;
+
+ save->pixclks_cntl = ((info->SavedReg.pixclks_cntl &
+ ~(RADEON_PIX2CLK_SRC_SEL_MASK)) |
+ RADEON_PIX2CLK_SRC_SEL_P2PLLCLK);
}
@@ -769,8 +859,8 @@ RADEONInitBIOSRegisters(ScrnInfoPtr pScrn, RADEONSavePtr save)
RADEONInfoPtr info = RADEONPTR(pScrn);
/* tell the bios not to muck with the hardware on events */
- save->bios_4_scratch = 0;
- save->bios_5_scratch = 0xff00;
+ save->bios_4_scratch = 0x4; /* 0x4 needed for backlight */
+ save->bios_5_scratch = (info->SavedReg.bios_5_scratch & 0xff) | 0xff00; /* bits 0-3 keep backlight level */
save->bios_6_scratch = info->SavedReg.bios_6_scratch | 0x40000000;
}
@@ -792,8 +882,8 @@ radeon_crtc_mode_set(xf86CrtcPtr crtc, DisplayModePtr mode,
RADEONInfoPtr info = RADEONPTR(pScrn);
Bool tilingOld = info->tilingEnabled;
int i = 0;
- double dot_clock = 0;
- Bool no_odd_post_div = FALSE;
+ double dot_clock = 0;
+ int pll_flags = 0;
Bool update_tv_routing = FALSE;
@@ -818,7 +908,9 @@ radeon_crtc_mode_set(xf86CrtcPtr crtc, DisplayModePtr mode,
if (output->crtc == crtc) {
if (radeon_output->MonType != MT_CRT)
- no_odd_post_div = TRUE;
+ pll_flags |= RADEON_PLL_NO_ODD_POST_DIV;
+ if (radeon_output->MonType == MT_LCD)
+ pll_flags |= (RADEON_PLL_USE_BIOS_DIVS | RADEON_PLL_USE_REF_DIV);
}
}
@@ -837,25 +929,25 @@ radeon_crtc_mode_set(xf86CrtcPtr crtc, DisplayModePtr mode,
ErrorF("init crtc1\n");
RADEONInitCrtcRegisters(crtc, &info->ModeReg, adjusted_mode);
RADEONInitCrtcBase(crtc, &info->ModeReg, x, y);
- dot_clock = adjusted_mode->Clock / 1000.0;
- if (dot_clock) {
+ dot_clock = adjusted_mode->Clock / 1000.0;
+ if (dot_clock) {
ErrorF("init pll1\n");
- RADEONInitPLLRegisters(pScrn, info, &info->ModeReg, &info->pll, dot_clock);
- } else {
- info->ModeReg.ppll_ref_div = info->SavedReg.ppll_ref_div;
- info->ModeReg.ppll_div_3 = info->SavedReg.ppll_div_3;
- info->ModeReg.htotal_cntl = info->SavedReg.htotal_cntl;
- }
+ RADEONInitPLLRegisters(pScrn, &info->ModeReg, &info->pll, adjusted_mode, pll_flags);
+ } else {
+ info->ModeReg.ppll_ref_div = info->SavedReg.ppll_ref_div;
+ info->ModeReg.ppll_div_3 = info->SavedReg.ppll_div_3;
+ info->ModeReg.htotal_cntl = info->SavedReg.htotal_cntl;
+ }
break;
case 1:
ErrorF("init crtc2\n");
- RADEONInitCrtc2Registers(crtc, &info->ModeReg, adjusted_mode);
+ RADEONInitCrtc2Registers(crtc, &info->ModeReg, adjusted_mode);
RADEONInitCrtc2Base(crtc, &info->ModeReg, x, y);
- dot_clock = adjusted_mode->Clock / 1000.0;
- if (dot_clock) {
+ dot_clock = adjusted_mode->Clock / 1000.0;
+ if (dot_clock) {
ErrorF("init pll2\n");
- RADEONInitPLL2Registers(pScrn, &info->ModeReg, &info->pll, dot_clock, no_odd_post_div);
- }
+ RADEONInitPLL2Registers(pScrn, &info->ModeReg, &info->pll, adjusted_mode, pll_flags);
+ }
break;
}
diff --git a/src/radeon_cursor.c b/src/radeon_cursor.c
index b8cfffd..ba1159c 100644
--- a/src/radeon_cursor.c
+++ b/src/radeon_cursor.c
@@ -166,9 +166,9 @@ radeon_crtc_set_cursor_position (xf86CrtcPtr crtc, int x, int y)
| ((xorigin ? 0 : x) << 16)
| (yorigin ? 0 : y)));
RADEONCTRACE(("cursor_offset: 0x%x, yorigin: %d, stride: %d, temp %08X\n",
- info->cursor_offset + pScrn->fbOffset, yorigin, stride, temp));
+ radeon_crtc->cursor_offset + pScrn->fbOffset, yorigin, stride, temp));
OUTREG(RADEON_CUR_OFFSET,
- info->cursor_offset + pScrn->fbOffset + yorigin * stride);
+ radeon_crtc->cursor_offset + pScrn->fbOffset + yorigin * stride);
} else if (crtc_id == 1) {
OUTREG(RADEON_CUR2_HORZ_VERT_OFF, (RADEON_CUR2_LOCK
| (xorigin << 16)
@@ -177,9 +177,9 @@ radeon_crtc_set_cursor_position (xf86CrtcPtr crtc, int x, int y)
| ((xorigin ? 0 : x) << 16)
| (yorigin ? 0 : y)));
RADEONCTRACE(("cursor_offset2: 0x%x, yorigin: %d, stride: %d, temp %08X\n",
- info->cursor_offset + pScrn->fbOffset, yorigin, stride, temp));
+ radeon_crtc->cursor_offset + pScrn->fbOffset, yorigin, stride, temp));
OUTREG(RADEON_CUR2_OFFSET,
- info->cursor_offset + pScrn->fbOffset + yorigin * stride);
+ radeon_crtc->cursor_offset + pScrn->fbOffset + yorigin * stride);
}
}
@@ -188,8 +188,9 @@ void
radeon_crtc_set_cursor_colors (xf86CrtcPtr crtc, int bg, int fg)
{
ScrnInfoPtr pScrn = crtc->scrn;
+ RADEONCrtcPrivatePtr radeon_crtc = crtc->driver_private;
RADEONInfoPtr info = RADEONPTR(pScrn);
- CARD32 *pixels = (CARD32 *)(pointer)(info->FB + info->cursor_offset + pScrn->fbOffset);
+ CARD32 *pixels = (CARD32 *)(pointer)(info->FB + radeon_crtc->cursor_offset + pScrn->fbOffset);
int pixel, i;
CURSOR_SWAPPING_DECL_MMIO
@@ -229,9 +230,10 @@ void
radeon_crtc_load_cursor_argb (xf86CrtcPtr crtc, CARD32 *image)
{
ScrnInfoPtr pScrn = crtc->scrn;
+ RADEONCrtcPrivatePtr radeon_crtc = crtc->driver_private;
RADEONInfoPtr info = RADEONPTR(pScrn);
- unsigned char *RADEONMMIO = info->MMIO;
- CARD32 *d = (CARD32 *)(pointer)(info->FB + info->cursor_offset + pScrn->fbOffset);
+ CURSOR_SWAPPING_DECL_MMIO
+ CARD32 *d = (CARD32 *)(pointer)(info->FB + radeon_crtc->cursor_offset + pScrn->fbOffset);
RADEONCTRACE(("RADEONLoadCursorARGB\n"));
@@ -252,16 +254,18 @@ Bool RADEONCursorInit(ScreenPtr pScreen)
{
ScrnInfoPtr pScrn = xf86Screens[pScreen->myNum];
RADEONInfoPtr info = RADEONPTR(pScrn);
+ xf86CrtcConfigPtr xf86_config = XF86_CRTC_CONFIG_PTR(pScrn);
int width;
int width_bytes;
int height;
int size_bytes;
-
+ CARD32 cursor_offset = 0;
+ int c;
size_bytes = CURSOR_WIDTH * 4 * CURSOR_HEIGHT;
width = pScrn->displayWidth;
width_bytes = width * (pScrn->bitsPerPixel / 8);
- height = (size_bytes + width_bytes - 1) / width_bytes;
+ height = ((size_bytes * xf86_config->num_crtc) + width_bytes - 1) / width_bytes;
#ifdef USE_XAA
if (!info->useEXA) {
@@ -271,19 +275,30 @@ Bool RADEONCursorInit(ScreenPtr pScreen)
256, NULL, NULL, NULL);
if (!fbarea) {
- info->cursor_offset = 0;
+ cursor_offset = 0;
xf86DrvMsg(pScrn->scrnIndex, X_WARNING,
"Hardware cursor disabled"
" due to insufficient offscreen memory\n");
+ return FALSE;
} else {
- info->cursor_offset = RADEON_ALIGN((fbarea->box.x1 +
- fbarea->box.y1 * width) *
- info->CurrentLayout.pixel_bytes,
- 256);
- info->cursor_end = info->cursor_offset + size_bytes;
+ cursor_offset = RADEON_ALIGN((fbarea->box.x1 +
+ fbarea->box.y1 * width) *
+ info->CurrentLayout.pixel_bytes,
+ 256);
+
+ for (c = 0; c < xf86_config->num_crtc; c++) {
+ xf86CrtcPtr crtc = xf86_config->crtc[c];
+ RADEONCrtcPrivatePtr radeon_crtc = crtc->driver_private;
+
+ radeon_crtc->cursor_offset = cursor_offset + (c * size_bytes);
+
+ xf86DrvMsg(pScrn->scrnIndex, X_INFO,
+ "Using hardware cursor %d (scanline %u)\n", c,
+ (unsigned)(radeon_crtc->cursor_offset / pScrn->displayWidth
+ / info->CurrentLayout.pixel_bytes));
+ }
+
}
- RADEONCTRACE(("RADEONCursorInit (0x%08x-0x%08x)\n",
- info->cursor_offset, info->cursor_end));
}
#endif
diff --git a/src/radeon_display.c b/src/radeon_display.c
index 5c4fbfa..ea31a82 100644
--- a/src/radeon_display.c
+++ b/src/radeon_display.c
@@ -163,7 +163,7 @@ void RADEONGetTVDacAdjInfo(xf86OutputPtr output)
ScrnInfoPtr pScrn = output->scrn;
RADEONInfoPtr info = RADEONPTR(pScrn);
RADEONOutputPrivatePtr radeon_output = output->driver_private;
-
+
/* Todo: get this setting from BIOS */
radeon_output->tv_dac_adj = default_tvdac_adj[info->ChipFamily];
if (info->IsMobility) { /* some mobility chips may different */
@@ -202,7 +202,7 @@ static void RADEONDacPowerSet(ScrnInfoPtr pScrn, Bool IsOn, Bool IsPrimaryDAC)
} else {
CARD32 tv_dac_cntl;
CARD32 fp2_gen_cntl;
-
+
switch(info->ChipFamily)
{
case CHIP_FAMILY_R420:
@@ -259,19 +259,19 @@ void RADEONDisableDisplays(ScrnInfoPtr pScrn) {
/* primary DAC */
tmp = INREG(RADEON_CRTC_EXT_CNTL);
- tmp &= ~RADEON_CRTC_CRT_ON;
+ tmp &= ~RADEON_CRTC_CRT_ON;
OUTREG(RADEON_CRTC_EXT_CNTL, tmp);
RADEONDacPowerSet(pScrn, FALSE, TRUE);
/* Secondary DAC */
if (info->ChipFamily == CHIP_FAMILY_R200) {
- tmp = INREG(RADEON_FP2_GEN_CNTL);
- tmp &= ~(RADEON_FP2_ON | RADEON_FP2_DVO_EN);
- OUTREG(RADEON_FP2_GEN_CNTL, tmp);
+ tmp = INREG(RADEON_FP2_GEN_CNTL);
+ tmp &= ~(RADEON_FP2_ON | RADEON_FP2_DVO_EN);
+ OUTREG(RADEON_FP2_GEN_CNTL, tmp);
} else {
- tmp = INREG(RADEON_CRTC2_GEN_CNTL);
- tmp &= ~RADEON_CRTC2_CRT2_ON;
- OUTREG(RADEON_CRTC2_GEN_CNTL, tmp);
+ tmp = INREG(RADEON_CRTC2_GEN_CNTL);
+ tmp &= ~RADEON_CRTC2_CRT2_ON;
+ OUTREG(RADEON_CRTC2_GEN_CNTL, tmp);
}
RADEONDacPowerSet(pScrn, FALSE, FALSE);
@@ -304,7 +304,7 @@ void RADEONDisableDisplays(ScrnInfoPtr pScrn) {
}
tmp = INREG(RADEON_LVDS_GEN_CNTL);
tmp |= RADEON_LVDS_DISPLAY_DIS;
- tmp &= ~(RADEON_LVDS_ON | RADEON_LVDS_BLON);
+ tmp &= ~(RADEON_LVDS_ON | RADEON_LVDS_BLON | RADEON_LVDS_EN);
OUTREG(RADEON_LVDS_GEN_CNTL, tmp);
if (info->IsMobility || info->IsIGP) {
OUTPLL(pScrn, RADEON_PIXCLKS_CNTL, tmpPixclksCntl);
@@ -322,130 +322,161 @@ void RADEONEnableDisplay(xf86OutputPtr output, BOOL bEnable)
unsigned char * RADEONMMIO = info->MMIO;
unsigned long tmp;
RADEONOutputPrivatePtr radeon_output;
- int tv_dac_change = 0;
+ int tv_dac_change = 0, o;
radeon_output = output->driver_private;
+ xf86CrtcConfigPtr xf86_config = XF86_CRTC_CONFIG_PTR(pScrn);
+
+ for (o = 0; o < xf86_config->num_output; o++) {
+ if (output == xf86_config->output[o]) {
+ break;
+ }
+ }
if (bEnable) {
ErrorF("enable montype: %d\n", radeon_output->MonType);
- if (radeon_output->MonType == MT_CRT) {
- if (radeon_output->DACType == DAC_PRIMARY) {
- tmp = INREG(RADEON_CRTC_EXT_CNTL);
- tmp |= RADEON_CRTC_CRT_ON;
- OUTREG(RADEON_CRTC_EXT_CNTL, tmp);
- save->crtc_ext_cntl |= RADEON_CRTC_CRT_ON;
- RADEONDacPowerSet(pScrn, bEnable, (radeon_output->DACType == DAC_PRIMARY));
- } else if (radeon_output->DACType == DAC_TVDAC) {
- if (info->ChipFamily == CHIP_FAMILY_R200) {
- tmp = INREG(RADEON_FP2_GEN_CNTL);
- tmp |= (RADEON_FP2_ON | RADEON_FP2_DVO_EN);
- OUTREG(RADEON_FP2_GEN_CNTL, tmp);
- save->fp2_gen_cntl |= (RADEON_FP2_ON | RADEON_FP2_DVO_EN);
- } else {
- tmp = INREG(RADEON_CRTC2_GEN_CNTL);
- tmp |= RADEON_CRTC2_CRT2_ON;
- OUTREG(RADEON_CRTC2_GEN_CNTL, tmp);
- save->crtc2_gen_cntl |= RADEON_CRTC2_CRT2_ON;
- }
- tv_dac_change = 1;
- }
- } else if (radeon_output->MonType == MT_DFP) {
- if (radeon_output->TMDSType == TMDS_INT) {
- tmp = INREG(RADEON_FP_GEN_CNTL);
- tmp |= (RADEON_FP_FPON | RADEON_FP_TMDS_EN);
- OUTREG(RADEON_FP_GEN_CNTL, tmp);
- save->fp_gen_cntl |= (RADEON_FP_FPON | RADEON_FP_TMDS_EN);
- } else if (radeon_output->TMDSType == TMDS_EXT) {
- tmp = INREG(RADEON_FP2_GEN_CNTL);
+ if (radeon_output->MonType == MT_CRT) {
+ if (radeon_output->DACType == DAC_PRIMARY) {
+ info->output_crt1 |= (1 << o);
+ tmp = INREG(RADEON_CRTC_EXT_CNTL);
+ tmp |= RADEON_CRTC_CRT_ON;
+ OUTREG(RADEON_CRTC_EXT_CNTL, tmp);
+ save->crtc_ext_cntl |= RADEON_CRTC_CRT_ON;
+ RADEONDacPowerSet(pScrn, bEnable, (radeon_output->DACType == DAC_PRIMARY));
+ } else if (radeon_output->DACType == DAC_TVDAC) {
+ info->output_crt2 |= (1 << o);
+ if (info->ChipFamily == CHIP_FAMILY_R200) {
+ tmp = INREG(RADEON_FP2_GEN_CNTL);
+ tmp |= (RADEON_FP2_ON | RADEON_FP2_DVO_EN);
+ OUTREG(RADEON_FP2_GEN_CNTL, tmp);
+ save->fp2_gen_cntl |= (RADEON_FP2_ON | RADEON_FP2_DVO_EN);
+ } else {
+ tmp = INREG(RADEON_CRTC2_GEN_CNTL);
+ tmp |= RADEON_CRTC2_CRT2_ON;
+ OUTREG(RADEON_CRTC2_GEN_CNTL, tmp);
+ save->crtc2_gen_cntl |= RADEON_CRTC2_CRT2_ON;
+ }
+ tv_dac_change = 1;
+ }
+ } else if (radeon_output->MonType == MT_DFP) {
+ if (radeon_output->TMDSType == TMDS_INT) {
+ info->output_dfp1 |= (1 << o);
+ tmp = INREG(RADEON_FP_GEN_CNTL);
+ tmp |= (RADEON_FP_FPON | RADEON_FP_TMDS_EN);
+ OUTREG(RADEON_FP_GEN_CNTL, tmp);
+ save->fp_gen_cntl |= (RADEON_FP_FPON | RADEON_FP_TMDS_EN);
+ } else if (radeon_output->TMDSType == TMDS_EXT) {
+ info->output_dfp2 |= (1 << o);
+ tmp = INREG(RADEON_FP2_GEN_CNTL);
tmp &= ~RADEON_FP2_BLANK_EN;
- tmp |= (RADEON_FP2_ON | RADEON_FP2_DVO_EN);
- OUTREG(RADEON_FP2_GEN_CNTL, tmp);
- save->fp2_gen_cntl |= (RADEON_FP2_ON | RADEON_FP2_DVO_EN);
+ tmp |= (RADEON_FP2_ON | RADEON_FP2_DVO_EN);
+ OUTREG(RADEON_FP2_GEN_CNTL, tmp);
+ save->fp2_gen_cntl |= (RADEON_FP2_ON | RADEON_FP2_DVO_EN);
save->fp2_gen_cntl &= ~RADEON_FP2_BLANK_EN;
- }
- } else if (radeon_output->MonType == MT_LCD) {
- tmp = INREG(RADEON_LVDS_GEN_CNTL);
- tmp |= (RADEON_LVDS_ON | RADEON_LVDS_BLON);
- tmp &= ~(RADEON_LVDS_DISPLAY_DIS);
+ }
+ } else if (radeon_output->MonType == MT_LCD) {
+ info->output_lcd1 |= (1 << o);
+ tmp = INREG(RADEON_LVDS_GEN_CNTL);
+ tmp |= (RADEON_LVDS_ON | RADEON_LVDS_BLON | RADEON_LVDS_EN);
+ tmp &= ~(RADEON_LVDS_DISPLAY_DIS);
usleep (radeon_output->PanelPwrDly * 1000);
- OUTREG(RADEON_LVDS_GEN_CNTL, tmp);
- save->lvds_gen_cntl |= (RADEON_LVDS_ON | RADEON_LVDS_BLON);
- save->lvds_gen_cntl &= ~(RADEON_LVDS_DISPLAY_DIS);
- } else if (radeon_output->MonType == MT_STV ||
+ OUTREG(RADEON_LVDS_GEN_CNTL, tmp);
+ save->lvds_gen_cntl |= (RADEON_LVDS_ON | RADEON_LVDS_BLON | RADEON_LVDS_EN);
+ save->lvds_gen_cntl &= ~(RADEON_LVDS_DISPLAY_DIS);
+ } else if (radeon_output->MonType == MT_STV ||
radeon_output->MonType == MT_CTV) {
+ info->output_tv1 |= (1 << o);
tmp = INREG(RADEON_TV_MASTER_CNTL);
tmp |= RADEON_TV_ON;
OUTREG(RADEON_TV_MASTER_CNTL, tmp);
- tv_dac_change = 2;
+ tv_dac_change = 2;
radeon_output->tv_on = TRUE;
}
} else {
ErrorF("disable montype: %d\n", radeon_output->MonType);
- if (radeon_output->MonType == MT_CRT) {
- if (radeon_output->DACType == DAC_PRIMARY) {
- tmp = INREG(RADEON_CRTC_EXT_CNTL);
- tmp &= ~RADEON_CRTC_CRT_ON;
- OUTREG(RADEON_CRTC_EXT_CNTL, tmp);
- save->crtc_ext_cntl &= ~RADEON_CRTC_CRT_ON;
- RADEONDacPowerSet(pScrn, bEnable, (radeon_output->DACType == DAC_PRIMARY));
- } else if (radeon_output->DACType == DAC_TVDAC) {
- if (info->ChipFamily == CHIP_FAMILY_R200) {
- tmp = INREG(RADEON_FP2_GEN_CNTL);
- tmp &= ~(RADEON_FP2_ON | RADEON_FP2_DVO_EN);
- OUTREG(RADEON_FP2_GEN_CNTL, tmp);
- save->fp2_gen_cntl &= ~(RADEON_FP2_ON | RADEON_FP2_DVO_EN);
- } else {
- tmp = INREG(RADEON_CRTC2_GEN_CNTL);
- tmp &= ~RADEON_CRTC2_CRT2_ON;
- OUTREG(RADEON_CRTC2_GEN_CNTL, tmp);
- save->crtc2_gen_cntl &= ~RADEON_CRTC2_CRT2_ON;
- }
- tv_dac_change = 1;
- }
- } else if (radeon_output->MonType == MT_DFP) {
- if (radeon_output->TMDSType == TMDS_INT) {
- tmp = INREG(RADEON_FP_GEN_CNTL);
- tmp &= ~(RADEON_FP_FPON | RADEON_FP_TMDS_EN);
- OUTREG(RADEON_FP_GEN_CNTL, tmp);
- save->fp_gen_cntl &= ~(RADEON_FP_FPON | RADEON_FP_TMDS_EN);
- } else if (radeon_output->TMDSType == TMDS_EXT) {
- tmp = INREG(RADEON_FP2_GEN_CNTL);
- tmp |= RADEON_FP2_BLANK_EN;
- tmp &= ~(RADEON_FP2_ON | RADEON_FP2_DVO_EN);
- OUTREG(RADEON_FP2_GEN_CNTL, tmp);
- save->fp2_gen_cntl &= ~(RADEON_FP2_ON | RADEON_FP2_DVO_EN);
- save->fp2_gen_cntl |= RADEON_FP2_BLANK_EN;
- }
- } else if (radeon_output->MonType == MT_LCD) {
- unsigned long tmpPixclksCntl = INPLL(pScrn, RADEON_PIXCLKS_CNTL);
- if (info->IsMobility || info->IsIGP) {
- /* Asic bug, when turning off LVDS_ON, we have to make sure
- RADEON_PIXCLK_LVDS_ALWAYS_ON bit is off
- */
- OUTPLLP(pScrn, RADEON_PIXCLKS_CNTL, 0, ~RADEON_PIXCLK_LVDS_ALWAYS_ONb);
+ if (radeon_output->MonType == MT_CRT) {
+ if (radeon_output->DACType == DAC_PRIMARY) {
+ info->output_crt1 &= ~(1 << o);
+ if (!info->output_crt1) {
+ tmp = INREG(RADEON_CRTC_EXT_CNTL);
+ tmp &= ~RADEON_CRTC_CRT_ON;
+ OUTREG(RADEON_CRTC_EXT_CNTL, tmp);
+ save->crtc_ext_cntl &= ~RADEON_CRTC_CRT_ON;
+ RADEONDacPowerSet(pScrn, bEnable, (radeon_output->DACType == DAC_PRIMARY));
+ }
+ } else if (radeon_output->DACType == DAC_TVDAC) {
+ info->output_crt2 &= ~(1 << o);
+ tv_dac_change = 1;
+ if (!info->output_crt2) {
+ if (info->ChipFamily == CHIP_FAMILY_R200) {
+ tmp = INREG(RADEON_FP2_GEN_CNTL);
+ tmp &= ~(RADEON_FP2_ON | RADEON_FP2_DVO_EN);
+ OUTREG(RADEON_FP2_GEN_CNTL, tmp);
+ save->fp2_gen_cntl &= ~(RADEON_FP2_ON | RADEON_FP2_DVO_EN);
+ } else {
+ tmp = INREG(RADEON_CRTC2_GEN_CNTL);
+ tmp &= ~RADEON_CRTC2_CRT2_ON;
+ OUTREG(RADEON_CRTC2_GEN_CNTL, tmp);
+ save->crtc2_gen_cntl &= ~RADEON_CRTC2_CRT2_ON;
+ }
+ }
}
- tmp = INREG(RADEON_LVDS_GEN_CNTL);
- tmp |= RADEON_LVDS_DISPLAY_DIS;
- tmp &= ~(RADEON_LVDS_ON | RADEON_LVDS_BLON);
- OUTREG(RADEON_LVDS_GEN_CNTL, tmp);
- save->lvds_gen_cntl |= RADEON_LVDS_DISPLAY_DIS;
- save->lvds_gen_cntl &= ~(RADEON_LVDS_ON | RADEON_LVDS_BLON);
- if (info->IsMobility || info->IsIGP) {
- OUTPLL(pScrn, RADEON_PIXCLKS_CNTL, tmpPixclksCntl);
+ } else if (radeon_output->MonType == MT_DFP) {
+ if (radeon_output->TMDSType == TMDS_INT) {
+ info->output_dfp1 &= ~(1 << o);
+ if (!info->output_dfp1) {
+ tmp = INREG(RADEON_FP_GEN_CNTL);
+ tmp &= ~(RADEON_FP_FPON | RADEON_FP_TMDS_EN);
+ OUTREG(RADEON_FP_GEN_CNTL, tmp);
+ save->fp_gen_cntl &= ~(RADEON_FP_FPON | RADEON_FP_TMDS_EN);
+ }
+ } else if (radeon_output->TMDSType == TMDS_EXT) {
+ info->output_dfp2 &= ~(1 << o);
+ if (!info->output_dfp2) {
+ tmp = INREG(RADEON_FP2_GEN_CNTL);
+ tmp |= RADEON_FP2_BLANK_EN;
+ tmp &= ~(RADEON_FP2_ON | RADEON_FP2_DVO_EN);
+ OUTREG(RADEON_FP2_GEN_CNTL, tmp);
+ save->fp2_gen_cntl &= ~(RADEON_FP2_ON | RADEON_FP2_DVO_EN);
+ save->fp2_gen_cntl |= RADEON_FP2_BLANK_EN;
+ }
+ }
+ } else if (radeon_output->MonType == MT_LCD) {
+ info->output_lcd1 &= ~(1 << o);
+ if (!info->output_lcd1) {
+ unsigned long tmpPixclksCntl = INPLL(pScrn, RADEON_PIXCLKS_CNTL);
+ if (info->IsMobility || info->IsIGP) {
+ /* Asic bug, when turning off LVDS_ON, we have to make sure
+ RADEON_PIXCLK_LVDS_ALWAYS_ON bit is off
+ */
+ OUTPLLP(pScrn, RADEON_PIXCLKS_CNTL, 0, ~RADEON_PIXCLK_LVDS_ALWAYS_ONb);
+ }
+ tmp = INREG(RADEON_LVDS_GEN_CNTL);
+ tmp |= RADEON_LVDS_DISPLAY_DIS;
+ tmp &= ~(RADEON_LVDS_ON | RADEON_LVDS_BLON | RADEON_LVDS_EN);
+ OUTREG(RADEON_LVDS_GEN_CNTL, tmp);
+ save->lvds_gen_cntl |= RADEON_LVDS_DISPLAY_DIS;
+ save->lvds_gen_cntl &= ~(RADEON_LVDS_ON | RADEON_LVDS_BLON | RADEON_LVDS_EN);
+ if (info->IsMobility || info->IsIGP) {
+ OUTPLL(pScrn, RADEON_PIXCLKS_CNTL, tmpPixclksCntl);
+ }
+ }
+ } else if (radeon_output->MonType == MT_STV || radeon_output->MonType == MT_CTV) {
+ info->output_tv1 &= ~(1 << o);
+ tv_dac_change = 2;
+ if (!info->output_tv1) {
+ tmp = INREG(RADEON_TV_MASTER_CNTL);
+ tmp &= ~RADEON_TV_ON;
+ OUTREG(RADEON_TV_MASTER_CNTL, tmp);
+ radeon_output->tv_on = FALSE;
}
- } else if (radeon_output->MonType == MT_STV || radeon_output->MonType == MT_CTV) {
- tmp = INREG(RADEON_TV_MASTER_CNTL);
- tmp &= ~RADEON_TV_ON;
- OUTREG(RADEON_TV_MASTER_CNTL, tmp);
- tv_dac_change = 2;
- radeon_output->tv_on = FALSE;
}
}
if (tv_dac_change) {
if (bEnable)
- info->tv_dac_enable_mask |= tv_dac_change;
+ info->tv_dac_enable_mask |= tv_dac_change;
else
- info->tv_dac_enable_mask &= ~tv_dac_change;
+ info->tv_dac_enable_mask &= ~tv_dac_change;
if (bEnable && info->tv_dac_enable_mask)
RADEONDacPowerSet(pScrn, bEnable, (radeon_output->DACType == DAC_PRIMARY));
@@ -487,13 +518,13 @@ void RADEONInitDispBandwidth2(ScrnInfoPtr pScrn, RADEONInfoPtr info, int pixel_b
int stop_req, max_stop_req;
float read_return_rate, time_disp1_drop_priority;
- /*
- * Set display0/1 priority up on r3/4xx in the memory controller for
- * high res modes if the user specifies HIGH for displaypriority
+ /*
+ * Set display0/1 priority up on r3/4xx in the memory controller for
+ * high res modes if the user specifies HIGH for displaypriority
* option.
*/
if ((info->DispPriority == 2) && IS_R300_VARIANT) {
- CARD32 mc_init_misc_lat_timer = INREG(R300_MC_INIT_MISC_LAT_TIMER);
+ CARD32 mc_init_misc_lat_timer = INREG(R300_MC_INIT_MISC_LAT_TIMER);
if (pRADEONEnt->pCrtc[1]->enabled) {
mc_init_misc_lat_timer |= 0x1100; /* display 0 and 1 */
} else {
@@ -522,14 +553,14 @@ void RADEONInitDispBandwidth2(ScrnInfoPtr pScrn, RADEONInfoPtr info, int pixel_b
peak_disp_bw += (pix_clk2 * pixel_bytes2);
if (peak_disp_bw >= mem_bw * min_mem_eff) {
- xf86DrvMsg(pScrn->scrnIndex, X_WARNING,
+ xf86DrvMsg(pScrn->scrnIndex, X_WARNING,
"You may not have enough display bandwidth for current mode\n"
"If you have flickering problem, try to lower resolution, refresh rate, or color depth\n");
- }
+ }
/* CRTC1
Set GRPH_BUFFER_CNTL register using h/w defined optimal values.
- GRPH_STOP_REQ <= MIN[ 0x7C, (CRTC_H_DISP + 1) * (bit depth) / 0x10 ]
+ GRPH_STOP_REQ <= MIN[ 0x7C, (CRTC_H_DISP + 1) * (bit depth) / 0x10 ]
*/
stop_req = mode1->HDisplay * info->CurrentLayout.pixel_bytes / 16;
@@ -540,7 +571,7 @@ void RADEONInitDispBandwidth2(ScrnInfoPtr pScrn, RADEONInfoPtr info, int pixel_b
max_stop_req = 0x7c;
if (stop_req > max_stop_req)
stop_req = max_stop_req;
-
+
/* Get values from the EXT_MEM_CNTL register...converting its contents. */
temp = INREG(RADEON_MEM_TIMING_CNTL);
if ((info->ChipFamily == CHIP_FAMILY_RV100) || info->IsIGP) { /* RV100, M6, IGPs */
@@ -552,8 +583,8 @@ void RADEONInitDispBandwidth2(ScrnInfoPtr pScrn, RADEONInfoPtr info, int pixel_b
mem_trp = MemTrpMemTimingCntl[ (temp & 0x700) >> 8];
mem_tras = MemTrasMemTimingCntl[(temp & 0xf000) >> 12];
}
-
- /* Get values from the MEM_SDRAM_MODE_REG register...converting its */
+
+ /* Get values from the MEM_SDRAM_MODE_REG register...converting its */
temp = INREG(RADEON_MEM_SDRAM_MODE_REG);
data = (temp & (7<<20)) >> 20;
if ((info->ChipFamily == CHIP_FAMILY_RV100) || info->IsIGP) { /* RV100, M6, IGPs */
@@ -625,7 +656,7 @@ void RADEONInitDispBandwidth2(ScrnInfoPtr pScrn, RADEONInfoPtr info, int pixel_b
}
mc_latency_sclk = sclk_delay / sclk_eff;
-
+
if (info->IsDDR) {
if (info->RamWidth == 32) {
k1 = 40;
@@ -667,7 +698,7 @@ void RADEONInitDispBandwidth2(ScrnInfoPtr pScrn, RADEONInfoPtr info, int pixel_b
/*
Find the critical point of the display buffer.
*/
- critical_point= (CARD32)(disp_drain_rate * disp_latency + 0.5);
+ critical_point= (CARD32)(disp_drain_rate * disp_latency + 0.5);
/* ???? */
/*
@@ -682,7 +713,7 @@ void RADEONInitDispBandwidth2(ScrnInfoPtr pScrn, RADEONInfoPtr info, int pixel_b
The critical point should never be above max_stop_req-4. Setting
GRPH_CRITICAL_CNTL = 0 will thus force high priority all the time.
*/
- if (max_stop_req - critical_point < 4) critical_point = 0;
+ if (max_stop_req - critical_point < 4) critical_point = 0;
if (critical_point == 0 && mode2 && info->ChipFamily == CHIP_FAMILY_R300) {
/* some R300 cards have problem with this set to 0, when CRTC2 is enabled.*/
@@ -712,7 +743,7 @@ void RADEONInitDispBandwidth2(ScrnInfoPtr pScrn, RADEONInfoPtr info, int pixel_b
xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG,
"GRPH_BUFFER_CNTL from %x to %x\n",
(unsigned int)info->SavedReg.grph_buffer_cntl,
- INREG(RADEON_GRPH_BUFFER_CNTL));
+ (unsigned int)INREG(RADEON_GRPH_BUFFER_CNTL));
if (mode2) {
stop_req = mode2->HDisplay * pixel_bytes2 / 16;
@@ -733,7 +764,7 @@ void RADEONInitDispBandwidth2(ScrnInfoPtr pScrn, RADEONInfoPtr info, int pixel_b
RADEON_GRPH_CRITICAL_AT_SOF |
RADEON_GRPH_STOP_CNTL);
- if ((info->ChipFamily == CHIP_FAMILY_RS100) ||
+ if ((info->ChipFamily == CHIP_FAMILY_RS100) ||
(info->ChipFamily == CHIP_FAMILY_RS200))
critical_point2 = 0;
else {
@@ -762,7 +793,7 @@ void RADEONInitDispBandwidth2(ScrnInfoPtr pScrn, RADEONInfoPtr info, int pixel_b
xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG,
"GRPH2_BUFFER_CNTL from %x to %x\n",
(unsigned int)info->SavedReg.grph2_buffer_cntl,
- INREG(RADEON_GRPH2_BUFFER_CNTL));
+ (unsigned int)INREG(RADEON_GRPH2_BUFFER_CNTL));
}
}
@@ -810,7 +841,7 @@ void RADEONBlank(ScrnInfoPtr pScrn)
for (c = 0; c < xf86_config->num_crtc; c++) {
crtc = xf86_config->crtc[c];
- for (o = 0; o < xf86_config->num_output; o++) {
+ for (o = 0; o < xf86_config->num_output; o++) {
output = xf86_config->output[o];
if (output->crtc != crtc)
continue;
@@ -833,7 +864,7 @@ void RADEONUnblank(ScrnInfoPtr pScrn)
if(!crtc->enabled)
continue;
crtc->funcs->dpms(crtc, DPMSModeOn);
- for (o = 0; o < xf86_config->num_output; o++) {
+ for (o = 0; o < xf86_config->num_output; o++) {
output = xf86_config->output[o];
if (output->crtc != crtc)
continue;
diff --git a/src/radeon_dri.c b/src/radeon_dri.c
index 2c533b1..3190451 100644
--- a/src/radeon_dri.c
+++ b/src/radeon_dri.c
@@ -559,12 +559,12 @@ static void RADEONDRIMoveBuffers(WindowPtr pParent, DDXPointRec ptOldOrg,
if (nbox > 1) {
/* Keep ordering in each band, reverse order of bands */
- pboxNew1 = (BoxPtr)ALLOCATE_LOCAL(sizeof(BoxRec)*nbox);
+ pboxNew1 = (BoxPtr)xalloc(sizeof(BoxRec)*nbox);
if (!pboxNew1) return;
- pptNew1 = (DDXPointPtr)ALLOCATE_LOCAL(sizeof(DDXPointRec)*nbox);
+ pptNew1 = (DDXPointPtr)xalloc(sizeof(DDXPointRec)*nbox);
if (!pptNew1) {
- DEALLOCATE_LOCAL(pboxNew1);
+ xfree(pboxNew1);
return;
}
@@ -601,14 +601,14 @@ static void RADEONDRIMoveBuffers(WindowPtr pParent, DDXPointRec ptOldOrg,
if (nbox > 1) {
/* reverse order of rects in each band */
- pboxNew2 = (BoxPtr)ALLOCATE_LOCAL(sizeof(BoxRec)*nbox);
- pptNew2 = (DDXPointPtr)ALLOCATE_LOCAL(sizeof(DDXPointRec)*nbox);
+ pboxNew2 = (BoxPtr)xalloc(sizeof(BoxRec)*nbox);
+ pptNew2 = (DDXPointPtr)xalloc(sizeof(DDXPointRec)*nbox);
if (!pboxNew2 || !pptNew2) {
- DEALLOCATE_LOCAL(pptNew2);
- DEALLOCATE_LOCAL(pboxNew2);
- DEALLOCATE_LOCAL(pptNew1);
- DEALLOCATE_LOCAL(pboxNew1);
+ xfree(pptNew2);
+ xfree(pboxNew2);
+ xfree(pptNew1);
+ xfree(pboxNew1);
return;
}
@@ -679,10 +679,10 @@ static void RADEONDRIMoveBuffers(WindowPtr pParent, DDXPointRec ptOldOrg,
info->dst_pitch_offset = info->frontPitchOffset;;
- DEALLOCATE_LOCAL(pptNew2);
- DEALLOCATE_LOCAL(pboxNew2);
- DEALLOCATE_LOCAL(pptNew1);
- DEALLOCATE_LOCAL(pboxNew1);
+ xfree(pptNew2);
+ xfree(pboxNew2);
+ xfree(pptNew1);
+ xfree(pboxNew1);
info->accel->NeedToSync = TRUE;
#endif /* USE_XAA */
@@ -722,20 +722,13 @@ static Bool RADEONSetAgpMode(RADEONInfoPtr info, ScreenPtr pScreen)
unsigned long mode = drmAgpGetMode(info->drmFD); /* Default mode */
unsigned int vendor = drmAgpVendorId(info->drmFD);
unsigned int device = drmAgpDeviceId(info->drmFD);
- CARD32 agp_status = INREG(RADEON_AGP_STATUS) & mode;
+ /* ignore agp 3.0 mode bit from the chip as it's buggy on some cards with
+ pcie-agp rialto bridge chip - use the one from bridge which must match */
+ CARD32 agp_status = (INREG(RADEON_AGP_STATUS) | RADEON_AGPv3_MODE) & mode;
Bool is_v3 = (agp_status & RADEON_AGPv3_MODE);
- unsigned int defaultMode;
- MessageType from;
-
- if (is_v3) {
- defaultMode = (agp_status & RADEON_AGPv3_8X_MODE) ? 8 : 4;
- } else {
- if (agp_status & RADEON_AGP_4X_MODE) defaultMode = 4;
- else if (agp_status & RADEON_AGP_2X_MODE) defaultMode = 2;
- else defaultMode = 1;
- }
-
- from = X_DEFAULT;
+ unsigned int defaultMode = is_v3 ?
+ ((agp_status & RADEON_AGPv3_8X_MODE) ? 8 : 4) : 1;
+ MessageType from = X_DEFAULT;
if (xf86GetOptValInteger(info->Options, OPTION_AGP_MODE, &info->agpMode)) {
if ((info->agpMode < (is_v3 ? 4 : 1)) ||
@@ -1359,6 +1352,9 @@ Bool RADEONDRISetVBlankInterrupt(ScrnInfoPtr pScrn, Bool on)
xf86CrtcConfigPtr xf86_config = XF86_CRTC_CONFIG_PTR(pScrn);
int value = 0;
+ if (!info->want_vblank_interrupts)
+ on = FALSE;
+
if (info->directRenderingEnabled && info->pKernelDRMVersion->version_minor >= 28) {
if (on) {
if (xf86_config->num_crtc > 1 && xf86_config->crtc[1]->enabled)
diff --git a/src/radeon_driver.c b/src/radeon_driver.c
index e027379..25b2119 100644
--- a/src/radeon_driver.c
+++ b/src/radeon_driver.c
@@ -90,7 +90,6 @@
/* X and server generic header files */
#include "xf86.h"
-#include "xf86_ansic.h" /* For xf86getsecs() */
#include "xf86_OSproc.h"
#include "xf86RAC.h"
#include "xf86RandR12.h"
@@ -107,9 +106,10 @@
#include <X11/extensions/dpms.h>
#include "atipciids.h"
-#include "radeon_chipset.h"
+#include "radeon_chipset_gen.h"
+#include "radeon_chipinfo_gen.h"
/* Forward definitions for driver functions */
static Bool RADEONCloseScreen(int scrnIndex, ScreenPtr pScreen);
@@ -191,6 +191,8 @@ static const OptionInfoRec RADEONOptions[] = {
{ OPTION_MAC_MODEL, "MacModel", OPTV_STRING, {0}, FALSE },
#endif
{ OPTION_TVDAC_LOAD_DETECT, "TVDACLoadDetect", OPTV_BOOLEAN, {0}, FALSE },
+ { OPTION_FORCE_TVOUT, "ForceTVOut", OPTV_BOOLEAN, {0}, FALSE },
+ { OPTION_TVSTD, "TVStandard", OPTV_STRING, {0}, FALSE },
{ -1, NULL, OPTV_NONE, {0}, FALSE }
};
@@ -802,8 +804,8 @@ static Bool RADEONProbePLLParameters(ScrnInfoPtr pScrn)
unsigned xclk, tmp, ref_div;
int hTotal, vTotal, num, denom, m, n;
float hz, prev_xtal, vclk, xtal, mpll, spll;
- long start_secs, start_usecs, stop_secs, stop_usecs, total_usecs;
- long to1_secs, to1_usecs, to2_secs, to2_usecs;
+ long total_usecs;
+ struct timeval start, stop, to1, to2;
unsigned int f1, f2, f3;
int tries = 0;
@@ -813,32 +815,32 @@ static Bool RADEONProbePLLParameters(ScrnInfoPtr pScrn)
if (++tries > 10)
goto failed;
- xf86getsecs(&to1_secs, &to1_usecs);
+ gettimeofday(&to1, NULL);
f1 = INREG(RADEON_CRTC_CRNT_FRAME);
for (;;) {
f2 = INREG(RADEON_CRTC_CRNT_FRAME);
if (f1 != f2)
break;
- xf86getsecs(&to2_secs, &to2_usecs);
- if ((to2_secs - to1_secs) > 1) {
+ gettimeofday(&to2, NULL);
+ if ((to2.tv_sec - to1.tv_sec) > 1) {
xf86DrvMsg(pScrn->scrnIndex, X_WARNING, "Clock not counting...\n");
goto failed;
}
}
- xf86getsecs(&start_secs, &start_usecs);
+ gettimeofday(&start, NULL);
for(;;) {
f3 = INREG(RADEON_CRTC_CRNT_FRAME);
if (f3 != f2)
break;
- xf86getsecs(&to2_secs, &to2_usecs);
- if ((to2_secs - start_secs) > 1)
+ gettimeofday(&to2, NULL);
+ if ((to2.tv_sec - start.tv_sec) > 1)
goto failed;
}
- xf86getsecs(&stop_secs, &stop_usecs);
+ gettimeofday(&stop, NULL);
- if ((stop_secs - start_secs) != 0)
+ if ((stop.tv_sec - start.tv_sec) != 0)
goto again;
- total_usecs = abs(stop_usecs - start_usecs);
+ total_usecs = abs(stop.tv_usec - start.tv_usec);
if (total_usecs == 0)
goto again;
hz = 1000000.0/(float)total_usecs;
@@ -1061,8 +1063,17 @@ static void RADEONGetClockInfo(ScrnInfoPtr pScrn)
info->RamWidth / 16);
}
+ /* card limits for computing PLLs */
+ pll->min_ref_div = 2;
+ pll->max_ref_div = 0x3ff;
+ pll->min_feedback_div = 4;
+ pll->max_feedback_div = 0x7ff;
+ pll->pll_in_min = 40;
+ pll->pll_in_max = 500;
+ pll->best_vco = 0;
+
xf86DrvMsg (pScrn->scrnIndex, X_INFO,
- "PLL parameters: rf=%d rd=%d min=%d max=%d; xclk=%d\n",
+ "PLL parameters: rf=%u rd=%u min=%u max=%u; xclk=%u\n",
pll->reference_freq,
pll->reference_div,
(unsigned)pll->min_pll_freq, (unsigned)pll->max_pll_freq,
@@ -1472,6 +1483,7 @@ static Bool RADEONPreInitChipType(ScrnInfoPtr pScrn)
GDevPtr dev = pEnt->device;
unsigned char *RADEONMMIO = info->MMIO;
MessageType from = X_PROBED;
+ int i;
#ifdef XF86DRI
const char *s;
uint32_t cmd_stat;
@@ -1511,20 +1523,25 @@ static Bool RADEONPreInitChipType(ScrnInfoPtr pScrn)
info->IsDellServer = FALSE;
info->HasSingleDAC = FALSE;
info->InternalTVOut = TRUE;
- switch (info->Chipset) {
- case PCI_CHIP_RADEON_LY:
- case PCI_CHIP_RADEON_LZ:
- info->IsMobility = TRUE;
- info->ChipFamily = CHIP_FAMILY_RV100;
- break;
+ for (i = 0; i < sizeof(RADEONCards) / sizeof(RADEONCardInfo); i++) {
+ if (info->Chipset == RADEONCards[i].pci_device_id) {
+ RADEONCardInfo *card = &RADEONCards[i];
+ info->ChipFamily = card->chip_family;
+ info->IsMobility = card->mobility;
+ info->IsIGP = card->igp;
+ pRADEONEnt->HasCRTC2 = !card->nocrtc2;
+ info->HasSingleDAC = card->singledac;
+ info->InternalTVOut = !card->nointtvout;
+ break;
+ }
+ }
+
+ switch (info->Chipset) {
case PCI_CHIP_RN50_515E: /* RN50 is based on the RV100 but 3D isn't guaranteed to work. YMMV. */
case PCI_CHIP_RN50_5969:
- pRADEONEnt->HasCRTC2 = FALSE;
case PCI_CHIP_RV100_QY:
case PCI_CHIP_RV100_QZ:
- info->ChipFamily = CHIP_FAMILY_RV100;
-
/* DELL triple-head configuration. */
if ((PCI_SUB_VENDOR_ID(info->PciInfo) == PCI_VENDOR_DELL) &&
((PCI_SUB_DEVICE_ID(info->PciInfo) == 0x016c) ||
@@ -1540,220 +1557,9 @@ static Bool RADEONPreInitChipType(ScrnInfoPtr pScrn)
info->IsDellServer = TRUE;
xf86DrvMsg(pScrn->scrnIndex, X_INFO, "DELL server detected, force to special setup\n");
}
-
- break;
-
- case PCI_CHIP_RS100_4336:
- info->IsMobility = TRUE;
- case PCI_CHIP_RS100_4136:
- info->ChipFamily = CHIP_FAMILY_RS100;
- info->IsIGP = TRUE;
- break;
-
- case PCI_CHIP_RS200_4337:
- info->IsMobility = TRUE;
- case PCI_CHIP_RS200_4137:
- info->ChipFamily = CHIP_FAMILY_RS200;
- info->IsIGP = TRUE;
- break;
-
- case PCI_CHIP_RS250_4437:
- info->IsMobility = TRUE;
- case PCI_CHIP_RS250_4237:
- info->ChipFamily = CHIP_FAMILY_RS200;
- info->IsIGP = TRUE;
- break;
-
- case PCI_CHIP_R200_BB:
- case PCI_CHIP_R200_BC:
- case PCI_CHIP_R200_QH:
- case PCI_CHIP_R200_QL:
- case PCI_CHIP_R200_QM:
- info->ChipFamily = CHIP_FAMILY_R200;
- info->InternalTVOut = FALSE;
- break;
-
- case PCI_CHIP_RADEON_LW:
- case PCI_CHIP_RADEON_LX:
- info->IsMobility = TRUE;
- case PCI_CHIP_RV200_QW: /* RV200 desktop */
- case PCI_CHIP_RV200_QX:
- info->ChipFamily = CHIP_FAMILY_RV200;
- break;
-
- case PCI_CHIP_RV250_Ld:
- case PCI_CHIP_RV250_Lf:
- case PCI_CHIP_RV250_Lg:
- info->IsMobility = TRUE;
- case PCI_CHIP_RV250_If:
- case PCI_CHIP_RV250_Ig:
- info->ChipFamily = CHIP_FAMILY_RV250;
- break;
-
- case PCI_CHIP_RS300_5835:
- case PCI_CHIP_RS350_7835:
- info->IsMobility = TRUE;
- case PCI_CHIP_RS300_5834:
- case PCI_CHIP_RS350_7834:
- info->ChipFamily = CHIP_FAMILY_RS300;
- info->IsIGP = TRUE;
- info->HasSingleDAC = TRUE;
- break;
-
- case PCI_CHIP_RV280_5C61:
- case PCI_CHIP_RV280_5C63:
- info->IsMobility = TRUE;
- case PCI_CHIP_RV280_5960:
- case PCI_CHIP_RV280_5961:
- case PCI_CHIP_RV280_5962:
- case PCI_CHIP_RV280_5964:
- case PCI_CHIP_RV280_5965:
- info->ChipFamily = CHIP_FAMILY_RV280;
break;
-
- case PCI_CHIP_R300_AD:
- case PCI_CHIP_R300_AE:
- case PCI_CHIP_R300_AF:
- case PCI_CHIP_R300_AG:
- case PCI_CHIP_R300_ND:
- case PCI_CHIP_R300_NE:
- case PCI_CHIP_R300_NF:
- case PCI_CHIP_R300_NG:
- info->ChipFamily = CHIP_FAMILY_R300;
- break;
-
- case PCI_CHIP_RV350_NP:
- case PCI_CHIP_RV350_NQ:
- case PCI_CHIP_RV350_NR:
- case PCI_CHIP_RV350_NS:
- case PCI_CHIP_RV350_NT:
- case PCI_CHIP_RV350_NV:
- info->IsMobility = TRUE;
- case PCI_CHIP_RV350_AP:
- case PCI_CHIP_RV350_AQ:
- case PCI_CHIP_RV360_AR:
- case PCI_CHIP_RV350_AS:
- case PCI_CHIP_RV350_AT:
- case PCI_CHIP_RV350_AV:
- case PCI_CHIP_RV350_4155:
- info->ChipFamily = CHIP_FAMILY_RV350;
- break;
-
- case PCI_CHIP_R350_AH:
- case PCI_CHIP_R350_AI:
- case PCI_CHIP_R350_AJ:
- case PCI_CHIP_R350_AK:
- case PCI_CHIP_R350_NH:
- case PCI_CHIP_R350_NI:
- case PCI_CHIP_R350_NK:
- case PCI_CHIP_R360_NJ:
- info->ChipFamily = CHIP_FAMILY_R350;
- break;
-
- case PCI_CHIP_RV380_3150:
- case PCI_CHIP_RV380_3152:
- case PCI_CHIP_RV380_3154:
- info->IsMobility = TRUE;
- case PCI_CHIP_RV380_3E50:
- case PCI_CHIP_RV380_3E54:
- info->ChipFamily = CHIP_FAMILY_RV380;
- break;
-
- case PCI_CHIP_RV370_5460:
- case PCI_CHIP_RV370_5462:
- case PCI_CHIP_RV370_5464:
- info->IsMobility = TRUE;
- case PCI_CHIP_RV370_5B60:
- case PCI_CHIP_RV370_5B62:
- case PCI_CHIP_RV370_5B63:
- case PCI_CHIP_RV370_5B64:
- case PCI_CHIP_RV370_5B65:
- info->ChipFamily = CHIP_FAMILY_RV380;
- break;
-
- case PCI_CHIP_RS400_5A42:
- case PCI_CHIP_RC410_5A62:
- case PCI_CHIP_RS480_5955:
- case PCI_CHIP_RS485_5975:
- info->IsMobility = TRUE;
- case PCI_CHIP_RS400_5A41:
- case PCI_CHIP_RC410_5A61:
- case PCI_CHIP_RS480_5954:
- case PCI_CHIP_RS482_5974:
- info->ChipFamily = CHIP_FAMILY_RS400;
- info->IsIGP = TRUE;
- info->HasSingleDAC = TRUE;
- break;
-
- case PCI_CHIP_RV410_564A:
- case PCI_CHIP_RV410_564B:
- case PCI_CHIP_RV410_564F:
- case PCI_CHIP_RV410_5652:
- case PCI_CHIP_RV410_5653:
- info->IsMobility = TRUE;
- case PCI_CHIP_RV410_5E48:
- case PCI_CHIP_RV410_5E4B:
- case PCI_CHIP_RV410_5E4A:
- case PCI_CHIP_RV410_5E4D:
- case PCI_CHIP_RV410_5E4C:
- case PCI_CHIP_RV410_5E4F:
- info->ChipFamily = CHIP_FAMILY_RV410;
- break;
-
- case PCI_CHIP_R420_JN:
- info->IsMobility = TRUE;
- case PCI_CHIP_R420_JH:
- case PCI_CHIP_R420_JI:
- case PCI_CHIP_R420_JJ:
- case PCI_CHIP_R420_JK:
- case PCI_CHIP_R420_JL:
- case PCI_CHIP_R420_JM:
- case PCI_CHIP_R420_JP:
- case PCI_CHIP_R420_4A4F:
- info->ChipFamily = CHIP_FAMILY_R420;
- break;
-
- case PCI_CHIP_R423_UH:
- case PCI_CHIP_R423_UI:
- case PCI_CHIP_R423_UJ:
- case PCI_CHIP_R423_UK:
- case PCI_CHIP_R423_UQ:
- case PCI_CHIP_R423_UR:
- case PCI_CHIP_R423_UT:
- case PCI_CHIP_R423_5D57:
- case PCI_CHIP_R423_5550:
- info->ChipFamily = CHIP_FAMILY_R420;
- break;
-
- case PCI_CHIP_R430_5D49:
- case PCI_CHIP_R430_5D4A:
- case PCI_CHIP_R430_5D48:
- info->IsMobility = TRUE;
- case PCI_CHIP_R430_554F:
- case PCI_CHIP_R430_554D:
- case PCI_CHIP_R430_554E:
- case PCI_CHIP_R430_554C:
- info->ChipFamily = CHIP_FAMILY_R420; /*CHIP_FAMILY_R430*/
- break;
-
- case PCI_CHIP_R480_5D4C:
- case PCI_CHIP_R480_5D50:
- case PCI_CHIP_R480_5D4E:
- case PCI_CHIP_R480_5D4F:
- case PCI_CHIP_R480_5D52:
- case PCI_CHIP_R480_5D4D:
- case PCI_CHIP_R481_4B4B:
- case PCI_CHIP_R481_4B4A:
- case PCI_CHIP_R481_4B49:
- case PCI_CHIP_R481_4B4C:
- info->ChipFamily = CHIP_FAMILY_R420; /*CHIP_FAMILY_R480*/
- break;
-
default:
- /* Original Radeon/7200 */
- info->ChipFamily = CHIP_FAMILY_RADEON;
- pRADEONEnt->HasCRTC2 = FALSE;
- info->InternalTVOut = FALSE;
+ break;
}
@@ -3736,10 +3542,6 @@ Bool RADEONScreenInit(int scrnIndex, ScreenPtr pScreen,
if (!info->useEXA) {
int width, height;
- xf86DrvMsg(pScrn->scrnIndex, X_INFO,
- "Using hardware cursor (scanline %u)\n",
- (unsigned)(info->cursor_offset / pScrn->displayWidth
- / info->CurrentLayout.pixel_bytes));
if (xf86QueryLargestOffscreenArea(pScreen, &width, &height,
0, 0, 0)) {
xf86DrvMsg(scrnIndex, X_INFO,
@@ -3754,7 +3556,6 @@ Bool RADEONScreenInit(int scrnIndex, ScreenPtr pScreen,
xf86DrvMsg(scrnIndex, X_INFO, "Using software cursor\n");
}
} else {
- info->cursor_offset = 0;
xf86DrvMsg(scrnIndex, X_INFO, "Using software cursor\n");
}
@@ -4237,6 +4038,10 @@ void RADEONRestoreLVDSRegisters(ScrnInfoPtr pScrn, RADEONSavePtr restore)
if (info->IsMobility) {
OUTREG(RADEON_LVDS_GEN_CNTL, restore->lvds_gen_cntl);
OUTREG(RADEON_LVDS_PLL_CNTL, restore->lvds_pll_cntl);
+
+ if (info->ChipFamily == CHIP_FAMILY_RV410) {
+ OUTREG(RADEON_CLOCK_CNTL_INDEX, 0);
+ }
}
}
@@ -4245,10 +4050,13 @@ void RADEONRestoreBIOSRegisters(ScrnInfoPtr pScrn, RADEONSavePtr restore)
{
RADEONInfoPtr info = RADEONPTR(pScrn);
unsigned char *RADEONMMIO = info->MMIO;
+ CARD32 bios_5_scratch = INREG(RADEON_BIOS_5_SCRATCH);
CARD32 bios_6_scratch = INREG(RADEON_BIOS_6_SCRATCH);
OUTREG(RADEON_BIOS_4_SCRATCH, restore->bios_4_scratch);
- OUTREG(RADEON_BIOS_5_SCRATCH, restore->bios_5_scratch);
+ bios_5_scratch &= 0xF;
+ bios_5_scratch |= (restore->bios_5_scratch & ~0xF);
+ OUTREG(RADEON_BIOS_5_SCRATCH, bios_5_scratch);
if (restore->bios_6_scratch & 0x40000000)
bios_6_scratch |= 0x40000000;
else
@@ -4904,9 +4712,9 @@ void RADEONChangeSurfaces(ScrnInfoPtr pScrn)
retvalue = drmCommandWrite(info->drmFD, DRM_RADEON_SURF_FREE,
&drmsurffree, sizeof(drmsurffree));
- if ((info->ChipFamily != CHIP_FAMILY_RV100) ||
- (info->ChipFamily != CHIP_FAMILY_RS100) ||
- (info->ChipFamily != CHIP_FAMILY_RS200)) {
+ if (!((info->ChipFamily == CHIP_FAMILY_RV100) ||
+ (info->ChipFamily == CHIP_FAMILY_RS100) ||
+ (info->ChipFamily == CHIP_FAMILY_RS200))) {
drmsurffree.address = info->depthOffset;
retvalue = drmCommandWrite(info->drmFD, DRM_RADEON_SURF_FREE,
&drmsurffree, sizeof(drmsurffree));
@@ -4961,9 +4769,10 @@ void RADEONChangeSurfaces(ScrnInfoPtr pScrn)
}
/* rv100 and probably the derivative igps don't have depth tiling on all the time? */
- if (info->have3DWindows && ((info->ChipFamily != CHIP_FAMILY_RV100) ||
- (info->ChipFamily != CHIP_FAMILY_RS100) ||
- (info->ChipFamily != CHIP_FAMILY_RS200))) {
+ if (info->have3DWindows &&
+ (!((info->ChipFamily == CHIP_FAMILY_RV100) ||
+ (info->ChipFamily == CHIP_FAMILY_RS100) ||
+ (info->ChipFamily == CHIP_FAMILY_RS200)))) {
drmRadeonSurfaceAlloc drmsurfalloc;
drmsurfalloc.size = depthBufferSize;
drmsurfalloc.address = info->depthOffset;
diff --git a/src/radeon_exa.c b/src/radeon_exa.c
index 8a12e1b..4da4841 100644
--- a/src/radeon_exa.c
+++ b/src/radeon_exa.c
@@ -374,6 +374,7 @@ Bool RADEONSetupMemEXA (ScreenPtr pScreen)
{
ScrnInfoPtr pScrn = xf86Screens[pScreen->myNum];
RADEONInfoPtr info = RADEONPTR(pScrn);
+ xf86CrtcConfigPtr xf86_config = XF86_CRTC_CONFIG_PTR(pScrn);
int cpp = info->CurrentLayout.pixel_bytes;
int screen_size;
int byteStride = pScrn->displayWidth * cpp;
@@ -405,14 +406,23 @@ Bool RADEONSetupMemEXA (ScreenPtr pScreen)
/* Reserve static area for hardware cursor */
if (!xf86ReturnOptValBool(info->Options, OPTION_SW_CURSOR, FALSE)) {
int cursor_size = 64 * 4 * 64;
+ int c;
- info->cursor_offset = info->exa->offScreenBase;
+ for (c = 0; c < xf86_config->num_crtc; c++) {
+ xf86CrtcPtr crtc = xf86_config->crtc[c];
+ RADEONCrtcPrivatePtr radeon_crtc = crtc->driver_private;
+
+ radeon_crtc->cursor_offset = info->exa->offScreenBase;
+ info->exa->offScreenBase += cursor_size;
+
+ xf86DrvMsg(pScrn->scrnIndex, X_INFO,
+ "Will use %d kb for hardware cursor %d at offset 0x%08x\n",
+ (cursor_size * xf86_config->num_crtc) / 1024,
+ c,
+ (unsigned int)radeon_crtc->cursor_offset);
+ }
- xf86DrvMsg(pScrn->scrnIndex, X_INFO,
- "Will use %d kb for hardware cursor at offset 0x%08x\n",
- cursor_size / 1024, (unsigned int)info->cursor_offset);
- info->exa->offScreenBase += cursor_size;
}
#if defined(XF86DRI)
diff --git a/src/radeon_exa_render.c b/src/radeon_exa_render.c
index 9251569..eae69c4 100644
--- a/src/radeon_exa_render.c
+++ b/src/radeon_exa_render.c
@@ -736,6 +736,21 @@ do { \
#endif /* !ACCEL_CP */
+#ifdef ONLY_ONCE
+static inline void transformPoint(PictTransform *transform, xPointFixed *point)
+{
+ PictVector v;
+ v.vector[0] = point->x;
+ v.vector[1] = point->y;
+ v.vector[2] = xFixed1;
+ PictureTransformPoint(transform, &v);
+ point->x = v.vector[0];
+ point->y = v.vector[1];
+}
+#endif
+
+#define xFixedToFloat(f) (((float) (f)) / 65536)
+
static void FUNC_NAME(RadeonComposite)(PixmapPtr pDst,
int srcX, int srcY,
int maskX, int maskY,
@@ -744,7 +759,8 @@ static void FUNC_NAME(RadeonComposite)(PixmapPtr pDst,
{
RINFO_FROM_SCREEN(pDst->drawable.pScreen);
int srcXend, srcYend, maskXend, maskYend;
- PictVector v;
+ xPointFixed srcTopLeft, srcTopRight, srcBottomLeft, srcBottomRight;
+ xPointFixed maskTopLeft, maskTopRight, maskBottomLeft, maskBottomRight;
ACCEL_PREAMBLE();
ENTER_DRAW(0);
@@ -756,33 +772,36 @@ static void FUNC_NAME(RadeonComposite)(PixmapPtr pDst,
srcYend = srcY + h;
maskXend = maskX + w;
maskYend = maskY + h;
+
+ srcTopLeft.x = IntToxFixed(srcX);
+ srcTopLeft.y = IntToxFixed(srcY);
+ srcTopRight.x = IntToxFixed(srcX + w);
+ srcTopRight.y = IntToxFixed(srcY);
+ srcBottomLeft.x = IntToxFixed(srcX);
+ srcBottomLeft.y = IntToxFixed(srcY + h);
+ srcBottomRight.x = IntToxFixed(srcX + w);
+ srcBottomRight.y = IntToxFixed(srcY + h);
+
+ maskTopLeft.x = IntToxFixed(maskX);
+ maskTopLeft.y = IntToxFixed(maskY);
+ maskTopRight.x = IntToxFixed(maskX + w);
+ maskTopRight.y = IntToxFixed(maskY);
+ maskBottomLeft.x = IntToxFixed(maskX);
+ maskBottomLeft.y = IntToxFixed(maskY + h);
+ maskBottomRight.x = IntToxFixed(maskX + w);
+ maskBottomRight.y = IntToxFixed(maskY + h);
+
if (is_transform[0]) {
- v.vector[0] = IntToxFixed(srcX);
- v.vector[1] = IntToxFixed(srcY);
- v.vector[2] = xFixed1;
- PictureTransformPoint(transform[0], &v);
- srcX = xFixedToInt(v.vector[0]);
- srcY = xFixedToInt(v.vector[1]);
- v.vector[0] = IntToxFixed(srcXend);
- v.vector[1] = IntToxFixed(srcYend);
- v.vector[2] = xFixed1;
- PictureTransformPoint(transform[0], &v);
- srcXend = xFixedToInt(v.vector[0]);
- srcYend = xFixedToInt(v.vector[1]);
+ transformPoint(transform[0], &srcTopLeft);
+ transformPoint(transform[0], &srcTopRight);
+ transformPoint(transform[0], &srcBottomLeft);
+ transformPoint(transform[0], &srcBottomRight);
}
if (is_transform[1]) {
- v.vector[0] = IntToxFixed(maskX);
- v.vector[1] = IntToxFixed(maskY);
- v.vector[2] = xFixed1;
- PictureTransformPoint(transform[1], &v);
- maskX = xFixedToInt(v.vector[0]);
- maskY = xFixedToInt(v.vector[1]);
- v.vector[0] = IntToxFixed(maskXend);
- v.vector[1] = IntToxFixed(maskYend);
- v.vector[2] = xFixed1;
- PictureTransformPoint(transform[1], &v);
- maskXend = xFixedToInt(v.vector[0]);
- maskYend = xFixedToInt(v.vector[1]);
+ transformPoint(transform[1], &maskTopLeft);
+ transformPoint(transform[1], &maskTopRight);
+ transformPoint(transform[1], &maskBottomLeft);
+ transformPoint(transform[1], &maskBottomRight);
}
#ifdef ACCEL_CP
@@ -828,18 +847,18 @@ static void FUNC_NAME(RadeonComposite)(PixmapPtr pDst,
VTX_OUT(dstX + w, dstY + h, srcXend, srcYend, maskXend, maskYend);
VTX_OUT(dstX + w, dstY, srcXend, srcY, maskXend, maskY);
} else {
- VTX_OUT((float)dstX, (float)dstY,
- (float)srcX / info->texW[0], (float)srcY / info->texH[0],
- (float)maskX / info->texW[1], (float)maskY / info->texH[1]);
- VTX_OUT((float)dstX, (float)(dstY + h),
- (float)srcX / info->texW[0], (float)srcYend / info->texH[0],
- (float)maskX / info->texW[1], (float)maskYend / info->texH[1]);
- VTX_OUT((float)(dstX + w), (float)(dstY + h),
- (float)srcXend / info->texW[0], (float)srcYend / info->texH[0],
- (float)maskXend / info->texW[1], (float)maskYend / info->texH[1]);
- VTX_OUT((float)(dstX + w), (float)dstY,
- (float)srcXend / info->texW[0], (float)srcY / info->texH[0],
- (float)maskXend / info->texW[1], (float)maskY / info->texH[1]);
+ VTX_OUT((float)dstX, (float)dstY,
+ xFixedToFloat(srcTopLeft.x) / info->texW[0], xFixedToFloat(srcTopLeft.y) / info->texH[0],
+ xFixedToFloat(maskTopLeft.x) / info->texW[1], xFixedToFloat(maskTopLeft.y) / info->texH[1]);
+ VTX_OUT((float)dstX, (float)(dstY + h),
+ xFixedToFloat(srcBottomLeft.x) / info->texW[0], xFixedToFloat(srcBottomLeft.y) / info->texH[0],
+ xFixedToFloat(maskBottomLeft.x) / info->texW[1], xFixedToFloat(maskBottomLeft.y) / info->texH[1]);
+ VTX_OUT((float)(dstX + w), (float)(dstY + h),
+ xFixedToFloat(srcBottomRight.x) / info->texW[0], xFixedToFloat(srcBottomRight.y) / info->texH[0],
+ xFixedToFloat(maskBottomRight.x) / info->texW[1], xFixedToFloat(maskBottomRight.y) / info->texH[1]);
+ VTX_OUT((float)(dstX + w), (float)dstY,
+ xFixedToFloat(srcTopRight.x) / info->texW[0], xFixedToFloat(srcTopRight.y) / info->texH[0],
+ xFixedToFloat(maskTopRight.x) / info->texW[1], xFixedToFloat(maskTopRight.y) / info->texH[1]);
}
#ifdef ACCEL_CP
diff --git a/src/radeon_output.c b/src/radeon_output.c
index 599a89c..6454460 100644
--- a/src/radeon_output.c
+++ b/src/radeon_output.c
@@ -218,22 +218,33 @@ RADEONRestoreDVOChip(ScrnInfoPtr pScrn, xf86OutputPtr output)
(CARD32)~(RADEON_GPIO_A_0 | RADEON_GPIO_A_1));
if (!RADEONInitExtTMDSInfoFromBIOS(output)) {
- /* do mac stuff here */
-#if defined(__powerpc__)
if (radeon_output->DVOChip) {
- switch(info->MacModel) {
- case RADEON_MAC_POWERBOOK_DL:
+ switch(info->ext_tmds_chip) {
+ case RADEON_SIL_164:
RADEONDVOWriteByte(radeon_output->DVOChip, 0x08, 0x30);
RADEONDVOWriteByte(radeon_output->DVOChip, 0x09, 0x00);
RADEONDVOWriteByte(radeon_output->DVOChip, 0x0a, 0x90);
RADEONDVOWriteByte(radeon_output->DVOChip, 0x0c, 0x89);
RADEONDVOWriteByte(radeon_output->DVOChip, 0x08, 0x3b);
break;
+#if 0
+ /* needs work see bug 10418 */
+ case RADEON_SIL_1178:
+ RADEONDVOWriteByte(radeon_output->DVOChip, 0x0f, 0x44);
+ RADEONDVOWriteByte(radeon_output->DVOChip, 0x0f, 0x4c);
+ RADEONDVOWriteByte(radeon_output->DVOChip, 0x0e, 0x01);
+ RADEONDVOWriteByte(radeon_output->DVOChip, 0x0a, 0x80);
+ RADEONDVOWriteByte(radeon_output->DVOChip, 0x09, 0x30);
+ RADEONDVOWriteByte(radeon_output->DVOChip, 0x0c, 0xc9);
+ RADEONDVOWriteByte(radeon_output->DVOChip, 0x0d, 0x70);
+ RADEONDVOWriteByte(radeon_output->DVOChip, 0x08, 0x32);
+ RADEONDVOWriteByte(radeon_output->DVOChip, 0x08, 0x33);
+ break;
+#endif
default:
break;
}
}
-#endif
}
}
@@ -623,11 +634,18 @@ void RADEONConnectorFindMonitor(ScrnInfoPtr pScrn, xf86OutputPtr output)
if (radeon_output->MonType == MT_UNKNOWN) {
if (radeon_output->type == OUTPUT_STV || radeon_output->type == OUTPUT_CTV) {
- if (info->InternalTVOut) {
- if (radeon_output->load_detection)
- radeon_output->MonType = radeon_detect_tv(pScrn);
+ if (xf86ReturnOptValBool(info->Options, OPTION_FORCE_TVOUT, FALSE)) {
+ if (radeon_output->type == OUTPUT_STV)
+ radeon_output->MonType = MT_STV;
else
- radeon_output->MonType = MT_NONE;
+ radeon_output->MonType = MT_CTV;
+ } else {
+ if (info->InternalTVOut) {
+ if (radeon_output->load_detection)
+ radeon_output->MonType = radeon_detect_tv(pScrn);
+ else
+ radeon_output->MonType = MT_NONE;
+ }
}
} else {
radeon_output->MonType = RADEONDisplayDDCConnected(pScrn, output);
@@ -666,6 +684,52 @@ void RADEONConnectorFindMonitor(ScrnInfoPtr pScrn, xf86OutputPtr output)
}
}
+#ifndef __powerpc__
+
+static RADEONMonitorType
+RADEONDetectLidStatus(ScrnInfoPtr pScrn)
+{
+ RADEONInfoPtr info = RADEONPTR(pScrn);
+ RADEONMonitorType MonType = MT_NONE;
+#ifdef __linux__
+ char lidline[50]; /* 50 should be sufficient for our purposes */
+ FILE *f = fopen ("/proc/acpi/button/lid/LID/state", "r");
+
+ if (f != NULL) {
+ while (fgets(lidline, sizeof lidline, f)) {
+ if (!strncmp(lidline, "state:", strlen ("state:"))) {
+ if (strstr(lidline, "open")) {
+ fclose(f);
+ ErrorF("proc lid open\n");
+ return MT_LCD;
+ }
+ else if (strstr(lidline, "closed")) {
+ fclose(f);
+ ErrorF("proc lid closed\n");
+ return MT_NONE;
+ }
+ }
+ }
+ fclose(f);
+ }
+#endif
+
+ if (!info->IsAtomBios) {
+ unsigned char *RADEONMMIO = info->MMIO;
+
+ /* see if the lid is closed -- only works at boot */
+ if (INREG(RADEON_BIOS_6_SCRATCH) & 0x10)
+ MonType = MT_NONE;
+ else
+ MonType = MT_LCD;
+ } else
+ MonType = MT_LCD;
+
+ return MonType;
+}
+
+#endif /* __powerpc__ */
+
static RADEONMonitorType RADEONPortCheckNonDDC(ScrnInfoPtr pScrn, xf86OutputPtr output)
{
RADEONOutputPrivatePtr radeon_output = output->driver_private;
@@ -673,21 +737,10 @@ static RADEONMonitorType RADEONPortCheckNonDDC(ScrnInfoPtr pScrn, xf86OutputPtr
if (radeon_output->type == OUTPUT_LVDS) {
#if defined(__powerpc__)
- /* not sure on ppc, OF? */
+ MonType = MT_LCD;
#else
- RADEONInfoPtr info = RADEONPTR(pScrn);
-
- if (!info->IsAtomBios) {
- unsigned char *RADEONMMIO = info->MMIO;
-
- /* see if the lid is closed -- only works at boot */
- if (INREG(RADEON_BIOS_6_SCRATCH) & 0x10)
- MonType = MT_NONE;
- else
- MonType = MT_LCD;
- } else
+ MonType = RADEONDetectLidStatus(pScrn);
#endif
- MonType = MT_LCD;
} /*else if (radeon_output->type == OUTPUT_DVI) {
if (radeon_output->TMDSType == TMDS_INT) {
if (INREG(RADEON_FP_GEN_CNTL) & RADEON_FP_DETECT_SENSE)
@@ -782,7 +835,7 @@ radeon_mode_fixup(xf86OutputPtr output, DisplayModePtr mode,
}
/* update timing for LVDS and DFP if RMX is active */
- if ((radeon_output->MonType == MT_LCD) || (radeon_output->Flags & RADEON_USE_RMX)) {
+ if (radeon_output->Flags & RADEON_USE_RMX) {
/* set to the panel's native mode */
adjusted_mode->HTotal = radeon_output->PanelXRes + radeon_output->HBlank;
adjusted_mode->HSyncStart = radeon_output->PanelXRes + radeon_output->HOverPlus;
@@ -937,7 +990,10 @@ static void RADEONInitLVDSRegisters(xf86OutputPtr output, RADEONSavePtr save,
save->lvds_gen_cntl = info->SavedReg.lvds_gen_cntl;
save->lvds_gen_cntl |= RADEON_LVDS_DISPLAY_DIS;
- save->lvds_gen_cntl &= ~(RADEON_LVDS_ON | RADEON_LVDS_BLON);
+ save->lvds_gen_cntl &= ~(RADEON_LVDS_ON |
+ RADEON_LVDS_BLON |
+ RADEON_LVDS_EN |
+ RADEON_LVDS_RST_FM);
if (IS_R300_VARIANT)
save->lvds_pll_cntl &= ~(R300_LVDS_SRC_SEL_MASK);
@@ -1039,11 +1095,12 @@ static void RADEONInitDACRegisters(xf86OutputPtr output, RADEONSavePtr save,
save->dac_macro_cntl = info->SavedReg.dac_macro_cntl;
}
-/* XXX: fix me */
static void
-RADEONInitTvDacCntl(ScrnInfoPtr pScrn, RADEONSavePtr save)
+RADEONInitTvDacCntl(xf86OutputPtr output, RADEONSavePtr save)
{
+ ScrnInfoPtr pScrn = output->scrn;
RADEONInfoPtr info = RADEONPTR(pScrn);
+ RADEONOutputPrivatePtr radeon_output = output->driver_private;
if (info->ChipFamily == CHIP_FAMILY_R420 ||
info->ChipFamily == CHIP_FAMILY_RV410) {
@@ -1064,10 +1121,11 @@ RADEONInitTvDacCntl(ScrnInfoPtr pScrn, RADEONSavePtr save)
RADEON_TV_DAC_GDACPD |
RADEON_TV_DAC_GDACPD);
}
- /* FIXME: doesn't make sense, this just replaces the previous value... */
+
save->tv_dac_cntl |= (RADEON_TV_DAC_NBLANK |
- RADEON_TV_DAC_NHOLD |
- RADEON_TV_DAC_STD_PS2);
+ RADEON_TV_DAC_NHOLD |
+ RADEON_TV_DAC_STD_PS2 |
+ radeon_output->tv_dac_adj);
}
@@ -1078,7 +1136,7 @@ static void RADEONInitDAC2Registers(xf86OutputPtr output, RADEONSavePtr save,
RADEONInfoPtr info = RADEONPTR(pScrn);
/*0x0028023;*/
- RADEONInitTvDacCntl(pScrn, save);
+ RADEONInitTvDacCntl(output, save);
if (IS_R300_VARIANT)
save->gpiopad_a = info->SavedReg.gpiopad_a | 1;
@@ -1670,10 +1728,16 @@ radeon_detect(xf86OutputPtr output)
/* default to unknown for flaky chips/connectors
* so we can get something on the screen
*/
- if (((radeon_output->type == OUTPUT_VGA || radeon_output->type == OUTPUT_DVI) &&
- radeon_output->DACType == DAC_TVDAC) ||
- (info->IsIGP && radeon_output->type == OUTPUT_DVI))
+ if ((radeon_output->type == OUTPUT_VGA || radeon_output->type == OUTPUT_DVI) &&
+ (radeon_output->DACType == DAC_TVDAC) &&
+ (info->ChipFamily == CHIP_FAMILY_RS400)) {
+ radeon_output->MonType = MT_CRT;
+ return XF86OutputStatusUnknown;
+ } else if ((info->ChipFamily == CHIP_FAMILY_RS400) &&
+ radeon_output->type == OUTPUT_DVI) {
+ radeon_output->MonType = MT_DFP; /* MT_LCD ??? */
return XF86OutputStatusUnknown;
+ }
}
if (connected)
@@ -1740,6 +1804,7 @@ radeon_create_resources(xf86OutputPtr output)
INT32 range[2];
int data, err;
const char *s;
+ char *optstr;
/* backlight control */
if (radeon_output->type == OUTPUT_LVDS) {
@@ -1975,6 +2040,26 @@ radeon_create_resources(xf86OutputPtr output)
s = "ntsc";
break;
}
+
+ optstr = (char *)xf86GetOptValString(info->Options, OPTION_TVSTD);
+ if (optstr) {
+ if (!strncmp("ntsc", optstr, strlen("ntsc")))
+ radeon_output->tvStd = TV_STD_NTSC;
+ else if (!strncmp("pal", optstr, strlen("pal")))
+ radeon_output->tvStd = TV_STD_PAL;
+ else if (!strncmp("pal-m", optstr, strlen("pal-m")))
+ radeon_output->tvStd = TV_STD_PAL_M;
+ else if (!strncmp("pal-60", optstr, strlen("pal-60")))
+ radeon_output->tvStd = TV_STD_PAL_60;
+ else if (!strncmp("ntsc-j", optstr, strlen("ntsc-j")))
+ radeon_output->tvStd = TV_STD_NTSC_J;
+ else if (!strncmp("scart-pal", optstr, strlen("scart-pal")))
+ radeon_output->tvStd = TV_STD_SCART_PAL;
+ else {
+ xf86DrvMsg(pScrn->scrnIndex, X_ERROR, "Invalid TV Standard: %s\n", optstr);
+ }
+ }
+
err = RRChangeOutputProperty(output->randr_output, tv_std_atom,
XA_STRING, 8, PropModeReplace, strlen(s), (pointer)s,
FALSE, FALSE);
@@ -2623,6 +2708,7 @@ void RADEONInitConnector(xf86OutputPtr output)
if (radeon_output->type == OUTPUT_STV ||
radeon_output->type == OUTPUT_CTV) {
RADEONGetTVInfo(output);
+ RADEONGetTVDacAdjInfo(output);
}
if (radeon_output->DACType == DAC_TVDAC) {
@@ -2658,7 +2744,7 @@ static Bool RADEONSetupAppleConnectors(ScrnInfoPtr pScrn)
info->BiosConnector[2].DDCType = DDC_NONE_DETECTED;
info->BiosConnector[2].valid = TRUE;
return TRUE;
- case RADEON_MAC_POWERBOOK_DL:
+ case RADEON_MAC_POWERBOOK_EXTERNAL:
info->BiosConnector[0].DDCType = DDC_DVI;
info->BiosConnector[0].DACType = DAC_NONE;
info->BiosConnector[0].TMDSType = TMDS_NONE;
@@ -2677,7 +2763,7 @@ static Bool RADEONSetupAppleConnectors(ScrnInfoPtr pScrn)
info->BiosConnector[2].DDCType = DDC_NONE_DETECTED;
info->BiosConnector[2].valid = TRUE;
return TRUE;
- case RADEON_MAC_POWERBOOK:
+ case RADEON_MAC_POWERBOOK_INTERNAL:
info->BiosConnector[0].DDCType = DDC_DVI;
info->BiosConnector[0].DACType = DAC_NONE;
info->BiosConnector[0].TMDSType = TMDS_NONE;
@@ -2696,7 +2782,26 @@ static Bool RADEONSetupAppleConnectors(ScrnInfoPtr pScrn)
info->BiosConnector[2].DDCType = DDC_NONE_DETECTED;
info->BiosConnector[2].valid = TRUE;
return TRUE;
- case RADEON_MAC_MINI:
+ case RADEON_MAC_POWERBOOK_VGA:
+ info->BiosConnector[0].DDCType = DDC_DVI;
+ info->BiosConnector[0].DACType = DAC_NONE;
+ info->BiosConnector[0].TMDSType = TMDS_NONE;
+ info->BiosConnector[0].ConnectorType = CONNECTOR_CRT;
+ info->BiosConnector[0].valid = TRUE;
+
+ info->BiosConnector[1].DDCType = DDC_VGA;
+ info->BiosConnector[1].DACType = DAC_PRIMARY;
+ info->BiosConnector[1].TMDSType = TMDS_INT;
+ info->BiosConnector[1].ConnectorType = CONNECTOR_DVI_I;
+ info->BiosConnector[1].valid = TRUE;
+
+ info->BiosConnector[2].ConnectorType = CONNECTOR_STV;
+ info->BiosConnector[2].DACType = DAC_TVDAC;
+ info->BiosConnector[2].TMDSType = TMDS_NONE;
+ info->BiosConnector[2].DDCType = DDC_NONE_DETECTED;
+ info->BiosConnector[2].valid = TRUE;
+ return TRUE;
+ case RADEON_MAC_MINI_EXTERNAL:
info->BiosConnector[0].DDCType = DDC_CRT2;
info->BiosConnector[0].DACType = DAC_TVDAC;
info->BiosConnector[0].TMDSType = TMDS_EXT;
@@ -2709,6 +2814,38 @@ static Bool RADEONSetupAppleConnectors(ScrnInfoPtr pScrn)
info->BiosConnector[1].DDCType = DDC_NONE_DETECTED;
info->BiosConnector[1].valid = TRUE;
return TRUE;
+ case RADEON_MAC_MINI_INTERNAL:
+ info->BiosConnector[0].DDCType = DDC_CRT2;
+ info->BiosConnector[0].DACType = DAC_TVDAC;
+ info->BiosConnector[0].TMDSType = TMDS_INT;
+ info->BiosConnector[0].ConnectorType = CONNECTOR_DVI_I;
+ info->BiosConnector[0].valid = TRUE;
+
+ info->BiosConnector[1].ConnectorType = CONNECTOR_STV;
+ info->BiosConnector[1].DACType = DAC_TVDAC;
+ info->BiosConnector[1].TMDSType = TMDS_NONE;
+ info->BiosConnector[1].DDCType = DDC_NONE_DETECTED;
+ info->BiosConnector[1].valid = TRUE;
+ return TRUE;
+ case RADEON_MAC_IMAC_G5_ISIGHT:
+ info->BiosConnector[0].DDCType = DDC_MONID;
+ info->BiosConnector[0].DACType = DAC_NONE;
+ info->BiosConnector[0].TMDSType = TMDS_INT;
+ info->BiosConnector[0].ConnectorType = CONNECTOR_DVI_D;
+ info->BiosConnector[0].valid = TRUE;
+
+ info->BiosConnector[1].DDCType = DDC_DVI;
+ info->BiosConnector[1].DACType = DAC_TVDAC;
+ info->BiosConnector[1].TMDSType = TMDS_NONE;
+ info->BiosConnector[1].ConnectorType = CONNECTOR_CRT;
+ info->BiosConnector[1].valid = TRUE;
+
+ info->BiosConnector[2].ConnectorType = CONNECTOR_STV;
+ info->BiosConnector[2].DACType = DAC_TVDAC;
+ info->BiosConnector[2].TMDSType = TMDS_NONE;
+ info->BiosConnector[2].DDCType = DDC_NONE_DETECTED;
+ info->BiosConnector[2].valid = TRUE;
+ return TRUE;
default:
return FALSE;
}
@@ -2793,11 +2930,19 @@ static void RADEONSetupGenericConnectors(ScrnInfoPtr pScrn)
info->BiosConnector[0].ConnectorType = CONNECTOR_DVI_I;
info->BiosConnector[0].valid = TRUE;
+#if defined(__powerpc__)
info->BiosConnector[1].DDCType = DDC_VGA;
info->BiosConnector[1].DACType = DAC_PRIMARY;
info->BiosConnector[1].TMDSType = TMDS_EXT;
+ info->BiosConnector[1].ConnectorType = CONNECTOR_DVI_I;
+ info->BiosConnector[1].valid = TRUE;
+#else
+ info->BiosConnector[1].DDCType = DDC_VGA;
+ info->BiosConnector[1].DACType = DAC_PRIMARY;
+ info->BiosConnector[1].TMDSType = TMDS_NONE;
info->BiosConnector[1].ConnectorType = CONNECTOR_CRT;
info->BiosConnector[1].valid = TRUE;
+#endif
}
}
@@ -2826,40 +2971,81 @@ static void RADEONSetupGenericConnectors(ScrnInfoPtr pScrn)
* in /proc/cpuinfo (on Linux) */
static RADEONMacModel RADEONDetectMacModel(ScrnInfoPtr pScrn)
{
+ RADEONInfoPtr info = RADEONPTR(pScrn);
RADEONMacModel ret = 0;
#ifdef __linux__
char cpuline[50]; /* 50 should be sufficient for our purposes */
FILE *f = fopen ("/proc/cpuinfo", "r");
+ /* Some macs (minis and powerbooks) use internal tmds, others use external tmds
+ * and not just for dual-link TMDS, it shows up with single-link as well.
+ * Unforunately, there doesn't seem to be any good way to figure it out.
+ */
+
+ /*
+ * PowerBook5,[1-5]: external tmds, single-link
+ * PowerBook5,[789]: external tmds, dual-link
+ * PowerBook5,6: external tmds, single-link or dual-link
+ * need to add another option to specify the external tmds chip
+ * or find out what's used and add it.
+ */
+
+
if (f != NULL) {
while (fgets(cpuline, sizeof cpuline, f)) {
if (!strncmp(cpuline, "machine", strlen ("machine"))) {
- if (strstr(cpuline, "PowerBook5,6") ||
- strstr(cpuline, "PowerBook5,7") ||
+ if (strstr(cpuline, "PowerBook5,1") ||
+ strstr(cpuline, "PowerBook5,2") ||
+ strstr(cpuline, "PowerBook5,3") ||
+ strstr(cpuline, "PowerBook5,4") ||
+ strstr(cpuline, "PowerBook5,5")) {
+ ret = RADEON_MAC_POWERBOOK_EXTERNAL; /* single link */
+ info->ext_tmds_chip = RADEON_SIL_164; /* works on 5,2 */
+ break;
+ }
+
+ if (strstr(cpuline, "PowerBook5,6")) {
+ ret = RADEON_MAC_POWERBOOK_EXTERNAL; /* dual or single link */
+ break;
+ }
+
+ if (strstr(cpuline, "PowerBook5,7") ||
strstr(cpuline, "PowerBook5,8") ||
strstr(cpuline, "PowerBook5,9")) {
- ret = RADEON_MAC_POWERBOOK_DL;
+ ret = RADEON_MAC_POWERBOOK_EXTERNAL; /* dual link */
+ info->ext_tmds_chip = RADEON_SIL_1178; /* guess */
+ break;
+ }
+
+ if (strstr(cpuline, "PowerBook3,3")) {
+ ret = RADEON_MAC_POWERBOOK_VGA; /* vga rather than dvi */
break;
}
- if (strstr(cpuline, "PowerMac10,1") ||
- strstr(cpuline, "PowerMac10,2")) {
- ret = RADEON_MAC_MINI;
+ if (strstr(cpuline, "PowerMac10,1")) {
+ ret = RADEON_MAC_MINI_INTERNAL; /* internal tmds */
+ break;
+ }
+ if (strstr(cpuline, "PowerMac10,2")) {
+ ret = RADEON_MAC_MINI_EXTERNAL; /* external tmds */
break;
}
} else if (!strncmp(cpuline, "detected as", strlen("detected as"))) {
- if (strstr(cpuline, "iBook")) {
- ret = RADEON_MAC_IBOOK;
+ if (strstr(cpuline, "iBook")) {
+ ret = RADEON_MAC_IBOOK;
break;
} else if (strstr(cpuline, "PowerBook")) {
- ret = RADEON_MAC_POWERBOOK_DL;
+ ret = RADEON_MAC_POWERBOOK_INTERNAL; /* internal tmds */
break;
- }
+ } else if (strstr(cpuline, "iMac G5 (iSight)")) {
+ ret = RADEON_MAC_IMAC_G5_ISIGHT;
+ break;
+ }
- /* No known PowerMac model detected */
- break;
- }
- }
+ /* No known PowerMac model detected */
+ break;
+ }
+ }
fclose (f);
} else
@@ -2871,10 +3057,13 @@ static RADEONMacModel RADEONDetectMacModel(ScrnInfoPtr pScrn)
if (ret) {
xf86DrvMsg(pScrn->scrnIndex, X_DEFAULT, "Detected %s.\n",
- ret == RADEON_MAC_POWERBOOK_DL ? "PowerBook with dual link DVI" :
- ret == RADEON_MAC_POWERBOOK ? "PowerBook with single link DVI" :
+ ret == RADEON_MAC_POWERBOOK_EXTERNAL ? "PowerBook with external DVI" :
+ ret == RADEON_MAC_POWERBOOK_INTERNAL ? "PowerBook with integrated DVI" :
+ ret == RADEON_MAC_POWERBOOK_VGA ? "PowerBook with VGA" :
ret == RADEON_MAC_IBOOK ? "iBook" :
- "Mac Mini");
+ ret == RADEON_MAC_MINI_EXTERNAL ? "Mac Mini with external DVI" :
+ ret == RADEON_MAC_MINI_INTERNAL ? "Mac Mini with integrated DVI" :
+ "iMac G5 iSight");
xf86DrvMsg(pScrn->scrnIndex, X_INFO,
"If this is not correct, try Option \"MacModel\" and "
"consider reporting to the\n");
@@ -2921,12 +3110,24 @@ Bool RADEONSetupConnectors(ScrnInfoPtr pScrn)
if (optstr) {
if (!strncmp("ibook", optstr, strlen("ibook")))
info->MacModel = RADEON_MAC_IBOOK;
- else if (!strncmp("powerbook-duallink", optstr, strlen("powerbook-duallink")))
- info->MacModel = RADEON_MAC_POWERBOOK_DL;
- else if (!strncmp("powerbook", optstr, strlen("powerbook")))
- info->MacModel = RADEON_MAC_POWERBOOK;
- else if (!strncmp("mini", optstr, strlen("mini")))
- info->MacModel = RADEON_MAC_MINI;
+ else if (!strncmp("powerbook-duallink", optstr, strlen("powerbook-duallink"))) /* alias */
+ info->MacModel = RADEON_MAC_POWERBOOK_EXTERNAL;
+ else if (!strncmp("powerbook-external", optstr, strlen("powerbook-external")))
+ info->MacModel = RADEON_MAC_POWERBOOK_EXTERNAL;
+ else if (!strncmp("powerbook-internal", optstr, strlen("powerbook-internal")))
+ info->MacModel = RADEON_MAC_POWERBOOK_INTERNAL;
+ else if (!strncmp("powerbook-vga", optstr, strlen("powerbook-vga")))
+ info->MacModel = RADEON_MAC_POWERBOOK_VGA;
+ else if (!strncmp("powerbook", optstr, strlen("powerbook"))) /* alias */
+ info->MacModel = RADEON_MAC_POWERBOOK_INTERNAL;
+ else if (!strncmp("mini-internal", optstr, strlen("mini-internal")))
+ info->MacModel = RADEON_MAC_MINI_INTERNAL;
+ else if (!strncmp("mini-external", optstr, strlen("mini-external")))
+ info->MacModel = RADEON_MAC_MINI_EXTERNAL;
+ else if (!strncmp("mini", optstr, strlen("mini"))) /* alias */
+ info->MacModel = RADEON_MAC_MINI_EXTERNAL;
+ else if (!strncmp("imac-g5-isight", optstr, strlen("imac-g5-isight")))
+ info->MacModel = RADEON_MAC_IMAC_G5_ISIGHT;
else {
xf86DrvMsg(pScrn->scrnIndex, X_ERROR, "Invalid Mac Model: %s\n", optstr);
}
@@ -3009,6 +3210,14 @@ Bool RADEONSetupConnectors(ScrnInfoPtr pScrn)
}
}
+ /* clear the enable masks */
+ info->output_crt1 = 0;
+ info->output_crt2 = 0;
+ info->output_dfp1 = 0;
+ info->output_dfp2 = 0;
+ info->output_lcd1 = 0;
+ info->output_tv1 = 0;
+
for (i = 0 ; i < RADEON_MAX_BIOS_CONNECTOR; i++) {
if (info->BiosConnector[i].valid) {
RADEONOutputPrivatePtr radeon_output = xnfcalloc(sizeof(RADEONOutputPrivateRec), 1);
diff --git a/src/radeon_pci_chipset_gen.h b/src/radeon_pci_chipset_gen.h
new file mode 100644
index 0000000..7a36242
--- /dev/null
+++ b/src/radeon_pci_chipset_gen.h
@@ -0,0 +1,141 @@
+/* This file is autogenerated please do not edit */
+PciChipsets RADEONPciChipsets[] = {
+ { PCI_CHIP_RV380_3150, PCI_CHIP_RV380_3150, RES_SHARED_VGA },
+ { PCI_CHIP_RV380_3152, PCI_CHIP_RV380_3152, RES_SHARED_VGA },
+ { PCI_CHIP_RV380_3154, PCI_CHIP_RV380_3154, RES_SHARED_VGA },
+ { PCI_CHIP_RV380_3E50, PCI_CHIP_RV380_3E50, RES_SHARED_VGA },
+ { PCI_CHIP_RV380_3E54, PCI_CHIP_RV380_3E54, RES_SHARED_VGA },
+ { PCI_CHIP_RS100_4136, PCI_CHIP_RS100_4136, RES_SHARED_VGA },
+ { PCI_CHIP_RS200_4137, PCI_CHIP_RS200_4137, RES_SHARED_VGA },
+ { PCI_CHIP_R300_AD, PCI_CHIP_R300_AD, RES_SHARED_VGA },
+ { PCI_CHIP_R300_AE, PCI_CHIP_R300_AE, RES_SHARED_VGA },
+ { PCI_CHIP_R300_AF, PCI_CHIP_R300_AF, RES_SHARED_VGA },
+ { PCI_CHIP_R300_AG, PCI_CHIP_R300_AG, RES_SHARED_VGA },
+ { PCI_CHIP_R350_AH, PCI_CHIP_R350_AH, RES_SHARED_VGA },
+ { PCI_CHIP_R350_AI, PCI_CHIP_R350_AI, RES_SHARED_VGA },
+ { PCI_CHIP_R350_AJ, PCI_CHIP_R350_AJ, RES_SHARED_VGA },
+ { PCI_CHIP_R350_AK, PCI_CHIP_R350_AK, RES_SHARED_VGA },
+ { PCI_CHIP_RV350_AP, PCI_CHIP_RV350_AP, RES_SHARED_VGA },
+ { PCI_CHIP_RV350_AQ, PCI_CHIP_RV350_AQ, RES_SHARED_VGA },
+ { PCI_CHIP_RV360_AR, PCI_CHIP_RV360_AR, RES_SHARED_VGA },
+ { PCI_CHIP_RV350_AS, PCI_CHIP_RV350_AS, RES_SHARED_VGA },
+ { PCI_CHIP_RV350_AT, PCI_CHIP_RV350_AT, RES_SHARED_VGA },
+ { PCI_CHIP_RV350_4155, PCI_CHIP_RV350_4155, RES_SHARED_VGA },
+ { PCI_CHIP_RV350_AV, PCI_CHIP_RV350_AV, RES_SHARED_VGA },
+ { PCI_CHIP_RS250_4237, PCI_CHIP_RS250_4237, RES_SHARED_VGA },
+ { PCI_CHIP_R200_BB, PCI_CHIP_R200_BB, RES_SHARED_VGA },
+ { PCI_CHIP_R200_BC, PCI_CHIP_R200_BC, RES_SHARED_VGA },
+ { PCI_CHIP_RS100_4336, PCI_CHIP_RS100_4336, RES_SHARED_VGA },
+ { PCI_CHIP_RS200_4337, PCI_CHIP_RS200_4337, RES_SHARED_VGA },
+ { PCI_CHIP_RS250_4437, PCI_CHIP_RS250_4437, RES_SHARED_VGA },
+ { PCI_CHIP_RV250_If, PCI_CHIP_RV250_If, RES_SHARED_VGA },
+ { PCI_CHIP_RV250_Ig, PCI_CHIP_RV250_Ig, RES_SHARED_VGA },
+ { PCI_CHIP_R420_JH, PCI_CHIP_R420_JH, RES_SHARED_VGA },
+ { PCI_CHIP_R420_JI, PCI_CHIP_R420_JI, RES_SHARED_VGA },
+ { PCI_CHIP_R420_JJ, PCI_CHIP_R420_JJ, RES_SHARED_VGA },
+ { PCI_CHIP_R420_JK, PCI_CHIP_R420_JK, RES_SHARED_VGA },
+ { PCI_CHIP_R420_JL, PCI_CHIP_R420_JL, RES_SHARED_VGA },
+ { PCI_CHIP_R420_JM, PCI_CHIP_R420_JM, RES_SHARED_VGA },
+ { PCI_CHIP_R420_JN, PCI_CHIP_R420_JN, RES_SHARED_VGA },
+ { PCI_CHIP_R420_4A4F, PCI_CHIP_R420_4A4F, RES_SHARED_VGA },
+ { PCI_CHIP_R420_JP, PCI_CHIP_R420_JP, RES_SHARED_VGA },
+ { PCI_CHIP_R481_4B49, PCI_CHIP_R481_4B49, RES_SHARED_VGA },
+ { PCI_CHIP_R481_4B4A, PCI_CHIP_R481_4B4A, RES_SHARED_VGA },
+ { PCI_CHIP_R481_4B4B, PCI_CHIP_R481_4B4B, RES_SHARED_VGA },
+ { PCI_CHIP_R481_4B4C, PCI_CHIP_R481_4B4C, RES_SHARED_VGA },
+ { PCI_CHIP_RADEON_LW, PCI_CHIP_RADEON_LW, RES_SHARED_VGA },
+ { PCI_CHIP_RADEON_LX, PCI_CHIP_RADEON_LX, RES_SHARED_VGA },
+ { PCI_CHIP_RADEON_LY, PCI_CHIP_RADEON_LY, RES_SHARED_VGA },
+ { PCI_CHIP_RADEON_LZ, PCI_CHIP_RADEON_LZ, RES_SHARED_VGA },
+ { PCI_CHIP_RV250_Ld, PCI_CHIP_RV250_Ld, RES_SHARED_VGA },
+ { PCI_CHIP_RV250_Lf, PCI_CHIP_RV250_Lf, RES_SHARED_VGA },
+ { PCI_CHIP_RV250_Lg, PCI_CHIP_RV250_Lg, RES_SHARED_VGA },
+ { PCI_CHIP_R300_ND, PCI_CHIP_R300_ND, RES_SHARED_VGA },
+ { PCI_CHIP_R300_NE, PCI_CHIP_R300_NE, RES_SHARED_VGA },
+ { PCI_CHIP_R300_NF, PCI_CHIP_R300_NF, RES_SHARED_VGA },
+ { PCI_CHIP_R300_NG, PCI_CHIP_R300_NG, RES_SHARED_VGA },
+ { PCI_CHIP_R350_NH, PCI_CHIP_R350_NH, RES_SHARED_VGA },
+ { PCI_CHIP_R350_NI, PCI_CHIP_R350_NI, RES_SHARED_VGA },
+ { PCI_CHIP_R360_NJ, PCI_CHIP_R360_NJ, RES_SHARED_VGA },
+ { PCI_CHIP_R350_NK, PCI_CHIP_R350_NK, RES_SHARED_VGA },
+ { PCI_CHIP_RV350_NP, PCI_CHIP_RV350_NP, RES_SHARED_VGA },
+ { PCI_CHIP_RV350_NQ, PCI_CHIP_RV350_NQ, RES_SHARED_VGA },
+ { PCI_CHIP_RV350_NR, PCI_CHIP_RV350_NR, RES_SHARED_VGA },
+ { PCI_CHIP_RV350_NS, PCI_CHIP_RV350_NS, RES_SHARED_VGA },
+ { PCI_CHIP_RV350_NT, PCI_CHIP_RV350_NT, RES_SHARED_VGA },
+ { PCI_CHIP_RV350_NV, PCI_CHIP_RV350_NV, RES_SHARED_VGA },
+ { PCI_CHIP_RADEON_QD, PCI_CHIP_RADEON_QD, RES_SHARED_VGA },
+ { PCI_CHIP_RADEON_QE, PCI_CHIP_RADEON_QE, RES_SHARED_VGA },
+ { PCI_CHIP_RADEON_QF, PCI_CHIP_RADEON_QF, RES_SHARED_VGA },
+ { PCI_CHIP_RADEON_QG, PCI_CHIP_RADEON_QG, RES_SHARED_VGA },
+ { PCI_CHIP_R200_QH, PCI_CHIP_R200_QH, RES_SHARED_VGA },
+ { PCI_CHIP_R200_QL, PCI_CHIP_R200_QL, RES_SHARED_VGA },
+ { PCI_CHIP_R200_QM, PCI_CHIP_R200_QM, RES_SHARED_VGA },
+ { PCI_CHIP_RV200_QW, PCI_CHIP_RV200_QW, RES_SHARED_VGA },
+ { PCI_CHIP_RV200_QX, PCI_CHIP_RV200_QX, RES_SHARED_VGA },
+ { PCI_CHIP_RV100_QY, PCI_CHIP_RV100_QY, RES_SHARED_VGA },
+ { PCI_CHIP_RV100_QZ, PCI_CHIP_RV100_QZ, RES_SHARED_VGA },
+ { PCI_CHIP_RN50_515E, PCI_CHIP_RN50_515E, RES_SHARED_VGA },
+ { PCI_CHIP_RV370_5460, PCI_CHIP_RV370_5460, RES_SHARED_VGA },
+ { PCI_CHIP_RV370_5462, PCI_CHIP_RV370_5462, RES_SHARED_VGA },
+ { PCI_CHIP_RV370_5464, PCI_CHIP_RV370_5464, RES_SHARED_VGA },
+ { PCI_CHIP_R423_UH, PCI_CHIP_R423_UH, RES_SHARED_VGA },
+ { PCI_CHIP_R423_UI, PCI_CHIP_R423_UI, RES_SHARED_VGA },
+ { PCI_CHIP_R423_UJ, PCI_CHIP_R423_UJ, RES_SHARED_VGA },
+ { PCI_CHIP_R423_UK, PCI_CHIP_R423_UK, RES_SHARED_VGA },
+ { PCI_CHIP_R430_554C, PCI_CHIP_R430_554C, RES_SHARED_VGA },
+ { PCI_CHIP_R430_554D, PCI_CHIP_R430_554D, RES_SHARED_VGA },
+ { PCI_CHIP_R430_554E, PCI_CHIP_R430_554E, RES_SHARED_VGA },
+ { PCI_CHIP_R430_554F, PCI_CHIP_R430_554F, RES_SHARED_VGA },
+ { PCI_CHIP_R423_5550, PCI_CHIP_R423_5550, RES_SHARED_VGA },
+ { PCI_CHIP_R423_UQ, PCI_CHIP_R423_UQ, RES_SHARED_VGA },
+ { PCI_CHIP_R423_UR, PCI_CHIP_R423_UR, RES_SHARED_VGA },
+ { PCI_CHIP_R423_UT, PCI_CHIP_R423_UT, RES_SHARED_VGA },
+ { PCI_CHIP_RV410_564A, PCI_CHIP_RV410_564A, RES_SHARED_VGA },
+ { PCI_CHIP_RV410_564B, PCI_CHIP_RV410_564B, RES_SHARED_VGA },
+ { PCI_CHIP_RV410_564F, PCI_CHIP_RV410_564F, RES_SHARED_VGA },
+ { PCI_CHIP_RV410_5652, PCI_CHIP_RV410_5652, RES_SHARED_VGA },
+ { PCI_CHIP_RV410_5653, PCI_CHIP_RV410_5653, RES_SHARED_VGA },
+ { PCI_CHIP_RS300_5834, PCI_CHIP_RS300_5834, RES_SHARED_VGA },
+ { PCI_CHIP_RS300_5835, PCI_CHIP_RS300_5835, RES_SHARED_VGA },
+ { PCI_CHIP_RS480_5954, PCI_CHIP_RS480_5954, RES_SHARED_VGA },
+ { PCI_CHIP_RS480_5955, PCI_CHIP_RS480_5955, RES_SHARED_VGA },
+ { PCI_CHIP_RV280_5960, PCI_CHIP_RV280_5960, RES_SHARED_VGA },
+ { PCI_CHIP_RV280_5961, PCI_CHIP_RV280_5961, RES_SHARED_VGA },
+ { PCI_CHIP_RV280_5962, PCI_CHIP_RV280_5962, RES_SHARED_VGA },
+ { PCI_CHIP_RV280_5964, PCI_CHIP_RV280_5964, RES_SHARED_VGA },
+ { PCI_CHIP_RV280_5965, PCI_CHIP_RV280_5965, RES_SHARED_VGA },
+ { PCI_CHIP_RN50_5969, PCI_CHIP_RN50_5969, RES_SHARED_VGA },
+ { PCI_CHIP_RS482_5974, PCI_CHIP_RS482_5974, RES_SHARED_VGA },
+ { PCI_CHIP_RS485_5975, PCI_CHIP_RS485_5975, RES_SHARED_VGA },
+ { PCI_CHIP_RS400_5A41, PCI_CHIP_RS400_5A41, RES_SHARED_VGA },
+ { PCI_CHIP_RS400_5A42, PCI_CHIP_RS400_5A42, RES_SHARED_VGA },
+ { PCI_CHIP_RC410_5A61, PCI_CHIP_RC410_5A61, RES_SHARED_VGA },
+ { PCI_CHIP_RC410_5A62, PCI_CHIP_RC410_5A62, RES_SHARED_VGA },
+ { PCI_CHIP_RV370_5B60, PCI_CHIP_RV370_5B60, RES_SHARED_VGA },
+ { PCI_CHIP_RV370_5B62, PCI_CHIP_RV370_5B62, RES_SHARED_VGA },
+ { PCI_CHIP_RV370_5B63, PCI_CHIP_RV370_5B63, RES_SHARED_VGA },
+ { PCI_CHIP_RV370_5B64, PCI_CHIP_RV370_5B64, RES_SHARED_VGA },
+ { PCI_CHIP_RV370_5B65, PCI_CHIP_RV370_5B65, RES_SHARED_VGA },
+ { PCI_CHIP_RV280_5C61, PCI_CHIP_RV280_5C61, RES_SHARED_VGA },
+ { PCI_CHIP_RV280_5C63, PCI_CHIP_RV280_5C63, RES_SHARED_VGA },
+ { PCI_CHIP_R430_5D48, PCI_CHIP_R430_5D48, RES_SHARED_VGA },
+ { PCI_CHIP_R430_5D49, PCI_CHIP_R430_5D49, RES_SHARED_VGA },
+ { PCI_CHIP_R430_5D4A, PCI_CHIP_R430_5D4A, RES_SHARED_VGA },
+ { PCI_CHIP_R480_5D4C, PCI_CHIP_R480_5D4C, RES_SHARED_VGA },
+ { PCI_CHIP_R480_5D4D, PCI_CHIP_R480_5D4D, RES_SHARED_VGA },
+ { PCI_CHIP_R480_5D4E, PCI_CHIP_R480_5D4E, RES_SHARED_VGA },
+ { PCI_CHIP_R480_5D4F, PCI_CHIP_R480_5D4F, RES_SHARED_VGA },
+ { PCI_CHIP_R480_5D50, PCI_CHIP_R480_5D50, RES_SHARED_VGA },
+ { PCI_CHIP_R480_5D52, PCI_CHIP_R480_5D52, RES_SHARED_VGA },
+ { PCI_CHIP_R423_5D57, PCI_CHIP_R423_5D57, RES_SHARED_VGA },
+ { PCI_CHIP_RV410_5E48, PCI_CHIP_RV410_5E48, RES_SHARED_VGA },
+ { PCI_CHIP_RV410_5E4A, PCI_CHIP_RV410_5E4A, RES_SHARED_VGA },
+ { PCI_CHIP_RV410_5E4B, PCI_CHIP_RV410_5E4B, RES_SHARED_VGA },
+ { PCI_CHIP_RV410_5E4C, PCI_CHIP_RV410_5E4C, RES_SHARED_VGA },
+ { PCI_CHIP_RV410_5E4D, PCI_CHIP_RV410_5E4D, RES_SHARED_VGA },
+ { PCI_CHIP_RV410_5E4F, PCI_CHIP_RV410_5E4F, RES_SHARED_VGA },
+ { PCI_CHIP_RS350_7834, PCI_CHIP_RS350_7834, RES_SHARED_VGA },
+ { PCI_CHIP_RS350_7835, PCI_CHIP_RS350_7835, RES_SHARED_VGA },
+ { -1, -1, RES_UNDEFINED }
+};
diff --git a/src/radeon_probe.c b/src/radeon_probe.c
index d68a956..baea47c 100644
--- a/src/radeon_probe.c
+++ b/src/radeon_probe.c
@@ -51,150 +51,9 @@
#include <X11/extensions/xf86misc.h>
#include "xf86Resources.h"
-#include "radeon_chipset.h"
+#include "radeon_chipset_gen.h"
-PciChipsets RADEONPciChipsets[] = {
- { PCI_CHIP_RADEON_QD, PCI_CHIP_RADEON_QD, RES_SHARED_VGA },
- { PCI_CHIP_RADEON_QE, PCI_CHIP_RADEON_QE, RES_SHARED_VGA },
- { PCI_CHIP_RADEON_QF, PCI_CHIP_RADEON_QF, RES_SHARED_VGA },
- { PCI_CHIP_RADEON_QG, PCI_CHIP_RADEON_QG, RES_SHARED_VGA },
- { PCI_CHIP_RV100_QY, PCI_CHIP_RV100_QY, RES_SHARED_VGA },
- { PCI_CHIP_RV100_QZ, PCI_CHIP_RV100_QZ, RES_SHARED_VGA },
- { PCI_CHIP_RN50_515E, PCI_CHIP_RN50_515E, RES_SHARED_VGA },
- { PCI_CHIP_RN50_5969, PCI_CHIP_RN50_5969, RES_SHARED_VGA },
- { PCI_CHIP_RADEON_LW, PCI_CHIP_RADEON_LW, RES_SHARED_VGA },
- { PCI_CHIP_RADEON_LX, PCI_CHIP_RADEON_LX, RES_SHARED_VGA },
- { PCI_CHIP_RADEON_LY, PCI_CHIP_RADEON_LY, RES_SHARED_VGA },
- { PCI_CHIP_RADEON_LZ, PCI_CHIP_RADEON_LZ, RES_SHARED_VGA },
- { PCI_CHIP_RS100_4136, PCI_CHIP_RS100_4136, RES_SHARED_VGA },
- { PCI_CHIP_RS100_4336, PCI_CHIP_RS100_4336, RES_SHARED_VGA },
- { PCI_CHIP_RS200_4137, PCI_CHIP_RS200_4137, RES_SHARED_VGA },
- { PCI_CHIP_RS200_4337, PCI_CHIP_RS200_4337, RES_SHARED_VGA },
- { PCI_CHIP_RS250_4237, PCI_CHIP_RS250_4237, RES_SHARED_VGA },
- { PCI_CHIP_RS250_4437, PCI_CHIP_RS250_4437, RES_SHARED_VGA },
- { PCI_CHIP_R200_QH, PCI_CHIP_R200_QH, RES_SHARED_VGA },
- { PCI_CHIP_R200_QL, PCI_CHIP_R200_QL, RES_SHARED_VGA },
- { PCI_CHIP_R200_QM, PCI_CHIP_R200_QM, RES_SHARED_VGA },
- { PCI_CHIP_R200_BB, PCI_CHIP_R200_BB, RES_SHARED_VGA },
- { PCI_CHIP_R200_BC, PCI_CHIP_R200_BC, RES_SHARED_VGA },
- { PCI_CHIP_RV200_QW, PCI_CHIP_RV200_QW, RES_SHARED_VGA },
- { PCI_CHIP_RV200_QX, PCI_CHIP_RV200_QX, RES_SHARED_VGA },
- { PCI_CHIP_RV250_If, PCI_CHIP_RV250_If, RES_SHARED_VGA },
- { PCI_CHIP_RV250_Ig, PCI_CHIP_RV250_Ig, RES_SHARED_VGA },
- { PCI_CHIP_RV250_Ld, PCI_CHIP_RV250_Ld, RES_SHARED_VGA },
- { PCI_CHIP_RV250_Lf, PCI_CHIP_RV250_Lf, RES_SHARED_VGA },
- { PCI_CHIP_RV250_Lg, PCI_CHIP_RV250_Lg, RES_SHARED_VGA },
- { PCI_CHIP_RS300_5834, PCI_CHIP_RS300_5834, RES_SHARED_VGA },
- { PCI_CHIP_RS300_5835, PCI_CHIP_RS300_5835, RES_SHARED_VGA },
- { PCI_CHIP_RS350_7834, PCI_CHIP_RS350_7834, RES_SHARED_VGA },
- { PCI_CHIP_RS350_7835, PCI_CHIP_RS350_7835, RES_SHARED_VGA },
- { PCI_CHIP_RV280_5960, PCI_CHIP_RV280_5960, RES_SHARED_VGA },
- { PCI_CHIP_RV280_5961, PCI_CHIP_RV280_5961, RES_SHARED_VGA },
- { PCI_CHIP_RV280_5962, PCI_CHIP_RV280_5962, RES_SHARED_VGA },
- { PCI_CHIP_RV280_5964, PCI_CHIP_RV280_5964, RES_SHARED_VGA },
- { PCI_CHIP_RV280_5965, PCI_CHIP_RV280_5965, RES_SHARED_VGA },
- { PCI_CHIP_RV280_5C61, PCI_CHIP_RV280_5C61, RES_SHARED_VGA },
- { PCI_CHIP_RV280_5C63, PCI_CHIP_RV280_5C63, RES_SHARED_VGA },
- { PCI_CHIP_R300_AD, PCI_CHIP_R300_AD, RES_SHARED_VGA },
- { PCI_CHIP_R300_AE, PCI_CHIP_R300_AE, RES_SHARED_VGA },
- { PCI_CHIP_R300_AF, PCI_CHIP_R300_AF, RES_SHARED_VGA },
- { PCI_CHIP_R300_AG, PCI_CHIP_R300_AG, RES_SHARED_VGA },
- { PCI_CHIP_R300_ND, PCI_CHIP_R300_ND, RES_SHARED_VGA },
- { PCI_CHIP_R300_NE, PCI_CHIP_R300_NE, RES_SHARED_VGA },
- { PCI_CHIP_R300_NF, PCI_CHIP_R300_NF, RES_SHARED_VGA },
- { PCI_CHIP_R300_NG, PCI_CHIP_R300_NG, RES_SHARED_VGA },
- { PCI_CHIP_RV350_AP, PCI_CHIP_RV350_AP, RES_SHARED_VGA },
- { PCI_CHIP_RV350_AQ, PCI_CHIP_RV350_AQ, RES_SHARED_VGA },
- { PCI_CHIP_RV360_AR, PCI_CHIP_RV360_AR, RES_SHARED_VGA },
- { PCI_CHIP_RV350_AS, PCI_CHIP_RV350_AS, RES_SHARED_VGA },
- { PCI_CHIP_RV350_AT, PCI_CHIP_RV350_AT, RES_SHARED_VGA },
- { PCI_CHIP_RV350_AV, PCI_CHIP_RV350_AV, RES_SHARED_VGA },
- { PCI_CHIP_RV350_NP, PCI_CHIP_RV350_NP, RES_SHARED_VGA },
- { PCI_CHIP_RV350_NQ, PCI_CHIP_RV350_NQ, RES_SHARED_VGA },
- { PCI_CHIP_RV350_NR, PCI_CHIP_RV350_NR, RES_SHARED_VGA },
- { PCI_CHIP_RV350_NS, PCI_CHIP_RV350_NS, RES_SHARED_VGA },
- { PCI_CHIP_RV350_NT, PCI_CHIP_RV350_NT, RES_SHARED_VGA },
- { PCI_CHIP_RV350_NV, PCI_CHIP_RV350_NV, RES_SHARED_VGA },
- { PCI_CHIP_RV350_4155, PCI_CHIP_RV350_4155, RES_SHARED_VGA },
- { PCI_CHIP_R350_AH, PCI_CHIP_R350_AH, RES_SHARED_VGA },
- { PCI_CHIP_R350_AI, PCI_CHIP_R350_AI, RES_SHARED_VGA },
- { PCI_CHIP_R350_AJ, PCI_CHIP_R350_AJ, RES_SHARED_VGA },
- { PCI_CHIP_R350_AK, PCI_CHIP_R350_AK, RES_SHARED_VGA },
- { PCI_CHIP_R350_NH, PCI_CHIP_R350_NH, RES_SHARED_VGA },
- { PCI_CHIP_R350_NI, PCI_CHIP_R350_NI, RES_SHARED_VGA },
- { PCI_CHIP_R350_NK, PCI_CHIP_R350_NK, RES_SHARED_VGA },
- { PCI_CHIP_R360_NJ, PCI_CHIP_R360_NJ, RES_SHARED_VGA },
- { PCI_CHIP_RV380_3E50, PCI_CHIP_RV380_3E50, RES_SHARED_VGA },
- { PCI_CHIP_RV380_3E54, PCI_CHIP_RV380_3E54, RES_SHARED_VGA },
- { PCI_CHIP_RV380_3150, PCI_CHIP_RV380_3150, RES_SHARED_VGA },
- { PCI_CHIP_RV380_3152, PCI_CHIP_RV380_3152, RES_SHARED_VGA },
- { PCI_CHIP_RV380_3154, PCI_CHIP_RV380_3154, RES_SHARED_VGA },
- { PCI_CHIP_RV370_5B60, PCI_CHIP_RV370_5B60, RES_SHARED_VGA },
- { PCI_CHIP_RV370_5B62, PCI_CHIP_RV370_5B62, RES_SHARED_VGA },
- { PCI_CHIP_RV370_5B63, PCI_CHIP_RV370_5B63, RES_SHARED_VGA },
- { PCI_CHIP_RV370_5B64, PCI_CHIP_RV370_5B64, RES_SHARED_VGA },
- { PCI_CHIP_RV370_5B65, PCI_CHIP_RV370_5B65, RES_SHARED_VGA },
- { PCI_CHIP_RV370_5460, PCI_CHIP_RV370_5460, RES_SHARED_VGA },
- { PCI_CHIP_RV370_5462, PCI_CHIP_RV370_5462, RES_SHARED_VGA },
- { PCI_CHIP_RV370_5464, PCI_CHIP_RV370_5464, RES_SHARED_VGA },
- { PCI_CHIP_RS400_5A41, PCI_CHIP_RS400_5A41, RES_SHARED_VGA },
- { PCI_CHIP_RS400_5A42, PCI_CHIP_RS400_5A42, RES_SHARED_VGA },
- { PCI_CHIP_RC410_5A61, PCI_CHIP_RC410_5A61, RES_SHARED_VGA },
- { PCI_CHIP_RC410_5A62, PCI_CHIP_RC410_5A62, RES_SHARED_VGA },
- { PCI_CHIP_RS480_5954, PCI_CHIP_RS480_5954, RES_SHARED_VGA },
- { PCI_CHIP_RS480_5955, PCI_CHIP_RS480_5955, RES_SHARED_VGA },
- { PCI_CHIP_RS482_5974, PCI_CHIP_RS482_5974, RES_SHARED_VGA },
- { PCI_CHIP_RS485_5975, PCI_CHIP_RS485_5975, RES_SHARED_VGA },
- { PCI_CHIP_RV410_5E48, PCI_CHIP_RV410_5E48, RES_SHARED_VGA },
- { PCI_CHIP_RV410_564A, PCI_CHIP_RV410_564A, RES_SHARED_VGA },
- { PCI_CHIP_RV410_564B, PCI_CHIP_RV410_564B, RES_SHARED_VGA },
- { PCI_CHIP_RV410_564F, PCI_CHIP_RV410_564F, RES_SHARED_VGA },
- { PCI_CHIP_RV410_5652, PCI_CHIP_RV410_5652, RES_SHARED_VGA },
- { PCI_CHIP_RV410_5653, PCI_CHIP_RV410_5653, RES_SHARED_VGA },
- { PCI_CHIP_RV410_5E4B, PCI_CHIP_RV410_5E4B, RES_SHARED_VGA },
- { PCI_CHIP_RV410_5E4A, PCI_CHIP_RV410_5E4A, RES_SHARED_VGA },
- { PCI_CHIP_RV410_5E4D, PCI_CHIP_RV410_5E4D, RES_SHARED_VGA },
- { PCI_CHIP_RV410_5E4C, PCI_CHIP_RV410_5E4C, RES_SHARED_VGA },
- { PCI_CHIP_RV410_5E4F, PCI_CHIP_RV410_5E4F, RES_SHARED_VGA },
- { PCI_CHIP_R420_JH, PCI_CHIP_R420_JH, RES_SHARED_VGA },
- { PCI_CHIP_R420_JI, PCI_CHIP_R420_JI, RES_SHARED_VGA },
- { PCI_CHIP_R420_JJ, PCI_CHIP_R420_JJ, RES_SHARED_VGA },
- { PCI_CHIP_R420_JK, PCI_CHIP_R420_JK, RES_SHARED_VGA },
- { PCI_CHIP_R420_JL, PCI_CHIP_R420_JL, RES_SHARED_VGA },
- { PCI_CHIP_R420_JM, PCI_CHIP_R420_JM, RES_SHARED_VGA },
- { PCI_CHIP_R420_JN, PCI_CHIP_R420_JN, RES_SHARED_VGA },
- { PCI_CHIP_R420_JP, PCI_CHIP_R420_JP, RES_SHARED_VGA },
- { PCI_CHIP_R420_4A4F, PCI_CHIP_R420_4A4F, RES_SHARED_VGA },
- { PCI_CHIP_R420_4A54, PCI_CHIP_R420_4A54, RES_SHARED_VGA },
- { PCI_CHIP_R423_UH, PCI_CHIP_R423_UH, RES_SHARED_VGA },
- { PCI_CHIP_R423_UI, PCI_CHIP_R423_UI, RES_SHARED_VGA },
- { PCI_CHIP_R423_UJ, PCI_CHIP_R423_UJ, RES_SHARED_VGA },
- { PCI_CHIP_R423_UK, PCI_CHIP_R423_UK, RES_SHARED_VGA },
- { PCI_CHIP_R423_UQ, PCI_CHIP_R423_UQ, RES_SHARED_VGA },
- { PCI_CHIP_R423_UR, PCI_CHIP_R423_UR, RES_SHARED_VGA },
- { PCI_CHIP_R423_UT, PCI_CHIP_R423_UT, RES_SHARED_VGA },
- { PCI_CHIP_R423_5D57, PCI_CHIP_R423_5D57, RES_SHARED_VGA },
- { PCI_CHIP_R423_5550, PCI_CHIP_R423_5550, RES_SHARED_VGA },
- { PCI_CHIP_R430_5D49, PCI_CHIP_R430_5D49, RES_SHARED_VGA },
- { PCI_CHIP_R430_5D4A, PCI_CHIP_R430_5D4A, RES_SHARED_VGA },
- { PCI_CHIP_R430_5D48, PCI_CHIP_R430_5D48, RES_SHARED_VGA },
- { PCI_CHIP_R430_554F, PCI_CHIP_R430_554F, RES_SHARED_VGA },
- { PCI_CHIP_R430_554D, PCI_CHIP_R430_554D, RES_SHARED_VGA },
- { PCI_CHIP_R430_554E, PCI_CHIP_R430_554E, RES_SHARED_VGA },
- { PCI_CHIP_R430_554C, PCI_CHIP_R430_554C, RES_SHARED_VGA },
- { PCI_CHIP_R480_5D4C, PCI_CHIP_R480_5D4C, RES_SHARED_VGA },
- { PCI_CHIP_R480_5D50, PCI_CHIP_R480_5D50, RES_SHARED_VGA },
- { PCI_CHIP_R480_5D4E, PCI_CHIP_R480_5D4E, RES_SHARED_VGA },
- { PCI_CHIP_R480_5D4F, PCI_CHIP_R480_5D4F, RES_SHARED_VGA },
- { PCI_CHIP_R480_5D52, PCI_CHIP_R480_5D52, RES_SHARED_VGA },
- { PCI_CHIP_R480_5D4D, PCI_CHIP_R480_5D4D, RES_SHARED_VGA },
- { PCI_CHIP_R481_4B4B, PCI_CHIP_R481_4B4B, RES_SHARED_VGA },
- { PCI_CHIP_R481_4B4A, PCI_CHIP_R481_4B4A, RES_SHARED_VGA },
- { PCI_CHIP_R481_4B49, PCI_CHIP_R481_4B49, RES_SHARED_VGA },
- { PCI_CHIP_R481_4B4C, PCI_CHIP_R481_4B4C, RES_SHARED_VGA },
-
- { -1, -1, RES_UNDEFINED }
-};
+#include "radeon_pci_chipset_gen.h"
int gRADEONEntityIndex = -1;
diff --git a/src/radeon_probe.h b/src/radeon_probe.h
index 66ece94..7f8ce45 100644
--- a/src/radeon_probe.h
+++ b/src/radeon_probe.h
@@ -166,6 +166,7 @@ typedef struct _RADEONCrtcPrivateRec {
#endif
int crtc_id;
int binding;
+ CARD32 cursor_offset;
/* Lookup table values to be set when the CRTC is enabled */
CARD8 lut_r[256], lut_g[256], lut_b[256];
} RADEONCrtcPrivateRec, *RADEONCrtcPrivatePtr;
diff --git a/src/radeon_reg.h b/src/radeon_reg.h
index 2653339..6e4e383 100644
--- a/src/radeon_reg.h
+++ b/src/radeon_reg.h
@@ -916,6 +916,7 @@
# define RADEON_LVDS_DISPLAY_DIS (1 << 1)
# define RADEON_LVDS_PANEL_TYPE (1 << 2)
# define RADEON_LVDS_PANEL_FORMAT (1 << 3)
+# define RADEON_LVDS_RST_FM (1 << 6)
# define RADEON_LVDS_EN (1 << 7)
# define RADEON_LVDS_BL_MOD_LEVEL_SHIFT 8
# define RADEON_LVDS_BL_MOD_LEVEL_MASK (0xff << 8)
diff --git a/src/radeon_render.c b/src/radeon_render.c
index 5074fe1..490dec1 100644
--- a/src/radeon_render.c
+++ b/src/radeon_render.c
@@ -392,7 +392,7 @@ static Bool FUNC_NAME(R100SetupTexture)(
#endif
ACCEL_PREAMBLE();
- if ((width > 2048) || (height > 2048))
+ if ((width > 2047) || (height > 2047))
return FALSE;
txformat = RadeonGetTextureFormat(format);
@@ -424,7 +424,7 @@ static Bool FUNC_NAME(R100SetupTexture)(
txformat |= ATILog2(width) << RADEON_TXFORMAT_WIDTH_SHIFT;
txformat |= ATILog2(height) << RADEON_TXFORMAT_HEIGHT_SHIFT;
} else {
- tex_size = ((height - 1) << 16) | (width - 1);
+ tex_size = (height << 16) | width;
txformat |= RADEON_TXFORMAT_NON_POWER2;
}
diff --git a/src/radeon_tv.c b/src/radeon_tv.c
index 3a26a0a..2a8873c 100644
--- a/src/radeon_tv.c
+++ b/src/radeon_tv.c
@@ -434,7 +434,7 @@ void RADEONInitTVRegisters(xf86OutputPtr output, RADEONSavePtr save,
save->tv_vscaler_cntl2 = ((save->tv_vscaler_cntl2 & 0x00fffff0)
| (0x10 << 24)
- | RADEON_DITHER_MODE
+ | RADEON_DITHER_MODE
| RADEON_Y_OUTPUT_DITHER_EN
| RADEON_UV_OUTPUT_DITHER_EN
| RADEON_UV_TO_BUF_DITHER_EN);
@@ -444,10 +444,12 @@ void RADEONInitTVRegisters(xf86OutputPtr output, RADEONSavePtr save,
tmp = (tmp << RADEON_UV_OUTPUT_POST_SCALE_SHIFT) | 0x000b0000;
save->tv_timing_cntl = tmp;
- save->tv_dac_cntl = RADEON_TV_DAC_NBLANK | RADEON_TV_DAC_NHOLD | (8 << 16) | (6 << 20);
+ save->tv_dac_cntl = (RADEON_TV_DAC_NBLANK |
+ RADEON_TV_DAC_NHOLD |
+ radeon_output->tv_dac_adj /*(8 << 16) | (6 << 20)*/);
if (radeon_output->tvStd == TV_STD_NTSC ||
- radeon_output->tvStd == TV_STD_NTSC_J)
+ radeon_output->tvStd == TV_STD_NTSC_J)
save->tv_dac_cntl |= RADEON_TV_DAC_STD_NTSC;
else
save->tv_dac_cntl |= RADEON_TV_DAC_STD_PAL;
diff --git a/src/radeon_video.c b/src/radeon_video.c
index 26857a5..3f0209e 100644
--- a/src/radeon_video.c
+++ b/src/radeon_video.c
@@ -414,11 +414,11 @@ static XF86AttributeRec Attributes[NUM_DEC_ATTRIBUTES+1] =
#define FOURCC_RGB24 0x00000000
-#define XVIMAGE_RGB24(byte_order) \
+#define XVIMAGE_RGB24 \
{ \
FOURCC_RGB24, \
XvRGB, \
- byte_order, \
+ LSBFirst, \
{ 'R', 'G', 'B', 0, \
0x00,0x00,0x00,0x10,0x80,0x00,0x00,0xAA,0x00,0x38,0x9B,0x71}, \
24, \
@@ -473,15 +473,14 @@ static XF86ImageRec Images[NUM_IMAGES] =
{
#if X_BYTE_ORDER == X_BIG_ENDIAN
XVIMAGE_RGBA32(MSBFirst),
- XVIMAGE_RGB24(MSBFirst),
XVIMAGE_RGBT16(MSBFirst),
XVIMAGE_RGB16(MSBFirst),
#else
XVIMAGE_RGBA32(LSBFirst),
- XVIMAGE_RGB24(LSBFirst),
XVIMAGE_RGBT16(LSBFirst),
XVIMAGE_RGB16(LSBFirst),
#endif
+ XVIMAGE_RGB24,
XVIMAGE_YUY2,
XVIMAGE_UYVY,
XVIMAGE_YV12,
@@ -2199,7 +2198,7 @@ RADEONCopyRGB24Data(
unsigned int w
){
CARD32 *dptr;
- CARD8 *sptr = 0;
+ CARD8 *sptr;
int i,j;
RADEONInfoPtr info = RADEONPTR(pScrn);
#ifdef XF86DRI
@@ -2210,11 +2209,9 @@ RADEONCopyRGB24Data(
int x, y;
unsigned int hpass;
- /* XXX Fix endian flip on R300 */
-
RADEONHostDataParams( pScrn, dst, dstPitch, 4, &dstPitchOff, &x, &y );
- while ( (dptr = ( CARD32* )RADEONHostDataBlit( pScrn, 4, w, dstPitch,
+ while ( (dptr = ( CARD32* )RADEONHostDataBlit( pScrn, 4, w, dstPitchOff,
&bufPitch, x, &y, &h,
&hpass )) )
{
@@ -2224,11 +2221,11 @@ RADEONCopyRGB24Data(
for ( i = 0 ; i < w; i++, sptr += 3 )
{
- *dptr++ = (sptr[0] << 24) | (sptr[1] << 16) | sptr[2];
+ dptr[i] = (sptr[2] << 16) | (sptr[1] << 8) | sptr[0];
}
- src += hpass * srcPitch;
- dptr += hpass * bufPitch;
+ src += srcPitch;
+ dptr += bufPitch / 4;
}
}
@@ -2246,14 +2243,12 @@ RADEONCopyRGB24Data(
& ~RADEON_NONSURF_AP0_SWP_16BPP);
#endif
- for(j=0;j<h;j++){
- dptr=(CARD32 *)(dst+j*dstPitch);
- sptr=src+j*srcPitch;
+ for (j = 0; j < h; j++) {
+ dptr = (CARD32 *)(dst + j * dstPitch);
+ sptr = src + j * srcPitch;
- for(i=w;i>0;i--){
- dptr[0]=((sptr[0])<<24)|((sptr[1])<<16)|(sptr[2]);
- dptr++;
- sptr+=3;
+ for (i = 0; i < w; i++, sptr += 3) {
+ dptr[i] = (sptr[2] << 16) | (sptr[1] << 8) | sptr[0];
}
}
@@ -2927,17 +2922,17 @@ RADEONPutImage(
switch(id) {
case FOURCC_RGB24:
- dstPitch=(width*4+0x0f)&(~0x0f);
- srcPitch=width*3;
+ dstPitch = width * 4;
+ srcPitch = width * 3;
break;
case FOURCC_RGBA32:
- dstPitch=(width*4+0x0f)&(~0x0f);
- srcPitch=width*4;
+ dstPitch = width * 4;
+ srcPitch = width * 4;
break;
case FOURCC_RGB16:
case FOURCC_RGBT16:
- dstPitch=(width*2+0x0f)&(~0x0f);
- srcPitch=(width*2+3)&(~0x03);
+ dstPitch = width * 2;
+ srcPitch = (width * 2 + 3) & ~3;
break;
case FOURCC_YV12:
case FOURCC_I420:
@@ -2950,11 +2945,20 @@ RADEONPutImage(
case FOURCC_UYVY:
case FOURCC_YUY2:
default:
- dstPitch = ((width << 1) + 63) & ~63;
- srcPitch = (width << 1);
+ dstPitch = width * 2;
+ srcPitch = width * 2;
break;
}
+#ifdef XF86DRI
+ if (info->directRenderingEnabled && info->DMAForXv) {
+ /* The upload blit only supports multiples of 64 bytes */
+ dstPitch = (dstPitch + 63) & ~63;
+ } else
+#endif
+ /* The overlay only supports multiples of 16 bytes */
+ dstPitch = (dstPitch + 15) & ~15;
+
new_size = dstPitch * height;
if (id == FOURCC_YV12 || id == FOURCC_I420) {
new_size += (dstPitch >> 1) * ((height + 1) & ~1);