diff --git a/src/AtomBios/CD_Operations.c b/src/AtomBios/CD_Operations.c
index 509aa0c..58c4ae9 100644
--- a/src/AtomBios/CD_Operations.c
+++ b/src/AtomBios/CD_Operations.c
@@ -44,7 +44,6 @@ Revision History:
#include "xorg-server.h"
#include "Decoder.h"
-#include "atombios.h"
VOID PutDataRegister(PARSER_TEMP_DATA STACK_BASED * pParserTempData);
VOID PutDataPS(PARSER_TEMP_DATA STACK_BASED * pParserTempData);
@@ -231,7 +230,7 @@ UINT32 IndirectInputOutput(PARSER_TEMP_DATA STACK_BASED * pParserTempData)
IndirectIOParserCommands[*pParserTempData->IndirectIOTablePointer].func(pParserTempData);
pParserTempData->IndirectIOTablePointer+=IndirectIOParserCommands[*pParserTempData->IndirectIOTablePointer].csize;
}
- pParserTempData->IndirectIOTablePointer-=*(UINT16*)(pParserTempData->IndirectIOTablePointer+1);
+ pParserTempData->IndirectIOTablePointer-=UINT16LE_TO_CPU(*(UINT16*)(pParserTempData->IndirectIOTablePointer+1));
pParserTempData->IndirectIOTablePointer++;
return pParserTempData->IndirectData;
} else pParserTempData->IndirectIOTablePointer+=IndirectIOParserCommands[*pParserTempData->IndirectIOTablePointer].csize;
@@ -243,7 +242,7 @@ UINT32 IndirectInputOutput(PARSER_TEMP_DATA STACK_BASED * pParserTempData)
VOID PutDataRegister(PARSER_TEMP_DATA STACK_BASED * pParserTempData)
{
- pParserTempData->Index=(UINT32)pParserTempData->pCmd->Parameters.WordXX.PA_Destination;
+ pParserTempData->Index=(UINT32)UINT16LE_TO_CPU(pParserTempData->pCmd->Parameters.WordXX.PA_Destination);
pParserTempData->Index+=pParserTempData->CurrentRegBlock;
switch(pParserTempData->Multipurpose.CurrentPort){
case ATI_RegsPort:
@@ -269,16 +268,16 @@ VOID PutDataRegister(PARSER_TEMP_DATA STACK_BASED * pParserTempData)
VOID PutDataPS(PARSER_TEMP_DATA STACK_BASED * pParserTempData)
{
*(pParserTempData->pDeviceData->pParameterSpace+pParserTempData->pCmd->Parameters.ByteXX.PA_Destination)=
- pParserTempData->DestData32;
+ CPU_TO_UINT32LE(pParserTempData->DestData32);
}
VOID PutDataWS(PARSER_TEMP_DATA STACK_BASED * pParserTempData)
{
if (pParserTempData->pCmd->Parameters.ByteXX.PA_Destination < WS_QUOTIENT_C)
- *(pParserTempData->pWorkingTableData->pWorkSpace+pParserTempData->pCmd->Parameters.ByteXX.PA_Destination) = pParserTempData->DestData32;
+ *(pParserTempData->pWorkingTableData->pWorkSpace+pParserTempData->pCmd->Parameters.ByteXX.PA_Destination) = pParserTempData->DestData32;
else
- switch (pParserTempData->pCmd->Parameters.ByteXX.PA_Destination)
- {
+ switch (pParserTempData->pCmd->Parameters.ByteXX.PA_Destination)
+ {
case WS_REMINDER_C:
pParserTempData->MultiplicationOrDivision.Division.Reminder32=pParserTempData->DestData32;
break;
@@ -339,7 +338,7 @@ VOID SkipParameters16(PARSER_TEMP_DATA STACK_BASED * pParserTempData)
UINT32 GetParametersRegister(PARSER_TEMP_DATA STACK_BASED * pParserTempData)
{
- pParserTempData->Index=*(UINT16*)pParserTempData->pWorkingTableData->IP;
+ pParserTempData->Index=UINT16LE_TO_CPU(*(UINT16*)pParserTempData->pWorkingTableData->IP);
pParserTempData->pWorkingTableData->IP+=sizeof(UINT16);
pParserTempData->Index+=pParserTempData->CurrentRegBlock;
switch(pParserTempData->Multipurpose.CurrentPort)
@@ -361,9 +360,11 @@ UINT32 GetParametersRegister(PARSER_TEMP_DATA STACK_BASED * pParserTempData)
UINT32 GetParametersPS(PARSER_TEMP_DATA STACK_BASED * pParserTempData)
{
+ UINT32 data;
pParserTempData->Index=*pParserTempData->pWorkingTableData->IP;
pParserTempData->pWorkingTableData->IP+=sizeof(UINT8);
- return *(pParserTempData->pDeviceData->pParameterSpace+pParserTempData->Index);
+ data = UINT32LE_TO_CPU(*(pParserTempData->pDeviceData->pParameterSpace+pParserTempData->Index));
+ return data;
}
UINT32 GetParametersWS(PARSER_TEMP_DATA STACK_BASED * pParserTempData)
@@ -419,9 +420,12 @@ UINT32 GetParametersMC(PARSER_TEMP_DATA STACK_BASED * pParserTempData)
UINT32 GetParametersIndirect(PARSER_TEMP_DATA STACK_BASED * pParserTempData)
{
- pParserTempData->Index=*(UINT16*)pParserTempData->pWorkingTableData->IP;
+ UINT32 ret;
+
+ pParserTempData->Index=UINT16LE_TO_CPU(*(UINT16*)pParserTempData->pWorkingTableData->IP);
pParserTempData->pWorkingTableData->IP+=sizeof(UINT16);
- return *(UINT32*)(RELATIVE_TO_BIOS_IMAGE(pParserTempData->Index)+pParserTempData->CurrentDataBlock);
+ ret = UINT32LE_TO_CPU(*(UINT32*)(RELATIVE_TO_BIOS_IMAGE(pParserTempData->Index)+pParserTempData->CurrentDataBlock));
+ return ret;
}
UINT32 GetParametersDirect8(PARSER_TEMP_DATA STACK_BASED * pParserTempData)
@@ -435,7 +439,7 @@ UINT32 GetParametersDirect8(PARSER_TEMP_DATA STACK_BASED * pParserTempData)
UINT32 GetParametersDirect16(PARSER_TEMP_DATA STACK_BASED * pParserTempData)
{
pParserTempData->CD_Mask.SrcAlignment=alignmentLowerWord;
- pParserTempData->Index=*(UINT16*)pParserTempData->pWorkingTableData->IP;
+ pParserTempData->Index=UINT16LE_TO_CPU(*(UINT16*)pParserTempData->pWorkingTableData->IP);
pParserTempData->pWorkingTableData->IP+=sizeof(UINT16);
return pParserTempData->Index;
}
@@ -443,7 +447,7 @@ UINT32 GetParametersDirect16(PARSER_TEMP_DATA STACK_BASED * pParserTempData)
UINT32 GetParametersDirect32(PARSER_TEMP_DATA STACK_BASED * pParserTempData)
{
pParserTempData->CD_Mask.SrcAlignment=alignmentDword;
- pParserTempData->Index=*(UINT32*)pParserTempData->pWorkingTableData->IP;
+ pParserTempData->Index=UINT32LE_TO_CPU(*(UINT32*)pParserTempData->pWorkingTableData->IP);
pParserTempData->pWorkingTableData->IP+=sizeof(UINT32);
return pParserTempData->Index;
}
@@ -474,7 +478,7 @@ VOID ProcessMove(PARSER_TEMP_DATA STACK_BASED * pParserTempData)
{
if (pParserTempData->CD_Mask.SrcAlignment!=alignmentDword)
{
- pParserTempData->DestData32=GetDestination[pParserTempData->ParametersType.Destination](pParserTempData);
+ pParserTempData->DestData32=GetDestination[pParserTempData->ParametersType.Destination](pParserTempData);
} else
{
SkipDestination[pParserTempData->ParametersType.Destination](pParserTempData);
@@ -664,7 +668,8 @@ VOID ProcessSwitch(PARSER_TEMP_DATA STACK_BASED * pParserTempData){
pParserTempData->SourceData32=GetSource[pParserTempData->ParametersType.Source](pParserTempData);
pParserTempData->SourceData32 >>= SourceAlignmentShift[pParserTempData->CD_Mask.SrcAlignment];
pParserTempData->SourceData32 &= AlignmentMask[pParserTempData->CD_Mask.SrcAlignment];
- while ( *(UINT16*)pParserTempData->pWorkingTableData->IP != (((UINT16)NOP_OPCODE << 8)+NOP_OPCODE))
+
+ while ( UINT16LE_TO_CPU(*(UINT16*)pParserTempData->pWorkingTableData->IP) != (((UINT16)NOP_OPCODE << 8)+NOP_OPCODE))
{
if (*pParserTempData->pWorkingTableData->IP == 'c')
{
@@ -673,7 +678,7 @@ VOID ProcessSwitch(PARSER_TEMP_DATA STACK_BASED * pParserTempData){
pParserTempData->Index=GetParametersDirect16(pParserTempData);
if (pParserTempData->SourceData32 == pParserTempData->DestData32)
{
- pParserTempData->pWorkingTableData->IP= RELATIVE_TO_TABLE(pParserTempData->Index);
+ pParserTempData->pWorkingTableData->IP= RELATIVE_TO_TABLE(pParserTempData->Index);
return;
}
}
@@ -695,7 +700,7 @@ VOID cmdSetDataBlock(PARSER_TEMP_DATA STACK_BASED * pParserTempData)
} else
{
pMasterDataTable = GetDataMasterTablePointer(pParserTempData->pDeviceData);
- pParserTempData->CurrentDataBlock= (TABLE_UNIT_TYPE)((PTABLE_UNIT_TYPE)pMasterDataTable)[value];
+ pParserTempData->CurrentDataBlock= UINT16LE_TO_CPU((TABLE_UNIT_TYPE)((PTABLE_UNIT_TYPE)pMasterDataTable)[value]);
}
}
pParserTempData->pWorkingTableData->IP+=sizeof(COMMAND_TYPE_OPCODE_VALUE_BYTE);
@@ -704,13 +709,13 @@ VOID cmdSetDataBlock(PARSER_TEMP_DATA STACK_BASED * pParserTempData)
VOID cmdSet_ATI_Port(PARSER_TEMP_DATA STACK_BASED * pParserTempData)
{
pParserTempData->Multipurpose.CurrentPort=ATI_RegsPort;
- pParserTempData->CurrentPortID = (UINT8)((COMMAND_TYPE_1*)pParserTempData->pWorkingTableData->IP)->Parameters.WordXX.PA_Destination;
+ pParserTempData->CurrentPortID = (UINT8)UINT16LE_TO_CPU(((COMMAND_TYPE_1*)pParserTempData->pWorkingTableData->IP)->Parameters.WordXX.PA_Destination);
pParserTempData->pWorkingTableData->IP+=sizeof(COMMAND_TYPE_OPCODE_OFFSET16);
}
VOID cmdSet_Reg_Block(PARSER_TEMP_DATA STACK_BASED * pParserTempData)
{
- pParserTempData->CurrentRegBlock = ((COMMAND_TYPE_1*)pParserTempData->pWorkingTableData->IP)->Parameters.WordXX.PA_Destination;
+ pParserTempData->CurrentRegBlock = UINT16LE_TO_CPU(((COMMAND_TYPE_1*)pParserTempData->pWorkingTableData->IP)->Parameters.WordXX.PA_Destination);
pParserTempData->pWorkingTableData->IP+=sizeof(COMMAND_TYPE_OPCODE_OFFSET16);
}
@@ -754,19 +759,23 @@ VOID ProcessDebug(PARSER_TEMP_DATA STACK_BASED * pParserTempData)
VOID ProcessDS(PARSER_TEMP_DATA STACK_BASED * pParserTempData)
{
- pParserTempData->pWorkingTableData->IP+=((COMMAND_TYPE_1*)pParserTempData->pWorkingTableData->IP)->Parameters.WordXX.PA_Destination+sizeof(COMMAND_TYPE_OPCODE_OFFSET16);
+ pParserTempData->pWorkingTableData->IP+=UINT16LE_TO_CPU(((COMMAND_TYPE_1*)pParserTempData->pWorkingTableData->IP)->Parameters.WordXX.PA_Destination)+sizeof(COMMAND_TYPE_OPCODE_OFFSET16);
}
-VOID cmdCall_Table(PARSER_TEMP_DATA STACK_BASED * pParserTempData){
+VOID cmdCall_Table(PARSER_TEMP_DATA STACK_BASED * pParserTempData)
+{
UINT16* MasterTableOffset;
pParserTempData->pWorkingTableData->IP+=sizeof(COMMAND_TYPE_OPCODE_VALUE_BYTE);
MasterTableOffset = GetCommandMasterTablePointer(pParserTempData->pDeviceData);
if(((PTABLE_UNIT_TYPE)MasterTableOffset)[((COMMAND_TYPE_OPCODE_VALUE_BYTE*)pParserTempData->pCmd)->Value]!=0 ) // if the offset is not ZERO
{
+ ATOM_TABLE_ATTRIBUTE lTableAttr;
+
pParserTempData->CommandSpecific.IndexInMasterTable=GetTrueIndexInMasterTable(pParserTempData,((COMMAND_TYPE_OPCODE_VALUE_BYTE*)pParserTempData->pCmd)->Value);
- pParserTempData->Multipurpose.PS_SizeInDwordsUsedByCallingTable =
- (((ATOM_COMMON_ROM_COMMAND_TABLE_HEADER *)pParserTempData->pWorkingTableData->pTableHead)->TableAttribute.PS_SizeInBytes>>2);
+
+ lTableAttr = GetCommandTableAttribute(pParserTempData->pWorkingTableData->pTableHead);
+ pParserTempData->Multipurpose.PS_SizeInDwordsUsedByCallingTable = (lTableAttr.PS_SizeInBytes >>2);
pParserTempData->pDeviceData->pParameterSpace+=
pParserTempData->Multipurpose.PS_SizeInDwordsUsedByCallingTable;
pParserTempData->Status=CD_CALL_TABLE;
@@ -792,7 +801,7 @@ VOID ProcessJump(PARSER_TEMP_DATA STACK_BASED * pParserTempData)
(pParserTempData->ParametersType.Destination == pParserTempData->CompareFlags ))
{
- pParserTempData->pWorkingTableData->IP= RELATIVE_TO_TABLE(((COMMAND_TYPE_OPCODE_OFFSET16*)pParserTempData->pWorkingTableData->IP)->CD_Offset16);
+ pParserTempData->pWorkingTableData->IP= RELATIVE_TO_TABLE(UINT16LE_TO_CPU(((COMMAND_TYPE_OPCODE_OFFSET16*)pParserTempData->pWorkingTableData->IP)->CD_Offset16));
} else
{
pParserTempData->pWorkingTableData->IP+=sizeof(COMMAND_TYPE_OPCODE_OFFSET16);
@@ -805,7 +814,7 @@ VOID ProcessJumpE(PARSER_TEMP_DATA STACK_BASED * pParserTempData)
(pParserTempData->CompareFlags == pParserTempData->ParametersType.Destination))
{
- pParserTempData->pWorkingTableData->IP= RELATIVE_TO_TABLE(((COMMAND_TYPE_OPCODE_OFFSET16*)pParserTempData->pWorkingTableData->IP)->CD_Offset16);
+ pParserTempData->pWorkingTableData->IP= RELATIVE_TO_TABLE(UINT16LE_TO_CPU(((COMMAND_TYPE_OPCODE_OFFSET16*)pParserTempData->pWorkingTableData->IP)->CD_Offset16));
} else
{
pParserTempData->pWorkingTableData->IP+=sizeof(COMMAND_TYPE_OPCODE_OFFSET16);
@@ -817,7 +826,7 @@ VOID ProcessJumpNE(PARSER_TEMP_DATA STACK_BASED * pParserTempData)
if (pParserTempData->CompareFlags != Equal)
{
- pParserTempData->pWorkingTableData->IP= RELATIVE_TO_TABLE(((COMMAND_TYPE_OPCODE_OFFSET16*)pParserTempData->pWorkingTableData->IP)->CD_Offset16);
+ pParserTempData->pWorkingTableData->IP= RELATIVE_TO_TABLE(UINT16LE_TO_CPU(((COMMAND_TYPE_OPCODE_OFFSET16*)pParserTempData->pWorkingTableData->IP)->CD_Offset16));
} else
{
pParserTempData->pWorkingTableData->IP+=sizeof(COMMAND_TYPE_OPCODE_OFFSET16);
diff --git a/src/AtomBios/Decoder.c b/src/AtomBios/Decoder.c
index e8b3b6e..73aac94 100644
--- a/src/AtomBios/Decoder.c
+++ b/src/AtomBios/Decoder.c
@@ -40,12 +40,9 @@ Revision History:
#endif
#include <X11/Xos.h>
-
+#include "xorg-server.h"
#include "Decoder.h"
-#include "atombios.h"
-#include "CD_binding.h"
-#include "CD_Common_Types.h"
#ifndef DISABLE_EASF
#include "easf.h"
@@ -77,13 +74,13 @@ UINT16* GetCommandMasterTablePointer(DEVICE_DATA STACK_BASED* pDeviceData)
/*
make MasterTableOffset point to EASF_ASIC_SETUP_TABLE structure, including usSize.
*/
- MasterTableOffset = (UINT16 *) (pDeviceData->pBIOS_Image+((EASF_ASIC_DESCRIPTOR*)pDeviceData->pBIOS_Image)->usAsicSetupTable_Offset);
+ MasterTableOffset = (UINT16 *) (pDeviceData->pBIOS_Image+(UINT16LE_TO_CPU(((EASF_ASIC_DESCRIPTOR*)pDeviceData->pBIOS_Image)->usAsicSetupTable_Offset));
} else
#endif
{
#ifndef UEFI_BUILD
- MasterTableOffset = (UINT16 *)(*(UINT16 *)(pDeviceData->pBIOS_Image+OFFSET_TO_POINTER_TO_ATOM_ROM_HEADER) + pDeviceData->pBIOS_Image);
- MasterTableOffset = (UINT16 *)((ULONG)((ATOM_ROM_HEADER *)MasterTableOffset)->usMasterCommandTableOffset + pDeviceData->pBIOS_Image );
+ MasterTableOffset = (UINT16 *)(UINT16LE_TO_CPU(*(UINT16 *)(pDeviceData->pBIOS_Image+OFFSET_TO_POINTER_TO_ATOM_ROM_HEADER)) + pDeviceData->pBIOS_Image);
+ MasterTableOffset = (UINT16 *)((ULONG)UINT16LE_TO_CPU(((ATOM_ROM_HEADER *)MasterTableOffset)->usMasterCommandTableOffset) + pDeviceData->pBIOS_Image );
MasterTableOffset =(UINT16 *) &(((ATOM_MASTER_COMMAND_TABLE *)MasterTableOffset)->ListOfCommandTables);
#else
MasterTableOffset = (UINT16 *)(&(GetCommandMasterTable( )->ListOfCommandTables));
@@ -97,8 +94,8 @@ UINT16* GetDataMasterTablePointer(DEVICE_DATA STACK_BASED* pDeviceData)
UINT16 *MasterTableOffset;
#ifndef UEFI_BUILD
- MasterTableOffset = (UINT16 *)(*(UINT16 *)(pDeviceData->pBIOS_Image+OFFSET_TO_POINTER_TO_ATOM_ROM_HEADER) + pDeviceData->pBIOS_Image);
- MasterTableOffset = (UINT16 *)((ULONG)((ATOM_ROM_HEADER *)MasterTableOffset)->usMasterDataTableOffset + pDeviceData->pBIOS_Image );
+ MasterTableOffset = (UINT16 *)(UINT16LE_TO_CPU(*(UINT16 *)(pDeviceData->pBIOS_Image+OFFSET_TO_POINTER_TO_ATOM_ROM_HEADER)) + pDeviceData->pBIOS_Image);
+ MasterTableOffset = (UINT16 *)((ULONG)(UINT16LE_TO_CPU(((ATOM_ROM_HEADER *)MasterTableOffset)->usMasterDataTableOffset)) + pDeviceData->pBIOS_Image );
MasterTableOffset =(UINT16 *) &(((ATOM_MASTER_DATA_TABLE *)MasterTableOffset)->ListOfDataTables);
#else
MasterTableOffset = (UINT16 *)(&(GetDataMasterTable( )->ListOfDataTables));
@@ -129,11 +126,29 @@ UINT8 GetTrueIndexInMasterTable(PARSER_TEMP_DATA STACK_BASED * pParserTempData,
}
}
+ATOM_TABLE_ATTRIBUTE GetCommandTableAttribute(UINT8 *pTableHeader)
+{
+ ATOM_TABLE_ATTRIBUTE_ACCESS lTableAccess;
+
+ /* It's unclear whether this union trick breaks C aliasing rules,
+ * however, it's explicitely permitted by gcc, and we have other
+ * case where the code relies on a union being accessed by either
+ * of the "ways" and stay consistent so if a compiler breaks this
+ * assumption, it will probably need us to compile without strict
+ * aliasing enforcement
+ */
+ lTableAccess.sbfAccess = ((ATOM_COMMON_ROM_COMMAND_TABLE_HEADER *)pTableHeader)->TableAttribute;
+ lTableAccess.susAccess = UINT16LE_TO_CPU(lTableAccess.susAccess);
+
+ return lTableAccess.sbfAccess;
+}
+
CD_STATUS ParseTable(DEVICE_DATA STACK_BASED* pDeviceData, UINT8 IndexInMasterTable)
{
PARSER_TEMP_DATA ParserTempData;
WORKING_TABLE_DATA STACK_BASED* prevWorkingTableData;
+ memset(&ParserTempData, 0, sizeof(PARSER_TEMP_DATA));
ParserTempData.pDeviceData=(DEVICE_DATA*)pDeviceData;
#ifndef DISABLE_EASF
if (pDeviceData->format == TABLE_FORMAT_EASF)
@@ -143,7 +158,7 @@ CD_STATUS ParseTable(DEVICE_DATA STACK_BASED* pDeviceData, UINT8 IndexInMasterTa
#endif
{
ParserTempData.pCmd=(GENERIC_ATTRIBUTE_COMMAND*)GetDataMasterTablePointer(pDeviceData);
- ParserTempData.IndirectIOTablePointer=(UINT8*)((ULONG)(((PTABLE_UNIT_TYPE)ParserTempData.pCmd)[INDIRECT_IO_TABLE]) + pDeviceData->pBIOS_Image);
+ ParserTempData.IndirectIOTablePointer=(UINT8*)((ULONG)(UINT16LE_TO_CPU(((PTABLE_UNIT_TYPE)ParserTempData.pCmd)[INDIRECT_IO_TABLE])) + pDeviceData->pBIOS_Image);
ParserTempData.IndirectIOTablePointer+=sizeof(ATOM_COMMON_TABLE_HEADER);
}
@@ -160,65 +175,66 @@ CD_STATUS ParseTable(DEVICE_DATA STACK_BASED* pDeviceData, UINT8 IndexInMasterTa
ParserTempData.Status=CD_CALL_TABLE;
do{
-
+
if (ParserTempData.Status==CD_CALL_TABLE)
- {
+ {
IndexInMasterTable=ParserTempData.CommandSpecific.IndexInMasterTable;
if(((PTABLE_UNIT_TYPE)ParserTempData.pCmd)[IndexInMasterTable]!=0) // if the offset is not ZERO
- {
+ {
+ ATOM_TABLE_ATTRIBUTE lTableAttr;
+ lTableAttr = GetCommandTableAttribute(UINT16LE_TO_CPU(((PTABLE_UNIT_TYPE)ParserTempData.pCmd)[IndexInMasterTable])+pDeviceData->pBIOS_Image);
#ifndef UEFI_BUILD
ParserTempData.pWorkingTableData =(WORKING_TABLE_DATA STACK_BASED*) AllocateWorkSpace(pDeviceData,
- ((ATOM_COMMON_ROM_COMMAND_TABLE_HEADER*)(((PTABLE_UNIT_TYPE)ParserTempData.pCmd)[IndexInMasterTable]+pDeviceData->pBIOS_Image))->TableAttribute.WS_SizeInBytes+sizeof(WORKING_TABLE_DATA));
+ lTableAttr.WS_SizeInBytes+sizeof(WORKING_TABLE_DATA));
#else
- ParserTempData.pWorkingTableData =(WORKING_TABLE_DATA STACK_BASED*) AllocateWorkSpace(pDeviceData,
- ((ATOM_COMMON_ROM_COMMAND_TABLE_HEADER*)(((PTABLE_UNIT_TYPE)ParserTempData.pCmd)[IndexInMasterTable]))->TableAttribute.WS_SizeInBytes+sizeof(WORKING_TABLE_DATA));
+ ParserTempData.pWorkingTableData =(WORKING_TABLE_DATA STACK_BASED*) AllocateWorkSpace(pDeviceData,
+ lTableAttr.WS_SizeInBytes+sizeof(WORKING_TABLE_DATA));
#endif
- if (ParserTempData.pWorkingTableData!=NULL)
- {
- ParserTempData.pWorkingTableData->pWorkSpace=(WORKSPACE_POINTER STACK_BASED*)((UINT8*)ParserTempData.pWorkingTableData+sizeof(WORKING_TABLE_DATA));
+ if (ParserTempData.pWorkingTableData!=NULL)
+ {
+ ParserTempData.pWorkingTableData->pWorkSpace=(WORKSPACE_POINTER STACK_BASED*)((UINT8*)ParserTempData.pWorkingTableData+sizeof(WORKING_TABLE_DATA));
#ifndef UEFI_BUILD
- ParserTempData.pWorkingTableData->pTableHead = (UINT8 *)(((PTABLE_UNIT_TYPE)ParserTempData.pCmd)[IndexInMasterTable]+pDeviceData->pBIOS_Image);
+ ParserTempData.pWorkingTableData->pTableHead = (UINT8 *)(UINT16LE_TO_CPU(((PTABLE_UNIT_TYPE)ParserTempData.pCmd)[IndexInMasterTable])+pDeviceData->pBIOS_Image);
#else
- ParserTempData.pWorkingTableData->pTableHead = (UINT8 *)(((PTABLE_UNIT_TYPE)ParserTempData.pCmd)[IndexInMasterTable]);
+ ParserTempData.pWorkingTableData->pTableHead = (UINT8 *)(UINT16LE_TO_CPU(((PTABLE_UNIT_TYPE)ParserTempData.pCmd)[IndexInMasterTable]));
#endif
- ParserTempData.pWorkingTableData->IP=((UINT8*)ParserTempData.pWorkingTableData->pTableHead)+sizeof(ATOM_COMMON_ROM_COMMAND_TABLE_HEADER);
- ParserTempData.pWorkingTableData->prevWorkingTableData=prevWorkingTableData;
- prevWorkingTableData=ParserTempData.pWorkingTableData;
- ParserTempData.Status = CD_SUCCESS;
- } else ParserTempData.Status = CD_UNEXPECTED_BEHAVIOR;
- } else ParserTempData.Status = CD_EXEC_TABLE_NOT_FOUND;
+ ParserTempData.pWorkingTableData->IP=((UINT8*)ParserTempData.pWorkingTableData->pTableHead)+sizeof(ATOM_COMMON_ROM_COMMAND_TABLE_HEADER);
+ ParserTempData.pWorkingTableData->prevWorkingTableData=prevWorkingTableData;
+ prevWorkingTableData=ParserTempData.pWorkingTableData;
+ ParserTempData.Status = CD_SUCCESS;
+ } else ParserTempData.Status = CD_UNEXPECTED_BEHAVIOR;
+ } else ParserTempData.Status = CD_EXEC_TABLE_NOT_FOUND;
}
if (!CD_ERROR(ParserTempData.Status))
{
- ParserTempData.Status = CD_SUCCESS;
+ ParserTempData.Status = CD_SUCCESS;
while (!CD_ERROR_OR_COMPLETED(ParserTempData.Status))
- {
-
+ {
if (IS_COMMAND_VALID(((COMMAND_HEADER*)ParserTempData.pWorkingTableData->IP)->Opcode))
- {
+ {
ParserTempData.pCmd = (GENERIC_ATTRIBUTE_COMMAND*)ParserTempData.pWorkingTableData->IP;
-
+
if (IS_END_OF_TABLE(((COMMAND_HEADER*)ParserTempData.pWorkingTableData->IP)->Opcode))
{
ParserTempData.Status=CD_COMPLETED;
- prevWorkingTableData=ParserTempData.pWorkingTableData->prevWorkingTableData;
-
+ prevWorkingTableData=ParserTempData.pWorkingTableData->prevWorkingTableData;
+
FreeWorkSpace(pDeviceData, ParserTempData.pWorkingTableData);
- ParserTempData.pWorkingTableData=prevWorkingTableData;
- if (prevWorkingTableData!=NULL)
- {
- ParserTempData.pDeviceData->pParameterSpace-=
- (((ATOM_COMMON_ROM_COMMAND_TABLE_HEADER*)ParserTempData.pWorkingTableData->
- pTableHead)->TableAttribute.PS_SizeInBytes>>2);
- }
- // if there is a parent table where to return, then restore PS_pointer to the original state
+ ParserTempData.pWorkingTableData=prevWorkingTableData;
+ if (prevWorkingTableData!=NULL)
+ {
+ ATOM_TABLE_ATTRIBUTE lTableAttr;
+ lTableAttr = GetCommandTableAttribute(ParserTempData.pWorkingTableData->pTableHead);
+ ParserTempData.pDeviceData->pParameterSpace-=(lTableAttr.PS_SizeInBytes>>2);
+ }
+ // if there is a parent table where to return, then restore PS_pointer to the original state
}
else
{
- IndexInMasterTable=ProcessCommandProperties((PARSER_TEMP_DATA STACK_BASED *)&ParserTempData);
+ IndexInMasterTable=ProcessCommandProperties((PARSER_TEMP_DATA STACK_BASED *)&ParserTempData);
(*CallTable[IndexInMasterTable].function)((PARSER_TEMP_DATA STACK_BASED *)&ParserTempData);
#if (PARSER_TYPE!=DRIVER_TYPE_PARSER)
- BIOS_STACK_MODIFIER();
+ BIOS_STACK_MODIFIER();
#endif
}
}
@@ -227,13 +243,13 @@ CD_STATUS ParseTable(DEVICE_DATA STACK_BASED* pDeviceData, UINT8 IndexInMasterTa
ParserTempData.Status=CD_INVALID_OPCODE;
break;
}
-
+
} // while
} // if
else
break;
} while (prevWorkingTableData!=NULL);
- if (ParserTempData.Status == CD_COMPLETED) return CD_SUCCESS;
+ if (ParserTempData.Status == CD_COMPLETED) return CD_SUCCESS;
return ParserTempData.Status;
} else return CD_SUCCESS;
}
diff --git a/src/AtomBios/hwserv_drv.c b/src/AtomBios/hwserv_drv.c
index a5f5a5b..9f2b6b9 100644
--- a/src/AtomBios/hwserv_drv.c
+++ b/src/AtomBios/hwserv_drv.c
@@ -34,8 +34,14 @@ Revision History:
NEG:27.09.2002 Initiated.
--*/
-#include "CD_binding.h"
-#include "CD_hw_services.h"
+#ifdef HAVE_CONFIG_H
+#include "config.h"
+#endif
+
+#include <X11/Xos.h>
+#include "xorg-server.h"
+
+#include "Decoder.h"
//trace settings
#if DEBUG_OUTPUT_DEVICE & 1
@@ -249,12 +255,12 @@ VOID WriteReg32(PARSER_TEMP_DATA STACK_BASED * pWorkingTableData)
VOID ReadIndReg32 (PARSER_TEMP_DATA STACK_BASED * pWorkingTableData)
{
- pWorkingTableData->IndirectData = CailReadATIRegister(pWorkingTableData->pDeviceData->CAIL,*(UINT16*)(pWorkingTableData->IndirectIOTablePointer+1));
+ pWorkingTableData->IndirectData = CailReadATIRegister(pWorkingTableData->pDeviceData->CAIL,UINT16LE_TO_CPU(*(UINT16*)(pWorkingTableData->IndirectIOTablePointer+1)));
}
VOID WriteIndReg32(PARSER_TEMP_DATA STACK_BASED * pWorkingTableData)
{
- CailWriteATIRegister(pWorkingTableData->pDeviceData->CAIL,*(UINT16*)(pWorkingTableData->IndirectIOTablePointer+1),pWorkingTableData->IndirectData );
+ CailWriteATIRegister(pWorkingTableData->pDeviceData->CAIL,UINT16LE_TO_CPU(*(UINT16*)(pWorkingTableData->IndirectIOTablePointer+1)),pWorkingTableData->IndirectData);
}
#endif
diff --git a/src/AtomBios/includes/CD_Common_Types.h b/src/AtomBios/includes/CD_Common_Types.h
index c60b652..071b8fd 100644
--- a/src/AtomBios/includes/CD_Common_Types.h
+++ b/src/AtomBios/includes/CD_Common_Types.h
@@ -155,6 +155,18 @@ typedef unsigned long ULONG_PTR;
#ifndef FGL_LINUX
#pragma warning ( default : 4142 )
#endif
+
+#ifndef ATOM_BIG_ENDIAN
+#ifdef X_BYTE_ORDER
+#if X_BYTE_ORDER == X_BIG_ENDIAN
+#define ATOM_BIG_ENDIAN 1
+#endif
+#endif
+#endif
+#ifndef ATOM_BIG_ENDIAN
+#define ATOM_BIG_ENDIAN 0
+#endif
+
#endif // _COMMON_TYPES_H_
// EOF
diff --git a/src/AtomBios/includes/CD_Definitions.h b/src/AtomBios/includes/CD_Definitions.h
index 98fd495..c00e93e 100644
--- a/src/AtomBios/includes/CD_Definitions.h
+++ b/src/AtomBios/includes/CD_Definitions.h
@@ -39,11 +39,12 @@ NEG:27.08.2002 Initiated.
#ifndef _CD_DEFINITIONS_H
#define _CD_DEFINITIONS_H_
#ifdef DRIVER_PARSER
-VOID *AllocateMemory(VOID *, UINT16);
+VOID *AllocateMemory(DEVICE_DATA *, UINT16);
VOID ReleaseMemory(DEVICE_DATA * , WORKING_TABLE_DATA* );
#endif
CD_STATUS ParseTable(DEVICE_DATA* pDeviceData, UINT8 IndexInMasterTable);
//CD_STATUS CD_MainLoop(PARSER_TEMP_DATA_POINTER pParserTempData);
CD_STATUS Main_Loop(DEVICE_DATA* pDeviceData,UINT16 *MasterTableOffset,UINT8 IndexInMasterTable);
UINT16* GetCommandMasterTablePointer(DEVICE_DATA* pDeviceData);
+ATOM_TABLE_ATTRIBUTE GetCommandTableAttribute(UINT8 *pTableHeader);
#endif //CD_DEFINITIONS
diff --git a/src/AtomBios/includes/CD_Structs.h b/src/AtomBios/includes/CD_Structs.h
index c43f81d..01fb80e 100644
--- a/src/AtomBios/includes/CD_Structs.h
+++ b/src/AtomBios/includes/CD_Structs.h
@@ -35,10 +35,18 @@ Revision History:
NEG:26.08.2002 Initiated.
--*/
-#include "CD_binding.h"
#ifndef _CD_STRUCTS_H_
#define _CD_STRUCTS_H_
+#include "CD_binding.h"
+
+/* Endaianness should be specified before inclusion,
+ * default to little endian
+ */
+#ifndef ATOM_BIG_ENDIAN
+#error Endian not specified
+#endif
+
#ifdef UEFI_BUILD
typedef UINT16** PTABLE_UNIT_TYPE;
typedef UINTN TABLE_UNIT_TYPE;
@@ -304,9 +312,15 @@ typedef union _PARAMETER_ACCESS {
}PARAMETER_ACCESS;
typedef struct _COMMAND_ATTRIBUTE {
+#if ATOM_BIG_ENDIAN
+ UINT8 DestinationAlignment:2;
+ UINT8 SourceAlignment:3;
+ UINT8 Source:3;
+#else
UINT8 Source:3;
UINT8 SourceAlignment:3;
UINT8 DestinationAlignment:2;
+#endif
}COMMAND_ATTRIBUTE;
typedef struct _SOURCE_DESTINATION_ALIGNMENT{
@@ -363,11 +377,19 @@ typedef union _COMMAND_SPECIFIC_UNION{
typedef struct _CD_GENERIC_BYTE{
+#if ATOM_BIG_ENDIAN
+ UINT16 PS_SizeInDwordsUsedByCallingTable:5;
+ UINT16 CurrentPort:2;
+ UINT16 CommandAccessType:3;
+ UINT16 CurrentParameterSize:3;
+ UINT16 CommandType:3;
+#else
UINT16 CommandType:3;
UINT16 CurrentParameterSize:3;
UINT16 CommandAccessType:3;
UINT16 CurrentPort:2;
UINT16 PS_SizeInDwordsUsedByCallingTable:5;
+#endif
}CD_GENERIC_BYTE;
typedef UINT8 COMMAND_TYPE_OPCODE_ONLY;
diff --git a/src/AtomBios/includes/Decoder.h b/src/AtomBios/includes/Decoder.h
index 24c25fc..1e143f0 100644
--- a/src/AtomBios/includes/Decoder.h
+++ b/src/AtomBios/includes/Decoder.h
@@ -47,12 +47,32 @@ NEG:27.08.2002 Initiated.
#define PARSER_VERSION_MAJOR 0x00000000
#define PARSER_VERSION_MINOR 0x0000000E
#define PARSER_VERSION (PARSER_VERSION_MAJOR | PARSER_VERSION_MINOR)
-#include "CD_binding.h"
+
#include "CD_Common_Types.h"
+
+#include "atombios.h"
+
+/* these depends on some struct defined in atombios.h */
+#include "CD_binding.h"
#include "CD_hw_services.h"
#include "CD_Structs.h"
-#include "CD_Definitions.h"
#include "CD_Opcodes.h"
+#include "CD_Definitions.h"
+
+#if ATOM_BIG_ENDIAN
+extern UINT16 ATOM_BSWAP16(UINT16 x);
+extern UINT32 ATOM_BSWAP32(UINT32 x);
+
+#define CPU_TO_UINT16LE(x) ATOM_BSWAP16(x)
+#define CPU_TO_UINT32LE(x) ATOM_BSWAP32(x)
+#define UINT16LE_TO_CPU(x) ATOM_BSWAP16(x)
+#define UINT32LE_TO_CPU(x) ATOM_BSWAP32(x)
+#else
+#define CPU_TO_UINT16LE(x) (x)
+#define CPU_TO_UINT32LE(x) (x)
+#define UINT16LE_TO_CPU(x) (x)
+#define UINT32LE_TO_CPU(x) (x)
+#endif
#define SOURCE_ONLY_CMD_TYPE 0//0xFE
#define SOURCE_DESTINATION_CMD_TYPE 1//0xFD
diff --git a/src/AtomBios/includes/atombios.h b/src/AtomBios/includes/atombios.h
index 17483a6..2e7dc6c 100644
--- a/src/AtomBios/includes/atombios.h
+++ b/src/AtomBios/includes/atombios.h
@@ -34,6 +34,12 @@
#define ATOM_HEADER_VERSION (ATOM_VERSION_MAJOR | ATOM_VERSION_MINOR)
+/* Endianness should be specified before inclusion,
+ * default to little endian
+ */
+#ifndef ATOM_BIG_ENDIAN
+#error Endian not specified
+#endif
#ifdef _H2INC
#ifndef ULONG
@@ -304,7 +310,7 @@ typedef struct _ATOM_MASTER_COMMAND_TABLE
typedef struct _ATOM_TABLE_ATTRIBUTE
{
-#if X_BYTE_ORDER == X_BIG_ENDIAN
+#if ATOM_BIG_ENDIAN
USHORT UpdatedByUtility:1; //[15]=Table updated by utility flag
USHORT PS_SizeInBytes:7; //[14:8]=Size of parameter space in Bytes (multiple of a dword),
USHORT WS_SizeInBytes:8; //[7:0]=Size of workspace in Bytes (in multiple of a dword),
@@ -315,6 +321,12 @@ typedef struct _ATOM_TABLE_ATTRIBUTE
#endif
}ATOM_TABLE_ATTRIBUTE;
+typedef union _ATOM_TABLE_ATTRIBUTE_ACCESS
+{
+ ATOM_TABLE_ATTRIBUTE sbfAccess;
+ USHORT susAccess;
+}ATOM_TABLE_ATTRIBUTE_ACCESS;
+
// Common header for all command tables.
//Every table pointed by _ATOM_MASTER_COMMAND_TABLE has this common header.
//And the pointer actually points to this header.
@@ -1258,7 +1270,7 @@ typedef struct _ATOM_MULTIMEDIA_CONFIG_INFO
//Please don't add or expand this bitfield structure below, this one will retire soon.!
typedef struct _ATOM_FIRMWARE_CAPABILITY
{
-#if X_BYTE_ORDER == X_BIG_ENDIAN
+#if ATOM_BIG_ENDIAN
USHORT Reserved:3;
USHORT HyperMemory_Size:4;
USHORT HyperMemory_Support:1;
@@ -1767,7 +1779,7 @@ for Griffin or Greyhound. SBIOS needs to convert to actual time by:
typedef struct _ATOM_I2C_ID_CONFIG
{
-#if X_BYTE_ORDER == X_BIG_ENDIAN
+#if ATOM_BIG_ENDIAN
UCHAR bfHW_Capable:1;
UCHAR bfHW_EngineID:3;
UCHAR bfI2C_LineMux:4;
@@ -1820,7 +1832,7 @@ typedef struct _ATOM_GPIO_I2C_INFO
//Please don't add or expand this bitfield structure below, this one will retire soon.!
typedef struct _ATOM_MODE_MISC_INFO
{
-#if X_BYTE_ORDER == X_BIG_ENDIAN
+#if ATOM_BIG_ENDIAN
USHORT Reserved:6;
USHORT RGB888:1;
USHORT DoubleClock:1;
@@ -3426,7 +3438,7 @@ typedef struct _ATOM_MEMORY_VENDOR_BLOCK{
typedef struct _ATOM_MEMORY_SETTING_ID_CONFIG{
-#if X_BYTE_ORDER == X_BIG_ENDIAN
+#if ATOM_BIG_ENDIAN
ULONG ucMemBlkId:8;
ULONG ulMemClockRange:24;
#else
@@ -4072,7 +4084,7 @@ typedef struct _COMPASSIONATE_DATA
typedef struct _ATOM_CONNECTOR_INFO
{
-#if X_BYTE_ORDER == X_BIG_ENDIAN
+#if ATOM_BIG_ENDIAN
UCHAR bfConnectorType:4;
UCHAR bfAssociatedDAC:4;
#else
diff --git a/src/Makefile.am b/src/Makefile.am
index 5333495..97c686b 100644
--- a/src/Makefile.am
+++ b/src/Makefile.am
@@ -26,8 +26,11 @@
# _ladir passes a dummy rpath to libtool so the thing will actually link
# TODO: -nostdlib/-Bstatic/-lgcc platform magic, not installing the .a, etc.
+radeon_drv_la_LIBADD =
+
if DRI
RADEON_DRI_SRCS = radeon_dri.c
+radeon_drv_la_LIBADD += $(DRI_LIBS)
endif
RADEON_ATOMBIOS_SOURCES = \
@@ -70,6 +73,11 @@ AM_CFLAGS = @XORG_CFLAGS@ @DRI_CFLAGS@ @XMODES_CFLAGS@ -DDISABLE_EASF -DENABLE_A
INCLUDES = -I$(srcdir)/AtomBios/includes
+if XSERVER_LIBPCIACCESS
+ati_drv_la_LIBADD = $(PCIACCESS_LIBS)
+radeon_drv_la_LIBADD += $(PCIACCESS_LIBS)
+endif
+
ati_drv_la_LTLIBRARIES = ati_drv.la
ati_drv_la_LDFLAGS = -module -avoid-version
ati_drv_ladir = @moduledir@/drivers
diff --git a/src/ati_pciids_gen.h b/src/ati_pciids_gen.h
index a740df8..1da8f1f 100644
--- a/src/ati_pciids_gen.h
+++ b/src/ati_pciids_gen.h
@@ -1,4 +1,5 @@
#define PCI_CHIP_RV380_3150 0x3150
+#define PCI_CHIP_RV380_3151 0x3151
#define PCI_CHIP_RV380_3152 0x3152
#define PCI_CHIP_RV380_3154 0x3154
#define PCI_CHIP_RV380_3E50 0x3E50
@@ -330,6 +331,8 @@
#define PCI_CHIP_R600_940A 0x940A
#define PCI_CHIP_R600_940B 0x940B
#define PCI_CHIP_R600_940F 0x940F
+#define PCI_CHIP_RV770_9440 0x9440
+#define PCI_CHIP_RV770_9442 0x9442
#define PCI_CHIP_RV610_94C0 0x94C0
#define PCI_CHIP_RV610_94C1 0x94C1
#define PCI_CHIP_RV610_94C3 0x94C3
@@ -347,6 +350,7 @@
#define PCI_CHIP_RV670_9507 0x9507
#define PCI_CHIP_RV670_950F 0x950F
#define PCI_CHIP_RV670_9511 0x9511
+#define PCI_CHIP_RV670_9515 0x9515
#define PCI_CHIP_RV630_9580 0x9580
#define PCI_CHIP_RV630_9581 0x9581
#define PCI_CHIP_RV630_9583 0x9583
diff --git a/src/atombios_crtc.c b/src/atombios_crtc.c
index 363addf..70650e1 100644
--- a/src/atombios_crtc.c
+++ b/src/atombios_crtc.c
@@ -48,6 +48,29 @@
#include "sarea.h"
#endif
+AtomBiosResult
+atombios_lock_crtc(atomBiosHandlePtr atomBIOS, int crtc, int lock)
+{
+ ENABLE_CRTC_PS_ALLOCATION crtc_data;
+ AtomBiosArgRec data;
+ unsigned char *space;
+
+ crtc_data.ucCRTC = crtc;
+ crtc_data.ucEnable = lock;
+
+ data.exec.index = GetIndexIntoMasterTable(COMMAND, UpdateCRTC_DoubleBufferRegisters);
+ data.exec.dataSpace = (void *)&space;
+ data.exec.pspace = &crtc_data;
+
+ if (RHDAtomBiosFunc(atomBIOS->scrnIndex, atomBIOS, ATOMBIOS_EXEC, &data) == ATOM_SUCCESS) {
+ ErrorF("%s CRTC %d success\n", lock? "Lock":"Unlock", crtc);
+ return ATOM_SUCCESS ;
+ }
+
+ ErrorF("Lock CRTC failed\n");
+ return ATOM_NOT_IMPLEMENTED;
+}
+
static AtomBiosResult
atombios_enable_crtc(atomBiosHandlePtr atomBIOS, int crtc, int state)
{
@@ -105,7 +128,7 @@ atombios_blank_crtc(atomBiosHandlePtr atomBIOS, int crtc, int state)
crtc_data.ucCRTC = crtc;
crtc_data.ucBlanking = state;
- data.exec.index = offsetof(ATOM_MASTER_LIST_OF_COMMAND_TABLES, BlankCRTC) / sizeof(unsigned short);
+ data.exec.index = GetIndexIntoMasterTable(COMMAND, BlankCRTC);
data.exec.dataSpace = (void *)&space;
data.exec.pspace = &crtc_data;
@@ -146,10 +169,27 @@ atombios_set_crtc_timing(atomBiosHandlePtr atomBIOS, SET_CRTC_TIMING_PARAMETERS_
{
AtomBiosArgRec data;
unsigned char *space;
+ SET_CRTC_TIMING_PARAMETERS_PS_ALLOCATION conv_param;
+
+ conv_param.usH_Total = cpu_to_le16(crtc_param->usH_Total);
+ conv_param.usH_Disp = cpu_to_le16(crtc_param->usH_Disp);
+ conv_param.usH_SyncStart = cpu_to_le16(crtc_param->usH_SyncStart);
+ conv_param.usH_SyncWidth = cpu_to_le16(crtc_param->usH_SyncWidth);
+ conv_param.usV_Total = cpu_to_le16(crtc_param->usV_Total);
+ conv_param.usV_Disp = cpu_to_le16(crtc_param->usV_Disp);
+ conv_param.usV_SyncStart = cpu_to_le16(crtc_param->usV_SyncStart);
+ conv_param.usV_SyncWidth = cpu_to_le16(crtc_param->usV_SyncWidth);
+ conv_param.susModeMiscInfo.usAccess = cpu_to_le16(crtc_param->susModeMiscInfo.usAccess);
+ conv_param.ucCRTC = crtc_param->ucCRTC;
+ conv_param.ucOverscanRight = crtc_param->ucOverscanRight;
+ conv_param.ucOverscanLeft = crtc_param->ucOverscanLeft;
+ conv_param.ucOverscanBottom = crtc_param->ucOverscanBottom;
+ conv_param.ucOverscanTop = crtc_param->ucOverscanTop;
+ conv_param.ucReserved = crtc_param->ucReserved;
data.exec.index = GetIndexIntoMasterTable(COMMAND, SetCRTC_Timing);
data.exec.dataSpace = (void *)&space;
- data.exec.pspace = crtc_param;
+ data.exec.pspace = &conv_param;
if (RHDAtomBiosFunc(atomBIOS->scrnIndex, atomBIOS, ATOMBIOS_EXEC, &data) == ATOM_SUCCESS) {
ErrorF("Set CRTC Timing success\n");
@@ -235,9 +275,9 @@ atombios_crtc_set_pll(xf86CrtcPtr crtc, DisplayModePtr mode, int pll_flags)
case 1:
case 2:
spc2_ptr = (PIXEL_CLOCK_PARAMETERS_V2*)&spc_param.sPCLKInput;
- spc2_ptr->usPixelClock = sclock;
- spc2_ptr->usRefDiv = ref_div;
- spc2_ptr->usFbDiv = fb_div;
+ spc2_ptr->usPixelClock = cpu_to_le16(sclock);
+ spc2_ptr->usRefDiv = cpu_to_le16(ref_div);
+ spc2_ptr->usFbDiv = cpu_to_le16(fb_div);
spc2_ptr->ucPostDiv = post_div;
spc2_ptr->ucPpll = radeon_crtc->crtc_id ? ATOM_PPLL2 : ATOM_PPLL1;
spc2_ptr->ucCRTC = radeon_crtc->crtc_id;
@@ -246,9 +286,9 @@ atombios_crtc_set_pll(xf86CrtcPtr crtc, DisplayModePtr mode, int pll_flags)
break;
case 3:
spc3_ptr = (PIXEL_CLOCK_PARAMETERS_V3*)&spc_param.sPCLKInput;
- spc3_ptr->usPixelClock = sclock;
- spc3_ptr->usRefDiv = ref_div;
- spc3_ptr->usFbDiv = fb_div;
+ spc3_ptr->usPixelClock = cpu_to_le16(sclock);
+ spc3_ptr->usRefDiv = cpu_to_le16(ref_div);
+ spc3_ptr->usFbDiv = cpu_to_le16(fb_div);
spc3_ptr->ucPostDiv = post_div;
spc3_ptr->ucPpll = radeon_crtc->crtc_id ? ATOM_PPLL2 : ATOM_PPLL1;
spc3_ptr->ucMiscInfo = (radeon_crtc->crtc_id << 2);
@@ -442,9 +482,6 @@ atombios_crtc_mode_set(xf86CrtcPtr crtc,
fb_location = fb_location + (char *)crtc->rotatedData - (char *)info->FB;
}
- /* lock the grph regs */
- OUTREG(AVIVO_D1GRPH_UPDATE + radeon_crtc->crtc_offset, AVIVO_D1GRPH_UPDATE_LOCK);
-
OUTREG(AVIVO_D1GRPH_PRIMARY_SURFACE_ADDRESS + radeon_crtc->crtc_offset, fb_location);
OUTREG(AVIVO_D1GRPH_SECONDARY_SURFACE_ADDRESS + radeon_crtc->crtc_offset, fb_location);
OUTREG(AVIVO_D1GRPH_CONTROL + radeon_crtc->crtc_offset, fb_format);
@@ -459,26 +496,27 @@ atombios_crtc_mode_set(xf86CrtcPtr crtc,
crtc->scrn->displayWidth);
OUTREG(AVIVO_D1GRPH_ENABLE + radeon_crtc->crtc_offset, 1);
- /* unlock the grph regs */
- OUTREG(AVIVO_D1GRPH_UPDATE + radeon_crtc->crtc_offset, 0);
-
- /* lock the mode regs */
- OUTREG(AVIVO_D1SCL_UPDATE + radeon_crtc->crtc_offset, AVIVO_D1SCL_UPDATE_LOCK);
-
OUTREG(AVIVO_D1MODE_DESKTOP_HEIGHT + radeon_crtc->crtc_offset,
mode->VDisplay);
OUTREG(AVIVO_D1MODE_VIEWPORT_START + radeon_crtc->crtc_offset, (x << 16) | y);
OUTREG(AVIVO_D1MODE_VIEWPORT_SIZE + radeon_crtc->crtc_offset,
(mode->HDisplay << 16) | mode->VDisplay);
- /* unlock the mode regs */
- OUTREG(AVIVO_D1SCL_UPDATE + radeon_crtc->crtc_offset, 0);
+ if (adjusted_mode->Flags & V_INTERLACE)
+ OUTREG(AVIVO_D1MODE_DATA_FORMAT + radeon_crtc->crtc_offset,
+ AVIVO_D1MODE_INTERLEAVE_EN);
+ else
+ OUTREG(AVIVO_D1MODE_DATA_FORMAT + radeon_crtc->crtc_offset,
+ 0);
}
atombios_crtc_set_pll(crtc, adjusted_mode, pll_flags);
atombios_set_crtc_timing(info->atomBIOS, &crtc_timing);
+ if (info->DispPriority)
+ RADEONInitDispBandwidth(pScrn);
+
if (tilingChanged) {
/* need to redraw front buffer, I guess this can be considered a hack ? */
/* if this is called during ScreenInit() we don't have pScrn->pScreen yet */
@@ -492,3 +530,126 @@ atombios_crtc_mode_set(xf86CrtcPtr crtc,
}
+/* Calculate display buffer watermark to prevent buffer underflow */
+void
+RADEONInitDispBandwidthAVIVO(ScrnInfoPtr pScrn,
+ DisplayModePtr mode1, int pixel_bytes1,
+ DisplayModePtr mode2, int pixel_bytes2)
+{
+ RADEONInfoPtr info = RADEONPTR(pScrn);
+ RADEONEntPtr pRADEONEnt = RADEONEntPriv(pScrn);
+ unsigned char *RADEONMMIO = info->MMIO;
+
+ uint32_t dc_lb_memory_split;
+ float mem_bw, peak_disp_bw;
+ float min_mem_eff = 0.8; /* XXX: taken from legacy method */
+ float pix_clk, pix_clk2; /* in MHz */
+
+ /*
+ * Set display0/1 priority up in the memory controller for
+ * modes if the user specifies HIGH for displaypriority
+ * option.
+ */
+ if (info->DispPriority == 2) {
+ uint32_t mc_init_misc_lat_timer = 0;
+ if (info->ChipFamily == CHIP_FAMILY_RV515)
+ mc_init_misc_lat_timer = INMC(pScrn, RV515_MC_INIT_MISC_LAT_TIMER);
+ else if (info->ChipFamily == CHIP_FAMILY_RS690)
+ mc_init_misc_lat_timer = INMC(pScrn, RS690_MC_INIT_MISC_LAT_TIMER);
+
+ mc_init_misc_lat_timer &= ~(R300_MC_DISP1R_INIT_LAT_MASK << R300_MC_DISP1R_INIT_LAT_SHIFT);
+ mc_init_misc_lat_timer &= ~(R300_MC_DISP0R_INIT_LAT_MASK << R300_MC_DISP0R_INIT_LAT_SHIFT);
+
+ if (pRADEONEnt->pCrtc[1]->enabled)
+ mc_init_misc_lat_timer |= (1 << R300_MC_DISP1R_INIT_LAT_SHIFT); /* display 1 */
+ if (pRADEONEnt->pCrtc[0]->enabled)
+ mc_init_misc_lat_timer |= (1 << R300_MC_DISP0R_INIT_LAT_SHIFT); /* display 0 */
+
+ if (info->ChipFamily == CHIP_FAMILY_RV515)
+ OUTMC(pScrn, RV515_MC_INIT_MISC_LAT_TIMER, mc_init_misc_lat_timer);
+ else if (info->ChipFamily == CHIP_FAMILY_RS690)
+ OUTMC(pScrn, RS690_MC_INIT_MISC_LAT_TIMER, mc_init_misc_lat_timer);
+ }
+
+ /* XXX: fix me for AVIVO
+ * Determine if there is enough bandwidth for current display mode
+ */
+ mem_bw = info->mclk * (info->RamWidth / 8) * (info->IsDDR ? 2 : 1);
+
+ pix_clk = 0;
+ pix_clk2 = 0;
+ peak_disp_bw = 0;
+ if (mode1) {
+ pix_clk = mode1->Clock/1000.0;
+ peak_disp_bw += (pix_clk * pixel_bytes1);
+ }
+ if (mode2) {
+ pix_clk2 = mode2->Clock/1000.0;
+ peak_disp_bw += (pix_clk2 * pixel_bytes2);
+ }
+
+ if (peak_disp_bw >= mem_bw * min_mem_eff) {
+ xf86DrvMsg(pScrn->scrnIndex, X_WARNING,
+ "You may not have enough display bandwidth for current mode\n"
+ "If you have flickering problem, try to lower resolution, refresh rate, or color depth\n");
+ }
+
+ /*
+ * Line Buffer Setup
+ * There is a single line buffer shared by both display controllers.
+ * DC_LB_MEMORY_SPLIT controls how that line buffer is shared between the display
+ * controllers. The paritioning can either be done manually or via one of four
+ * preset allocations specified in bits 1:0:
+ * 0 - line buffer is divided in half and shared between each display controller
+ * 1 - D1 gets 3/4 of the line buffer, D2 gets 1/4
+ * 2 - D1 gets the whole buffer
+ * 3 - D1 gets 1/4 of the line buffer, D2 gets 3/4
+ * Setting bit 2 of DC_LB_MEMORY_SPLIT controls switches to manual allocation mode.
+ * In manual allocation mode, D1 always starts at 0, D1 end/2 is specified in bits
+ * 14:4; D2 allocation follows D1.
+ */
+
+ /* is auto or manual better ? */
+ dc_lb_memory_split = INREG(AVIVO_DC_LB_MEMORY_SPLIT) & ~AVIVO_DC_LB_MEMORY_SPLIT_MASK;
+ dc_lb_memory_split &= ~AVIVO_DC_LB_MEMORY_SPLIT_SHIFT_MODE;
+#if 1
+ /* auto */
+ if (mode1 && mode2) {
+ if (mode1->HDisplay > mode2->HDisplay) {
+ if (mode1->HDisplay > 2560)
+ dc_lb_memory_split |= AVIVO_DC_LB_MEMORY_SPLIT_D1_3Q_D2_1Q;
+ else
+ dc_lb_memory_split |= AVIVO_DC_LB_MEMORY_SPLIT_D1HALF_D2HALF;
+ } else if (mode2->HDisplay > mode1->HDisplay) {
+ if (mode2->HDisplay > 2560)
+ dc_lb_memory_split |= AVIVO_DC_LB_MEMORY_SPLIT_D1_1Q_D2_3Q;
+ else
+ dc_lb_memory_split |= AVIVO_DC_LB_MEMORY_SPLIT_D1HALF_D2HALF;
+ } else
+ dc_lb_memory_split |= AVIVO_DC_LB_MEMORY_SPLIT_D1HALF_D2HALF;
+ } else if (mode1) {
+ dc_lb_memory_split |= AVIVO_DC_LB_MEMORY_SPLIT_D1_ONLY;
+ } else if (mode2) {
+ dc_lb_memory_split |= AVIVO_DC_LB_MEMORY_SPLIT_D1_1Q_D2_3Q;
+ }
+#else
+ /* manual */
+ dc_lb_memory_split |= AVIVO_DC_LB_MEMORY_SPLIT_SHIFT_MODE;
+ dc_lb_memory_split &= ~(AVIVO_DC_LB_DISP1_END_ADR_MASK << AVIVO_DC_LB_DISP1_END_ADR_SHIFT);
+ if (mode1) {
+ dc_lb_memory_split |= ((((mode1->HDisplay / 2) + 64 /*???*/) & AVIVO_DC_LB_DISP1_END_ADR_MASK)
+ << AVIVO_DC_LB_DISP1_END_ADR_SHIFT);
+ } else if (mode2) {
+ dc_lb_memory_split |= (0 << AVIVO_DC_LB_DISP1_END_ADR_SHIFT);
+ }
+ OUTREG(AVIVO_DC_LB_MEMORY_SPLIT, dc_lb_memory_split);
+#endif
+
+ /*
+ * Watermark setup
+ * TODO...
+ * Unforunately, I haven't been able to dig up the avivo watermark programming
+ * guide yet. -AGD
+ */
+
+}
diff --git a/src/atombios_output.c b/src/atombios_output.c
index 51be301..83b86a7 100644
--- a/src/atombios_output.c
+++ b/src/atombios_output.c
@@ -78,7 +78,7 @@ atombios_output_dac1_setup(xf86OutputPtr output, DisplayModePtr mode)
}
}
- disp_data.usPixelClock = mode->Clock / 10;
+ disp_data.usPixelClock = cpu_to_le16(mode->Clock / 10);
data.exec.index = GetIndexIntoMasterTable(COMMAND, DAC1EncoderControl);
data.exec.dataSpace = (void *)&space;
data.exec.pspace = &disp_data;
@@ -128,7 +128,7 @@ atombios_output_dac2_setup(xf86OutputPtr output, DisplayModePtr mode)
}
}
- disp_data.usPixelClock = mode->Clock / 10;
+ disp_data.usPixelClock = cpu_to_le16(mode->Clock / 10);
data.exec.index = GetIndexIntoMasterTable(COMMAND, DAC2EncoderControl);
data.exec.dataSpace = (void *)&space;
data.exec.pspace = &disp_data;
@@ -188,7 +188,7 @@ atombios_output_tv1_setup(xf86OutputPtr output, DisplayModePtr mode)
}
}
- disp_data.sTVEncoder.usPixelClock = mode->Clock / 10;
+ disp_data.sTVEncoder.usPixelClock = cpu_to_le16(mode->Clock / 10);
data.exec.index = GetIndexIntoMasterTable(COMMAND, TVEncoderControl);
data.exec.dataSpace = (void *)&space;
data.exec.pspace = &disp_data;
@@ -243,7 +243,7 @@ atombios_output_ddia_setup(xf86OutputPtr output, DisplayModePtr mode)
unsigned char *space;
disp_data.sDVOEncoder.ucAction = ATOM_ENABLE;
- disp_data.sDVOEncoder.usPixelClock = mode->Clock / 10;
+ disp_data.sDVOEncoder.usPixelClock = cpu_to_le16(mode->Clock / 10);
if (mode->Clock > 165000)
disp_data.sDVOEncoder.usDevAttr.sDigAttrib.ucAttribute = PANEL_ENCODER_MISC_DUAL;
@@ -276,7 +276,7 @@ atombios_output_tmds1_setup(xf86OutputPtr output, DisplayModePtr mode)
disp_data.ucMisc = 1;
else
disp_data.ucMisc = 0;
- disp_data.usPixelClock = mode->Clock / 10;
+ disp_data.usPixelClock = cpu_to_le16(mode->Clock / 10);
data.exec.index = GetIndexIntoMasterTable(COMMAND, TMDS1EncoderControl);
data.exec.dataSpace = (void *)&space;
data.exec.pspace = &disp_data;
@@ -304,7 +304,7 @@ atombios_output_tmds2_setup(xf86OutputPtr output, DisplayModePtr mode)
disp_data.ucMisc = 1;
else
disp_data.ucMisc = 0;
- disp_data.usPixelClock = mode->Clock / 10;
+ disp_data.usPixelClock = cpu_to_le16(mode->Clock / 10);
data.exec.index = GetIndexIntoMasterTable(COMMAND, TMDS2EncoderControl);
data.exec.dataSpace = (void *)&space;
data.exec.pspace = &disp_data;
@@ -331,7 +331,7 @@ atombios_output_lvds_setup(xf86OutputPtr output, DisplayModePtr mode)
disp_data.ucMisc = 1;
else
disp_data.ucMisc = 0;
- disp_data.usPixelClock = mode->Clock / 10;
+ disp_data.usPixelClock = cpu_to_le16(mode->Clock / 10);
data.exec.index = GetIndexIntoMasterTable(COMMAND, LVDSEncoderControl);
data.exec.dataSpace = (void *)&space;
data.exec.pspace = &disp_data;
@@ -355,7 +355,7 @@ atombios_output_dig1_setup(xf86OutputPtr output, DisplayModePtr mode)
unsigned char *space;
disp_data.ucAction = 1;
- disp_data.usPixelClock = mode->Clock / 10;
+ disp_data.usPixelClock = cpu_to_le16(mode->Clock / 10);
disp_data.ucConfig = ATOM_ENCODER_CONFIG_TRANSMITTER1;
if (OUTPUT_IS_DVI || (radeon_output->type == OUTPUT_HDMI)) {
if (radeon_output->coherent_mode) {
@@ -406,7 +406,7 @@ atombios_output_dig1_transmitter_setup(xf86OutputPtr output, DisplayModePtr mode
unsigned char *space;
disp_data.ucAction = ATOM_TRANSMITTER_ACTION_ENABLE;
- disp_data.usPixelClock = mode->Clock / 10;
+ disp_data.usPixelClock = cpu_to_le16(mode->Clock / 10);
disp_data.ucConfig = ATOM_TRANSMITTER_CONFIG_DIG1_ENCODER | ATOM_TRANSMITTER_CONFIG_CLKSRC_PPLL;
if (info->IsIGP && (radeon_output->TMDSType == TMDS_UNIPHY)) {
@@ -464,7 +464,7 @@ atombios_output_dig2_setup(xf86OutputPtr output, DisplayModePtr mode)
unsigned char *space;
disp_data.ucAction = 1;
- disp_data.usPixelClock = mode->Clock / 10;
+ disp_data.usPixelClock = cpu_to_le16(mode->Clock / 10);
disp_data.ucConfig = ATOM_ENCODER_CONFIG_TRANSMITTER2;
if (OUTPUT_IS_DVI || (radeon_output->type == OUTPUT_HDMI)) {
if (radeon_output->coherent_mode) {
@@ -515,7 +515,7 @@ atombios_output_dig2_transmitter_setup(xf86OutputPtr output, DisplayModePtr mode
unsigned char *space;
disp_data.ucAction = ATOM_TRANSMITTER_ACTION_ENABLE;
- disp_data.usPixelClock = mode->Clock / 10;
+ disp_data.usPixelClock = cpu_to_le16(mode->Clock / 10);
disp_data.ucConfig = ATOM_TRANSMITTER_CONFIG_DIG2_ENCODER | ATOM_TRANSMITTER_CONFIG_CLKSRC_PPLL;
if (info->IsIGP && (radeon_output->TMDSType == TMDS_UNIPHY)) {
@@ -979,19 +979,19 @@ atom_bios_dac_load_detect(atomBiosHandlePtr atomBIOS, xf86OutputPtr output)
dac_data.sDacload.ucMisc = 0;
if (radeon_output->devices & ATOM_DEVICE_CRT1_SUPPORT) {
- dac_data.sDacload.usDeviceID = ATOM_DEVICE_CRT1_SUPPORT;
+ dac_data.sDacload.usDeviceID = cpu_to_le16(ATOM_DEVICE_CRT1_SUPPORT);
if (radeon_output->DACType == DAC_PRIMARY)
dac_data.sDacload.ucDacType = ATOM_DAC_A;
else if (radeon_output->DACType == DAC_TVDAC)
dac_data.sDacload.ucDacType = ATOM_DAC_B;
} else if (radeon_output->devices & ATOM_DEVICE_CRT2_SUPPORT) {
- dac_data.sDacload.usDeviceID = ATOM_DEVICE_CRT2_SUPPORT;
+ dac_data.sDacload.usDeviceID = cpu_to_le16(ATOM_DEVICE_CRT2_SUPPORT);
if (radeon_output->DACType == DAC_PRIMARY)
dac_data.sDacload.ucDacType = ATOM_DAC_A;
else if (radeon_output->DACType == DAC_TVDAC)
dac_data.sDacload.ucDacType = ATOM_DAC_B;
} else if (radeon_output->devices & ATOM_DEVICE_CV_SUPPORT) {
- dac_data.sDacload.usDeviceID = ATOM_DEVICE_CV_SUPPORT;
+ dac_data.sDacload.usDeviceID = cpu_to_le16(ATOM_DEVICE_CV_SUPPORT);
if (radeon_output->DACType == DAC_PRIMARY)
dac_data.sDacload.ucDacType = ATOM_DAC_A;
else if (radeon_output->DACType == DAC_TVDAC)
@@ -999,7 +999,7 @@ atom_bios_dac_load_detect(atomBiosHandlePtr atomBIOS, xf86OutputPtr output)
if (IS_DCE3_VARIANT)
dac_data.sDacload.ucMisc = 1;
} else if (radeon_output->devices & ATOM_DEVICE_TV1_SUPPORT) {
- dac_data.sDacload.usDeviceID = ATOM_DEVICE_TV1_SUPPORT;
+ dac_data.sDacload.usDeviceID = cpu_to_le16(ATOM_DEVICE_TV1_SUPPORT);
if (radeon_output->DACType == DAC_PRIMARY)
dac_data.sDacload.ucDacType = ATOM_DAC_A;
else if (radeon_output->DACType == DAC_TVDAC)
diff --git a/src/legacy_crtc.c b/src/legacy_crtc.c
index 3df61a7..334194a 100644
--- a/src/legacy_crtc.c
+++ b/src/legacy_crtc.c
@@ -625,6 +625,9 @@ radeon_crtc_modeset_ioctl(xf86CrtcPtr crtc, Bool post)
RADEONCrtcPrivatePtr radeon_crtc = crtc->driver_private;
struct drm_modeset_ctl modeset;
+ if (!info->directRenderingEnabled)
+ return;
+
modeset.crtc = radeon_crtc->crtc_id;
modeset.cmd = post ? _DRM_POST_MODESET : _DRM_PRE_MODESET;
@@ -1327,9 +1330,12 @@ radeon_update_tv_routing(ScrnInfoPtr pScrn, RADEONSavePtr restore)
}
/* Calculate display buffer watermark to prevent buffer underflow */
-static void
-RADEONInitDispBandwidth2(ScrnInfoPtr pScrn, RADEONInfoPtr info, int pixel_bytes2, DisplayModePtr mode1, DisplayModePtr mode2)
+void
+RADEONInitDispBandwidthLegacy(ScrnInfoPtr pScrn,
+ DisplayModePtr mode1, int pixel_bytes1,
+ DisplayModePtr mode2, int pixel_bytes2)
{
+ RADEONInfoPtr info = RADEONPTR(pScrn);
RADEONEntPtr pRADEONEnt = RADEONEntPriv(pScrn);
unsigned char *RADEONMMIO = info->MMIO;
@@ -1352,10 +1358,10 @@ RADEONInitDispBandwidth2(ScrnInfoPtr pScrn, RADEONInfoPtr info, int pixel_bytes2
float min_mem_eff = 0.8;
float sclk_eff, sclk_delay;
float mc_latency_mclk, mc_latency_sclk, cur_latency_mclk, cur_latency_sclk;
- float disp_latency, disp_latency_overhead, disp_drain_rate, disp_drain_rate2;
+ float disp_latency, disp_latency_overhead, disp_drain_rate = 0, disp_drain_rate2;
float pix_clk, pix_clk2; /* in MHz */
int cur_size = 16; /* in octawords */
- int critical_point, critical_point2;
+ int critical_point = 0, critical_point2;
int stop_req, max_stop_req;
float read_return_rate, time_disp1_drop_priority;
@@ -1366,15 +1372,15 @@ RADEONInitDispBandwidth2(ScrnInfoPtr pScrn, RADEONInfoPtr info, int pixel_bytes2
*/
if ((info->DispPriority == 2) && IS_R300_VARIANT) {
uint32_t mc_init_misc_lat_timer = INREG(R300_MC_INIT_MISC_LAT_TIMER);
- if (pRADEONEnt->pCrtc[1]->enabled) {
- mc_init_misc_lat_timer |= 0x1100; /* display 0 and 1 */
- } else {
- mc_init_misc_lat_timer |= 0x0100; /* display 0 only */
- }
+ mc_init_misc_lat_timer &= ~(R300_MC_DISP1R_INIT_LAT_MASK << R300_MC_DISP1R_INIT_LAT_SHIFT);
+ mc_init_misc_lat_timer &= ~(R300_MC_DISP0R_INIT_LAT_MASK << R300_MC_DISP0R_INIT_LAT_SHIFT);
+ if (pRADEONEnt->pCrtc[1]->enabled)
+ mc_init_misc_lat_timer |= (1 << R300_MC_DISP1R_INIT_LAT_SHIFT); /* display 1 */
+ if (pRADEONEnt->pCrtc[0]->enabled)
+ mc_init_misc_lat_timer |= (1 << R300_MC_DISP0R_INIT_LAT_SHIFT); /* display 0 */
OUTREG(R300_MC_INIT_MISC_LAT_TIMER, mc_init_misc_lat_timer);
}
-
/* R420 and RV410 family not supported yet */
if (info->ChipFamily == CHIP_FAMILY_R420 || info->ChipFamily == CHIP_FAMILY_RV410) return;
@@ -1383,15 +1389,17 @@ RADEONInitDispBandwidth2(ScrnInfoPtr pScrn, RADEONInfoPtr info, int pixel_bytes2
*/
mem_bw = info->mclk * (info->RamWidth / 8) * (info->IsDDR ? 2 : 1);
- pix_clk = mode1->Clock/1000.0;
- if (mode2)
+ pix_clk = 0;
+ pix_clk2 = 0;
+ peak_disp_bw = 0;
+ if (mode1) {
+ pix_clk = mode1->Clock/1000.0;
+ peak_disp_bw += (pix_clk * pixel_bytes1);
+ }
+ if (mode2) {
pix_clk2 = mode2->Clock/1000.0;
- else
- pix_clk2 = 0;
-
- peak_disp_bw = (pix_clk * info->CurrentLayout.pixel_bytes);
- if (pixel_bytes2)
- peak_disp_bw += (pix_clk2 * pixel_bytes2);
+ peak_disp_bw += (pix_clk2 * pixel_bytes2);
+ }
if (peak_disp_bw >= mem_bw * min_mem_eff) {
xf86DrvMsg(pScrn->scrnIndex, X_WARNING,
@@ -1399,20 +1407,6 @@ RADEONInitDispBandwidth2(ScrnInfoPtr pScrn, RADEONInfoPtr info, int pixel_bytes2
"If you have flickering problem, try to lower resolution, refresh rate, or color depth\n");
}
- /* CRTC1
- Set GRPH_BUFFER_CNTL register using h/w defined optimal values.
- GRPH_STOP_REQ <= MIN[ 0x7C, (CRTC_H_DISP + 1) * (bit depth) / 0x10 ]
- */
- stop_req = mode1->HDisplay * info->CurrentLayout.pixel_bytes / 16;
-
- /* setup Max GRPH_STOP_REQ default value */
- if (IS_RV100_VARIANT)
- max_stop_req = 0x5c;
- else
- max_stop_req = 0x7c;
- if (stop_req > max_stop_req)
- stop_req = max_stop_req;
-
/* Get values from the EXT_MEM_CNTL register...converting its contents. */
temp = INREG(RADEON_MEM_TIMING_CNTL);
if ((info->ChipFamily == CHIP_FAMILY_RV100) || info->IsIGP) { /* RV100, M6, IGPs */
@@ -1435,9 +1429,8 @@ RADEONInitDispBandwidth2(ScrnInfoPtr pScrn, RADEONInfoPtr info, int pixel_bytes2
}
if (IS_R300_VARIANT) {
-
/* on the R300, Tcas is included in Trbs.
- */
+ */
temp = INREG(RADEON_MEM_CNTL);
data = (R300_MEM_NUM_CHANNELS_MASK & temp);
if (data == 1) {
@@ -1473,7 +1466,8 @@ RADEONInitDispBandwidth2(ScrnInfoPtr pScrn, RADEONInfoPtr info, int pixel_bytes2
sclk_eff = info->sclk;
}
- /* Find the memory controller latency for the display client.
+ /*
+ Find the memory controller latency for the display client.
*/
if (IS_R300_VARIANT) {
/*not enough for R350 ???*/
@@ -1527,89 +1521,107 @@ RADEONInitDispBandwidth2(ScrnInfoPtr pScrn, RADEONInfoPtr info, int pixel_bytes2
mc_latency_sclk = mc_latency_sclk + disp_latency_overhead + cur_latency_sclk;
disp_latency = MAX(mc_latency_mclk, mc_latency_sclk);
- /*
- Find the drain rate of the display buffer.
- */
- disp_drain_rate = pix_clk / (16.0/info->CurrentLayout.pixel_bytes);
- if (pixel_bytes2)
- disp_drain_rate2 = pix_clk2 / (16.0/pixel_bytes2);
+ /* setup Max GRPH_STOP_REQ default value */
+ if (IS_RV100_VARIANT)
+ max_stop_req = 0x5c;
else
- disp_drain_rate2 = 0;
+ max_stop_req = 0x7c;
- /*
- Find the critical point of the display buffer.
- */
- critical_point= (uint32_t)(disp_drain_rate * disp_latency + 0.5);
+ if (mode1) {
+ /* CRTC1
+ Set GRPH_BUFFER_CNTL register using h/w defined optimal values.
+ GRPH_STOP_REQ <= MIN[ 0x7C, (CRTC_H_DISP + 1) * (bit depth) / 0x10 ]
+ */
+ stop_req = mode1->HDisplay * pixel_bytes1 / 16;
- /* ???? */
- /*
- temp = (info->SavedReg.grph_buffer_cntl & RADEON_GRPH_CRITICAL_POINT_MASK) >> RADEON_GRPH_CRITICAL_POINT_SHIFT;
- if (critical_point < temp) critical_point = temp;
- */
- if (info->DispPriority == 2) {
- critical_point = 0;
- }
+ if (stop_req > max_stop_req)
+ stop_req = max_stop_req;
- /*
- The critical point should never be above max_stop_req-4. Setting
- GRPH_CRITICAL_CNTL = 0 will thus force high priority all the time.
- */
- if (max_stop_req - critical_point < 4) critical_point = 0;
+ /*
+ Find the drain rate of the display buffer.
+ */
+ disp_drain_rate = pix_clk / (16.0/pixel_bytes1);
- if (critical_point == 0 && mode2 && info->ChipFamily == CHIP_FAMILY_R300) {
- /* some R300 cards have problem with this set to 0, when CRTC2 is enabled.*/
- critical_point = 0x10;
- }
+ /*
+ Find the critical point of the display buffer.
+ */
+ critical_point= (uint32_t)(disp_drain_rate * disp_latency + 0.5);
- temp = info->SavedReg->grph_buffer_cntl;
- temp &= ~(RADEON_GRPH_STOP_REQ_MASK);
- temp |= (stop_req << RADEON_GRPH_STOP_REQ_SHIFT);
- temp &= ~(RADEON_GRPH_START_REQ_MASK);
- if ((info->ChipFamily == CHIP_FAMILY_R350) &&
- (stop_req > 0x15)) {
- stop_req -= 0x10;
- }
- temp |= (stop_req << RADEON_GRPH_START_REQ_SHIFT);
+ /* ???? */
+ /*
+ temp = (info->SavedReg.grph_buffer_cntl & RADEON_GRPH_CRITICAL_POINT_MASK) >> RADEON_GRPH_CRITICAL_POINT_SHIFT;
+ if (critical_point < temp) critical_point = temp;
+ */
+ if (info->DispPriority == 2) {
+ critical_point = 0;
+ }
- temp |= RADEON_GRPH_BUFFER_SIZE;
- temp &= ~(RADEON_GRPH_CRITICAL_CNTL |
- RADEON_GRPH_CRITICAL_AT_SOF |
- RADEON_GRPH_STOP_CNTL);
- /*
- Write the result into the register.
- */
- OUTREG(RADEON_GRPH_BUFFER_CNTL, ((temp & ~RADEON_GRPH_CRITICAL_POINT_MASK) |
- (critical_point << RADEON_GRPH_CRITICAL_POINT_SHIFT)));
+ /*
+ The critical point should never be above max_stop_req-4. Setting
+ GRPH_CRITICAL_CNTL = 0 will thus force high priority all the time.
+ */
+ if (max_stop_req - critical_point < 4) critical_point = 0;
+
+ if (critical_point == 0 && mode2 && info->ChipFamily == CHIP_FAMILY_R300) {
+ /* some R300 cards have problem with this set to 0, when CRTC2 is enabled.*/
+ critical_point = 0x10;
+ }
+
+ temp = info->SavedReg->grph_buffer_cntl;
+ temp &= ~(RADEON_GRPH_STOP_REQ_MASK);
+ temp |= (stop_req << RADEON_GRPH_STOP_REQ_SHIFT);
+ temp &= ~(RADEON_GRPH_START_REQ_MASK);
+ if ((info->ChipFamily == CHIP_FAMILY_R350) &&
+ (stop_req > 0x15)) {
+ stop_req -= 0x10;
+ }
+ temp |= (stop_req << RADEON_GRPH_START_REQ_SHIFT);
+
+ temp |= RADEON_GRPH_BUFFER_SIZE;
+ temp &= ~(RADEON_GRPH_CRITICAL_CNTL |
+ RADEON_GRPH_CRITICAL_AT_SOF |
+ RADEON_GRPH_STOP_CNTL);
+ /*
+ Write the result into the register.
+ */
+ OUTREG(RADEON_GRPH_BUFFER_CNTL, ((temp & ~RADEON_GRPH_CRITICAL_POINT_MASK) |
+ (critical_point << RADEON_GRPH_CRITICAL_POINT_SHIFT)));
#if 0
- if ((info->ChipFamily == CHIP_FAMILY_RS400) ||
- (info->ChipFamily == CHIP_FAMILY_RS480)) {
- /* attempt to program RS400 disp regs correctly ??? */
- temp = info->SavedReg->disp1_req_cntl1;
- temp &= ~(RS400_DISP1_START_REQ_LEVEL_MASK |
- RS400_DISP1_STOP_REQ_LEVEL_MASK);
- OUTREG(RS400_DISP1_REQ_CNTL1, (temp |
- (critical_point << RS400_DISP1_START_REQ_LEVEL_SHIFT) |
- (critical_point << RS400_DISP1_STOP_REQ_LEVEL_SHIFT)));
- temp = info->SavedReg->dmif_mem_cntl1;
- temp &= ~(RS400_DISP1_CRITICAL_POINT_START_MASK |
- RS400_DISP1_CRITICAL_POINT_STOP_MASK);
- OUTREG(RS400_DMIF_MEM_CNTL1, (temp |
- (critical_point << RS400_DISP1_CRITICAL_POINT_START_SHIFT) |
- (critical_point << RS400_DISP1_CRITICAL_POINT_STOP_SHIFT)));
- }
+ if ((info->ChipFamily == CHIP_FAMILY_RS400) ||
+ (info->ChipFamily == CHIP_FAMILY_RS480)) {
+ /* attempt to program RS400 disp regs correctly ??? */
+ temp = info->SavedReg->disp1_req_cntl1;
+ temp &= ~(RS400_DISP1_START_REQ_LEVEL_MASK |
+ RS400_DISP1_STOP_REQ_LEVEL_MASK);
+ OUTREG(RS400_DISP1_REQ_CNTL1, (temp |
+ (critical_point << RS400_DISP1_START_REQ_LEVEL_SHIFT) |
+ (critical_point << RS400_DISP1_STOP_REQ_LEVEL_SHIFT)));
+ temp = info->SavedReg->dmif_mem_cntl1;
+ temp &= ~(RS400_DISP1_CRITICAL_POINT_START_MASK |
+ RS400_DISP1_CRITICAL_POINT_STOP_MASK);
+ OUTREG(RS400_DMIF_MEM_CNTL1, (temp |
+ (critical_point << RS400_DISP1_CRITICAL_POINT_START_SHIFT) |
+ (critical_point << RS400_DISP1_CRITICAL_POINT_STOP_SHIFT)));
+ }
#endif
- xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG,
- "GRPH_BUFFER_CNTL from %x to %x\n",
- (unsigned int)info->SavedReg->grph_buffer_cntl,
- (unsigned int)INREG(RADEON_GRPH_BUFFER_CNTL));
+ xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG,
+ "GRPH_BUFFER_CNTL from %x to %x\n",
+ (unsigned int)info->SavedReg->grph_buffer_cntl,
+ (unsigned int)INREG(RADEON_GRPH_BUFFER_CNTL));
+ }
if (mode2) {
stop_req = mode2->HDisplay * pixel_bytes2 / 16;
if (stop_req > max_stop_req) stop_req = max_stop_req;
+ /*
+ Find the drain rate of the display buffer.
+ */
+ disp_drain_rate2 = pix_clk2 / (16.0/pixel_bytes2);
+
temp = info->SavedReg->grph2_buffer_cntl;
temp &= ~(RADEON_GRPH_STOP_REQ_MASK);
temp |= (stop_req << RADEON_GRPH_STOP_REQ_SHIFT);
@@ -1629,7 +1641,10 @@ RADEONInitDispBandwidth2(ScrnInfoPtr pScrn, RADEONInfoPtr info, int pixel_bytes2
critical_point2 = 0;
else {
read_return_rate = MIN(info->sclk, info->mclk*(info->RamWidth*(info->IsDDR+1)/128));
- time_disp1_drop_priority = critical_point / (read_return_rate - disp_drain_rate);
+ if (mode1)
+ time_disp1_drop_priority = critical_point / (read_return_rate - disp_drain_rate);
+ else
+ time_disp1_drop_priority = 0;
critical_point2 = (uint32_t)((disp_latency + time_disp1_drop_priority +
disp_latency) * disp_drain_rate2 + 0.5);
@@ -1681,45 +1696,6 @@ RADEONInitDispBandwidth2(ScrnInfoPtr pScrn, RADEONInfoPtr info, int pixel_bytes2
}
void
-RADEONInitDispBandwidth(ScrnInfoPtr pScrn)
-{
- RADEONInfoPtr info = RADEONPTR(pScrn);
- xf86CrtcConfigPtr xf86_config = XF86_CRTC_CONFIG_PTR(pScrn);
- DisplayModePtr mode1, mode2;
- int pixel_bytes2 = 0;
-
- if (info->IsPrimary || info->IsSecondary)
- mode1 = &xf86_config->crtc[0]->mode;
- else
- mode1 = info->CurrentLayout.mode;
- mode2 = NULL;
- pixel_bytes2 = info->CurrentLayout.pixel_bytes;
-
- if (xf86_config->num_crtc == 2) {
- pixel_bytes2 = 0;
- mode2 = NULL;
-
- if (xf86_config->crtc[1]->enabled && xf86_config->crtc[0]->enabled) {
- pixel_bytes2 = info->CurrentLayout.pixel_bytes;
- mode1 = &xf86_config->crtc[0]->mode;
- mode2 = &xf86_config->crtc[1]->mode;
- } else if (xf86_config->crtc[0]->enabled) {
- mode1 = &xf86_config->crtc[0]->mode;
- } else if (xf86_config->crtc[1]->enabled) {
- mode1 = &xf86_config->crtc[1]->mode;
- } else
- return;
- } else {
- if (xf86_config->crtc[0]->enabled)
- mode1 = &xf86_config->crtc[0]->mode;
- else
- return;
- }
-
- RADEONInitDispBandwidth2(pScrn, info, pixel_bytes2, mode1, mode2);
-}
-
-void
legacy_crtc_mode_set(xf86CrtcPtr crtc, DisplayModePtr mode,
DisplayModePtr adjusted_mode, int x, int y)
{
diff --git a/src/legacy_output.c b/src/legacy_output.c
index 9c9ebb9..e5ddf1f 100644
--- a/src/legacy_output.c
+++ b/src/legacy_output.c
@@ -48,6 +48,8 @@
#include "radeon_tv.h"
#include "radeon_atombios.h"
+#include "ati_pciids_gen.h"
+
static RADEONMonitorType radeon_detect_tv(ScrnInfoPtr pScrn);
static RADEONMonitorType radeon_detect_primary_dac(ScrnInfoPtr pScrn, Bool color);
static RADEONMonitorType radeon_detect_tv_dac(ScrnInfoPtr pScrn, Bool color);
@@ -277,16 +279,12 @@ static void
RADEONRestoreDVOChip(ScrnInfoPtr pScrn, xf86OutputPtr output)
{
RADEONInfoPtr info = RADEONPTR(pScrn);
- unsigned char *RADEONMMIO = info->MMIO;
RADEONOutputPrivatePtr radeon_output = output->driver_private;
if (!radeon_output->DVOChip)
return;
- OUTREG(radeon_output->dvo_i2c.mask_clk_reg,
- INREG(radeon_output->dvo_i2c.mask_clk_reg) &
- (uint32_t)~(RADEON_GPIO_A_0 | RADEON_GPIO_A_1));
-
+ RADEONI2CDoLock(output, TRUE);
if (!RADEONInitExtTMDSInfoFromBIOS(output)) {
if (radeon_output->DVOChip) {
switch(info->ext_tmds_chip) {
@@ -316,6 +314,7 @@ RADEONRestoreDVOChip(ScrnInfoPtr pScrn, xf86OutputPtr output)
}
}
}
+ RADEONI2CDoLock(output, FALSE);
}
#if 0
@@ -727,14 +726,6 @@ RADEONEnableDisplay(xf86OutputPtr output, BOOL bEnable)
save->crtc2_gen_cntl |= RADEON_CRTC2_CRT2_ON;
}
tv_dac_change = 1;
- /* IGP chips seem to use a mix of Primary and TVDAC controls */
- if (info->IsIGP) {
- tmp = INREG(RADEON_CRTC_EXT_CNTL);
- tmp |= RADEON_CRTC_CRT_ON;
- OUTREG(RADEON_CRTC_EXT_CNTL, tmp);
- save->crtc_ext_cntl |= RADEON_CRTC_CRT_ON;
- RADEONDacPowerSet(pScrn, bEnable, TRUE);
- }
}
} else if (radeon_output->MonType == MT_DFP) {
if (radeon_output->TMDSType == TMDS_INT) {
@@ -815,14 +806,6 @@ RADEONEnableDisplay(xf86OutputPtr output, BOOL bEnable)
save->crtc2_gen_cntl &= ~RADEON_CRTC2_CRT2_ON;
}
}
- /* IGP chips seem to use a mix of Primary and TVDAC controls */
- if (info->IsIGP) {
- tmp = INREG(RADEON_CRTC_EXT_CNTL);
- tmp &= ~RADEON_CRTC_CRT_ON;
- OUTREG(RADEON_CRTC_EXT_CNTL, tmp);
- save->crtc_ext_cntl &= ~RADEON_CRTC_CRT_ON;
- RADEONDacPowerSet(pScrn, bEnable, TRUE);
- }
}
} else if (radeon_output->MonType == MT_DFP) {
if (radeon_output->TMDSType == TMDS_INT) {
@@ -1033,9 +1016,14 @@ RADEONInitFP2Registers(xf86OutputPtr output, RADEONSavePtr save,
RADEON_FP2_DVO_RATE_SEL_SDR);
- /* XXX: these may be oem specific */
+ /* XXX: these are oem specific */
if (IS_R300_VARIANT) {
- save->fp2_gen_cntl |= RADEON_FP2_PAD_FLOP_EN | R300_FP2_DVO_CLOCK_MODE_SINGLE;
+ if ((info->Chipset == PCI_CHIP_RV350_NP) &&
+ (PCI_SUB_VENDOR_ID(info->PciInfo) == 0x1028) &&
+ (PCI_SUB_DEVICE_ID(info->PciInfo) == 0x2001))
+ save->fp2_gen_cntl |= R300_FP2_DVO_CLOCK_MODE_SINGLE; /* Dell Inspiron 8600 */
+ else
+ save->fp2_gen_cntl |= RADEON_FP2_PAD_FLOP_EN | R300_FP2_DVO_CLOCK_MODE_SINGLE;
#if 0
if (mode->Clock > 165000)
save->fp2_gen_cntl |= R300_FP2_DVO_DUAL_CHANNEL_EN;
@@ -1383,7 +1371,6 @@ RADEONInitOutputRegisters(ScrnInfoPtr pScrn, RADEONSavePtr save,
{
Bool IsPrimary = crtc_num == 0 ? TRUE : FALSE;
RADEONOutputPrivatePtr radeon_output = output->driver_private;
- RADEONInfoPtr info = RADEONPTR(pScrn);
if (crtc_num == 0)
RADEONInitRMXRegisters(output, save, mode);
@@ -1393,9 +1380,6 @@ RADEONInitOutputRegisters(ScrnInfoPtr pScrn, RADEONSavePtr save,
RADEONInitDACRegisters(output, save, mode, IsPrimary);
} else {
RADEONInitDAC2Registers(output, save, mode, IsPrimary);
- /* IGP chips seem to use a mix of primary and TVDAC controls */
- if (info->IsIGP)
- RADEONInitDACRegisters(output, save, mode, IsPrimary);
}
} else if (radeon_output->MonType == MT_LCD) {
RADEONInitLVDSRegisters(output, save, mode, IsPrimary);
@@ -1456,8 +1440,8 @@ legacy_output_mode_set(xf86OutputPtr output, DisplayModePtr mode,
}
OUTREG(RADEON_FP2_GEN_CNTL, fp2_gen_cntl);
} else {
- RADEONRestoreDVOChip(pScrn, output);
RADEONRestoreFP2Registers(pScrn, info->ModeReg);
+ RADEONRestoreDVOChip(pScrn, output);
}
}
break;
diff --git a/src/pcidb/ati_pciids.csv b/src/pcidb/ati_pciids.csv
index 1f6fa82..364f4e1 100644
--- a/src/pcidb/ati_pciids.csv
+++ b/src/pcidb/ati_pciids.csv
@@ -1,5 +1,6 @@
"#pciid","define","family","mobility","igp","nocrtc2","Nointtvout","singledac","name"
"0x3150","RV380_3150","RV380",1,,,,,"ATI Radeon Mobility X600 (M24) 3150 (PCIE)"
+"0x3151","RV380_3151","RV380",,,,,,"ATI FireMV 2400 (PCI)"
"0x3152","RV380_3152","RV380",1,,,,,"ATI Radeon Mobility X300 (M24) 3152 (PCIE)"
"0x3154","RV380_3154","RV380",1,,,,,"ATI FireGL M24 GL 3154 (PCIE)"
"0x3E50","RV380_3E50","RV380",,,,,,"ATI Radeon X600 (RV380) 3E50 (PCIE)"
@@ -331,6 +332,8 @@
"0x940A","R600_940A","R600",,,,,,"ATI FireGL V8650"
"0x940B","R600_940B","R600",,,,,,"ATI FireGL V8600"
"0x940F","R600_940F","R600",,,,,,"ATI FireGL V7600"
+"0x9440","RV770_9440","RV770",,,,,,"ATI Radeon 4800 Series"
+"0x9442","RV770_9442","RV770",,,,,,"ATI Radeon 4800 Series"
"0x94C0","RV610_94C0","RV610",,,,,,"ATI RV610"
"0x94C1","RV610_94C1","RV610",,,,,,"ATI Radeon HD 2400 XT"
"0x94C3","RV610_94C3","RV610",,,,,,"ATI Radeon HD 2400 Pro"
@@ -348,6 +351,7 @@
"0x9507","RV670_9507","RV670",,,,,,"ATI RV670"
"0x950F","RV670_950F","RV670",,,,,,"ATI Radeon HD3870 X2"
"0x9511","RV670_9511","RV670",,,,,,"ATI FireGL V7700"
+"0x9515","RV670_9515","RV670",,,,,,"ATI Radeon HD3850"
"0x9580","RV630_9580","RV630",,,,,,"ATI RV630"
"0x9581","RV630_9581","RV630",1,,,,,"ATI Mobility Radeon HD 2600"
"0x9583","RV630_9583","RV630",1,,,,,"ATI Mobility Radeon HD 2600 XT"
diff --git a/src/radeon.h b/src/radeon.h
index 4f77c3b..63655b8 100644
--- a/src/radeon.h
+++ b/src/radeon.h
@@ -98,6 +98,36 @@
#define MIN(a,b) ((a)>(b)?(b):(a))
#endif
+#if HAVE_BYTESWAP_H
+#include <byteswap.h>
+#elif defined(USE_SYS_ENDIAN_H)
+#include <sys/endian.h>
+#else
+#define bswap_16(value) \
+ ((((value) & 0xff) << 8) | ((value) >> 8))
+
+#define bswap_32(value) \
+ (((uint32_t)bswap_16((uint16_t)((value) & 0xffff)) << 16) | \
+ (uint32_t)bswap_16((uint16_t)((value) >> 16)))
+
+#define bswap_64(value) \
+ (((uint64_t)bswap_32((uint32_t)((value) & 0xffffffff)) \
+ << 32) | \
+ (uint64_t)bswap_32((uint32_t)((value) >> 32)))
+#endif
+
+#if X_BYTE_ORDER == X_BIG_ENDIAN
+#define le32_to_cpu(x) bswap_32(x)
+#define le16_to_cpu(x) bswap_16(x)
+#define cpu_to_le32(x) bswap_32(x)
+#define cpu_to_le16(x) bswap_16(x)
+#else
+#define le32_to_cpu(x) (x)
+#define le16_to_cpu(x) (x)
+#define cpu_to_le32(x) (x)
+#define cpu_to_le16(x) (x)
+#endif
+
/* Provide substitutes for gcc's __FUNCTION__ on other compilers */
#if !defined(__GNUC__) && !defined(__FUNCTION__)
# define __FUNCTION__ __func__ /* C99 */
@@ -287,6 +317,7 @@ typedef enum {
CHIP_FAMILY_RV620,
CHIP_FAMILY_RV635,
CHIP_FAMILY_RS780,
+ CHIP_FAMILY_RV770,
CHIP_FAMILY_LAST
} RADEONChipFamily;
@@ -567,7 +598,6 @@ typedef struct {
Bool CPRuns; /* CP is running */
Bool CPInUse; /* CP has been used by X server */
Bool CPStarted; /* CP has started */
- int CPMode; /* CP mode that server/clients use */
int CPFifoSize; /* Size of the CP command FIFO */
int CPusecTimeout; /* CP timeout in usecs */
Bool needCacheFlush;
@@ -787,7 +817,6 @@ do { \
extern void legacy_crtc_dpms(xf86CrtcPtr crtc, int mode);
extern void legacy_crtc_mode_set(xf86CrtcPtr crtc, DisplayModePtr mode,
DisplayModePtr adjusted_mode, int x, int y);
-extern void RADEONInitDispBandwidth(ScrnInfoPtr pScrn);
extern void RADEONRestoreCommonRegisters(ScrnInfoPtr pScrn,
RADEONSavePtr restore);
extern void RADEONRestoreCrtcRegisters(ScrnInfoPtr pScrn,
@@ -872,6 +901,7 @@ extern Bool RADEONGetTMDSInfoFromBIOS(xf86OutputPtr output);
extern Bool RADEONGetTVInfoFromBIOS(xf86OutputPtr output);
extern Bool RADEONInitExtTMDSInfoFromBIOS (xf86OutputPtr output);
extern Bool RADEONPostCardFromBIOSTables(ScrnInfoPtr pScrn);
+extern Bool radeon_card_posted(ScrnInfoPtr pScrn);
/* radeon_commonfuncs.c */
#ifdef XF86DRI
@@ -894,6 +924,7 @@ extern DisplayModePtr RADEONCrtcFindClosestMode(xf86CrtcPtr crtc,
DisplayModePtr pMode);
extern void RADEONUnblank(ScrnInfoPtr pScrn);
extern Bool RADEONSetTiling(ScrnInfoPtr pScrn);
+extern void RADEONInitDispBandwidth(ScrnInfoPtr pScrn);
/* radeon_cursor.c */
extern Bool RADEONCursorInit(ScreenPtr pScreen);
@@ -983,6 +1014,8 @@ extern void RADEONPrintPortMap(ScrnInfoPtr pScrn);
extern void RADEONSetOutputType(ScrnInfoPtr pScrn,
RADEONOutputPrivatePtr radeon_output);
extern Bool RADEONSetupConnectors(ScrnInfoPtr pScrn);
+extern Bool RADEONI2CDoLock(xf86OutputPtr output, Bool lock_state);
+
/* radeon_tv.c */
extern void RADEONSaveTVRegisters(ScrnInfoPtr pScrn, RADEONSavePtr save);
@@ -1046,13 +1079,11 @@ do { \
#define RADEONCP_RESET(pScrn, info) \
do { \
- if (RADEONCP_USE_RING_BUFFER(info->CPMode)) { \
int _ret = drmCommandNone(info->drmFD, DRM_RADEON_CP_RESET); \
if (_ret) { \
xf86DrvMsg(pScrn->scrnIndex, X_ERROR, \
"%s: CP reset %d\n", __FUNCTION__, _ret); \
} \
- } \
} while (0)
#define RADEONCP_REFRESH(pScrn, info) \
diff --git a/src/radeon_accel.c b/src/radeon_accel.c
index 65ad33d..91f463a 100644
--- a/src/radeon_accel.c
+++ b/src/radeon_accel.c
@@ -1046,18 +1046,6 @@ RADEONSetupMemXAA_DRI(int scrnIndex, ScreenPtr pScreen)
depthSize = ((((pScrn->virtualY + 15) & ~15) * info->depthPitch
* depthCpp + RADEON_BUFFER_ALIGN) & ~RADEON_BUFFER_ALIGN);
- switch (info->CPMode) {
- case RADEON_DEFAULT_CP_PIO_MODE:
- xf86DrvMsg(pScrn->scrnIndex, X_INFO, "CP in PIO mode\n");
- break;
- case RADEON_DEFAULT_CP_BM_MODE:
- xf86DrvMsg(pScrn->scrnIndex, X_INFO, "CP in BM mode\n");
- break;
- default:
- xf86DrvMsg(pScrn->scrnIndex, X_INFO, "CP in UNKNOWN mode\n");
- break;
- }
-
xf86DrvMsg(pScrn->scrnIndex, X_INFO,
"Using %d MB GART aperture\n", info->gartSize);
xf86DrvMsg(pScrn->scrnIndex, X_INFO,
diff --git a/src/radeon_atombios.c b/src/radeon_atombios.c
index 20aa722..f0a3a31 100644
--- a/src/radeon_atombios.c
+++ b/src/radeon_atombios.c
@@ -501,11 +501,11 @@ rhdAtomASICInit(atomBiosHandlePtr handle)
RHDAtomBiosFunc(handle->scrnIndex, handle,
GET_DEFAULT_ENGINE_CLOCK,
&data);
- asicInit.sASICInitClocks.ulDefaultEngineClock = data.val / 10;/*in 10 Khz*/
+ asicInit.sASICInitClocks.ulDefaultEngineClock = cpu_to_le32(data.val / 10);/*in 10 Khz*/
RHDAtomBiosFunc(handle->scrnIndex, handle,
GET_DEFAULT_MEMORY_CLOCK,
&data);
- asicInit.sASICInitClocks.ulDefaultMemoryClock = data.val / 10;/*in 10 Khz*/
+ asicInit.sASICInitClocks.ulDefaultMemoryClock = cpu_to_le32(data.val / 10);/*in 10 Khz*/
data.exec.dataSpace = NULL;
data.exec.index = 0x0;
data.exec.pspace = &asicInit;
@@ -609,17 +609,6 @@ rhdAtomInit(atomBiosHandlePtr unused1, AtomBiosRequestID unused2,
#endif
handle->BIOSImageSize = BIOSImageSize;
-# if ATOM_BIOS_PARSER
- /* Try to find out if BIOS has been posted (either by system or int10 */
- if (!rhdAtomGetFbBaseAndSize(handle, NULL, NULL)) {
- /* run AsicInit */
- if (!rhdAtomASICInit(handle))
- xf86DrvMsg(scrnIndex, X_WARNING,
- "%s: AsicInit failed. Won't be able to obtain in VRAM "
- "FB scratch space\n",__func__);
- }
-# endif
-
data->atomhandle = handle;
return ATOM_SUCCESS;
@@ -654,12 +643,18 @@ rhdAtomVramInfoQuery(atomBiosHandlePtr handle, AtomBiosRequestID func,
switch (func) {
case GET_FW_FB_START:
- *val = le32_to_cpu(atomDataPtr->VRAM_UsageByFirmware
- ->asFirmwareVramReserveInfo[0].ulStartAddrUsedByFirmware);
+ if (atomDataPtr->VRAM_UsageByFirmware)
+ *val = le32_to_cpu(atomDataPtr->VRAM_UsageByFirmware
+ ->asFirmwareVramReserveInfo[0].ulStartAddrUsedByFirmware);
+ else
+ return ATOM_NOT_IMPLEMENTED;
break;
case GET_FW_FB_SIZE:
- *val = le16_to_cpu(atomDataPtr->VRAM_UsageByFirmware
- ->asFirmwareVramReserveInfo[0].usFirmwareUseInKb);
+ if (atomDataPtr->VRAM_UsageByFirmware)
+ *val = le16_to_cpu(atomDataPtr->VRAM_UsageByFirmware
+ ->asFirmwareVramReserveInfo[0].usFirmwareUseInKb);
+ else
+ return ATOM_NOT_IMPLEMENTED;
break;
default:
return ATOM_NOT_IMPLEMENTED;
@@ -1391,36 +1386,6 @@ const int object_connector_convert[] =
CONNECTOR_DISPLAY_PORT,
};
-static void
-rhdAtomParseI2CRecord(atomBiosHandlePtr handle,
- ATOM_I2C_RECORD *Record, int *ddc_line)
-{
- ErrorF(" %s: I2C Record: %s[%x] EngineID: %x I2CAddr: %x\n",
- __func__,
- Record->sucI2cId.bfHW_Capable ? "HW_Line" : "GPIO_ID",
- Record->sucI2cId.bfI2C_LineMux,
- Record->sucI2cId.bfHW_EngineID,
- Record->ucI2CAddr);
-
- if (!*(unsigned char *)&(Record->sucI2cId))
- *ddc_line = 0;
- else {
- if (Record->ucI2CAddr != 0)
- return;
-
- if (Record->sucI2cId.bfHW_Capable) {
- switch(Record->sucI2cId.bfI2C_LineMux) {
- case 0: *ddc_line = 0x7e40; break;
- case 1: *ddc_line = 0x7e50; break;
- case 2: *ddc_line = 0x7e30; break;
- default: break;
- }
- return;
- } else {
- /* add GPIO pin parsing */
- }
- }
-}
static RADEONI2CBusRec
RADEONLookupGPIOLineForDDC(ScrnInfoPtr pScrn, uint8_t id)
@@ -1450,12 +1415,16 @@ RADEONLookupGPIOLineForDDC(ScrnInfoPtr pScrn, uint8_t id)
i2c.put_data_reg = le16_to_cpu(gpio.usDataEnRegisterIndex) * 4;
i2c.get_clk_reg = le16_to_cpu(gpio.usClkY_RegisterIndex) * 4;
i2c.get_data_reg = le16_to_cpu(gpio.usDataY_RegisterIndex) * 4;
+ i2c.a_clk_reg = le16_to_cpu(gpio.usClkA_RegisterIndex) * 4;
+ i2c.a_data_reg = le16_to_cpu(gpio.usDataA_RegisterIndex) * 4;
i2c.mask_clk_mask = (1 << gpio.ucClkMaskShift);
i2c.mask_data_mask = (1 << gpio.ucDataMaskShift);
i2c.put_clk_mask = (1 << gpio.ucClkEnShift);
i2c.put_data_mask = (1 << gpio.ucDataEnShift);
i2c.get_clk_mask = (1 << gpio.ucClkY_Shift);
i2c.get_data_mask = (1 << gpio.ucDataY_Shift);
+ i2c.a_clk_mask = (1 << gpio.ucClkA_Shift);
+ i2c.a_data_mask = (1 << gpio.ucDataA_Shift);
i2c.valid = TRUE;
#if 0
@@ -1465,21 +1434,28 @@ RADEONLookupGPIOLineForDDC(ScrnInfoPtr pScrn, uint8_t id)
ErrorF("put_data_reg: 0x%x\n", gpio.usDataEnRegisterIndex * 4);
ErrorF("get_clk_reg: 0x%x\n", gpio.usClkY_RegisterIndex * 4);
ErrorF("get_data_reg: 0x%x\n", gpio.usDataY_RegisterIndex * 4);
- ErrorF("other_clk_reg: 0x%x\n", gpio.usClkA_RegisterIndex * 4);
- ErrorF("other_data_reg: 0x%x\n", gpio.usDataA_RegisterIndex * 4);
+ ErrorF("a_clk_reg: 0x%x\n", gpio.usClkA_RegisterIndex * 4);
+ ErrorF("a_data_reg: 0x%x\n", gpio.usDataA_RegisterIndex * 4);
ErrorF("mask_clk_mask: %d\n", gpio.ucClkMaskShift);
ErrorF("mask_data_mask: %d\n", gpio.ucDataMaskShift);
ErrorF("put_clk_mask: %d\n", gpio.ucClkEnShift);
ErrorF("put_data_mask: %d\n", gpio.ucDataEnShift);
ErrorF("get_clk_mask: %d\n", gpio.ucClkY_Shift);
ErrorF("get_data_mask: %d\n", gpio.ucDataY_Shift);
- ErrorF("other_clk_mask: %d\n", gpio.ucClkA_Shift);
- ErrorF("other_data_mask: %d\n", gpio.ucDataA_Shift);
+ ErrorF("a_clk_mask: %d\n", gpio.ucClkA_Shift);
+ ErrorF("a_data_mask: %d\n", gpio.ucDataA_Shift);
#endif
return i2c;
}
+static RADEONI2CBusRec
+rhdAtomParseI2CRecord(ScrnInfoPtr pScrn, atomBiosHandlePtr handle,
+ ATOM_I2C_RECORD *Record)
+{
+ return RADEONLookupGPIOLineForDDC(pScrn, Record->sucI2cId.bfI2C_LineMux);
+}
+
Bool
RADEONGetATOMConnectorInfoFromBIOSObject (ScrnInfoPtr pScrn)
{
@@ -1489,7 +1465,7 @@ RADEONGetATOMConnectorInfoFromBIOSObject (ScrnInfoPtr pScrn)
atomDataTablesPtr atomDataPtr;
ATOM_CONNECTOR_OBJECT_TABLE *con_obj;
ATOM_INTEGRATED_SYSTEM_INFO_V2 *igp_obj = NULL;
- int i, j, ddc_line = 0;
+ int i, j;
atomDataPtr = info->atomBIOS->atomDataPtr;
if (!rhdAtomGetTableRevisionAndSize((ATOM_COMMON_TABLE_HEADER *)(atomDataPtr->Object_Header), &crev, &frev, &size))
@@ -1617,10 +1593,8 @@ RADEONGetATOMConnectorInfoFromBIOSObject (ScrnInfoPtr pScrn)
ErrorF("record type %d\n", Record->ucRecordType);
switch (Record->ucRecordType) {
case ATOM_I2C_RECORD_TYPE:
- rhdAtomParseI2CRecord(info->atomBIOS,
- (ATOM_I2C_RECORD *)Record,
- &ddc_line);
- info->BiosConnector[i].ddc_i2c = atom_setup_i2c_bus(ddc_line);
+ info->BiosConnector[i].ddc_i2c = rhdAtomParseI2CRecord(pScrn, info->atomBIOS,
+ (ATOM_I2C_RECORD *)Record);
break;
case ATOM_HPD_INT_RECORD_TYPE:
break;
@@ -1751,6 +1725,15 @@ static void RADEONApplyATOMQuirks(ScrnInfoPtr pScrn, int index)
}
}
+ /* Falcon NW laptop lists vga ddc line for LVDS */
+ if ((info->Chipset == PCI_CHIP_RV410_5653) &&
+ (PCI_SUB_VENDOR_ID(info->PciInfo) == 0x1462) &&
+ (PCI_SUB_DEVICE_ID(info->PciInfo) == 0x0291)) {
+ if (info->BiosConnector[index].ConnectorType == CONNECTOR_LVDS) {
+ info->BiosConnector[index].ddc_i2c.valid = FALSE;
+ }
+ }
+
}
Bool
@@ -2027,9 +2010,12 @@ RHDAtomBiosFunc(int scrnIndex, atomBiosHandlePtr handle,
VOID*
CailAllocateMemory(VOID *CAIL,UINT16 size)
{
+ void *ret;
CAILFUNC(CAIL);
- return malloc(size);
+ ret = malloc(size);
+ memset(ret, 0, size);
+ return ret;
}
VOID
@@ -2256,4 +2242,15 @@ atombios_get_command_table_version(atomBiosHandlePtr atomBIOS, int index, int *m
}
+UINT16 ATOM_BSWAP16(UINT16 x)
+{
+ return bswap_16(x);
+}
+
+UINT32 ATOM_BSWAP32(UINT32 x)
+{
+ return bswap_32(x);
+}
+
+
#endif /* ATOM_BIOS */
diff --git a/src/radeon_atomwrapper.c b/src/radeon_atomwrapper.c
index 3e7ae01..bed1471 100644
--- a/src/radeon_atomwrapper.c
+++ b/src/radeon_atomwrapper.c
@@ -31,6 +31,7 @@
#define INT32 INT32
#include "CD_Common_Types.h"
+#include "atombios.h"
#include "CD_Definitions.h"
diff --git a/src/radeon_bios.c b/src/radeon_bios.c
index 529dda7..b34a421 100644
--- a/src/radeon_bios.c
+++ b/src/radeon_bios.c
@@ -266,6 +266,26 @@ radeon_read_unposted_bios(ScrnInfoPtr pScrn)
return ret;
}
+Bool
+radeon_card_posted(ScrnInfoPtr pScrn)
+{
+ RADEONInfoPtr info = RADEONPTR(pScrn);
+ unsigned char *RADEONMMIO = info->MMIO;
+ uint32_t reg;
+
+ if (IS_AVIVO_VARIANT) {
+ reg = INREG(AVIVO_D1CRTC_CONTROL) | INREG(AVIVO_D2CRTC_CONTROL);
+ if (reg & AVIVO_CRTC_EN)
+ return TRUE;
+ } else {
+ reg = INREG(RADEON_CRTC_GEN_CNTL) | INREG(RADEON_CRTC2_GEN_CNTL);
+ if (reg & RADEON_CRTC_EN)
+ return TRUE;
+ }
+
+ return FALSE;
+}
+
/* Read the Video BIOS block and the FP registers (if applicable). */
Bool
RADEONGetBIOSInfo(ScrnInfoPtr pScrn, xf86Int10InfoPtr pInt10)
@@ -273,6 +293,7 @@ RADEONGetBIOSInfo(ScrnInfoPtr pScrn, xf86Int10InfoPtr pInt10)
RADEONInfoPtr info = RADEONPTR(pScrn);
int tmp;
unsigned short dptr;
+ Bool posted = TRUE;
#ifdef XSERVER_LIBPCIACCESS
int size = info->PciInfo->rom_size > RADEON_VBIOS_SIZE ? info->PciInfo->rom_size : RADEON_VBIOS_SIZE;
@@ -291,6 +312,7 @@ RADEONGetBIOSInfo(ScrnInfoPtr pScrn, xf86Int10InfoPtr pInt10)
RADEON_VBIOS_SIZE);
} else if (!radeon_read_bios(pScrn)) {
(void)radeon_read_unposted_bios(pScrn);
+ posted = FALSE;
}
}
@@ -326,7 +348,7 @@ RADEONGetBIOSInfo(ScrnInfoPtr pScrn, xf86Int10InfoPtr pInt10)
info->VBIOS = NULL;
return FALSE;
}
-
+
tmp = info->ROMHeaderStart + 4;
if ((RADEON_BIOS8(tmp) == 'A' &&
RADEON_BIOS8(tmp+1) == 'T' &&
@@ -344,51 +366,65 @@ RADEONGetBIOSInfo(ScrnInfoPtr pScrn, xf86Int10InfoPtr pInt10)
info->IsAtomBios ? "ATOM":"Legacy");
if (info->IsAtomBios) {
- AtomBiosArgRec atomBiosArg;
+ AtomBiosArgRec atomBiosArg;
- if (RHDAtomBiosFunc(pScrn->scrnIndex, NULL, ATOMBIOS_INIT, &atomBiosArg)
- == ATOM_SUCCESS) {
- info->atomBIOS = atomBiosArg.atomhandle;
- }
+ if (RHDAtomBiosFunc(pScrn->scrnIndex, NULL, ATOMBIOS_INIT, &atomBiosArg)
+ == ATOM_SUCCESS) {
+ info->atomBIOS = atomBiosArg.atomhandle;
+ }
- atomBiosArg.fb.start = info->FbFreeStart;
- atomBiosArg.fb.size = info->FbFreeSize;
- if (RHDAtomBiosFunc(pScrn->scrnIndex, info->atomBIOS, ATOMBIOS_ALLOCATE_FB_SCRATCH,
+ atomBiosArg.fb.start = info->FbFreeStart;
+ atomBiosArg.fb.size = info->FbFreeSize;
+ if (RHDAtomBiosFunc(pScrn->scrnIndex, info->atomBIOS, ATOMBIOS_ALLOCATE_FB_SCRATCH,
&atomBiosArg) == ATOM_SUCCESS) {
info->FbFreeStart = atomBiosArg.fb.start;
info->FbFreeSize = atomBiosArg.fb.size;
- }
-
- RHDAtomBiosFunc(pScrn->scrnIndex, info->atomBIOS, GET_DEFAULT_ENGINE_CLOCK,
- &atomBiosArg);
- RHDAtomBiosFunc(pScrn->scrnIndex, info->atomBIOS, GET_DEFAULT_MEMORY_CLOCK,
- &atomBiosArg);
- RHDAtomBiosFunc(pScrn->scrnIndex, info->atomBIOS,
- GET_MAX_PIXEL_CLOCK_PLL_OUTPUT, &atomBiosArg);
- RHDAtomBiosFunc(pScrn->scrnIndex, info->atomBIOS,
- GET_MIN_PIXEL_CLOCK_PLL_OUTPUT, &atomBiosArg);
- RHDAtomBiosFunc(pScrn->scrnIndex, info->atomBIOS,
- GET_MAX_PIXEL_CLOCK_PLL_INPUT, &atomBiosArg);
- RHDAtomBiosFunc(pScrn->scrnIndex, info->atomBIOS,
+ }
+
+ RHDAtomBiosFunc(pScrn->scrnIndex, info->atomBIOS, GET_DEFAULT_ENGINE_CLOCK,
+ &atomBiosArg);
+ RHDAtomBiosFunc(pScrn->scrnIndex, info->atomBIOS, GET_DEFAULT_MEMORY_CLOCK,
+ &atomBiosArg);
+ RHDAtomBiosFunc(pScrn->scrnIndex, info->atomBIOS,
+ GET_MAX_PIXEL_CLOCK_PLL_OUTPUT, &atomBiosArg);
+ RHDAtomBiosFunc(pScrn->scrnIndex, info->atomBIOS,
+ GET_MIN_PIXEL_CLOCK_PLL_OUTPUT, &atomBiosArg);
+ RHDAtomBiosFunc(pScrn->scrnIndex, info->atomBIOS,
+ GET_MAX_PIXEL_CLOCK_PLL_INPUT, &atomBiosArg);
+ RHDAtomBiosFunc(pScrn->scrnIndex, info->atomBIOS,
GET_MIN_PIXEL_CLOCK_PLL_INPUT, &atomBiosArg);
- RHDAtomBiosFunc(pScrn->scrnIndex, info->atomBIOS,
+ RHDAtomBiosFunc(pScrn->scrnIndex, info->atomBIOS,
GET_MAX_PIXEL_CLK, &atomBiosArg);
- RHDAtomBiosFunc(pScrn->scrnIndex, info->atomBIOS,
- GET_REF_CLOCK, &atomBiosArg);
+ RHDAtomBiosFunc(pScrn->scrnIndex, info->atomBIOS,
+ GET_REF_CLOCK, &atomBiosArg);
info->MasterDataStart = RADEON_BIOS16 (info->ROMHeaderStart + 32);
}
+
+ /* We are a bit too quick at using this "unposted" to re-post the
+ * card. This causes some problems with VT switch on some machines,
+ * so let's work around this for now by only POSTing if none of the
+ * CRTCs are enabled
+ */
+ if ((!posted) && info->VBIOS) {
+ posted = radeon_card_posted(pScrn);
+ }
+
+ if ((!posted) && info->VBIOS) {
+ if (info->IsAtomBios) {
+ if (!rhdAtomASICInit(info->atomBIOS))
+ xf86DrvMsg(pScrn->scrnIndex, X_WARNING,
+ "%s: AsicInit failed.\n",__func__);
+ } else {
#if 0
- else {
- /* non-primary card may need posting */
- if (!pInt10) {
- xf86DrvMsg(pScrn->scrnIndex, X_INFO, "Attempting to POST via BIOS tables\n");
+ xf86DrvMsg(pScrn->scrnIndex, X_INFO, "Attempting to POST via legacy BIOS tables\n");
RADEONGetBIOSInitTableOffsets(pScrn);
RADEONPostCardFromBIOSTables(pScrn);
+#endif
}
}
-#endif
+
return TRUE;
}
@@ -397,7 +433,7 @@ static Bool RADEONGetATOMConnectorInfoFromBIOS (ScrnInfoPtr pScrn)
RADEONInfoPtr info = RADEONPTR (pScrn);
if (!info->VBIOS) return FALSE;
-
+
if (RADEONGetATOMConnectorInfoFromBIOSObject(pScrn))
return TRUE;
@@ -411,28 +447,41 @@ static void RADEONApplyLegacyQuirks(ScrnInfoPtr pScrn, int index)
{
RADEONInfoPtr info = RADEONPTR (pScrn);
- /* on XPRESS chips, CRT2_DDC and MONID_DCC both use the
- * MONID gpio, but use different pins.
- * CRT2_DDC uses the standard pinout, MONID_DDC uses
- * something else.
+ /* For RS300/RS350/RS400 chips, there is no primary DAC. Force VGA port to use TVDAC
+ * Also there is no internal TMDS
*/
+ if ((info->ChipFamily == CHIP_FAMILY_RS300) ||
+ (info->ChipFamily == CHIP_FAMILY_RS400) ||
+ (info->ChipFamily == CHIP_FAMILY_RS480)) {
+ info->BiosConnector[index].DACType = DAC_TVDAC;
+ info->BiosConnector[index].TMDSType = TMDS_EXT;
+ }
+
+ /* XPRESS DDC quirks */
if ((info->ChipFamily == CHIP_FAMILY_RS400 ||
info->ChipFamily == CHIP_FAMILY_RS480) &&
- info->BiosConnector[index].ConnectorType == CONNECTOR_VGA &&
info->BiosConnector[index].ddc_i2c.mask_clk_reg == RADEON_GPIO_CRT2_DDC) {
info->BiosConnector[index].ddc_i2c = legacy_setup_i2c_bus(RADEON_GPIO_MONID);
- }
-
- /* XPRESS desktop chips seem to have a proprietary connector listed for
- * DVI-D, try and do the right thing here.
- */
- if ((!info->IsMobility) &&
- (info->BiosConnector[index].ConnectorType == CONNECTOR_LVDS)) {
- xf86DrvMsg(pScrn->scrnIndex, X_WARNING,
- "Proprietary connector found, assuming DVI-D\n");
- info->BiosConnector[index].DACType = DAC_NONE;
- info->BiosConnector[index].TMDSType = TMDS_EXT;
- info->BiosConnector[index].ConnectorType = CONNECTOR_DVI_D;
+ } else if ((info->ChipFamily == CHIP_FAMILY_RS400 ||
+ info->ChipFamily == CHIP_FAMILY_RS480) &&
+ info->BiosConnector[index].ddc_i2c.mask_clk_reg == RADEON_GPIO_MONID) {
+ info->BiosConnector[index].ddc_i2c.valid = TRUE;
+ info->BiosConnector[index].ddc_i2c.mask_clk_mask = (0x20 << 8);
+ info->BiosConnector[index].ddc_i2c.mask_data_mask = 0x80;
+ info->BiosConnector[index].ddc_i2c.a_clk_mask = (0x20 << 8);
+ info->BiosConnector[index].ddc_i2c.a_data_mask = 0x80;
+ info->BiosConnector[index].ddc_i2c.put_clk_mask = (0x20 << 8);
+ info->BiosConnector[index].ddc_i2c.put_data_mask = 0x80;
+ info->BiosConnector[index].ddc_i2c.get_clk_mask = (0x20 << 8);
+ info->BiosConnector[index].ddc_i2c.get_data_mask = 0x80;
+ info->BiosConnector[index].ddc_i2c.mask_clk_reg = RADEON_GPIOPAD_MASK;
+ info->BiosConnector[index].ddc_i2c.mask_data_reg = RADEON_GPIOPAD_MASK;
+ info->BiosConnector[index].ddc_i2c.a_clk_reg = RADEON_GPIOPAD_A;
+ info->BiosConnector[index].ddc_i2c.a_data_reg = RADEON_GPIOPAD_A;
+ info->BiosConnector[index].ddc_i2c.put_clk_reg = RADEON_GPIOPAD_EN;
+ info->BiosConnector[index].ddc_i2c.put_data_reg = RADEON_GPIOPAD_EN;
+ info->BiosConnector[index].ddc_i2c.get_clk_reg = RADEON_LCD_GPIO_Y_REG;
+ info->BiosConnector[index].ddc_i2c.get_data_reg = RADEON_LCD_GPIO_Y_REG;
}
/* Certain IBM chipset RN50s have a BIOS reporting two VGAs,
@@ -454,6 +503,16 @@ static void RADEONApplyLegacyQuirks(ScrnInfoPtr pScrn, int index)
}
}
+ /* X300 card with extra non-existent DVI port */
+ if (info->Chipset == PCI_CHIP_RV370_5B60 &&
+ PCI_SUB_VENDOR_ID(info->PciInfo) == 0x17af &&
+ PCI_SUB_DEVICE_ID(info->PciInfo) == 0x201e &&
+ index == 2) {
+ if (info->BiosConnector[index].ConnectorType == CONNECTOR_DVI_I) {
+ info->BiosConnector[index].valid = FALSE;
+ }
+ }
+
}
static Bool RADEONGetLegacyConnectorInfoFromBIOS (ScrnInfoPtr pScrn)
@@ -479,7 +538,7 @@ static Bool RADEONGetLegacyConnectorInfoFromBIOS (ScrnInfoPtr pScrn)
ConnectorType = (tmp >> 12) & 0xf;
switch (ConnectorType) {
case CONNECTOR_PROPRIETARY_LEGACY:
- info->BiosConnector[i].ConnectorType = CONNECTOR_LVDS;
+ info->BiosConnector[i].ConnectorType = CONNECTOR_DVI_D;
break;
case CONNECTOR_CRT_LEGACY:
info->BiosConnector[i].ConnectorType = CONNECTOR_VGA;
@@ -528,10 +587,6 @@ static Bool RADEONGetLegacyConnectorInfoFromBIOS (ScrnInfoPtr pScrn)
else
info->BiosConnector[i].DACType = DAC_PRIMARY;
- /* For RS300/RS350/RS400 chips, there is no primary DAC. Force VGA port to use TVDAC*/
- if (info->IsIGP)
- info->BiosConnector[i].DACType = DAC_TVDAC;
-
if ((tmp >> 4) & 0x1)
info->BiosConnector[i].TMDSType = TMDS_EXT;
else
@@ -560,7 +615,10 @@ static Bool RADEONGetLegacyConnectorInfoFromBIOS (ScrnInfoPtr pScrn)
}
/* check LVDS table */
- if (info->IsMobility) {
+ /* RS4xx can be mobile or desktop so check the connectors */
+ if (info->IsMobility ||
+ info->ChipFamily == CHIP_FAMILY_RS400 ||
+ info->ChipFamily == CHIP_FAMILY_RS480) {
offset = RADEON_BIOS16(info->ROMHeaderStart + 0x40);
if (offset) {
info->BiosConnector[4].valid = TRUE;
@@ -591,10 +649,10 @@ static Bool RADEONGetLegacyConnectorInfoFromBIOS (ScrnInfoPtr pScrn)
break;
case DDC_LCD:
info->BiosConnector[4].ddc_i2c = legacy_setup_i2c_bus(RADEON_LCD_GPIO_MASK);
- info->BiosConnector[4].ddc_i2c.mask_clk_mask =
- RADEON_BIOS32(tmp0 + 0x03) | RADEON_BIOS32(tmp0 + 0x07);
- info->BiosConnector[4].ddc_i2c.mask_data_mask =
- RADEON_BIOS32(tmp0 + 0x03) | RADEON_BIOS32(tmp0 + 0x07);
+ info->BiosConnector[4].ddc_i2c.mask_clk_mask = RADEON_BIOS32(tmp0 + 0x03);
+ info->BiosConnector[4].ddc_i2c.mask_data_mask = RADEON_BIOS32(tmp0 + 0x07);
+ info->BiosConnector[4].ddc_i2c.a_clk_mask = RADEON_BIOS32(tmp0 + 0x03);
+ info->BiosConnector[4].ddc_i2c.a_data_mask = RADEON_BIOS32(tmp0 + 0x07);
info->BiosConnector[4].ddc_i2c.put_clk_mask = RADEON_BIOS32(tmp0 + 0x03);
info->BiosConnector[4].ddc_i2c.put_data_mask = RADEON_BIOS32(tmp0 + 0x07);
info->BiosConnector[4].ddc_i2c.get_clk_mask = RADEON_BIOS32(tmp0 + 0x03);
@@ -602,10 +660,10 @@ static Bool RADEONGetLegacyConnectorInfoFromBIOS (ScrnInfoPtr pScrn)
break;
case DDC_GPIO:
info->BiosConnector[4].ddc_i2c = legacy_setup_i2c_bus(RADEON_MDGPIO_EN_REG);
- info->BiosConnector[4].ddc_i2c.mask_clk_mask =
- RADEON_BIOS32(tmp0 + 0x03) | RADEON_BIOS32(tmp0 + 0x07);
- info->BiosConnector[4].ddc_i2c.mask_data_mask =
- RADEON_BIOS32(tmp0 + 0x03) | RADEON_BIOS32(tmp0 + 0x07);
+ info->BiosConnector[4].ddc_i2c.mask_clk_mask = RADEON_BIOS32(tmp0 + 0x03);
+ info->BiosConnector[4].ddc_i2c.mask_data_mask = RADEON_BIOS32(tmp0 + 0x07);
+ info->BiosConnector[4].ddc_i2c.a_clk_mask = RADEON_BIOS32(tmp0 + 0x03);
+ info->BiosConnector[4].ddc_i2c.a_data_mask = RADEON_BIOS32(tmp0 + 0x07);
info->BiosConnector[4].ddc_i2c.put_clk_mask = RADEON_BIOS32(tmp0 + 0x03);
info->BiosConnector[4].ddc_i2c.put_data_mask = RADEON_BIOS32(tmp0 + 0x07);
info->BiosConnector[4].ddc_i2c.get_clk_mask = RADEON_BIOS32(tmp0 + 0x03);
@@ -1118,6 +1176,50 @@ Bool RADEONGetTMDSInfoFromBIOS (xf86OutputPtr output)
return FALSE;
}
+static RADEONI2CBusRec
+RADEONLookupI2CBlock(ScrnInfoPtr pScrn, int id)
+{
+ RADEONInfoPtr info = RADEONPTR (pScrn);
+ int offset, blocks, i;
+ RADEONI2CBusRec i2c;
+
+ memset(&i2c, 0, sizeof(RADEONI2CBusRec));
+ i2c.valid = FALSE;
+
+ offset = RADEON_BIOS16(info->ROMHeaderStart + 0x70);
+ if (offset) {
+ blocks = RADEON_BIOS8(offset + 2);
+ for (i = 0; i < blocks; i++) {
+ int i2c_id = RADEON_BIOS8(offset + 3 + (i * 5) + 0);
+ if (id == i2c_id) {
+ int reg = RADEON_BIOS16(offset + 3 + (i * 5) + 1) * 4;
+ int clock_shift = RADEON_BIOS8(offset + 3 + (i * 5) + 3);
+ int data_shift = RADEON_BIOS8(offset + 3 + (i * 5) + 4);
+
+ i2c.mask_clk_mask = (1 << clock_shift);
+ i2c.mask_data_mask = (1 << data_shift);
+ i2c.a_clk_mask = (1 << clock_shift);
+ i2c.a_data_mask = (1 << data_shift);
+ i2c.put_clk_mask = (1 << clock_shift);
+ i2c.put_data_mask = (1 << data_shift);
+ i2c.get_clk_mask = (1 << clock_shift);
+ i2c.get_data_mask = (1 << data_shift);
+ i2c.mask_clk_reg = reg;
+ i2c.mask_data_reg = reg;
+ i2c.a_clk_reg = reg;
+ i2c.a_data_reg = reg;
+ i2c.put_clk_reg = reg;
+ i2c.put_data_reg = reg;
+ i2c.get_clk_reg = reg;
+ i2c.get_data_reg = reg;
+ i2c.valid = TRUE;
+ break;
+ }
+ }
+ }
+ return i2c;
+}
+
Bool RADEONGetExtTMDSInfoFromBIOS (xf86OutputPtr output)
{
ScrnInfoPtr pScrn = output->scrn;
@@ -1129,6 +1231,52 @@ Bool RADEONGetExtTMDSInfoFromBIOS (xf86OutputPtr output)
if (info->IsAtomBios) {
return FALSE;
+ } else if (info->IsIGP) {
+ /* RS4xx TMDS stuff is in the mobile table */
+ offset = RADEON_BIOS16(info->ROMHeaderStart + 0x42);
+ if (offset) {
+ int rev = RADEON_BIOS8(offset);
+ if (rev >= 6) {
+ offset = RADEON_BIOS16(offset + 0x17);
+ if (offset) {
+ offset = RADEON_BIOS16(offset + 2);
+ rev = RADEON_BIOS8(offset);
+ if (offset && (rev > 1)) {
+ int blocks = RADEON_BIOS8(offset + 3);
+ int index = offset + 4;
+ radeon_output->dvo_i2c.valid = FALSE;
+ while (blocks > 0) {
+ int id = RADEON_BIOS16(index);
+ index += 2;
+ switch (id >> 13) {
+ case 0:
+ index += 6;
+ break;
+ case 2:
+ index += 10;
+ break;
+ case 3:
+ index += 2;
+ break;
+ case 4:
+ index += 2;
+ break;
+ case 6:
+ radeon_output->dvo_i2c_slave_addr =
+ RADEON_BIOS16(index) & 0xff;
+ index += 2;
+ radeon_output->dvo_i2c =
+ RADEONLookupI2CBlock(pScrn, RADEON_BIOS8(index));
+ return TRUE;
+ default:
+ break;
+ }
+ blocks--;
+ }
+ }
+ }
+ }
+ }
} else {
offset = RADEON_BIOS16(info->ROMHeaderStart + 0x58);
if (offset) {
@@ -1148,10 +1296,11 @@ Bool RADEONGetExtTMDSInfoFromBIOS (xf86OutputPtr output)
radeon_output->dvo_i2c = legacy_setup_i2c_bus(RADEON_GPIO_VGA_DDC);
else if (gpio_reg == 4)
radeon_output->dvo_i2c = legacy_setup_i2c_bus(RADEON_GPIO_CRT2_DDC);
- else if (gpio_reg == 5)
+ else if (gpio_reg == 5) {
xf86DrvMsg(pScrn->scrnIndex, X_ERROR,
"unsupported MM gpio_reg\n");
- else {
+ return FALSE;
+ } else {
xf86DrvMsg(pScrn->scrnIndex, X_ERROR,
"Unknown gpio reg: %d\n", gpio_reg);
return FALSE;
@@ -1179,12 +1328,82 @@ Bool RADEONInitExtTMDSInfoFromBIOS (xf86OutputPtr output)
unsigned char *RADEONMMIO = info->MMIO;
RADEONOutputPrivatePtr radeon_output = output->driver_private;
int offset, index, id;
- uint32_t val, reg, andmask, ormask;
+ uint32_t val, reg, and_mask, or_mask;
if (!info->VBIOS) return FALSE;
if (info->IsAtomBios) {
return FALSE;
+ } else if (info->IsIGP) {
+ /* RS4xx TMDS stuff is in the mobile table */
+ offset = RADEON_BIOS16(info->ROMHeaderStart + 0x42);
+ if (offset) {
+ int rev = RADEON_BIOS8(offset);
+ if (rev >= 6) {
+ offset = RADEON_BIOS16(offset + 0x17);
+ if (offset) {
+ offset = RADEON_BIOS16(offset + 2);
+ rev = RADEON_BIOS8(offset);
+ if (offset && (rev > 1)) {
+ int blocks = RADEON_BIOS8(offset + 3);
+ index = offset + 4;
+ while (blocks > 0) {
+ id = RADEON_BIOS16(index);
+ index += 2;
+ switch (id >> 13) {
+ case 0:
+ reg = (id & 0x1fff) * 4;
+ val = RADEON_BIOS32(index);
+ index += 4;
+ ErrorF("MMIO: 0x%x 0x%x\n",
+ (unsigned)reg, (unsigned)val);
+ OUTREG(reg, val);
+ break;
+ case 2:
+ reg = (id & 0x1fff) * 4;
+ and_mask = RADEON_BIOS32(index);
+ index += 4;
+ or_mask = RADEON_BIOS32(index);
+ index += 4;
+ ErrorF("MMIO mask: 0x%x 0x%x 0x%x\n",
+ (unsigned)reg, (unsigned)and_mask, (unsigned)or_mask);
+ val = INREG(reg);
+ val = (val & and_mask) | or_mask;
+ OUTREG(reg, val);
+ break;
+ case 3:
+ val = RADEON_BIOS16(index);
+ index += 2;
+ ErrorF("delay: %u\n", (unsigned)val);
+ usleep(val);
+ break;
+ case 4:
+ val = RADEON_BIOS16(index);
+ index += 2;
+ ErrorF("delay: %u\n", (unsigned)val * 1000);
+ usleep(val * 1000);
+ break;
+ case 6:
+ index++;
+ reg = RADEON_BIOS8(index);
+ index++;
+ val = RADEON_BIOS8(index);
+ index++;
+ ErrorF("i2c write: 0x%x, 0x%x\n", (unsigned)reg,
+ (unsigned)val);
+ RADEONDVOWriteByte(radeon_output->DVOChip, reg, val);
+ break;
+ default:
+ ErrorF("unknown id %d\n", id>>13);
+ return FALSE;
+ }
+ blocks--;
+ }
+ return TRUE;
+ }
+ }
+ }
+ }
} else {
offset = RADEON_BIOS16(info->ROMHeaderStart + 0x58);
if (offset) {
@@ -1194,24 +1413,24 @@ Bool RADEONInitExtTMDSInfoFromBIOS (xf86OutputPtr output)
index += 2;
switch(id >> 13) {
case 0:
- reg = id & 0x1fff;
+ reg = (id & 0x1fff) * 4;
val = RADEON_BIOS32(index);
index += 4;
- ErrorF("WRITE INDEXED: 0x%x 0x%x\n",
+ ErrorF("MMIO: 0x%x 0x%x\n",
(unsigned)reg, (unsigned)val);
- /*OUTREG(reg, val);*/
+ OUTREG(reg, val);
break;
case 2:
- reg = id & 0x1fff;
- andmask = RADEON_BIOS32(index);
+ reg = (id & 0x1fff) * 4;
+ and_mask = RADEON_BIOS32(index);
index += 4;
- ormask = RADEON_BIOS32(index);
+ or_mask = RADEON_BIOS32(index);
index += 4;
val = INREG(reg);
- val = (val & andmask) | ormask;
- ErrorF("MASK DIRECT: 0x%x 0x%x 0x%x\n",
- (unsigned)reg, (unsigned)andmask, (unsigned)ormask);
- /*OUTREG(reg, val);*/
+ val = (val & and_mask) | or_mask;
+ ErrorF("MMIO mask: 0x%x 0x%x 0x%x\n",
+ (unsigned)reg, (unsigned)and_mask, (unsigned)or_mask);
+ OUTREG(reg, val);
break;
case 4:
val = RADEON_BIOS16(index);
@@ -1221,15 +1440,15 @@ Bool RADEONInitExtTMDSInfoFromBIOS (xf86OutputPtr output)
break;
case 5:
reg = id & 0x1fff;
- andmask = RADEON_BIOS32(index);
+ and_mask = RADEON_BIOS32(index);
index += 4;
- ormask = RADEON_BIOS32(index);
+ or_mask = RADEON_BIOS32(index);
index += 4;
- ErrorF("MASK PLL: 0x%x 0x%x 0x%x\n",
- (unsigned)reg, (unsigned)andmask, (unsigned)ormask);
- /*val = INPLL(pScrn, reg);
- val = (val & andmask) | ormask;
- OUTPLL(pScrn, reg, val);*/
+ ErrorF("PLL mask: 0x%x 0x%x 0x%x\n",
+ (unsigned)reg, (unsigned)and_mask, (unsigned)or_mask);
+ val = INPLL(pScrn, reg);
+ val = (val & and_mask) | or_mask;
+ OUTPLL(pScrn, reg, val);
break;
case 6:
reg = id & 0x1fff;
diff --git a/src/radeon_chipinfo_gen.h b/src/radeon_chipinfo_gen.h
index ed3174a..0d7d085 100644
--- a/src/radeon_chipinfo_gen.h
+++ b/src/radeon_chipinfo_gen.h
@@ -1,6 +1,7 @@
/* This file is autogenerated please do not edit */
RADEONCardInfo RADEONCards[] = {
{ 0x3150, CHIP_FAMILY_RV380, 1, 0, 0, 0, 0 },
+ { 0x3151, CHIP_FAMILY_RV380, 0, 0, 0, 0, 0 },
{ 0x3152, CHIP_FAMILY_RV380, 1, 0, 0, 0, 0 },
{ 0x3154, CHIP_FAMILY_RV380, 1, 0, 0, 0, 0 },
{ 0x3E50, CHIP_FAMILY_RV380, 0, 0, 0, 0, 0 },
@@ -250,6 +251,8 @@ RADEONCardInfo RADEONCards[] = {
{ 0x940A, CHIP_FAMILY_R600, 0, 0, 0, 0, 0 },
{ 0x940B, CHIP_FAMILY_R600, 0, 0, 0, 0, 0 },
{ 0x940F, CHIP_FAMILY_R600, 0, 0, 0, 0, 0 },
+ { 0x9440, CHIP_FAMILY_RV770, 0, 0, 0, 0, 0 },
+ { 0x9442, CHIP_FAMILY_RV770, 0, 0, 0, 0, 0 },
{ 0x94C0, CHIP_FAMILY_RV610, 0, 0, 0, 0, 0 },
{ 0x94C1, CHIP_FAMILY_RV610, 0, 0, 0, 0, 0 },
{ 0x94C3, CHIP_FAMILY_RV610, 0, 0, 0, 0, 0 },
@@ -267,6 +270,7 @@ RADEONCardInfo RADEONCards[] = {
{ 0x9507, CHIP_FAMILY_RV670, 0, 0, 0, 0, 0 },
{ 0x950F, CHIP_FAMILY_RV670, 0, 0, 0, 0, 0 },
{ 0x9511, CHIP_FAMILY_RV670, 0, 0, 0, 0, 0 },
+ { 0x9515, CHIP_FAMILY_RV670, 0, 0, 0, 0, 0 },
{ 0x9580, CHIP_FAMILY_RV630, 0, 0, 0, 0, 0 },
{ 0x9581, CHIP_FAMILY_RV630, 1, 0, 0, 0, 0 },
{ 0x9583, CHIP_FAMILY_RV630, 1, 0, 0, 0, 0 },
diff --git a/src/radeon_chipset_gen.h b/src/radeon_chipset_gen.h
index d1761d2..96b60e9 100644
--- a/src/radeon_chipset_gen.h
+++ b/src/radeon_chipset_gen.h
@@ -1,6 +1,7 @@
/* This file is autogenerated please do not edit */
static SymTabRec RADEONChipsets[] = {
{ PCI_CHIP_RV380_3150, "ATI Radeon Mobility X600 (M24) 3150 (PCIE)" },
+ { PCI_CHIP_RV380_3151, "ATI FireMV 2400 (PCI)" },
{ PCI_CHIP_RV380_3152, "ATI Radeon Mobility X300 (M24) 3152 (PCIE)" },
{ PCI_CHIP_RV380_3154, "ATI FireGL M24 GL 3154 (PCIE)" },
{ PCI_CHIP_RV380_3E50, "ATI Radeon X600 (RV380) 3E50 (PCIE)" },
@@ -250,6 +251,8 @@ static SymTabRec RADEONChipsets[] = {
{ PCI_CHIP_R600_940A, "ATI FireGL V8650" },
{ PCI_CHIP_R600_940B, "ATI FireGL V8600" },
{ PCI_CHIP_R600_940F, "ATI FireGL V7600" },
+ { PCI_CHIP_RV770_9440, "ATI Radeon 4800 Series" },
+ { PCI_CHIP_RV770_9442, "ATI Radeon 4800 Series" },
{ PCI_CHIP_RV610_94C0, "ATI RV610" },
{ PCI_CHIP_RV610_94C1, "ATI Radeon HD 2400 XT" },
{ PCI_CHIP_RV610_94C3, "ATI Radeon HD 2400 Pro" },
@@ -267,6 +270,7 @@ static SymTabRec RADEONChipsets[] = {
{ PCI_CHIP_RV670_9507, "ATI RV670" },
{ PCI_CHIP_RV670_950F, "ATI Radeon HD3870 X2" },
{ PCI_CHIP_RV670_9511, "ATI FireGL V7700" },
+ { PCI_CHIP_RV670_9515, "ATI Radeon HD3850" },
{ PCI_CHIP_RV630_9580, "ATI RV630" },
{ PCI_CHIP_RV630_9581, "ATI Mobility Radeon HD 2600" },
{ PCI_CHIP_RV630_9583, "ATI Mobility Radeon HD 2600 XT" },
diff --git a/src/radeon_commonfuncs.c b/src/radeon_commonfuncs.c
index 58fe306..d0c5229 100644
--- a/src/radeon_commonfuncs.c
+++ b/src/radeon_commonfuncs.c
@@ -158,13 +158,14 @@ static void FUNC_NAME(RADEONInit3DEngine)(ScrnInfoPtr pScrn)
if (info->ChipFamily == CHIP_FAMILY_RV515)
vap_cntl |= (2 << R300_PVS_NUM_FPUS_SHIFT);
else if ((info->ChipFamily == CHIP_FAMILY_RV530) ||
- (info->ChipFamily == CHIP_FAMILY_RV560))
+ (info->ChipFamily == CHIP_FAMILY_RV560) ||
+ (info->ChipFamily == CHIP_FAMILY_RV570))
vap_cntl |= (5 << R300_PVS_NUM_FPUS_SHIFT);
- else if (info->ChipFamily == CHIP_FAMILY_R420)
+ else if ((info->ChipFamily == CHIP_FAMILY_RV410) ||
+ (info->ChipFamily == CHIP_FAMILY_R420))
vap_cntl |= (6 << R300_PVS_NUM_FPUS_SHIFT);
else if ((info->ChipFamily == CHIP_FAMILY_R520) ||
- (info->ChipFamily == CHIP_FAMILY_R580) ||
- (info->ChipFamily == CHIP_FAMILY_RV570))
+ (info->ChipFamily == CHIP_FAMILY_R580))
vap_cntl |= (8 << R300_PVS_NUM_FPUS_SHIFT);
else
vap_cntl |= (4 << R300_PVS_NUM_FPUS_SHIFT);
diff --git a/src/radeon_crtc.c b/src/radeon_crtc.c
index c63b650..1316669 100644
--- a/src/radeon_crtc.c
+++ b/src/radeon_crtc.c
@@ -58,6 +58,14 @@ extern void atombios_crtc_mode_set(xf86CrtcPtr crtc,
DisplayModePtr adjusted_mode,
int x, int y);
extern void atombios_crtc_dpms(xf86CrtcPtr crtc, int mode);
+extern void
+RADEONInitDispBandwidthLegacy(ScrnInfoPtr pScrn,
+ DisplayModePtr mode1, int pixel_bytes1,
+ DisplayModePtr mode2, int pixel_bytes2);
+extern void
+RADEONInitDispBandwidthAVIVO(ScrnInfoPtr pScrn,
+ DisplayModePtr mode1, int pixel_bytes1,
+ DisplayModePtr mode2, int pixel_bytes2);
void
radeon_crtc_dpms(xf86CrtcPtr crtc, int mode)
@@ -567,6 +575,43 @@ static const xf86CrtcFuncsRec radeon_crtc_funcs = {
.destroy = NULL, /* XXX */
};
+void
+RADEONInitDispBandwidth(ScrnInfoPtr pScrn)
+{
+ RADEONInfoPtr info = RADEONPTR(pScrn);
+ xf86CrtcConfigPtr xf86_config = XF86_CRTC_CONFIG_PTR(pScrn);
+ DisplayModePtr mode1 = NULL, mode2 = NULL;
+ int pixel_bytes1 = info->CurrentLayout.pixel_bytes;
+ int pixel_bytes2 = info->CurrentLayout.pixel_bytes;
+
+ if (xf86_config->num_crtc == 2) {
+ if (xf86_config->crtc[1]->enabled &&
+ xf86_config->crtc[0]->enabled) {
+ mode1 = &xf86_config->crtc[0]->mode;
+ mode2 = &xf86_config->crtc[1]->mode;
+ } else if (xf86_config->crtc[0]->enabled) {
+ mode1 = &xf86_config->crtc[0]->mode;
+ } else if (xf86_config->crtc[1]->enabled) {
+ mode2 = &xf86_config->crtc[1]->mode;
+ } else
+ return;
+ } else {
+ if (info->IsPrimary)
+ mode1 = &xf86_config->crtc[0]->mode;
+ else if (info->IsSecondary)
+ mode2 = &xf86_config->crtc[0]->mode;
+ else if (xf86_config->crtc[0]->enabled)
+ mode1 = &xf86_config->crtc[0]->mode;
+ else
+ return;
+ }
+
+ if (IS_AVIVO_VARIANT)
+ RADEONInitDispBandwidthAVIVO(pScrn, mode1, pixel_bytes1, mode2, pixel_bytes2);
+ else
+ RADEONInitDispBandwidthLegacy(pScrn, mode1, pixel_bytes1, mode2, pixel_bytes2);
+}
+
Bool RADEONAllocateControllers(ScrnInfoPtr pScrn, int mask)
{
RADEONEntPtr pRADEONEnt = RADEONEntPriv(pScrn);
diff --git a/src/radeon_cursor.c b/src/radeon_cursor.c
index c4472db..13c2b9c 100644
--- a/src/radeon_cursor.c
+++ b/src/radeon_cursor.c
@@ -209,21 +209,23 @@ radeon_crtc_set_cursor_position (xf86CrtcPtr crtc, int x, int y)
if (xorigin >= CURSOR_WIDTH) xorigin = CURSOR_WIDTH - 1;
if (yorigin >= CURSOR_HEIGHT) yorigin = CURSOR_HEIGHT - 1;
- if (mode->Flags & V_INTERLACE)
- y /= 2;
- else if (mode->Flags & V_DBLSCAN)
- y *= 2;
-
if (IS_AVIVO_VARIANT) {
/* avivo cursor spans the full fb width */
- x += crtc->x;
- y += crtc->y;
+ if (crtc->rotatedData == NULL) {
+ x += crtc->x;
+ y += crtc->y;
+ }
avivo_lock_cursor(crtc, TRUE);
OUTREG(AVIVO_D1CUR_POSITION + radeon_crtc->crtc_offset, ((xorigin ? 0 : x) << 16)
| (yorigin ? 0 : y));
OUTREG(AVIVO_D1CUR_HOT_SPOT + radeon_crtc->crtc_offset, (xorigin << 16) | yorigin);
avivo_lock_cursor(crtc, FALSE);
} else {
+ if (mode->Flags & V_INTERLACE)
+ y /= 2;
+ else if (mode->Flags & V_DBLSCAN)
+ y *= 2;
+
if (crtc_id == 0) {
OUTREG(RADEON_CUR_HORZ_VERT_OFF, (RADEON_CUR_LOCK
| (xorigin << 16)
diff --git a/src/radeon_dri.c b/src/radeon_dri.c
index 0fc03e4..a192811 100644
--- a/src/radeon_dri.c
+++ b/src/radeon_dri.c
@@ -1103,7 +1103,7 @@ static int RADEONDRIKernelInit(RADEONInfoPtr info, ScreenPtr pScreen)
drmInfo.sarea_priv_offset = sizeof(XF86DRISAREARec);
drmInfo.is_pci = (info->cardType!=CARD_AGP);
- drmInfo.cp_mode = info->CPMode;
+ drmInfo.cp_mode = RADEON_CSQ_PRIBM_INDBM;
drmInfo.gart_size = info->gartSize*1024*1024;
drmInfo.ring_size = info->ringSize*1024*1024;
drmInfo.usec_timeout = info->CPusecTimeout;
@@ -1211,6 +1211,12 @@ static void RADEONDRIIrqInit(RADEONInfoPtr info, ScreenPtr pScreen)
} else {
unsigned char *RADEONMMIO = info->MMIO;
info->ModeReg->gen_int_cntl = INREG( RADEON_GEN_INT_CNTL );
+
+ /* Let the DRM know it can safely disable the vblank interrupts */
+ radeon_crtc_modeset_ioctl(XF86_CRTC_CONFIG_PTR(pScrn)->crtc[0],
+ FALSE);
+ radeon_crtc_modeset_ioctl(XF86_CRTC_CONFIG_PTR(pScrn)->crtc[0],
+ TRUE);
}
}
@@ -1453,10 +1459,9 @@ Bool RADEONDRIScreenInit(ScreenPtr pScreen)
PCI_DEV_DEV(info->PciInfo),
PCI_DEV_FUNC(info->PciInfo));
}
- pDRIInfo->ddxDriverMajorVersion = info->allowColorTiling ?
- RADEON_VERSION_MAJOR_TILED : RADEON_VERSION_MAJOR;
- pDRIInfo->ddxDriverMinorVersion = RADEON_VERSION_MINOR;
- pDRIInfo->ddxDriverPatchVersion = RADEON_VERSION_PATCH;
+ pDRIInfo->ddxDriverMajorVersion = info->allowColorTiling ? 5 : 4;
+ pDRIInfo->ddxDriverMinorVersion = 3;
+ pDRIInfo->ddxDriverPatchVersion = 0;
pDRIInfo->frameBufferPhysicalAddress = (void *)info->LinearAddr + info->frontOffset;
pDRIInfo->frameBufferSize = info->FbMapSize - info->FbSecureSize;
pDRIInfo->frameBufferStride = (pScrn->displayWidth *
diff --git a/src/radeon_dri.h b/src/radeon_dri.h
index 67892a6..6e3ad62 100644
--- a/src/radeon_dri.h
+++ b/src/radeon_dri.h
@@ -39,9 +39,8 @@
#include "xf86drm.h"
/* DRI Driver defaults */
-#define RADEON_DEFAULT_CP_PIO_MODE RADEON_CSQ_PRIPIO_INDPIO
-#define RADEON_DEFAULT_CP_BM_MODE RADEON_CSQ_PRIBM_INDBM
#define RADEON_DEFAULT_GART_SIZE 8 /* MB (must be 2^n and > 4MB) */
+#define R300_DEFAULT_GART_SIZE 32 /* MB (for R300 and above) */
#define RADEON_DEFAULT_RING_SIZE 1 /* MB (must be page aligned) */
#define RADEON_DEFAULT_BUFFER_SIZE 2 /* MB (must be page aligned) */
#define RADEON_DEFAULT_GART_TEX_SIZE 1 /* MB (must be page aligned) */
@@ -52,10 +51,6 @@
#define RADEON_CARD_TYPE_RADEON 1
-#define RADEONCP_USE_RING_BUFFER(m) \
- (((m) == RADEON_CSQ_PRIBM_INDDIS) || \
- ((m) == RADEON_CSQ_PRIBM_INDBM))
-
typedef struct {
/* DRI screen private data */
int deviceID; /* PCI device ID */
diff --git a/src/radeon_driver.c b/src/radeon_driver.c
index f18ad99..45d2c2f 100644
--- a/src/radeon_driver.c
+++ b/src/radeon_driver.c
@@ -669,7 +669,14 @@ static void radeon_write_mc_fb_agp_location(ScrnInfoPtr pScrn, int mask, uint32_
RADEONInfoPtr info = RADEONPTR(pScrn);
unsigned char *RADEONMMIO = info->MMIO;
- if (info->ChipFamily >= CHIP_FAMILY_R600) {
+ if (info->ChipFamily >= CHIP_FAMILY_RV770) {
+ if (mask & LOC_FB)
+ OUTREG(R700_MC_VM_FB_LOCATION, fb_loc);
+ if (mask & LOC_AGP) {
+ OUTREG(R600_MC_VM_AGP_BOT, agp_loc);
+ OUTREG(R600_MC_VM_AGP_TOP, agp_loc_hi);
+ }
+ } else if (info->ChipFamily >= CHIP_FAMILY_R600) {
if (mask & LOC_FB)
OUTREG(R600_MC_VM_FB_LOCATION, fb_loc);
if (mask & LOC_AGP) {
@@ -712,7 +719,14 @@ static void radeon_read_mc_fb_agp_location(ScrnInfoPtr pScrn, int mask, uint32_t
RADEONInfoPtr info = RADEONPTR(pScrn);
unsigned char *RADEONMMIO = info->MMIO;
- if (info->ChipFamily >= CHIP_FAMILY_R600) {
+ if (info->ChipFamily >= CHIP_FAMILY_RV770) {
+ if (mask & LOC_FB)
+ *fb_loc = INREG(R700_MC_VM_FB_LOCATION);
+ if (mask & LOC_AGP) {
+ *agp_loc = INREG(R600_MC_VM_AGP_BOT);
+ *agp_loc_hi = INREG(R600_MC_VM_AGP_TOP);
+ }
+ } else if (info->ChipFamily >= CHIP_FAMILY_R600) {
if (mask & LOC_FB)
*fb_loc = INREG(R600_MC_VM_FB_LOCATION);
if (mask & LOC_AGP) {
@@ -2032,16 +2046,22 @@ static Bool RADEONPreInitAccel(ScrnInfoPtr pScrn)
static Bool RADEONPreInitInt10(ScrnInfoPtr pScrn, xf86Int10InfoPtr *ppInt10)
{
-#if !defined(__powerpc__) && !defined(__sparc__)
+#if (!defined(__powerpc__) && !defined(__sparc__)) || \
+ (defined(XSERVER_LIBPCIACCESS) && HAVE_PCI_DEVICE_ENABLE)
RADEONInfoPtr info = RADEONPTR(pScrn);
+#endif
+#if !defined(__powerpc__) && !defined(__sparc__)
unsigned char *RADEONMMIO = info->MMIO;
uint32_t fp2_gen_ctl_save = 0;
+#endif
#ifdef XSERVER_LIBPCIACCESS
#if HAVE_PCI_DEVICE_ENABLE
pci_device_enable(info->PciInfo);
#endif
#endif
+
+#if !defined(__powerpc__) && !defined(__sparc__)
/* don't need int10 on atom cards.
* in theory all radeons, but the older stuff
* isn't 100% yet
@@ -2106,19 +2126,16 @@ static Bool RADEONPreInitDRI(ScrnInfoPtr pScrn)
if (info->Chipset == PCI_CHIP_RN50_515E ||
info->Chipset == PCI_CHIP_RN50_5969 ||
- info->Chipset == PCI_CHIP_RC410_5A61 ||
- info->Chipset == PCI_CHIP_RC410_5A62 ||
- info->Chipset == PCI_CHIP_RS485_5975 ||
info->ChipFamily == CHIP_FAMILY_RS600 ||
info->ChipFamily >= CHIP_FAMILY_R600) {
if (xf86ReturnOptValBool(info->Options, OPTION_DRI, FALSE)) {
xf86DrvMsg(pScrn->scrnIndex, X_WARNING,
- "Direct rendering for RN50/RC410/RS485/RS600/R600 forced on -- "
+ "Direct rendering for RN50/RS600/R600 forced on -- "
"This is NOT officially supported at the hardware level "
"and may cause instability or lockups\n");
} else {
xf86DrvMsg(pScrn->scrnIndex, X_INFO,
- "Direct rendering not officially supported on RN50/RC410/R600\n");
+ "Direct rendering not officially supported on RN50/RS600/R600\n");
return FALSE;
}
}
@@ -2167,14 +2184,11 @@ static Bool RADEONPreInitDRI(ScrnInfoPtr pScrn)
"Direct rendering experimental on RS400/Xpress 200 enabled\n");
}
- if (xf86ReturnOptValBool(info->Options, OPTION_CP_PIO, FALSE)) {
- xf86DrvMsg(pScrn->scrnIndex, X_CONFIG, "Forcing CP into PIO mode\n");
- info->CPMode = RADEON_DEFAULT_CP_PIO_MODE;
- } else {
- info->CPMode = RADEON_DEFAULT_CP_BM_MODE;
- }
+ if (info->ChipFamily >= CHIP_FAMILY_R300)
+ info->gartSize = R300_DEFAULT_GART_SIZE;
+ else
+ info->gartSize = RADEON_DEFAULT_GART_SIZE;
- info->gartSize = RADEON_DEFAULT_GART_SIZE;
info->ringSize = RADEON_DEFAULT_RING_SIZE;
info->bufSize = RADEON_DEFAULT_BUFFER_SIZE;
info->gartTexSize = RADEON_DEFAULT_GART_TEX_SIZE;
@@ -4178,6 +4192,7 @@ avivo_save(ScrnInfoPtr pScrn, RADEONSavePtr save)
state->crtc_master_en = INREG(AVIVO_DC_CRTC_MASTER_EN);
state->crtc_tv_control = INREG(AVIVO_DC_CRTC_TV_CONTROL);
+ state->dc_lb_memory_split = INREG(AVIVO_DC_LB_MEMORY_SPLIT);
state->pll1.ref_div_src = INREG(AVIVO_EXT1_PPLL_REF_DIV_SRC);
state->pll1.ref_div = INREG(AVIVO_EXT1_PPLL_REF_DIV);
@@ -4233,8 +4248,10 @@ avivo_save(ScrnInfoPtr pScrn, RADEONSavePtr save)
state->grph1.x_end = INREG(AVIVO_D1GRPH_X_END);
state->grph1.y_end = INREG(AVIVO_D1GRPH_Y_END);
+ state->grph1.desktop_height = INREG(AVIVO_D1MODE_DESKTOP_HEIGHT);
state->grph1.viewport_start = INREG(AVIVO_D1MODE_VIEWPORT_START);
state->grph1.viewport_size = INREG(AVIVO_D1MODE_VIEWPORT_SIZE);
+ state->grph1.mode_data_format = INREG(AVIVO_D1MODE_DATA_FORMAT);
state->crtc2.pll_source = INREG(AVIVO_PCLK_CRTC2_CNTL);
@@ -4272,8 +4289,10 @@ avivo_save(ScrnInfoPtr pScrn, RADEONSavePtr save)
state->grph2.x_end = INREG(AVIVO_D2GRPH_X_END);
state->grph2.y_end = INREG(AVIVO_D2GRPH_Y_END);
+ state->grph2.desktop_height = INREG(AVIVO_D2MODE_DESKTOP_HEIGHT);
state->grph2.viewport_start = INREG(AVIVO_D2MODE_VIEWPORT_START);
state->grph2.viewport_size = INREG(AVIVO_D2MODE_VIEWPORT_SIZE);
+ state->grph2.mode_data_format = INREG(AVIVO_D2MODE_DATA_FORMAT);
if (IS_DCE3_VARIANT) {
/* save DVOA regs */
@@ -4477,14 +4496,71 @@ avivo_restore(ScrnInfoPtr pScrn, RADEONSavePtr restore)
struct avivo_state *state = &restore->avivo;
int i, j;
- // OUTMC(pScrn, AVIVO_MC_MEMORY_MAP, state->mc_memory_map);
- // OUTREG(AVIVO_VGA_MEMORY_BASE, state->vga_memory_base);
- // OUTREG(AVIVO_VGA_FB_START, state->vga_fb_start);
+ xf86DrvMsg(pScrn->scrnIndex, X_INFO, "avivo_restore !\n");
+
+ /* Disable VGA control for now.. maybe needs to be changed */
+ OUTREG(AVIVO_D1VGA_CONTROL, 0);
+ OUTREG(AVIVO_D2VGA_CONTROL, 0);
+
+ /* Disable CRTCs */
+ OUTREG(AVIVO_D1CRTC_CONTROL,
+ (INREG(AVIVO_D1CRTC_CONTROL) & ~0x300) | 0x01000000);
+ OUTREG(AVIVO_D2CRTC_CONTROL,
+ (INREG(AVIVO_D2CRTC_CONTROL) & ~0x300) | 0x01000000);
+ OUTREG(AVIVO_D1CRTC_CONTROL,
+ INREG(AVIVO_D1CRTC_CONTROL) & ~0x1);
+ OUTREG(AVIVO_D2CRTC_CONTROL,
+ INREG(AVIVO_D2CRTC_CONTROL) & ~0x1);
+ OUTREG(AVIVO_D1CRTC_CONTROL,
+ INREG(AVIVO_D1CRTC_CONTROL) | 0x100);
+ OUTREG(AVIVO_D2CRTC_CONTROL,
+ INREG(AVIVO_D2CRTC_CONTROL) | 0x100);
+
+ /* Lock graph registers */
+ OUTREG(AVIVO_D1GRPH_UPDATE, AVIVO_D1GRPH_UPDATE_LOCK);
+ OUTREG(AVIVO_D1GRPH_PRIMARY_SURFACE_ADDRESS, state->grph1.prim_surf_addr);
+ OUTREG(AVIVO_D1GRPH_SECONDARY_SURFACE_ADDRESS, state->grph1.sec_surf_addr);
+ OUTREG(AVIVO_D1GRPH_CONTROL, state->grph1.control);
+ OUTREG(AVIVO_D1GRPH_SURFACE_OFFSET_X, state->grph1.x_offset);
+ OUTREG(AVIVO_D1GRPH_SURFACE_OFFSET_Y, state->grph1.y_offset);
+ OUTREG(AVIVO_D1GRPH_X_START, state->grph1.x_start);
+ OUTREG(AVIVO_D1GRPH_Y_START, state->grph1.y_start);
+ OUTREG(AVIVO_D1GRPH_X_END, state->grph1.x_end);
+ OUTREG(AVIVO_D1GRPH_Y_END, state->grph1.y_end);
+ OUTREG(AVIVO_D1GRPH_PITCH, state->grph1.pitch);
+ OUTREG(AVIVO_D1GRPH_ENABLE, state->grph1.enable);
+ OUTREG(AVIVO_D1GRPH_UPDATE, 0);
+
+ OUTREG(AVIVO_D2GRPH_UPDATE, AVIVO_D1GRPH_UPDATE_LOCK);
+ OUTREG(AVIVO_D2GRPH_PRIMARY_SURFACE_ADDRESS, state->grph2.prim_surf_addr);
+ OUTREG(AVIVO_D2GRPH_SECONDARY_SURFACE_ADDRESS, state->grph2.sec_surf_addr);
+ OUTREG(AVIVO_D2GRPH_CONTROL, state->grph2.control);
+ OUTREG(AVIVO_D2GRPH_SURFACE_OFFSET_X, state->grph2.x_offset);
+ OUTREG(AVIVO_D2GRPH_SURFACE_OFFSET_Y, state->grph2.y_offset);
+ OUTREG(AVIVO_D2GRPH_X_START, state->grph2.x_start);
+ OUTREG(AVIVO_D2GRPH_Y_START, state->grph2.y_start);
+ OUTREG(AVIVO_D2GRPH_X_END, state->grph2.x_end);
+ OUTREG(AVIVO_D2GRPH_Y_END, state->grph2.y_end);
+ OUTREG(AVIVO_D2GRPH_PITCH, state->grph2.pitch);
+ OUTREG(AVIVO_D2GRPH_ENABLE, state->grph2.enable);
+ OUTREG(AVIVO_D2GRPH_UPDATE, 0);
+ /* Whack some mode regs too */
+ OUTREG(AVIVO_D1SCL_UPDATE, AVIVO_D1SCL_UPDATE_LOCK);
+ OUTREG(AVIVO_D1MODE_DESKTOP_HEIGHT, state->grph1.desktop_height);
+ OUTREG(AVIVO_D1MODE_VIEWPORT_START, state->grph1.viewport_start);
+ OUTREG(AVIVO_D1MODE_VIEWPORT_SIZE, state->grph1.viewport_size);
+ OUTREG(AVIVO_D1MODE_DATA_FORMAT, state->grph1.mode_data_format);
+ OUTREG(AVIVO_D1SCL_UPDATE, 0);
- OUTREG(AVIVO_DC_CRTC_MASTER_EN, state->crtc_master_en);
- OUTREG(AVIVO_DC_CRTC_TV_CONTROL, state->crtc_tv_control);
+ OUTREG(AVIVO_D2SCL_UPDATE, AVIVO_D1SCL_UPDATE_LOCK);
+ OUTREG(AVIVO_D2MODE_DESKTOP_HEIGHT, state->grph2.desktop_height);
+ OUTREG(AVIVO_D2MODE_VIEWPORT_START, state->grph2.viewport_start);
+ OUTREG(AVIVO_D2MODE_VIEWPORT_SIZE, state->grph2.viewport_size);
+ OUTREG(AVIVO_D2MODE_DATA_FORMAT, state->grph2.mode_data_format);
+ OUTREG(AVIVO_D2SCL_UPDATE, 0);
+ /* Set the PLL */
OUTREG(AVIVO_EXT1_PPLL_REF_DIV_SRC, state->pll1.ref_div_src);
OUTREG(AVIVO_EXT1_PPLL_REF_DIV, state->pll1.ref_div);
OUTREG(AVIVO_EXT1_PPLL_FB_DIV, state->pll1.fb_div);
@@ -4504,7 +4580,9 @@ avivo_restore(ScrnInfoPtr pScrn, RADEONSavePtr restore)
OUTREG(AVIVO_P2PLL_INT_SS_CNTL, state->pll2.int_ss_cntl);
OUTREG(AVIVO_PCLK_CRTC1_CNTL, state->crtc1.pll_source);
+ OUTREG(AVIVO_PCLK_CRTC2_CNTL, state->crtc2.pll_source);
+ /* Set the CRTC */
OUTREG(AVIVO_D1CRTC_H_TOTAL, state->crtc1.h_total);
OUTREG(AVIVO_D1CRTC_H_BLANK_START_END, state->crtc1.h_blank_start_end);
OUTREG(AVIVO_D1CRTC_H_SYNC_A, state->crtc1.h_sync_a);
@@ -4519,29 +4597,12 @@ avivo_restore(ScrnInfoPtr pScrn, RADEONSavePtr restore)
OUTREG(AVIVO_D1CRTC_V_SYNC_B, state->crtc1.v_sync_b);
OUTREG(AVIVO_D1CRTC_V_SYNC_B_CNTL, state->crtc1.v_sync_b_cntl);
- OUTREG(AVIVO_D1CRTC_CONTROL, state->crtc1.control);
- OUTREG(AVIVO_D1CRTC_BLANK_CONTROL, state->crtc1.blank_control);
OUTREG(AVIVO_D1CRTC_INTERLACE_CONTROL, state->crtc1.interlace_control);
OUTREG(AVIVO_D1CRTC_STEREO_CONTROL, state->crtc1.stereo_control);
OUTREG(AVIVO_D1CUR_CONTROL, state->crtc1.cursor_control);
- OUTREG(AVIVO_D1GRPH_ENABLE, state->grph1.enable);
- OUTREG(AVIVO_D1GRPH_CONTROL, state->grph1.control);
- OUTREG(AVIVO_D1GRPH_PRIMARY_SURFACE_ADDRESS, state->grph1.prim_surf_addr);
- OUTREG(AVIVO_D1GRPH_SECONDARY_SURFACE_ADDRESS, state->grph1.sec_surf_addr);
- OUTREG(AVIVO_D1GRPH_PITCH, state->grph1.pitch);
- OUTREG(AVIVO_D1GRPH_SURFACE_OFFSET_X, state->grph1.x_offset);
- OUTREG(AVIVO_D1GRPH_SURFACE_OFFSET_Y, state->grph1.y_offset);
- OUTREG(AVIVO_D1GRPH_X_START, state->grph1.x_start);
- OUTREG(AVIVO_D1GRPH_Y_START, state->grph1.y_start);
- OUTREG(AVIVO_D1GRPH_X_END, state->grph1.x_end);
- OUTREG(AVIVO_D1GRPH_Y_END, state->grph1.y_end);
-
- OUTREG(AVIVO_D1MODE_VIEWPORT_START, state->grph1.viewport_start);
- OUTREG(AVIVO_D1MODE_VIEWPORT_SIZE, state->grph1.viewport_size);
-
- OUTREG(AVIVO_PCLK_CRTC2_CNTL, state->crtc2.pll_source);
+ /* XXX Fix scaler */
OUTREG(AVIVO_D2CRTC_H_TOTAL, state->crtc2.h_total);
OUTREG(AVIVO_D2CRTC_H_BLANK_START_END, state->crtc2.h_blank_start_end);
@@ -4557,29 +4618,11 @@ avivo_restore(ScrnInfoPtr pScrn, RADEONSavePtr restore)
OUTREG(AVIVO_D2CRTC_V_SYNC_B, state->crtc2.v_sync_b);
OUTREG(AVIVO_D2CRTC_V_SYNC_B_CNTL, state->crtc2.v_sync_b_cntl);
- OUTREG(AVIVO_D2CRTC_CONTROL, state->crtc2.control);
- OUTREG(AVIVO_D2CRTC_BLANK_CONTROL, state->crtc2.blank_control);
OUTREG(AVIVO_D2CRTC_INTERLACE_CONTROL, state->crtc2.interlace_control);
OUTREG(AVIVO_D2CRTC_STEREO_CONTROL, state->crtc2.stereo_control);
OUTREG(AVIVO_D2CUR_CONTROL, state->crtc2.cursor_control);
- OUTREG(AVIVO_D2GRPH_ENABLE, state->grph2.enable);
- OUTREG(AVIVO_D2GRPH_CONTROL, state->grph2.control);
- OUTREG(AVIVO_D2GRPH_PRIMARY_SURFACE_ADDRESS, state->grph2.prim_surf_addr);
- OUTREG(AVIVO_D2GRPH_SECONDARY_SURFACE_ADDRESS, state->grph2.sec_surf_addr);
- OUTREG(AVIVO_D2GRPH_PITCH, state->grph2.pitch);
- OUTREG(AVIVO_D2GRPH_SURFACE_OFFSET_X, state->grph2.x_offset);
- OUTREG(AVIVO_D2GRPH_SURFACE_OFFSET_Y, state->grph2.y_offset);
- OUTREG(AVIVO_D2GRPH_X_START, state->grph2.x_start);
- OUTREG(AVIVO_D2GRPH_Y_START, state->grph2.y_start);
- OUTREG(AVIVO_D2GRPH_X_END, state->grph2.x_end);
- OUTREG(AVIVO_D2GRPH_Y_END, state->grph2.y_end);
-
- OUTREG(AVIVO_D2MODE_VIEWPORT_START, state->grph2.viewport_start);
- OUTREG(AVIVO_D2MODE_VIEWPORT_SIZE, state->grph2.viewport_size);
-
-
if (IS_DCE3_VARIANT) {
/* DVOA regs */
OUTREG(0x7080, state->dvoa[0]);
@@ -4699,7 +4742,7 @@ avivo_restore(ScrnInfoPtr pScrn, RADEONSavePtr restore)
}
j = 0;
- /* DAC regs */
+ /* DAC regs */ /* -- MIGHT NEED ORDERING FIX & DELAYS -- */
for (i = 0x7800; i <= 0x782c; i += 4) {
OUTREG(i, state->daca[j]);
OUTREG((i + 0x200), state->dacb[j]);
@@ -4766,8 +4809,31 @@ avivo_restore(ScrnInfoPtr pScrn, RADEONSavePtr restore)
OUTREG(0x6e30, state->dxscl[6]);
OUTREG(0x6e34, state->dxscl[7]);
+ /* Enable CRTCs */
+ if (state->crtc1.control & 1) {
+ OUTREG(AVIVO_D1CRTC_CONTROL, 0x01000101);
+ INREG(AVIVO_D1CRTC_CONTROL);
+ OUTREG(AVIVO_D1CRTC_CONTROL, 0x00010101);
+ }
+ if (state->crtc2.control & 1) {
+ OUTREG(AVIVO_D2CRTC_CONTROL, 0x01000101);
+ INREG(AVIVO_D2CRTC_CONTROL);
+ OUTREG(AVIVO_D2CRTC_CONTROL, 0x00010101);
+ }
+
+ /* Where should that go ? */
+ OUTREG(AVIVO_DC_CRTC_TV_CONTROL, state->crtc_tv_control);
+ OUTREG(AVIVO_DC_LB_MEMORY_SPLIT, state->dc_lb_memory_split);
+
+ /* Need fixing too ? */
+ OUTREG(AVIVO_D1CRTC_BLANK_CONTROL, state->crtc1.blank_control);
+ OUTREG(AVIVO_D2CRTC_BLANK_CONTROL, state->crtc2.blank_control);
+
+ /* Dbl check */
OUTREG(AVIVO_D1VGA_CONTROL, state->vga1_cntl);
OUTREG(AVIVO_D2VGA_CONTROL, state->vga2_cntl);
+
+ /* Should only enable outputs here */
}
static void avivo_restore_vga_regs(ScrnInfoPtr pScrn, RADEONSavePtr restore)
@@ -5318,26 +5384,18 @@ Bool RADEONEnterVT(int scrnIndex, int flags)
{
ScrnInfoPtr pScrn = xf86Screens[scrnIndex];
RADEONInfoPtr info = RADEONPTR(pScrn);
- unsigned char *RADEONMMIO = info->MMIO;
- uint32_t mem_size;
xf86CrtcConfigPtr config = XF86_CRTC_CONFIG_PTR(pScrn);
int i;
xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG,
"RADEONEnterVT\n");
- if (info->ChipFamily >= CHIP_FAMILY_R600)
- mem_size = INREG(R600_CONFIG_MEMSIZE);
- else
- mem_size = INREG(RADEON_CONFIG_MEMSIZE);
-
- if (mem_size == 0) { /* Softboot V_BIOS */
+ if (!radeon_card_posted(pScrn)) { /* Softboot V_BIOS */
if (info->IsAtomBios) {
rhdAtomASICInit(info->atomBIOS);
} else {
xf86Int10InfoPtr pInt;
- xf86DrvMsg(pScrn->scrnIndex, X_WARNING,
- "zero MEMSIZE, probably at D3cold. Re-POSTing via int10.\n");
+
pInt = xf86InitInt10 (info->pEnt->index);
if (pInt) {
pInt->num = 0xe6;
diff --git a/src/radeon_exa.c b/src/radeon_exa.c
index f461f3c..02fd4fc 100644
--- a/src/radeon_exa.c
+++ b/src/radeon_exa.c
@@ -413,14 +413,16 @@ Bool RADEONSetupMemEXA (ScreenPtr pScreen)
/* Reserve static area for hardware cursor */
if (!xf86ReturnOptValBool(info->Options, OPTION_SW_CURSOR, FALSE)) {
int cursor_size = 64 * 4 * 64;
+ int align = IS_AVIVO_VARIANT ? 4096 : 256;
int c;
for (c = 0; c < xf86_config->num_crtc; c++) {
xf86CrtcPtr crtc = xf86_config->crtc[c];
RADEONCrtcPrivatePtr radeon_crtc = crtc->driver_private;
- radeon_crtc->cursor_offset = info->exa->offScreenBase;
- info->exa->offScreenBase += cursor_size;
+ radeon_crtc->cursor_offset =
+ RADEON_ALIGN(info->exa->offScreenBase, align);
+ info->exa->offScreenBase = radeon_crtc->cursor_offset + cursor_size;
xf86DrvMsg(pScrn->scrnIndex, X_INFO,
"Will use %d kb for hardware cursor %d at offset 0x%08x\n",
diff --git a/src/radeon_exa_render.c b/src/radeon_exa_render.c
index 4736e4f..5d28d80 100644
--- a/src/radeon_exa_render.c
+++ b/src/radeon_exa_render.c
@@ -1962,9 +1962,9 @@ static void FUNC_NAME(RadeonCompositeTile)(PixmapPtr pDst,
#ifdef ACCEL_CP
if (info->ChipFamily < CHIP_FAMILY_R200) {
- BEGIN_RING(4 * vtx_count + 3);
+ BEGIN_RING(3 * vtx_count + 3);
OUT_RING(CP_PACKET3(RADEON_CP_PACKET3_3D_DRAW_IMMD,
- 4 * vtx_count + 1));
+ 3 * vtx_count + 1));
if (has_mask)
OUT_RING(RADEON_CP_VC_FRMT_XY |
RADEON_CP_VC_FRMT_ST0 |
@@ -1972,11 +1972,11 @@ static void FUNC_NAME(RadeonCompositeTile)(PixmapPtr pDst,
else
OUT_RING(RADEON_CP_VC_FRMT_XY |
RADEON_CP_VC_FRMT_ST0);
- OUT_RING(RADEON_CP_VC_CNTL_PRIM_TYPE_TRI_FAN |
+ OUT_RING(RADEON_CP_VC_CNTL_PRIM_TYPE_RECT_LIST |
RADEON_CP_VC_CNTL_PRIM_WALK_RING |
RADEON_CP_VC_CNTL_MAOS_ENABLE |
RADEON_CP_VC_CNTL_VTX_FMT_RADEON_MODE |
- (4 << RADEON_CP_VC_CNTL_NUM_SHIFT));
+ (3 << RADEON_CP_VC_CNTL_NUM_SHIFT));
} else {
if (IS_R300_3D || IS_R500_3D)
BEGIN_RING(4 * vtx_count + 4);
@@ -1985,7 +1985,7 @@ static void FUNC_NAME(RadeonCompositeTile)(PixmapPtr pDst,
OUT_RING(CP_PACKET3(R200_CP_PACKET3_3D_DRAW_IMMD_2,
4 * vtx_count));
- OUT_RING(RADEON_CP_VC_CNTL_PRIM_TYPE_TRI_FAN |
+ OUT_RING(RADEON_CP_VC_CNTL_PRIM_TYPE_QUAD_LIST |
RADEON_CP_VC_CNTL_PRIM_WALK_RING |
(4 << RADEON_CP_VC_CNTL_NUM_SHIFT));
}
@@ -1993,25 +1993,29 @@ static void FUNC_NAME(RadeonCompositeTile)(PixmapPtr pDst,
#else /* ACCEL_CP */
if (IS_R300_3D || IS_R500_3D)
BEGIN_ACCEL(2 + vtx_count * 4);
+ else if (info->ChipFamily < CHIP_FAMILY_R200)
+ BEGIN_ACCEL(1 + vtx_count * 3);
else
BEGIN_ACCEL(1 + vtx_count * 4);
if (info->ChipFamily < CHIP_FAMILY_R200) {
- OUT_ACCEL_REG(RADEON_SE_VF_CNTL, (RADEON_VF_PRIM_TYPE_TRIANGLE_FAN |
+ OUT_ACCEL_REG(RADEON_SE_VF_CNTL, (RADEON_VF_PRIM_TYPE_RECTANGLE_LIST |
RADEON_VF_PRIM_WALK_DATA |
RADEON_VF_RADEON_MODE |
- 4 << RADEON_VF_NUM_VERTICES_SHIFT));
+ (3 << RADEON_VF_NUM_VERTICES_SHIFT)));
} else {
OUT_ACCEL_REG(RADEON_SE_VF_CNTL, (RADEON_VF_PRIM_TYPE_QUAD_LIST |
RADEON_VF_PRIM_WALK_DATA |
- 4 << RADEON_VF_NUM_VERTICES_SHIFT));
+ (4 << RADEON_VF_NUM_VERTICES_SHIFT)));
}
#endif
if (has_mask) {
- VTX_OUT_MASK((float)dstX, (float)dstY,
- xFixedToFloat(srcTopLeft.x) / info->texW[0], xFixedToFloat(srcTopLeft.y) / info->texH[0],
- xFixedToFloat(maskTopLeft.x) / info->texW[1], xFixedToFloat(maskTopLeft.y) / info->texH[1]);
+ if (info->ChipFamily >= CHIP_FAMILY_R200) {
+ VTX_OUT_MASK((float)dstX, (float)dstY,
+ xFixedToFloat(srcTopLeft.x) / info->texW[0], xFixedToFloat(srcTopLeft.y) / info->texH[0],
+ xFixedToFloat(maskTopLeft.x) / info->texW[1], xFixedToFloat(maskTopLeft.y) / info->texH[1]);
+ }
VTX_OUT_MASK((float)dstX, (float)(dstY + h),
xFixedToFloat(srcBottomLeft.x) / info->texW[0], xFixedToFloat(srcBottomLeft.y) / info->texH[0],
xFixedToFloat(maskBottomLeft.x) / info->texW[1], xFixedToFloat(maskBottomLeft.y) / info->texH[1]);
@@ -2022,8 +2026,10 @@ static void FUNC_NAME(RadeonCompositeTile)(PixmapPtr pDst,
xFixedToFloat(srcTopRight.x) / info->texW[0], xFixedToFloat(srcTopRight.y) / info->texH[0],
xFixedToFloat(maskTopRight.x) / info->texW[1], xFixedToFloat(maskTopRight.y) / info->texH[1]);
} else {
- VTX_OUT((float)dstX, (float)dstY,
- xFixedToFloat(srcTopLeft.x) / info->texW[0], xFixedToFloat(srcTopLeft.y) / info->texH[0]);
+ if (info->ChipFamily >= CHIP_FAMILY_R200) {
+ VTX_OUT((float)dstX, (float)dstY,
+ xFixedToFloat(srcTopLeft.x) / info->texW[0], xFixedToFloat(srcTopLeft.y) / info->texH[0]);
+ }
VTX_OUT((float)dstX, (float)(dstY + h),
xFixedToFloat(srcBottomLeft.x) / info->texW[0], xFixedToFloat(srcBottomLeft.y) / info->texH[0]);
VTX_OUT((float)(dstX + w), (float)(dstY + h),
diff --git a/src/radeon_macros.h b/src/radeon_macros.h
index afe442e..f19bc3e 100644
--- a/src/radeon_macros.h
+++ b/src/radeon_macros.h
@@ -51,32 +51,6 @@
#include "compiler.h"
-#if HAVE_BYTESWAP_H
-#include <byteswap.h>
-#elif defined(USE_SYS_ENDIAN_H)
-#include <sys/endian.h>
-#else
-#define bswap_16(value) \
- ((((value) & 0xff) << 8) | ((value) >> 8))
-
-#define bswap_32(value) \
- (((uint32_t)bswap_16((uint16_t)((value) & 0xffff)) << 16) | \
- (uint32_t)bswap_16((uint16_t)((value) >> 16)))
-
-#define bswap_64(value) \
- (((uint64_t)bswap_32((uint32_t)((value) & 0xffffffff)) \
- << 32) | \
- (uint64_t)bswap_32((uint32_t)((value) >> 32)))
-#endif
-
-#if X_BYTE_ORDER == X_BIG_ENDIAN
-#define le32_to_cpu(x) bswap_32(x)
-#define le16_to_cpu(x) bswap_16(x)
-#else
-#define le32_to_cpu(x) (x)
-#define le16_to_cpu(x) (x)
-#endif
-
#define RADEON_BIOS8(v) (info->VBIOS[v])
#define RADEON_BIOS16(v) (info->VBIOS[v] | \
(info->VBIOS[(v) + 1] << 8))
diff --git a/src/radeon_output.c b/src/radeon_output.c
index 7b89d66..7d7f88a 100644
--- a/src/radeon_output.c
+++ b/src/radeon_output.c
@@ -173,9 +173,6 @@ static const uint32_t default_tvdac_adj [CHIP_FAMILY_LAST] =
static void RADEONUpdatePanelSize(xf86OutputPtr output);
static void RADEONGetTMDSInfoFromTable(xf86OutputPtr output);
-#define AVIVO_I2C_DISABLE 0
-#define AVIVO_I2C_ENABLE 1
-static Bool AVIVOI2CDoLock(xf86OutputPtr output, int lock_state);
extern void atombios_output_mode_set(xf86OutputPtr output,
DisplayModePtr mode,
@@ -183,6 +180,8 @@ extern void atombios_output_mode_set(xf86OutputPtr output,
extern void atombios_output_dpms(xf86OutputPtr output, int mode);
extern RADEONMonitorType atombios_dac_detect(ScrnInfoPtr pScrn, xf86OutputPtr output);
extern int atombios_external_tmds_setup(xf86OutputPtr output, DisplayModePtr mode);
+extern AtomBiosResult
+atombios_lock_crtc(atomBiosHandlePtr atomBIOS, int crtc, int lock);
static void
radeon_bios_output_dpms(xf86OutputPtr output, int mode);
static void
@@ -213,88 +212,6 @@ void RADEONPrintPortMap(ScrnInfoPtr pScrn)
}
-static xf86MonPtr
-radeon_do_ddc(xf86OutputPtr output)
-{
- RADEONInfoPtr info = RADEONPTR(output->scrn);
- unsigned char *RADEONMMIO = info->MMIO;
- uint32_t DDCReg;
- xf86MonPtr MonInfo = NULL;
- RADEONOutputPrivatePtr radeon_output = output->driver_private;
- int i, j;
-
- if (radeon_output->pI2CBus) {
- DDCReg = radeon_output->ddc_i2c.mask_clk_reg;
-
- if (IS_AVIVO_VARIANT) {
- AVIVOI2CDoLock(output, AVIVO_I2C_ENABLE);
- MonInfo = xf86OutputGetEDID(output, radeon_output->pI2CBus);
- AVIVOI2CDoLock(output, AVIVO_I2C_DISABLE);
- } else if ((DDCReg == RADEON_LCD_GPIO_MASK) || (DDCReg == RADEON_MDGPIO_EN_REG)) {
- MonInfo = xf86OutputGetEDID(output, radeon_output->pI2CBus);
- } else {
- OUTREG(DDCReg, INREG(DDCReg) &
- (uint32_t)~(RADEON_GPIO_A_0 | RADEON_GPIO_A_1));
-
- /* For some old monitors (like Compaq Presario FP500), we need
- * following process to initialize/stop DDC
- */
- OUTREG(DDCReg, INREG(DDCReg) & ~(RADEON_GPIO_EN_1));
- for (j = 0; j < 3; j++) {
- OUTREG(DDCReg,
- INREG(DDCReg) & ~(RADEON_GPIO_EN_0));
- usleep(13000);
-
- OUTREG(DDCReg,
- INREG(DDCReg) & ~(RADEON_GPIO_EN_1));
- for (i = 0; i < 10; i++) {
- usleep(15000);
- if (INREG(DDCReg) & RADEON_GPIO_Y_1)
- break;
- }
- if (i == 10) continue;
-
- usleep(15000);
-
- OUTREG(DDCReg, INREG(DDCReg) | RADEON_GPIO_EN_0);
- usleep(15000);
-
- OUTREG(DDCReg, INREG(DDCReg) | RADEON_GPIO_EN_1);
- usleep(15000);
- OUTREG(DDCReg,
- INREG(DDCReg) & ~(RADEON_GPIO_EN_0));
- usleep(15000);
-
- MonInfo = xf86OutputGetEDID(output, radeon_output->pI2CBus);
-
- OUTREG(DDCReg, INREG(DDCReg) | RADEON_GPIO_EN_1);
- OUTREG(DDCReg, INREG(DDCReg) | RADEON_GPIO_EN_0);
- usleep(15000);
- OUTREG(DDCReg,
- INREG(DDCReg) & ~(RADEON_GPIO_EN_1));
- for (i = 0; i < 5; i++) {
- usleep(15000);
- if (INREG(DDCReg) & RADEON_GPIO_Y_1)
- break;
- }
- usleep(15000);
- OUTREG(DDCReg,
- INREG(DDCReg) & ~(RADEON_GPIO_EN_0));
- usleep(15000);
-
- OUTREG(DDCReg, INREG(DDCReg) | RADEON_GPIO_EN_1);
- OUTREG(DDCReg, INREG(DDCReg) | RADEON_GPIO_EN_0);
- usleep(15000);
- if (MonInfo) break;
- }
- OUTREG(DDCReg, INREG(DDCReg) &
- ~(RADEON_GPIO_EN_0 | RADEON_GPIO_EN_1));
- }
- }
-
- return MonInfo;
-}
-
static RADEONMonitorType
radeon_ddc_connected(xf86OutputPtr output)
{
@@ -304,8 +221,11 @@ radeon_ddc_connected(xf86OutputPtr output)
xf86MonPtr MonInfo = NULL;
RADEONOutputPrivatePtr radeon_output = output->driver_private;
- if (radeon_output->pI2CBus)
- MonInfo = radeon_do_ddc(output);
+ if (radeon_output->pI2CBus) {
+ RADEONI2CDoLock(output, TRUE);
+ MonInfo = xf86OutputGetEDID(output, radeon_output->pI2CBus);
+ RADEONI2CDoLock(output, FALSE);
+ }
if (MonInfo) {
if (!xf86ReturnOptValBool(info->Options, OPTION_IGNORE_EDID, FALSE))
xf86OutputSetEDID(output, MonInfo);
@@ -317,13 +237,14 @@ radeon_ddc_connected(xf86OutputPtr output)
MonType = MT_DFP;
else if (radeon_output->type == OUTPUT_DP)
MonType = MT_DFP;
- else if (radeon_output->type == OUTPUT_DVI_I && (MonInfo->rawData[0x14] & 0x80)) /* if it's digital and DVI */
+ else if (radeon_output->type == OUTPUT_DVI_I &&
+ (MonInfo->rawData[0x14] & 0x80)) /* if it's digital and DVI */
MonType = MT_DFP;
else
MonType = MT_CRT;
} else
MonType = MT_NONE;
-
+
xf86DrvMsg(pScrn->scrnIndex, X_INFO,
"Output: %s, Detected Monitor Type: %d\n", output->name, MonType);
@@ -537,7 +458,7 @@ radeon_mode_fixup(xf86OutputPtr output, DisplayModePtr mode,
if (IS_AVIVO_VARIANT) {
/* set to the panel's native mode */
adjusted_mode->HDisplay = radeon_output->PanelXRes;
- adjusted_mode->HDisplay = radeon_output->PanelYRes;
+ adjusted_mode->VDisplay = radeon_output->PanelYRes;
adjusted_mode->HTotal = radeon_output->PanelXRes + radeon_output->HBlank;
adjusted_mode->HSyncStart = radeon_output->PanelXRes + radeon_output->HOverPlus;
adjusted_mode->HSyncEnd = adjusted_mode->HSyncStart + radeon_output->HSyncWidth;
@@ -580,12 +501,20 @@ radeon_mode_fixup(xf86OutputPtr output, DisplayModePtr mode,
}
}
+ if (IS_AVIVO_VARIANT) {
+ /* hw bug */
+ if ((mode->Flags & V_INTERLACE)
+ && (mode->CrtcVSyncStart < (mode->CrtcVDisplay + 2)))
+ adjusted_mode->CrtcVSyncStart = adjusted_mode->CrtcVDisplay + 2;
+ }
+
return TRUE;
}
static void
radeon_mode_prepare(xf86OutputPtr output)
{
+ RADEONInfoPtr info = RADEONPTR(output->scrn);
xf86CrtcConfigPtr config = XF86_CRTC_CONFIG_PTR (output->scrn);
int o;
@@ -595,9 +524,12 @@ radeon_mode_prepare(xf86OutputPtr output)
continue;
else if (loop_output->crtc) {
xf86CrtcPtr other_crtc = loop_output->crtc;
+ RADEONCrtcPrivatePtr other_radeon_crtc = other_crtc->driver_private;
if (other_crtc->enabled) {
- radeon_dpms(loop_output, DPMSModeOff);
radeon_crtc_dpms(other_crtc, DPMSModeOff);
+ if (IS_AVIVO_VARIANT)
+ atombios_lock_crtc(info->atomBIOS, other_radeon_crtc->crtc_id, 1);
+ radeon_dpms(loop_output, DPMSModeOff);
}
}
}
@@ -625,6 +557,7 @@ radeon_mode_set(xf86OutputPtr output, DisplayModePtr mode,
static void
radeon_mode_commit(xf86OutputPtr output)
{
+ RADEONInfoPtr info = RADEONPTR(output->scrn);
xf86CrtcConfigPtr config = XF86_CRTC_CONFIG_PTR (output->scrn);
int o;
@@ -634,9 +567,12 @@ radeon_mode_commit(xf86OutputPtr output)
continue;
else if (loop_output->crtc) {
xf86CrtcPtr other_crtc = loop_output->crtc;
+ RADEONCrtcPrivatePtr other_radeon_crtc = other_crtc->driver_private;
if (other_crtc->enabled) {
- radeon_dpms(loop_output, DPMSModeOn);
radeon_crtc_dpms(other_crtc, DPMSModeOn);
+ if (IS_AVIVO_VARIANT)
+ atombios_lock_crtc(info->atomBIOS, other_radeon_crtc->crtc_id, 0);
+ radeon_dpms(loop_output, DPMSModeOn);
}
}
}
@@ -1682,8 +1618,8 @@ Bool AVIVOI2CReset(ScrnInfoPtr pScrn)
}
#endif
-static
-Bool AVIVOI2CDoLock(xf86OutputPtr output, int lock_state)
+Bool
+RADEONI2CDoLock(xf86OutputPtr output, int lock_state)
{
ScrnInfoPtr pScrn = output->scrn;
RADEONInfoPtr info = RADEONPTR(pScrn);
@@ -1692,19 +1628,29 @@ Bool AVIVOI2CDoLock(xf86OutputPtr output, int lock_state)
unsigned char *RADEONMMIO = info->MMIO;
uint32_t temp;
+ if (lock_state) {
+ temp = INREG(pRADEONI2CBus->a_clk_reg);
+ temp &= ~(pRADEONI2CBus->a_clk_mask);
+ OUTREG(pRADEONI2CBus->a_clk_reg, temp);
+
+ temp = INREG(pRADEONI2CBus->a_data_reg);
+ temp &= ~(pRADEONI2CBus->a_data_mask);
+ OUTREG(pRADEONI2CBus->a_data_reg, temp);
+ }
+
temp = INREG(pRADEONI2CBus->mask_clk_reg);
- if (lock_state == AVIVO_I2C_ENABLE)
- temp |= (pRADEONI2CBus->put_clk_mask);
+ if (lock_state)
+ temp |= (pRADEONI2CBus->mask_clk_mask);
else
- temp &= ~(pRADEONI2CBus->put_clk_mask);
+ temp &= ~(pRADEONI2CBus->mask_clk_mask);
OUTREG(pRADEONI2CBus->mask_clk_reg, temp);
temp = INREG(pRADEONI2CBus->mask_clk_reg);
temp = INREG(pRADEONI2CBus->mask_data_reg);
- if (lock_state == AVIVO_I2C_ENABLE)
- temp |= (pRADEONI2CBus->put_data_mask);
+ if (lock_state)
+ temp |= (pRADEONI2CBus->mask_data_mask);
else
- temp &= ~(pRADEONI2CBus->put_data_mask);
+ temp &= ~(pRADEONI2CBus->mask_data_mask);
OUTREG(pRADEONI2CBus->mask_data_reg, temp);
temp = INREG(pRADEONI2CBus->mask_data_reg);
@@ -1786,8 +1732,10 @@ legacy_setup_i2c_bus(int ddc_line)
{
RADEONI2CBusRec i2c;
- i2c.mask_clk_mask = RADEON_GPIO_EN_1 | RADEON_GPIO_Y_1;
- i2c.mask_data_mask = RADEON_GPIO_EN_0 | RADEON_GPIO_Y_0;
+ i2c.mask_clk_mask = RADEON_GPIO_EN_1;
+ i2c.mask_data_mask = RADEON_GPIO_EN_0;
+ i2c.a_clk_mask = RADEON_GPIO_A_1;
+ i2c.a_data_mask = RADEON_GPIO_A_0;
i2c.put_clk_mask = RADEON_GPIO_EN_1;
i2c.put_data_mask = RADEON_GPIO_EN_0;
i2c.get_clk_mask = RADEON_GPIO_Y_1;
@@ -1796,6 +1744,8 @@ legacy_setup_i2c_bus(int ddc_line)
(ddc_line == RADEON_MDGPIO_EN_REG)) {
i2c.mask_clk_reg = ddc_line;
i2c.mask_data_reg = ddc_line;
+ i2c.a_clk_reg = ddc_line;
+ i2c.a_data_reg = ddc_line;
i2c.put_clk_reg = ddc_line;
i2c.put_data_reg = ddc_line;
i2c.get_clk_reg = ddc_line + 4;
@@ -1803,6 +1753,8 @@ legacy_setup_i2c_bus(int ddc_line)
} else {
i2c.mask_clk_reg = ddc_line;
i2c.mask_data_reg = ddc_line;
+ i2c.a_clk_reg = ddc_line;
+ i2c.a_data_reg = ddc_line;
i2c.put_clk_reg = ddc_line;
i2c.put_data_reg = ddc_line;
i2c.get_clk_reg = ddc_line;
@@ -1829,6 +1781,8 @@ atom_setup_i2c_bus(int ddc_line)
i2c.get_data_mask = (1 << 18);
i2c.mask_clk_mask = (1 << 19);
i2c.mask_data_mask = (1 << 18);
+ i2c.a_clk_mask = (1 << 19);
+ i2c.a_data_mask = (1 << 18);
} else {
i2c.put_clk_mask = (1 << 0);
i2c.put_data_mask = (1 << 8);
@@ -1836,9 +1790,13 @@ atom_setup_i2c_bus(int ddc_line)
i2c.get_data_mask = (1 << 8);
i2c.mask_clk_mask = (1 << 0);
i2c.mask_data_mask = (1 << 8);
+ i2c.a_clk_mask = (1 << 0);
+ i2c.a_data_mask = (1 << 8);
}
i2c.mask_clk_reg = ddc_line;
i2c.mask_data_reg = ddc_line;
+ i2c.a_clk_reg = ddc_line + 0x4;
+ i2c.a_data_reg = ddc_line + 0x4;
i2c.put_clk_reg = ddc_line + 0x8;
i2c.put_data_reg = ddc_line + 0x8;
i2c.get_clk_reg = ddc_line + 0xc;
@@ -2301,7 +2259,7 @@ static Bool RADEONSetupAppleConnectors(ScrnInfoPtr pScrn)
info->BiosConnector[0].ddc_i2c = legacy_setup_i2c_bus(RADEON_GPIO_DVI_DDC);
info->BiosConnector[0].DACType = DAC_NONE;
info->BiosConnector[0].TMDSType = TMDS_NONE;
- info->BiosConnector[0].ConnectorType = CONNECTOR_VGA;
+ info->BiosConnector[0].ConnectorType = CONNECTOR_LVDS;
info->BiosConnector[0].valid = TRUE;
info->BiosConnector[1].ddc_i2c = legacy_setup_i2c_bus(RADEON_GPIO_VGA_DDC);
@@ -2677,7 +2635,6 @@ Bool RADEONSetupConnectors(ScrnInfoPtr pScrn)
{
xf86CrtcConfigPtr xf86_config = XF86_CRTC_CONFIG_PTR(pScrn);
RADEONInfoPtr info = RADEONPTR(pScrn);
- RADEONEntPtr pRADEONEnt = RADEONEntPriv(pScrn);
xf86OutputPtr output;
char *optstr;
int i = 0;
@@ -2742,13 +2699,6 @@ Bool RADEONSetupConnectors(ScrnInfoPtr pScrn)
RADEONSetupGenericConnectors(pScrn);
}
- if (!pRADEONEnt->HasCRTC2) {
- for (i = 0; i < RADEON_MAX_BIOS_CONNECTOR; i++) {
- if (info->BiosConnector[i].ConnectorType == CONNECTOR_VGA)
- info->BiosConnector[i].DACType = DAC_PRIMARY;
- }
- }
-
/* parse connector table option */
optstr = (char *)xf86GetOptValString(info->Options, OPTION_CONNECTORTABLE);
diff --git a/src/radeon_pci_chipset_gen.h b/src/radeon_pci_chipset_gen.h
index 39adb5e..f24deb5 100644
--- a/src/radeon_pci_chipset_gen.h
+++ b/src/radeon_pci_chipset_gen.h
@@ -1,6 +1,7 @@
/* This file is autogenerated please do not edit */
PciChipsets RADEONPciChipsets[] = {
{ PCI_CHIP_RV380_3150, PCI_CHIP_RV380_3150, RES_SHARED_VGA },
+ { PCI_CHIP_RV380_3151, PCI_CHIP_RV380_3151, RES_SHARED_VGA },
{ PCI_CHIP_RV380_3152, PCI_CHIP_RV380_3152, RES_SHARED_VGA },
{ PCI_CHIP_RV380_3154, PCI_CHIP_RV380_3154, RES_SHARED_VGA },
{ PCI_CHIP_RV380_3E50, PCI_CHIP_RV380_3E50, RES_SHARED_VGA },
@@ -250,6 +251,8 @@ PciChipsets RADEONPciChipsets[] = {
{ PCI_CHIP_R600_940A, PCI_CHIP_R600_940A, RES_SHARED_VGA },
{ PCI_CHIP_R600_940B, PCI_CHIP_R600_940B, RES_SHARED_VGA },
{ PCI_CHIP_R600_940F, PCI_CHIP_R600_940F, RES_SHARED_VGA },
+ { PCI_CHIP_RV770_9440, PCI_CHIP_RV770_9440, RES_SHARED_VGA },
+ { PCI_CHIP_RV770_9442, PCI_CHIP_RV770_9442, RES_SHARED_VGA },
{ PCI_CHIP_RV610_94C0, PCI_CHIP_RV610_94C0, RES_SHARED_VGA },
{ PCI_CHIP_RV610_94C1, PCI_CHIP_RV610_94C1, RES_SHARED_VGA },
{ PCI_CHIP_RV610_94C3, PCI_CHIP_RV610_94C3, RES_SHARED_VGA },
@@ -267,6 +270,7 @@ PciChipsets RADEONPciChipsets[] = {
{ PCI_CHIP_RV670_9507, PCI_CHIP_RV670_9507, RES_SHARED_VGA },
{ PCI_CHIP_RV670_950F, PCI_CHIP_RV670_950F, RES_SHARED_VGA },
{ PCI_CHIP_RV670_9511, PCI_CHIP_RV670_9511, RES_SHARED_VGA },
+ { PCI_CHIP_RV670_9515, PCI_CHIP_RV670_9515, RES_SHARED_VGA },
{ PCI_CHIP_RV630_9580, PCI_CHIP_RV630_9580, RES_SHARED_VGA },
{ PCI_CHIP_RV630_9581, PCI_CHIP_RV630_9581, RES_SHARED_VGA },
{ PCI_CHIP_RV630_9583, PCI_CHIP_RV630_9583, RES_SHARED_VGA },
diff --git a/src/radeon_pci_device_match_gen.h b/src/radeon_pci_device_match_gen.h
index d81cbe3..aa19d6a 100644
--- a/src/radeon_pci_device_match_gen.h
+++ b/src/radeon_pci_device_match_gen.h
@@ -1,6 +1,7 @@
/* This file is autogenerated please do not edit */
static const struct pci_id_match radeon_device_match[] = {
ATI_DEVICE_MATCH( PCI_CHIP_RV380_3150, 0 ),
+ ATI_DEVICE_MATCH( PCI_CHIP_RV380_3151, 0 ),
ATI_DEVICE_MATCH( PCI_CHIP_RV380_3152, 0 ),
ATI_DEVICE_MATCH( PCI_CHIP_RV380_3154, 0 ),
ATI_DEVICE_MATCH( PCI_CHIP_RV380_3E50, 0 ),
@@ -250,6 +251,8 @@ static const struct pci_id_match radeon_device_match[] = {
ATI_DEVICE_MATCH( PCI_CHIP_R600_940A, 0 ),
ATI_DEVICE_MATCH( PCI_CHIP_R600_940B, 0 ),
ATI_DEVICE_MATCH( PCI_CHIP_R600_940F, 0 ),
+ ATI_DEVICE_MATCH( PCI_CHIP_RV770_9440, 0 ),
+ ATI_DEVICE_MATCH( PCI_CHIP_RV770_9442, 0 ),
ATI_DEVICE_MATCH( PCI_CHIP_RV610_94C0, 0 ),
ATI_DEVICE_MATCH( PCI_CHIP_RV610_94C1, 0 ),
ATI_DEVICE_MATCH( PCI_CHIP_RV610_94C3, 0 ),
@@ -267,6 +270,7 @@ static const struct pci_id_match radeon_device_match[] = {
ATI_DEVICE_MATCH( PCI_CHIP_RV670_9507, 0 ),
ATI_DEVICE_MATCH( PCI_CHIP_RV670_950F, 0 ),
ATI_DEVICE_MATCH( PCI_CHIP_RV670_9511, 0 ),
+ ATI_DEVICE_MATCH( PCI_CHIP_RV670_9515, 0 ),
ATI_DEVICE_MATCH( PCI_CHIP_RV630_9580, 0 ),
ATI_DEVICE_MATCH( PCI_CHIP_RV630_9581, 0 ),
ATI_DEVICE_MATCH( PCI_CHIP_RV630_9583, 0 ),
diff --git a/src/radeon_probe.h b/src/radeon_probe.h
index 24af52b..3770abf 100644
--- a/src/radeon_probe.h
+++ b/src/radeon_probe.h
@@ -166,6 +166,8 @@ typedef struct
Bool valid;
uint32_t mask_clk_reg;
uint32_t mask_data_reg;
+ uint32_t a_clk_reg;
+ uint32_t a_data_reg;
uint32_t put_clk_reg;
uint32_t put_data_reg;
uint32_t get_clk_reg;
@@ -176,6 +178,8 @@ typedef struct
uint32_t put_data_mask;
uint32_t get_clk_mask;
uint32_t get_data_mask;
+ uint32_t a_clk_mask;
+ uint32_t a_data_mask;
} RADEONI2CBusRec, *RADEONI2CBusPtr;
typedef struct _RADEONCrtcPrivateRec {
@@ -310,8 +314,10 @@ struct avivo_grph_state {
uint32_t x_end;
uint32_t y_end;
+ uint32_t desktop_height;
uint32_t viewport_start;
uint32_t viewport_size;
+ uint32_t mode_data_format;
};
struct avivo_state
@@ -326,6 +332,7 @@ struct avivo_state
uint32_t crtc_master_en;
uint32_t crtc_tv_control;
+ uint32_t dc_lb_memory_split;
struct avivo_pll_state pll1;
struct avivo_pll_state pll2;
diff --git a/src/radeon_reg.h b/src/radeon_reg.h
index 59e2f12..1d35236 100644
--- a/src/radeon_reg.h
+++ b/src/radeon_reg.h
@@ -1032,6 +1032,10 @@
#define RADEON_OV0_BASE_ADDR 0x43c
#define RADEON_NB_TOM 0x15c
#define R300_MC_INIT_MISC_LAT_TIMER 0x180
+# define R300_MC_DISP0R_INIT_LAT_SHIFT 8
+# define R300_MC_DISP0R_INIT_LAT_MASK 0xf
+# define R300_MC_DISP1R_INIT_LAT_SHIFT 12
+# define R300_MC_DISP1R_INIT_LAT_MASK 0xf
#define RADEON_MCLK_CNTL 0x0012 /* PLL */
# define RADEON_FORCEON_MCLKA (1 << 16)
# define RADEON_FORCEON_MCLKB (1 << 17)
@@ -3185,6 +3189,7 @@
#define RADEON_CP_VC_CNTL_PRIM_TYPE_RECT_LIST 0x00000008
#define RADEON_CP_VC_CNTL_PRIM_TYPE_3VRT_POINT_LIST 0x00000009
#define RADEON_CP_VC_CNTL_PRIM_TYPE_3VRT_LINE_LIST 0x0000000a
+#define RADEON_CP_VC_CNTL_PRIM_TYPE_QUAD_LIST 0x0000000d
#define RADEON_CP_VC_CNTL_PRIM_WALK_IND 0x00000010
#define RADEON_CP_VC_CNTL_PRIM_WALK_LIST 0x00000020
#define RADEON_CP_VC_CNTL_PRIM_WALK_RING 0x00000030
@@ -3418,6 +3423,7 @@
#define RS690_MC_AGP_LOCATION 0x101
#define RS690_MC_AGP_BASE 0x102
#define RS690_MC_AGP_BASE_2 0x103
+#define RS690_MC_INIT_MISC_LAT_TIMER 0x104
#define RS690_MC_STATUS 0x90
#define RS690_MC_STATUS_IDLE (1 << 0)
@@ -3431,12 +3437,13 @@
#define RS600_MC_STATUS 0x0
#define RS600_MC_STATUS_IDLE (1 << 0)
-#define AVIVO_MC_INDEX 0x0070
-#define R520_MC_STATUS 0x00
-#define R520_MC_STATUS_IDLE (1<<1)
-#define RV515_MC_STATUS 0x08
-#define RV515_MC_STATUS_IDLE (1<<4)
-#define AVIVO_MC_DATA 0x0074
+#define AVIVO_MC_INDEX 0x0070
+#define R520_MC_STATUS 0x00
+# define R520_MC_STATUS_IDLE (1 << 1)
+#define RV515_MC_STATUS 0x08
+# define RV515_MC_STATUS_IDLE (1 << 4)
+#define RV515_MC_INIT_MISC_LAT_TIMER 0x09
+#define AVIVO_MC_DATA 0x0074
#define RV515_MC_FB_LOCATION 0x1
#define RV515_MC_AGP_LOCATION 0x2
@@ -3598,8 +3605,20 @@
#define AVIVO_DC_LUTA_WHITE_OFFSET_GREEN 0x64d4
#define AVIVO_DC_LUTA_WHITE_OFFSET_RED 0x64d8
-
-#define AVIVO_D1MODE_DESKTOP_HEIGHT 0x652C
+#define AVIVO_DC_LB_MEMORY_SPLIT 0x6520
+# define AVIVO_DC_LB_MEMORY_SPLIT_MASK 0x3
+# define AVIVO_DC_LB_MEMORY_SPLIT_SHIFT 0
+# define AVIVO_DC_LB_MEMORY_SPLIT_D1HALF_D2HALF 0
+# define AVIVO_DC_LB_MEMORY_SPLIT_D1_3Q_D2_1Q 1
+# define AVIVO_DC_LB_MEMORY_SPLIT_D1_ONLY 2
+# define AVIVO_DC_LB_MEMORY_SPLIT_D1_1Q_D2_3Q 3
+# define AVIVO_DC_LB_MEMORY_SPLIT_SHIFT_MODE (1 << 2)
+# define AVIVO_DC_LB_DISP1_END_ADR_SHIFT 4
+# define AVIVO_DC_LB_DISP1_END_ADR_MASK 0x7ff
+
+#define AVIVO_D1MODE_DATA_FORMAT 0x6528
+# define AVIVO_D1MODE_INTERLEAVE_EN (1 << 0)
+#define AVIVO_D1MODE_DESKTOP_HEIGHT 0x652c
#define AVIVO_D1MODE_VIEWPORT_START 0x6580
#define AVIVO_D1MODE_VIEWPORT_SIZE 0x6584
#define AVIVO_D1MODE_EXT_OVERSCAN_LEFT_RIGHT 0x6588
@@ -3651,6 +3670,8 @@
#define AVIVO_D2CUR_SIZE 0x6c10
#define AVIVO_D2CUR_POSITION 0x6c14
+#define AVIVO_D2MODE_DATA_FORMAT 0x6d28
+#define AVIVO_D2MODE_DESKTOP_HEIGHT 0x6d2c
#define AVIVO_D2MODE_VIEWPORT_START 0x6d80
#define AVIVO_D2MODE_VIEWPORT_SIZE 0x6d84
#define AVIVO_D2MODE_EXT_OVERSCAN_LEFT_RIGHT 0x6d88
@@ -3658,6 +3679,7 @@
#define AVIVO_D2SCL_SCALER_ENABLE 0x6d90
#define AVIVO_D2SCL_SCALER_TAP_CONTROL 0x6d94
+#define AVIVO_D2SCL_UPDATE 0x6dcc
#define AVIVO_DDIA_BIT_DEPTH_CONTROL 0x7214
@@ -3918,6 +3940,8 @@
#define R600_MC_VM_SYSTEM_APERTURE_HIGH_ADDR 0x2194
#define R600_MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR 0x2198
+#define R700_MC_VM_FB_LOCATION 0x2024
+
#define R600_HDP_NONSURFACE_BASE 0x2c04
#define R600_BUS_CNTL 0x5420
diff --git a/src/radeon_textured_videofuncs.c b/src/radeon_textured_videofuncs.c
index 277d9b2..d39f74d 100644
--- a/src/radeon_textured_videofuncs.c
+++ b/src/radeon_textured_videofuncs.c
@@ -486,6 +486,8 @@ FUNC_NAME(RADEONDisplayTexturedVideo)(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv
OUT_VIDEO_REG(R200_PP_TXFILTER_0,
R200_MAG_FILTER_LINEAR |
R200_MIN_FILTER_LINEAR |
+ R200_CLAMP_S_CLAMP_LAST |
+ R200_CLAMP_T_CLAMP_LAST |
R200_YUV_TO_RGB);
OUT_VIDEO_REG(R200_PP_TXFORMAT_0, txformat);
OUT_VIDEO_REG(R200_PP_TXFORMAT_X_0, 0);
@@ -521,8 +523,11 @@ FUNC_NAME(RADEONDisplayTexturedVideo)(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv
OUT_VIDEO_REG(RADEON_SE_VTX_FMT, RADEON_SE_VTX_FMT_XY |
RADEON_SE_VTX_FMT_ST0);
- OUT_VIDEO_REG(RADEON_PP_TXFILTER_0, RADEON_MAG_FILTER_LINEAR |
+ OUT_VIDEO_REG(RADEON_PP_TXFILTER_0,
+ RADEON_MAG_FILTER_LINEAR |
RADEON_MIN_FILTER_LINEAR |
+ RADEON_CLAMP_S_CLAMP_LAST |
+ RADEON_CLAMP_T_CLAMP_LAST |
RADEON_YUV_TO_RGB);
OUT_VIDEO_REG(RADEON_PP_TXFORMAT_0, txformat);
OUT_VIDEO_REG(RADEON_PP_TXOFFSET_0, pPriv->src_offset);
@@ -582,16 +587,16 @@ FUNC_NAME(RADEONDisplayTexturedVideo)(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv
#ifdef ACCEL_CP
if (info->ChipFamily < CHIP_FAMILY_R200) {
- BEGIN_RING(4 * VTX_DWORD_COUNT + 3);
+ BEGIN_RING(3 * VTX_DWORD_COUNT + 3);
OUT_RING(CP_PACKET3(RADEON_CP_PACKET3_3D_DRAW_IMMD,
- 4 * VTX_DWORD_COUNT + 1));
+ 3 * VTX_DWORD_COUNT + 1));
OUT_RING(RADEON_CP_VC_FRMT_XY |
RADEON_CP_VC_FRMT_ST0);
- OUT_RING(RADEON_CP_VC_CNTL_PRIM_TYPE_TRI_FAN |
+ OUT_RING(RADEON_CP_VC_CNTL_PRIM_TYPE_RECT_LIST |
RADEON_CP_VC_CNTL_PRIM_WALK_RING |
RADEON_CP_VC_CNTL_MAOS_ENABLE |
RADEON_CP_VC_CNTL_VTX_FMT_RADEON_MODE |
- (4 << RADEON_CP_VC_CNTL_NUM_SHIFT));
+ (3 << RADEON_CP_VC_CNTL_NUM_SHIFT));
} else {
if (IS_R300_3D || IS_R500_3D)
BEGIN_RING(4 * VTX_DWORD_COUNT + 4);
@@ -599,30 +604,33 @@ FUNC_NAME(RADEONDisplayTexturedVideo)(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv
BEGIN_RING(4 * VTX_DWORD_COUNT + 2);
OUT_RING(CP_PACKET3(R200_CP_PACKET3_3D_DRAW_IMMD_2,
4 * VTX_DWORD_COUNT));
- OUT_RING(RADEON_CP_VC_CNTL_PRIM_TYPE_TRI_FAN |
+ OUT_RING(RADEON_CP_VC_CNTL_PRIM_TYPE_QUAD_LIST |
RADEON_CP_VC_CNTL_PRIM_WALK_RING |
(4 << RADEON_CP_VC_CNTL_NUM_SHIFT));
}
#else /* ACCEL_CP */
if (IS_R300_3D || IS_R500_3D)
BEGIN_VIDEO(2 + VTX_DWORD_COUNT * 4);
+ else if (info->ChipFamily < CHIP_FAMILY_R200)
+ BEGIN_VIDEO(1 + VTX_DWORD_COUNT * 3);
else
BEGIN_VIDEO(1 + VTX_DWORD_COUNT * 4);
if (info->ChipFamily < CHIP_FAMILY_R200) {
- OUT_VIDEO_REG(RADEON_SE_VF_CNTL, (RADEON_VF_PRIM_TYPE_TRIANGLE_FAN |
+ OUT_VIDEO_REG(RADEON_SE_VF_CNTL, (RADEON_VF_PRIM_TYPE_RECTANGLE_LIST |
RADEON_VF_PRIM_WALK_DATA |
RADEON_VF_RADEON_MODE |
- 4 << RADEON_VF_NUM_VERTICES_SHIFT));
+ (3 << RADEON_VF_NUM_VERTICES_SHIFT)));
} else {
OUT_VIDEO_REG(RADEON_SE_VF_CNTL, (RADEON_VF_PRIM_TYPE_QUAD_LIST |
RADEON_VF_PRIM_WALK_DATA |
- 4 << RADEON_VF_NUM_VERTICES_SHIFT));
+ (4 << RADEON_VF_NUM_VERTICES_SHIFT)));
}
#endif
-
- VTX_OUT((float)dstX, (float)dstY,
- xFixedToFloat(srcTopLeft.x) / info->texW[0], xFixedToFloat(srcTopLeft.y) / info->texH[0]);
+ if (info->ChipFamily >= CHIP_FAMILY_R200) {
+ VTX_OUT((float)dstX, (float)dstY,
+ xFixedToFloat(srcTopLeft.x) / info->texW[0], xFixedToFloat(srcTopLeft.y) / info->texH[0]);
+ }
VTX_OUT((float)dstX, (float)(dstY + dsth),
xFixedToFloat(srcBottomLeft.x) / info->texW[0], xFixedToFloat(srcBottomLeft.y) / info->texH[0]);
VTX_OUT((float)(dstX + dstw), (float)(dstY + dsth),
diff --git a/src/radeon_tv.c b/src/radeon_tv.c
index 90020b3..90d1ac9 100644
--- a/src/radeon_tv.c
+++ b/src/radeon_tv.c
@@ -140,7 +140,7 @@ static const uint16_t vert_timing_PAL[] =
**********************************************************************/
static const TVModeConstants availableTVModes[] =
{
- {
+ { /* NTSC timing for 27 Mhz ref clk */
800, /* horResolution */
600, /* verResolution */
TV_STD_NTSC, /* standard */
@@ -155,7 +155,7 @@ static const TVModeConstants availableTVModes[] =
4, /* crtcPLL_postDiv */
1022, /* pixToTV */
},
- {
+ { /* PAL timing for 27 Mhz ref clk */
800, /* horResolution */
600, /* verResolution */
TV_STD_PAL, /* standard */
@@ -169,7 +169,22 @@ static const TVModeConstants availableTVModes[] =
231, /* crtcPLL_M */
4, /* crtcPLL_postDiv */
759, /* pixToTV */
- }
+ },
+ { /* NTSC timing for 14 Mhz ref clk */
+ 800, /* horResolution */
+ 600, /* verResolution */
+ TV_STD_NTSC, /* standard */
+ 1018, /* horTotal */
+ 727, /* verTotal */
+ 813, /* horStart */
+ 840, /* horSyncStart */
+ 633, /* verSyncStart */
+ 630627, /* defRestart */
+ 347, /* crtcPLL_N */
+ 14, /* crtcPLL_M */
+ 8, /* crtcPLL_postDiv */
+ 1022, /* pixToTV */
+ },
};
#define N_AVAILABLE_MODES (sizeof(availableModes) / sizeof(availableModes[ 0 ]))
@@ -582,6 +597,8 @@ static Bool RADEONInitTVRestarts(xf86OutputPtr output, RADEONSavePtr save,
DisplayModePtr mode)
{
RADEONOutputPrivatePtr radeon_output = output->driver_private;
+ RADEONInfoPtr info = RADEONPTR(output->scrn);
+ RADEONPLLPtr pll = &info->pll;
int restart;
unsigned hTotal;
unsigned vTotal;
@@ -597,14 +614,21 @@ static Bool RADEONInitTVRestarts(xf86OutputPtr output, RADEONSavePtr save,
/* FIXME: need to revisit this when we add more modes */
if (radeon_output->tvStd == TV_STD_NTSC ||
radeon_output->tvStd == TV_STD_NTSC_J ||
- radeon_output->tvStd == TV_STD_PAL_M)
- constPtr = &availableTVModes[0];
- else
- constPtr = &availableTVModes[1];
+ radeon_output->tvStd == TV_STD_PAL_M) {
+ if (pll->reference_freq == 2700)
+ constPtr = &availableTVModes[0];
+ else
+ constPtr = &availableTVModes[2];
+ } else {
+ if (pll->reference_freq == 2700)
+ constPtr = &availableTVModes[1];
+ else
+ constPtr = &availableTVModes[1]; /* FIXME */
+ }
hTotal = constPtr->horTotal;
vTotal = constPtr->verTotal;
-
+
if (radeon_output->tvStd == TV_STD_NTSC ||
radeon_output->tvStd == TV_STD_NTSC_J ||
radeon_output->tvStd == TV_STD_PAL_M ||
@@ -696,6 +720,8 @@ void RADEONInitTVRegisters(xf86OutputPtr output, RADEONSavePtr save,
ScrnInfoPtr pScrn = output->scrn;
RADEONOutputPrivatePtr radeon_output = output->driver_private;
RADEONInfoPtr info = RADEONPTR(pScrn);
+ RADEONPLLPtr pll = &info->pll;
+ unsigned m, n, p;
unsigned i;
unsigned long vert_space, flicker_removal;
uint32_t tmp;
@@ -703,14 +729,20 @@ void RADEONInitTVRegisters(xf86OutputPtr output, RADEONSavePtr save,
const uint16_t *hor_timing;
const uint16_t *vert_timing;
-
/* FIXME: need to revisit this when we add more modes */
if (radeon_output->tvStd == TV_STD_NTSC ||
radeon_output->tvStd == TV_STD_NTSC_J ||
- radeon_output->tvStd == TV_STD_PAL_M)
- constPtr = &availableTVModes[0];
- else
- constPtr = &availableTVModes[1];
+ radeon_output->tvStd == TV_STD_PAL_M) {
+ if (pll->reference_freq == 2700)
+ constPtr = &availableTVModes[0];
+ else
+ constPtr = &availableTVModes[2];
+ } else {
+ if (pll->reference_freq == 2700)
+ constPtr = &availableTVModes[1];
+ else
+ constPtr = &availableTVModes[1]; /* FIXME */
+ }
save->tv_crc_cntl = 0;
@@ -796,7 +828,10 @@ void RADEONInitTVRegisters(xf86OutputPtr output, RADEONSavePtr save,
save->tv_vscaler_cntl1 = RADEON_Y_W_EN;
save->tv_vscaler_cntl1 =
(save->tv_vscaler_cntl1 & 0xe3ff0000) | (vert_space * (1 << FRAC_BITS) / 10000);
- save->tv_vscaler_cntl1 |= RADEON_RESTART_FIELD;
+
+ if (pll->reference_freq == 2700)
+ save->tv_vscaler_cntl1 |= RADEON_RESTART_FIELD;
+
if (constPtr->horResolution == 1024)
save->tv_vscaler_cntl1 |= (4 << RADEON_Y_DEL_W_SIG_SHIFT);
else
@@ -873,18 +908,33 @@ void RADEONInitTVRegisters(xf86OutputPtr output, RADEONSavePtr save,
#endif
if (radeon_output->tvStd == TV_STD_NTSC ||
- radeon_output->tvStd == TV_STD_NTSC_J)
- save->tv_pll_cntl = (NTSC_TV_PLL_M & RADEON_TV_M0LO_MASK) |
- (((NTSC_TV_PLL_M >> 8) & RADEON_TV_M0HI_MASK) << RADEON_TV_M0HI_SHIFT) |
- ((NTSC_TV_PLL_N & RADEON_TV_N0LO_MASK) << RADEON_TV_N0LO_SHIFT) |
- (((NTSC_TV_PLL_N >> 9) & RADEON_TV_N0HI_MASK) << RADEON_TV_N0HI_SHIFT) |
- ((NTSC_TV_PLL_P & RADEON_TV_P_MASK) << RADEON_TV_P_SHIFT);
- else
- save->tv_pll_cntl = (PAL_TV_PLL_M & RADEON_TV_M0LO_MASK) |
- (((PAL_TV_PLL_M >> 8) & RADEON_TV_M0HI_MASK) << RADEON_TV_M0HI_SHIFT) |
- ((PAL_TV_PLL_N & RADEON_TV_N0LO_MASK) << RADEON_TV_N0LO_SHIFT) |
- (((PAL_TV_PLL_N >> 9) & RADEON_TV_N0HI_MASK) << RADEON_TV_N0HI_SHIFT) |
- ((PAL_TV_PLL_P & RADEON_TV_P_MASK) << RADEON_TV_P_SHIFT);
+ radeon_output->tvStd == TV_STD_NTSC_J) {
+ if (pll->reference_freq == 2700) {
+ m = NTSC_TV_PLL_M_27;
+ n = NTSC_TV_PLL_N_27;
+ p = NTSC_TV_PLL_P_27;
+ } else {
+ m = NTSC_TV_PLL_M_14;
+ n = NTSC_TV_PLL_N_14;
+ p = NTSC_TV_PLL_P_14;
+ }
+ } else {
+ if (pll->reference_freq == 2700) {
+ m = PAL_TV_PLL_M_27;
+ n = PAL_TV_PLL_N_27;
+ p = PAL_TV_PLL_P_27;
+ } else {
+ /* FIXME */
+ m = PAL_TV_PLL_M_27;
+ n = PAL_TV_PLL_N_27;
+ p = PAL_TV_PLL_P_27;
+ }
+ }
+ save->tv_pll_cntl = (m & RADEON_TV_M0LO_MASK) |
+ (((m >> 8) & RADEON_TV_M0HI_MASK) << RADEON_TV_M0HI_SHIFT) |
+ ((n & RADEON_TV_N0LO_MASK) << RADEON_TV_N0LO_SHIFT) |
+ (((n >> 9) & RADEON_TV_N0HI_MASK) << RADEON_TV_N0HI_SHIFT) |
+ ((p & RADEON_TV_P_MASK) << RADEON_TV_P_SHIFT);
save->tv_pll_cntl1 = (((4 & RADEON_TVPCP_MASK)<< RADEON_TVPCP_SHIFT) |
((4 & RADEON_TVPVG_MASK) << RADEON_TVPVG_SHIFT) |
@@ -999,14 +1049,23 @@ void RADEONAdjustCrtcRegistersForTV(ScrnInfoPtr pScrn, RADEONSavePtr save,
{
const TVModeConstants *constPtr;
RADEONOutputPrivatePtr radeon_output = output->driver_private;
+ RADEONInfoPtr info = RADEONPTR(pScrn);
+ RADEONPLLPtr pll = &info->pll;
/* FIXME: need to revisit this when we add more modes */
if (radeon_output->tvStd == TV_STD_NTSC ||
radeon_output->tvStd == TV_STD_NTSC_J ||
- radeon_output->tvStd == TV_STD_PAL_M)
- constPtr = &availableTVModes[0];
- else
- constPtr = &availableTVModes[1];
+ radeon_output->tvStd == TV_STD_PAL_M) {
+ if (pll->reference_freq == 2700)
+ constPtr = &availableTVModes[0];
+ else
+ constPtr = &availableTVModes[2];
+ } else {
+ if (pll->reference_freq == 2700)
+ constPtr = &availableTVModes[1];
+ else
+ constPtr = &availableTVModes[1]; /* FIXME */
+ }
save->crtc_h_total_disp = (((constPtr->horResolution / 8) - 1) << RADEON_CRTC_H_DISP_SHIFT) |
(((constPtr->horTotal / 8) - 1) << RADEON_CRTC_H_TOTAL_SHIFT);
@@ -1030,14 +1089,23 @@ void RADEONAdjustPLLRegistersForTV(ScrnInfoPtr pScrn, RADEONSavePtr save,
unsigned postDiv;
const TVModeConstants *constPtr;
RADEONOutputPrivatePtr radeon_output = output->driver_private;
+ RADEONInfoPtr info = RADEONPTR(pScrn);
+ RADEONPLLPtr pll = &info->pll;
/* FIXME: need to revisit this when we add more modes */
if (radeon_output->tvStd == TV_STD_NTSC ||
radeon_output->tvStd == TV_STD_NTSC_J ||
- radeon_output->tvStd == TV_STD_PAL_M)
- constPtr = &availableTVModes[0];
- else
- constPtr = &availableTVModes[1];
+ radeon_output->tvStd == TV_STD_PAL_M) {
+ if (pll->reference_freq == 2700)
+ constPtr = &availableTVModes[0];
+ else
+ constPtr = &availableTVModes[2];
+ } else {
+ if (pll->reference_freq == 2700)
+ constPtr = &availableTVModes[1];
+ else
+ constPtr = &availableTVModes[1]; /* FIXME */
+ }
save->htotal_cntl = (constPtr->horTotal & 0x7 /*0xf*/) | RADEON_HTOT_CNTL_VGA_EN;
@@ -1083,14 +1151,23 @@ void RADEONAdjustCrtc2RegistersForTV(ScrnInfoPtr pScrn, RADEONSavePtr save,
{
const TVModeConstants *constPtr;
RADEONOutputPrivatePtr radeon_output = output->driver_private;
+ RADEONInfoPtr info = RADEONPTR(pScrn);
+ RADEONPLLPtr pll = &info->pll;
/* FIXME: need to revisit this when we add more modes */
if (radeon_output->tvStd == TV_STD_NTSC ||
radeon_output->tvStd == TV_STD_NTSC_J ||
- radeon_output->tvStd == TV_STD_PAL_M)
- constPtr = &availableTVModes[0];
- else
- constPtr = &availableTVModes[1];
+ radeon_output->tvStd == TV_STD_PAL_M) {
+ if (pll->reference_freq == 2700)
+ constPtr = &availableTVModes[0];
+ else
+ constPtr = &availableTVModes[2];
+ } else {
+ if (pll->reference_freq == 2700)
+ constPtr = &availableTVModes[1];
+ else
+ constPtr = &availableTVModes[1]; /* FIXME */
+ }
save->crtc2_h_total_disp = (((constPtr->horResolution / 8) - 1) << RADEON_CRTC_H_DISP_SHIFT) |
(((constPtr->horTotal / 8) - 1) << RADEON_CRTC_H_TOTAL_SHIFT);
@@ -1114,14 +1191,23 @@ void RADEONAdjustPLL2RegistersForTV(ScrnInfoPtr pScrn, RADEONSavePtr save,
unsigned postDiv;
const TVModeConstants *constPtr;
RADEONOutputPrivatePtr radeon_output = output->driver_private;
+ RADEONInfoPtr info = RADEONPTR(pScrn);
+ RADEONPLLPtr pll = &info->pll;
/* FIXME: need to revisit this when we add more modes */
if (radeon_output->tvStd == TV_STD_NTSC ||
radeon_output->tvStd == TV_STD_NTSC_J ||
- radeon_output->tvStd == TV_STD_PAL_M)
- constPtr = &availableTVModes[0];
- else
- constPtr = &availableTVModes[1];
+ radeon_output->tvStd == TV_STD_PAL_M) {
+ if (pll->reference_freq == 2700)
+ constPtr = &availableTVModes[0];
+ else
+ constPtr = &availableTVModes[2];
+ } else {
+ if (pll->reference_freq == 2700)
+ constPtr = &availableTVModes[1];
+ else
+ constPtr = &availableTVModes[1]; /* FIXME */
+ }
save->htotal_cntl2 = (constPtr->horTotal & 0x7); /* 0xf */
diff --git a/src/radeon_tv.h b/src/radeon_tv.h
index c4b7838..8d77a77 100644
--- a/src/radeon_tv.h
+++ b/src/radeon_tv.h
@@ -27,24 +27,31 @@
#define MAX_H_SIZE 5 /* Range: [-5..5], negative is smaller, positive is larger */
/* tv standard constants */
-#define NTSC_TV_PLL_M 22
-#define NTSC_TV_PLL_N 175
-#define NTSC_TV_PLL_P 5
#define NTSC_TV_CLOCK_T 233
#define NTSC_TV_VFTOTAL 1
#define NTSC_TV_LINES_PER_FRAME 525
#define NTSC_TV_ZERO_H_SIZE 479166
#define NTSC_TV_H_SIZE_UNIT 9478
-#define PAL_TV_PLL_M 113
-#define PAL_TV_PLL_N 668
-#define PAL_TV_PLL_P 3
#define PAL_TV_CLOCK_T 188
#define PAL_TV_VFTOTAL 3
#define PAL_TV_LINES_PER_FRAME 625
#define PAL_TV_ZERO_H_SIZE 473200
#define PAL_TV_H_SIZE_UNIT 9360
+/* tv pll setting for 27 mhz ref clk */
+#define NTSC_TV_PLL_M_27 22
+#define NTSC_TV_PLL_N_27 175
+#define NTSC_TV_PLL_P_27 5
+
+#define PAL_TV_PLL_M_27 113
+#define PAL_TV_PLL_N_27 668
+#define PAL_TV_PLL_P_27 3
+
+/* tv pll setting for 14 mhz ref clk */
+#define NTSC_TV_PLL_M_14 33
+#define NTSC_TV_PLL_N_14 693
+#define NTSC_TV_PLL_P_14 7
#define VERT_LEAD_IN_LINES 2
#define FRAC_BITS 0xe
diff --git a/src/radeon_version.h b/src/radeon_version.h
index ccc1367..5717ead 100644
--- a/src/radeon_version.h
+++ b/src/radeon_version.h
@@ -39,10 +39,9 @@
#define R200_DRIVER_NAME "r200"
#define R300_DRIVER_NAME "r300"
-#define RADEON_VERSION_MAJOR 4
-#define RADEON_VERSION_MAJOR_TILED 5
-#define RADEON_VERSION_MINOR 3
-#define RADEON_VERSION_PATCH 0
+#define RADEON_VERSION_MAJOR PACKAGE_VERSION_MAJOR
+#define RADEON_VERSION_MINOR PACKAGE_VERSION_MINOR
+#define RADEON_VERSION_PATCH PACKAGE_VERSION_PATCHLEVEL
#ifndef RADEON_VERSION_EXTRA
#define RADEON_VERSION_EXTRA ""