Blob Blame History Raw
diff --git a/src/drmmode_display.c b/src/drmmode_display.c
index f82dec8..a1ec2c2 100644
--- a/src/drmmode_display.c
+++ b/src/drmmode_display.c
@@ -449,7 +449,7 @@ drmmode_crtc_shadow_create(xf86CrtcPtr crtc, void *data, int width, int height)
 					       pScrn->depth,
 					       pScrn->bitsPerPixel,
 					       rotate_pitch,
-					       data);
+					       NULL);
 
 	if (rotate_pixmap == NULL) {
 		xf86DrvMsg(pScrn->scrnIndex, X_ERROR,
diff --git a/src/legacy_output.c b/src/legacy_output.c
index 73c86b9..186cd25 100644
--- a/src/legacy_output.c
+++ b/src/legacy_output.c
@@ -1521,7 +1521,7 @@ RADEONInitTvDacCntl(xf86OutputPtr output, RADEONSavePtr save)
 			       R420_TV_DAC_DACADJ_MASK |
 			       R420_TV_DAC_RDACPD |
 			       R420_TV_DAC_GDACPD |
-			       R420_TV_DAC_GDACPD |
+			       R420_TV_DAC_BDACPD |
 			       R420_TV_DAC_TVENABLE);
     } else {
 	save->tv_dac_cntl = info->SavedReg->tv_dac_cntl &
@@ -1530,7 +1530,7 @@ RADEONInitTvDacCntl(xf86OutputPtr output, RADEONSavePtr save)
 			       RADEON_TV_DAC_DACADJ_MASK |
 			       RADEON_TV_DAC_RDACPD |
 			       RADEON_TV_DAC_GDACPD |
-			       RADEON_TV_DAC_GDACPD);
+			       RADEON_TV_DAC_BDACPD);
     }
 
     save->tv_dac_cntl |= (RADEON_TV_DAC_NBLANK |
diff --git a/src/radeon_pm.c b/src/radeon_pm.c
index fe8f214..d5152c8 100644
--- a/src/radeon_pm.c
+++ b/src/radeon_pm.c
@@ -226,7 +226,7 @@ static void LegacySetClockGating(ScrnInfoPtr pScrn, Bool enable)
 			R300_PIXCLK_TRANS_ALWAYS_ONb      |
 			R300_PIXCLK_TVO_ALWAYS_ONb        |
 			R300_P2G2CLK_ALWAYS_ONb           |
-			R300_P2G2CLK_ALWAYS_ONb);
+			R300_P2G2CLK_DAC_ALWAYS_ONb);
 		OUTPLL(pScrn, RADEON_PIXCLKS_CNTL, tmp);
 	    } else if (info->ChipFamily >= CHIP_FAMILY_RV350) {
 		tmp = INPLL(pScrn, R300_SCLK_CNTL2);
@@ -273,7 +273,7 @@ static void LegacySetClockGating(ScrnInfoPtr pScrn, Bool enable)
 			R300_PIXCLK_TRANS_ALWAYS_ONb      |
 			R300_PIXCLK_TVO_ALWAYS_ONb        |
 			R300_P2G2CLK_ALWAYS_ONb           |
-			R300_P2G2CLK_ALWAYS_ONb);
+			R300_P2G2CLK_DAC_ALWAYS_ONb);
 		OUTPLL(pScrn, RADEON_PIXCLKS_CNTL, tmp);
 
 		tmp = INPLL(pScrn, RADEON_MCLK_MISC);
@@ -454,8 +454,8 @@ static void LegacySetClockGating(ScrnInfoPtr pScrn, Bool enable)
 		     RADEON_PIXCLK_TMDS_ALWAYS_ONb     |
 		     R300_PIXCLK_TRANS_ALWAYS_ONb      |
 		     R300_PIXCLK_TVO_ALWAYS_ONb        |
-		     R300_P2G2CLK_ALWAYS_ONb            |
 		     R300_P2G2CLK_ALWAYS_ONb           |
+		     R300_P2G2CLK_DAC_ALWAYS_ONb       |
 		     R300_DISP_DAC_PIXCLK_DAC2_BLANK_OFF);
 	    OUTPLL(pScrn, RADEON_PIXCLKS_CNTL, tmp);
 	} else if (info->ChipFamily >= CHIP_FAMILY_RV350) {
@@ -507,8 +507,8 @@ static void LegacySetClockGating(ScrnInfoPtr pScrn, Bool enable)
 		     RADEON_PIXCLK_TMDS_ALWAYS_ONb     |
 		     R300_PIXCLK_TRANS_ALWAYS_ONb      |
 		     R300_PIXCLK_TVO_ALWAYS_ONb        |
-		     R300_P2G2CLK_ALWAYS_ONb            |
 		     R300_P2G2CLK_ALWAYS_ONb           |
+		     R300_P2G2CLK_DAC_ALWAYS_ONb       |
 		     R300_DISP_DAC_PIXCLK_DAC2_BLANK_OFF);
 	    OUTPLL(pScrn, RADEON_PIXCLKS_CNTL, tmp);
 	}  else {