From 3c08742aad802157134c6d5f5312dc80d8863585 Mon Sep 17 00:00:00 2001 From: Dave Airlie Date: Dec 02 2008 09:13:33 +0000 Subject: - radeon-modeset.patch: fix some DFS issues on r5xx - better fix for rs4xx --- diff --git a/radeon-modeset.patch b/radeon-modeset.patch index 81ed4db..3f5a20a 100644 --- a/radeon-modeset.patch +++ b/radeon-modeset.patch @@ -1,3 +1,23 @@ +commit c14f510c877c5ccfb38ebc11b910891a4bcf40ba +Author: Dave Airlie +Date: Mon Dec 1 15:31:08 2008 +1100 + + radeon: don't have 2D and 3D in one CS buffer + +commit 73b6e729a09421f759a8c0e55ef830ab6bb2be84 +Author: Dave Airlie +Date: Wed Nov 26 16:09:29 2008 +1100 + + radeon: set touched flag on pinned buffers + +commit 5f3d3de0fbe755177109d1ab308266b423db1ae6 +Author: Dave Airlie +Date: Wed Nov 26 16:04:35 2008 +1100 + + radeon: fix up some of the touched by gpu handling and force gtt handling + + this fixes DFS on the rs690 + commit 969fb5d72094a2a7b6a2ad40a80a8ed93d6c8193 Author: Dave Airlie Date: Wed Nov 26 12:52:24 2008 +1100 @@ -2454,10 +2474,10 @@ index 0000000..481c5cf +#endif diff --git a/src/radeon_bufmgr_gem.c b/src/radeon_bufmgr_gem.c new file mode 100644 -index 0000000..30f439f +index 0000000..7508dd7 --- /dev/null +++ b/src/radeon_bufmgr_gem.c -@@ -0,0 +1,649 @@ +@@ -0,0 +1,656 @@ +/************************************************************************** + * + * Copyright © 2007-2008 Red Hat Inc. @@ -2702,6 +2722,9 @@ index 0000000..30f439f + dri_bo_gem *gem_bo = (dri_bo_gem *)buf; + int ret; + ++ if (!gem_bo->touched) ++ return; ++ + /* do a set domain */ + if (gem_bo->force_gtt) { + sd_args.handle = gem_bo->gem_handle; @@ -2744,6 +2767,8 @@ index 0000000..30f439f + bo_gem->pinned = 1; + bo_gem->gem_handle = handle; + bo_gem->in_vram = 1; ++ /* if we get from kernel assume touched */ ++ bo_gem->touched = 1; + + bo_gem->next = bufmgr_gem->bo_list; + bufmgr_gem->bo_list = bo_gem; @@ -2869,7 +2894,7 @@ index 0000000..30f439f + int ret; + + if (domain == RADEON_GEM_DOMAIN_VRAM) -+ gem_bo->in_vram = 1; ++ gem_bo->in_vram = 1; + + pin.pin_domain = domain; + pin.handle = gem_bo->gem_handle; @@ -2879,6 +2904,8 @@ index 0000000..30f439f + if (ret != 0) + return -1; + ++ /* pinned buffers are considered touched */ ++ gem_bo->touched = 1; + gem_bo->pinned = 1; + return 0; +} @@ -3098,7 +3125,7 @@ index 0000000..30f439f +{ + dri_bo_gem *gem_bo = (dri_bo_gem *)buf; + -+ if (!gem_bo->pinned) ++ if (!gem_bo->pinned && !gem_bo->force_gtt) + gem_bo->force_gtt = 1; +} + @@ -6022,7 +6049,7 @@ index 66cefb7..af7d382 100644 + #endif diff --git a/src/radeon_exa.c b/src/radeon_exa.c -index 0f86fdd..f0d1f48 100644 +index 0f86fdd..9fb0f75 100644 --- a/src/radeon_exa.c +++ b/src/radeon_exa.c @@ -43,7 +43,11 @@ @@ -6130,7 +6157,7 @@ index 0f86fdd..f0d1f48 100644 /* Front buffer is always set with proper swappers */ if (offset == 0) return; -@@ -291,14 +341,97 @@ static void RADEONFinishAccess(PixmapPtr pPix, int index) +@@ -291,42 +341,124 @@ static void RADEONFinishAccess(PixmapPtr pPix, int index) OUTREG(RADEON_SURFACE0_LOWER_BOUND + soff, 0); OUTREG(RADEON_SURFACE0_UPPER_BOUND + soff, 0); swapper_surfaces[index] = 0; @@ -6227,47 +6254,50 @@ index 0f86fdd..f0d1f48 100644 do { \ - uint32_t wait_until = 0; \ - BEGIN_ACCEL(1); \ -+ uint32_t wait_until = 0; \ ++ uint32_t flush = 0; \ switch (info->accel_state->engineMode) { \ case EXA_ENGINEMODE_UNKNOWN: \ - wait_until |= RADEON_WAIT_HOST_IDLECLEAN | RADEON_WAIT_2D_IDLECLEAN; \ -@@ -307,15 +440,17 @@ do { \ +- wait_until |= RADEON_WAIT_HOST_IDLECLEAN | RADEON_WAIT_2D_IDLECLEAN; \ + case EXA_ENGINEMODE_3D: \ +- wait_until |= RADEON_WAIT_3D_IDLECLEAN; \ ++ flush = 1; \ case EXA_ENGINEMODE_2D: \ break; \ } \ - OUT_ACCEL_REG(RADEON_WAIT_UNTIL, wait_until); \ - FINISH_ACCEL(); \ -+ if (wait_until) { \ -+ BEGIN_ACCEL(1); \ -+ OUT_ACCEL_REG(RADEON_WAIT_UNTIL, wait_until); \ -+ FINISH_ACCEL(); \ +- info->accel_state->engineMode = EXA_ENGINEMODE_2D; \ ++ if (flush) { \ ++ RADEONCPFlushIndirect(pScrn, 1); \ + } \ - info->accel_state->engineMode = EXA_ENGINEMODE_2D; \ ++ info->accel_state->engineMode = EXA_ENGINEMODE_2D; \ } while (0); #define RADEON_SWITCH_TO_3D() \ do { \ - uint32_t wait_until = 0; \ - BEGIN_ACCEL(1); \ -+ uint32_t wait_until = 0; \ ++ uint32_t flush = 0; \ switch (info->accel_state->engineMode) { \ case EXA_ENGINEMODE_UNKNOWN: \ - wait_until |= RADEON_WAIT_HOST_IDLECLEAN | RADEON_WAIT_3D_IDLECLEAN; \ -@@ -324,8 +459,11 @@ do { \ +- wait_until |= RADEON_WAIT_HOST_IDLECLEAN | RADEON_WAIT_3D_IDLECLEAN; \ + case EXA_ENGINEMODE_2D: \ +- wait_until |= RADEON_WAIT_2D_IDLECLEAN | RADEON_WAIT_DMA_GUI_IDLE; \ ++ flush = 1; \ case EXA_ENGINEMODE_3D: \ break; \ } \ - OUT_ACCEL_REG(RADEON_WAIT_UNTIL, wait_until); \ - FINISH_ACCEL(); \ -+ if (wait_until) { \ -+ BEGIN_ACCEL(1); \ -+ OUT_ACCEL_REG(RADEON_WAIT_UNTIL, wait_until); \ -+ FINISH_ACCEL(); \ +- info->accel_state->engineMode = EXA_ENGINEMODE_3D; \ ++ if (flush) { \ ++ RADEONCPFlushIndirect(pScrn, 1); \ + } \ - info->accel_state->engineMode = EXA_ENGINEMODE_3D; \ ++ info->accel_state->engineMode = EXA_ENGINEMODE_3D; \ } while (0); -@@ -338,6 +476,7 @@ do { \ + #define ENTER_DRAW(x) TRACE +@@ -338,6 +470,7 @@ do { \ #define BEGIN_ACCEL(n) RADEONWaitForFifo(pScrn, (n)) #define OUT_ACCEL_REG(reg, val) OUTREG(reg, val) #define OUT_ACCEL_REG_F(reg, val) OUTREG(reg, F_TO_DW(val)) @@ -6275,7 +6305,7 @@ index 0f86fdd..f0d1f48 100644 #define FINISH_ACCEL() #ifdef RENDER -@@ -351,6 +490,7 @@ do { \ +@@ -351,6 +484,7 @@ do { \ #undef OUT_ACCEL_REG #undef OUT_ACCEL_REG_F #undef FINISH_ACCEL @@ -6283,7 +6313,7 @@ index 0f86fdd..f0d1f48 100644 #ifdef XF86DRI -@@ -361,6 +501,7 @@ do { \ +@@ -361,6 +495,7 @@ do { \ #define BEGIN_ACCEL(n) BEGIN_RING(2*(n)) #define OUT_ACCEL_REG(reg, val) OUT_RING_REG(reg, val) #define FINISH_ACCEL() ADVANCE_RING() @@ -6291,7 +6321,7 @@ index 0f86fdd..f0d1f48 100644 #define OUT_RING_F(x) OUT_RING(F_TO_DW(x)) -@@ -378,6 +519,8 @@ do { \ +@@ -378,6 +513,8 @@ do { \ #endif /* XF86DRI */ @@ -6300,7 +6330,7 @@ index 0f86fdd..f0d1f48 100644 /* * Once screen->off_screen_base is set, this function * allocates the remaining memory appropriately -@@ -399,122 +542,126 @@ Bool RADEONSetupMemEXA (ScreenPtr pScreen) +@@ -399,122 +536,126 @@ Bool RADEONSetupMemEXA (ScreenPtr pScreen) if (info->accel_state->exa == NULL) return FALSE; @@ -6530,7 +6560,7 @@ index 0f86fdd..f0d1f48 100644 return TRUE; } -@@ -527,10 +674,21 @@ extern void ExaOffscreenMarkUsed(PixmapPtr); +@@ -527,10 +668,21 @@ extern void ExaOffscreenMarkUsed(PixmapPtr); unsigned long long RADEONTexOffsetStart(PixmapPtr pPix) { @@ -7217,7 +7247,7 @@ index 62224d0..eba325e 100644 xf86DrvMsg(pScrn->scrnIndex, X_INFO, "Setting EXA maxPitchBytes\n"); diff --git a/src/radeon_exa_render.c b/src/radeon_exa_render.c -index 97199ae..0bc0c41 100644 +index 97199ae..5399906 100644 --- a/src/radeon_exa_render.c +++ b/src/radeon_exa_render.c @@ -54,6 +54,10 @@ @@ -7803,7 +7833,7 @@ index 97199ae..0bc0c41 100644 #ifdef ACCEL_CP ADVANCE_RING(); -@@ -2121,14 +2363,22 @@ static void FUNC_NAME(RadeonDoneComposite)(PixmapPtr pDst) +@@ -2121,14 +2363,24 @@ static void FUNC_NAME(RadeonDoneComposite)(PixmapPtr pDst) ENTER_DRAW(0); if (IS_R300_3D || IS_R500_3D) { @@ -7818,12 +7848,14 @@ index 97199ae..0bc0c41 100644 LEAVE_DRAW(0); + ++#if 0 + /* workaround hang on RS4xx and RS6xx chips */ + if(info->ChipFamily == CHIP_FAMILY_RS400 || + info->ChipFamily == CHIP_FAMILY_RS480 || + info->ChipFamily == CHIP_FAMILY_RS600 || + info->ChipFamily == CHIP_FAMILY_RS690) + RADEONCPFlushIndirect(pScrn, 1); ++#endif } #undef ONLY_ONCE diff --git a/xorg-x11-drv-ati.spec b/xorg-x11-drv-ati.spec index 2bad1c8..c70d32b 100644 --- a/xorg-x11-drv-ati.spec +++ b/xorg-x11-drv-ati.spec @@ -5,7 +5,7 @@ Summary: Xorg X11 ati video driver Name: xorg-x11-drv-ati Version: 6.9.0 -Release: 60%{?dist} +Release: 61%{?dist} URL: http://www.x.org License: MIT Group: User Interface/X Hardware Support @@ -86,6 +86,9 @@ rm -rf $RPM_BUILD_ROOT %{_mandir}/man4/radeon.4* %changelog +* Tue Dec 02 2008 Dave Airlie 6.9.0-61 +- radeon-modeset.patch: fix some DFS issues on r5xx - better fix for rs4xx + * Sun Nov 30 2008 Dave Airlie 6.9.0-60 - radeon-6.9.0-posting-fix.patch - add fix to post the second GPU properly