From 553af02c6be38a8a83be60ce9f2d75761e1dd6e7 Mon Sep 17 00:00:00 2001 From: Dave Airlie Date: Sep 26 2008 00:53:39 +0000 Subject: - rebase to a later tree - still not fully up to git master - add some fixes to the resize stuff - not fully done --- diff --git a/copy-fb-contents.patch b/copy-fb-contents.patch index 92411e0..8f65375 100644 --- a/copy-fb-contents.patch +++ b/copy-fb-contents.patch @@ -1,6 +1,7 @@ -diff -up xf86-video-ati-6.9.0/src/drmmode_display.c.copy-fb-contents xf86-video-ati-6.9.0/src/drmmode_display.c ---- xf86-video-ati-6.9.0/src/drmmode_display.c.copy-fb-contents 2008-09-19 15:46:48.000000000 -0400 -+++ xf86-video-ati-6.9.0/src/drmmode_display.c 2008-09-22 14:05:15.000000000 -0400 +diff --git a/src/drmmode_display.c b/src/drmmode_display.c +index 25e6183..a22cd62 100644 +--- a/src/drmmode_display.c ++++ b/src/drmmode_display.c @@ -31,8 +31,11 @@ #ifdef XF86DRM_MODE @@ -13,7 +14,7 @@ diff -up xf86-video-ati-6.9.0/src/drmmode_display.c.copy-fb-contents xf86-video- static Bool drmmode_resize_fb(ScrnInfoPtr scrn, drmmode_ptr drmmode, int width, int height); static Bool -@@ -119,6 +122,76 @@ drmmode_crtc_dpms(xf86CrtcPtr drmmode_cr +@@ -119,6 +122,76 @@ drmmode_crtc_dpms(xf86CrtcPtr drmmode_crtc, int mode) } @@ -90,28 +91,34 @@ diff -up xf86-video-ati-6.9.0/src/drmmode_display.c.copy-fb-contents xf86-video- static Bool drmmode_set_mode_major(xf86CrtcPtr crtc, DisplayModePtr mode, Rotation rotation, int x, int y) -@@ -170,15 +243,14 @@ drmmode_set_mode_major(xf86CrtcPtr crtc, - - drmmode_ConvertToKMode(crtc->scrn, &kmode, mode); - -- +@@ -174,7 +247,8 @@ drmmode_set_mode_major(xf86CrtcPtr crtc, DisplayModePtr mode, fb_id = drmmode->fb_id; if (drmmode_crtc->rotate_fb_id) fb_id = drmmode_crtc->rotate_fb_id; - ErrorF("fb id is %d\n", fb_id); -+ copy_fb_contents (drmmode, crtc->scrn, fb_id, x, y, -+ drmmode_crtc->mode_crtc->buffer_id); ++ copy_fb_contents (drmmode, crtc->scrn, fb_id, x, y, ++ drmmode_crtc->mode_crtc->buffer_id); drmModeSetCrtc(drmmode->fd, drmmode_crtc->mode_crtc->crtc_id, fb_id, x, y, output_ids, output_count, &kmode); -- - done: - if (!ret) { - crtc->x = saved_x; -diff -up xf86-video-ati-6.9.0/src/radeon_bufmgr_gem.c.copy-fb-contents xf86-video-ati-6.9.0/src/radeon_bufmgr_gem.c ---- xf86-video-ati-6.9.0/src/radeon_bufmgr_gem.c.copy-fb-contents 2008-09-19 15:46:48.000000000 -0400 -+++ xf86-video-ati-6.9.0/src/radeon_bufmgr_gem.c 2008-09-19 15:46:48.000000000 -0400 -@@ -353,6 +353,27 @@ void radeon_bufmgr_gem_wait_rendering(dr +diff --git a/src/radeon_bufmgr.h b/src/radeon_bufmgr.h +index a16ad9a..b3034d7 100644 +--- a/src/radeon_bufmgr.h ++++ b/src/radeon_bufmgr.h +@@ -16,6 +16,8 @@ struct radeon_bufmgr { + dri_bufmgr *radeon_bufmgr_gem_init(int fd); + dri_bo *radeon_bo_gem_create_from_name(dri_bufmgr *bufmgr, const char *name, + unsigned int handle); ++dri_bo *radeon_bo_gem_create_from_handle(dri_bufmgr *bufmgr, ++ uint32_t handle, unsigned long size); + + void radeon_bufmgr_emit_reloc(dri_bo *buf, uint32_t *head, uint32_t *count_p, uint32_t read_domains, uint32_t write_domain); + +diff --git a/src/radeon_bufmgr_gem.c b/src/radeon_bufmgr_gem.c +index db28edc..75cff8e 100644 +--- a/src/radeon_bufmgr_gem.c ++++ b/src/radeon_bufmgr_gem.c +@@ -353,6 +353,27 @@ void radeon_bufmgr_gem_wait_rendering(dri_bo *buf) return; } @@ -139,7 +146,7 @@ diff -up xf86-video-ati-6.9.0/src/radeon_bufmgr_gem.c.copy-fb-contents xf86-vide /** * Returns a dri_bo wrapping the given buffer object handle. * -@@ -364,32 +385,20 @@ radeon_bo_gem_create_from_name(dri_bufmg +@@ -364,32 +385,20 @@ radeon_bo_gem_create_from_name(dri_bufmgr *bufmgr, const char *name, unsigned int handle) { dri_bufmgr_gem *bufmgr_gem = (dri_bufmgr_gem *)bufmgr; @@ -174,23 +181,11 @@ diff -up xf86-video-ati-6.9.0/src/radeon_bufmgr_gem.c.copy-fb-contents xf86-vide } #define BUF_OUT_RING(x) do { \ -diff -up xf86-video-ati-6.9.0/src/radeon_bufmgr_gem.h.copy-fb-contents xf86-video-ati-6.9.0/src/radeon_bufmgr_gem.h -diff -up xf86-video-ati-6.9.0/src/radeon_bufmgr.h.copy-fb-contents xf86-video-ati-6.9.0/src/radeon_bufmgr.h ---- xf86-video-ati-6.9.0/src/radeon_bufmgr.h.copy-fb-contents 2008-09-19 15:46:48.000000000 -0400 -+++ xf86-video-ati-6.9.0/src/radeon_bufmgr.h 2008-09-19 15:46:48.000000000 -0400 -@@ -16,6 +16,8 @@ struct radeon_bufmgr { - dri_bufmgr *radeon_bufmgr_gem_init(int fd); - dri_bo *radeon_bo_gem_create_from_name(dri_bufmgr *bufmgr, const char *name, - unsigned int handle); -+dri_bo *radeon_bo_gem_create_from_handle(dri_bufmgr *bufmgr, -+ uint32_t handle, unsigned long size); - - void radeon_bufmgr_emit_reloc(dri_bo *buf, uint32_t *head, uint32_t *count_p, uint32_t read_domains, uint32_t write_domain); - -diff -up xf86-video-ati-6.9.0/src/radeon_driver.c.copy-fb-contents xf86-video-ati-6.9.0/src/radeon_driver.c ---- xf86-video-ati-6.9.0/src/radeon_driver.c.copy-fb-contents 2008-09-19 15:46:48.000000000 -0400 -+++ xf86-video-ati-6.9.0/src/radeon_driver.c 2008-09-19 15:46:48.000000000 -0400 -@@ -3644,6 +3644,24 @@ Bool RADEONScreenInit(int scrnIndex, Scr +diff --git a/src/radeon_driver.c b/src/radeon_driver.c +index d5bb24d..070cc56 100644 +--- a/src/radeon_driver.c ++++ b/src/radeon_driver.c +@@ -3640,6 +3640,24 @@ Bool RADEONScreenInit(int scrnIndex, ScreenPtr pScreen, /* xf86CrtcRotate() accesses pScrn->pScreen */ pScrn->pScreen = pScreen; @@ -215,7 +210,7 @@ diff -up xf86-video-ati-6.9.0/src/radeon_driver.c.copy-fb-contents xf86-video-at if (!xf86SetDesiredModes (pScrn)) return FALSE; -@@ -3714,25 +3732,6 @@ Bool RADEONScreenInit(int scrnIndex, Scr +@@ -3710,25 +3728,6 @@ Bool RADEONScreenInit(int scrnIndex, ScreenPtr pScreen, RADEONChangeSurfaces(pScrn); } diff --git a/radeon-6.9.0-to-git.patch b/radeon-6.9.0-to-git.patch index eb117e1..d5f61ba 100644 --- a/radeon-6.9.0-to-git.patch +++ b/radeon-6.9.0-to-git.patch @@ -1149,6 +1149,736 @@ index 51be301..83b86a7 100644 if (radeon_output->DACType == DAC_PRIMARY) dac_data.sDacload.ucDacType = ATOM_DAC_A; else if (radeon_output->DACType == DAC_TVDAC) +diff --git a/src/bicubic_table.h b/src/bicubic_table.h +new file mode 100644 +index 0000000..765cfff +--- /dev/null ++++ b/src/bicubic_table.h +@@ -0,0 +1,646 @@ ++static const uint16_t bicubic_tex_512[] = { ++ 0xb266, 0x3c00, 0x3aaa, 0x3155, ++ 0xb287, 0x3bf0, 0x3aa2, 0x3175, ++ 0xb2a9, 0x3be0, 0x3a9a, 0x3196, ++ 0xb2cc, 0x3bd0, 0x3a92, 0x31b7, ++ 0xb2ee, 0x3bc0, 0x3a89, 0x31d9, ++ 0xb312, 0x3bb0, 0x3a81, 0x31fb, ++ 0xb335, 0x3ba0, 0x3a78, 0x321e, ++ 0xb359, 0x3b90, 0x3a6f, 0x3241, ++ 0xb37d, 0x3b80, 0x3a66, 0x3264, ++ 0xb3a2, 0x3b70, 0x3a5d, 0x3288, ++ 0xb3c7, 0x3b60, 0x3a54, 0x32ad, ++ 0xb3ed, 0x3b51, 0x3a4b, 0x32d1, ++ 0xb409, 0x3b41, 0x3a42, 0x32f7, ++ 0xb41c, 0x3b31, 0x3a38, 0x331c, ++ 0xb42f, 0x3b21, 0x3a2f, 0x3342, ++ 0xb443, 0x3b12, 0x3a25, 0x3369, ++ 0xb456, 0x3b02, 0x3a1c, 0x3390, ++ 0xb46a, 0x3af3, 0x3a12, 0x33b7, ++ 0xb47e, 0x3ae3, 0x3a08, 0x33de, ++ 0xb492, 0x3ad4, 0x39fe, 0x3403, ++ 0xb4a6, 0x3ac5, 0x39f4, 0x3417, ++ 0xb4bb, 0x3ab5, 0x39ea, 0x342b, ++ 0xb4cf, 0x3aa6, 0x39df, 0x3440, ++ 0xb4e4, 0x3a97, 0x39d5, 0x3454, ++ 0xb4f9, 0x3a88, 0x39cb, 0x3469, ++ 0xb50e, 0x3a79, 0x39c0, 0x347e, ++ 0xb523, 0x3a6a, 0x39b6, 0x3493, ++ 0xb539, 0x3a5a, 0x39ab, 0x34a8, ++ 0xb54e, 0x3a4c, 0x39a0, 0x34be, ++ 0xb564, 0x3a3d, 0x3996, 0x34d3, ++ 0xb57a, 0x3a2e, 0x398b, 0x34e9, ++ 0xb590, 0x3a1f, 0x3980, 0x34ff, ++ 0xb5a6, 0x3a10, 0x3975, 0x3515, ++ 0xb5bc, 0x3a02, 0x396a, 0x352b, ++ 0xb5d2, 0x39f3, 0x395f, 0x3541, ++ 0xb5e9, 0x39e4, 0x3954, 0x3557, ++ 0xb5ff, 0x39d6, 0x3948, 0x356e, ++ 0xb616, 0x39c7, 0x393d, 0x3584, ++ 0xb62d, 0x39b9, 0x3932, 0x359b, ++ 0xb644, 0x39ab, 0x3926, 0x35b2, ++ 0xb65b, 0x399c, 0x391b, 0x35c9, ++ 0xb672, 0x398e, 0x3910, 0x35df, ++ 0xb68a, 0x3980, 0x3904, 0x35f6, ++ 0xb6a1, 0x3972, 0x38f8, 0x360e, ++ 0xb6b9, 0x3964, 0x38ed, 0x3625, ++ 0xb6d1, 0x3956, 0x38e1, 0x363c, ++ 0xb6e8, 0x3948, 0x38d6, 0x3653, ++ 0xb700, 0x393a, 0x38ca, 0x366b, ++ 0xb719, 0x392c, 0x38be, 0x3682, ++ 0xb731, 0x391e, 0x38b2, 0x369a, ++ 0xb749, 0x3910, 0x38a7, 0x36b1, ++ 0xb762, 0x3902, 0x389b, 0x36c9, ++ 0xb77a, 0x38f5, 0x388f, 0x36e1, ++ 0xb793, 0x38e7, 0x3883, 0x36f8, ++ 0xb7ac, 0x38da, 0x3877, 0x3710, ++ 0xb7c5, 0x38cc, 0x386b, 0x3728, ++ 0xb7de, 0x38bf, 0x385f, 0x3740, ++ 0xb7f7, 0x38b1, 0x3853, 0x3758, ++ 0xb808, 0x38a4, 0x3847, 0x3770, ++ 0xb815, 0x3897, 0x383b, 0x3788, ++ 0xb821, 0x3889, 0x382f, 0x37a0, ++ 0xb82e, 0x387c, 0x3823, 0x37b8, ++ 0xb83b, 0x386f, 0x3817, 0x37d0, ++ 0xb848, 0x3862, 0x380b, 0x37e8, ++ 0xb855, 0x3855, 0x3800, 0x3800, ++ 0xb862, 0x3848, 0x37e8, 0x380b, ++ 0xb86f, 0x383b, 0x37d0, 0x3817, ++ 0xb87c, 0x382e, 0x37b8, 0x3823, ++ 0xb889, 0x3821, 0x37a0, 0x382f, ++ 0xb897, 0x3815, 0x3788, 0x383b, ++ 0xb8a4, 0x3808, 0x3770, 0x3847, ++ 0xb8b1, 0x37f7, 0x3758, 0x3853, ++ 0xb8bf, 0x37de, 0x3740, 0x385f, ++ 0xb8cc, 0x37c5, 0x3728, 0x386b, ++ 0xb8da, 0x37ac, 0x3710, 0x3877, ++ 0xb8e7, 0x3793, 0x36f8, 0x3883, ++ 0xb8f5, 0x377a, 0x36e1, 0x388f, ++ 0xb902, 0x3762, 0x36c9, 0x389b, ++ 0xb910, 0x3749, 0x36b1, 0x38a7, ++ 0xb91e, 0x3731, 0x369a, 0x38b2, ++ 0xb92c, 0x3719, 0x3682, 0x38be, ++ 0xb93a, 0x3700, 0x366b, 0x38ca, ++ 0xb948, 0x36e8, 0x3653, 0x38d6, ++ 0xb956, 0x36d1, 0x363c, 0x38e1, ++ 0xb964, 0x36b9, 0x3625, 0x38ed, ++ 0xb972, 0x36a1, 0x360e, 0x38f8, ++ 0xb980, 0x368a, 0x35f6, 0x3904, ++ 0xb98e, 0x3672, 0x35df, 0x3910, ++ 0xb99c, 0x365b, 0x35c9, 0x391b, ++ 0xb9ab, 0x3644, 0x35b2, 0x3926, ++ 0xb9b9, 0x362d, 0x359b, 0x3932, ++ 0xb9c7, 0x3616, 0x3584, 0x393d, ++ 0xb9d6, 0x35ff, 0x356e, 0x3948, ++ 0xb9e4, 0x35e9, 0x3557, 0x3954, ++ 0xb9f3, 0x35d2, 0x3541, 0x395f, ++ 0xba02, 0x35bc, 0x352b, 0x396a, ++ 0xba10, 0x35a6, 0x3515, 0x3975, ++ 0xba1f, 0x3590, 0x34ff, 0x3980, ++ 0xba2e, 0x357a, 0x34e9, 0x398b, ++ 0xba3d, 0x3564, 0x34d3, 0x3996, ++ 0xba4c, 0x354e, 0x34be, 0x39a0, ++ 0xba5a, 0x3539, 0x34a8, 0x39ab, ++ 0xba6a, 0x3523, 0x3493, 0x39b6, ++ 0xba79, 0x350e, 0x347e, 0x39c0, ++ 0xba88, 0x34f9, 0x3469, 0x39cb, ++ 0xba97, 0x34e4, 0x3454, 0x39d5, ++ 0xbaa6, 0x34cf, 0x3440, 0x39df, ++ 0xbab5, 0x34bb, 0x342b, 0x39ea, ++ 0xbac5, 0x34a6, 0x3417, 0x39f4, ++ 0xbad4, 0x3492, 0x3403, 0x39fe, ++ 0xbae3, 0x347e, 0x33de, 0x3a08, ++ 0xbaf3, 0x346a, 0x33b7, 0x3a12, ++ 0xbb02, 0x3456, 0x3390, 0x3a1c, ++ 0xbb12, 0x3443, 0x3369, 0x3a25, ++ 0xbb21, 0x342f, 0x3342, 0x3a2f, ++ 0xbb31, 0x341c, 0x331c, 0x3a38, ++ 0xbb41, 0x3409, 0x32f7, 0x3a42, ++ 0xbb51, 0x33ed, 0x32d1, 0x3a4b, ++ 0xbb60, 0x33c7, 0x32ad, 0x3a54, ++ 0xbb70, 0x33a2, 0x3288, 0x3a5d, ++ 0xbb80, 0x337d, 0x3264, 0x3a66, ++ 0xbb90, 0x3359, 0x3241, 0x3a6f, ++ 0xbba0, 0x3335, 0x321e, 0x3a78, ++ 0xbbb0, 0x3312, 0x31fb, 0x3a81, ++ 0xbbc0, 0x32ee, 0x31d9, 0x3a89, ++ 0xbbd0, 0x32cc, 0x31b7, 0x3a92, ++ 0xbbe0, 0x32a9, 0x3196, 0x3a9a, ++ 0xbbf0, 0x3287, 0x3175, 0x3aa2, ++ 0 }; ++ ++static const uint16_t bicubic_tex_2048[] = { ++ 0xb266, 0x3c00, 0x3aaa, 0x3155, ++ 0xb26e, 0x3bfc, 0x3aa8, 0x315d, ++ 0xb277, 0x3bf8, 0x3aa6, 0x3165, ++ 0xb27f, 0x3bf4, 0x3aa4, 0x316d, ++ 0xb287, 0x3bf0, 0x3aa2, 0x3175, ++ 0xb290, 0x3bec, 0x3aa0, 0x317d, ++ 0xb298, 0x3be8, 0x3a9e, 0x3185, ++ 0xb2a1, 0x3be4, 0x3a9c, 0x318e, ++ 0xb2a9, 0x3be0, 0x3a9a, 0x3196, ++ 0xb2b2, 0x3bdc, 0x3a98, 0x319e, ++ 0xb2ba, 0x3bd8, 0x3a96, 0x31a6, ++ 0xb2c3, 0x3bd4, 0x3a94, 0x31af, ++ 0xb2cc, 0x3bd0, 0x3a92, 0x31b7, ++ 0xb2d4, 0x3bcc, 0x3a90, 0x31bf, ++ 0xb2dd, 0x3bc8, 0x3a8d, 0x31c8, ++ 0xb2e6, 0x3bc4, 0x3a8b, 0x31d0, ++ 0xb2ee, 0x3bc0, 0x3a89, 0x31d9, ++ 0xb2f7, 0x3bbc, 0x3a87, 0x31e1, ++ 0xb300, 0x3bb8, 0x3a85, 0x31ea, ++ 0xb309, 0x3bb4, 0x3a83, 0x31f2, ++ 0xb312, 0x3bb0, 0x3a81, 0x31fb, ++ 0xb31a, 0x3bac, 0x3a7e, 0x3204, ++ 0xb323, 0x3ba8, 0x3a7c, 0x320c, ++ 0xb32c, 0x3ba4, 0x3a7a, 0x3215, ++ 0xb335, 0x3ba0, 0x3a78, 0x321e, ++ 0xb33e, 0x3b9c, 0x3a76, 0x3226, ++ 0xb347, 0x3b98, 0x3a74, 0x322f, ++ 0xb350, 0x3b94, 0x3a71, 0x3238, ++ 0xb359, 0x3b90, 0x3a6f, 0x3241, ++ 0xb362, 0x3b8c, 0x3a6d, 0x3249, ++ 0xb36b, 0x3b88, 0x3a6b, 0x3252, ++ 0xb374, 0x3b84, 0x3a69, 0x325b, ++ 0xb37d, 0x3b80, 0x3a66, 0x3264, ++ 0xb387, 0x3b7c, 0x3a64, 0x326d, ++ 0xb390, 0x3b78, 0x3a62, 0x3276, ++ 0xb399, 0x3b74, 0x3a60, 0x327f, ++ 0xb3a2, 0x3b70, 0x3a5d, 0x3288, ++ 0xb3ab, 0x3b6c, 0x3a5b, 0x3291, ++ 0xb3b5, 0x3b68, 0x3a59, 0x329a, ++ 0xb3be, 0x3b64, 0x3a57, 0x32a3, ++ 0xb3c7, 0x3b60, 0x3a54, 0x32ad, ++ 0xb3d0, 0x3b5c, 0x3a52, 0x32b6, ++ 0xb3da, 0x3b58, 0x3a50, 0x32bf, ++ 0xb3e3, 0x3b54, 0x3a4d, 0x32c8, ++ 0xb3ed, 0x3b51, 0x3a4b, 0x32d1, ++ 0xb3f6, 0x3b4d, 0x3a49, 0x32db, ++ 0xb3ff, 0x3b49, 0x3a46, 0x32e4, ++ 0xb404, 0x3b45, 0x3a44, 0x32ed, ++ 0xb409, 0x3b41, 0x3a42, 0x32f7, ++ 0xb40e, 0x3b3d, 0x3a3f, 0x3300, ++ 0xb412, 0x3b39, 0x3a3d, 0x3309, ++ 0xb417, 0x3b35, 0x3a3b, 0x3313, ++ 0xb41c, 0x3b31, 0x3a38, 0x331c, ++ 0xb421, 0x3b2d, 0x3a36, 0x3326, ++ 0xb426, 0x3b29, 0x3a34, 0x332f, ++ 0xb42a, 0x3b25, 0x3a31, 0x3339, ++ 0xb42f, 0x3b21, 0x3a2f, 0x3342, ++ 0xb434, 0x3b1e, 0x3a2c, 0x334c, ++ 0xb439, 0x3b1a, 0x3a2a, 0x3355, ++ 0xb43e, 0x3b16, 0x3a28, 0x335f, ++ 0xb443, 0x3b12, 0x3a25, 0x3369, ++ 0xb448, 0x3b0e, 0x3a23, 0x3372, ++ 0xb44d, 0x3b0a, 0x3a20, 0x337c, ++ 0xb451, 0x3b06, 0x3a1e, 0x3386, ++ 0xb456, 0x3b02, 0x3a1c, 0x3390, ++ 0xb45b, 0x3afe, 0x3a19, 0x3399, ++ 0xb460, 0x3afb, 0x3a17, 0x33a3, ++ 0xb465, 0x3af7, 0x3a14, 0x33ad, ++ 0xb46a, 0x3af3, 0x3a12, 0x33b7, ++ 0xb46f, 0x3aef, 0x3a0f, 0x33c1, ++ 0xb474, 0x3aeb, 0x3a0d, 0x33ca, ++ 0xb479, 0x3ae7, 0x3a0a, 0x33d4, ++ 0xb47e, 0x3ae3, 0x3a08, 0x33de, ++ 0xb483, 0x3ae0, 0x3a05, 0x33e8, ++ 0xb488, 0x3adc, 0x3a03, 0x33f2, ++ 0xb48d, 0x3ad8, 0x3a00, 0x33fc, ++ 0xb492, 0x3ad4, 0x39fe, 0x3403, ++ 0xb497, 0x3ad0, 0x39fb, 0x3408, ++ 0xb49c, 0x3acc, 0x39f9, 0x340d, ++ 0xb4a1, 0x3ac8, 0x39f6, 0x3412, ++ 0xb4a6, 0x3ac5, 0x39f4, 0x3417, ++ 0xb4ac, 0x3ac1, 0x39f1, 0x341c, ++ 0xb4b1, 0x3abd, 0x39ef, 0x3421, ++ 0xb4b6, 0x3ab9, 0x39ec, 0x3426, ++ 0xb4bb, 0x3ab5, 0x39ea, 0x342b, ++ 0xb4c0, 0x3ab1, 0x39e7, 0x3430, ++ 0xb4c5, 0x3aae, 0x39e5, 0x3435, ++ 0xb4ca, 0x3aaa, 0x39e2, 0x343b, ++ 0xb4cf, 0x3aa6, 0x39df, 0x3440, ++ 0xb4d5, 0x3aa2, 0x39dd, 0x3445, ++ 0xb4da, 0x3a9e, 0x39da, 0x344a, ++ 0xb4df, 0x3a9b, 0x39d8, 0x344f, ++ 0xb4e4, 0x3a97, 0x39d5, 0x3454, ++ 0xb4e9, 0x3a93, 0x39d2, 0x345a, ++ 0xb4ef, 0x3a8f, 0x39d0, 0x345f, ++ 0xb4f4, 0x3a8b, 0x39cd, 0x3464, ++ 0xb4f9, 0x3a88, 0x39cb, 0x3469, ++ 0xb4fe, 0x3a84, 0x39c8, 0x346e, ++ 0xb504, 0x3a80, 0x39c5, 0x3474, ++ 0xb509, 0x3a7c, 0x39c3, 0x3479, ++ 0xb50e, 0x3a79, 0x39c0, 0x347e, ++ 0xb513, 0x3a75, 0x39be, 0x3483, ++ 0xb519, 0x3a71, 0x39bb, 0x3489, ++ 0xb51e, 0x3a6d, 0x39b8, 0x348e, ++ 0xb523, 0x3a6a, 0x39b6, 0x3493, ++ 0xb529, 0x3a66, 0x39b3, 0x3499, ++ 0xb52e, 0x3a62, 0x39b0, 0x349e, ++ 0xb533, 0x3a5e, 0x39ae, 0x34a3, ++ 0xb539, 0x3a5a, 0x39ab, 0x34a8, ++ 0xb53e, 0x3a57, 0x39a8, 0x34ae, ++ 0xb543, 0x3a53, 0x39a6, 0x34b3, ++ 0xb549, 0x3a4f, 0x39a3, 0x34b9, ++ 0xb54e, 0x3a4c, 0x39a0, 0x34be, ++ 0xb554, 0x3a48, 0x399e, 0x34c3, ++ 0xb559, 0x3a44, 0x399b, 0x34c9, ++ 0xb55e, 0x3a40, 0x3998, 0x34ce, ++ 0xb564, 0x3a3d, 0x3996, 0x34d3, ++ 0xb569, 0x3a39, 0x3993, 0x34d9, ++ 0xb56f, 0x3a35, 0x3990, 0x34de, ++ 0xb574, 0x3a32, 0x398d, 0x34e4, ++ 0xb57a, 0x3a2e, 0x398b, 0x34e9, ++ 0xb57f, 0x3a2a, 0x3988, 0x34ef, ++ 0xb585, 0x3a26, 0x3985, 0x34f4, ++ 0xb58a, 0x3a23, 0x3983, 0x34f9, ++ 0xb590, 0x3a1f, 0x3980, 0x34ff, ++ 0xb595, 0x3a1b, 0x397d, 0x3504, ++ 0xb59b, 0x3a18, 0x397a, 0x350a, ++ 0xb5a0, 0x3a14, 0x3978, 0x350f, ++ 0xb5a6, 0x3a10, 0x3975, 0x3515, ++ 0xb5ab, 0x3a0d, 0x3972, 0x351a, ++ 0xb5b1, 0x3a09, 0x396f, 0x3520, ++ 0xb5b6, 0x3a05, 0x396d, 0x3525, ++ 0xb5bc, 0x3a02, 0x396a, 0x352b, ++ 0xb5c1, 0x39fe, 0x3967, 0x3530, ++ 0xb5c7, 0x39fa, 0x3964, 0x3536, ++ 0xb5cd, 0x39f7, 0x3961, 0x353c, ++ 0xb5d2, 0x39f3, 0x395f, 0x3541, ++ 0xb5d8, 0x39ef, 0x395c, 0x3547, ++ 0xb5dd, 0x39ec, 0x3959, 0x354c, ++ 0xb5e3, 0x39e8, 0x3956, 0x3552, ++ 0xb5e9, 0x39e4, 0x3954, 0x3557, ++ 0xb5ee, 0x39e1, 0x3951, 0x355d, ++ 0xb5f4, 0x39dd, 0x394e, 0x3563, ++ 0xb5fa, 0x39d9, 0x394b, 0x3568, ++ 0xb5ff, 0x39d6, 0x3948, 0x356e, ++ 0xb605, 0x39d2, 0x3946, 0x3573, ++ 0xb60b, 0x39cf, 0x3943, 0x3579, ++ 0xb610, 0x39cb, 0x3940, 0x357f, ++ 0xb616, 0x39c7, 0x393d, 0x3584, ++ 0xb61c, 0x39c4, 0x393a, 0x358a, ++ 0xb621, 0x39c0, 0x3937, 0x3590, ++ 0xb627, 0x39bd, 0x3935, 0x3595, ++ 0xb62d, 0x39b9, 0x3932, 0x359b, ++ 0xb633, 0x39b5, 0x392f, 0x35a1, ++ 0xb638, 0x39b2, 0x392c, 0x35a6, ++ 0xb63e, 0x39ae, 0x3929, 0x35ac, ++ 0xb644, 0x39ab, 0x3926, 0x35b2, ++ 0xb64a, 0x39a7, 0x3924, 0x35b7, ++ 0xb64f, 0x39a3, 0x3921, 0x35bd, ++ 0xb655, 0x39a0, 0x391e, 0x35c3, ++ 0xb65b, 0x399c, 0x391b, 0x35c9, ++ 0xb661, 0x3999, 0x3918, 0x35ce, ++ 0xb667, 0x3995, 0x3915, 0x35d4, ++ 0xb66c, 0x3992, 0x3912, 0x35da, ++ 0xb672, 0x398e, 0x3910, 0x35df, ++ 0xb678, 0x398a, 0x390d, 0x35e5, ++ 0xb67e, 0x3987, 0x390a, 0x35eb, ++ 0xb684, 0x3983, 0x3907, 0x35f1, ++ 0xb68a, 0x3980, 0x3904, 0x35f6, ++ 0xb68f, 0x397c, 0x3901, 0x35fc, ++ 0xb695, 0x3979, 0x38fe, 0x3602, ++ 0xb69b, 0x3975, 0x38fb, 0x3608, ++ 0xb6a1, 0x3972, 0x38f8, 0x360e, ++ 0xb6a7, 0x396e, 0x38f6, 0x3613, ++ 0xb6ad, 0x396b, 0x38f3, 0x3619, ++ 0xb6b3, 0x3967, 0x38f0, 0x361f, ++ 0xb6b9, 0x3964, 0x38ed, 0x3625, ++ 0xb6bf, 0x3960, 0x38ea, 0x362b, ++ 0xb6c5, 0x395d, 0x38e7, 0x3630, ++ 0xb6cb, 0x3959, 0x38e4, 0x3636, ++ 0xb6d1, 0x3956, 0x38e1, 0x363c, ++ 0xb6d6, 0x3952, 0x38de, 0x3642, ++ 0xb6dc, 0x394f, 0x38db, 0x3648, ++ 0xb6e2, 0x394b, 0x38d9, 0x364d, ++ 0xb6e8, 0x3948, 0x38d6, 0x3653, ++ 0xb6ee, 0x3944, 0x38d3, 0x3659, ++ 0xb6f4, 0x3941, 0x38d0, 0x365f, ++ 0xb6fa, 0x393d, 0x38cd, 0x3665, ++ 0xb700, 0x393a, 0x38ca, 0x366b, ++ 0xb706, 0x3936, 0x38c7, 0x3671, ++ 0xb70c, 0x3933, 0x38c4, 0x3676, ++ 0xb712, 0x392f, 0x38c1, 0x367c, ++ 0xb719, 0x392c, 0x38be, 0x3682, ++ 0xb71f, 0x3928, 0x38bb, 0x3688, ++ 0xb725, 0x3925, 0x38b8, 0x368e, ++ 0xb72b, 0x3921, 0x38b5, 0x3694, ++ 0xb731, 0x391e, 0x38b2, 0x369a, ++ 0xb737, 0x391a, 0x38af, 0x36a0, ++ 0xb73d, 0x3917, 0x38ad, 0x36a5, ++ 0xb743, 0x3914, 0x38aa, 0x36ab, ++ 0xb749, 0x3910, 0x38a7, 0x36b1, ++ 0xb74f, 0x390d, 0x38a4, 0x36b7, ++ 0xb755, 0x3909, 0x38a1, 0x36bd, ++ 0xb75b, 0x3906, 0x389e, 0x36c3, ++ 0xb762, 0x3902, 0x389b, 0x36c9, ++ 0xb768, 0x38ff, 0x3898, 0x36cf, ++ 0xb76e, 0x38fc, 0x3895, 0x36d5, ++ 0xb774, 0x38f8, 0x3892, 0x36db, ++ 0xb77a, 0x38f5, 0x388f, 0x36e1, ++ 0xb780, 0x38f1, 0x388c, 0x36e7, ++ 0xb787, 0x38ee, 0x3889, 0x36ec, ++ 0xb78d, 0x38eb, 0x3886, 0x36f2, ++ 0xb793, 0x38e7, 0x3883, 0x36f8, ++ 0xb799, 0x38e4, 0x3880, 0x36fe, ++ 0xb79f, 0x38e0, 0x387d, 0x3704, ++ 0xb7a5, 0x38dd, 0x387a, 0x370a, ++ 0xb7ac, 0x38da, 0x3877, 0x3710, ++ 0xb7b2, 0x38d6, 0x3874, 0x3716, ++ 0xb7b8, 0x38d3, 0x3871, 0x371c, ++ 0xb7be, 0x38cf, 0x386e, 0x3722, ++ 0xb7c5, 0x38cc, 0x386b, 0x3728, ++ 0xb7cb, 0x38c9, 0x3868, 0x372e, ++ 0xb7d1, 0x38c5, 0x3865, 0x3734, ++ 0xb7d7, 0x38c2, 0x3862, 0x373a, ++ 0xb7de, 0x38bf, 0x385f, 0x3740, ++ 0xb7e4, 0x38bb, 0x385c, 0x3746, ++ 0xb7ea, 0x38b8, 0x3859, 0x374c, ++ 0xb7f1, 0x38b5, 0x3856, 0x3752, ++ 0xb7f7, 0x38b1, 0x3853, 0x3758, ++ 0xb7fd, 0x38ae, 0x3850, 0x375e, ++ 0xb801, 0x38aa, 0x384d, 0x3764, ++ 0xb805, 0x38a7, 0x384a, 0x376a, ++ 0xb808, 0x38a4, 0x3847, 0x3770, ++ 0xb80b, 0x38a0, 0x3844, 0x3776, ++ 0xb80e, 0x389d, 0x3841, 0x377c, ++ 0xb811, 0x389a, 0x383e, 0x3782, ++ 0xb815, 0x3897, 0x383b, 0x3788, ++ 0xb818, 0x3893, 0x3838, 0x378e, ++ 0xb81b, 0x3890, 0x3835, 0x3794, ++ 0xb81e, 0x388d, 0x3832, 0x379a, ++ 0xb821, 0x3889, 0x382f, 0x37a0, ++ 0xb824, 0x3886, 0x382c, 0x37a6, ++ 0xb828, 0x3883, 0x3829, 0x37ac, ++ 0xb82b, 0x387f, 0x3826, 0x37b2, ++ 0xb82e, 0x387c, 0x3823, 0x37b8, ++ 0xb831, 0x3879, 0x3820, 0x37be, ++ 0xb835, 0x3876, 0x381d, 0x37c4, ++ 0xb838, 0x3872, 0x381a, 0x37ca, ++ 0xb83b, 0x386f, 0x3817, 0x37d0, ++ 0xb83e, 0x386c, 0x3814, 0x37d6, ++ 0xb841, 0x3868, 0x3811, 0x37dc, ++ 0xb845, 0x3865, 0x380e, 0x37e2, ++ 0xb848, 0x3862, 0x380b, 0x37e8, ++ 0xb84b, 0x385f, 0x3808, 0x37ee, ++ 0xb84e, 0x385b, 0x3806, 0x37f4, ++ 0xb852, 0x3858, 0x3803, 0x37fa, ++ 0xb855, 0x3855, 0x3800, 0x3800, ++ 0xb858, 0x3852, 0x37fa, 0x3803, ++ 0xb85b, 0x384e, 0x37f4, 0x3806, ++ 0xb85f, 0x384b, 0x37ee, 0x3808, ++ 0xb862, 0x3848, 0x37e8, 0x380b, ++ 0xb865, 0x3845, 0x37e2, 0x380e, ++ 0xb868, 0x3841, 0x37dc, 0x3811, ++ 0xb86c, 0x383e, 0x37d6, 0x3814, ++ 0xb86f, 0x383b, 0x37d0, 0x3817, ++ 0xb872, 0x3838, 0x37ca, 0x381a, ++ 0xb876, 0x3835, 0x37c4, 0x381d, ++ 0xb879, 0x3831, 0x37be, 0x3820, ++ 0xb87c, 0x382e, 0x37b8, 0x3823, ++ 0xb87f, 0x382b, 0x37b2, 0x3826, ++ 0xb883, 0x3828, 0x37ac, 0x3829, ++ 0xb886, 0x3824, 0x37a6, 0x382c, ++ 0xb889, 0x3821, 0x37a0, 0x382f, ++ 0xb88d, 0x381e, 0x379a, 0x3832, ++ 0xb890, 0x381b, 0x3794, 0x3835, ++ 0xb893, 0x3818, 0x378e, 0x3838, ++ 0xb897, 0x3815, 0x3788, 0x383b, ++ 0xb89a, 0x3811, 0x3782, 0x383e, ++ 0xb89d, 0x380e, 0x377c, 0x3841, ++ 0xb8a0, 0x380b, 0x3776, 0x3844, ++ 0xb8a4, 0x3808, 0x3770, 0x3847, ++ 0xb8a7, 0x3805, 0x376a, 0x384a, ++ 0xb8aa, 0x3801, 0x3764, 0x384d, ++ 0xb8ae, 0x37fd, 0x375e, 0x3850, ++ 0xb8b1, 0x37f7, 0x3758, 0x3853, ++ 0xb8b5, 0x37f1, 0x3752, 0x3856, ++ 0xb8b8, 0x37ea, 0x374c, 0x3859, ++ 0xb8bb, 0x37e4, 0x3746, 0x385c, ++ 0xb8bf, 0x37de, 0x3740, 0x385f, ++ 0xb8c2, 0x37d7, 0x373a, 0x3862, ++ 0xb8c5, 0x37d1, 0x3734, 0x3865, ++ 0xb8c9, 0x37cb, 0x372e, 0x3868, ++ 0xb8cc, 0x37c5, 0x3728, 0x386b, ++ 0xb8cf, 0x37be, 0x3722, 0x386e, ++ 0xb8d3, 0x37b8, 0x371c, 0x3871, ++ 0xb8d6, 0x37b2, 0x3716, 0x3874, ++ 0xb8da, 0x37ac, 0x3710, 0x3877, ++ 0xb8dd, 0x37a5, 0x370a, 0x387a, ++ 0xb8e0, 0x379f, 0x3704, 0x387d, ++ 0xb8e4, 0x3799, 0x36fe, 0x3880, ++ 0xb8e7, 0x3793, 0x36f8, 0x3883, ++ 0xb8eb, 0x378d, 0x36f2, 0x3886, ++ 0xb8ee, 0x3787, 0x36ec, 0x3889, ++ 0xb8f1, 0x3780, 0x36e7, 0x388c, ++ 0xb8f5, 0x377a, 0x36e1, 0x388f, ++ 0xb8f8, 0x3774, 0x36db, 0x3892, ++ 0xb8fc, 0x376e, 0x36d5, 0x3895, ++ 0xb8ff, 0x3768, 0x36cf, 0x3898, ++ 0xb902, 0x3762, 0x36c9, 0x389b, ++ 0xb906, 0x375b, 0x36c3, 0x389e, ++ 0xb909, 0x3755, 0x36bd, 0x38a1, ++ 0xb90d, 0x374f, 0x36b7, 0x38a4, ++ 0xb910, 0x3749, 0x36b1, 0x38a7, ++ 0xb914, 0x3743, 0x36ab, 0x38aa, ++ 0xb917, 0x373d, 0x36a5, 0x38ad, ++ 0xb91a, 0x3737, 0x36a0, 0x38af, ++ 0xb91e, 0x3731, 0x369a, 0x38b2, ++ 0xb921, 0x372b, 0x3694, 0x38b5, ++ 0xb925, 0x3725, 0x368e, 0x38b8, ++ 0xb928, 0x371f, 0x3688, 0x38bb, ++ 0xb92c, 0x3719, 0x3682, 0x38be, ++ 0xb92f, 0x3712, 0x367c, 0x38c1, ++ 0xb933, 0x370c, 0x3676, 0x38c4, ++ 0xb936, 0x3706, 0x3671, 0x38c7, ++ 0xb93a, 0x3700, 0x366b, 0x38ca, ++ 0xb93d, 0x36fa, 0x3665, 0x38cd, ++ 0xb941, 0x36f4, 0x365f, 0x38d0, ++ 0xb944, 0x36ee, 0x3659, 0x38d3, ++ 0xb948, 0x36e8, 0x3653, 0x38d6, ++ 0xb94b, 0x36e2, 0x364d, 0x38d9, ++ 0xb94f, 0x36dc, 0x3648, 0x38db, ++ 0xb952, 0x36d6, 0x3642, 0x38de, ++ 0xb956, 0x36d1, 0x363c, 0x38e1, ++ 0xb959, 0x36cb, 0x3636, 0x38e4, ++ 0xb95d, 0x36c5, 0x3630, 0x38e7, ++ 0xb960, 0x36bf, 0x362b, 0x38ea, ++ 0xb964, 0x36b9, 0x3625, 0x38ed, ++ 0xb967, 0x36b3, 0x361f, 0x38f0, ++ 0xb96b, 0x36ad, 0x3619, 0x38f3, ++ 0xb96e, 0x36a7, 0x3613, 0x38f6, ++ 0xb972, 0x36a1, 0x360e, 0x38f8, ++ 0xb975, 0x369b, 0x3608, 0x38fb, ++ 0xb979, 0x3695, 0x3602, 0x38fe, ++ 0xb97c, 0x368f, 0x35fc, 0x3901, ++ 0xb980, 0x368a, 0x35f6, 0x3904, ++ 0xb983, 0x3684, 0x35f1, 0x3907, ++ 0xb987, 0x367e, 0x35eb, 0x390a, ++ 0xb98a, 0x3678, 0x35e5, 0x390d, ++ 0xb98e, 0x3672, 0x35df, 0x3910, ++ 0xb992, 0x366c, 0x35da, 0x3912, ++ 0xb995, 0x3667, 0x35d4, 0x3915, ++ 0xb999, 0x3661, 0x35ce, 0x3918, ++ 0xb99c, 0x365b, 0x35c9, 0x391b, ++ 0xb9a0, 0x3655, 0x35c3, 0x391e, ++ 0xb9a3, 0x364f, 0x35bd, 0x3921, ++ 0xb9a7, 0x364a, 0x35b7, 0x3924, ++ 0xb9ab, 0x3644, 0x35b2, 0x3926, ++ 0xb9ae, 0x363e, 0x35ac, 0x3929, ++ 0xb9b2, 0x3638, 0x35a6, 0x392c, ++ 0xb9b5, 0x3633, 0x35a1, 0x392f, ++ 0xb9b9, 0x362d, 0x359b, 0x3932, ++ 0xb9bd, 0x3627, 0x3595, 0x3935, ++ 0xb9c0, 0x3621, 0x3590, 0x3937, ++ 0xb9c4, 0x361c, 0x358a, 0x393a, ++ 0xb9c7, 0x3616, 0x3584, 0x393d, ++ 0xb9cb, 0x3610, 0x357f, 0x3940, ++ 0xb9cf, 0x360b, 0x3579, 0x3943, ++ 0xb9d2, 0x3605, 0x3573, 0x3946, ++ 0xb9d6, 0x35ff, 0x356e, 0x3948, ++ 0xb9d9, 0x35fa, 0x3568, 0x394b, ++ 0xb9dd, 0x35f4, 0x3563, 0x394e, ++ 0xb9e1, 0x35ee, 0x355d, 0x3951, ++ 0xb9e4, 0x35e9, 0x3557, 0x3954, ++ 0xb9e8, 0x35e3, 0x3552, 0x3956, ++ 0xb9ec, 0x35dd, 0x354c, 0x3959, ++ 0xb9ef, 0x35d8, 0x3547, 0x395c, ++ 0xb9f3, 0x35d2, 0x3541, 0x395f, ++ 0xb9f7, 0x35cd, 0x353c, 0x3961, ++ 0xb9fa, 0x35c7, 0x3536, 0x3964, ++ 0xb9fe, 0x35c1, 0x3530, 0x3967, ++ 0xba02, 0x35bc, 0x352b, 0x396a, ++ 0xba05, 0x35b6, 0x3525, 0x396d, ++ 0xba09, 0x35b1, 0x3520, 0x396f, ++ 0xba0d, 0x35ab, 0x351a, 0x3972, ++ 0xba10, 0x35a6, 0x3515, 0x3975, ++ 0xba14, 0x35a0, 0x350f, 0x3978, ++ 0xba18, 0x359b, 0x350a, 0x397a, ++ 0xba1b, 0x3595, 0x3504, 0x397d, ++ 0xba1f, 0x3590, 0x34ff, 0x3980, ++ 0xba23, 0x358a, 0x34f9, 0x3983, ++ 0xba26, 0x3585, 0x34f4, 0x3985, ++ 0xba2a, 0x357f, 0x34ef, 0x3988, ++ 0xba2e, 0x357a, 0x34e9, 0x398b, ++ 0xba32, 0x3574, 0x34e4, 0x398d, ++ 0xba35, 0x356f, 0x34de, 0x3990, ++ 0xba39, 0x3569, 0x34d9, 0x3993, ++ 0xba3d, 0x3564, 0x34d3, 0x3996, ++ 0xba40, 0x355e, 0x34ce, 0x3998, ++ 0xba44, 0x3559, 0x34c9, 0x399b, ++ 0xba48, 0x3554, 0x34c3, 0x399e, ++ 0xba4c, 0x354e, 0x34be, 0x39a0, ++ 0xba4f, 0x3549, 0x34b9, 0x39a3, ++ 0xba53, 0x3543, 0x34b3, 0x39a6, ++ 0xba57, 0x353e, 0x34ae, 0x39a8, ++ 0xba5a, 0x3539, 0x34a8, 0x39ab, ++ 0xba5e, 0x3533, 0x34a3, 0x39ae, ++ 0xba62, 0x352e, 0x349e, 0x39b0, ++ 0xba66, 0x3529, 0x3499, 0x39b3, ++ 0xba6a, 0x3523, 0x3493, 0x39b6, ++ 0xba6d, 0x351e, 0x348e, 0x39b8, ++ 0xba71, 0x3519, 0x3489, 0x39bb, ++ 0xba75, 0x3513, 0x3483, 0x39be, ++ 0xba79, 0x350e, 0x347e, 0x39c0, ++ 0xba7c, 0x3509, 0x3479, 0x39c3, ++ 0xba80, 0x3504, 0x3474, 0x39c5, ++ 0xba84, 0x34fe, 0x346e, 0x39c8, ++ 0xba88, 0x34f9, 0x3469, 0x39cb, ++ 0xba8b, 0x34f4, 0x3464, 0x39cd, ++ 0xba8f, 0x34ef, 0x345f, 0x39d0, ++ 0xba93, 0x34e9, 0x345a, 0x39d2, ++ 0xba97, 0x34e4, 0x3454, 0x39d5, ++ 0xba9b, 0x34df, 0x344f, 0x39d8, ++ 0xba9e, 0x34da, 0x344a, 0x39da, ++ 0xbaa2, 0x34d5, 0x3445, 0x39dd, ++ 0xbaa6, 0x34cf, 0x3440, 0x39df, ++ 0xbaaa, 0x34ca, 0x343b, 0x39e2, ++ 0xbaae, 0x34c5, 0x3435, 0x39e5, ++ 0xbab1, 0x34c0, 0x3430, 0x39e7, ++ 0xbab5, 0x34bb, 0x342b, 0x39ea, ++ 0xbab9, 0x34b6, 0x3426, 0x39ec, ++ 0xbabd, 0x34b1, 0x3421, 0x39ef, ++ 0xbac1, 0x34ac, 0x341c, 0x39f1, ++ 0xbac5, 0x34a6, 0x3417, 0x39f4, ++ 0xbac8, 0x34a1, 0x3412, 0x39f6, ++ 0xbacc, 0x349c, 0x340d, 0x39f9, ++ 0xbad0, 0x3497, 0x3408, 0x39fb, ++ 0xbad4, 0x3492, 0x3403, 0x39fe, ++ 0xbad8, 0x348d, 0x33fc, 0x3a00, ++ 0xbadc, 0x3488, 0x33f2, 0x3a03, ++ 0xbae0, 0x3483, 0x33e8, 0x3a05, ++ 0xbae3, 0x347e, 0x33de, 0x3a08, ++ 0xbae7, 0x3479, 0x33d4, 0x3a0a, ++ 0xbaeb, 0x3474, 0x33ca, 0x3a0d, ++ 0xbaef, 0x346f, 0x33c1, 0x3a0f, ++ 0xbaf3, 0x346a, 0x33b7, 0x3a12, ++ 0xbaf7, 0x3465, 0x33ad, 0x3a14, ++ 0xbafb, 0x3460, 0x33a3, 0x3a17, ++ 0xbafe, 0x345b, 0x3399, 0x3a19, ++ 0xbb02, 0x3456, 0x3390, 0x3a1c, ++ 0xbb06, 0x3451, 0x3386, 0x3a1e, ++ 0xbb0a, 0x344d, 0x337c, 0x3a20, ++ 0xbb0e, 0x3448, 0x3372, 0x3a23, ++ 0xbb12, 0x3443, 0x3369, 0x3a25, ++ 0xbb16, 0x343e, 0x335f, 0x3a28, ++ 0xbb1a, 0x3439, 0x3355, 0x3a2a, ++ 0xbb1e, 0x3434, 0x334c, 0x3a2c, ++ 0xbb21, 0x342f, 0x3342, 0x3a2f, ++ 0xbb25, 0x342a, 0x3339, 0x3a31, ++ 0xbb29, 0x3426, 0x332f, 0x3a34, ++ 0xbb2d, 0x3421, 0x3326, 0x3a36, ++ 0xbb31, 0x341c, 0x331c, 0x3a38, ++ 0xbb35, 0x3417, 0x3313, 0x3a3b, ++ 0xbb39, 0x3412, 0x3309, 0x3a3d, ++ 0xbb3d, 0x340e, 0x3300, 0x3a3f, ++ 0xbb41, 0x3409, 0x32f7, 0x3a42, ++ 0xbb45, 0x3404, 0x32ed, 0x3a44, ++ 0xbb49, 0x33ff, 0x32e4, 0x3a46, ++ 0xbb4d, 0x33f6, 0x32db, 0x3a49, ++ 0xbb51, 0x33ed, 0x32d1, 0x3a4b, ++ 0xbb54, 0x33e3, 0x32c8, 0x3a4d, ++ 0xbb58, 0x33da, 0x32bf, 0x3a50, ++ 0xbb5c, 0x33d0, 0x32b6, 0x3a52, ++ 0xbb60, 0x33c7, 0x32ad, 0x3a54, ++ 0xbb64, 0x33be, 0x32a3, 0x3a57, ++ 0xbb68, 0x33b5, 0x329a, 0x3a59, ++ 0xbb6c, 0x33ab, 0x3291, 0x3a5b, ++ 0xbb70, 0x33a2, 0x3288, 0x3a5d, ++ 0xbb74, 0x3399, 0x327f, 0x3a60, ++ 0xbb78, 0x3390, 0x3276, 0x3a62, ++ 0xbb7c, 0x3387, 0x326d, 0x3a64, ++ 0xbb80, 0x337d, 0x3264, 0x3a66, ++ 0xbb84, 0x3374, 0x325b, 0x3a69, ++ 0xbb88, 0x336b, 0x3252, 0x3a6b, ++ 0xbb8c, 0x3362, 0x3249, 0x3a6d, ++ 0xbb90, 0x3359, 0x3241, 0x3a6f, ++ 0xbb94, 0x3350, 0x3238, 0x3a71, ++ 0xbb98, 0x3347, 0x322f, 0x3a74, ++ 0xbb9c, 0x333e, 0x3226, 0x3a76, ++ 0xbba0, 0x3335, 0x321e, 0x3a78, ++ 0xbba4, 0x332c, 0x3215, 0x3a7a, ++ 0xbba8, 0x3323, 0x320c, 0x3a7c, ++ 0xbbac, 0x331a, 0x3204, 0x3a7e, ++ 0xbbb0, 0x3312, 0x31fb, 0x3a81, ++ 0xbbb4, 0x3309, 0x31f2, 0x3a83, ++ 0xbbb8, 0x3300, 0x31ea, 0x3a85, ++ 0xbbbc, 0x32f7, 0x31e1, 0x3a87, ++ 0xbbc0, 0x32ee, 0x31d9, 0x3a89, ++ 0xbbc4, 0x32e6, 0x31d0, 0x3a8b, ++ 0xbbc8, 0x32dd, 0x31c8, 0x3a8d, ++ 0xbbcc, 0x32d4, 0x31bf, 0x3a90, ++ 0xbbd0, 0x32cc, 0x31b7, 0x3a92, ++ 0xbbd4, 0x32c3, 0x31af, 0x3a94, ++ 0xbbd8, 0x32ba, 0x31a6, 0x3a96, ++ 0xbbdc, 0x32b2, 0x319e, 0x3a98, ++ 0xbbe0, 0x32a9, 0x3196, 0x3a9a, ++ 0xbbe4, 0x32a1, 0x318e, 0x3a9c, ++ 0xbbe8, 0x3298, 0x3185, 0x3a9e, ++ 0xbbec, 0x3290, 0x317d, 0x3aa0, ++ 0xbbf0, 0x3287, 0x3175, 0x3aa2, ++ 0xbbf4, 0x327f, 0x316d, 0x3aa4, ++ 0xbbf8, 0x3277, 0x3165, 0x3aa6, ++ 0xbbfc, 0x326e, 0x315d, 0x3aa8, ++ 0 }; ++ +diff --git a/src/bicubic_table.py b/src/bicubic_table.py +new file mode 100755 +index 0000000..232ccb7 +--- /dev/null ++++ b/src/bicubic_table.py +@@ -0,0 +1,72 @@ ++#!/usr/bin/python ++ ++import struct ++ ++def half(i): ++ fs, fe, fm = ((i >> 31) & 0x1, (i >> 23) & 0xff, i & 0x7fffff) ++ s, e, m = (fs, 0, 0) ++ ++ if (fe == 0x0): ++ pass ++ if ((fe == 0xff) and (fm == 0x0)): ++ e = 31 ++ elif (fe == 0xff): ++ m = 1 ++ e = 31 ++ else: ++ exp = fe - 127; ++ if (exp < -24): ++ pass ++ elif (exp < -14): ++ temp = 10 - (-14 - exp) ++ m = 2**temp + (m >> (23 - temp)) ++ elif (exp > 15): ++ e = 31 ++ else: ++ e = exp + 15 ++ m = fm >> 13 ++ ++ return ((s << 15) | (e << 10) | m) ++ ++def texgen(pix): ++ ++ tex = [] ++ ++ for i in range(0,pix,4): ++ ++ a = i / float(pix) ++ a2 = a ** 2 ++ a3 = a ** 3 ++ ++ w0 = 1 / 6.0 * (-a3 + 3 * a2 + -3 * a + 1) ++ w1 = 1 / 6.0 * (3 * a3 + -6 * a2 + 4) ++ w2 = 1 / 6.0 * (-3 * a3 + 3 * a2 + 3 * a + 1) ++ w3 = 1 / 6.0 * a3 ++ ++ tex.append(-(1 - (w1 / (w0 + w1)) + a)) ++ tex.append(1 + (w3 / (w2 + w3)) - a) ++ tex.append(w0 + w1) ++ tex.append(w2 + w3) ++ ++ return tex ++ ++def printrow(l, offset): ++ ++ seq = [ struct.unpack('has_tcl) { +- /* exa mask shader program */ ++ /* exa mask/Xv bicubic shader program */ + BEGIN_ACCEL(13); + OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_INDX_REG, 0); + /* PVS inst 0 */ +@@ -498,14 +499,14 @@ static void FUNC_NAME(RADEONInit3DEngine)(ScrnInfoPtr pScrn) + if (IS_R300_3D) { + BEGIN_ACCEL(2); + /* tex inst for src texture */ +- OUT_ACCEL_REG(R300_US_TEX_INST_0, ++ OUT_ACCEL_REG(R300_US_TEX_INST(0), + (R300_TEX_SRC_ADDR(0) | + R300_TEX_DST_ADDR(0) | + R300_TEX_ID(0) | + R300_TEX_INST(R300_TEX_INST_LD))); + + /* tex inst for mask texture */ +- OUT_ACCEL_REG(R300_US_TEX_INST_1, ++ OUT_ACCEL_REG(R300_US_TEX_INST(1), + (R300_TEX_SRC_ADDR(1) | + R300_TEX_DST_ADDR(1) | + R300_TEX_ID(1) | +@@ -514,9 +515,8 @@ static void FUNC_NAME(RADEONInit3DEngine)(ScrnInfoPtr pScrn) + } + + if (IS_R300_3D) { +- BEGIN_ACCEL(9); ++ BEGIN_ACCEL(8); + OUT_ACCEL_REG(R300_US_CONFIG, (0 << R300_NLEVEL_SHIFT) | R300_FIRST_TEX); +- OUT_ACCEL_REG(R300_US_PIXSIZE, 1); /* highest temp used */ + OUT_ACCEL_REG(R300_US_CODE_ADDR_0, + (R300_ALU_START(0) | + R300_ALU_SIZE(0) | +@@ -533,9 +533,8 @@ static void FUNC_NAME(RADEONInit3DEngine)(ScrnInfoPtr pScrn) + R300_TEX_START(0) | + R300_TEX_SIZE(0))); + } else { +- BEGIN_ACCEL(7); ++ BEGIN_ACCEL(6); + OUT_ACCEL_REG(R300_US_CONFIG, R500_ZERO_TIMES_ANYTHING_EQUALS_ZERO); +- OUT_ACCEL_REG(R300_US_PIXSIZE, 1); /* highest temp used */ + OUT_ACCEL_REG(R500_US_FC_CTRL, 0); + } + OUT_ACCEL_REG(R300_US_W_FMT, 0); diff --git a/src/radeon_crtc.c b/src/radeon_crtc.c index c63b650..5ab00c1 100644 --- a/src/radeon_crtc.c @@ -3293,10 +4071,96 @@ index f461f3c..02fd4fc 100644 xf86DrvMsg(pScrn->scrnIndex, X_INFO, "Will use %d kb for hardware cursor %d at offset 0x%08x\n", diff --git a/src/radeon_exa_render.c b/src/radeon_exa_render.c -index 4736e4f..5d28d80 100644 +index 4736e4f..043b0d4 100644 --- a/src/radeon_exa_render.c +++ b/src/radeon_exa_render.c -@@ -1962,9 +1962,9 @@ static void FUNC_NAME(RadeonCompositeTile)(PixmapPtr pDst, +@@ -1419,7 +1419,7 @@ static Bool FUNC_NAME(R300PrepareComposite)(int op, PicturePtr pSrcPicture, + + + /* setup the rasterizer, load FS */ +- BEGIN_ACCEL(9); ++ BEGIN_ACCEL(10); + if (pMask) { + /* 4 components: 2 for tex0, 2 for tex1 */ + OUT_ACCEL_REG(R300_RS_COUNT, +@@ -1461,6 +1461,7 @@ static Bool FUNC_NAME(R300PrepareComposite)(int op, PicturePtr pSrcPicture, + R300_RGBA_OUT)); + } + ++ OUT_ACCEL_REG(R300_US_PIXSIZE, 1); /* highest temp used */ + /* shader output swizzling */ + OUT_ACCEL_REG(R300_US_OUT_FMT_0, output_fmt); + +@@ -1474,7 +1475,7 @@ static Bool FUNC_NAME(R300PrepareComposite)(int op, PicturePtr pSrcPicture, + * R300_ALU_RGB_OMASK - output components to write + * R300_ALU_RGB_TARGET_A - render target + */ +- OUT_ACCEL_REG(R300_US_ALU_RGB_ADDR_0, ++ OUT_ACCEL_REG(R300_US_ALU_RGB_ADDR(0), + (R300_ALU_RGB_ADDR0(0) | + R300_ALU_RGB_ADDR1(1) | + R300_ALU_RGB_ADDR2(0) | +@@ -1486,7 +1487,7 @@ static Bool FUNC_NAME(R300PrepareComposite)(int op, PicturePtr pSrcPicture, + /* RGB inst + * ALU operation + */ +- OUT_ACCEL_REG(R300_US_ALU_RGB_INST_0, ++ OUT_ACCEL_REG(R300_US_ALU_RGB_INST(0), + (R300_ALU_RGB_SEL_A(src_color) | + R300_ALU_RGB_MOD_A(R300_ALU_RGB_MOD_NOP) | + R300_ALU_RGB_SEL_B(mask_color) | +@@ -1503,7 +1504,7 @@ static Bool FUNC_NAME(R300PrepareComposite)(int op, PicturePtr pSrcPicture, + * R300_ALU_ALPHA_OMASK - output components to write + * R300_ALU_ALPHA_TARGET_A - render target + */ +- OUT_ACCEL_REG(R300_US_ALU_ALPHA_ADDR_0, ++ OUT_ACCEL_REG(R300_US_ALU_ALPHA_ADDR(0), + (R300_ALU_ALPHA_ADDR0(0) | + R300_ALU_ALPHA_ADDR1(1) | + R300_ALU_ALPHA_ADDR2(0) | +@@ -1514,7 +1515,7 @@ static Bool FUNC_NAME(R300PrepareComposite)(int op, PicturePtr pSrcPicture, + /* Alpha inst + * ALU operation + */ +- OUT_ACCEL_REG(R300_US_ALU_ALPHA_INST_0, ++ OUT_ACCEL_REG(R300_US_ALU_ALPHA_INST(0), + (R300_ALU_ALPHA_SEL_A(src_alpha) | + R300_ALU_ALPHA_MOD_A(R300_ALU_ALPHA_MOD_NOP) | + R300_ALU_ALPHA_SEL_B(mask_alpha) | +@@ -1633,7 +1634,7 @@ static Bool FUNC_NAME(R300PrepareComposite)(int op, PicturePtr pSrcPicture, + break; + } + +- BEGIN_ACCEL(6); ++ BEGIN_ACCEL(7); + if (pMask) { + /* 4 components: 2 for tex0, 2 for tex1 */ + OUT_ACCEL_REG(R300_RS_COUNT, +@@ -1662,12 +1663,13 @@ static Bool FUNC_NAME(R300PrepareComposite)(int op, PicturePtr pSrcPicture, + OUT_ACCEL_REG(R500_US_CODE_OFFSET, 0); + } + ++ OUT_ACCEL_REG(R300_US_PIXSIZE, 1); /* highest temp used */ + OUT_ACCEL_REG(R300_US_OUT_FMT_0, output_fmt); + FINISH_ACCEL(); + + if (pMask) { + BEGIN_ACCEL(19); +- OUT_ACCEL_REG(R500_GA_US_VECTOR_INDEX, 0); ++ OUT_ACCEL_REG(R500_GA_US_VECTOR_INDEX, R500_US_VECTOR_INST_INDEX(0)); + /* tex inst for src texture */ + OUT_ACCEL_REG(R500_GA_US_VECTOR_DATA, (R500_INST_TYPE_TEX | + R500_INST_RGB_WMASK_R | +@@ -1739,7 +1741,7 @@ static Bool FUNC_NAME(R300PrepareComposite)(int op, PicturePtr pSrcPicture, + OUT_ACCEL_REG(R500_GA_US_VECTOR_DATA, 0x00000000); + } else { + BEGIN_ACCEL(13); +- OUT_ACCEL_REG(R500_GA_US_VECTOR_INDEX, 0); ++ OUT_ACCEL_REG(R500_GA_US_VECTOR_INDEX, R500_US_VECTOR_INST_INDEX(0)); + /* tex inst for src texture */ + OUT_ACCEL_REG(R500_GA_US_VECTOR_DATA, (R500_INST_TYPE_TEX | + R500_INST_TEX_SEM_WAIT | +@@ -1962,9 +1964,9 @@ static void FUNC_NAME(RadeonCompositeTile)(PixmapPtr pDst, #ifdef ACCEL_CP if (info->ChipFamily < CHIP_FAMILY_R200) { @@ -3308,7 +4172,7 @@ index 4736e4f..5d28d80 100644 if (has_mask) OUT_RING(RADEON_CP_VC_FRMT_XY | RADEON_CP_VC_FRMT_ST0 | -@@ -1972,11 +1972,11 @@ static void FUNC_NAME(RadeonCompositeTile)(PixmapPtr pDst, +@@ -1972,11 +1974,11 @@ static void FUNC_NAME(RadeonCompositeTile)(PixmapPtr pDst, else OUT_RING(RADEON_CP_VC_FRMT_XY | RADEON_CP_VC_FRMT_ST0); @@ -3322,7 +4186,7 @@ index 4736e4f..5d28d80 100644 } else { if (IS_R300_3D || IS_R500_3D) BEGIN_RING(4 * vtx_count + 4); -@@ -1985,7 +1985,7 @@ static void FUNC_NAME(RadeonCompositeTile)(PixmapPtr pDst, +@@ -1985,7 +1987,7 @@ static void FUNC_NAME(RadeonCompositeTile)(PixmapPtr pDst, OUT_RING(CP_PACKET3(R200_CP_PACKET3_3D_DRAW_IMMD_2, 4 * vtx_count)); @@ -3331,7 +4195,7 @@ index 4736e4f..5d28d80 100644 RADEON_CP_VC_CNTL_PRIM_WALK_RING | (4 << RADEON_CP_VC_CNTL_NUM_SHIFT)); } -@@ -1993,25 +1993,29 @@ static void FUNC_NAME(RadeonCompositeTile)(PixmapPtr pDst, +@@ -1993,25 +1995,29 @@ static void FUNC_NAME(RadeonCompositeTile)(PixmapPtr pDst, #else /* ACCEL_CP */ if (IS_R300_3D || IS_R500_3D) BEGIN_ACCEL(2 + vtx_count * 4); @@ -3367,7 +4231,7 @@ index 4736e4f..5d28d80 100644 VTX_OUT_MASK((float)dstX, (float)(dstY + h), xFixedToFloat(srcBottomLeft.x) / info->texW[0], xFixedToFloat(srcBottomLeft.y) / info->texH[0], xFixedToFloat(maskBottomLeft.x) / info->texW[1], xFixedToFloat(maskBottomLeft.y) / info->texH[1]); -@@ -2022,8 +2026,10 @@ static void FUNC_NAME(RadeonCompositeTile)(PixmapPtr pDst, +@@ -2022,8 +2028,10 @@ static void FUNC_NAME(RadeonCompositeTile)(PixmapPtr pDst, xFixedToFloat(srcTopRight.x) / info->texW[0], xFixedToFloat(srcTopRight.y) / info->texH[0], xFixedToFloat(maskTopRight.x) / info->texW[1], xFixedToFloat(maskTopRight.y) / info->texH[1]); } else { @@ -3418,7 +4282,7 @@ index afe442e..f19bc3e 100644 #define RADEON_BIOS16(v) (info->VBIOS[v] | \ (info->VBIOS[(v) + 1] << 8)) diff --git a/src/radeon_output.c b/src/radeon_output.c -index 7b89d66..7d7f88a 100644 +index 7b89d66..2cc38a5 100644 --- a/src/radeon_output.c +++ b/src/radeon_output.c @@ -173,9 +173,6 @@ static const uint32_t default_tvdac_adj [CHIP_FAMILY_LAST] = @@ -3727,7 +4591,7 @@ index 7b89d66..7d7f88a 100644 i2c.put_clk_reg = ddc_line + 0x8; i2c.put_data_reg = ddc_line + 0x8; i2c.get_clk_reg = ddc_line + 0xc; -@@ -2301,7 +2259,7 @@ static Bool RADEONSetupAppleConnectors(ScrnInfoPtr pScrn) +@@ -2301,13 +2259,13 @@ static Bool RADEONSetupAppleConnectors(ScrnInfoPtr pScrn) info->BiosConnector[0].ddc_i2c = legacy_setup_i2c_bus(RADEON_GPIO_DVI_DDC); info->BiosConnector[0].DACType = DAC_NONE; info->BiosConnector[0].TMDSType = TMDS_NONE; @@ -3736,6 +4600,14 @@ index 7b89d66..7d7f88a 100644 info->BiosConnector[0].valid = TRUE; info->BiosConnector[1].ddc_i2c = legacy_setup_i2c_bus(RADEON_GPIO_VGA_DDC); + info->BiosConnector[1].DACType = DAC_PRIMARY; +- info->BiosConnector[1].TMDSType = TMDS_INT; +- info->BiosConnector[1].ConnectorType = CONNECTOR_DVI_I; ++ info->BiosConnector[1].TMDSType = TMDS_NONE; ++ info->BiosConnector[1].ConnectorType = CONNECTOR_VGA; + info->BiosConnector[1].valid = TRUE; + + info->BiosConnector[2].ConnectorType = CONNECTOR_STV; @@ -2677,7 +2635,6 @@ Bool RADEONSetupConnectors(ScrnInfoPtr pScrn) { xf86CrtcConfigPtr xf86_config = XF86_CRTC_CONFIG_PTR(pScrn); @@ -3860,7 +4732,7 @@ index 24af52b..3770abf 100644 struct avivo_pll_state pll1; struct avivo_pll_state pll2; diff --git a/src/radeon_reg.h b/src/radeon_reg.h -index 59e2f12..1d35236 100644 +index 59e2f12..19f9869 100644 --- a/src/radeon_reg.h +++ b/src/radeon_reg.h @@ -1032,6 +1032,10 @@ @@ -3959,41 +4831,1362 @@ index 59e2f12..1d35236 100644 #define R600_HDP_NONSURFACE_BASE 0x2c04 #define R600_BUS_CNTL 0x5420 +@@ -4234,7 +4258,7 @@ + #define R300_PVS_SRC_ADDR_SEL(x) (x << 29) + #define R300_PVS_SRC_ADDR_MODE_1 (1 << 31) + +-#define R300_VAP_PVS_FLOW_CNTL_OPC 0x22DC ++#define R300_VAP_PVS_FLOW_CNTL_OPC 0x22dc + #define R300_VAP_OUT_VTX_FMT_0 0x2090 + # define R300_VTX_POS_PRESENT (1 << 0) + # define R300_VTX_COLOR_0_PRESENT (1 << 1) +@@ -4322,6 +4346,7 @@ + + #define R300_TX_INVALTAGS 0x4100 + #define R300_TX_FILTER0_0 0x4400 ++#define R300_TX_FILTER0_1 0x4404 + # define R300_TX_CLAMP_S(x) (x << 0) + # define R300_TX_CLAMP_T(x) (x << 3) + # define R300_TX_CLAMP_R(x) (x << 6) +@@ -4339,7 +4364,9 @@ + # define R300_TX_MIN_FILTER_LINEAR (2 << 11) + # define R300_TX_ID_SHIFT 28 + #define R300_TX_FILTER1_0 0x4440 ++#define R300_TX_FILTER1_1 0x4444 + #define R300_TX_FORMAT0_0 0x4480 ++#define R300_TX_FORMAT0_1 0x4484 + # define R300_TXWIDTH_SHIFT 0 + # define R300_TXHEIGHT_SHIFT 11 + # define R300_NUM_LEVELS_SHIFT 26 +@@ -4347,6 +4374,7 @@ + # define R300_TXPROJECTED (1 << 30) + # define R300_TXPITCH_EN (1 << 31) + #define R300_TX_FORMAT1_0 0x44c0 ++#define R300_TX_FORMAT1_1 0x44c4 + # define R300_TX_FORMAT_X8 0x0 + # define R300_TX_FORMAT_X16 0x1 + # define R300_TX_FORMAT_Y4X4 0x2 +@@ -4420,10 +4448,12 @@ + # define R300_TX_FORMAT_SWAP_YUV (1 << 24) + + #define R300_TX_FORMAT2_0 0x4500 ++#define R300_TX_FORMAT2_1 0x4504 + # define R500_TXWIDTH_11 (1 << 15) + # define R500_TXHEIGHT_11 (1 << 16) + + #define R300_TX_OFFSET_0 0x4540 ++#define R300_TX_OFFSET_1 0x4544 + # define R300_ENDIAN_SWAP_16_BIT (1 << 0) + # define R300_ENDIAN_SWAP_32_BIT (2 << 0) + # define R300_ENDIAN_SWAP_HALF_DWORD (3 << 0) +@@ -4500,6 +4530,7 @@ + #define R300_US_TEX_INST_0 0x4620 + #define R300_US_TEX_INST_1 0x4624 + #define R300_US_TEX_INST_2 0x4628 ++#define R300_US_TEX_INST(x) (R300_US_TEX_INST_0 + (x)*4) + # define R300_TEX_SRC_ADDR(x) (x << 0) + # define R300_TEX_DST_ADDR(x) (x << 6) + # define R300_TEX_ID(x) (x << 11) +@@ -4512,11 +4543,13 @@ + #define R300_US_ALU_RGB_ADDR_0 0x46c0 + #define R300_US_ALU_RGB_ADDR_1 0x46c4 + #define R300_US_ALU_RGB_ADDR_2 0x46c8 ++#define R300_US_ALU_RGB_ADDR(x) (R300_US_ALU_RGB_ADDR_0 + (x)*4) + /* for ADDR0-2, values 0-31 specify a location in the pixel stack, + values 32-63 specify a constant */ + # define R300_ALU_RGB_ADDR0(x) (x << 0) + # define R300_ALU_RGB_ADDR1(x) (x << 6) + # define R300_ALU_RGB_ADDR2(x) (x << 12) ++# define R300_ALU_RGB_CONST(x) ((x) | (1 << 5)) + /* ADDRD - where on the pixel stack the result of this instruction + will be written */ + # define R300_ALU_RGB_ADDRD(x) (x << 18) +@@ -4526,6 +4559,7 @@ + # define R300_ALU_RGB_MASK_R 1 + # define R300_ALU_RGB_MASK_G 2 + # define R300_ALU_RGB_MASK_B 4 ++# define R300_ALU_RGB_MASK_RGB 7 + # define R300_ALU_RGB_TARGET_A (0 << 29) + # define R300_ALU_RGB_TARGET_B (1 << 29) + # define R300_ALU_RGB_TARGET_C (2 << 29) +@@ -4533,6 +4567,7 @@ + #define R300_US_ALU_RGB_INST_0 0x48c0 + #define R300_US_ALU_RGB_INST_1 0x48c4 + #define R300_US_ALU_RGB_INST_2 0x48c8 ++#define R300_US_ALU_RGB_INST(x) (R300_US_ALU_RGB_INST_0 + (x)*4) + # define R300_ALU_RGB_SEL_A(x) (x << 0) + # define R300_ALU_RGB_SRC0_RGB 0 + # define R300_ALU_RGB_SRC0_RRR 1 +@@ -4604,11 +4639,13 @@ + #define R300_US_ALU_ALPHA_ADDR_0 0x47c0 + #define R300_US_ALU_ALPHA_ADDR_1 0x47c4 + #define R300_US_ALU_ALPHA_ADDR_2 0x47c8 ++#define R300_US_ALU_ALPHA_ADDR(x) (R300_US_ALU_ALPHA_ADDR_0 + (x)*4) + /* for ADDR0-2, values 0-31 specify a location in the pixel stack, + values 32-63 specify a constant */ + # define R300_ALU_ALPHA_ADDR0(x) (x << 0) + # define R300_ALU_ALPHA_ADDR1(x) (x << 6) + # define R300_ALU_ALPHA_ADDR2(x) (x << 12) ++# define R300_ALU_ALPHA_CONST(x) ((x) | (1 << 5)) + /* ADDRD - where on the pixel stack the result of this instruction + will be written */ + # define R300_ALU_ALPHA_ADDRD(x) (x << 18) +@@ -4624,6 +4661,7 @@ + #define R300_US_ALU_ALPHA_INST_0 0x49c0 + #define R300_US_ALU_ALPHA_INST_1 0x49c4 + #define R300_US_ALU_ALPHA_INST_2 0x49c8 ++#define R300_US_ALU_ALPHA_INST(x) (R300_US_ALU_ALPHA_INST_0 + (x)*4) + # define R300_ALU_ALPHA_SEL_A(x) (x << 0) + # define R300_ALU_ALPHA_SRC0_R 0 + # define R300_ALU_ALPHA_SRC0_G 1 +@@ -4680,6 +4718,15 @@ + # define R300_ALU_ALPHA_OMOD_DIV_8 6 + # define R300_ALU_ALPHA_CLAMP (1 << 30) + ++#define R300_US_ALU_CONST_R_0 0x4c00 ++#define R300_US_ALU_CONST_R(x) (R300_US_ALU_CONST_R_0 + (x)*16) ++#define R300_US_ALU_CONST_G_0 0x4c04 ++#define R300_US_ALU_CONST_G(x) (R300_US_ALU_CONST_G_0 + (x)*16) ++#define R300_US_ALU_CONST_B_0 0x4c08 ++#define R300_US_ALU_CONST_B(x) (R300_US_ALU_CONST_B_0 + (x)*16) ++#define R300_US_ALU_CONST_A_0 0x4c0c ++#define R300_US_ALU_CONST_A(x) (R300_US_ALU_CONST_A_0 + (x)*16) ++ + #define R300_FG_DEPTH_SRC 0x4bd8 + #define R300_FG_FOG_BLEND 0x4bc0 + #define R300_FG_ALPHA_FUNC 0x4bd4 +@@ -4759,10 +4806,11 @@ + + /* R500 US has to be loaded through an index/data pair */ + #define R500_GA_US_VECTOR_INDEX 0x4250 +-# define R500_US_VECTOR_INDEX(x) (x << 0) + # define R500_US_VECTOR_TYPE_INST (0 << 16) + # define R500_US_VECTOR_TYPE_CONST (1 << 16) + # define R500_US_VECTOR_CLAMP (1 << 17) ++# define R500_US_VECTOR_INST_INDEX(x) ((x) | R500_US_VECTOR_TYPE_INST) ++# define R500_US_VECTOR_CONST_INDEX(x) ((x) | R500_US_VECTOR_TYPE_CONST) + #define R500_GA_US_VECTOR_DATA 0x4254 + + /* +diff --git a/src/radeon_textured_video.c b/src/radeon_textured_video.c +index cfa349d..da1d60f 100644 +--- a/src/radeon_textured_video.c ++++ b/src/radeon_textured_video.c +@@ -93,6 +93,7 @@ static __inline__ uint32_t F_TO_DW(float val) + #undef VIDEO_PREAMBLE + #undef BEGIN_VIDEO + #undef OUT_VIDEO_REG ++#undef OUT_VIDEO_REG_F + #undef FINISH_VIDEO + + #ifdef XF86DRI +@@ -103,6 +104,7 @@ static __inline__ uint32_t F_TO_DW(float val) + RADEONCP_REFRESH(pScrn, info) + #define BEGIN_VIDEO(n) BEGIN_RING(2*(n)) + #define OUT_VIDEO_REG(reg, val) OUT_RING_REG(reg, val) ++#define OUT_VIDEO_REG_F(reg, val) OUT_VIDEO_REG(reg, F_TO_DW(val)) + #define FINISH_VIDEO() ADVANCE_RING() + #define OUT_VIDEO_RING_F(x) OUT_RING(F_TO_DW(x)) + +@@ -199,6 +201,18 @@ RADEONPutImageTextured(ScrnInfoPtr pScrn, + return BadAlloc; + } + ++ /* Bicubic filter loading */ ++ if (!IS_R500_3D) ++ pPriv->bicubic_enabled = FALSE; ++ if (pPriv->bicubic_memory == NULL && pPriv->bicubic_enabled) { ++ pPriv->bicubic_offset = RADEONAllocateMemory(pScrn, ++ &pPriv->bicubic_memory, ++ sizeof(bicubic_tex_512)); ++ pPriv->bicubic_src_offset = pPriv->bicubic_offset + info->fbLocation + pScrn->fbOffset; ++ if (pPriv->bicubic_offset == 0) ++ pPriv->bicubic_enabled = FALSE; ++ } ++ + if (pDraw->type == DRAWABLE_WINDOW) + pPriv->pPixmap = (*pScreen->GetWindowPixmap)((WindowPtr)pDraw); + else +@@ -267,6 +281,10 @@ RADEONPutImageTextured(ScrnInfoPtr pScrn, + break; + } + ++ /* Upload bicubic filter tex */ ++ if (pPriv->bicubic_enabled) ++ RADEONCopyData(pScrn, (uint8_t *)bicubic_tex_512, (uint8_t *)(info->FB + pPriv->bicubic_offset), 1024, 1024, 1, 512, 2); ++ + /* update cliplist */ + if (!REGION_EQUAL(pScrn->pScreen, &pPriv->clip, clipBoxes)) { + REGION_COPY(pScrn->pScreen, &pPriv->clip, clipBoxes); +@@ -320,12 +338,16 @@ static XF86VideoFormatRec Formats[NUM_FORMATS] = + {15, TrueColor}, {16, TrueColor}, {24, TrueColor} + }; + +-#define NUM_ATTRIBUTES 0 ++#define NUM_ATTRIBUTES 1 + +-static XF86AttributeRec Attributes[NUM_ATTRIBUTES] = ++static XF86AttributeRec Attributes[NUM_ATTRIBUTES+1] = + { ++ {XvSettable | XvGettable, 0, 1, "XV_BICUBIC"}, ++ {0, 0, 0, NULL} + }; + ++static Atom xvBicubic; ++ + #define NUM_IMAGES 4 + + static XF86ImageRec Images[NUM_IMAGES] = +@@ -336,6 +358,44 @@ static XF86ImageRec Images[NUM_IMAGES] = + XVIMAGE_UYVY + }; + ++int ++RADEONGetTexPortAttribute(ScrnInfoPtr pScrn, ++ Atom attribute, ++ INT32 *value, ++ pointer data) ++{ ++ RADEONInfoPtr info = RADEONPTR(pScrn); ++ RADEONPortPrivPtr pPriv = (RADEONPortPrivPtr)data; ++ ++ if (info->accelOn) RADEON_SYNC(info, pScrn); ++ ++ if (attribute == xvBicubic) ++ *value = pPriv->bicubic_enabled ? 1 : 0; ++ else ++ return BadMatch; ++ ++ return Success; ++} ++ ++int ++RADEONSetTexPortAttribute(ScrnInfoPtr pScrn, ++ Atom attribute, ++ INT32 value, ++ pointer data) ++{ ++ RADEONInfoPtr info = RADEONPTR(pScrn); ++ RADEONPortPrivPtr pPriv = (RADEONPortPrivPtr)data; ++ ++ RADEON_SYNC(info, pScrn); ++ ++ if (attribute == xvBicubic) ++ pPriv->bicubic_enabled = ClipValue (value, 0, 1); ++ else ++ return BadMatch; ++ ++ return Success; ++} ++ + XF86VideoAdaptorPtr + RADEONSetupImageTexturedVideo(ScreenPtr pScreen) + { +@@ -351,6 +411,8 @@ RADEONSetupImageTexturedVideo(ScreenPtr pScreen) + if (adapt == NULL) + return NULL; + ++ xvBicubic = MAKE_ATOM("XV_BICUBIC"); ++ + adapt->type = XvWindowMask | XvInputMask | XvImageMask; + adapt->flags = 0; + adapt->name = "Radeon Textured Video"; +@@ -367,8 +429,13 @@ RADEONSetupImageTexturedVideo(ScreenPtr pScreen) + pPortPriv = + (RADEONPortPrivPtr)(&adapt->pPortPrivates[num_texture_ports]); + +- adapt->nAttributes = NUM_ATTRIBUTES; +- adapt->pAttributes = Attributes; ++ if (IS_R500_3D) { ++ adapt->nAttributes = NUM_ATTRIBUTES; ++ adapt->pAttributes = Attributes; ++ } else { ++ adapt->nAttributes = 0; ++ adapt->pAttributes = NULL; ++ } + adapt->pImages = Images; + adapt->nImages = NUM_IMAGES; + adapt->PutVideo = NULL; +@@ -376,8 +443,8 @@ RADEONSetupImageTexturedVideo(ScreenPtr pScreen) + adapt->GetVideo = NULL; + adapt->GetStill = NULL; + adapt->StopVideo = RADEONStopVideo; +- adapt->SetPortAttribute = RADEONSetPortAttribute; +- adapt->GetPortAttribute = RADEONGetPortAttribute; ++ adapt->SetPortAttribute = RADEONSetTexPortAttribute; ++ adapt->GetPortAttribute = RADEONGetTexPortAttribute; + adapt->QueryBestSize = RADEONQueryBestSize; + adapt->PutImage = RADEONPutImageTextured; + adapt->ReputImage = NULL; +@@ -390,6 +457,7 @@ RADEONSetupImageTexturedVideo(ScreenPtr pScreen) + pPriv->videoStatus = 0; + pPriv->currentBuffer = 0; + pPriv->doubleBuffer = 0; ++ pPriv->bicubic_enabled = (info->ChipFamily >= CHIP_FAMILY_RV515); + + /* gotta uninit this someplace, XXX: shouldn't be necessary for textured */ + REGION_NULL(pScreen, &pPriv->clip); diff --git a/src/radeon_textured_videofuncs.c b/src/radeon_textured_videofuncs.c -index 277d9b2..d39f74d 100644 +index 277d9b2..b53e114 100644 --- a/src/radeon_textured_videofuncs.c +++ b/src/radeon_textured_videofuncs.c -@@ -486,6 +486,8 @@ FUNC_NAME(RADEONDisplayTexturedVideo)(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv +@@ -45,10 +45,21 @@ + #endif + #endif + ++#define VTX_DWORD_COUNT_FILTER 6 + #define VTX_DWORD_COUNT 4 + + #ifdef ACCEL_CP + ++#define VTX_OUT_FILTER(_dstX, _dstY, _srcX, _srcY, _maskX, _maskY) \ ++do { \ ++ OUT_VIDEO_RING_F(_dstX); \ ++ OUT_VIDEO_RING_F(_dstY); \ ++ OUT_VIDEO_RING_F(_srcX); \ ++ OUT_VIDEO_RING_F(_srcY); \ ++ OUT_VIDEO_RING_F(_maskX); \ ++ OUT_VIDEO_RING_F(_maskY); \ ++} while (0) ++ + #define VTX_OUT(_dstX, _dstY, _srcX, _srcY) \ + do { \ + OUT_VIDEO_RING_F(_dstX); \ +@@ -59,6 +70,16 @@ do { \ + + #else /* ACCEL_CP */ + ++#define VTX_OUT_FILTER(_dstX, _dstY, _srcX, _srcY, _maskX, _maskY) \ ++do { \ ++ OUT_VIDEO_REG_F(RADEON_SE_PORT_DATA0, _dstX); \ ++ OUT_VIDEO_REG_F(RADEON_SE_PORT_DATA0, _dstY); \ ++ OUT_VIDEO_REG_F(RADEON_SE_PORT_DATA0, _srcX); \ ++ OUT_VIDEO_REG_F(RADEON_SE_PORT_DATA0, _srcY); \ ++ OUT_VIDEO_REG_F(RADEON_SE_PORT_DATA0, _maskX); \ ++ OUT_VIDEO_REG_F(RADEON_SE_PORT_DATA0, _maskY); \ ++} while (0) ++ + #define VTX_OUT(_dstX, _dstY, _srcX, _srcY) \ + do { \ + OUT_VIDEO_REG_F(RADEON_SE_PORT_DATA0, _dstX); \ +@@ -79,7 +100,7 @@ FUNC_NAME(RADEONDisplayTexturedVideo)(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv + uint32_t dst_offset, dst_pitch, dst_format; + uint32_t txenable, colorpitch; + uint32_t blendcntl; +- int dstxoff, dstyoff, pixel_shift; ++ int dstxoff, dstyoff, pixel_shift, vtx_count; + BoxPtr pBox = REGION_RECTS(&pPriv->clip); + int nBox = REGION_NUM_RECTS(&pPriv->clip); + VIDEO_PREAMBLE(); +@@ -123,6 +144,11 @@ FUNC_NAME(RADEONDisplayTexturedVideo)(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv + RADEON_WAIT_DMA_GUI_IDLE); + FINISH_VIDEO(); + ++ if (pPriv->bicubic_enabled) ++ vtx_count = VTX_DWORD_COUNT_FILTER; ++ else ++ vtx_count = VTX_DWORD_COUNT; ++ + if (IS_R300_3D || IS_R500_3D) { + uint32_t output_fmt; + +@@ -160,16 +186,17 @@ FUNC_NAME(RADEONDisplayTexturedVideo)(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv + txformat1 |= R300_TX_FORMAT_YUV_TO_RGB_CLAMP; + + txformat0 = ((((pPriv->w - 1) & 0x7ff) << R300_TXWIDTH_SHIFT) | +- (((pPriv->h - 1) & 0x7ff) << R300_TXHEIGHT_SHIFT)); +- +- txformat0 |= R300_TXPITCH_EN; ++ (((pPriv->h - 1) & 0x7ff) << R300_TXHEIGHT_SHIFT) | ++ R300_TXPITCH_EN); + + info->texW[0] = pPriv->w; + info->texH[0] = pPriv->h; + + txfilter = (R300_TX_CLAMP_S(R300_TX_CLAMP_CLAMP_LAST) | + R300_TX_CLAMP_T(R300_TX_CLAMP_CLAMP_LAST) | +- R300_TX_MAG_FILTER_LINEAR | R300_TX_MIN_FILTER_LINEAR); ++ R300_TX_MAG_FILTER_LINEAR | ++ R300_TX_MIN_FILTER_LINEAR | ++ (0 << R300_TX_ID_SHIFT)); + + /* pitch is in pixels */ + txpitch = pPriv->src_pitch / 2; +@@ -194,11 +221,47 @@ FUNC_NAME(RADEONDisplayTexturedVideo)(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv + + txenable = R300_TEX_0_ENABLE; + ++ if (pPriv->bicubic_enabled) { ++ /* Size is 128x1 */ ++ txformat0 = ((0x7f << R300_TXWIDTH_SHIFT) | ++ (0x0 << R300_TXHEIGHT_SHIFT) | ++ R300_TXPITCH_EN); ++ /* Format is 32-bit floats, 4bpp */ ++ txformat1 = R300_EASY_TX_FORMAT(Z, Y, X, W, FL_R16G16B16A16); ++ /* Pitch is 127 (128-1) */ ++ txpitch = 0x7f; ++ /* Tex filter */ ++ txfilter = (R300_TX_CLAMP_S(R300_TX_CLAMP_WRAP) | ++ R300_TX_CLAMP_T(R300_TX_CLAMP_WRAP) | ++ R300_TX_MIN_FILTER_NEAREST | ++ R300_TX_MAG_FILTER_NEAREST | ++ (1 << R300_TX_ID_SHIFT)); ++ ++ BEGIN_VIDEO(6); ++ OUT_VIDEO_REG(R300_TX_FILTER0_1, txfilter); ++ OUT_VIDEO_REG(R300_TX_FILTER1_1, 0); ++ OUT_VIDEO_REG(R300_TX_FORMAT0_1, txformat0); ++ OUT_VIDEO_REG(R300_TX_FORMAT1_1, txformat1); ++ OUT_VIDEO_REG(R300_TX_FORMAT2_1, txpitch); ++ OUT_VIDEO_REG(R300_TX_OFFSET_1, pPriv->bicubic_src_offset); ++ FINISH_VIDEO(); ++ ++ /* Enable tex 1 */ ++ txenable |= R300_TEX_1_ENABLE; ++ } ++ + /* setup the VAP */ +- if (info->has_tcl) +- BEGIN_VIDEO(6); +- else +- BEGIN_VIDEO(4); ++ if (info->has_tcl) { ++ if (pPriv->bicubic_enabled) ++ BEGIN_VIDEO(7); ++ else ++ BEGIN_VIDEO(6); ++ } else { ++ if (pPriv->bicubic_enabled) ++ BEGIN_VIDEO(5); ++ else ++ BEGIN_VIDEO(4); ++ } + + /* These registers define the number, type, and location of data submitted + * to the PVS unit of GA input (when PVS is disabled) +@@ -213,42 +276,74 @@ FUNC_NAME(RADEONDisplayTexturedVideo)(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv + * Textures 0-7 + * Fog + */ +- OUT_VIDEO_REG(R300_VAP_PROG_STREAM_CNTL_0, +- ((R300_DATA_TYPE_FLOAT_2 << R300_DATA_TYPE_0_SHIFT) | +- (0 << R300_SKIP_DWORDS_0_SHIFT) | +- (0 << R300_DST_VEC_LOC_0_SHIFT) | +- R300_SIGNED_0 | +- (R300_DATA_TYPE_FLOAT_2 << R300_DATA_TYPE_1_SHIFT) | +- (0 << R300_SKIP_DWORDS_1_SHIFT) | +- (6 << R300_DST_VEC_LOC_1_SHIFT) | +- R300_LAST_VEC_1 | +- R300_SIGNED_1)); ++ if (pPriv->bicubic_enabled) { ++ OUT_VIDEO_REG(R300_VAP_PROG_STREAM_CNTL_0, ++ ((R300_DATA_TYPE_FLOAT_2 << R300_DATA_TYPE_0_SHIFT) | ++ (0 << R300_SKIP_DWORDS_0_SHIFT) | ++ (0 << R300_DST_VEC_LOC_0_SHIFT) | ++ R300_SIGNED_0 | ++ (R300_DATA_TYPE_FLOAT_2 << R300_DATA_TYPE_1_SHIFT) | ++ (0 << R300_SKIP_DWORDS_1_SHIFT) | ++ (6 << R300_DST_VEC_LOC_1_SHIFT) | ++ R300_SIGNED_1)); ++ OUT_VIDEO_REG(R300_VAP_PROG_STREAM_CNTL_1, ++ ((R300_DATA_TYPE_FLOAT_2 << R300_DATA_TYPE_2_SHIFT) | ++ (0 << R300_SKIP_DWORDS_2_SHIFT) | ++ (7 << R300_DST_VEC_LOC_2_SHIFT) | ++ R300_LAST_VEC_2 | ++ R300_SIGNED_2)); ++ } else { ++ OUT_VIDEO_REG(R300_VAP_PROG_STREAM_CNTL_0, ++ ((R300_DATA_TYPE_FLOAT_2 << R300_DATA_TYPE_0_SHIFT) | ++ (0 << R300_SKIP_DWORDS_0_SHIFT) | ++ (0 << R300_DST_VEC_LOC_0_SHIFT) | ++ R300_SIGNED_0 | ++ (R300_DATA_TYPE_FLOAT_2 << R300_DATA_TYPE_1_SHIFT) | ++ (0 << R300_SKIP_DWORDS_1_SHIFT) | ++ (6 << R300_DST_VEC_LOC_1_SHIFT) | ++ R300_LAST_VEC_1 | ++ R300_SIGNED_1)); ++ } + + /* load the vertex shader + * We pre-load vertex programs in RADEONInit3DEngine(): ++ * - exa mask/Xv bicubic + * - exa no mask +- * - exa mask + * - Xv + * Here we select the offset of the vertex program we want to use + */ + if (info->has_tcl) { +- OUT_VIDEO_REG(R300_VAP_PVS_CODE_CNTL_0, +- ((5 << R300_PVS_FIRST_INST_SHIFT) | +- (6 << R300_PVS_XYZW_VALID_INST_SHIFT) | +- (6 << R300_PVS_LAST_INST_SHIFT))); +- OUT_VIDEO_REG(R300_VAP_PVS_CODE_CNTL_1, +- (6 << R300_PVS_LAST_VTX_SRC_INST_SHIFT)); ++ if (pPriv->bicubic_enabled) { ++ OUT_VIDEO_REG(R300_VAP_PVS_CODE_CNTL_0, ++ ((0 << R300_PVS_FIRST_INST_SHIFT) | ++ (2 << R300_PVS_XYZW_VALID_INST_SHIFT) | ++ (2 << R300_PVS_LAST_INST_SHIFT))); ++ OUT_VIDEO_REG(R300_VAP_PVS_CODE_CNTL_1, ++ (2 << R300_PVS_LAST_VTX_SRC_INST_SHIFT)); ++ } else { ++ OUT_VIDEO_REG(R300_VAP_PVS_CODE_CNTL_0, ++ ((5 << R300_PVS_FIRST_INST_SHIFT) | ++ (6 << R300_PVS_XYZW_VALID_INST_SHIFT) | ++ (6 << R300_PVS_LAST_INST_SHIFT))); ++ OUT_VIDEO_REG(R300_VAP_PVS_CODE_CNTL_1, ++ (6 << R300_PVS_LAST_VTX_SRC_INST_SHIFT)); ++ } + } + + /* Position and one set of 2 texture coordinates */ + OUT_VIDEO_REG(R300_VAP_OUT_VTX_FMT_0, R300_VTX_POS_PRESENT); +- OUT_VIDEO_REG(R300_VAP_OUT_VTX_FMT_1, (2 << R300_TEX_0_COMP_CNT_SHIFT)); ++ if (pPriv->bicubic_enabled) ++ OUT_VIDEO_REG(R300_VAP_OUT_VTX_FMT_1, ((2 << R300_TEX_0_COMP_CNT_SHIFT) | ++ (2 << R300_TEX_1_COMP_CNT_SHIFT))); ++ else ++ OUT_VIDEO_REG(R300_VAP_OUT_VTX_FMT_1, (2 << R300_TEX_0_COMP_CNT_SHIFT)); ++ + OUT_VIDEO_REG(R300_US_OUT_FMT_0, output_fmt); + FINISH_VIDEO(); + + /* setup pixel shader */ + if (IS_R300_3D) { +- BEGIN_VIDEO(8); ++ BEGIN_VIDEO(9); + /* 2 components: 2 for tex0 */ + OUT_VIDEO_REG(R300_RS_COUNT, + ((2 << R300_RS_COUNT_IT_COUNT_SHIFT) | +@@ -256,6 +351,8 @@ FUNC_NAME(RADEONDisplayTexturedVideo)(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv + /* R300_INST_COUNT_RS - highest RS instruction used */ + OUT_VIDEO_REG(R300_RS_INST_COUNT, R300_INST_COUNT_RS(0) | R300_TX_OFFSET_RS(6)); + ++ OUT_VIDEO_REG(R300_US_PIXSIZE, 0); /* highest temp used */ ++ + OUT_VIDEO_REG(R300_US_CODE_OFFSET, + (R300_ALU_CODE_OFFSET(0) | + R300_ALU_CODE_SIZE(1) | +@@ -313,102 +410,577 @@ FUNC_NAME(RADEONDisplayTexturedVideo)(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv + R300_ALU_ALPHA_CLAMP)); + FINISH_VIDEO(); + } else { +- BEGIN_VIDEO(18); +- /* 2 components: 2 for tex0 */ +- OUT_VIDEO_REG(R300_RS_COUNT, +- ((2 << R300_RS_COUNT_IT_COUNT_SHIFT) | +- R300_RS_COUNT_HIRES_EN)); +- +- /* R300_INST_COUNT_RS - highest RS instruction used */ +- OUT_VIDEO_REG(R300_RS_INST_COUNT, R300_INST_COUNT_RS(0) | R300_TX_OFFSET_RS(6)); +- +- OUT_VIDEO_REG(R500_US_CODE_ADDR, (R500_US_CODE_START_ADDR(0) | +- R500_US_CODE_END_ADDR(1))); +- OUT_VIDEO_REG(R500_US_CODE_RANGE, (R500_US_CODE_RANGE_ADDR(0) | +- R500_US_CODE_RANGE_SIZE(1))); +- OUT_VIDEO_REG(R500_US_CODE_OFFSET, 0); +- OUT_VIDEO_REG(R500_GA_US_VECTOR_INDEX, 0); +- +- /* tex inst */ +- OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_INST_TYPE_TEX | +- R500_INST_TEX_SEM_WAIT | +- R500_INST_RGB_WMASK_R | +- R500_INST_RGB_WMASK_G | +- R500_INST_RGB_WMASK_B | +- R500_INST_ALPHA_WMASK | +- R500_INST_RGB_CLAMP | +- R500_INST_ALPHA_CLAMP)); +- +- OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_TEX_ID(0) | +- R500_TEX_INST_LD | +- R500_TEX_SEM_ACQUIRE | +- R500_TEX_IGNORE_UNCOVERED)); +- +- OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_TEX_SRC_ADDR(0) | +- R500_TEX_SRC_S_SWIZ_R | +- R500_TEX_SRC_T_SWIZ_G | +- R500_TEX_DST_ADDR(0) | +- R500_TEX_DST_R_SWIZ_R | +- R500_TEX_DST_G_SWIZ_G | +- R500_TEX_DST_B_SWIZ_B | +- R500_TEX_DST_A_SWIZ_A)); +- OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_DX_ADDR(0) | +- R500_DX_S_SWIZ_R | +- R500_DX_T_SWIZ_R | +- R500_DX_R_SWIZ_R | +- R500_DX_Q_SWIZ_R | +- R500_DY_ADDR(0) | +- R500_DY_S_SWIZ_R | +- R500_DY_T_SWIZ_R | +- R500_DY_R_SWIZ_R | +- R500_DY_Q_SWIZ_R)); +- OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, 0x00000000); +- OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, 0x00000000); +- +- /* ALU inst */ +- OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_INST_TYPE_OUT | +- R500_INST_TEX_SEM_WAIT | +- R500_INST_LAST | +- R500_INST_RGB_OMASK_R | +- R500_INST_RGB_OMASK_G | +- R500_INST_RGB_OMASK_B | +- R500_INST_ALPHA_OMASK | +- R500_INST_RGB_CLAMP | +- R500_INST_ALPHA_CLAMP)); +- +- OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_RGB_ADDR0(0) | +- R500_RGB_ADDR1(0) | +- R500_RGB_ADDR1_CONST | +- R500_RGB_ADDR2(0) | +- R500_RGB_ADDR2_CONST)); +- OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_ALPHA_ADDR0(0) | +- R500_ALPHA_ADDR1(0) | +- R500_ALPHA_ADDR1_CONST | +- R500_ALPHA_ADDR2(0) | +- R500_ALPHA_ADDR2_CONST)); +- +- OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_ALU_RGB_SEL_A_SRC0 | +- R500_ALU_RGB_R_SWIZ_A_R | +- R500_ALU_RGB_G_SWIZ_A_G | +- R500_ALU_RGB_B_SWIZ_A_B | +- R500_ALU_RGB_SEL_B_SRC0 | +- R500_ALU_RGB_R_SWIZ_B_1 | +- R500_ALU_RGB_B_SWIZ_B_1 | +- R500_ALU_RGB_G_SWIZ_B_1)); +- +- OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_ALPHA_OP_MAD | +- R500_ALPHA_SWIZ_A_A | +- R500_ALPHA_SWIZ_B_1)); +- +- OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_ALU_RGBA_OP_MAD | +- R500_ALU_RGBA_R_SWIZ_0 | +- R500_ALU_RGBA_G_SWIZ_0 | +- R500_ALU_RGBA_B_SWIZ_0 | +- R500_ALU_RGBA_A_SWIZ_0)); +- FINISH_VIDEO(); ++ if (pPriv->bicubic_enabled) { ++ BEGIN_VIDEO(7); ++ ++ /* 4 components: 2 for tex0 and 2 for tex1 */ ++ OUT_VIDEO_REG(R300_RS_COUNT, ++ ((4 << R300_RS_COUNT_IT_COUNT_SHIFT) | ++ R300_RS_COUNT_HIRES_EN)); ++ ++ /* R300_INST_COUNT_RS - highest RS instruction used */ ++ OUT_VIDEO_REG(R300_RS_INST_COUNT, R300_INST_COUNT_RS(1) | R300_TX_OFFSET_RS(6)); ++ ++ /* Pixel stack frame size. */ ++ OUT_VIDEO_REG(R300_US_PIXSIZE, 5); ++ ++ /* FP length. */ ++ OUT_VIDEO_REG(R500_US_CODE_ADDR, (R500_US_CODE_START_ADDR(0) | ++ R500_US_CODE_END_ADDR(13))); ++ OUT_VIDEO_REG(R500_US_CODE_RANGE, (R500_US_CODE_RANGE_ADDR(0) | ++ R500_US_CODE_RANGE_SIZE(13))); ++ ++ /* Prepare for FP emission. */ ++ OUT_VIDEO_REG(R500_US_CODE_OFFSET, 0); ++ OUT_VIDEO_REG(R500_GA_US_VECTOR_INDEX, R500_US_VECTOR_INST_INDEX(0)); ++ FINISH_VIDEO(); ++ ++ BEGIN_VIDEO(89); ++ /* Pixel shader. ++ * I've gone ahead and annotated each instruction, since this ++ * thing is MASSIVE. :3 ++ * Note: In order to avoid buggies with temps and multiple ++ * inputs, all temps are offset by 2. temp0 -> register2. */ ++ ++ /* TEX temp2, input1.xxxx, tex1, 1D */ ++ OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_INST_TYPE_TEX | ++ R500_INST_RGB_WMASK_R | ++ R500_INST_RGB_WMASK_G | ++ R500_INST_RGB_WMASK_B)); ++ OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_TEX_ID(1) | ++ R500_TEX_INST_LD | ++ R500_TEX_IGNORE_UNCOVERED)); ++ OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_TEX_SRC_ADDR(1) | ++ R500_TEX_SRC_S_SWIZ_R | ++ R500_TEX_SRC_T_SWIZ_R | ++ R500_TEX_SRC_R_SWIZ_R | ++ R500_TEX_SRC_Q_SWIZ_R | ++ R500_TEX_DST_ADDR(2) | ++ R500_TEX_DST_R_SWIZ_R | ++ R500_TEX_DST_G_SWIZ_G | ++ R500_TEX_DST_B_SWIZ_B | ++ R500_TEX_DST_A_SWIZ_A)); ++ OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, 0x00000000); ++ OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, 0x00000000); ++ OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, 0x00000000); ++ ++ /* TEX temp5, input1.yyyy, tex1, 1D */ ++ OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_INST_TYPE_TEX | ++ R500_INST_TEX_SEM_WAIT | ++ R500_INST_RGB_WMASK_R | ++ R500_INST_RGB_WMASK_G | ++ R500_INST_RGB_WMASK_B)); ++ OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_TEX_ID(1) | ++ R500_TEX_INST_LD | ++ R500_TEX_SEM_ACQUIRE | ++ R500_TEX_IGNORE_UNCOVERED)); ++ OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_TEX_SRC_ADDR(1) | ++ R500_TEX_SRC_S_SWIZ_G | ++ R500_TEX_SRC_T_SWIZ_G | ++ R500_TEX_SRC_R_SWIZ_G | ++ R500_TEX_SRC_Q_SWIZ_G | ++ R500_TEX_DST_ADDR(5) | ++ R500_TEX_DST_R_SWIZ_R | ++ R500_TEX_DST_G_SWIZ_G | ++ R500_TEX_DST_B_SWIZ_B | ++ R500_TEX_DST_A_SWIZ_A)); ++ OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, 0x00000000); ++ OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, 0x00000000); ++ OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, 0x00000000); ++ ++ /* MUL temp4, const0.x0x0, temp2.yyxx */ ++ OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_INST_TYPE_ALU | ++ R500_INST_TEX_SEM_WAIT | ++ R500_INST_RGB_WMASK_R | ++ R500_INST_RGB_WMASK_G | ++ R500_INST_RGB_WMASK_B | ++ R500_INST_ALPHA_WMASK)); ++ OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_RGB_ADDR0(0) | ++ R500_RGB_ADDR0_CONST | ++ R500_RGB_ADDR1(2))); ++ OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_ALPHA_ADDR0(0) | ++ R500_ALPHA_ADDR0_CONST | ++ R500_ALPHA_ADDR1(2))); ++ OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_ALU_RGB_SEL_A_SRC0 | ++ R500_ALU_RGB_R_SWIZ_A_R | ++ R500_ALU_RGB_G_SWIZ_A_0 | ++ R500_ALU_RGB_B_SWIZ_A_R | ++ R500_ALU_RGB_SEL_B_SRC1 | ++ R500_ALU_RGB_R_SWIZ_B_G | ++ R500_ALU_RGB_G_SWIZ_B_G | ++ R500_ALU_RGB_B_SWIZ_B_R)); ++ OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_ALPHA_ADDRD(4) | ++ R500_ALPHA_OP_MAD | ++ R500_ALPHA_SEL_A_SRC0 | ++ R500_ALPHA_SWIZ_A_0 | ++ R500_ALPHA_SEL_B_SRC1 | ++ R500_ALPHA_SWIZ_B_R)); ++ OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_ALU_RGBA_ADDRD(4) | ++ R500_ALU_RGBA_OP_MAD | ++ R500_ALU_RGBA_R_SWIZ_0 | ++ R500_ALU_RGBA_G_SWIZ_0 | ++ R500_ALU_RGBA_B_SWIZ_0 | ++ R500_ALU_RGBA_A_SWIZ_0)); ++ ++ /* MAD temp3, const0.0y0y, temp5.xxxx, temp4 */ ++ OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_INST_TYPE_ALU | ++ R500_INST_RGB_WMASK_R | ++ R500_INST_RGB_WMASK_G | ++ R500_INST_RGB_WMASK_B | ++ R500_INST_ALPHA_WMASK)); ++ OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_RGB_ADDR0(0) | ++ R500_RGB_ADDR0_CONST | ++ R500_RGB_ADDR1(5) | ++ R500_RGB_ADDR2(4))); ++ OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_ALPHA_ADDR0(0) | ++ R500_ALPHA_ADDR0_CONST | ++ R500_ALPHA_ADDR1(5) | ++ R500_ALPHA_ADDR2(4))); ++ OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_ALU_RGB_SEL_A_SRC0 | ++ R500_ALU_RGB_R_SWIZ_A_0 | ++ R500_ALU_RGB_G_SWIZ_A_G | ++ R500_ALU_RGB_B_SWIZ_A_0 | ++ R500_ALU_RGB_SEL_B_SRC1 | ++ R500_ALU_RGB_R_SWIZ_B_R | ++ R500_ALU_RGB_G_SWIZ_B_R | ++ R500_ALU_RGB_B_SWIZ_B_R)); ++ OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_ALPHA_ADDRD(3) | ++ R500_ALPHA_OP_MAD | ++ R500_ALPHA_SEL_A_SRC0 | ++ R500_ALPHA_SWIZ_A_G | ++ R500_ALPHA_SEL_B_SRC1 | ++ R500_ALPHA_SWIZ_B_R)); ++ OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_ALU_RGBA_ADDRD(3) | ++ R500_ALU_RGBA_OP_MAD | ++ R500_ALU_RGBA_SEL_C_SRC2 | ++ R500_ALU_RGBA_R_SWIZ_R | ++ R500_ALU_RGBA_G_SWIZ_G | ++ R500_ALU_RGBA_B_SWIZ_B | ++ R500_ALU_RGBA_A_SWIZ_A)); ++ ++ /* ADD temp3, temp3, input0.xyxy */ ++ OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_INST_TYPE_ALU | ++ R500_INST_RGB_WMASK_R | ++ R500_INST_RGB_WMASK_G | ++ R500_INST_RGB_WMASK_B | ++ R500_INST_ALPHA_WMASK)); ++ OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_RGB_ADDR1(3) | ++ R500_RGB_ADDR2(0))); ++ OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_ALPHA_ADDR1(3) | ++ R500_ALPHA_ADDR2(0))); ++ OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_ALU_RGB_R_SWIZ_A_1 | ++ R500_ALU_RGB_G_SWIZ_A_1 | ++ R500_ALU_RGB_B_SWIZ_A_1 | ++ R500_ALU_RGB_SEL_B_SRC1 | ++ R500_ALU_RGB_R_SWIZ_B_R | ++ R500_ALU_RGB_G_SWIZ_B_G | ++ R500_ALU_RGB_B_SWIZ_B_B)); ++ OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_ALPHA_ADDRD(3) | ++ R500_ALPHA_OP_MAD | ++ R500_ALPHA_SWIZ_A_1 | ++ R500_ALPHA_SEL_B_SRC1 | ++ R500_ALPHA_SWIZ_B_A)); ++ OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_ALU_RGBA_ADDRD(3) | ++ R500_ALU_RGBA_OP_MAD | ++ R500_ALU_RGBA_SEL_C_SRC2 | ++ R500_ALU_RGBA_R_SWIZ_R | ++ R500_ALU_RGBA_G_SWIZ_G | ++ R500_ALU_RGBA_B_SWIZ_R | ++ R500_ALU_RGBA_A_SWIZ_G)); ++ ++ /* TEX temp1, temp3.zwxy, tex0, 1D */ ++ OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_INST_TYPE_TEX | ++ R500_INST_RGB_WMASK_R | ++ R500_INST_RGB_WMASK_G | ++ R500_INST_RGB_WMASK_B | ++ R500_INST_ALPHA_WMASK)); ++ OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_TEX_ID(0) | ++ R500_TEX_INST_LD | ++ R500_TEX_IGNORE_UNCOVERED)); ++ OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_TEX_SRC_ADDR(3) | ++ R500_TEX_SRC_S_SWIZ_B | ++ R500_TEX_SRC_T_SWIZ_A | ++ R500_TEX_SRC_R_SWIZ_R | ++ R500_TEX_SRC_Q_SWIZ_G | ++ R500_TEX_DST_ADDR(1) | ++ R500_TEX_DST_R_SWIZ_R | ++ R500_TEX_DST_G_SWIZ_G | ++ R500_TEX_DST_B_SWIZ_B | ++ R500_TEX_DST_A_SWIZ_A)); ++ OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, 0x00000000); ++ OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, 0x00000000); ++ OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, 0x00000000); ++ ++ /* TEX temp3, temp3.xyzw, tex0, 1D */ ++ OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_INST_TYPE_TEX | ++ R500_INST_TEX_SEM_WAIT | ++ R500_INST_RGB_WMASK_R | ++ R500_INST_RGB_WMASK_G | ++ R500_INST_RGB_WMASK_B | ++ R500_INST_ALPHA_WMASK)); ++ OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_TEX_ID(0) | ++ R500_TEX_INST_LD | ++ R500_TEX_SEM_ACQUIRE | ++ R500_TEX_IGNORE_UNCOVERED)); ++ OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_TEX_SRC_ADDR(3) | ++ R500_TEX_SRC_S_SWIZ_R | ++ R500_TEX_SRC_T_SWIZ_G | ++ R500_TEX_SRC_R_SWIZ_B | ++ R500_TEX_SRC_Q_SWIZ_A | ++ R500_TEX_DST_ADDR(3) | ++ R500_TEX_DST_R_SWIZ_R | ++ R500_TEX_DST_G_SWIZ_G | ++ R500_TEX_DST_B_SWIZ_B | ++ R500_TEX_DST_A_SWIZ_A)); ++ OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, 0x00000000); ++ OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, 0x00000000); ++ OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, 0x00000000); ++ ++ /* MAD temp4, const1.0y0y, temp5.yyyy, temp4 */ ++ OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_INST_TYPE_ALU | ++ R500_INST_RGB_WMASK_R | ++ R500_INST_RGB_WMASK_G | ++ R500_INST_RGB_WMASK_B | ++ R500_INST_ALPHA_WMASK)); ++ OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_RGB_ADDR0(0) | ++ R500_RGB_ADDR0_CONST | ++ R500_RGB_ADDR1(5) | ++ R500_RGB_ADDR2(4))); ++ OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_ALPHA_ADDR0(0) | ++ R500_ALPHA_ADDR0_CONST | ++ R500_ALPHA_ADDR1(5) | ++ R500_ALPHA_ADDR2(4))); ++ OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_ALU_RGB_SEL_A_SRC0 | ++ R500_ALU_RGB_R_SWIZ_A_0 | ++ R500_ALU_RGB_G_SWIZ_A_G | ++ R500_ALU_RGB_B_SWIZ_A_0 | ++ R500_ALU_RGB_SEL_B_SRC1 | ++ R500_ALU_RGB_R_SWIZ_B_G | ++ R500_ALU_RGB_G_SWIZ_B_G | ++ R500_ALU_RGB_B_SWIZ_B_G)); ++ OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_ALPHA_ADDRD(4) | ++ R500_ALPHA_OP_MAD | ++ R500_ALPHA_SEL_A_SRC0 | ++ R500_ALPHA_SWIZ_A_G | ++ R500_ALPHA_SEL_B_SRC1 | ++ R500_ALPHA_SWIZ_B_G)); ++ OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_ALU_RGBA_ADDRD(4) | ++ R500_ALU_RGBA_OP_MAD | ++ R500_ALU_RGBA_SEL_C_SRC2 | ++ R500_ALU_RGBA_R_SWIZ_R | ++ R500_ALU_RGBA_G_SWIZ_G | ++ R500_ALU_RGBA_B_SWIZ_B | ++ R500_ALU_RGBA_A_SWIZ_A)); ++ ++ /* ADD temp0, temp4, input0.xyxy */ ++ OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_INST_TYPE_ALU | ++ R500_INST_RGB_WMASK_R | ++ R500_INST_RGB_WMASK_G | ++ R500_INST_RGB_WMASK_B | ++ R500_INST_ALPHA_WMASK)); ++ OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_RGB_ADDR1(4) | ++ R500_RGB_ADDR2(0))); ++ OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_ALPHA_ADDR1(4) | ++ R500_ALPHA_ADDR2(0))); ++ OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_ALU_RGB_R_SWIZ_A_1 | ++ R500_ALU_RGB_G_SWIZ_A_1 | ++ R500_ALU_RGB_B_SWIZ_A_1 | ++ R500_ALU_RGB_SEL_B_SRC1 | ++ R500_ALU_RGB_R_SWIZ_B_R | ++ R500_ALU_RGB_G_SWIZ_B_G | ++ R500_ALU_RGB_B_SWIZ_B_B)); ++ OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_ALPHA_ADDRD(0) | ++ R500_ALPHA_OP_MAD | ++ R500_ALPHA_SWIZ_A_1 | ++ R500_ALPHA_SEL_B_SRC1 | ++ R500_ALPHA_SWIZ_B_A)); ++ OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_ALU_RGBA_ADDRD(0) | ++ R500_ALU_RGBA_OP_MAD | ++ R500_ALU_RGBA_SEL_C_SRC2 | ++ R500_ALU_RGBA_R_SWIZ_R | ++ R500_ALU_RGBA_G_SWIZ_G | ++ R500_ALU_RGBA_B_SWIZ_R | ++ R500_ALU_RGBA_A_SWIZ_G)); ++ ++ /* TEX temp4, temp0.zwzw, tex0, 1D */ ++ OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_INST_TYPE_TEX | ++ R500_INST_TEX_SEM_WAIT | ++ R500_INST_RGB_WMASK_R | ++ R500_INST_RGB_WMASK_G | ++ R500_INST_RGB_WMASK_B | ++ R500_INST_ALPHA_WMASK)); ++ OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_TEX_ID(0) | ++ R500_TEX_INST_LD | ++ R500_TEX_IGNORE_UNCOVERED)); ++ OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_TEX_SRC_ADDR(0) | ++ R500_TEX_SRC_S_SWIZ_B | ++ R500_TEX_SRC_T_SWIZ_A | ++ R500_TEX_SRC_R_SWIZ_B | ++ R500_TEX_SRC_Q_SWIZ_A | ++ R500_TEX_DST_ADDR(4) | ++ R500_TEX_DST_R_SWIZ_R | ++ R500_TEX_DST_G_SWIZ_G | ++ R500_TEX_DST_B_SWIZ_B | ++ R500_TEX_DST_A_SWIZ_A)); ++ OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, 0x00000000); ++ OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, 0x00000000); ++ OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, 0x00000000); ++ ++ /* TEX temp0, temp0.xyzw, tex0, 1D */ ++ OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_INST_TYPE_TEX | ++ R500_INST_TEX_SEM_WAIT | ++ R500_INST_RGB_WMASK_R | ++ R500_INST_RGB_WMASK_G | ++ R500_INST_RGB_WMASK_B | ++ R500_INST_ALPHA_WMASK)); ++ OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_TEX_ID(0) | ++ R500_TEX_INST_LD | ++ R500_TEX_SEM_ACQUIRE | ++ R500_TEX_IGNORE_UNCOVERED)); ++ OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_TEX_SRC_ADDR(0) | ++ R500_TEX_SRC_S_SWIZ_R | ++ R500_TEX_SRC_T_SWIZ_G | ++ R500_TEX_SRC_R_SWIZ_B | ++ R500_TEX_SRC_Q_SWIZ_A | ++ R500_TEX_DST_ADDR(0) | ++ R500_TEX_DST_R_SWIZ_R | ++ R500_TEX_DST_G_SWIZ_G | ++ R500_TEX_DST_B_SWIZ_B | ++ R500_TEX_DST_A_SWIZ_A)); ++ OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, 0x00000000); ++ OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, 0x00000000); ++ OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, 0x00000000); ++ ++ /* LRP temp3, temp2.zzzz, temp1, temp3 -> ++ * - PRESUB temps, temp1 - temp3 ++ * - MAD temp2.zzzz, temps, temp3 */ ++ OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_INST_TYPE_ALU | ++ R500_INST_RGB_WMASK_R | ++ R500_INST_RGB_WMASK_G | ++ R500_INST_RGB_WMASK_B | ++ R500_INST_ALPHA_WMASK)); ++ OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_RGB_ADDR0(3) | ++ R500_RGB_SRCP_OP_RGB1_MINUS_RGB0 | ++ R500_RGB_ADDR1(1) | ++ R500_RGB_ADDR2(2))); ++ OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_ALPHA_ADDR0(3) | ++ R500_ALPHA_SRCP_OP_A1_MINUS_A0 | ++ R500_ALPHA_ADDR1(1) | ++ R500_ALPHA_ADDR2(2))); ++ OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_ALU_RGB_SEL_A_SRC2 | ++ R500_ALU_RGB_R_SWIZ_A_B | ++ R500_ALU_RGB_G_SWIZ_A_B | ++ R500_ALU_RGB_B_SWIZ_A_B | ++ R500_ALU_RGB_SEL_B_SRCP | ++ R500_ALU_RGB_R_SWIZ_B_R | ++ R500_ALU_RGB_G_SWIZ_B_G | ++ R500_ALU_RGB_B_SWIZ_B_B)); ++ OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_ALPHA_ADDRD(3) | ++ R500_ALPHA_OP_MAD | ++ R500_ALPHA_SEL_A_SRC2 | ++ R500_ALPHA_SWIZ_A_B | ++ R500_ALPHA_SEL_B_SRCP | ++ R500_ALPHA_SWIZ_B_A)); ++ OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_ALU_RGBA_ADDRD(3) | ++ R500_ALU_RGBA_OP_MAD | ++ R500_ALU_RGBA_SEL_C_SRC0 | ++ R500_ALU_RGBA_R_SWIZ_R | ++ R500_ALU_RGBA_G_SWIZ_G | ++ R500_ALU_RGBA_B_SWIZ_B | ++ R500_ALU_RGBA_A_SWIZ_A)); ++ ++ /* LRP temp0, temp2.zzzz, temp4, temp0 -> ++ * - PRESUB temps, temp4 - temp1 ++ * - MAD temp2.zzzz, temps, temp0 */ ++ OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_INST_TYPE_ALU | ++ R500_INST_TEX_SEM_WAIT | ++ R500_INST_RGB_WMASK_R | ++ R500_INST_RGB_WMASK_G | ++ R500_INST_RGB_WMASK_B | ++ R500_INST_ALPHA_WMASK)); ++ OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_RGB_ADDR0(0) | ++ R500_RGB_SRCP_OP_RGB1_MINUS_RGB0 | ++ R500_RGB_ADDR1(4) | ++ R500_RGB_ADDR2(2))); ++ OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_ALPHA_ADDR0(0) | ++ R500_ALPHA_SRCP_OP_A1_MINUS_A0 | ++ R500_ALPHA_ADDR1(4) | ++ R500_ALPHA_ADDR2(2))); ++ OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_ALU_RGB_SEL_A_SRC2 | ++ R500_ALU_RGB_R_SWIZ_A_B | ++ R500_ALU_RGB_G_SWIZ_A_B | ++ R500_ALU_RGB_B_SWIZ_A_B | ++ R500_ALU_RGB_SEL_B_SRCP | ++ R500_ALU_RGB_R_SWIZ_B_R | ++ R500_ALU_RGB_G_SWIZ_B_G | ++ R500_ALU_RGB_B_SWIZ_B_B)); ++ OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_ALPHA_ADDRD(0) | ++ R500_ALPHA_OP_MAD | ++ R500_ALPHA_SEL_A_SRC2 | ++ R500_ALPHA_SWIZ_A_B | ++ R500_ALPHA_SEL_B_SRCP | ++ R500_ALPHA_SWIZ_B_A)); ++ OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_ALU_RGBA_ADDRD(0) | ++ R500_ALU_RGBA_OP_MAD | ++ R500_ALU_RGBA_SEL_C_SRC0 | ++ R500_ALU_RGBA_R_SWIZ_R | ++ R500_ALU_RGBA_G_SWIZ_G | ++ R500_ALU_RGBA_B_SWIZ_B | ++ R500_ALU_RGBA_A_SWIZ_A)); ++ ++ /* LRP output, temp5.zzzz, temp3, temp0 -> ++ * - PRESUB temps, temp3 - temp0 ++ * - MAD temp5.zzzz, temps, temp0 */ ++ OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_INST_TYPE_OUT | ++ R500_INST_LAST | ++ R500_INST_TEX_SEM_WAIT | ++ R500_INST_RGB_WMASK_R | ++ R500_INST_RGB_WMASK_G | ++ R500_INST_RGB_WMASK_B | ++ R500_INST_ALPHA_WMASK | ++ R500_INST_RGB_OMASK_R | ++ R500_INST_RGB_OMASK_G | ++ R500_INST_RGB_OMASK_B | ++ R500_INST_ALPHA_OMASK)); ++ OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_RGB_ADDR0(0) | ++ R500_RGB_SRCP_OP_RGB1_MINUS_RGB0 | ++ R500_RGB_ADDR1(3) | ++ R500_RGB_ADDR2(5))); ++ OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_ALPHA_ADDR0(0) | ++ R500_ALPHA_SRCP_OP_A1_MINUS_A0 | ++ R500_ALPHA_ADDR1(3) | ++ R500_ALPHA_ADDR2(5))); ++ OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_ALU_RGB_SEL_A_SRC2 | ++ R500_ALU_RGB_R_SWIZ_A_B | ++ R500_ALU_RGB_G_SWIZ_A_B | ++ R500_ALU_RGB_B_SWIZ_A_B | ++ R500_ALU_RGB_SEL_B_SRCP | ++ R500_ALU_RGB_R_SWIZ_B_R | ++ R500_ALU_RGB_G_SWIZ_B_G | ++ R500_ALU_RGB_B_SWIZ_B_B)); ++ OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_ALPHA_ADDRD(0) | ++ R500_ALPHA_OP_MAD | ++ R500_ALPHA_SEL_A_SRC2 | ++ R500_ALPHA_SWIZ_A_B | ++ R500_ALPHA_SEL_B_SRCP | ++ R500_ALPHA_SWIZ_B_A)); ++ OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_ALU_RGBA_ADDRD(0) | ++ R500_ALU_RGBA_OP_MAD | ++ R500_ALU_RGBA_SEL_C_SRC0 | ++ R500_ALU_RGBA_R_SWIZ_R | ++ R500_ALU_RGBA_G_SWIZ_G | ++ R500_ALU_RGBA_B_SWIZ_B | ++ R500_ALU_RGBA_A_SWIZ_A)); ++ ++ /* Shader constants. */ ++ OUT_VIDEO_REG(R500_GA_US_VECTOR_INDEX, R500_US_VECTOR_CONST_INDEX(0)); ++ ++ /* const0 = {1 / texture[0].width, 0, 0, 0} */ ++ OUT_VIDEO_REG_F(R500_GA_US_VECTOR_DATA, (1.0/(float)pPriv->w)); ++ OUT_VIDEO_REG_F(R500_GA_US_VECTOR_DATA, (1.0/(float)pPriv->h)); ++ OUT_VIDEO_REG_F(R500_GA_US_VECTOR_DATA, 0x0); ++ OUT_VIDEO_REG_F(R500_GA_US_VECTOR_DATA, 0x0); ++ ++ FINISH_VIDEO(); ++ ++ } else { ++ BEGIN_VIDEO(19); ++ /* 2 components: 2 for tex0 */ ++ OUT_VIDEO_REG(R300_RS_COUNT, ++ ((2 << R300_RS_COUNT_IT_COUNT_SHIFT) | ++ R300_RS_COUNT_HIRES_EN)); ++ ++ /* R300_INST_COUNT_RS - highest RS instruction used */ ++ OUT_VIDEO_REG(R300_RS_INST_COUNT, R300_INST_COUNT_RS(0) | R300_TX_OFFSET_RS(6)); ++ ++ /* Pixel stack frame size. */ ++ OUT_VIDEO_REG(R300_US_PIXSIZE, 0); /* highest temp used */ ++ ++ /* FP length. */ ++ OUT_VIDEO_REG(R500_US_CODE_ADDR, (R500_US_CODE_START_ADDR(0) | ++ R500_US_CODE_END_ADDR(1))); ++ OUT_VIDEO_REG(R500_US_CODE_RANGE, (R500_US_CODE_RANGE_ADDR(0) | ++ R500_US_CODE_RANGE_SIZE(1))); ++ ++ /* Prepare for FP emission. */ ++ OUT_VIDEO_REG(R500_US_CODE_OFFSET, 0); ++ OUT_VIDEO_REG(R500_GA_US_VECTOR_INDEX, R500_US_VECTOR_INST_INDEX(0)); ++ ++ /* tex inst */ ++ OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_INST_TYPE_TEX | ++ R500_INST_TEX_SEM_WAIT | ++ R500_INST_RGB_WMASK_R | ++ R500_INST_RGB_WMASK_G | ++ R500_INST_RGB_WMASK_B | ++ R500_INST_ALPHA_WMASK | ++ R500_INST_RGB_CLAMP | ++ R500_INST_ALPHA_CLAMP)); ++ OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_TEX_ID(0) | ++ R500_TEX_INST_LD | ++ R500_TEX_SEM_ACQUIRE | ++ R500_TEX_IGNORE_UNCOVERED)); ++ OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_TEX_SRC_ADDR(0) | ++ R500_TEX_SRC_S_SWIZ_R | ++ R500_TEX_SRC_T_SWIZ_G | ++ R500_TEX_DST_ADDR(0) | ++ R500_TEX_DST_R_SWIZ_R | ++ R500_TEX_DST_G_SWIZ_G | ++ R500_TEX_DST_B_SWIZ_B | ++ R500_TEX_DST_A_SWIZ_A)); ++ OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_DX_ADDR(0) | ++ R500_DX_S_SWIZ_R | ++ R500_DX_T_SWIZ_R | ++ R500_DX_R_SWIZ_R | ++ R500_DX_Q_SWIZ_R | ++ R500_DY_ADDR(0) | ++ R500_DY_S_SWIZ_R | ++ R500_DY_T_SWIZ_R | ++ R500_DY_R_SWIZ_R | ++ R500_DY_Q_SWIZ_R)); ++ OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, 0x00000000); ++ OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, 0x00000000); ++ ++ /* ALU inst */ ++ OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_INST_TYPE_OUT | ++ R500_INST_TEX_SEM_WAIT | ++ R500_INST_LAST | ++ R500_INST_RGB_OMASK_R | ++ R500_INST_RGB_OMASK_G | ++ R500_INST_RGB_OMASK_B | ++ R500_INST_ALPHA_OMASK | ++ R500_INST_RGB_CLAMP | ++ R500_INST_ALPHA_CLAMP)); ++ OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_RGB_ADDR0(0) | ++ R500_RGB_ADDR1(0) | ++ R500_RGB_ADDR1_CONST | ++ R500_RGB_ADDR2(0) | ++ R500_RGB_ADDR2_CONST)); ++ OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_ALPHA_ADDR0(0) | ++ R500_ALPHA_ADDR1(0) | ++ R500_ALPHA_ADDR1_CONST | ++ R500_ALPHA_ADDR2(0) | ++ R500_ALPHA_ADDR2_CONST)); ++ OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_ALU_RGB_SEL_A_SRC0 | ++ R500_ALU_RGB_R_SWIZ_A_R | ++ R500_ALU_RGB_G_SWIZ_A_G | ++ R500_ALU_RGB_B_SWIZ_A_B | ++ R500_ALU_RGB_SEL_B_SRC0 | ++ R500_ALU_RGB_R_SWIZ_B_1 | ++ R500_ALU_RGB_B_SWIZ_B_1 | ++ R500_ALU_RGB_G_SWIZ_B_1)); ++ OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_ALPHA_OP_MAD | ++ R500_ALPHA_SWIZ_A_A | ++ R500_ALPHA_SWIZ_B_1)); ++ OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_ALU_RGBA_OP_MAD | ++ R500_ALU_RGBA_R_SWIZ_0 | ++ R500_ALU_RGBA_G_SWIZ_0 | ++ R500_ALU_RGBA_B_SWIZ_0 | ++ R500_ALU_RGBA_A_SWIZ_0)); ++ FINISH_VIDEO(); ++ } + } + +- BEGIN_VIDEO(5); ++ BEGIN_VIDEO(6); + OUT_VIDEO_REG(R300_TX_INVALTAGS, 0); + OUT_VIDEO_REG(R300_TX_ENABLE, txenable); + +@@ -418,10 +990,8 @@ FUNC_NAME(RADEONDisplayTexturedVideo)(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv + blendcntl = RADEON_SRC_BLEND_GL_ONE | RADEON_DST_BLEND_GL_ZERO; + /* no need to enable blending */ + OUT_VIDEO_REG(R300_RB3D_BLENDCNTL, blendcntl); +- FINISH_VIDEO(); + +- BEGIN_VIDEO(1); +- OUT_VIDEO_REG(R300_VAP_VTX_SIZE, VTX_DWORD_COUNT); ++ OUT_VIDEO_REG(R300_VAP_VTX_SIZE, vtx_count); + FINISH_VIDEO(); + + } else { +@@ -456,15 +1026,15 @@ FUNC_NAME(RADEONDisplayTexturedVideo)(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv + BEGIN_VIDEO(5); + + OUT_VIDEO_REG(RADEON_PP_CNTL, +- RADEON_TEX_0_ENABLE | RADEON_TEX_BLEND_0_ENABLE); ++ RADEON_TEX_0_ENABLE | RADEON_TEX_BLEND_0_ENABLE); + OUT_VIDEO_REG(RADEON_RB3D_CNTL, +- dst_format | RADEON_ALPHA_BLEND_ENABLE); ++ dst_format | RADEON_ALPHA_BLEND_ENABLE); + OUT_VIDEO_REG(RADEON_RB3D_COLOROFFSET, dst_offset); + + OUT_VIDEO_REG(RADEON_RB3D_COLORPITCH, colorpitch); + + OUT_VIDEO_REG(RADEON_RB3D_BLENDCNTL, +- RADEON_SRC_BLEND_GL_ONE | RADEON_DST_BLEND_GL_ZERO); ++ RADEON_SRC_BLEND_GL_ONE | RADEON_DST_BLEND_GL_ZERO); + + FINISH_VIDEO(); + +@@ -481,35 +1051,37 @@ FUNC_NAME(RADEONDisplayTexturedVideo)(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv + + OUT_VIDEO_REG(R200_SE_VTX_FMT_0, R200_VTX_XY); + OUT_VIDEO_REG(R200_SE_VTX_FMT_1, +- (2 << R200_VTX_TEX0_COMP_CNT_SHIFT)); ++ (2 << R200_VTX_TEX0_COMP_CNT_SHIFT)); + OUT_VIDEO_REG(R200_PP_TXFILTER_0, - R200_MAG_FILTER_LINEAR | - R200_MIN_FILTER_LINEAR | -+ R200_CLAMP_S_CLAMP_LAST | -+ R200_CLAMP_T_CLAMP_LAST | - R200_YUV_TO_RGB); +- R200_MAG_FILTER_LINEAR | +- R200_MIN_FILTER_LINEAR | +- R200_YUV_TO_RGB); ++ R200_MAG_FILTER_LINEAR | ++ R200_MIN_FILTER_LINEAR | ++ R200_CLAMP_S_CLAMP_LAST | ++ R200_CLAMP_T_CLAMP_LAST | ++ R200_YUV_TO_RGB); OUT_VIDEO_REG(R200_PP_TXFORMAT_0, txformat); OUT_VIDEO_REG(R200_PP_TXFORMAT_X_0, 0); -@@ -521,8 +523,11 @@ FUNC_NAME(RADEONDisplayTexturedVideo)(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv - OUT_VIDEO_REG(RADEON_SE_VTX_FMT, RADEON_SE_VTX_FMT_XY | - RADEON_SE_VTX_FMT_ST0); + OUT_VIDEO_REG(R200_PP_TXSIZE_0, +- (pPriv->w - 1) | +- ((pPriv->h - 1) << RADEON_TEX_VSIZE_SHIFT)); ++ (pPriv->w - 1) | ++ ((pPriv->h - 1) << RADEON_TEX_VSIZE_SHIFT)); + OUT_VIDEO_REG(R200_PP_TXPITCH_0, pPriv->src_pitch - 32); + + OUT_VIDEO_REG(R200_PP_TXOFFSET_0, pPriv->src_offset); + + OUT_VIDEO_REG(R200_PP_TXCBLEND_0, +- R200_TXC_ARG_A_ZERO | +- R200_TXC_ARG_B_ZERO | +- R200_TXC_ARG_C_R0_COLOR | +- R200_TXC_OP_MADD); ++ R200_TXC_ARG_A_ZERO | ++ R200_TXC_ARG_B_ZERO | ++ R200_TXC_ARG_C_R0_COLOR | ++ R200_TXC_OP_MADD); + OUT_VIDEO_REG(R200_PP_TXCBLEND2_0, +- R200_TXC_CLAMP_0_1 | R200_TXC_OUTPUT_REG_R0); ++ R200_TXC_CLAMP_0_1 | R200_TXC_OUTPUT_REG_R0); + OUT_VIDEO_REG(R200_PP_TXABLEND_0, +- R200_TXA_ARG_A_ZERO | +- R200_TXA_ARG_B_ZERO | +- R200_TXA_ARG_C_R0_ALPHA | +- R200_TXA_OP_MADD); ++ R200_TXA_ARG_A_ZERO | ++ R200_TXA_ARG_B_ZERO | ++ R200_TXA_ARG_C_R0_ALPHA | ++ R200_TXA_OP_MADD); + OUT_VIDEO_REG(R200_PP_TXABLEND2_0, +- R200_TXA_CLAMP_0_1 | R200_TXA_OUTPUT_REG_R0); ++ R200_TXA_CLAMP_0_1 | R200_TXA_OUTPUT_REG_R0); + FINISH_VIDEO(); + } else { + +@@ -518,32 +1090,35 @@ FUNC_NAME(RADEONDisplayTexturedVideo)(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv + + BEGIN_VIDEO(8); + +- OUT_VIDEO_REG(RADEON_SE_VTX_FMT, RADEON_SE_VTX_FMT_XY | +- RADEON_SE_VTX_FMT_ST0); ++ OUT_VIDEO_REG(RADEON_SE_VTX_FMT, (RADEON_SE_VTX_FMT_XY | ++ RADEON_SE_VTX_FMT_ST0)); - OUT_VIDEO_REG(RADEON_PP_TXFILTER_0, RADEON_MAG_FILTER_LINEAR | +- RADEON_MIN_FILTER_LINEAR | +- RADEON_YUV_TO_RGB); + OUT_VIDEO_REG(RADEON_PP_TXFILTER_0, -+ RADEON_MAG_FILTER_LINEAR | - RADEON_MIN_FILTER_LINEAR | -+ RADEON_CLAMP_S_CLAMP_LAST | -+ RADEON_CLAMP_T_CLAMP_LAST | - RADEON_YUV_TO_RGB); ++ RADEON_MAG_FILTER_LINEAR | ++ RADEON_MIN_FILTER_LINEAR | ++ RADEON_CLAMP_S_CLAMP_LAST | ++ RADEON_CLAMP_T_CLAMP_LAST | ++ RADEON_YUV_TO_RGB); OUT_VIDEO_REG(RADEON_PP_TXFORMAT_0, txformat); OUT_VIDEO_REG(RADEON_PP_TXOFFSET_0, pPriv->src_offset); -@@ -582,16 +587,16 @@ FUNC_NAME(RADEONDisplayTexturedVideo)(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv + OUT_VIDEO_REG(RADEON_PP_TXCBLEND_0, +- RADEON_COLOR_ARG_A_ZERO | +- RADEON_COLOR_ARG_B_ZERO | +- RADEON_COLOR_ARG_C_T0_COLOR | +- RADEON_BLEND_CTL_ADD | +- RADEON_CLAMP_TX); ++ RADEON_COLOR_ARG_A_ZERO | ++ RADEON_COLOR_ARG_B_ZERO | ++ RADEON_COLOR_ARG_C_T0_COLOR | ++ RADEON_BLEND_CTL_ADD | ++ RADEON_CLAMP_TX); + OUT_VIDEO_REG(RADEON_PP_TXABLEND_0, +- RADEON_ALPHA_ARG_A_ZERO | +- RADEON_ALPHA_ARG_B_ZERO | +- RADEON_ALPHA_ARG_C_T0_ALPHA | +- RADEON_BLEND_CTL_ADD | +- RADEON_CLAMP_TX); ++ RADEON_ALPHA_ARG_A_ZERO | ++ RADEON_ALPHA_ARG_B_ZERO | ++ RADEON_ALPHA_ARG_C_T0_ALPHA | ++ RADEON_BLEND_CTL_ADD | ++ RADEON_CLAMP_TX); + + OUT_VIDEO_REG(RADEON_PP_TEX_SIZE_0, +- (pPriv->w - 1) | +- ((pPriv->h - 1) << RADEON_TEX_VSIZE_SHIFT)); ++ (pPriv->w - 1) | ++ ((pPriv->h - 1) << RADEON_TEX_VSIZE_SHIFT)); + OUT_VIDEO_REG(RADEON_PP_TEX_PITCH_0, +- pPriv->src_pitch - 32); ++ pPriv->src_pitch - 32); + FINISH_VIDEO(); + } + } +@@ -582,53 +1157,71 @@ FUNC_NAME(RADEONDisplayTexturedVideo)(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv #ifdef ACCEL_CP if (info->ChipFamily < CHIP_FAMILY_R200) { - BEGIN_RING(4 * VTX_DWORD_COUNT + 3); -+ BEGIN_RING(3 * VTX_DWORD_COUNT + 3); ++ BEGIN_RING(3 * vtx_count + 3); OUT_RING(CP_PACKET3(RADEON_CP_PACKET3_3D_DRAW_IMMD, - 4 * VTX_DWORD_COUNT + 1)); -+ 3 * VTX_DWORD_COUNT + 1)); ++ 3 * vtx_count + 1)); OUT_RING(RADEON_CP_VC_FRMT_XY | RADEON_CP_VC_FRMT_ST0); - OUT_RING(RADEON_CP_VC_CNTL_PRIM_TYPE_TRI_FAN | @@ -4005,48 +6198,86 @@ index 277d9b2..d39f74d 100644 + (3 << RADEON_CP_VC_CNTL_NUM_SHIFT)); } else { if (IS_R300_3D || IS_R500_3D) - BEGIN_RING(4 * VTX_DWORD_COUNT + 4); -@@ -599,30 +604,33 @@ FUNC_NAME(RADEONDisplayTexturedVideo)(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv - BEGIN_RING(4 * VTX_DWORD_COUNT + 2); +- BEGIN_RING(4 * VTX_DWORD_COUNT + 4); ++ BEGIN_RING(4 * vtx_count + 4); + else +- BEGIN_RING(4 * VTX_DWORD_COUNT + 2); ++ BEGIN_RING(4 * vtx_count + 2); OUT_RING(CP_PACKET3(R200_CP_PACKET3_3D_DRAW_IMMD_2, - 4 * VTX_DWORD_COUNT)); +- 4 * VTX_DWORD_COUNT)); - OUT_RING(RADEON_CP_VC_CNTL_PRIM_TYPE_TRI_FAN | ++ 4 * vtx_count)); + OUT_RING(RADEON_CP_VC_CNTL_PRIM_TYPE_QUAD_LIST | RADEON_CP_VC_CNTL_PRIM_WALK_RING | (4 << RADEON_CP_VC_CNTL_NUM_SHIFT)); } #else /* ACCEL_CP */ if (IS_R300_3D || IS_R500_3D) - BEGIN_VIDEO(2 + VTX_DWORD_COUNT * 4); +- BEGIN_VIDEO(2 + VTX_DWORD_COUNT * 4); ++ BEGIN_VIDEO(2 + vtx_count * 4); + else if (info->ChipFamily < CHIP_FAMILY_R200) -+ BEGIN_VIDEO(1 + VTX_DWORD_COUNT * 3); ++ BEGIN_VIDEO(1 + vtx_count * 3); else - BEGIN_VIDEO(1 + VTX_DWORD_COUNT * 4); +- BEGIN_VIDEO(1 + VTX_DWORD_COUNT * 4); ++ BEGIN_VIDEO(1 + vtx_count * 4); - if (info->ChipFamily < CHIP_FAMILY_R200) { +- if (info->ChipFamily < CHIP_FAMILY_R200) { - OUT_VIDEO_REG(RADEON_SE_VF_CNTL, (RADEON_VF_PRIM_TYPE_TRIANGLE_FAN | ++ if (info->ChipFamily < CHIP_FAMILY_R200) + OUT_VIDEO_REG(RADEON_SE_VF_CNTL, (RADEON_VF_PRIM_TYPE_RECTANGLE_LIST | RADEON_VF_PRIM_WALK_DATA | RADEON_VF_RADEON_MODE | - 4 << RADEON_VF_NUM_VERTICES_SHIFT)); +- } else { + (3 << RADEON_VF_NUM_VERTICES_SHIFT))); - } else { ++ else OUT_VIDEO_REG(RADEON_SE_VF_CNTL, (RADEON_VF_PRIM_TYPE_QUAD_LIST | RADEON_VF_PRIM_WALK_DATA | - 4 << RADEON_VF_NUM_VERTICES_SHIFT)); +- } +-#endif + (4 << RADEON_VF_NUM_VERTICES_SHIFT))); - } - #endif -- + - VTX_OUT((float)dstX, (float)dstY, - xFixedToFloat(srcTopLeft.x) / info->texW[0], xFixedToFloat(srcTopLeft.y) / info->texH[0]); -+ if (info->ChipFamily >= CHIP_FAMILY_R200) { -+ VTX_OUT((float)dstX, (float)dstY, -+ xFixedToFloat(srcTopLeft.x) / info->texW[0], xFixedToFloat(srcTopLeft.y) / info->texH[0]); -+ } - VTX_OUT((float)dstX, (float)(dstY + dsth), +- VTX_OUT((float)dstX, (float)(dstY + dsth), ++#endif ++ if (pPriv->bicubic_enabled) { ++ VTX_OUT_FILTER((float)dstX, (float)dstY, ++ xFixedToFloat(srcTopLeft.x) / info->texW[0], xFixedToFloat(srcTopLeft.y) / info->texH[0], ++ xFixedToFloat(srcTopLeft.x) + 0.5, xFixedToFloat(srcTopLeft.y) + 0.5); ++ VTX_OUT_FILTER((float)dstX, (float)(dstY + dsth), ++ xFixedToFloat(srcBottomLeft.x) / info->texW[0], xFixedToFloat(srcBottomLeft.y) / info->texH[0], ++ xFixedToFloat(srcBottomLeft.x) + 0.5, xFixedToFloat(srcBottomLeft.y) + 0.5); ++ VTX_OUT_FILTER((float)(dstX + dstw), (float)(dstY + dsth), ++ xFixedToFloat(srcBottomRight.x) / info->texW[0], xFixedToFloat(srcBottomRight.y) / info->texH[0], ++ xFixedToFloat(srcBottomRight.x) + 0.5, xFixedToFloat(srcBottomRight.y) + 0.5); ++ VTX_OUT_FILTER((float)(dstX + dstw), (float)dstY, ++ xFixedToFloat(srcTopRight.x) / info->texW[0], xFixedToFloat(srcTopRight.y) / info->texH[0], ++ xFixedToFloat(srcTopRight.x) + 0.5, xFixedToFloat(srcTopRight.y) + 0.5); ++ } else { ++ if (info->ChipFamily >= CHIP_FAMILY_R200) { ++ VTX_OUT((float)dstX, (float)dstY, ++ xFixedToFloat(srcTopLeft.x) / info->texW[0], xFixedToFloat(srcTopLeft.y) / info->texH[0]); ++ } ++ VTX_OUT((float)dstX, (float)(dstY + dsth), xFixedToFloat(srcBottomLeft.x) / info->texW[0], xFixedToFloat(srcBottomLeft.y) / info->texH[0]); - VTX_OUT((float)(dstX + dstw), (float)(dstY + dsth), +- VTX_OUT((float)(dstX + dstw), (float)(dstY + dsth), ++ VTX_OUT((float)(dstX + dstw), (float)(dstY + dsth), + xFixedToFloat(srcBottomRight.x) / info->texW[0], xFixedToFloat(srcBottomRight.y) / info->texH[0]); +- VTX_OUT((float)(dstX + dstw), (float)dstY, ++ VTX_OUT((float)(dstX + dstw), (float)dstY, + xFixedToFloat(srcTopRight.x) / info->texW[0], xFixedToFloat(srcTopRight.y) / info->texH[0]); ++ } + + if (IS_R300_3D || IS_R500_3D) + /* flushing is pipelined, free/finish is not */ +@@ -655,4 +1248,5 @@ FUNC_NAME(RADEONDisplayTexturedVideo)(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv + } + + #undef VTX_OUT ++#undef VTX_OUT_FILTER + #undef FUNC_NAME diff --git a/src/radeon_tv.c b/src/radeon_tv.c index 90020b3..90d1ac9 100644 --- a/src/radeon_tv.c @@ -4395,10 +6626,69 @@ index ccc1367..5717ead 100644 #ifndef RADEON_VERSION_EXTRA #define RADEON_VERSION_EXTRA "" diff --git a/src/radeon_video.c b/src/radeon_video.c -index ac60166..57dcd8a 100644 +index ac60166..e71f0f8 100644 --- a/src/radeon_video.c +++ b/src/radeon_video.c -@@ -2586,6 +2586,7 @@ RADEONDisplayVideo( +@@ -89,10 +89,6 @@ static void RADEON_MSP_SetEncoding(RADEONPortPrivPtr pPriv); + static void RADEON_TDA9885_SetEncoding(RADEONPortPrivPtr pPriv); + static void RADEON_FI1236_SetEncoding(RADEONPortPrivPtr pPriv); + +- +- +-#define ClipValue(v,min,max) ((v) < (min) ? (min) : (v) > (max) ? (max) : (v)) +- + static Atom xvBrightness, xvColorKey, xvSaturation, xvDoubleBuffer; + static Atom xvRedIntensity, xvGreenIntensity, xvBlueIntensity; + static Atom xvContrast, xvHue, xvColor, xvAutopaintColorkey, xvSetDefaults; +@@ -106,7 +102,6 @@ static Atom xvEncoding, xvFrequency, xvVolume, xvMute, + + static Atom xvOvAlpha, xvGrAlpha, xvAlphaMode; + +- + #define GET_PORT_PRIVATE(pScrn) \ + (RADEONPortPrivPtr)((RADEONPTR(pScrn))->adaptor->pPortPrivates[0].ptr) + +@@ -1678,6 +1673,10 @@ RADEONStopVideo(ScrnInfoPtr pScrn, pointer data, Bool cleanup) + RADEONFreeMemory(pScrn, pPriv->video_memory); + pPriv->video_memory = NULL; + } ++ if (pPriv->bicubic_memory != NULL) { ++ RADEONFreeMemory(pScrn, pPriv->bicubic_memory); ++ pPriv->bicubic_memory = NULL; ++ } + pPriv->videoStatus = 0; + } else { + if(pPriv->videoStatus & CLIENT_VIDEO_ON) { +@@ -1699,9 +1698,6 @@ RADEONSetPortAttribute(ScrnInfoPtr pScrn, + Bool setAlpha = FALSE; + unsigned char *RADEONMMIO = info->MMIO; + +- if (pPriv->textured) +- return BadMatch; +- + RADEON_SYNC(info, pScrn); + + #define RTFSaturation(a) (1.0 + ((a)*1.0)/1000.0) +@@ -1928,7 +1924,7 @@ RADEONSetPortAttribute(ScrnInfoPtr pScrn, + if(pPriv->fi1236!=NULL){ + xf86_fi1236_dump_status(pPriv->fi1236); + } +- } ++ } + else if(attribute == xvAdjustment) + { + pPriv->adjustment=value; +@@ -1973,9 +1969,6 @@ RADEONGetPortAttribute(ScrnInfoPtr pScrn, + RADEONInfoPtr info = RADEONPTR(pScrn); + RADEONPortPrivPtr pPriv = (RADEONPortPrivPtr)data; + +- if (pPriv->textured) +- return BadMatch; +- + if (info->accelOn) RADEON_SYNC(info, pScrn); + + if(attribute == xvAutopaintColorkey) +@@ -2586,6 +2579,7 @@ RADEONDisplayVideo( RADEONOutputPrivatePtr radeon_output; xf86OutputPtr output; RADEONCrtcPrivatePtr radeon_crtc = crtc->driver_private; @@ -4406,7 +6696,7 @@ index ac60166..57dcd8a 100644 is_rgb=0; is_planar=0; switch(id){ -@@ -2715,6 +2716,22 @@ RADEONDisplayVideo( +@@ -2715,6 +2709,22 @@ RADEONDisplayVideo( } #endif @@ -4429,7 +6719,7 @@ index ac60166..57dcd8a 100644 /* keep everything in 16.16 */ if (is_planar) { -@@ -2846,6 +2863,10 @@ RADEONDisplayVideo( +@@ -2846,6 +2856,10 @@ RADEONDisplayVideo( src_w >>= 1; OUTREG(RADEON_OV0_P2_X_START_END, (src_w + leftuv - 1) | (leftuv << 16)); OUTREG(RADEON_OV0_P3_X_START_END, (src_w + leftuv - 1) | (leftuv << 16)); @@ -4440,3 +6730,77 @@ index ac60166..57dcd8a 100644 OUTREG(RADEON_OV0_VID_BUF0_BASE_ADRS, offset1); OUTREG(RADEON_OV0_VID_BUF1_BASE_ADRS, offset2); OUTREG(RADEON_OV0_VID_BUF2_BASE_ADRS, offset3); +@@ -3236,6 +3250,10 @@ RADEONVideoTimerCallback(ScrnInfoPtr pScrn, Time now) + RADEONFreeMemory(pScrn, pPriv->video_memory); + pPriv->video_memory = NULL; + } ++ if (pPriv->bicubic_memory != NULL) { ++ RADEONFreeMemory(pScrn, pPriv->bicubic_memory); ++ pPriv->bicubic_memory = NULL; ++ } + pPriv->videoStatus = 0; + info->VideoTimerCallback = NULL; + } +diff --git a/src/radeon_video.h b/src/radeon_video.h +index 096de37..b9d900d 100644 +--- a/src/radeon_video.h ++++ b/src/radeon_video.h +@@ -13,6 +13,10 @@ + + #include "xf86Crtc.h" + ++#include "bicubic_table.h" ++ ++#define ClipValue(v,min,max) ((v) < (min) ? (min) : (v) > (max) ? (max) : (v)) ++ + /* Xvideo port struct */ + typedef struct { + uint32_t transform_index; +@@ -37,7 +41,7 @@ typedef struct { + uint32_t radeon_N; + uint32_t i2c_status; + uint32_t i2c_cntl; +- ++ + FI1236Ptr fi1236; + uint8_t tuner_type; + MSP3430Ptr msp3430; +@@ -46,7 +50,7 @@ typedef struct { + + /* VIP bus and devices */ + GENERIC_BUS_Ptr VIP; +- TheatrePtr theatre; ++ TheatrePtr theatre; + + Bool video_stream_active; + int encoding; +@@ -56,7 +60,7 @@ typedef struct { + int sap_channel; + int v; + uint32_t adjustment; /* general purpose variable */ +- ++ + #define METHOD_BOB 0 + #define METHOD_SINGLE 1 + #define METHOD_WEAVE 2 +@@ -89,6 +93,12 @@ typedef struct { + void *video_memory; + int video_offset; + ++ /* bicubic filtering */ ++ void *bicubic_memory; ++ int bicubic_offset; ++ Bool bicubic_enabled; ++ uint32_t bicubic_src_offset; ++ + Atom device_id, location_id, instance_id; + + /* textured video */ +@@ -106,7 +116,6 @@ typedef struct { + int drw_x, drw_y; + } RADEONPortPrivRec, *RADEONPortPrivPtr; + +- + void RADEONInitI2C(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv); + void RADEONResetI2C(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv); + diff --git a/radeon-fix-pipe-config.patch b/radeon-fix-pipe-config.patch deleted file mode 100644 index 273e5c0..0000000 --- a/radeon-fix-pipe-config.patch +++ /dev/null @@ -1,41 +0,0 @@ -diff --git a/src/radeon_accel.c b/src/radeon_accel.c -index 30a5756..ef8b4a5 100644 ---- a/src/radeon_accel.c -+++ b/src/radeon_accel.c -@@ -440,7 +440,8 @@ void RADEONEngineInit(ScrnInfoPtr pScrn) - - OUTREG(R300_GB_TILE_CONFIG, gb_tile_config); - OUTREG(RADEON_WAIT_UNTIL, RADEON_WAIT_2D_IDLECLEAN | RADEON_WAIT_3D_IDLECLEAN); -- OUTREG(R300_DST_PIPE_CONFIG, INREG(R300_DST_PIPE_CONFIG) | R300_PIPE_AUTO_CONFIG); -+ if (info->ChipFamily >= CHIP_FAMILY_R420) -+ OUTREG(R300_DST_PIPE_CONFIG, INREG(R300_DST_PIPE_CONFIG) | R300_PIPE_AUTO_CONFIG); - OUTREG(R300_RB2D_DSTCACHE_MODE, (INREG(R300_RB2D_DSTCACHE_MODE) | - R300_DC_AUTOFLUSH_ENABLE | - R300_DC_DC_DISABLE_IGNORE_PE)); -diff --git a/src/radeon_commonfuncs.c b/src/radeon_commonfuncs.c -index 15a3beb..aab42d0 100644 ---- a/src/radeon_commonfuncs.c -+++ b/src/radeon_commonfuncs.c -@@ -61,6 +61,7 @@ static void FUNC_NAME(RADEONInit3DEngine)(ScrnInfoPtr pScrn) - info->texW[0] = info->texH[0] = info->texW[1] = info->texH[1] = 1; - - if (IS_R300_3D || IS_R500_3D) { -+ int size; - - if (!info->new_cs) { - BEGIN_ACCEL(3); -@@ -80,10 +81,12 @@ static void FUNC_NAME(RADEONInit3DEngine)(ScrnInfoPtr pScrn) - case 1: gb_tile_config |= R300_PIPE_COUNT_RV350; break; - } - -- BEGIN_ACCEL(5); -+ size = (info->ChipFamily >= CHIP_FAMILY_R420) ? 5 : 4; -+ BEGIN_ACCEL(size); - OUT_ACCEL_REG(R300_GB_TILE_CONFIG, gb_tile_config); - OUT_ACCEL_REG(RADEON_WAIT_UNTIL, RADEON_WAIT_2D_IDLECLEAN | RADEON_WAIT_3D_IDLECLEAN); -- OUT_ACCEL_REG(R300_DST_PIPE_CONFIG, R300_PIPE_AUTO_CONFIG); -+ if (info->ChipFamily >= CHIP_FAMILY_R420) -+ OUT_ACCEL_REG(R300_DST_PIPE_CONFIG, R300_PIPE_AUTO_CONFIG); - OUT_ACCEL_REG(R300_GB_SELECT, 0); - OUT_ACCEL_REG(R300_GB_ENABLE, 0); - FINISH_ACCEL(); diff --git a/radeon-modeset.patch b/radeon-modeset.patch index e1ad8d2..3b5dac8 100644 --- a/radeon-modeset.patch +++ b/radeon-modeset.patch @@ -2,7 +2,7 @@ diff --git a/configure.ac b/configure.ac index b8c18a6..a7e954d 100644 --- a/configure.ac +++ b/configure.ac -@@ -115,6 +115,15 @@ if test "$DRI" = yes; then +@@ -115,6 +115,14 @@ if test "$DRI" = yes; then if test "$have_damage_h" = yes; then AC_DEFINE(DAMAGE,1,[Use Damage extension]) fi @@ -14,7 +14,6 @@ index b8c18a6..a7e954d 100644 + if test "x$DRM_MODE" = xyes; then + AC_DEFINE(XF86DRM_MODE,1,[DRM kernel modesetting]) + fi -+ CFLAGS="$save_CFLAGS" fi save_CFLAGS="$CFLAGS" @@ -47,10 +46,10 @@ index 97c686b..d32e74a 100644 + drmmode_display.h diff --git a/src/drmmode_display.c b/src/drmmode_display.c new file mode 100644 -index 0000000..97762ce +index 0000000..25e6183 --- /dev/null +++ b/src/drmmode_display.c -@@ -0,0 +1,681 @@ +@@ -0,0 +1,685 @@ +/* + * Copyright © 2007 Red Hat, Inc. + * @@ -100,7 +99,7 @@ index 0000000..97762ce + ret = drmmode_resize_fb(scrn, drmmode, width, height); + scrn->virtualX = width; + scrn->virtualY = height; -+ return ret; ++ return TRUE; +} + +static void @@ -184,7 +183,7 @@ index 0000000..97762ce + DisplayModeRec saved_mode; + uint32_t *output_ids; + int output_count = 0; -+ int ret = TRUE; ++ Bool ret = TRUE; + int i; + int fb_id; + struct drm_mode_modeinfo kmode; @@ -231,6 +230,9 @@ index 0000000..97762ce + drmModeSetCrtc(drmmode->fd, drmmode_crtc->mode_crtc->crtc_id, + fb_id, x, y, output_ids, output_count, &kmode); + ++ if (crtc->scrn->pScreen) ++ xf86CrtcSetScreenSubpixelOrder(crtc->scrn->pScreen); ++ + +done: + if (!ret) { @@ -583,6 +585,7 @@ index 0000000..97762ce + + output->possible_crtcs = kencoder->possible_crtcs; + output->possible_clones = kencoder->possible_clones; ++ + return; +} + @@ -1029,7 +1032,7 @@ index 2348e7c..32bfa4e 100644 do { \ if (RADEON_VERBOSE) \ diff --git a/src/radeon_accel.c b/src/radeon_accel.c -index e617fd5..09aa7f6 100644 +index e617fd5..dfb88a6 100644 --- a/src/radeon_accel.c +++ b/src/radeon_accel.c @@ -313,6 +313,9 @@ void RADEONEngineRestore(ScrnInfoPtr pScrn) @@ -1051,7 +1054,7 @@ index e617fd5..09aa7f6 100644 drmRadeonGetParam np; int num_pipes; -@@ -391,60 +394,62 @@ void RADEONEngineInit(ScrnInfoPtr pScrn) +@@ -391,60 +394,63 @@ void RADEONEngineInit(ScrnInfoPtr pScrn) } #endif @@ -1125,7 +1128,8 @@ index e617fd5..09aa7f6 100644 + + OUTREG(R300_GB_TILE_CONFIG, gb_tile_config); + OUTREG(RADEON_WAIT_UNTIL, RADEON_WAIT_2D_IDLECLEAN | RADEON_WAIT_3D_IDLECLEAN); -+ OUTREG(R300_DST_PIPE_CONFIG, INREG(R300_DST_PIPE_CONFIG) | R300_PIPE_AUTO_CONFIG); ++ if (info->ChipFamily >= CHIP_FAMILY_R420) ++ OUTREG(R300_DST_PIPE_CONFIG, INREG(R300_DST_PIPE_CONFIG) | R300_PIPE_AUTO_CONFIG); + OUTREG(R300_RB2D_DSTCACHE_MODE, (INREG(R300_RB2D_DSTCACHE_MODE) | + R300_DC_AUTOFLUSH_ENABLE | + R300_DC_DC_DISABLE_IGNORE_PE)); @@ -1164,7 +1168,7 @@ index e617fd5..09aa7f6 100644 switch (info->CurrentLayout.pixel_code) { case 8: info->datatype = 2; break; case 15: info->datatype = 3; break; -@@ -556,6 +561,149 @@ int RADEONCPStop(ScrnInfoPtr pScrn, RADEONInfoPtr info) +@@ -556,6 +562,149 @@ int RADEONCPStop(ScrnInfoPtr pScrn, RADEONInfoPtr info) } } @@ -1314,7 +1318,7 @@ index e617fd5..09aa7f6 100644 /* Get an indirect buffer for the CP 2D acceleration commands */ drmBufPtr RADEONCPGetBuffer(ScrnInfoPtr pScrn) { -@@ -566,6 +714,9 @@ drmBufPtr RADEONCPGetBuffer(ScrnInfoPtr pScrn) +@@ -566,6 +715,9 @@ drmBufPtr RADEONCPGetBuffer(ScrnInfoPtr pScrn) int size = 0; int i = 0; int ret; @@ -1324,7 +1328,7 @@ index e617fd5..09aa7f6 100644 #if 0 /* FIXME: pScrn->pScreen has not been initialized when this is first -@@ -631,6 +782,11 @@ void RADEONCPFlushIndirect(ScrnInfoPtr pScrn, int discard) +@@ -631,6 +783,11 @@ void RADEONCPFlushIndirect(ScrnInfoPtr pScrn, int discard) if (!buffer) return; if (start == buffer->used && !discard) return; @@ -1336,7 +1340,7 @@ index e617fd5..09aa7f6 100644 if (RADEON_VERBOSE) { xf86DrvMsg(pScrn->scrnIndex, X_INFO, "Flushing buffer %d\n", buffer->idx); -@@ -665,10 +821,17 @@ void RADEONCPReleaseIndirect(ScrnInfoPtr pScrn) +@@ -665,10 +822,17 @@ void RADEONCPReleaseIndirect(ScrnInfoPtr pScrn) int start = info->indirectStart; drmRadeonIndirect indirect; @@ -1354,7 +1358,7 @@ index e617fd5..09aa7f6 100644 if (RADEON_VERBOSE) { xf86DrvMsg(pScrn->scrnIndex, X_INFO, "Releasing buffer %d\n", -@@ -795,6 +958,7 @@ RADEONHostDataBlit( +@@ -795,6 +959,7 @@ RADEONHostDataBlit( ret = ( uint8_t* )&__head[__count]; __count += dwords; @@ -1362,7 +1366,7 @@ index e617fd5..09aa7f6 100644 ADVANCE_RING(); *y += *hpass; -@@ -932,7 +1096,7 @@ Bool RADEONAccelInit(ScreenPtr pScreen) +@@ -932,7 +1097,7 @@ Bool RADEONAccelInit(ScreenPtr pScreen) #ifdef USE_EXA if (info->useEXA) { # ifdef XF86DRI @@ -1371,7 +1375,7 @@ index e617fd5..09aa7f6 100644 if (!RADEONDrawInitCP(pScreen)) return FALSE; } else -@@ -953,7 +1117,7 @@ Bool RADEONAccelInit(ScreenPtr pScreen) +@@ -953,7 +1118,7 @@ Bool RADEONAccelInit(ScreenPtr pScreen) } #ifdef XF86DRI @@ -1380,7 +1384,7 @@ index e617fd5..09aa7f6 100644 RADEONAccelInitCP(pScreen, a); else #endif /* XF86DRI */ -@@ -975,11 +1139,13 @@ void RADEONInit3DEngine(ScrnInfoPtr pScrn) +@@ -975,11 +1140,13 @@ void RADEONInit3DEngine(ScrnInfoPtr pScrn) RADEONInfoPtr info = RADEONPTR (pScrn); #ifdef XF86DRI @@ -2370,12 +2374,14 @@ index 193c1f9..c3b7e3b 100644 +typedef drm_radeon_setparam_t drmRadeonSetParam; +#endif diff --git a/src/radeon_commonfuncs.c b/src/radeon_commonfuncs.c -index d0c5229..15a3beb 100644 +index 1de6bf8..6ead191 100644 --- a/src/radeon_commonfuncs.c +++ b/src/radeon_commonfuncs.c -@@ -62,11 +62,13 @@ static void FUNC_NAME(RADEONInit3DEngine)(ScrnInfoPtr pScrn) +@@ -61,12 +61,15 @@ static void FUNC_NAME(RADEONInit3DEngine)(ScrnInfoPtr pScrn) + info->texW[0] = info->texH[0] = info->texW[1] = info->texH[1] = 1; if (IS_R300_3D || IS_R500_3D) { ++ int size; - BEGIN_ACCEL(3); - OUT_ACCEL_REG(R300_RB3D_DSTCACHE_CTLSTAT, R300_DC_FLUSH_3D | R300_DC_FREE_3D); @@ -2392,7 +2398,22 @@ index d0c5229..15a3beb 100644 gb_tile_config = (R300_ENABLE_TILING | R300_TILE_SIZE_16 | R300_SUBPIXEL_1_16); -@@ -688,7 +690,7 @@ void FUNC_NAME(RADEONWaitForIdle)(ScrnInfoPtr pScrn) +@@ -78,10 +81,12 @@ static void FUNC_NAME(RADEONInit3DEngine)(ScrnInfoPtr pScrn) + case 1: gb_tile_config |= R300_PIPE_COUNT_RV350; break; + } + +- BEGIN_ACCEL(5); ++ size = (info->ChipFamily >= CHIP_FAMILY_R420) ? 5 : 4; ++ BEGIN_ACCEL(size); + OUT_ACCEL_REG(R300_GB_TILE_CONFIG, gb_tile_config); + OUT_ACCEL_REG(RADEON_WAIT_UNTIL, RADEON_WAIT_2D_IDLECLEAN | RADEON_WAIT_3D_IDLECLEAN); +- OUT_ACCEL_REG(R300_DST_PIPE_CONFIG, R300_PIPE_AUTO_CONFIG); ++ if (info->ChipFamily >= CHIP_FAMILY_R420) ++ OUT_ACCEL_REG(R300_DST_PIPE_CONFIG, R300_PIPE_AUTO_CONFIG); + OUT_ACCEL_REG(R300_GB_SELECT, 0); + OUT_ACCEL_REG(R300_GB_ENABLE, 0); + FINISH_ACCEL(); +@@ -686,7 +691,7 @@ void FUNC_NAME(RADEONWaitForIdle)(ScrnInfoPtr pScrn) #ifdef ACCEL_CP /* Make sure the CP is idle first */ @@ -2490,7 +2511,7 @@ index 13c2b9c..1e1835a 100644 FBAreaPtr fbarea; diff --git a/src/radeon_dri.c b/src/radeon_dri.c -index a192811..9fa0add 100644 +index a192811..45414b4 100644 --- a/src/radeon_dri.c +++ b/src/radeon_dri.c @@ -40,6 +40,8 @@ @@ -2545,7 +2566,7 @@ index a192811..9fa0add 100644 static void RADEONDRIClipNotify(ScreenPtr pScreen, WindowPtr *ppWin, int num); #endif #endif -@@ -345,6 +363,120 @@ static void RADEONDestroyContext(ScreenPtr pScreen, drm_context_t hwContext, +@@ -345,6 +363,125 @@ static void RADEONDestroyContext(ScreenPtr pScreen, drm_context_t hwContext, #endif } @@ -2629,6 +2650,7 @@ index a192811..9fa0add 100644 + if (!info->drm_mm) + return TRUE; + ++ + fb_addr = info->mm.front_buffer->offset + info->LinearAddr; + fb_size = ROUND_TO_PAGE(pScrn->displayWidth * pScrn->virtualY * info->CurrentLayout.pixel_bytes); + @@ -2653,6 +2675,10 @@ index a192811..9fa0add 100644 + RADEONInfoPtr info = RADEONPTR(pScrn); + Bool success; + RADEONSAREAPrivPtr sarea = DRIGetSAREAPrivate(pScrn->pScreen); ++ ++ if (info->ChipFamily >= CHIP_FAMILY_R600) ++ return TRUE; ++ + success = radeon_update_dri_mappings(pScrn, sarea); + + if (!success) @@ -2666,7 +2692,7 @@ index a192811..9fa0add 100644 /* Called when the X server is woken up to allow the last client's * context to be saved and the X server's context to be loaded. This is * not necessary for the Radeon since the client detects when it's -@@ -362,7 +494,7 @@ static void RADEONEnterServer(ScreenPtr pScreen) +@@ -362,7 +499,7 @@ static void RADEONEnterServer(ScreenPtr pScreen) RADEON_MARK_SYNC(info, pScrn); pSAREAPriv = DRIGetSAREAPrivate(pScrn->pScreen); @@ -2675,7 +2701,7 @@ index a192811..9fa0add 100644 info->XInited3D = FALSE; info->needCacheFlush = (info->ChipFamily >= CHIP_FAMILY_R300); } -@@ -694,25 +826,37 @@ static void RADEONDRIInitGARTValues(RADEONInfoPtr info) +@@ -694,25 +831,37 @@ static void RADEONDRIInitGARTValues(RADEONInfoPtr info) info->gartOffset = 0; @@ -2729,7 +2755,7 @@ index a192811..9fa0add 100644 } /* Set AGP transfer mode according to requests and constraints */ -@@ -884,6 +1028,7 @@ static Bool RADEONDRIAgpInit(RADEONInfoPtr info, ScreenPtr pScreen) +@@ -884,6 +1033,7 @@ static Bool RADEONDRIAgpInit(RADEONInfoPtr info, ScreenPtr pScreen) xf86DrvMsg(pScreen->myNum, X_INFO, "[agp] ring handle = 0x%08x\n", info->ringHandle); @@ -2737,7 +2763,7 @@ index a192811..9fa0add 100644 if (drmMap(info->drmFD, info->ringHandle, info->ringMapSize, &info->ring) < 0) { xf86DrvMsg(pScreen->myNum, X_ERROR, "[agp] Could not map ring\n"); -@@ -892,7 +1037,7 @@ static Bool RADEONDRIAgpInit(RADEONInfoPtr info, ScreenPtr pScreen) +@@ -892,7 +1042,7 @@ static Bool RADEONDRIAgpInit(RADEONInfoPtr info, ScreenPtr pScreen) xf86DrvMsg(pScreen->myNum, X_INFO, "[agp] Ring mapped at 0x%08lx\n", (unsigned long)info->ring); @@ -2746,7 +2772,7 @@ index a192811..9fa0add 100644 if (drmAddMap(info->drmFD, info->ringReadOffset, info->ringReadMapSize, DRM_AGP, DRM_READ_ONLY, &info->ringReadPtrHandle) < 0) { xf86DrvMsg(pScreen->myNum, X_ERROR, -@@ -903,6 +1048,7 @@ static Bool RADEONDRIAgpInit(RADEONInfoPtr info, ScreenPtr pScreen) +@@ -903,6 +1053,7 @@ static Bool RADEONDRIAgpInit(RADEONInfoPtr info, ScreenPtr pScreen) "[agp] ring read ptr handle = 0x%08x\n", info->ringReadPtrHandle); @@ -2754,7 +2780,7 @@ index a192811..9fa0add 100644 if (drmMap(info->drmFD, info->ringReadPtrHandle, info->ringReadMapSize, &info->ringReadPtr) < 0) { xf86DrvMsg(pScreen->myNum, X_ERROR, -@@ -912,7 +1058,7 @@ static Bool RADEONDRIAgpInit(RADEONInfoPtr info, ScreenPtr pScreen) +@@ -912,7 +1063,7 @@ static Bool RADEONDRIAgpInit(RADEONInfoPtr info, ScreenPtr pScreen) xf86DrvMsg(pScreen->myNum, X_INFO, "[agp] Ring read ptr mapped at 0x%08lx\n", (unsigned long)info->ringReadPtr); @@ -2763,7 +2789,7 @@ index a192811..9fa0add 100644 if (drmAddMap(info->drmFD, info->bufStart, info->bufMapSize, DRM_AGP, 0, &info->bufHandle) < 0) { xf86DrvMsg(pScreen->myNum, X_ERROR, -@@ -986,7 +1132,7 @@ static Bool RADEONDRIPciInit(RADEONInfoPtr info, ScreenPtr pScreen) +@@ -986,7 +1137,7 @@ static Bool RADEONDRIPciInit(RADEONInfoPtr info, ScreenPtr pScreen) } xf86DrvMsg(pScreen->myNum, X_INFO, "[pci] ring handle = 0x%08x\n", info->ringHandle); @@ -2772,7 +2798,7 @@ index a192811..9fa0add 100644 if (drmMap(info->drmFD, info->ringHandle, info->ringMapSize, &info->ring) < 0) { xf86DrvMsg(pScreen->myNum, X_ERROR, "[pci] Could not map ring\n"); -@@ -998,6 +1144,7 @@ static Bool RADEONDRIPciInit(RADEONInfoPtr info, ScreenPtr pScreen) +@@ -998,6 +1149,7 @@ static Bool RADEONDRIPciInit(RADEONInfoPtr info, ScreenPtr pScreen) xf86DrvMsg(pScreen->myNum, X_INFO, "[pci] Ring contents 0x%08lx\n", *(unsigned long *)(pointer)info->ring); @@ -2780,7 +2806,7 @@ index a192811..9fa0add 100644 if (drmAddMap(info->drmFD, info->ringReadOffset, info->ringReadMapSize, DRM_SCATTER_GATHER, flags, &info->ringReadPtrHandle) < 0) { -@@ -1008,7 +1155,7 @@ static Bool RADEONDRIPciInit(RADEONInfoPtr info, ScreenPtr pScreen) +@@ -1008,7 +1160,7 @@ static Bool RADEONDRIPciInit(RADEONInfoPtr info, ScreenPtr pScreen) xf86DrvMsg(pScreen->myNum, X_INFO, "[pci] ring read ptr handle = 0x%08x\n", info->ringReadPtrHandle); @@ -2789,7 +2815,7 @@ index a192811..9fa0add 100644 if (drmMap(info->drmFD, info->ringReadPtrHandle, info->ringReadMapSize, &info->ringReadPtr) < 0) { xf86DrvMsg(pScreen->myNum, X_ERROR, -@@ -1021,6 +1168,7 @@ static Bool RADEONDRIPciInit(RADEONInfoPtr info, ScreenPtr pScreen) +@@ -1021,6 +1173,7 @@ static Bool RADEONDRIPciInit(RADEONInfoPtr info, ScreenPtr pScreen) xf86DrvMsg(pScreen->myNum, X_INFO, "[pci] Ring read ptr contents 0x%08lx\n", *(unsigned long *)(pointer)info->ringReadPtr); @@ -2797,7 +2823,7 @@ index a192811..9fa0add 100644 if (drmAddMap(info->drmFD, info->bufStart, info->bufMapSize, DRM_SCATTER_GATHER, 0, &info->bufHandle) < 0) { -@@ -1073,6 +1221,9 @@ static Bool RADEONDRIPciInit(RADEONInfoPtr info, ScreenPtr pScreen) +@@ -1073,6 +1226,9 @@ static Bool RADEONDRIPciInit(RADEONInfoPtr info, ScreenPtr pScreen) */ static Bool RADEONDRIMapInit(RADEONInfoPtr info, ScreenPtr pScreen) { @@ -2807,7 +2833,7 @@ index a192811..9fa0add 100644 /* Map registers */ info->registerSize = info->MMIOSize; if (drmAddMap(info->drmFD, info->MMIOAddr, info->registerSize, -@@ -1094,12 +1245,12 @@ static int RADEONDRIKernelInit(RADEONInfoPtr info, ScreenPtr pScreen) +@@ -1094,12 +1250,12 @@ static int RADEONDRIKernelInit(RADEONInfoPtr info, ScreenPtr pScreen) memset(&drmInfo, 0, sizeof(drmRadeonInit)); if ( info->ChipFamily >= CHIP_FAMILY_R300 ) @@ -2823,7 +2849,7 @@ index a192811..9fa0add 100644 drmInfo.sarea_priv_offset = sizeof(XF86DRISAREARec); drmInfo.is_pci = (info->cardType!=CARD_AGP); -@@ -1111,19 +1262,22 @@ static int RADEONDRIKernelInit(RADEONInfoPtr info, ScreenPtr pScreen) +@@ -1111,19 +1267,22 @@ static int RADEONDRIKernelInit(RADEONInfoPtr info, ScreenPtr pScreen) drmInfo.fb_bpp = info->CurrentLayout.pixel_code; drmInfo.depth_bpp = (info->depthBits - 8) * 2; @@ -2859,7 +2885,7 @@ index a192811..9fa0add 100644 if (drmCommandWrite(info->drmFD, DRM_RADEON_CP_INIT, &drmInfo, sizeof(drmRadeonInit)) < 0) -@@ -1133,7 +1287,8 @@ static int RADEONDRIKernelInit(RADEONInfoPtr info, ScreenPtr pScreen) +@@ -1133,7 +1292,8 @@ static int RADEONDRIKernelInit(RADEONInfoPtr info, ScreenPtr pScreen) * registers back to their default values, so we need to restore * those engine register here. */ @@ -2869,7 +2895,7 @@ index a192811..9fa0add 100644 return TRUE; } -@@ -1329,12 +1484,11 @@ Bool RADEONDRIGetVersion(ScrnInfoPtr pScrn) +@@ -1329,12 +1489,11 @@ Bool RADEONDRIGetVersion(ScrnInfoPtr pScrn) /* Get DRM version & close DRM */ info->pKernelDRMVersion = drmGetVersion(fd); @@ -2883,7 +2909,7 @@ index a192811..9fa0add 100644 } /* Now check if we qualify */ -@@ -1368,10 +1522,29 @@ Bool RADEONDRIGetVersion(ScrnInfoPtr pScrn) +@@ -1368,10 +1527,29 @@ Bool RADEONDRIGetVersion(ScrnInfoPtr pScrn) req_patch); drmFreeVersion(info->pKernelDRMVersion); info->pKernelDRMVersion = NULL; @@ -2914,7 +2940,7 @@ index a192811..9fa0add 100644 } Bool RADEONDRISetVBlankInterrupt(ScrnInfoPtr pScrn, Bool on) -@@ -1380,6 +1553,9 @@ Bool RADEONDRISetVBlankInterrupt(ScrnInfoPtr pScrn, Bool on) +@@ -1380,6 +1558,9 @@ Bool RADEONDRISetVBlankInterrupt(ScrnInfoPtr pScrn, Bool on) xf86CrtcConfigPtr xf86_config = XF86_CRTC_CONFIG_PTR(pScrn); int value = 0; @@ -2924,7 +2950,7 @@ index a192811..9fa0add 100644 if (!info->want_vblank_interrupts) on = FALSE; -@@ -1399,6 +1575,44 @@ Bool RADEONDRISetVBlankInterrupt(ScrnInfoPtr pScrn, Bool on) +@@ -1399,6 +1580,48 @@ Bool RADEONDRISetVBlankInterrupt(ScrnInfoPtr pScrn, Bool on) return TRUE; } @@ -2937,6 +2963,10 @@ index a192811..9fa0add 100644 + * common mappings. Add additional + * mappings here. + */ ++ ++ if (info->ChipFamily >= CHIP_FAMILY_R600) ++ return TRUE; ++ + if (!RADEONDRIMapInit(info, pScreen)) { + RADEONDRICloseScreen(pScreen); + return FALSE; @@ -2969,7 +2999,7 @@ index a192811..9fa0add 100644 /* Initialize the screen-specific data structures for the DRI and the * Radeon. This is the main entry point to the device-specific -@@ -1462,10 +1676,23 @@ Bool RADEONDRIScreenInit(ScreenPtr pScreen) +@@ -1462,10 +1685,23 @@ Bool RADEONDRIScreenInit(ScreenPtr pScreen) pDRIInfo->ddxDriverMajorVersion = info->allowColorTiling ? 5 : 4; pDRIInfo->ddxDriverMinorVersion = 3; pDRIInfo->ddxDriverPatchVersion = 0; @@ -2997,7 +3027,7 @@ index a192811..9fa0add 100644 pDRIInfo->ddxDrawableTableEntry = RADEON_MAX_DRAWABLES; pDRIInfo->maxDrawableTableEntry = (SAREA_MAX_DRAWABLES < RADEON_MAX_DRAWABLES -@@ -1518,9 +1745,7 @@ Bool RADEONDRIScreenInit(ScreenPtr pScreen) +@@ -1518,9 +1754,7 @@ Bool RADEONDRIScreenInit(ScreenPtr pScreen) pDRIInfo->TransitionTo3d = RADEONDRITransitionTo3d; pDRIInfo->TransitionSingleToMulti3D = RADEONDRITransitionSingleToMulti3d; pDRIInfo->TransitionMultiToSingle3D = RADEONDRITransitionMultiToSingle3d; @@ -3008,7 +3038,7 @@ index a192811..9fa0add 100644 pDRIInfo->ClipNotify = RADEONDRIClipNotify; #endif -@@ -1552,57 +1777,61 @@ Bool RADEONDRIScreenInit(ScreenPtr pScreen) +@@ -1552,57 +1786,61 @@ Bool RADEONDRIScreenInit(ScreenPtr pScreen) pDRIInfo = NULL; return FALSE; } @@ -3113,7 +3143,7 @@ index a192811..9fa0add 100644 static Bool RADEONDRIDoCloseScreen(int scrnIndex, ScreenPtr pScreen) { ScrnInfoPtr pScrn = xf86Screens[pScreen->myNum]; -@@ -1644,14 +1873,18 @@ Bool RADEONDRIFinishScreenInit(ScreenPtr pScreen) +@@ -1644,14 +1882,18 @@ Bool RADEONDRIFinishScreenInit(ScreenPtr pScreen) return FALSE; } @@ -3138,7 +3168,7 @@ index a192811..9fa0add 100644 /* Initialize kernel GART memory manager */ RADEONDRIGartHeapInit(info, pScreen); -@@ -1663,6 +1896,10 @@ Bool RADEONDRIFinishScreenInit(ScreenPtr pScreen) +@@ -1663,6 +1905,10 @@ Bool RADEONDRIFinishScreenInit(ScreenPtr pScreen) pSAREAPriv = (RADEONSAREAPrivPtr)DRIGetSAREAPrivate(pScreen); memset(pSAREAPriv, 0, sizeof(*pSAREAPriv)); @@ -3149,7 +3179,7 @@ index a192811..9fa0add 100644 pRADEONDRI = (RADEONDRIPtr)info->pDRIInfo->devPrivate; pRADEONDRI->deviceID = info->Chipset; -@@ -1806,7 +2043,7 @@ void RADEONDRICloseScreen(ScreenPtr pScreen) +@@ -1806,7 +2052,7 @@ void RADEONDRICloseScreen(ScreenPtr pScreen) /* De-allocate all kernel resources */ memset(&drmInfo, 0, sizeof(drmRadeonInit)); @@ -3158,7 +3188,7 @@ index a192811..9fa0add 100644 drmCommandWrite(info->drmFD, DRM_RADEON_CP_INIT, &drmInfo, sizeof(drmRadeonInit)); -@@ -1819,6 +2056,7 @@ void RADEONDRICloseScreen(ScreenPtr pScreen) +@@ -1819,6 +2065,7 @@ void RADEONDRICloseScreen(ScreenPtr pScreen) drmUnmap(info->buf, info->bufMapSize); info->buf = NULL; } @@ -3166,7 +3196,7 @@ index a192811..9fa0add 100644 if (info->ringReadPtr) { drmUnmap(info->ringReadPtr, info->ringReadMapSize); info->ringReadPtr = NULL; -@@ -1827,6 +2065,7 @@ void RADEONDRICloseScreen(ScreenPtr pScreen) +@@ -1827,6 +2074,7 @@ void RADEONDRICloseScreen(ScreenPtr pScreen) drmUnmap(info->ring, info->ringMapSize); info->ring = NULL; } @@ -3174,7 +3204,7 @@ index a192811..9fa0add 100644 if (info->agpMemHandle != DRM_AGP_NO_HANDLE) { drmAgpUnbind(info->drmFD, info->agpMemHandle); drmAgpFree(info->drmFD, info->agpMemHandle); -@@ -1903,7 +2142,7 @@ static void RADEONDRIRefreshArea(ScrnInfoPtr pScrn, RegionPtr pReg) +@@ -1903,7 +2151,7 @@ static void RADEONDRIRefreshArea(ScrnInfoPtr pScrn, RegionPtr pReg) /* Don't want to do this when no 3d is active and pages are * right-way-round */ @@ -3183,7 +3213,7 @@ index a192811..9fa0add 100644 return; REGION_NULL(pScreen, ®ion); -@@ -1992,7 +2231,7 @@ static void RADEONEnablePageFlip(ScreenPtr pScreen) +@@ -1992,7 +2240,7 @@ static void RADEONEnablePageFlip(ScreenPtr pScreen) .y2 = pScrn->virtualY - 1 }; RegionPtr pReg = REGION_CREATE(pScreen, &box, 1); @@ -3192,7 +3222,7 @@ index a192811..9fa0add 100644 RADEONDRIRefreshArea(pScrn, pReg); REGION_DESTROY(pScreen, pReg); } -@@ -2007,7 +2246,7 @@ static void RADEONDisablePageFlip(ScreenPtr pScreen) +@@ -2007,7 +2255,7 @@ static void RADEONDisablePageFlip(ScreenPtr pScreen) */ RADEONSAREAPrivPtr pSAREAPriv = DRIGetSAREAPrivate(pScreen); @@ -3201,7 +3231,7 @@ index a192811..9fa0add 100644 } static void RADEONDRITransitionSingleToMulti3d(ScreenPtr pScreen) -@@ -2232,3 +2471,16 @@ int RADEONDRISetParam(ScrnInfoPtr pScrn, unsigned int param, int64_t value) +@@ -2232,3 +2480,16 @@ int RADEONDRISetParam(ScrnInfoPtr pScrn, unsigned int param, int64_t value) &radeonsetparam, sizeof(drmRadeonSetParam)); return ret; } @@ -3219,10 +3249,22 @@ index a192811..9fa0add 100644 + +} diff --git a/src/radeon_driver.c b/src/radeon_driver.c -index 45d2c2f..8fa32ab 100644 +index 45d2c2f..d5bb24d 100644 --- a/src/radeon_driver.c +++ b/src/radeon_driver.c -@@ -1621,6 +1621,7 @@ static Bool RADEONPreInitVRAM(ScrnInfoPtr pScrn) +@@ -224,7 +224,10 @@ radeonShadowWindow(ScreenPtr screen, CARD32 row, CARD32 offset, int mode, + stride = (pScrn->displayWidth * pScrn->bitsPerPixel) / 8; + *size = stride; + +- return ((uint8_t *)info->FB + row * stride + offset); ++ if (info->drm_mm) ++ return ((uint8_t *)info->mm.front_buffer->map + row * stride + offset); ++ else ++ return ((uint8_t *)info->FB + row * stride + offset); + } + static Bool + RADEONCreateScreenResources (ScreenPtr pScreen) +@@ -1621,6 +1624,7 @@ static Bool RADEONPreInitVRAM(ScrnInfoPtr pScrn) } pScrn->videoRam &= ~1023; @@ -3230,7 +3272,7 @@ index 45d2c2f..8fa32ab 100644 info->FbMapSize = pScrn->videoRam * 1024; /* if the card is PCI Express reserve the last 32k for the gart table */ -@@ -1748,56 +1749,62 @@ static Bool RADEONPreInitChipType(ScrnInfoPtr pScrn) +@@ -1748,56 +1752,62 @@ static Bool RADEONPreInitChipType(ScrnInfoPtr pScrn) from = X_PROBED; info->LinearAddr = PCI_REGION_BASE(info->PciInfo, 0, REGION_MEM) & ~0x1ffffffUL; pScrn->memPhysBase = info->LinearAddr; @@ -3335,7 +3377,7 @@ index 45d2c2f..8fa32ab 100644 #ifdef XF86DRI /* AGP/PCI */ -@@ -1985,6 +1992,9 @@ static Bool RADEONPreInitAccel(ScrnInfoPtr pScrn) +@@ -1985,6 +1995,9 @@ static Bool RADEONPreInitAccel(ScrnInfoPtr pScrn) if (!xf86ReturnOptValBool(info->Options, OPTION_NOACCEL, FALSE)) { int errmaj = 0, errmin = 0; @@ -3345,7 +3387,7 @@ index 45d2c2f..8fa32ab 100644 from = X_DEFAULT; #if defined(USE_EXA) #if defined(USE_XAA) -@@ -1995,6 +2005,7 @@ static Bool RADEONPreInitAccel(ScrnInfoPtr pScrn) +@@ -1995,6 +2008,7 @@ static Bool RADEONPreInitAccel(ScrnInfoPtr pScrn) info->useEXA = TRUE; } else if (xf86NameCmp(optstr, "XAA") == 0) { from = X_CONFIG; @@ -3353,7 +3395,7 @@ index 45d2c2f..8fa32ab 100644 } } #else /* USE_XAA */ -@@ -2664,6 +2675,37 @@ static const xf86CrtcConfigFuncsRec RADEONCRTCResizeFuncs = { +@@ -2664,6 +2678,37 @@ static const xf86CrtcConfigFuncsRec RADEONCRTCResizeFuncs = { RADEONCRTCResize }; @@ -3391,7 +3433,7 @@ index 45d2c2f..8fa32ab 100644 Bool RADEONPreInit(ScrnInfoPtr pScrn, int flags) { xf86CrtcConfigPtr xf86_config; -@@ -2684,6 +2726,8 @@ Bool RADEONPreInit(ScrnInfoPtr pScrn, int flags) +@@ -2684,6 +2729,8 @@ Bool RADEONPreInit(ScrnInfoPtr pScrn, int flags) info = RADEONPTR(pScrn); info->MMIO = NULL; @@ -3400,7 +3442,7 @@ index 45d2c2f..8fa32ab 100644 info->IsSecondary = FALSE; info->IsPrimary = FALSE; -@@ -2718,59 +2762,63 @@ Bool RADEONPreInit(ScrnInfoPtr pScrn, int flags) +@@ -2718,59 +2765,63 @@ Bool RADEONPreInit(ScrnInfoPtr pScrn, int flags) } info->PciInfo = xf86GetPciInfoForEntity(info->pEnt->index); @@ -3508,7 +3550,7 @@ index 45d2c2f..8fa32ab 100644 if (xf86RegisterResources(info->pEnt->index, 0, ResExclusive)) goto fail; -@@ -2780,10 +2828,12 @@ Bool RADEONPreInit(ScrnInfoPtr pScrn, int flags) +@@ -2780,10 +2831,12 @@ Bool RADEONPreInit(ScrnInfoPtr pScrn, int flags) pScrn->racMemFlags = RAC_FB | RAC_COLORMAP | RAC_VIEWPORT | RAC_CURSOR; pScrn->monitor = pScrn->confScreen->monitor; @@ -3525,7 +3567,7 @@ index 45d2c2f..8fa32ab 100644 if (!RADEONPreInitVisual(pScrn)) goto fail; -@@ -2797,136 +2847,192 @@ Bool RADEONPreInit(ScrnInfoPtr pScrn, int flags) +@@ -2797,136 +2850,194 @@ Bool RADEONPreInit(ScrnInfoPtr pScrn, int flags) memcpy(info->Options, RADEONOptions, sizeof(RADEONOptions)); xf86ProcessOptions(pScrn->scrnIndex, pScrn->options, info->Options); @@ -3806,10 +3848,12 @@ index 45d2c2f..8fa32ab 100644 + info->fbLocation = (value & 0xffff) << 16; + } + } -+ info->useEXA = TRUE; -+ info->drm_mm = TRUE; -+ info->directRenderingEnabled = TRUE; ++ if (info->ChipFamily < CHIP_FAMILY_R600) { ++ info->useEXA = TRUE; ++ info->directRenderingEnabled = TRUE; ++ } + info->new_cs = TRUE; ++ info->drm_mm = TRUE; + // info->directRenderingDisabled = FALSE; +#endif + } @@ -3823,7 +3867,7 @@ index 45d2c2f..8fa32ab 100644 /* Get ScreenInit function */ if (!xf86LoadSubModule(pScrn, "fb")) return FALSE; -@@ -2941,10 +3047,12 @@ Bool RADEONPreInit(ScrnInfoPtr pScrn, int flags) +@@ -2941,10 +3052,12 @@ Bool RADEONPreInit(ScrnInfoPtr pScrn, int flags) if (!RADEONPreInitXv(pScrn)) goto fail; } @@ -3840,7 +3884,7 @@ index 45d2c2f..8fa32ab 100644 } if (pScrn->modes == NULL) { -@@ -3185,7 +3293,7 @@ Bool RADEONScreenInit(int scrnIndex, ScreenPtr pScreen, +@@ -3185,7 +3298,7 @@ Bool RADEONScreenInit(int scrnIndex, ScreenPtr pScreen, int subPixelOrder = SubPixelUnknown; char* s; #endif @@ -3849,7 +3893,7 @@ index 45d2c2f..8fa32ab 100644 info->accelOn = FALSE; #ifdef USE_XAA -@@ -3205,52 +3313,55 @@ Bool RADEONScreenInit(int scrnIndex, ScreenPtr pScreen, +@@ -3205,52 +3318,55 @@ Bool RADEONScreenInit(int scrnIndex, ScreenPtr pScreen, "RADEONScreenInit %lx %ld\n", pScrn->memPhysBase, pScrn->fbOffset); #endif @@ -3939,7 +3983,7 @@ index 45d2c2f..8fa32ab 100644 /* Visual setup */ miClearVisualTypes(); if (!miSetVisualTypes(pScrn->depth, -@@ -3284,19 +3395,21 @@ Bool RADEONScreenInit(int scrnIndex, ScreenPtr pScreen, +@@ -3284,19 +3400,21 @@ Bool RADEONScreenInit(int scrnIndex, ScreenPtr pScreen, hasDRI = info->directRenderingEnabled; #endif /* XF86DRI */ @@ -3973,7 +4017,7 @@ index 45d2c2f..8fa32ab 100644 } } -@@ -3341,6 +3454,9 @@ Bool RADEONScreenInit(int scrnIndex, ScreenPtr pScreen, +@@ -3341,6 +3459,9 @@ Bool RADEONScreenInit(int scrnIndex, ScreenPtr pScreen, from = X_CONFIG; } @@ -3983,7 +4027,25 @@ index 45d2c2f..8fa32ab 100644 /* Reserve approx. half of offscreen memory for local textures by * default, can be overridden with Option "FBTexPercent". * Round down to a whole number of texture regions. -@@ -3407,7 +3523,7 @@ Bool RADEONScreenInit(int scrnIndex, ScreenPtr pScreen, +@@ -3369,7 +3490,7 @@ Bool RADEONScreenInit(int scrnIndex, ScreenPtr pScreen, + #endif + + #if defined(XF86DRI) && defined(USE_XAA) +- if (!info->useEXA && hasDRI) { ++ if (!info->useEXA && hasDRI && !info->drm_mm) { + info->textureSize = -1; + if (xf86GetOptValInteger(info->Options, OPTION_FBTEX_PERCENT, + &(info->textureSize))) { +@@ -3387,7 +3508,7 @@ Bool RADEONScreenInit(int scrnIndex, ScreenPtr pScreen, + #endif + + #ifdef USE_XAA +- if (!info->useEXA && !hasDRI && !RADEONSetupMemXAA(scrnIndex, pScreen)) ++ if (!info->useEXA && !hasDRI && !info->drm_mm && !RADEONSetupMemXAA(scrnIndex, pScreen)) + return FALSE; + #endif + +@@ -3407,7 +3528,7 @@ Bool RADEONScreenInit(int scrnIndex, ScreenPtr pScreen, info->CurrentLayout.pixel_bytes); int maxy = info->FbMapSize / width_bytes; @@ -3992,7 +4054,7 @@ index 45d2c2f..8fa32ab 100644 xf86DrvMsg(scrnIndex, X_ERROR, "Static buffer allocation failed. Disabling DRI.\n"); xf86DrvMsg(scrnIndex, X_ERROR, -@@ -3421,15 +3537,39 @@ Bool RADEONScreenInit(int scrnIndex, ScreenPtr pScreen, +@@ -3421,15 +3542,39 @@ Bool RADEONScreenInit(int scrnIndex, ScreenPtr pScreen, } } @@ -4035,7 +4097,7 @@ index 45d2c2f..8fa32ab 100644 #endif xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG, "Initializing fb layer\n"); -@@ -3453,7 +3593,7 @@ Bool RADEONScreenInit(int scrnIndex, ScreenPtr pScreen, +@@ -3453,7 +3598,7 @@ Bool RADEONScreenInit(int scrnIndex, ScreenPtr pScreen, if (info->r600_shadow_fb == FALSE) { /* Init fb layer */ @@ -4044,7 +4106,7 @@ index 45d2c2f..8fa32ab 100644 pScrn->virtualX, pScrn->virtualY, pScrn->xDpi, pScrn->yDpi, pScrn->displayWidth, pScrn->bitsPerPixel)) -@@ -3508,7 +3648,7 @@ Bool RADEONScreenInit(int scrnIndex, ScreenPtr pScreen, +@@ -3508,7 +3653,7 @@ Bool RADEONScreenInit(int scrnIndex, ScreenPtr pScreen, /* DRI finalisation */ #ifdef XF86DRI @@ -4053,7 +4115,7 @@ index 45d2c2f..8fa32ab 100644 info->pKernelDRMVersion->version_minor >= 19) { if (RADEONDRISetParam(pScrn, RADEON_SETPARAM_PCIGART_LOCATION, info->pciGartOffset) < 0) -@@ -3527,15 +3667,21 @@ Bool RADEONScreenInit(int scrnIndex, ScreenPtr pScreen, +@@ -3527,15 +3672,21 @@ Bool RADEONScreenInit(int scrnIndex, ScreenPtr pScreen, info->directRenderingEnabled = RADEONDRIFinishScreenInit(pScreen); } if (info->directRenderingEnabled) { @@ -4079,7 +4141,7 @@ index 45d2c2f..8fa32ab 100644 } xf86DrvMsg(pScrn->scrnIndex, X_INFO, "Direct rendering enabled\n"); -@@ -5355,6 +5501,11 @@ void RADEONAdjustFrame(int scrnIndex, int x, int y, int flags) +@@ -5355,6 +5506,11 @@ void RADEONAdjustFrame(int scrnIndex, int x, int y, int flags) xf86OutputPtr output = config->output[config->compat_output]; xf86CrtcPtr crtc = output->crtc; @@ -4091,7 +4153,7 @@ index 45d2c2f..8fa32ab 100644 #ifdef XF86DRI if (info->CPStarted && pScrn->pScreen) DRILock(pScrn->pScreen, 0); #endif -@@ -5390,67 +5541,76 @@ Bool RADEONEnterVT(int scrnIndex, int flags) +@@ -5390,67 +5546,80 @@ Bool RADEONEnterVT(int scrnIndex, int flags) xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG, "RADEONEnterVT\n"); @@ -4100,37 +4162,53 @@ index 45d2c2f..8fa32ab 100644 - rhdAtomASICInit(info->atomBIOS); - } else { - xf86Int10InfoPtr pInt; -- -- pInt = xf86InitInt10 (info->pEnt->index); -- if (pInt) { -- pInt->num = 0xe6; -- xf86ExecX86int10 (pInt); -- xf86FreeInt10 (pInt); + if (!info->drm_mode_setting) { + if (!radeon_card_posted(pScrn)) { /* Softboot V_BIOS */ -+ if (info->IsAtomBios) { ++ if (info->IsAtomBios) { + rhdAtomASICInit(info->atomBIOS); - } else { -- RADEONGetBIOSInitTableOffsets(pScrn); -- RADEONPostCardFromBIOSTables(pScrn); -+ xf86Int10InfoPtr pInt; -+ pInt = xf86InitInt10 (info->pEnt->index); -+ if (pInt) { ++ } else { ++ xf86Int10InfoPtr pInt; ++ ++ pInt = xf86InitInt10 (info->pEnt->index); ++ if (pInt) { + pInt->num = 0xe6; + xf86ExecX86int10 (pInt); + xf86FreeInt10 (pInt); -+ } else { ++ } else { + RADEONGetBIOSInitTableOffsets(pScrn); + RADEONPostCardFromBIOSTables(pScrn); -+ } ++ } ++ } ++ } ++ /* Makes sure the engine is idle before doing anything */ ++ RADEONWaitForIdleMMIO(pScrn); + +- pInt = xf86InitInt10 (info->pEnt->index); +- if (pInt) { +- pInt->num = 0xe6; +- xf86ExecX86int10 (pInt); +- xf86FreeInt10 (pInt); ++ if (info->IsMobility && !IS_AVIVO_VARIANT) { ++ if (xf86ReturnOptValBool(info->Options, OPTION_DYNAMIC_CLOCKS, FALSE)) { ++ RADEONSetDynamicClock(pScrn, 1); + } else { +- RADEONGetBIOSInitTableOffsets(pScrn); +- RADEONPostCardFromBIOSTables(pScrn); ++ RADEONSetDynamicClock(pScrn, 0); ++ } ++ } else if (IS_AVIVO_VARIANT) { ++ if (xf86ReturnOptValBool(info->Options, OPTION_DYNAMIC_CLOCKS, FALSE)) { ++ atombios_static_pwrmgt_setup(pScrn, 1); ++ atombios_dyn_clk_setup(pScrn, 1); } } - } - - /* Makes sure the engine is idle before doing anything */ - RADEONWaitForIdleMMIO(pScrn); -+ /* Makes sure the engine is idle before doing anything */ -+ RADEONWaitForIdleMMIO(pScrn); ++ ++ if (IS_R300_VARIANT || IS_RV100_VARIANT) ++ RADEONForceSomeClocks(pScrn); - if (info->IsMobility && !IS_AVIVO_VARIANT) { - if (xf86ReturnOptValBool(info->Options, OPTION_DYNAMIC_CLOCKS, FALSE)) { @@ -4142,28 +4220,16 @@ index 45d2c2f..8fa32ab 100644 - if (xf86ReturnOptValBool(info->Options, OPTION_DYNAMIC_CLOCKS, FALSE)) { - atombios_static_pwrmgt_setup(pScrn, 1); - atombios_dyn_clk_setup(pScrn, 1); -+ if (info->IsMobility && !IS_AVIVO_VARIANT) { -+ if (xf86ReturnOptValBool(info->Options, OPTION_DYNAMIC_CLOCKS, FALSE)) { -+ RADEONSetDynamicClock(pScrn, 1); -+ } else { -+ RADEONSetDynamicClock(pScrn, 0); -+ } -+ } else if (IS_AVIVO_VARIANT) { -+ if (xf86ReturnOptValBool(info->Options, OPTION_DYNAMIC_CLOCKS, FALSE)) { -+ atombios_static_pwrmgt_setup(pScrn, 1); -+ atombios_dyn_clk_setup(pScrn, 1); -+ } - } -+ -+ if (IS_R300_VARIANT || IS_RV100_VARIANT) -+ RADEONForceSomeClocks(pScrn); -+ +- } } - if (IS_R300_VARIANT || IS_RV100_VARIANT) - RADEONForceSomeClocks(pScrn); -+ if (info->drm_mm) ++ if (info->drm_mm) { + radeon_bind_all_memory(pScrn); ++ info->XInited3D = FALSE; ++ info->engineMode = EXA_ENGINEMODE_UNKNOWN; ++ } - for (i = 0; i < config->num_crtc; i++) - radeon_crtc_modeset_ioctl(config->crtc[i], TRUE); @@ -4214,7 +4280,7 @@ index 45d2c2f..8fa32ab 100644 } #endif /* this will get XVideo going again, but only if XVideo was initialised -@@ -5462,7 +5622,7 @@ Bool RADEONEnterVT(int scrnIndex, int flags) +@@ -5462,7 +5631,7 @@ Bool RADEONEnterVT(int scrnIndex, int flags) RADEONEngineRestore(pScrn); #ifdef XF86DRI @@ -4223,7 +4289,7 @@ index 45d2c2f..8fa32ab 100644 RADEONCP_START(pScrn, info); DRIUnlock(pScrn->pScreen); } -@@ -5485,24 +5645,26 @@ void RADEONLeaveVT(int scrnIndex, int flags) +@@ -5485,24 +5654,26 @@ void RADEONLeaveVT(int scrnIndex, int flags) "RADEONLeaveVT\n"); #ifdef XF86DRI if (RADEONPTR(pScrn)->directRenderingInited) { @@ -4263,7 +4329,7 @@ index 45d2c2f..8fa32ab 100644 i = 0; -@@ -5531,10 +5693,15 @@ void RADEONLeaveVT(int scrnIndex, int flags) +@@ -5531,10 +5702,15 @@ void RADEONLeaveVT(int scrnIndex, int flags) xf86_hide_cursors (pScrn); @@ -4282,7 +4348,7 @@ index 45d2c2f..8fa32ab 100644 xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG, "Ok, leaving now...\n"); -@@ -5579,7 +5746,8 @@ static Bool RADEONCloseScreen(int scrnIndex, ScreenPtr pScreen) +@@ -5579,7 +5755,8 @@ static Bool RADEONCloseScreen(int scrnIndex, ScreenPtr pScreen) #endif /* USE_XAA */ if (pScrn->vtSema) { @@ -4292,7 +4358,7 @@ index 45d2c2f..8fa32ab 100644 } xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG, -@@ -5614,6 +5782,12 @@ static Bool RADEONCloseScreen(int scrnIndex, ScreenPtr pScreen) +@@ -5614,6 +5791,12 @@ static Bool RADEONCloseScreen(int scrnIndex, ScreenPtr pScreen) info->DGAModes = NULL; xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG, "Unmapping memory\n"); @@ -4820,10 +4886,10 @@ index 02fd4fc..555ae16 100644 } #endif diff --git a/src/radeon_exa_funcs.c b/src/radeon_exa_funcs.c -index 56de23e..628d2c7 100644 +index 56de23e..b8b6602 100644 --- a/src/radeon_exa_funcs.c +++ b/src/radeon_exa_funcs.c -@@ -74,21 +74,69 @@ FUNC_NAME(RADEONSync)(ScreenPtr pScreen, int marker) +@@ -74,21 +74,78 @@ FUNC_NAME(RADEONSync)(ScreenPtr pScreen, int marker) ScrnInfoPtr pScrn = xf86Screens[pScreen->myNum]; RADEONInfoPtr info = RADEONPTR(pScrn); @@ -4856,8 +4922,17 @@ index 56de23e..628d2c7 100644 + + qwords = info->new_cs ? 11 : 9; + qwords += (has_src ? (info->new_cs ? 3 : 1) : 0); ++ qwords += (info->ChipFamily <= CHIP_FAMILY_RV280 ? 3 : 2); + + BEGIN_ACCEL(qwords); ++ if (info->ChipFamily <= CHIP_FAMILY_RV280) { ++ OUT_ACCEL_REG(RADEON_RE_TOP_LEFT, 0); ++ OUT_ACCEL_REG(RADEON_RE_WIDTH_HEIGHT, 0x7ff07ff); ++ OUT_ACCEL_REG(RADEON_AUX_SC_CNTL, 0); ++ } else { ++ OUT_ACCEL_REG(R300_SC_SCISSOR0, 0); ++ OUT_ACCEL_REG(R300_SC_SCISSOR1, 0x7ff07ff); ++ } + OUT_ACCEL_REG(RADEON_DEFAULT_SC_BOTTOM_RIGHT, info->state_2d.default_sc_bottom_right); + OUT_ACCEL_REG(RADEON_DP_GUI_MASTER_CNTL, info->state_2d.dp_gui_master_cntl); + OUT_ACCEL_REG(RADEON_DP_BRUSH_FRGD_CLR, info->state_2d.dp_brush_frgd_clr); @@ -4894,7 +4969,7 @@ index 56de23e..628d2c7 100644 ACCEL_PREAMBLE(); TRACE; -@@ -97,25 +145,35 @@ FUNC_NAME(RADEONPrepareSolid)(PixmapPtr pPix, int alu, Pixel pm, Pixel fg) +@@ -97,25 +154,35 @@ FUNC_NAME(RADEONPrepareSolid)(PixmapPtr pPix, int alu, Pixel pm, Pixel fg) RADEON_FALLBACK(("24bpp unsupported\n")); if (!RADEONGetDatatypeBpp(pPix->drawable.bitsPerPixel, &datatype)) RADEON_FALLBACK(("RADEONGetDatatypeBpp failed\n")); @@ -4945,7 +5020,7 @@ index 56de23e..628d2c7 100644 return TRUE; } -@@ -148,8 +206,10 @@ FUNC_NAME(RADEONDoneSolid)(PixmapPtr pPix) +@@ -148,8 +215,10 @@ FUNC_NAME(RADEONDoneSolid)(PixmapPtr pPix) OUT_ACCEL_REG(RADEON_WAIT_UNTIL, RADEON_WAIT_2D_IDLECLEAN | RADEON_WAIT_DMA_GUI_IDLE); FINISH_ACCEL(); @@ -4956,7 +5031,7 @@ index 56de23e..628d2c7 100644 void FUNC_NAME(RADEONDoPrepareCopy)(ScrnInfoPtr pScrn, uint32_t src_pitch_offset, uint32_t dst_pitch_offset, uint32_t datatype, int rop, -@@ -160,23 +220,28 @@ FUNC_NAME(RADEONDoPrepareCopy)(ScrnInfoPtr pScrn, uint32_t src_pitch_offset, +@@ -160,23 +229,28 @@ FUNC_NAME(RADEONDoPrepareCopy)(ScrnInfoPtr pScrn, uint32_t src_pitch_offset, RADEON_SWITCH_TO_2D(); @@ -5002,7 +5077,7 @@ index 56de23e..628d2c7 100644 } static Bool -@@ -187,7 +252,7 @@ FUNC_NAME(RADEONPrepareCopy)(PixmapPtr pSrc, PixmapPtr pDst, +@@ -187,7 +261,7 @@ FUNC_NAME(RADEONPrepareCopy)(PixmapPtr pSrc, PixmapPtr pDst, { RINFO_FROM_SCREEN(pDst->drawable.pScreen); uint32_t datatype, src_pitch_offset, dst_pitch_offset; @@ -5011,7 +5086,7 @@ index 56de23e..628d2c7 100644 TRACE; info->xdir = xdir; -@@ -197,10 +262,19 @@ FUNC_NAME(RADEONPrepareCopy)(PixmapPtr pSrc, PixmapPtr pDst, +@@ -197,10 +271,19 @@ FUNC_NAME(RADEONPrepareCopy)(PixmapPtr pSrc, PixmapPtr pDst, RADEON_FALLBACK(("24bpp unsupported")); if (!RADEONGetDatatypeBpp(pDst->drawable.bitsPerPixel, &datatype)) RADEON_FALLBACK(("RADEONGetDatatypeBpp failed\n")); @@ -5033,7 +5108,7 @@ index 56de23e..628d2c7 100644 FUNC_NAME(RADEONDoPrepareCopy)(pScrn, src_pitch_offset, dst_pitch_offset, datatype, rop, planemask); -@@ -250,6 +324,8 @@ FUNC_NAME(RADEONDoneCopy)(PixmapPtr pDst) +@@ -250,6 +333,8 @@ FUNC_NAME(RADEONDoneCopy)(PixmapPtr pDst) OUT_ACCEL_REG(RADEON_WAIT_UNTIL, RADEON_WAIT_2D_IDLECLEAN | RADEON_WAIT_DMA_GUI_IDLE); FINISH_ACCEL(); @@ -5042,7 +5117,7 @@ index 56de23e..628d2c7 100644 } static Bool -@@ -260,6 +336,8 @@ FUNC_NAME(RADEONUploadToScreen)(PixmapPtr pDst, int x, int y, int w, int h, +@@ -260,6 +345,8 @@ FUNC_NAME(RADEONUploadToScreen)(PixmapPtr pDst, int x, int y, int w, int h, uint8_t *dst = info->FB + exaGetPixmapOffset(pDst); unsigned int dst_pitch = exaGetPixmapPitch(pDst); unsigned int bpp = pDst->drawable.bitsPerPixel; @@ -5051,7 +5126,7 @@ index 56de23e..628d2c7 100644 #ifdef ACCEL_CP unsigned int hpass; uint32_t buf_pitch, dst_pitch_off; -@@ -276,10 +354,47 @@ FUNC_NAME(RADEONUploadToScreen)(PixmapPtr pDst, int x, int y, int w, int h, +@@ -276,10 +363,47 @@ FUNC_NAME(RADEONUploadToScreen)(PixmapPtr pDst, int x, int y, int w, int h, if (bpp < 8) return FALSE; @@ -5102,7 +5177,7 @@ index 56de23e..628d2c7 100644 int cpp = bpp / 8; ACCEL_PREAMBLE(); -@@ -294,9 +409,10 @@ FUNC_NAME(RADEONUploadToScreen)(PixmapPtr pDst, int x, int y, int w, int h, +@@ -294,9 +418,10 @@ FUNC_NAME(RADEONUploadToScreen)(PixmapPtr pDst, int x, int y, int w, int h, exaMarkSync(pDst->drawable.pScreen); return TRUE; @@ -5115,7 +5190,7 @@ index 56de23e..628d2c7 100644 /* Do we need that sync here ? probably not .... */ exaWaitSync(pDst->drawable.pScreen); -@@ -388,13 +504,17 @@ FUNC_NAME(RADEONDownloadFromScreen)(PixmapPtr pSrc, int x, int y, int w, int h, +@@ -388,13 +513,17 @@ FUNC_NAME(RADEONDownloadFromScreen)(PixmapPtr pSrc, int x, int y, int w, int h, TRACE; @@ -5134,7 +5209,7 @@ index 56de23e..628d2c7 100644 RADEONGetPixmapOffsetPitch(pSrc, &src_pitch_offset) && (scratch = RADEONCPGetBuffer(pScrn))) { -@@ -540,17 +660,23 @@ Bool FUNC_NAME(RADEONDrawInit)(ScreenPtr pScreen) +@@ -540,17 +669,23 @@ Bool FUNC_NAME(RADEONDrawInit)(ScreenPtr pScreen) info->exa->MarkSync = FUNC_NAME(RADEONMarkSync); info->exa->WaitMarker = FUNC_NAME(RADEONSync); @@ -5162,7 +5237,7 @@ index 56de23e..628d2c7 100644 #ifdef RENDER if (info->RenderAccel) { -@@ -560,7 +686,7 @@ Bool FUNC_NAME(RADEONDrawInit)(ScreenPtr pScreen) +@@ -560,7 +695,7 @@ Bool FUNC_NAME(RADEONDrawInit)(ScreenPtr pScreen) else if (IS_R300_3D || IS_R500_3D) { if ((info->ChipFamily < CHIP_FAMILY_RS400) #ifdef XF86DRI @@ -5171,7 +5246,7 @@ index 56de23e..628d2c7 100644 #endif ) { xf86DrvMsg(pScrn->scrnIndex, X_INFO, "Render acceleration " -@@ -595,6 +721,16 @@ Bool FUNC_NAME(RADEONDrawInit)(ScreenPtr pScreen) +@@ -595,6 +730,16 @@ Bool FUNC_NAME(RADEONDrawInit)(ScreenPtr pScreen) } #endif @@ -5189,7 +5264,7 @@ index 56de23e..628d2c7 100644 xf86DrvMsg(pScrn->scrnIndex, X_INFO, "Setting EXA maxPitchBytes\n"); diff --git a/src/radeon_exa_render.c b/src/radeon_exa_render.c -index 5d28d80..6426736 100644 +index 043b0d4..456cefe 100644 --- a/src/radeon_exa_render.c +++ b/src/radeon_exa_render.c @@ -410,19 +410,22 @@ static Bool FUNC_NAME(R100TextureSetup)(PicturePtr pPict, PixmapPtr pPix, @@ -5295,7 +5370,7 @@ index 5d28d80..6426736 100644 dst_pitch = exaGetPixmapPitch(pDst); colorpitch = dst_pitch >> pixel_shift; -@@ -1830,9 +1851,18 @@ static Bool FUNC_NAME(R300PrepareComposite)(int op, PicturePtr pSrcPicture, +@@ -1832,9 +1853,18 @@ static Bool FUNC_NAME(R300PrepareComposite)(int op, PicturePtr pSrcPicture, FINISH_ACCEL(); } @@ -5318,10 +5393,10 @@ index 5d28d80..6426736 100644 blendcntl = RADEONGetBlendCntl(op, pMaskPicture, pDstPicture->format); diff --git a/src/radeon_memory.c b/src/radeon_memory.c new file mode 100644 -index 0000000..ccc3bb8 +index 0000000..8a23ccd --- /dev/null +++ b/src/radeon_memory.c -@@ -0,0 +1,424 @@ +@@ -0,0 +1,428 @@ + +#include +#include @@ -5345,6 +5420,10 @@ index 0000000..ccc3bb8 + + int ret; + ++ if (mem->pool == RADEON_POOL_VRAM) ++ pin.pin_domain = RADEON_GEM_DOMAIN_VRAM; ++ else ++ pin.pin_domain = RADEON_GEM_DOMAIN_GTT; + pin.handle = mem->kernel_bo_handle; + pin.alignment = mem->alignment; + @@ -5807,7 +5886,7 @@ index 80333a4..c33632b 100644 +typedef drm_radeon_sarea_t RADEONSAREAPriv, *RADEONSAREAPrivPtr; +#endif diff --git a/src/radeon_textured_video.c b/src/radeon_textured_video.c -index cfa349d..ef05c72 100644 +index da1d60f..9682ad8 100644 --- a/src/radeon_textured_video.c +++ b/src/radeon_textured_video.c @@ -85,6 +85,7 @@ static __inline__ uint32_t F_TO_DW(float val) @@ -5818,23 +5897,23 @@ index cfa349d..ef05c72 100644 #define FINISH_VIDEO() #include "radeon_textured_videofuncs.c" -@@ -93,6 +94,7 @@ static __inline__ uint32_t F_TO_DW(float val) - #undef VIDEO_PREAMBLE +@@ -94,6 +95,7 @@ static __inline__ uint32_t F_TO_DW(float val) #undef BEGIN_VIDEO #undef OUT_VIDEO_REG + #undef OUT_VIDEO_REG_F +#undef OUT_RELOC #undef FINISH_VIDEO #ifdef XF86DRI -@@ -105,6 +107,7 @@ static __inline__ uint32_t F_TO_DW(float val) - #define OUT_VIDEO_REG(reg, val) OUT_RING_REG(reg, val) +@@ -107,6 +109,7 @@ static __inline__ uint32_t F_TO_DW(float val) + #define OUT_VIDEO_REG_F(reg, val) OUT_VIDEO_REG(reg, F_TO_DW(val)) #define FINISH_VIDEO() ADVANCE_RING() #define OUT_VIDEO_RING_F(x) OUT_RING(F_TO_DW(x)) +#define OUT_RELOC(x, read, write) OUT_RING_RELOC(x, read, write) #include "radeon_textured_videofuncs.c" -@@ -179,7 +182,8 @@ RADEONPutImageTextured(ScrnInfoPtr pScrn, +@@ -181,7 +184,8 @@ RADEONPutImageTextured(ScrnInfoPtr pScrn, } #ifdef XF86DRI @@ -5844,7 +5923,7 @@ index cfa349d..ef05c72 100644 /* The upload blit only supports multiples of 64 bytes */ dstPitch = (dstPitch + 63) & ~63; else -@@ -226,8 +230,12 @@ RADEONPutImageTextured(ScrnInfoPtr pScrn, +@@ -240,8 +244,12 @@ RADEONPutImageTextured(ScrnInfoPtr pScrn, left = (x1 >> 16) & ~1; npixels = ((((x2 + 0xffff) >> 16) + 1) & ~1) - left; @@ -5859,7 +5938,7 @@ index cfa349d..ef05c72 100644 pPriv->src_pitch = dstPitch; pPriv->size = size; pPriv->pDraw = pDraw; -@@ -283,7 +291,7 @@ RADEONPutImageTextured(ScrnInfoPtr pScrn, +@@ -301,7 +309,7 @@ RADEONPutImageTextured(ScrnInfoPtr pScrn, pPriv->h = height; #ifdef XF86DRI @@ -5869,11 +5948,11 @@ index cfa349d..ef05c72 100644 else #endif diff --git a/src/radeon_textured_videofuncs.c b/src/radeon_textured_videofuncs.c -index d39f74d..56d71b1 100644 +index b53e114..1e9f3b1 100644 --- a/src/radeon_textured_videofuncs.c +++ b/src/radeon_textured_videofuncs.c -@@ -82,19 +82,19 @@ FUNC_NAME(RADEONDisplayTexturedVideo)(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv - int dstxoff, dstyoff, pixel_shift; +@@ -103,19 +103,19 @@ FUNC_NAME(RADEONDisplayTexturedVideo)(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv + int dstxoff, dstyoff, pixel_shift, vtx_count; BoxPtr pBox = REGION_RECTS(&pPriv->clip); int nBox = REGION_NUM_RECTS(&pPriv->clip); + int qwords; @@ -5895,7 +5974,7 @@ index d39f74d..56d71b1 100644 dst_pitch = pPixmap->devKind; } -@@ -183,13 +183,21 @@ FUNC_NAME(RADEONDisplayTexturedVideo)(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv +@@ -210,13 +210,21 @@ FUNC_NAME(RADEONDisplayTexturedVideo)(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv txoffset = pPriv->src_offset; @@ -5919,12 +5998,12 @@ index d39f74d..56d71b1 100644 FINISH_VIDEO(); txenable = R300_TEX_0_ENABLE; -@@ -408,11 +416,18 @@ FUNC_NAME(RADEONDisplayTexturedVideo)(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv - FINISH_VIDEO(); +@@ -980,11 +988,18 @@ FUNC_NAME(RADEONDisplayTexturedVideo)(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv + } } -- BEGIN_VIDEO(5); -+ qwords = info->new_cs ? 7 : 5; +- BEGIN_VIDEO(6); ++ qwords = info->new_cs ? 8 : 6; + BEGIN_VIDEO(qwords); OUT_VIDEO_REG(R300_TX_INVALTAGS, 0); OUT_VIDEO_REG(R300_TX_ENABLE, txenable); @@ -5940,16 +6019,16 @@ index d39f74d..56d71b1 100644 OUT_VIDEO_REG(R300_RB3D_COLORPITCH0, colorpitch); blendcntl = RADEON_SRC_BLEND_GL_ONE | RADEON_DST_BLEND_GL_ZERO; -@@ -459,6 +474,7 @@ FUNC_NAME(RADEONDisplayTexturedVideo)(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv - RADEON_TEX_0_ENABLE | RADEON_TEX_BLEND_0_ENABLE); +@@ -1029,6 +1044,7 @@ FUNC_NAME(RADEONDisplayTexturedVideo)(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv + RADEON_TEX_0_ENABLE | RADEON_TEX_BLEND_0_ENABLE); OUT_VIDEO_REG(RADEON_RB3D_CNTL, - dst_format | RADEON_ALPHA_BLEND_ENABLE); + dst_format | RADEON_ALPHA_BLEND_ENABLE); + dst_offset += info->fbLocation + pScrn->fbOffset; OUT_VIDEO_REG(RADEON_RB3D_COLOROFFSET, dst_offset); OUT_VIDEO_REG(RADEON_RB3D_COLORPITCH, colorpitch); -@@ -496,7 +512,8 @@ FUNC_NAME(RADEONDisplayTexturedVideo)(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv - ((pPriv->h - 1) << RADEON_TEX_VSIZE_SHIFT)); +@@ -1066,7 +1082,8 @@ FUNC_NAME(RADEONDisplayTexturedVideo)(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv + ((pPriv->h - 1) << RADEON_TEX_VSIZE_SHIFT)); OUT_VIDEO_REG(R200_PP_TXPITCH_0, pPriv->src_pitch - 32); - OUT_VIDEO_REG(R200_PP_TXOFFSET_0, pPriv->src_offset); @@ -5957,22 +6036,22 @@ index d39f74d..56d71b1 100644 + info->fbLocation + pScrn->fbOffset); OUT_VIDEO_REG(R200_PP_TXCBLEND_0, - R200_TXC_ARG_A_ZERO | -@@ -530,7 +547,8 @@ FUNC_NAME(RADEONDisplayTexturedVideo)(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv - RADEON_CLAMP_T_CLAMP_LAST | - RADEON_YUV_TO_RGB); + R200_TXC_ARG_A_ZERO | +@@ -1100,7 +1117,8 @@ FUNC_NAME(RADEONDisplayTexturedVideo)(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv + RADEON_CLAMP_T_CLAMP_LAST | + RADEON_YUV_TO_RGB); OUT_VIDEO_REG(RADEON_PP_TXFORMAT_0, txformat); - OUT_VIDEO_REG(RADEON_PP_TXOFFSET_0, pPriv->src_offset); + OUT_VIDEO_REG(RADEON_PP_TXOFFSET_0, pPriv->src_offset + + info->fbLocation + pScrn->fbOffset); OUT_VIDEO_REG(RADEON_PP_TXCBLEND_0, - RADEON_COLOR_ARG_A_ZERO | - RADEON_COLOR_ARG_B_ZERO | + RADEON_COLOR_ARG_A_ZERO | + RADEON_COLOR_ARG_B_ZERO | diff --git a/src/radeon_video.c b/src/radeon_video.c -index 57dcd8a..ecd34a1 100644 +index e71f0f8..a7ea788 100644 --- a/src/radeon_video.c +++ b/src/radeon_video.c -@@ -275,7 +275,7 @@ void RADEONInitVideo(ScreenPtr pScreen) +@@ -270,7 +270,7 @@ void RADEONInitVideo(ScreenPtr pScreen) memcpy(newAdaptors, adaptors, num_adaptors * sizeof(XF86VideoAdaptorPtr)); adaptors = newAdaptors; @@ -5981,7 +6060,7 @@ index 57dcd8a..ecd34a1 100644 overlayAdaptor = RADEONSetupImageVideo(pScreen); if (overlayAdaptor != NULL) { adaptors[num_adaptors++] = overlayAdaptor; -@@ -288,7 +288,7 @@ void RADEONInitVideo(ScreenPtr pScreen) +@@ -283,7 +283,7 @@ void RADEONInitVideo(ScreenPtr pScreen) if (info->ChipFamily != CHIP_FAMILY_RV250) { if ((info->ChipFamily < CHIP_FAMILY_RS400) #ifdef XF86DRI diff --git a/radeon-suspend-fix.patch b/radeon-suspend-fix.patch deleted file mode 100644 index c2a8b1f..0000000 --- a/radeon-suspend-fix.patch +++ /dev/null @@ -1,32 +0,0 @@ -diff --git a/src/radeon_driver.c b/src/radeon_driver.c -index 1ae6018..1a3b74a 100644 ---- a/src/radeon_driver.c -+++ b/src/radeon_driver.c -@@ -5590,8 +5590,11 @@ Bool RADEONEnterVT(int scrnIndex, int flags) - - } - -- if (info->drm_mm) -+ if (info->drm_mm) { - radeon_bind_all_memory(pScrn); -+ info->XInited3D = FALSE; -+ info->engineMode = EXA_ENGINEMODE_UNKNOWN; -+ } - - radeon_update_dri_buffers(pScrn); - -diff --git a/src/radeon_memory.c b/src/radeon_memory.c -index ccc3bb8..8a23ccd 100644 ---- a/src/radeon_memory.c -+++ b/src/radeon_memory.c -@@ -21,6 +21,10 @@ radeon_bind_memory(ScrnInfoPtr pScrn, struct radeon_memory *mem) - - int ret; - -+ if (mem->pool == RADEON_POOL_VRAM) -+ pin.pin_domain = RADEON_GEM_DOMAIN_VRAM; -+ else -+ pin.pin_domain = RADEON_GEM_DOMAIN_GTT; - pin.handle = mem->kernel_bo_handle; - pin.alignment = mem->alignment; - diff --git a/xorg-x11-drv-ati.spec b/xorg-x11-drv-ati.spec index dea4e0d..649196d 100644 --- a/xorg-x11-drv-ati.spec +++ b/xorg-x11-drv-ati.spec @@ -5,7 +5,7 @@ Summary: Xorg X11 ati video driver Name: xorg-x11-drv-ati Version: 6.9.0 -Release: 15%{?dist} +Release: 16%{?dist} URL: http://www.x.org License: MIT Group: User Interface/X Hardware Support @@ -16,8 +16,6 @@ Source1: radeon.xinf Patch0: radeon-6.9.0-to-git.patch Patch1: radeon-modeset.patch -Patch2: radeon-suspend-fix.patch -Patch3: radeon-fix-pipe-config.patch Patch4: radeon-6.9.0-remove-limit-heuristics.patch Patch5: radeon-6.9.0-panel-size-sanity.patch Patch6: copy-fb-contents.patch @@ -41,8 +39,6 @@ X.Org X11 ati video driver. %setup -q -n %{tarball}-%{version} %patch0 -p1 -b .git %patch1 -p1 -b .modeset -%patch2 -p1 -b .suspend -%patch3 -p1 -b .pipe-config %patch4 -p1 -b .remove-limit-heuristics %patch5 -p1 -b .panel-size %patch6 -p1 -b .copy-fb-contents @@ -77,6 +73,10 @@ rm -rf $RPM_BUILD_ROOT %{_mandir}/man4/radeon.4* %changelog +* Fri Sep 26 2008 Dave Airlie 6.9.0-16 +- rebase to a later tree - still not fully up to git master +- add some fixes to the resize stuff - not fully done + * Fri Sep 19 2008 Kristian Høgsberg - 6.9.0-15 - Add copy-fb-contents.patch to initialize the root window contents with the fbdev contents for slick startup.