From 5ca8881b07e5b4d3d236dd5a7464716a25255720 Mon Sep 17 00:00:00 2001 From: Dave Airlie Date: Mar 03 2009 09:20:16 +0000 Subject: - initial support for dynamic fb resize --- diff --git a/radeon-modeset.patch b/radeon-modeset.patch index 4903060..d2b1231 100644 --- a/radeon-modeset.patch +++ b/radeon-modeset.patch @@ -1,3 +1,895 @@ +commit 00c0032dac820986b84effdb37c5cc1884eabcaf +Author: Dave Airlie +Date: Tue Mar 3 15:30:21 2009 +1000 + + radeon: initial framebuffer resize support + + This relies on the kernel pinning everything which the latest + rawhide kernel should do fine + +commit 354303071be3e40e5cffb97e61d1ec6475ea4685 +Author: Dave Airlie +Date: Tue Mar 3 09:20:30 2009 +1000 + + radeon: do get sarea until we know we aren't DRI2 + +commit 908f5308463b69b89d8b7ff34b2f534fddf0fd77 +Author: Dave Airlie +Date: Tue Mar 3 09:12:30 2009 +1000 + + radeon: no need to do any of this for DRI2 + +commit 0b144608c88ce2dfc265873cd55608f5fbd179bd +Author: Dave Airlie +Date: Fri Feb 27 12:00:29 2009 +1000 + + fixup issues post rebase + +commit d6801eeb38720a7aec7c6392136382a006561a15 +Author: Dave Airlie +Date: Thu Feb 26 10:47:42 2009 +1000 + + radeon: don't init 3d engine in Xv path for drm mm + +commit f49b3d2a3b523cfc0ea3ec10ee1bdfdea0da9423 +Author: Dave Airlie +Date: Tue Feb 17 19:14:27 2009 +1000 + + radeon: fix vt switch for legacy paths + +commit cd0fd2b14d6b732e2852bf93cd4bd4cce79936bf +Author: Dave Airlie +Date: Tue Feb 17 19:13:05 2009 +1000 + + radeon: only init gart heap for non-kms + +commit 6d5fc6d6ca642ceda1351b941955614a792fc5ec +Author: Dave Airlie +Date: Sun Jan 11 09:29:44 2009 +1000 + + radeon: drop CS1 + +commit c1a806452b802f5284a113908109cf810d3b33be +Author: Jerome Glisse +Date: Wed Nov 12 14:36:52 2008 +0100 + + radeon: enable dri2 only if memory manager is present + (cherry picked from commit fd4bb9b7b639befd63e7acd37254011b9e46732d) + +commit 48c2d0902416bfed8a5d768ea1e923b5d34c6320 +Author: Jerome Glisse +Date: Mon Nov 10 22:16:57 2008 +0100 + + radeon: flush command stream in block handler and in dri2 copy callback + (cherry picked from commit 13fa5ab73a707af52e71af400ea186073022f8b7) + +commit 2ea27ca1bf6fa9e96703932981e57b11e653d6a3 +Author: Jerome Glisse +Date: Fri Nov 14 12:44:29 2008 +0100 + + radeon: bufmgr exa doesn't exist + (cherry picked from commit 8a00de47a186db1707b82a5977da8cbf2e8e0c80) + +commit 68b3becc0620c4357872ca034fc6ae5b41432591 +Author: Jerome Glisse +Date: Thu Nov 6 00:25:18 2008 +0100 + + radeon: initial dri2 support + +commit 1190226af0c2685557fe90cb0a5fd3446f31c672 +Author: Dave Airlie +Date: Mon Dec 1 19:15:41 2008 +1000 + + radeno: fixup unpinned buffers + (cherry picked from commit d9759ca976cad48e6c8fd3c7d17ce38588522c34) + +commit eb09bc9aaee774acff6d07cae0018d020ad3ec44 +Author: Dave Airlie +Date: Mon Dec 22 16:16:16 2008 +1000 + + radeon: fix for 1.6 server + +commit 068107ac540d8e7bd1781799fb2b3268f3d9fe34 +Author: Dave Airlie +Date: Fri Dec 19 12:37:01 2008 +1100 + + radeon: only do mappings if direct rendering is enabled + +commit fa8b8dc164393bc43c6f6273aeed50924bc1d6c1 +Author: Dave Airlie +Date: Tue Dec 9 13:29:18 2008 +1000 + + radeon: upstream fix for Init3D vs switch to/from 2d/3d + +commit 77034ccc327b54f2f6c643e3baa9f42477fa221c +Author: Dave Airlie +Date: Mon Dec 8 14:19:47 2008 +1000 + + radeon: only update dri buffers if DRI enabled + +commit 400bc21d00dfe433c3341f8c3be87f15c1b52fae +Author: Dave Airlie +Date: Mon Dec 1 15:31:08 2008 +1100 + + radeon: don't have 2D and 3D in one CS buffer + +commit c25a72d143129b4cd4c8a6c16c27d13b9b173e74 +Author: Dave Airlie +Date: Wed Nov 26 16:09:29 2008 +1100 + + radeon: set touched flag on pinned buffers + +commit 1d2a6732029a80e8c47fc1420186941eb8f210dc +Author: Dave Airlie +Date: Wed Nov 26 16:04:35 2008 +1100 + + radeon: fix up some of the touched by gpu handling and force gtt handling + + this fixes DFS on the rs690 + +commit 434c9f580cb7350510997070b191f3202e88d24b +Author: Dave Airlie +Date: Wed Nov 26 12:52:24 2008 +1100 + + radeon: brutal attempt to fix RS4xx and RS6xx by flushing more often + + this might take more CPU but hopefully leads to stabler GPU + +commit e6b95cd6c312e3ea785956f1d26f65724f66af46 +Author: Dave Airlie +Date: Sun Nov 23 17:56:02 2008 +1000 + + radeon: wait for rendering before doing UTS + +commit a80b03a333c17334400abe0ad65c8eacf203e4e7 +Author: Dave Airlie +Date: Sun Nov 23 17:54:27 2008 +1000 + + radeon: stop this_op_read from going negative + +commit d802c2d18b877b4f45057d550bf8e72136ca6143 +Author: Dave Airlie +Date: Sun Nov 23 17:52:42 2008 +1000 + + radeon: return flush for conflicting domains + +commit c96555c16890ccdb148fb3b84c7544786418a599 +Author: Dave Airlie +Date: Sun Nov 23 17:50:47 2008 +1000 + + radeon: only reset state2d before emitting cache flush + +commit 1c00a7c0b71cbf0161c21f3eab01670717b6fd81 +Author: Dave Airlie +Date: Thu Nov 20 16:48:33 2008 +1000 + + flush on UTS if any references + +commit 77cb0c5b5a1c0c4bcffbcfc0a0c55facdc0aa451 +Author: Dave Airlie +Date: Thu Nov 20 16:44:40 2008 +1000 + + radeon: add gart vs vram writes + +commit cdc160b2aa809f7c6cb6dd47083ea4ca0857eeac +Author: Dave Airlie +Date: Thu Nov 20 16:37:07 2008 +1000 + + radeon: improve DFS performance for non-vram objects + +commit 2ff1aa8bdd2f54b46291ce8b3b9683e01f959c7d +Author: Dave Airlie +Date: Wed Nov 19 14:49:44 2008 +1000 + + radeon: scrap state on LeaveVT not EnterVT + +commit a6023c6f60cb49db2479c9bd9ae1b09cfb5edf0d +Author: Dave Airlie +Date: Wed Nov 19 11:08:34 2008 +1000 + + radeon: even more typos + +commit 754d9743cafbae194e2060e1b119c3b78d0f66e5 +Author: Dave Airlie +Date: Wed Nov 19 07:51:03 2008 +1000 + + radeon: oops bad typo + +commit fb033bc3e6fe02dc98209efef3e5d21c7b885f89 +Author: Dave Airlie +Date: Tue Nov 18 16:09:10 2008 +1000 + + radeon: even if kernels fails, struggle onwards + + try and keep the session going even if visual glitches happen + +commit 5a444b214dc743e6e9eeceb30394a97ed2580cbc +Author: Dave Airlie +Date: Tue Nov 18 15:46:46 2008 +1000 + + radeon_bufmgr: much more complete size check functionality + +commit b64bca1a42abeff57e565f14fbf904329da9ebb5 +Author: Dave Airlie +Date: Tue Nov 18 14:33:44 2008 +1000 + + radeon: I fail at uint32_t division + +commit 551600d7f262f8e6b28d44f8682f2c20e856bc3f +Author: Dave Airlie +Date: Tue Nov 18 12:06:02 2008 +1000 + + radeon: workaround O(wtf) logic in post_submit bufmgr + +commit 960d79a125e983bc547fb308cc200246b20ffeb9 +Author: Dave Airlie +Date: Mon Nov 17 19:19:43 2008 +1000 + + radeon: set emit limit to 90% VRAM + +commit 0906e781b9cdbe6b6aac9e1331c10b258c495768 +Author: Dave Airlie +Date: Mon Nov 17 16:16:51 2008 +1000 + + radeon: use get/set master ioctls + +commit 10dfd9b73060daff0d5a63d108b3bb636d706e50 +Author: Dave Airlie +Date: Fri Nov 14 15:56:16 2008 +1000 + + radeon: make space accounting a lot smarter + +commit 4ea0d643a90c9ad6b9dfc52c3633101c0c1404be +Author: Dave Airlie +Date: Fri Nov 14 15:55:12 2008 +1000 + + radeon: retry on CS2 EAGAIN + +commit 156750c19cbebfde006c6025cee834021b0d591f +Author: Dave Airlie +Date: Fri Nov 14 15:20:59 2008 +1000 + + radeon: add src/mask/dest to fallbacks + +commit fa717f5f9c30af039eb5f6b47f26f63c0942156b +Author: Dave Airlie +Date: Fri Nov 14 15:20:37 2008 +1000 + + radeon_memory: align all allocations + +commit 24f17583021515c6d81d4009f84539a90a491195 +Author: Dave Airlie +Date: Fri Nov 14 11:03:34 2008 +1000 + + radeon: force gtt for mmap after fallbacks + +commit ed019780b9ef897f32d834b12c183d6734d4ecf7 +Author: Dave Airlie +Date: Mon Nov 10 14:18:17 2008 +1000 + + radeon: add more buffer info + fix read objects too big fallback + +commit 76154a56db2c4f86e61bf4310d6ea9bdb0f21ff0 +Author: Dave Airlie +Date: Mon Nov 10 11:47:02 2008 +1000 + + radeon: remove old exa bufmgr not used anymore code + +commit 140f511b2183ead469b61d3ffa71284fdc71b713 +Author: Dave Airlie +Date: Mon Nov 10 11:18:27 2008 +1000 + + radeon: fix crtc dpms + + need to find a better way to switch displays off + +commit 836e48ae2d8a53293d9d687724c0a25c9c5d50b5 +Author: Dave Airlie +Date: Sat Nov 8 14:48:29 2008 +1000 + + radeon: add DPMS support for connectors + +commit 2ffbd858a1f8d9906836ff5c5cdb922910e5c522 +Author: Dave Airlie +Date: Fri Nov 7 16:20:09 2008 +1000 + + radeon: fix rotation of right-of heads + +commit 66e6d3d4f16b10c1b1a1301874a95eefa0a95cbf +Author: Dave Airlie +Date: Mon Nov 3 14:51:43 2008 +1000 + + radeon: respect fb tex percent + trust kernel values + +commit bb967f80e260d5ba84b700cbebdfe83c882e4074 +Author: Dave Airlie +Date: Fri Oct 31 15:05:14 2008 +1000 + + radeon: remove workaround hack since kernel is hopefully fixed + +commit f2ea624ac7f8e397ebb8c2164edf77b90b14f583 +Author: Dave Airlie +Date: Fri Oct 31 15:04:31 2008 +1000 + + radeon: workaround use after free + +commit c39f256cb3f55b8856ff7a0cbbf425340694982f +Author: Dave Airlie +Date: Thu Oct 30 13:53:02 2008 +1000 + + radeon: setup accel dfs for PCIE cards only if drm_mm + +commit 55c6ca51207871f1a713f890b1d9eca0950699ca +Author: Dave Airlie +Date: Thu Oct 30 10:00:10 2008 +1000 + + radeon: fixup name handling for bufmgr + +commit a53e9ae9fdba42ee6d4ea8a8868fe94da5839ed0 +Author: Dave Airlie +Date: Thu Oct 30 09:59:11 2008 +1000 + + radeon: fix memory leak in CS2 code + +commit ffdb167bc74b6fdf1775e04c524d927bd248cac0 +Author: Dave Airlie +Date: Tue Oct 28 20:35:19 2008 +1000 + + return on empty IBs, flush happen in the kernel + +commit da8f605d63de37e7469d25afd3fa3a9f8d1f54b8 +Author: Dave Airlie +Date: Tue Oct 28 10:16:09 2008 +1000 + + radeon: remove some debugging + +commit c98d54139e40bcbe077be5096ef5cc8a9dbf03e7 +Author: Dave Airlie +Date: Tue Oct 28 06:40:31 2008 +1000 + + radeon: enable gem wait rendering. + +commit 3ae5a806eb8e7c4bcc08e214d3fdbdf4386304b6 +Author: Dave Airlie +Date: Mon Oct 27 16:51:00 2008 +1000 + + radeon: add new CS submission scheme + +commit 728361aa97b7fa6c7ca7f6ded9c9bb0b02d2782c +Author: Dave Airlie +Date: Thu Oct 23 17:05:12 2008 +1000 + + radeon: really rough effort at vram limit setting + +commit 03a1797d90ce550a2d5195dcd3a58abff8c7aebb +Author: Dave Airlie +Date: Thu Oct 23 17:04:51 2008 +1000 + + radeon: this shouldn't fail but it did once while debugging so patch up + +commit a0e577f5ab128b310ae00f0cabf072fc067d62b5 +Author: Dave Airlie +Date: Thu Oct 23 10:43:09 2008 +1000 + + radeon: fixup some memory allocation issues + + hopefully since the alignment got fixed this doesn't break anything + +commit e21dcdbeacf60bfebfc82c4119f2ad62e6b94c2f +Author: Dave Airlie +Date: Tue Oct 21 15:50:17 2008 +1000 + + radeon: cleanup reserved space calcs + +commit 37a44646ee3fca050fec56ee6cb6ccd7c3181673 +Author: Dave Airlie +Date: Tue Oct 21 15:49:48 2008 +1000 + + radeon: fixup Owen's optimisation - this fixes corruption + + I haven't a good explaination why mapping the buffer twice in a row + seems to cause this failure. but I probably don't have time to track + it down before release. + +commit e04c58e4f1b5fece2601603dd5d14fdfe92727d2 +Author: Dave Airlie +Date: Sun Oct 19 18:27:53 2008 +1000 + + radeon: fixup tex offset for no modeset + +commit 20521bd438fa3bbc00cc7c131ad143353c922d3d +Author: Dave Airlie +Date: Wed Oct 15 17:01:34 2008 +1000 + + radeon: add DFS support for CS + +commit a72197efa5acb5086ef1aad5596276addefe08ba +Author: airlied +Date: Wed Oct 15 23:55:13 2008 +1000 + + radeon: add r100/r200 support for EXA render + +commit b0afa63afc461fb61fc9a545ad7b31c4bdca28a5 +Author: Dave Airlie +Date: Mon Oct 13 16:59:02 2008 +1000 + + radeon: fix switch mode path so nexuiz starts + +commit 70ef5d335475b1bbab524a842a202b9776051921 +Author: Dave Airlie +Date: Fri Oct 10 15:29:24 2008 +1000 + + remove gem buf caching useless on radeon + +commit a433033f8c6d6d0b9a34689c0387e3043067535f +Author: Dave Airlie +Date: Fri Oct 10 15:18:41 2008 +1000 + + radeon: drmmode make names same as for non-kms drivers + +commit 4b8c3d5cedb4fc1f9872d35ab0b2fc462488e6a3 +Author: Dave Airlie +Date: Fri Oct 10 15:10:28 2008 +1000 + + radeon: fix rotation under kms + +commit 8f68fe2151503466e0e27b1d84c22f445952313e +Author: Dave Airlie +Date: Fri Oct 10 14:44:39 2008 +1000 + + radeon: remove testing fallback + +commit b656b31ac14003b1925656ab4941baff850b37dd +Author: Kristian Høgsberg +Date: Fri Oct 10 10:57:47 2008 +1100 + + radeon: add copy fb contents patch + +commit 5b30500df1595ac9fd4a4ebc555536a3736dc2a0 +Author: Dave Airlie +Date: Fri Oct 10 10:57:20 2008 +1100 + + bufmgr: turn off debug + +commit 15ebeac41bdf7a24389634db16284a0f0e0ff537 +Author: Dave Airlie +Date: Fri Oct 10 10:38:38 2008 +1100 + + radeon: fixup modesetting code after rebasing to master + +commit 8cad0abd7717e4d24201a19dd9921f8a28f8176d +Author: Dave Airlie +Date: Thu Oct 9 16:34:52 2008 +1100 + + radeon: misc cleanups in exa + +commit 4da0198297cd08d7c723a23c7c13beeccbb4d07f +Author: Dave Airlie +Date: Thu Oct 9 16:34:23 2008 +1100 + + radeon: fix UTS for non-modesetting + +commit 4d713860077916e547cec30441766aedd0ec54e5 +Author: Dave Airlie +Date: Thu Oct 9 16:33:59 2008 +1100 + + radeon: fix exa limits problem - shouldn't have been resetting scissor + +commit f4dcb33ab67d884a6cd2e6ad08e7a25870ff4b3a +Author: Dave Airlie +Date: Wed Oct 1 11:21:53 2008 +1000 + + radeon: fixup for latest libdrm changes + +commit 08139fafdc537de8d83054c7e63767b161016f5d +Author: Owen Taylor +Date: Fri Sep 26 16:17:49 2008 -0400 + + Don't flush when mapping a newly created pixmap into system ram If we have a pixmap that has never been mapped into vram (and thus never written to by the GPU), there is no need to flush the graphics pipeline and wait for idle before starting to write to it. + +commit c05eddc144ebc7187417ffa30927f9f1b116b2eb +Author: Dave Airlie +Date: Mon Sep 29 16:32:51 2008 +1000 + + radeon: hopefully fix textured xv + +commit 308d3c763e3e805fc06e4f83aaf6115c4c547b09 +Author: Dave Airlie +Date: Fri Sep 26 11:38:36 2008 +1000 + + radeon: fix the offset checks for command submission + + since we are relocating in the kernel we don't need these + +commit 5b6c1015fbe516d2581a2337e07e0e9b8412746b +Author: Dave Airlie +Date: Fri Sep 26 10:46:20 2008 +1000 + + radeon: fixup after mertge + +commit 5192b6bed534056d160341684b53cec6880eedf5 +Author: Dave Airlie +Date: Fri Sep 26 10:34:41 2008 +1000 + + radeon: fix issues with emitting DST PIPE on cards that don't use it + +commit 7741152ce929278f5768cbafcd3eeb22be84d36d +Author: Dave Airlie +Date: Wed Sep 24 17:12:19 2008 +1000 + + modesetting: fixup bits of drmmode_display.c + +commit 519250b04b5eccd42ac977052f16d29477b6fe45 +Author: Dave Airlie +Date: Wed Sep 24 15:42:01 2008 +1000 + + r600: fixup for kms + +commit a50fc6c938ec6774ce5eb901f957304b792456a4 +Author: Dave Airlie +Date: Sun Sep 7 08:01:56 2008 +1000 + + modeset: fix AddFB for current tree + +commit 1acfa20073823b399d72ab58d69f32b4d4ec2297 +Author: Dave Airlie +Date: Thu Aug 14 10:52:52 2008 +1000 + + radeon: disable overlay for modesetting for now + +commit c981de57577f6ea57ba455a414fc7eb015acfcbf +Author: Dave Airlie +Date: Thu Aug 14 10:52:42 2008 +1000 + + radeon: no need for this anymore + +commit 773fd7a81cd7404c4adcf0f549e710fcc03fca9f +Author: Dave Airlie +Date: Fri Sep 5 16:32:01 2008 +1000 + + radeon: fix up for suspend/resume - uses new API + +commit bbb87f49273cc12f366506ba52d976eefd4690f5 +Author: Dave Airlie +Date: Wed Aug 27 13:09:55 2008 +1000 + + radeon: update to proper domain + + this should fix 3d again for now at least + +commit 0dd982c1e3263a8e39c5ea9a6fe254275217725c +Author: Dave Airlie +Date: Tue Aug 26 18:29:23 2008 +1000 + + ddx: move to using new gem interface + + add a GEM bufmgr backend along the lines of Intels one. + + The buffer reuse is disabled and I'll probably rip it out for radeon + as we can't just re-use buffers that might have ended up in VRAM etc. + + Probably need some sort of in-kernel re-use. + +commit 0cc73177663be1897fbdaab57d6903dae7f6df1b +Author: Dave Airlie +Date: Mon Aug 25 11:37:48 2008 +1000 + + radeon: add an initial GEM bufmgr + +commit 5fef64ad52b7e91ea0e416b9d4e6d2c829ae8f07 +Author: Dave Airlie +Date: Mon Aug 25 11:37:20 2008 +1000 + + radeon: implement simple UTS + +commit 55565e480631ce30e1abfaf6e3220001006383fb +Author: Dave Airlie +Date: Fri Aug 22 15:34:58 2008 +1000 + + radeon: add read/write domains properly + +commit 5d318501c57643513a95622a6e795f0e305d7b48 +Author: Dave Airlie +Date: Fri Aug 15 11:25:31 2008 +1000 + + radeon: fix some rotate bugs + +commit 6671103f8e609d608c882c27de26b2f803c8edc2 +Author: Dave Airlie +Date: Fri Aug 15 11:16:18 2008 +1000 + + radeon: when create fake bos, they are already mapped + +commit 77b2173406ed875e8196fb734c2d1cdce582af1c +Author: Dave Airlie +Date: Fri Aug 15 11:15:58 2008 +1000 + + exa: remove wrong assert + +commit 750aca4cdc9f2d324a5d23c350a217261d3f5d84 +Author: Dave Airlie +Date: Tue Aug 12 19:27:44 2008 +1000 + + radeon: start to work on rotate pixmap support + +commit 927b541d3ef8c01887677dda54689ea2c38872bd +Author: Dave Airlie +Date: Tue Aug 12 18:28:23 2008 +1000 + + radeon: port simple exa bufmgr + + exa pixmaps work now but they are slow + +commit 09472769aa55bda09be76afd0fda1b1eb713a95c +Author: Dave Airlie +Date: Thu Aug 7 17:52:04 2008 +1000 + + further pixmaps on EXA + +commit 0c2079cc5c3ecdbd9a2b77103546540b22ad581e +Author: Dave Airlie +Date: Thu Aug 7 11:22:46 2008 +1000 + + initial exa on gem hackx + + Conflicts: + + src/radeon_exa.c + src/radeon_memory.c + +commit 77d86019b6881ac49c2a3397aaf6ff13ceae8f3d +Author: Dave Airlie +Date: Tue Aug 12 15:31:03 2008 +1000 + + radeon: initial rotate pixmap + + This doesn't work, we really need EXA pixmaps for this stuff + +commit aa89d1e78d34f4d9f86442135ebaa8b1b353b000 +Author: Dave Airlie +Date: Tue Aug 12 14:40:18 2008 +1000 + + radeon: use buffer names + +commit 47b650b53ca9cbf1298717ea49849a98f75ada55 +Author: Dave Airlie +Date: Tue Aug 12 14:38:56 2008 +1000 + + ati: fix do adjust mode + +commit 9aa2c37674e7e92a590f55f671aebf969b5a2653 +Author: Dave Airlie +Date: Tue Aug 12 09:38:48 2008 +1000 + + FEDORA: update offsets in DRI private + +commit 4a803ac551df2c84174faeaf45d9fcb35215dc95 +Author: Dave Airlie +Date: Tue Aug 12 09:10:18 2008 +1000 + + radeon: add vt bind flag + +commit 2dc1897cf0cf90ea7eea39ee70f10b0fccfef0a2 +Author: Dave Airlie +Date: Wed Aug 6 13:30:54 2008 +1000 + + radeon: warning cleanups + +commit f25d18044a08ecd451585162fe8d51129cbd65c8 +Author: Dave Airlie +Date: Wed Aug 6 13:18:52 2008 +1000 + + radeon: remove debugging + +commit 963d1a62cf51b834183dab1d3312ef20262c2ec4 +Author: Dave Airlie +Date: Wed Aug 6 13:17:31 2008 +1000 + + radeon: add code to set memory map and not futz with mappings + +commit 03c3c7aeff5108917a2d4283c1715f03c3f3b41d +Author: Dave Airlie +Date: Wed Aug 6 13:16:56 2008 +1000 + + drm: don't futz with framebuffer when no drm_mm + +commit 3b5773862110a7513801d1cd8929f5c33cb44208 +Author: Dave Airlie +Date: Tue Aug 5 16:47:21 2008 +1000 + + radeon: undef OUT_RELOC + +commit 55b5e2297b40ad4b296d91ce7d8520ec19cedbea +Author: Dave Airlie +Date: Tue Aug 5 16:37:52 2008 +1000 + + radeon: add stdint/lib to check for modesetting + +commit 0b515d8f217583ce432715b5d3abc8468597f60c +Author: Dave Airlie +Date: Tue Aug 5 16:07:31 2008 +1000 + + fix whitespace + +commit 6b492d113905257a1b12586eafb93a1c21649dfd +Author: Dave Airlie +Date: Tue Aug 5 16:07:07 2008 +1000 + + radeon: fix build issue + +commit c9ff3947e40716847fe1ce0187c83c073ba4d9c8 +Author: Dave Airlie +Date: Mon Aug 4 16:27:55 2008 +1000 + + radeon: free all pinned memory on server shutdown + +commit 8872b1bdc623eaccb746862d4e2d881afb1c3923 +Author: Dave Airlie +Date: Mon Aug 4 16:11:30 2008 +1000 + + radeon: get textured video working on the memory manager + +commit bf51c8f1d2023eec5ce9b621c3c2caf6ffc11cc8 +Author: Dave Airlie +Date: Mon Aug 4 16:11:18 2008 +1000 + + radeon: convert bus addr to void pointer + +commit e616681225088fdb6784c1df4cbbfa63b4d3bc1d +Author: Dave Airlie +Date: Mon Aug 4 15:11:13 2008 +1000 + + radeon: avoid z cache flushes if not needed + +commit efec614d5a5cab051968810a10f5dc1620a42146 +Author: Dave Airlie +Date: Wed Jul 30 17:04:22 2008 +1000 + + radeon: update DRI support, so mappings get added + + We only add fake frontbuffer mapping as DRI clients expect one. + +commit 23c37b78d7af1874e5a63251eb44231e91b8300c +Author: Dave Airlie +Date: Tue Jul 29 16:50:03 2008 +1000 + + radeon: exa through the handle relocation function + +commit d0527a52ee83562b442b006a59eb03f41c4889a5 +Author: Dave Airlie +Date: Tue Jul 29 14:58:22 2008 +1000 + + radeon: keep track of 2D state + + This lets the kernel use the 2D blit engine in theory + +commit 0d9dcbc26f04a606c498b47d1c0228a6906b9518 +Author: Dave Airlie +Date: Mon Jul 28 17:48:59 2008 +1000 + + new command submission attempt + +commit 69ce5d53c186bbd3dce93909e94f12855e6b296e +Author: Dave Airlie +Date: Mon Jul 28 17:48:08 2008 +1000 + + radeon: fixup over fluishing problem + +commit d92685f8f9bb7e240822bbdd1a1d2424542b7d50 +Author: Dave Airlie +Date: Mon Jul 28 17:44:51 2008 +1000 + + hack for now: divide texture size by 2 + +commit 2c0ce08b8e2e32e4cbaf6f4271ab95369da73954 +Author: Dave Airlie +Date: Fri Jul 25 17:07:20 2008 +1000 + + radeon: fix dri message + +commit 769fdab086f42d64cacf73fc07175a6811d6e3dd +Author: Dave Airlie +Date: Fri Jul 25 15:11:58 2008 +1000 + + radeon: fix pool which caused memory corruption + +commit 79ae58c84558ef4ad3c021f842b16c8621eb7d20 +Author: Dave Airlie +Date: Fri Jul 25 14:59:07 2008 +1000 + + radeon: get DRI to attempt to start up + +commit 80fae5b9af8b8d7a4907fae2d607668170de8d85 +Author: Dave Airlie +Date: Fri Jul 25 14:58:23 2008 +1000 + + radeon: call the right sync function + +commit 50497f43feb52ffc0cfa1420a6509e15b0bd2a82 +Author: Dave Airlie +Date: Fri Jul 25 14:57:21 2008 +1000 + + radeon: unmap memory from objects + +commit 02e4a3ab2f955415ca1b52f0c860d54edb60d99e +Author: Dave Airlie +Date: Wed Jul 23 10:59:16 2008 +1000 + + use CP for 3D engine with modeset + +commit b7c23b09e1ced1b36cafeb150c58605a4c7699c4 +Author: Dave Airlie +Date: Wed Jul 23 10:59:04 2008 +1000 + + radeon: fix DFS + +commit e3a5ff240714ea5871e95f2a8ba74c3419cf6bb7 +Author: Dave Airlie +Date: Wed Jul 23 10:48:45 2008 +1000 + + radeon: get the fb location right + +commit 2cb38725c09f6c80cdf7ef0db95e065f74a57cf4 +Author: Dave Airlie +Date: Tue Jul 22 18:08:25 2008 +1000 + + radeon: make at least the EXA stipple work.. + +commit bcf36a6c8360fcec90d2430d58b6ac8e282b57f8 +Author: Dave Airlie +Date: Tue Jul 22 18:07:15 2008 +1000 + + radeon: disable debugging for now + +commit 2598b49272cffc937bb2c449868d2e0dd2c4d719 +Author: Dave Airlie +Date: Mon Jul 21 18:40:14 2008 +1000 + + radeon: initial indirect buffer use. + + Move EXA and front allocation into one big buffer to workaround + EXA issues - need to move to driver pixmap hooks. + + Add new indirect GEM to take indirect buffers. + + doesn't work think the offsets are all wrong. + +commit 4a91206107a218747bea080f721dce253638eac4 +Author: Dave Airlie +Date: Fri Jul 18 13:46:41 2008 +1000 + + modesetting step 1: have X and a cursor + +commit 9a7fbdd2ccb4073f7cbcc48e8d65d430cbb08b3a +Author: Dave Airlie +Date: Thu Jul 17 09:59:19 2008 +1000 + + radeon: add radeon_memory.c + +commit e516b7612d2fcfe115306f8de049feebe463a0fd +Author: Dave Airlie +Date: Tue Jul 8 16:55:27 2008 +1000 + + remove mappings of some buffers. + + use drm gart code if available + +commit 2e0da77a17f9c6767a602e09ed60a5de91f3e5cb +Author: Dave Airlie +Date: Mon Jul 7 16:54:35 2008 +1000 + + add initial support for a kernel memory manager + + This just pins all the current allocations via the kernel memory manager + instead of trying to do them all in userspace. + + useful steps towards getting kernel modesetting + +commit a4a1143fbfd783a9278c8b9aa7997011c9f4852f +Author: Dave Airlie +Date: Fri Jul 4 10:39:34 2008 +1000 + + port to using drm header files diff --git a/configure.ac b/configure.ac index b094a50..29a19e3 100644 --- a/configure.ac @@ -61,10 +953,10 @@ index 7cc2a6f..8a55d1c 100644 + radeon_dri_bufmgr.h diff --git a/src/drmmode_display.c b/src/drmmode_display.c new file mode 100644 -index 0000000..69d82ea +index 0000000..84f5f0a --- /dev/null +++ b/src/drmmode_display.c -@@ -0,0 +1,864 @@ +@@ -0,0 +1,905 @@ +/* + * Copyright © 2007 Red Hat, Inc. + * @@ -106,23 +998,6 @@ index 0000000..69d82ea +#define DPMS_SERVER +#include + -+static Bool drmmode_resize_fb(ScrnInfoPtr scrn, drmmode_ptr drmmode, int width, int height); -+ -+static Bool -+drmmode_xf86crtc_resize (ScrnInfoPtr scrn, int width, int height) -+{ -+ xf86CrtcConfigPtr xf86_config = XF86_CRTC_CONFIG_PTR(scrn); -+ drmmode_crtc_private_ptr drmmode_crtc = xf86_config->crtc[0]->driver_private; -+ drmmode_ptr drmmode = drmmode_crtc->drmmode; -+ Bool ret; -+ -+ ErrorF("resize called %d %d\n", width, height); -+ ret = drmmode_resize_fb(scrn, drmmode, width, height); -+ scrn->virtualX = width; -+ scrn->virtualY = height; -+ return TRUE; -+} -+ +static void +drmmode_ConvertFromKMode(ScrnInfoPtr scrn, + struct drm_mode_modeinfo *kmode, @@ -182,10 +1057,6 @@ index 0000000..69d82ea + +} + -+static const xf86CrtcConfigFuncsRec drmmode_xf86crtc_config_funcs = { -+ drmmode_xf86crtc_resize -+}; -+ +static void +drmmode_crtc_dpms(xf86CrtcPtr crtc, int mode) +{ @@ -730,6 +1601,102 @@ index 0000000..69d82ea + return; +} + ++static Bool ++drmmode_xf86crtc_resize (ScrnInfoPtr scrn, int width, int height) ++{ ++ xf86CrtcConfigPtr xf86_config = XF86_CRTC_CONFIG_PTR(scrn); ++ drmmode_crtc_private_ptr ++ drmmode_crtc = xf86_config->crtc[0]->driver_private; ++ drmmode_ptr drmmode = drmmode_crtc->drmmode; ++ RADEONInfoPtr info = RADEONPTR(scrn); ++ struct radeon_memory *old_front = NULL; ++ BoxRec mem_box; ++ Bool tiled, ret; ++ ScreenPtr screen = screenInfo.screens[scrn->scrnIndex]; ++ uint32_t old_fb_id; ++ int i, pitch, old_width, old_height, old_pitch; ++ int screen_size; ++ int cpp = info->CurrentLayout.pixel_bytes; ++ dri_bo *front_bo; ++ ++ if (scrn->virtualX == width && scrn->virtualY == height) ++ return TRUE; ++ ++ front_bo = radeon_get_pixmap_bo(screen->GetScreenPixmap(screen)); ++ RADEONCPFlushIndirect(scrn, 0); ++ ++ if (front_bo) ++ radeon_bufmgr_gem_wait_rendering(front_bo); ++ pitch = RADEON_ALIGN(width, 63); ++ height = RADEON_ALIGN(height, 16); ++ ++ screen_size = pitch * height * cpp; ++ ++ xf86DrvMsg(scrn->scrnIndex, X_INFO, ++ "Allocate new frame buffer %dx%d stride %d\n", ++ width, height, pitch); ++ ++ old_width = scrn->virtualX; ++ old_height = scrn->virtualY; ++ old_pitch = scrn->displayWidth; ++ old_fb_id = drmmode->fb_id; ++ old_front = info->mm.front_buffer; ++ ++ scrn->virtualX = width; ++ scrn->virtualY = height; ++ scrn->displayWidth = pitch; ++ info->mm.front_buffer = radeon_allocate_memory(scrn, RADEON_POOL_VRAM, screen_size, 0, 1, "Front Buffer", 0); ++ if (!info->mm.front_buffer) ++ goto fail; ++ ++ ret = drmModeAddFB(drmmode->fd, width, height, scrn->depth, ++ scrn->bitsPerPixel, pitch * cpp, ++ info->mm.front_buffer->kernel_bo_handle, ++ &drmmode->fb_id); ++ if (ret) ++ goto fail; ++ ++ radeon_set_pixmap_bo(screen->GetScreenPixmap(screen), info->mm.front_buffer); ++ screen->ModifyPixmapHeader(screen->GetScreenPixmap(screen), ++ width, height, -1, -1, pitch * cpp, NULL); ++ ++ xf86DrvMsg(scrn->scrnIndex, X_INFO, "New front buffer at 0x%lx\n", ++ info->mm.front_buffer->offset); ++ ++ for (i = 0; i < xf86_config->num_crtc; i++) { ++ xf86CrtcPtr crtc = xf86_config->crtc[i]; ++ ++ if (!crtc->enabled) ++ continue; ++ ++ drmmode_set_mode_major(crtc, &crtc->mode, ++ crtc->rotation, crtc->x, crtc->y); ++ } ++ ++ if (old_fb_id) ++ drmModeRmFB(drmmode->fd, old_fb_id); ++ if (old_front) ++ radeon_free_memory(scrn, old_front); ++ ++ return TRUE; ++ ++ fail: ++ if (info->mm.front_buffer) ++ radeon_free_memory(scrn, info->mm.front_buffer); ++ info->mm.front_buffer = old_front; ++ scrn->virtualX = old_width; ++ scrn->virtualY = old_height; ++ scrn->displayWidth = old_pitch; ++ drmmode->fb_id = old_fb_id; ++ ++ return FALSE; ++} ++ ++static const xf86CrtcConfigFuncsRec drmmode_xf86crtc_config_funcs = { ++ drmmode_xf86crtc_resize ++}; ++ ++ +Bool drmmode_pre_init(ScrnInfoPtr pScrn, drmmode_ptr drmmode, char *busId, char *driver_name, int cpp) +{ + xf86CrtcConfigPtr xf86_config; @@ -763,7 +1730,7 @@ index 0000000..69d82ea + for (i = 0; i < drmmode->mode_res->count_connectors; i++) + drmmode_output_init(pScrn, drmmode, i); + -+ xf86InitialConfiguration(pScrn, FALSE); ++ xf86InitialConfiguration(pScrn, TRUE); + + return TRUE; +} @@ -829,40 +1796,6 @@ index 0000000..69d82ea + +} + -+static Bool drmmode_resize_fb(ScrnInfoPtr scrn, drmmode_ptr drmmode, int width, int height) -+{ -+ uint32_t handle; -+ int pitch; -+ int ret; -+ -+ return FALSE; -+ -+ if (drmmode->mode_fb->width == width && drmmode->mode_fb->height == height) -+ return TRUE; -+ -+ if (!drmmode->create_new_fb) -+ return FALSE; -+ -+ handle = drmmode->create_new_fb(scrn, width, height, &pitch); -+ if (handle == 0) -+ return FALSE; -+ -+ ret = drmModeReplaceFB(drmmode->fd, drmmode->fb_id, -+ width, height, -+ scrn->depth, scrn->bitsPerPixel, pitch, -+ handle); -+ -+ if (ret) -+ return FALSE; -+ -+ drmModeFreeFB(drmmode->mode_fb); -+ drmmode->mode_fb = drmModeGetFB(drmmode->fd, drmmode->fb_id); -+ if (!drmmode->mode_fb) -+ return FALSE; -+ -+ return TRUE; -+} -+ +void drmmode_adjust_frame(ScrnInfoPtr pScrn, drmmode_ptr drmmode, int x, int y, int flags) +{ + xf86CrtcConfigPtr config = XF86_CRTC_CONFIG_PTR(pScrn); @@ -931,10 +1864,10 @@ index 0000000..69d82ea +#endif diff --git a/src/drmmode_display.h b/src/drmmode_display.h new file mode 100644 -index 0000000..dbb6412 +index 0000000..5ea904b --- /dev/null +++ b/src/drmmode_display.h -@@ -0,0 +1,76 @@ +@@ -0,0 +1,74 @@ +/* + * Copyright © 2007 Red Hat, Inc. + * @@ -978,8 +1911,6 @@ index 0000000..dbb6412 + drmModeFBPtr mode_fb; + int cpp; + dri_bufmgr *bufmgr; -+ -+ uint32_t (*create_new_fb)(ScrnInfoPtr pScrn, int width, int height, int *pitch); +} drmmode_rec, *drmmode_ptr; + +typedef struct { @@ -1012,7 +1943,7 @@ index 0000000..dbb6412 +#endif +#endif diff --git a/src/radeon.h b/src/radeon.h -index 355a949..9cdc12a 100644 +index 355a949..21118d7 100644 --- a/src/radeon.h +++ b/src/radeon.h @@ -46,6 +46,8 @@ @@ -1126,7 +2057,7 @@ index 355a949..9cdc12a 100644 #ifdef USE_EXA Bool accelDFS; #endif -@@ -884,6 +920,44 @@ typedef struct { +@@ -884,6 +920,45 @@ typedef struct { int virtualX; int virtualY; @@ -1167,11 +2098,12 @@ index 355a949..9cdc12a 100644 + drmmode_rec drmmode; +#endif + ++ int can_resize; + dri_bufmgr *bufmgr; } RADEONInfoRec, *RADEONInfoPtr; #define RADEONWaitForFifo(pScrn, entries) \ -@@ -1136,6 +1210,23 @@ extern void +@@ -1136,6 +1211,23 @@ extern void radeon_legacy_free_memory(ScrnInfoPtr pScrn, void *mem_struct); @@ -1181,7 +2113,6 @@ index 355a949..9cdc12a 100644 +extern Bool radeon_unbind_all_memory(ScrnInfoPtr pScrn); +extern struct radeon_memory *radeon_allocate_memory(ScrnInfoPtr pScrn, int pool, int size, int alignment, Bool no_backing_store, char *name, + int need_bind); -+uint32_t radeon_create_new_fb(ScrnInfoPtr pScrn, int width, int height, int *pitch); +int radeon_map_memory(ScrnInfoPtr pScrn, struct radeon_memory *mem); +void radeon_unmap_memory(ScrnInfoPtr pScrn, struct radeon_memory *mem); +void radeon_free_memory(ScrnInfoPtr pScrn, struct radeon_memory *mem); @@ -1190,12 +2121,13 @@ index 355a949..9cdc12a 100644 +Bool radeon_setup_kernel_mem(ScreenPtr pScreen); +Bool RADEONDRIDoMappings(ScreenPtr pScreen); +Bool radeon_update_dri_buffers(ScreenPtr pScreen); -+Bool radeon_setup_gart_mem(ScreenPtr pScreen); + ++dri_bo *radeon_get_pixmap_bo(PixmapPtr pPix); ++void radeon_set_pixmap_bo(PixmapPtr pPix, struct radeon_memory *mem); #ifdef XF86DRI # ifdef USE_XAA /* radeon_accelfuncs.c */ -@@ -1154,7 +1245,9 @@ do { \ +@@ -1154,7 +1246,9 @@ do { \ #define RADEONCP_RELEASE(pScrn, info) \ do { \ @@ -1206,7 +2138,7 @@ index 355a949..9cdc12a 100644 RADEON_PURGE_CACHE(); \ RADEON_WAIT_UNTIL_IDLE(); \ RADEONCPReleaseIndirect(pScrn); \ -@@ -1189,7 +1282,7 @@ do { \ +@@ -1189,7 +1283,7 @@ do { \ #define RADEONCP_REFRESH(pScrn, info) \ do { \ @@ -1215,7 +2147,7 @@ index 355a949..9cdc12a 100644 if (info->cp->needCacheFlush) { \ RADEON_PURGE_CACHE(); \ RADEON_PURGE_ZCACHE(); \ -@@ -1216,6 +1309,13 @@ do { \ +@@ -1216,6 +1310,13 @@ do { \ #define RING_LOCALS uint32_t *__head = NULL; int __expected; int __count = 0 #define BEGIN_RING(n) do { \ @@ -1229,7 +2161,7 @@ index 355a949..9cdc12a 100644 if (RADEON_VERBOSE) { \ xf86DrvMsg(pScrn->scrnIndex, X_INFO, \ "BEGIN_RING(%d) in %s\n", (unsigned int)n, __FUNCTION__);\ -@@ -1228,13 +1328,6 @@ do { \ +@@ -1228,13 +1329,6 @@ do { \ } \ info->cp->dma_debug_func = __FILE__; \ info->cp->dma_debug_lineno = __LINE__; \ @@ -1243,7 +2175,7 @@ index 355a949..9cdc12a 100644 __expected = n; \ __head = (pointer)((char *)info->cp->indirectBuffer->address + \ info->cp->indirectBuffer->used); \ -@@ -1277,6 +1370,14 @@ do { \ +@@ -1277,6 +1371,14 @@ do { \ OUT_RING(val); \ } while (0) @@ -1648,10 +2580,10 @@ index 0000000..481c5cf +#endif diff --git a/src/radeon_bufmgr_gem.c b/src/radeon_bufmgr_gem.c new file mode 100644 -index 0000000..6cf13ba +index 0000000..a2fd61a --- /dev/null +++ b/src/radeon_bufmgr_gem.c -@@ -0,0 +1,666 @@ +@@ -0,0 +1,668 @@ +/************************************************************************** + * + * Copyright © 2007-2008 Red Hat Inc. @@ -2310,11 +3242,13 @@ index 0000000..6cf13ba + int r; + + flink.handle = gem_bo->gem_handle; ++ fprintf(stderr,"naming attemp %d\n", flink.handle); + r = ioctl(bufmgr_gem->fd, DRM_IOCTL_GEM_FLINK, &flink); + if (r) { + DBG("[drm] failed to name buffer %d\n", -errno); + return r; + } ++ fprintf(stderr,"naming %d with %d\n", flink.handle, flink.name); + *name = flink.name; + return 0; +} @@ -2481,7 +3415,7 @@ index 0fcdcf0..49601cf 100644 xf86CrtcPtr crtc = xf86_config->crtc[c]; RADEONCrtcPrivatePtr radeon_crtc = crtc->driver_private; diff --git a/src/radeon_dri.c b/src/radeon_dri.c -index 45f79ed..0b1f7d8 100644 +index 45f79ed..318ebc0 100644 --- a/src/radeon_dri.c +++ b/src/radeon_dri.c @@ -40,6 +40,8 @@ @@ -2878,8 +3812,8 @@ index 45f79ed..0b1f7d8 100644 info->dri->pKernelDRMVersion = NULL; - return FALSE; + goto fail; - } - ++ } ++ + if (info->dri->pKernelDRMVersion->version_minor >= 30) { + struct drm_radeon_gem_info mminfo; + @@ -2893,8 +3827,8 @@ index 45f79ed..0b1f7d8 100644 + ErrorF("initing %llx %llx %llx %llx\n", mminfo.gart_start, + mminfo.gart_size, mminfo.vram_start, mminfo.vram_size); + } -+ } -+ + } + + drmClose(fd); return TRUE; +fail: @@ -2913,7 +3847,7 @@ index 45f79ed..0b1f7d8 100644 if (!info->want_vblank_interrupts) on = FALSE; -@@ -1510,6 +1705,48 @@ Bool RADEONDRISetVBlankInterrupt(ScrnInfoPtr pScrn, Bool on) +@@ -1510,6 +1705,52 @@ Bool RADEONDRISetVBlankInterrupt(ScrnInfoPtr pScrn, Bool on) return TRUE; } @@ -2930,6 +3864,10 @@ index 45f79ed..0b1f7d8 100644 + if (info->ChipFamily >= CHIP_FAMILY_R600) + return TRUE; + ++ if (info->dri2.enabled) ++ return TRUE; ++ ++ pSAREAPriv = DRIGetSAREAPrivate(pScreen); + if (!RADEONDRIMapInit(info, pScreen)) { + RADEONDRICloseScreen(pScreen); + return FALSE; @@ -2962,7 +3900,7 @@ index 45f79ed..0b1f7d8 100644 /* Initialize the screen-specific data structures for the DRI and the * Radeon. This is the main entry point to the device-specific -@@ -1573,10 +1810,22 @@ Bool RADEONDRIScreenInit(ScreenPtr pScreen) +@@ -1573,10 +1814,22 @@ Bool RADEONDRIScreenInit(ScreenPtr pScreen) pDRIInfo->ddxDriverMajorVersion = info->allowColorTiling ? 5 : 4; pDRIInfo->ddxDriverMinorVersion = 3; pDRIInfo->ddxDriverPatchVersion = 0; @@ -2989,7 +3927,7 @@ index 45f79ed..0b1f7d8 100644 pDRIInfo->ddxDrawableTableEntry = RADEON_MAX_DRAWABLES; pDRIInfo->maxDrawableTableEntry = (SAREA_MAX_DRAWABLES < RADEON_MAX_DRAWABLES -@@ -1629,9 +1878,7 @@ Bool RADEONDRIScreenInit(ScreenPtr pScreen) +@@ -1629,9 +1882,7 @@ Bool RADEONDRIScreenInit(ScreenPtr pScreen) pDRIInfo->TransitionTo3d = RADEONDRITransitionTo3d; pDRIInfo->TransitionSingleToMulti3D = RADEONDRITransitionSingleToMulti3d; pDRIInfo->TransitionMultiToSingle3D = RADEONDRITransitionMultiToSingle3d; @@ -3000,7 +3938,7 @@ index 45f79ed..0b1f7d8 100644 pDRIInfo->ClipNotify = RADEONDRIClipNotify; #endif -@@ -1663,57 +1910,60 @@ Bool RADEONDRIScreenInit(ScreenPtr pScreen) +@@ -1663,57 +1914,60 @@ Bool RADEONDRIScreenInit(ScreenPtr pScreen) pDRIInfo = NULL; return FALSE; } @@ -3105,7 +4043,7 @@ index 45f79ed..0b1f7d8 100644 static Bool RADEONDRIDoCloseScreen(int scrnIndex, ScreenPtr pScreen) { ScrnInfoPtr pScrn = xf86Screens[pScreen->myNum]; -@@ -1755,17 +2005,21 @@ Bool RADEONDRIFinishScreenInit(ScreenPtr pScreen) +@@ -1755,17 +2009,21 @@ Bool RADEONDRIFinishScreenInit(ScreenPtr pScreen) return FALSE; } @@ -3135,7 +4073,7 @@ index 45f79ed..0b1f7d8 100644 /* Initialize and start the CP if required */ RADEONDRICPInit(pScrn); -@@ -1774,6 +2028,10 @@ Bool RADEONDRIFinishScreenInit(ScreenPtr pScreen) +@@ -1774,6 +2032,10 @@ Bool RADEONDRIFinishScreenInit(ScreenPtr pScreen) pSAREAPriv = (drm_radeon_sarea_t*)DRIGetSAREAPrivate(pScreen); memset(pSAREAPriv, 0, sizeof(*pSAREAPriv)); @@ -3146,7 +4084,7 @@ index 45f79ed..0b1f7d8 100644 pRADEONDRI = (RADEONDRIPtr)info->dri->pDRIInfo->devPrivate; pRADEONDRI->deviceID = info->Chipset; -@@ -1931,6 +2189,8 @@ void RADEONDRICloseScreen(ScreenPtr pScreen) +@@ -1931,6 +2193,8 @@ void RADEONDRICloseScreen(ScreenPtr pScreen) drmUnmap(info->dri->buf, info->dri->bufMapSize); info->dri->buf = NULL; } @@ -3155,7 +4093,7 @@ index 45f79ed..0b1f7d8 100644 if (info->dri->ringReadPtr) { drmUnmap(info->dri->ringReadPtr, info->dri->ringReadMapSize); info->dri->ringReadPtr = NULL; -@@ -1939,6 +2199,7 @@ void RADEONDRICloseScreen(ScreenPtr pScreen) +@@ -1939,6 +2203,7 @@ void RADEONDRICloseScreen(ScreenPtr pScreen) drmUnmap(info->dri->ring, info->dri->ringMapSize); info->dri->ring = NULL; } @@ -3163,7 +4101,7 @@ index 45f79ed..0b1f7d8 100644 if (info->dri->agpMemHandle != DRM_AGP_NO_HANDLE) { drmAgpUnbind(info->dri->drmFD, info->dri->agpMemHandle); drmAgpFree(info->dri->drmFD, info->dri->agpMemHandle); -@@ -2344,3 +2605,16 @@ int RADEONDRISetParam(ScrnInfoPtr pScrn, unsigned int param, int64_t value) +@@ -2344,3 +2609,11 @@ int RADEONDRISetParam(ScrnInfoPtr pScrn, unsigned int param, int64_t value) &radeonsetparam, sizeof(drm_radeon_setparam_t)); return ret; } @@ -3174,11 +4112,6 @@ index 45f79ed..0b1f7d8 100644 + RADEONInfoPtr info = RADEONPTR(pScrn); + + RADEONDRIInitGARTValues(info); -+ -+ /* so we want to allocate the buffers/gart texmap */ -+ /* ignore ring stuff */ -+ return radeon_setup_gart_mem(pScreen); -+ +} diff --git a/src/radeon_dri2.c b/src/radeon_dri2.c new file mode 100644 @@ -3939,7 +4872,7 @@ index 0000000..a19d7ec + +#endif diff --git a/src/radeon_driver.c b/src/radeon_driver.c -index 7cac321..dbdae69 100644 +index 7cac321..b65bb51 100644 --- a/src/radeon_driver.c +++ b/src/radeon_driver.c @@ -67,7 +67,7 @@ @@ -3963,7 +4896,21 @@ index 7cac321..dbdae69 100644 } static Bool RADEONCreateScreenResources (ScreenPtr pScreen) -@@ -1625,6 +1628,7 @@ static Bool RADEONPreInitVRAM(ScrnInfoPtr pScrn) +@@ -246,6 +249,13 @@ RADEONCreateScreenResources (ScreenPtr pScreen) + radeonShadowWindow, 0, NULL)) + return FALSE; + } ++ ++ if (info->dri2.enabled) { ++ if (info->mm.front_buffer->kernel_bo_handle) { ++ PixmapPtr pPix = pScreen->GetScreenPixmap(pScreen); ++ radeon_set_pixmap_bo(pPix, info->mm.front_buffer); ++ } ++ } + return TRUE; + } + +@@ -1625,6 +1635,7 @@ static Bool RADEONPreInitVRAM(ScrnInfoPtr pScrn) } pScrn->videoRam &= ~1023; @@ -3971,7 +4918,7 @@ index 7cac321..dbdae69 100644 info->FbMapSize = pScrn->videoRam * 1024; /* if the card is PCI Express reserve the last 32k for the gart table */ -@@ -1755,58 +1759,64 @@ static Bool RADEONPreInitChipType(ScrnInfoPtr pScrn) +@@ -1755,58 +1766,64 @@ static Bool RADEONPreInitChipType(ScrnInfoPtr pScrn) } from = X_PROBED; @@ -4079,7 +5026,7 @@ index 7cac321..dbdae69 100644 #ifdef XF86DRI /* AGP/PCI */ -@@ -1998,6 +2008,9 @@ static Bool RADEONPreInitAccel(ScrnInfoPtr pScrn) +@@ -1998,6 +2015,9 @@ static Bool RADEONPreInitAccel(ScrnInfoPtr pScrn) if (!xf86ReturnOptValBool(info->Options, OPTION_NOACCEL, FALSE)) { int errmaj = 0, errmin = 0; @@ -4089,7 +5036,7 @@ index 7cac321..dbdae69 100644 from = X_DEFAULT; #if defined(USE_EXA) #if defined(USE_XAA) -@@ -2008,6 +2021,7 @@ static Bool RADEONPreInitAccel(ScrnInfoPtr pScrn) +@@ -2008,6 +2028,7 @@ static Bool RADEONPreInitAccel(ScrnInfoPtr pScrn) info->useEXA = TRUE; } else if (xf86NameCmp(optstr, "XAA") == 0) { from = X_CONFIG; @@ -4097,7 +5044,7 @@ index 7cac321..dbdae69 100644 } } #else /* USE_XAA */ -@@ -2111,15 +2125,9 @@ static Bool RADEONPreInitInt10(ScrnInfoPtr pScrn, xf86Int10InfoPtr *ppInt10) +@@ -2111,15 +2132,9 @@ static Bool RADEONPreInitInt10(ScrnInfoPtr pScrn, xf86Int10InfoPtr *ppInt10) return TRUE; } @@ -4114,7 +5061,7 @@ index 7cac321..dbdae69 100644 if (!(info->dri = xcalloc(1, sizeof(struct radeon_dri)))) { xf86DrvMsg(pScrn->scrnIndex, X_ERROR,"Unable to allocate dri rec!\n"); -@@ -2130,6 +2138,22 @@ static Bool RADEONPreInitDRI(ScrnInfoPtr pScrn) +@@ -2130,6 +2145,22 @@ static Bool RADEONPreInitDRI(ScrnInfoPtr pScrn) xf86DrvMsg(pScrn->scrnIndex, X_ERROR,"Unable to allocate cp rec!\n"); return FALSE; } @@ -4137,7 +5084,7 @@ index 7cac321..dbdae69 100644 info->cp->CPInUse = FALSE; info->cp->CPStarted = FALSE; info->cp->CPusecTimeout = RADEON_DEFAULT_CP_TIMEOUT; -@@ -2704,6 +2728,37 @@ static const xf86CrtcConfigFuncsRec RADEONCRTCResizeFuncs = { +@@ -2704,6 +2735,37 @@ static const xf86CrtcConfigFuncsRec RADEONCRTCResizeFuncs = { RADEONCRTCResize }; @@ -4175,7 +5122,7 @@ index 7cac321..dbdae69 100644 Bool RADEONPreInit(ScrnInfoPtr pScrn, int flags) { xf86CrtcConfigPtr xf86_config; -@@ -2724,6 +2779,8 @@ Bool RADEONPreInit(ScrnInfoPtr pScrn, int flags) +@@ -2724,6 +2786,8 @@ Bool RADEONPreInit(ScrnInfoPtr pScrn, int flags) info = RADEONPTR(pScrn); info->MMIO = NULL; @@ -4184,7 +5131,7 @@ index 7cac321..dbdae69 100644 info->IsSecondary = FALSE; info->IsPrimary = FALSE; -@@ -2758,62 +2815,63 @@ Bool RADEONPreInit(ScrnInfoPtr pScrn, int flags) +@@ -2758,62 +2822,63 @@ Bool RADEONPreInit(ScrnInfoPtr pScrn, int flags) } info->PciInfo = xf86GetPciInfoForEntity(info->pEnt->index); @@ -4295,7 +5242,7 @@ index 7cac321..dbdae69 100644 if (xf86RegisterResources(info->pEnt->index, 0, ResExclusive)) goto fail; -@@ -2823,10 +2881,12 @@ Bool RADEONPreInit(ScrnInfoPtr pScrn, int flags) +@@ -2823,10 +2888,12 @@ Bool RADEONPreInit(ScrnInfoPtr pScrn, int flags) pScrn->racMemFlags = RAC_FB | RAC_COLORMAP | RAC_VIEWPORT | RAC_CURSOR; pScrn->monitor = pScrn->confScreen->monitor; @@ -4312,7 +5259,7 @@ index 7cac321..dbdae69 100644 if (!RADEONPreInitVisual(pScrn)) goto fail; -@@ -2840,136 +2900,199 @@ Bool RADEONPreInit(ScrnInfoPtr pScrn, int flags) +@@ -2840,136 +2907,198 @@ Bool RADEONPreInit(ScrnInfoPtr pScrn, int flags) memcpy(info->Options, RADEONOptions, sizeof(RADEONOptions)); xf86ProcessOptions(pScrn->scrnIndex, pScrn->options, info->Options); @@ -4562,7 +5509,6 @@ index 7cac321..dbdae69 100644 + } - ErrorF("after xf86InitialConfiguration\n"); -+ info->drmmode.create_new_fb = radeon_create_new_fb; + info->dri->drmFD = info->drmmode.fd; + info->dri2.drm_fd = info->drmmode.fd; + info->dri2.enabled = FALSE; @@ -4617,7 +5563,7 @@ index 7cac321..dbdae69 100644 /* Get ScreenInit function */ if (!xf86LoadSubModule(pScrn, "fb")) return FALSE; -@@ -2984,10 +3107,12 @@ Bool RADEONPreInit(ScrnInfoPtr pScrn, int flags) +@@ -2984,10 +3113,12 @@ Bool RADEONPreInit(ScrnInfoPtr pScrn, int flags) if (!RADEONPreInitXv(pScrn)) goto fail; } @@ -4634,7 +5580,7 @@ index 7cac321..dbdae69 100644 } if (pScrn->modes == NULL) { -@@ -3140,6 +3265,9 @@ static void RADEONBlockHandler(int i, pointer blockData, +@@ -3140,6 +3271,9 @@ static void RADEONBlockHandler(int i, pointer blockData, #ifdef USE_EXA info->accel_state->engineMode = EXA_ENGINEMODE_UNKNOWN; @@ -4644,7 +5590,7 @@ index 7cac321..dbdae69 100644 #endif } -@@ -3228,7 +3356,7 @@ Bool RADEONScreenInit(int scrnIndex, ScreenPtr pScreen, +@@ -3228,7 +3362,7 @@ Bool RADEONScreenInit(int scrnIndex, ScreenPtr pScreen, int subPixelOrder = SubPixelUnknown; char* s; #endif @@ -4653,7 +5599,7 @@ index 7cac321..dbdae69 100644 info->accelOn = FALSE; #ifdef USE_XAA -@@ -3248,58 +3376,61 @@ Bool RADEONScreenInit(int scrnIndex, ScreenPtr pScreen, +@@ -3248,58 +3382,61 @@ Bool RADEONScreenInit(int scrnIndex, ScreenPtr pScreen, "RADEONScreenInit %lx %ld\n", pScrn->memPhysBase, pScrn->fbOffset); #endif @@ -4754,7 +5700,7 @@ index 7cac321..dbdae69 100644 /* Visual setup */ miClearVisualTypes(); if (!miSetVisualTypes(pScrn->depth, -@@ -3333,19 +3464,21 @@ Bool RADEONScreenInit(int scrnIndex, ScreenPtr pScreen, +@@ -3333,19 +3470,21 @@ Bool RADEONScreenInit(int scrnIndex, ScreenPtr pScreen, hasDRI = info->directRenderingEnabled; #endif /* XF86DRI */ @@ -4788,7 +5734,7 @@ index 7cac321..dbdae69 100644 } } -@@ -3382,7 +3515,10 @@ Bool RADEONScreenInit(int scrnIndex, ScreenPtr pScreen, +@@ -3382,7 +3521,10 @@ Bool RADEONScreenInit(int scrnIndex, ScreenPtr pScreen, #ifdef XF86DRI if (hasDRI) { info->accelDFS = xf86ReturnOptValBool(info->Options, OPTION_ACCEL_DFS, @@ -4800,7 +5746,7 @@ index 7cac321..dbdae69 100644 /* Reserve approx. half of offscreen memory for local textures by * default, can be overridden with Option "FBTexPercent". -@@ -3408,7 +3544,7 @@ Bool RADEONScreenInit(int scrnIndex, ScreenPtr pScreen, +@@ -3408,7 +3550,7 @@ Bool RADEONScreenInit(int scrnIndex, ScreenPtr pScreen, #endif #if defined(XF86DRI) && defined(USE_XAA) @@ -4809,7 +5755,7 @@ index 7cac321..dbdae69 100644 info->dri->textureSize = -1; if (xf86GetOptValInteger(info->Options, OPTION_FBTEX_PERCENT, &(info->dri->textureSize))) { -@@ -3426,7 +3562,7 @@ Bool RADEONScreenInit(int scrnIndex, ScreenPtr pScreen, +@@ -3426,7 +3568,7 @@ Bool RADEONScreenInit(int scrnIndex, ScreenPtr pScreen, #endif #ifdef USE_XAA @@ -4818,7 +5764,7 @@ index 7cac321..dbdae69 100644 return FALSE; #endif -@@ -3447,7 +3583,7 @@ Bool RADEONScreenInit(int scrnIndex, ScreenPtr pScreen, +@@ -3447,7 +3589,7 @@ Bool RADEONScreenInit(int scrnIndex, ScreenPtr pScreen, info->CurrentLayout.pixel_bytes); int maxy = info->FbMapSize / width_bytes; @@ -4827,7 +5773,7 @@ index 7cac321..dbdae69 100644 xf86DrvMsg(scrnIndex, X_ERROR, "Static buffer allocation failed. Disabling DRI.\n"); xf86DrvMsg(scrnIndex, X_ERROR, -@@ -3457,19 +3593,54 @@ Bool RADEONScreenInit(int scrnIndex, ScreenPtr pScreen, +@@ -3457,19 +3599,54 @@ Bool RADEONScreenInit(int scrnIndex, ScreenPtr pScreen, info->CurrentLayout.pixel_bytes * 3 + 1023) / 1024); info->directRenderingEnabled = FALSE; } else { @@ -4886,7 +5832,7 @@ index 7cac321..dbdae69 100644 #endif xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG, "Initializing fb layer\n"); -@@ -3493,7 +3664,7 @@ Bool RADEONScreenInit(int scrnIndex, ScreenPtr pScreen, +@@ -3493,7 +3670,7 @@ Bool RADEONScreenInit(int scrnIndex, ScreenPtr pScreen, if (info->r600_shadow_fb == FALSE) { /* Init fb layer */ @@ -4895,7 +5841,7 @@ index 7cac321..dbdae69 100644 pScrn->virtualX, pScrn->virtualY, pScrn->xDpi, pScrn->yDpi, pScrn->displayWidth, pScrn->bitsPerPixel)) -@@ -3535,8 +3706,10 @@ Bool RADEONScreenInit(int scrnIndex, ScreenPtr pScreen, +@@ -3535,8 +3712,10 @@ Bool RADEONScreenInit(int scrnIndex, ScreenPtr pScreen, /* restore the memory map here otherwise we may get a hang when * initializing the drm below */ @@ -4908,7 +5854,7 @@ index 7cac321..dbdae69 100644 /* Backing store setup */ xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG, -@@ -3546,7 +3719,7 @@ Bool RADEONScreenInit(int scrnIndex, ScreenPtr pScreen, +@@ -3546,7 +3725,7 @@ Bool RADEONScreenInit(int scrnIndex, ScreenPtr pScreen, /* DRI finalisation */ #ifdef XF86DRI @@ -4917,7 +5863,7 @@ index 7cac321..dbdae69 100644 info->dri->pKernelDRMVersion->version_minor >= 19) { if (RADEONDRISetParam(pScrn, RADEON_SETPARAM_PCIGART_LOCATION, info->dri->pciGartOffset) < 0) -@@ -3562,14 +3735,24 @@ Bool RADEONScreenInit(int scrnIndex, ScreenPtr pScreen, +@@ -3562,14 +3741,24 @@ Bool RADEONScreenInit(int scrnIndex, ScreenPtr pScreen, if (info->directRenderingEnabled) { xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG, "DRI Finishing init !\n"); @@ -4943,7 +5889,7 @@ index 7cac321..dbdae69 100644 xf86DrvMsg(pScrn->scrnIndex, X_INFO, "Direct rendering enabled\n"); -@@ -3665,10 +3848,16 @@ Bool RADEONScreenInit(int scrnIndex, ScreenPtr pScreen, +@@ -3665,10 +3854,16 @@ Bool RADEONScreenInit(int scrnIndex, ScreenPtr pScreen, return FALSE; } } @@ -4953,15 +5899,15 @@ index 7cac321..dbdae69 100644 - if (!xf86SetDesiredModes (pScrn)) + if (info->drm_mode_setting) { + if (!drmmode_set_desired_modes(pScrn, &info->drmmode)) -+ return FALSE; + return FALSE; + } else { + if (!xf86SetDesiredModes (pScrn)) - return FALSE; ++ return FALSE; + } /* Provide SaveScreen & wrap BlockHandler and CloseScreen */ /* Wrap CloseScreen */ -@@ -5245,7 +5434,7 @@ Bool RADEONSwitchMode(int scrnIndex, DisplayModePtr mode, int flags) +@@ -5245,7 +5440,7 @@ Bool RADEONSwitchMode(int scrnIndex, DisplayModePtr mode, int flags) #ifdef XF86DRI Bool CPStarted = info->cp->CPStarted; @@ -4970,7 +5916,7 @@ index 7cac321..dbdae69 100644 DRILock(pScrn->pScreen, 0); RADEONCP_STOP(pScrn, info); } -@@ -5268,8 +5457,10 @@ Bool RADEONSwitchMode(int scrnIndex, DisplayModePtr mode, int flags) +@@ -5268,8 +5463,10 @@ Bool RADEONSwitchMode(int scrnIndex, DisplayModePtr mode, int flags) #endif } @@ -4983,7 +5929,7 @@ index 7cac321..dbdae69 100644 ret = xf86SetSingleMode (pScrn, mode, RR_Rotate_0); -@@ -5281,16 +5472,19 @@ Bool RADEONSwitchMode(int scrnIndex, DisplayModePtr mode, int flags) +@@ -5281,16 +5478,19 @@ Bool RADEONSwitchMode(int scrnIndex, DisplayModePtr mode, int flags) /* xf86SetRootClip would do, but can't access that here */ } @@ -5011,7 +5957,7 @@ index 7cac321..dbdae69 100644 } #endif -@@ -5488,6 +5682,11 @@ void RADEONAdjustFrame(int scrnIndex, int x, int y, int flags) +@@ -5488,6 +5688,11 @@ void RADEONAdjustFrame(int scrnIndex, int x, int y, int flags) xf86OutputPtr output = config->output[config->compat_output]; xf86CrtcPtr crtc = output->crtc; @@ -5023,7 +5969,7 @@ index 7cac321..dbdae69 100644 /* not handled */ if (IS_AVIVO_VARIANT) return; -@@ -5527,76 +5726,103 @@ Bool RADEONEnterVT(int scrnIndex, int flags) +@@ -5527,76 +5732,103 @@ Bool RADEONEnterVT(int scrnIndex, int flags) xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG, "RADEONEnterVT\n"); @@ -5176,7 +6122,7 @@ index 7cac321..dbdae69 100644 } #endif /* this will get XVideo going again, but only if XVideo was initialised -@@ -5611,7 +5837,7 @@ Bool RADEONEnterVT(int scrnIndex, int flags) +@@ -5611,7 +5843,7 @@ Bool RADEONEnterVT(int scrnIndex, int flags) info->accel_state->XInited3D = FALSE; #ifdef XF86DRI @@ -5185,7 +6131,7 @@ index 7cac321..dbdae69 100644 RADEONCP_START(pScrn, info); DRIUnlock(pScrn->pScreen); } -@@ -5634,26 +5860,28 @@ void RADEONLeaveVT(int scrnIndex, int flags) +@@ -5634,26 +5866,28 @@ void RADEONLeaveVT(int scrnIndex, int flags) "RADEONLeaveVT\n"); #ifdef XF86DRI if (RADEONPTR(pScrn)->directRenderingInited) { @@ -5229,7 +6175,7 @@ index 7cac321..dbdae69 100644 /* Make sure 3D clients will re-upload textures to video RAM */ if (info->dri->textureSize) { -@@ -5669,6 +5897,11 @@ void RADEONLeaveVT(int scrnIndex, int flags) +@@ -5669,6 +5903,11 @@ void RADEONLeaveVT(int scrnIndex, int flags) i = list[i].next; } while (i != 0); } @@ -5241,7 +6187,7 @@ index 7cac321..dbdae69 100644 } #endif -@@ -5695,10 +5928,18 @@ void RADEONLeaveVT(int scrnIndex, int flags) +@@ -5695,10 +5934,18 @@ void RADEONLeaveVT(int scrnIndex, int flags) xf86_hide_cursors (pScrn); @@ -5263,7 +6209,7 @@ index 7cac321..dbdae69 100644 xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG, "Ok, leaving now...\n"); -@@ -5752,7 +5993,8 @@ static Bool RADEONCloseScreen(int scrnIndex, ScreenPtr pScreen) +@@ -5752,7 +5999,8 @@ static Bool RADEONCloseScreen(int scrnIndex, ScreenPtr pScreen) #endif /* USE_XAA */ if (pScrn->vtSema) { @@ -5273,7 +6219,7 @@ index 7cac321..dbdae69 100644 } xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG, -@@ -5787,6 +6029,12 @@ static Bool RADEONCloseScreen(int scrnIndex, ScreenPtr pScreen) +@@ -5787,6 +6035,12 @@ static Bool RADEONCloseScreen(int scrnIndex, ScreenPtr pScreen) info->DGAModes = NULL; xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG, "Unmapping memory\n"); @@ -5580,22 +6526,19 @@ index 54bc234..06fbad3 100644 + #endif diff --git a/src/radeon_exa.c b/src/radeon_exa.c -index ae68146..dcf4e96 100644 +index ae68146..67299a4 100644 --- a/src/radeon_exa.c +++ b/src/radeon_exa.c -@@ -44,7 +44,11 @@ +@@ -44,7 +44,7 @@ #include "radeon_version.h" #include "xf86.h" +- +#include "radeon_bufmgr_gem.h" -+#define RADEON_PIXMAP_IS_FRONTBUFFER 1 -+ -+/* quick hacks lolz */ - /***********************************************************************/ #define RINFO_FROM_SCREEN(pScr) ScrnInfoPtr pScrn = xf86Screens[pScr->myNum]; \ -@@ -182,12 +186,23 @@ Bool RADEONGetPixmapOffsetPitch(PixmapPtr pPix, uint32_t *pitch_offset) +@@ -182,12 +182,23 @@ Bool RADEONGetPixmapOffsetPitch(PixmapPtr pPix, uint32_t *pitch_offset) RINFO_FROM_SCREEN(pPix->drawable.pScreen); uint32_t pitch, offset; int bpp; @@ -5620,7 +6563,7 @@ index ae68146..dcf4e96 100644 pitch = exaGetPixmapPitch(pPix); return RADEONGetOffsetPitch(pPix, bpp, pitch_offset, offset, pitch); -@@ -220,10 +235,27 @@ int RADEONBiggerCrtcArea(PixmapPtr pPix) +@@ -220,10 +231,27 @@ int RADEONBiggerCrtcArea(PixmapPtr pPix) return crtc_num; } @@ -5648,7 +6591,7 @@ index ae68146..dcf4e96 100644 static Bool RADEONPrepareAccess(PixmapPtr pPix, int index) { RINFO_FROM_SCREEN(pPix->drawable.pScreen); -@@ -231,7 +263,31 @@ static Bool RADEONPrepareAccess(PixmapPtr pPix, int index) +@@ -231,7 +259,31 @@ static Bool RADEONPrepareAccess(PixmapPtr pPix, int index) uint32_t offset = exaGetPixmapOffset(pPix); int bpp, soff; uint32_t size, flags; @@ -5664,7 +6607,7 @@ index ae68146..dcf4e96 100644 + RADEONCPFlushIndirect(pScrn, 0); + + radeon_bufmgr_gem_wait_rendering(driver_priv->bo); -+ + + /* flush IB */ + ret = dri_bo_map(driver_priv->bo, 1); + if (ret) { @@ -5675,12 +6618,12 @@ index ae68146..dcf4e96 100644 + pPix->devPrivate.ptr = driver_priv->bo->virtual; + } + } - ++ +#if X_BYTE_ORDER == X_BIG_ENDIAN /* Front buffer is always set with proper swappers */ if (offset == 0) return TRUE; -@@ -287,6 +343,7 @@ static Bool RADEONPrepareAccess(PixmapPtr pPix, int index) +@@ -287,6 +339,7 @@ static Bool RADEONPrepareAccess(PixmapPtr pPix, int index) OUTREG(RADEON_SURFACE0_LOWER_BOUND + soff, offset); OUTREG(RADEON_SURFACE0_UPPER_BOUND + soff, offset + size - 1); swapper_surfaces[index] = offset; @@ -5688,12 +6631,12 @@ index ae68146..dcf4e96 100644 return TRUE; } -@@ -296,7 +353,17 @@ static void RADEONFinishAccess(PixmapPtr pPix, int index) +@@ -296,7 +349,17 @@ static void RADEONFinishAccess(PixmapPtr pPix, int index) unsigned char *RADEONMMIO = info->MMIO; uint32_t offset = exaGetPixmapOffset(pPix); int soff; + struct radeon_exa_pixmap_priv *driver_priv; -+ + + driver_priv = exaGetPixmapDriverPrivate(pPix); + + if (driver_priv) { @@ -5701,12 +6644,12 @@ index ae68146..dcf4e96 100644 + pPix->devPrivate.ptr = NULL; + } + - ++ +#if X_BYTE_ORDER == X_BIG_ENDIAN /* Front buffer is always set with proper swappers */ if (offset == 0) return; -@@ -319,9 +386,93 @@ static void RADEONFinishAccess(PixmapPtr pPix, int index) +@@ -319,9 +382,135 @@ static void RADEONFinishAccess(PixmapPtr pPix, int index) OUTREG(RADEON_SURFACE0_LOWER_BOUND + soff, 0); OUTREG(RADEON_SURFACE0_UPPER_BOUND + soff, 0); swapper_surfaces[index] = 0; @@ -5773,19 +6716,61 @@ index ae68146..dcf4e96 100644 + return TRUE; + } + ++#if 0 + if (pPixData == info->mm.front_buffer->map) { -+ driver_priv->flags |= RADEON_PIXMAP_IS_FRONTBUFFER; ++ if (driver_priv->bo) ++ dri_bo_unreference(driver_priv->bo); + + driver_priv->bo = radeon_bo_gem_create_from_name(info->bufmgr, "front", + radeon_name_buffer(pScrn, info->mm.front_buffer)); + ++ if (!driver_priv->bo) ++ return FALSE; ++ + miModifyPixmapHeader(pPixmap, width, height, depth, + bitsPerPixel, devKind, NULL); + return TRUE; + } ++#endif + return FALSE; +} + ++dri_bo *radeon_get_pixmap_bo(PixmapPtr pPix) ++{ ++ ScrnInfoPtr pScrn = xf86Screens[pPix->drawable.pScreen->myNum]; ++ RADEONInfoPtr info = RADEONPTR(pScrn); ++ ++#ifdef XF86DRM_MODE ++ struct radeon_exa_pixmap_priv *driver_priv; ++ driver_priv = exaGetPixmapDriverPrivate(pPix); ++ if (driver_priv) ++ if (driver_priv->bo) ++ return driver_priv->bo; ++#endif ++ return NULL; ++ ++} ++ ++void radeon_set_pixmap_bo(PixmapPtr pPix, struct radeon_memory *mem) ++{ ++ ScrnInfoPtr pScrn = xf86Screens[pPix->drawable.pScreen->myNum]; ++ RADEONInfoPtr info = RADEONPTR(pScrn); ++ ++#ifdef XF86DRM_MODE ++ struct radeon_exa_pixmap_priv *driver_priv; ++ ++ driver_priv = exaGetPixmapDriverPrivate(pPix); ++ if (driver_priv) { ++ if (driver_priv->bo) ++ dri_bo_unreference(driver_priv->bo); ++ ++ driver_priv->bo = radeon_bo_gem_create_from_name(info->bufmgr, "front", ++ radeon_name_buffer(pScrn, mem)); ++ } ++#endif ++} ++ ++ +static Bool RADEONEXAPixmapIsOffscreen(PixmapPtr pPix) +{ + struct radeon_exa_pixmap_priv *driver_priv; @@ -5801,7 +6786,7 @@ index ae68146..dcf4e96 100644 #define ENTER_DRAW(x) TRACE #define LEAVE_DRAW(x) TRACE -@@ -332,6 +483,7 @@ static void RADEONFinishAccess(PixmapPtr pPix, int index) +@@ -332,6 +521,7 @@ static void RADEONFinishAccess(PixmapPtr pPix, int index) #define BEGIN_ACCEL(n) RADEONWaitForFifo(pScrn, (n)) #define OUT_ACCEL_REG(reg, val) OUTREG(reg, val) #define OUT_ACCEL_REG_F(reg, val) OUTREG(reg, F_TO_DW(val)) @@ -5809,7 +6794,7 @@ index ae68146..dcf4e96 100644 #define FINISH_ACCEL() #ifdef RENDER -@@ -345,6 +497,7 @@ static void RADEONFinishAccess(PixmapPtr pPix, int index) +@@ -345,6 +535,7 @@ static void RADEONFinishAccess(PixmapPtr pPix, int index) #undef OUT_ACCEL_REG #undef OUT_ACCEL_REG_F #undef FINISH_ACCEL @@ -5817,7 +6802,7 @@ index ae68146..dcf4e96 100644 #ifdef XF86DRI -@@ -355,6 +508,7 @@ static void RADEONFinishAccess(PixmapPtr pPix, int index) +@@ -355,6 +546,7 @@ static void RADEONFinishAccess(PixmapPtr pPix, int index) #define BEGIN_ACCEL(n) BEGIN_RING(2*(n)) #define OUT_ACCEL_REG(reg, val) OUT_RING_REG(reg, val) #define FINISH_ACCEL() ADVANCE_RING() @@ -5825,7 +6810,7 @@ index ae68146..dcf4e96 100644 #define OUT_RING_F(x) OUT_RING(F_TO_DW(x)) -@@ -372,6 +526,8 @@ static void RADEONFinishAccess(PixmapPtr pPix, int index) +@@ -372,6 +564,8 @@ static void RADEONFinishAccess(PixmapPtr pPix, int index) #endif /* XF86DRI */ @@ -5834,7 +6819,7 @@ index ae68146..dcf4e96 100644 /* * Once screen->off_screen_base is set, this function * allocates the remaining memory appropriately -@@ -393,122 +549,126 @@ Bool RADEONSetupMemEXA (ScreenPtr pScreen) +@@ -393,122 +587,126 @@ Bool RADEONSetupMemEXA (ScreenPtr pScreen) if (info->accel_state->exa == NULL) return FALSE; @@ -6064,7 +7049,7 @@ index ae68146..dcf4e96 100644 return TRUE; } -@@ -523,14 +683,23 @@ RADEONTexOffsetStart(PixmapPtr pPix) +@@ -523,14 +721,23 @@ RADEONTexOffsetStart(PixmapPtr pPix) { RINFO_FROM_SCREEN(pPix->drawable.pScreen); unsigned long long offset; @@ -7357,10 +8342,10 @@ index 861fd97..c436faf 100644 diff --git a/src/radeon_memory.c b/src/radeon_memory.c new file mode 100644 -index 0000000..2b6bc4d +index 0000000..568f9ba --- /dev/null +++ b/src/radeon_memory.c -@@ -0,0 +1,423 @@ +@@ -0,0 +1,396 @@ + +#include +#include @@ -7420,7 +8405,6 @@ index 0000000..2b6bc4d + if (!info->drm_mm) + return FALSE; + -+ + if (mem->kernel_bo_handle) { + struct drm_radeon_gem_unpin unpin; + @@ -7639,13 +8623,11 @@ index 0000000..2b6bc4d + cursor_size = RADEON_ALIGN(cursor_size, pagesize); + for (c = 0; c < xf86_config->num_crtc; c++) { + /* cursor objects */ -+ info->mm.cursor[c] = radeon_allocate_memory(pScrn, RADEON_POOL_VRAM, cursor_size, 0, 1, "Cursor", 1); ++ info->mm.cursor[c] = radeon_allocate_memory(pScrn, RADEON_POOL_VRAM, cursor_size, 0, 1, "Cursor", 0); + if (!info->mm.cursor[c]) { + return FALSE; + } + -+ radeon_bind_memory(pScrn, info->mm.cursor[c]); -+ + if (radeon_map_memory(pScrn, info->mm.cursor[c])) { + ErrorF("Failed to map front buffer memory\n"); + } @@ -7665,13 +8647,12 @@ index 0000000..2b6bc4d + /* keep area front front buffer - but don't allocate it yet */ + total_size_bytes += screen_size; + -+ if (info->directRenderingEnabled) { ++ if (info->directRenderingEnabled && !info->dri2.enabled) { + info->dri->backPitch = pScrn->displayWidth; + info->mm.back_buffer = radeon_allocate_memory(pScrn, RADEON_POOL_VRAM, screen_size, 0, 1, "Back Buffer", 0); + if (!info->mm.back_buffer) { + return FALSE; + } -+ // radeon_bind_memory(pScrn, info->mm.back_buffer); + total_size_bytes += screen_size; + + info->dri->depthPitch = RADEON_ALIGN(pScrn->displayWidth, 32); @@ -7683,7 +8664,6 @@ index 0000000..2b6bc4d + if (!info->mm.depth_buffer) { + return FALSE; + } -+ // radeon_bind_memory(pScrn, info->mm.depth_buffer); + total_size_bytes += depth_size; + } + } @@ -7715,11 +8695,13 @@ index 0000000..2b6bc4d + return FALSE; + } + -+ radeon_bind_memory(pScrn, info->mm.front_buffer); -+ if (radeon_map_memory(pScrn, info->mm.front_buffer)) { ++ /* don't need to bind or map memory */ ++ if (!info->dri2.enabled) { ++ if (radeon_map_memory(pScrn, info->mm.front_buffer)) { + ErrorF("Failed to map front buffer memory\n"); ++ } ++ info->dri->frontPitch = pScrn->displayWidth; + } -+ info->dri->frontPitch = pScrn->displayWidth; + + if (info->directRenderingEnabled && info->dri->textureSize) { + info->mm.texture_buffer = radeon_allocate_memory(pScrn, RADEON_POOL_VRAM, info->dri->textureSize, 0, 1, "Texture Buffer", 1); @@ -7734,8 +8716,10 @@ index 0000000..2b6bc4d + } + + xf86DrvMsg(pScrn->scrnIndex, X_INFO, "Front buffer size: %dK at 0x%08x\n", info->mm.front_buffer->size/1024, info->mm.front_buffer->offset); -+ xf86DrvMsg(pScrn->scrnIndex, X_INFO, "Back buffer size: %dK at 0x%08x\n", info->mm.back_buffer->size/1024, info->mm.back_buffer->offset); -+ xf86DrvMsg(pScrn->scrnIndex, X_INFO, "Depth buffer size: %dK at 0x%08x\n", info->mm.depth_buffer->size/1024, info->mm.depth_buffer->offset); ++ if (info->directRenderingEnabled && !info->dri2.enabled) { ++ xf86DrvMsg(pScrn->scrnIndex, X_INFO, "Back buffer size: %dK at 0x%08x\n", info->mm.back_buffer->size/1024, info->mm.back_buffer->offset); ++ xf86DrvMsg(pScrn->scrnIndex, X_INFO, "Depth buffer size: %dK at 0x%08x\n", info->mm.depth_buffer->size/1024, info->mm.depth_buffer->offset); ++ } + if (info->mm.texture_buffer) + xf86DrvMsg(pScrn->scrnIndex, X_INFO, "Texture size: %dK at 0x%08x\n", info->mm.texture_buffer->size/1024, info->mm.texture_buffer->offset); + xf86DrvMsg(pScrn->scrnIndex, X_INFO, "Remaining VRAM size (used for pixmaps): %dK\n", remain_size_bytes/1024); @@ -7747,32 +8731,6 @@ index 0000000..2b6bc4d + return TRUE; +} + -+Bool radeon_setup_gart_mem(ScreenPtr pScreen) -+{ -+ ScrnInfoPtr pScrn = xf86Screens[pScreen->myNum]; -+ RADEONInfoPtr info = RADEONPTR(pScrn); -+ -+#if 0 -+ info->mm.gart_texture_buffer = -+ radeon_allocate_memory(pScrn, RADEON_POOL_GART, -+ info->dri->gartTexMapSize, -+ 0, 1, "GART texture buffers", 1); -+ -+ if (!info->mm.gart_texture_buffer) { -+ return FALSE; -+ } -+ -+ radeon_bind_memory(pScrn, info->mm.gart_texture_buffer); -+#endif -+ return TRUE; -+} -+ -+uint32_t radeon_create_new_fb(ScrnInfoPtr pScrn, int width, int height, int *pitch) -+{ -+ return 0; -+} -+ -+ +dri_bo *radeon_create_rotate_bo(ScrnInfoPtr pScrn, int size) +{ + RADEONInfoPtr info = RADEONPTR(pScrn); diff --git a/xorg-x11-drv-ati.spec b/xorg-x11-drv-ati.spec index dada28a..e22670a 100644 --- a/xorg-x11-drv-ati.spec +++ b/xorg-x11-drv-ati.spec @@ -5,7 +5,7 @@ Summary: Xorg X11 ati video driver Name: xorg-x11-drv-ati Version: 6.11.0 -Release: 2%{?dist} +Release: 3%{?dist} URL: http://www.x.org License: MIT Group: User Interface/X Hardware Support @@ -76,6 +76,9 @@ rm -rf $RPM_BUILD_ROOT %{_mandir}/man4/radeon.4* %changelog +* Tue Mar 03 2009 Dave Airlie 6.11.0-3 +- initial support for dynamic fb resize + * Tue Mar 03 2009 Dave Airlie 6.11.0-2 - rebase to latest upstream r600 accel - fixup VT switch on DRI2