From f7d10d08c6cd1bd4377a4464d9d40094a2069ff1 Mon Sep 17 00:00:00 2001 From: Dave Airlie Date: Jun 26 2008 06:27:58 +0000 Subject: - update to latest git 6.8.192 beta --- diff --git a/radeon-git-upstream-fixes2.patch b/radeon-git-upstream-fixes2.patch index 059c938..3ac111f 100644 --- a/radeon-git-upstream-fixes2.patch +++ b/radeon-git-upstream-fixes2.patch @@ -1,1499 +1,16 @@ -commit faea008806802ec0e045754ec1eca492ebae320e -Author: Alex Deucher -Date: Tue May 27 18:36:01 2008 -0400 - - R3/4/5xx: use get_param to get the num_gb_pipes from the drm - -commit 965a5dbcd9dc4bf1cdd7f2bbdec15e9733b2e090 -Author: Alex Deucher -Date: Tue May 27 16:48:41 2008 -0400 - - RADEON: improve support for secondary cards - - this should fix bugs 16115, 16035 - -commit 5f951a5573f0c7572230c9aa4d3f75d67f91ed71 -Author: Alex Deucher -Date: Wed May 21 00:35:14 2008 -0400 - - ATOM: remove duplicate code - -commit edce33e87fb79a540d8c285f205d4c3f2c2bc9f4 -Author: Dave Airlie -Date: Wed May 28 06:43:40 2008 +1000 - - radeon: fix surface access on avivo chips. - - This should fix VT switch on vesafb - -commit 307bd65a25ee425d8359dd30572b002ce2338f91 -Author: Michael Babej -Date: Tue May 27 19:13:49 2008 +1000 - - r600: fix vt switch issue - - RH BZ 441492 - -commit bf48c9eb8ec592515be9d1732d60283af715674d -Author: Dave Airlie -Date: Sat May 24 11:51:20 2008 +1000 - - atombios: for LVDS set use ref div as per legacy - -commit 04500c8419b1aeaeac7968492b82e1d7cad1d05b -Author: Alan Coopersmith -Date: Tue May 20 20:34:31 2008 -0700 - - Strip ^M's from src/AtomBios/includes/ObjectID.h - -commit 521a0488d1c414209c3534dc242000faa332a441 -Author: Alan Coopersmith -Date: Tue May 20 20:33:37 2008 -0700 - - On non-gcc compilers, use C99's __func__ instead of gcc's __FUNCTION__ - -commit b7c80d0c86646105d2bce5d4d59ba6c45aa7cafc -Author: Tobias Diedrich -Date: Tue May 20 19:16:54 2008 -0400 - - R200/R300: fix gamma setup for overlay - - More pending. See bug 16001 - -commit 69423482e2e94637142a9ba675589a1449a346a8 -Author: Alex Deucher -Date: Tue May 20 18:57:13 2008 -0400 - - RADEON: cleanup connection detection and remove duplicate code - -commit 55e4469f59c82bb5762673de5f3f27d18b0bd9a3 -Author: Alex Deucher -Date: Tue May 20 17:46:58 2008 -0400 - - RADEON: enable cloning on multi-crtc cards - -commit 12f185634071980041aaac6265d89708b181b215 -Author: Alex Deucher -Date: Tue May 20 16:05:41 2008 -0400 - - ATOM: Ignore invalid connector entries - -commit 19e97f74e39fc2b35727708ac429de33d0b70162 -Author: Egbert Eich -Date: Tue May 20 11:16:15 2008 +0200 - - Change RMX code to follow the programming algorithm suggested by ATI. - - ATI provides the following algorithm to calculate the RMX scaling ratios - in its programming specs: - when RMX_AUTO_RATIO_HORZ_INC set to 1,Horizontal auto ratio result trucated, - and then incremented by 1. - Horz_Ratio = ( ((Active display width in characters (including overscan) + 1) - / (Panel width in characters)) x 4096 + 1 ) - else - Horz_Ratio = ( ((Active display width in characters (including overscan)) - / (Panel width in characters)) x 4096 + 1 ) - - when RMX_AUTO_RATIO_VERT_INC set to 1, Vertical auto ratio result trucated, - and then incremented by 1. - Vert_Ration = ( ((Active display width in characters (including overscan) + 1) - / (Panel width in characters)) x 4096 + 1) - else - Vert_Ration = ( ((Active display width in characters (including overscan)) - / (Panel width in characters)) x 4096 + 1) - - This patch implements this behavor. Additionally it avoids the use of floats. - -commit a4f3d0088ba763ed8eab1d331959b5ecde8262e8 -Author: Alex Deucher -Date: Tue May 20 11:42:53 2008 -0400 - - R3/4/5xx: fixup logic from last commit - - Spotted by otaylor and MrCooper - -commit 130e55738047f2a073bcc47e3e1400f7b694a81b -Author: Alex Deucher -Date: Tue May 20 11:32:42 2008 -0400 - - R3/4/5xx: fix EXA rotation - - xrandr uses PictOpSrc for rotation which we were falling back on since - render semanties require alpha=0 for REPEAT_NONE when there is no alpha - channel and there is a transform. If the dst has no alpha channel we - should be ok I think. - - Otayler and I discussed this on IRC. the more general fix would be - to clip the dst to the src and mask for bounded ops like in/add/over - in the pixel exact transform case. - -commit cc9f510770700228e5d597c872e926a4e99bd950 -Author: Corbin Simpson -Date: Wed May 14 16:49:01 2008 -0400 - - RADEON: missing stdint.h includes - -commit 71fa57f871dba03260dba2180ce1dab44048ac1a -Author: Alex Deucher -Date: Wed May 14 13:36:38 2008 -0400 - - Add RS600 support - -commit 582c1a1b2c7b1032e9f9f54ca36100c57f580c5c -Author: Alex Deucher -Date: Tue May 13 20:50:25 2008 -0400 - - RS4xx: Split out RS400 and RS480 as separate families - - RS400 (intel based IGP) and RS480 (AMD based IGP) have different - MC setups and need to be handled differently - -commit 708e7c98f636738fbcc47a597bc94b309a4dc1c4 -Author: Michel Dänzer -Date: Tue May 13 11:00:38 2008 +0200 - - Reinstate CARD* types that are part of external interfaces. - - The compiler pointed this out... - -commit 908b7b940e3ef296836bc94680ebb8ab67650e31 -Author: Matt Turner -Date: Mon May 12 12:06:33 2008 -0400 - - Replace CARD{8,16,32} with uint{8,16,32}_t - - As has been done with xf86-video-intel, replace all CARD* datatypes with - uint*_t datatypes available from stdint.h. - -commit 87e66ce76430890ab4939ffcd42f72b9288eb598 -Author: Avi Rozen -Date: Mon May 12 08:33:38 2008 -0400 - - RADEON: fix lockup on start - - see debian bug 480312 - -commit 94bf8f01bd43cb103fffecfe04d04a214f892baf -Author: Dave Airlie -Date: Mon May 12 20:02:51 2008 +1000 - - radeon: fix set_cursor_colours remove fb offset - -commit 1d0f1d31e2ed1d91ee87cb3e02ce48c8c07aa418 -Author: Dave Airlie -Date: Mon May 12 15:44:35 2008 +1000 - - radeon: rs485 vs rs485m.. mobile? non-mobile? bi? - - So it appears we have in the wild two chipsets with the same PCI ID (0x1002:0x5974) - that are mobile and non-mobile. - - the RH bug references is a desktop system. - The Dell Vostro 1100 also has this chipset with LVDS bits. - -commit 25e0c3945a51ae8c14b3a847ec75a256e1397f24 -Author: Alex Deucher -Date: Mon May 12 10:28:33 2008 +1000 - - radeon: add initial support for cloning outputs. (single-CRTC cards only) - - airlied - This code was originally written by Alex, and I've modified it to - only run on single-CRTC cards for now until we can test it some more. - -commit 94405eb1c9e4e0ababc6aef03b753d6ed9eb7838 -Author: Alex Deucher -Date: Fri May 9 05:28:44 2008 -0400 - - RADEON: fixup ifdef from last commit - -commit 18e20bc22a55ecfee9798c01079d7b24d19f0051 -Author: Alex Deucher -Date: Thu May 8 08:45:51 2008 -0400 - - RADEON: disable MMIO paths for EXA composite/texvid on IGP/R5xx - - The MMIO paths eventually lead to a hang on r5xx/IGP. I haven't - been able to find out why yet. - -commit c3532268875fd24e6519bea2fb1b814d612bbdb4 -Author: Dave Airlie -Date: Wed May 7 02:37:18 2008 +1000 - - radeon: fix zaphod EXA with texture video - -commit ffc437f3606ab8ceba1ff152e4bb08988a58b54c -Author: Dave Airlie -Date: Wed May 7 02:30:28 2008 +1000 - - avivo: fix zaphod cursor in theory - -commit e36ef14e3a1087e1fe41baa26ade2937f396001f -Author: Dave Airlie -Date: Wed May 7 01:39:28 2008 +1000 - - radeon: fix textured-xv on zaphod - -commit 8fc19bee27c0f151d2ab3354f6ac0992b358436d -Author: Dave Airlie -Date: Wed May 7 01:38:24 2008 +1000 - - radeon: zaphod: fix render accel for EXA - -commit fc41b9042a5220a8419cc7b69ca3850cae6b903c -Author: Dave Airlie -Date: Wed May 7 01:32:23 2008 +1000 - - radeon: fix EXA pixmap offset on zaphod - -commit 4568cb820d567c6909a4be956d7e79b91232535e -Author: Dave Airlie -Date: Wed May 7 01:19:39 2008 +1000 - - radeon: zaphod fixes for pciaccess not allowing multiple MMIO maps - -commit ca81fa086b21633a7fd926833fb6d1d4fa080646 -Author: Dave Airlie -Date: Wed May 7 01:12:01 2008 +1000 - - radeon: zaphod fix for cursor on second head - - We don't need to add fbOffset here as the mmap we have of the framebuffer - starts half way. - -commit 24b60c8965f6a0b3f0c2bb1e7236b4d6642c5918 -Author: Julien Cristau -Date: Fri May 2 15:30:45 2008 -0400 - - Add a test for __GLIBC__ to CD_Common_Types.h. - - Atombios redefines the standard types but the definitions conflict - with the ones from glibc (causes build failures on GNU/Hurd - and GNU/kFreeBSD). - -commit f051359ac09c6b9416e39b9ca7d9dc0880aa1557 -Author: thegraze -Date: Fri May 2 14:02:16 2008 -0400 - - ATOM: add support for DragonFlyBSD - -commit 3d469cbc3225d890a895dac7cbc1ab7e08054b48 -Author: Alex Deucher -Date: Wed Apr 30 18:33:04 2008 -0400 - - RADEON: lock the cursors when updating - - this should fix occasional corruption seen when updating - the cursor. - -commit 445b71021843665ba32f37b2ce5c9d2857c07cc7 -Author: Alex Deucher -Date: Tue Apr 29 21:01:41 2008 -0400 - - RADEON: assorted fixes - - - free rotate pixmaps on VT switch - - save crtc/output status so we only turn on - crtcs/outputs if they are off - - show/hide cursors when changing modes - -commit 070cce5255a5c311f9d8b85ec54bd56655014933 -Author: Stephan Wolf -Date: Mon Apr 28 11:26:37 2008 -0400 - - R3xx+: further fix for IGP chips - - see bug 15538 - -commit 211e0041c7fc2df494b77428553943a2b526ee4e -Author: Alex Deucher -Date: Sun Apr 27 21:08:00 2008 -0400 - - IGP: fix EXA composite corruption - -commit 656b06bdde129ca4fc370f5a2cf7311c9179b0ff -Author: Alex Deucher -Date: Sun Apr 27 20:20:49 2008 -0400 - - RADEON: remove duplicate register define - - Also add more bit defs to wait_until register - -commit 8a9820a3aa49bc667f90ac291a27e4d7b4ae38b3 -Author: Alex Deucher -Date: Sun Apr 27 19:02:22 2008 -0400 - - RADEON: decrease crtc/output verbosity - -commit c5d62fa0e8f52c3264ff9db3ff10cdf5a806bfc0 -Author: Owen Taylor -Date: Thu Apr 17 13:14:53 2008 +0200 - - Emulate repeats by drawing in tiles - - When we can't turn on hardware repeats, because the texture - is non-power-of-two, or has padding at the ends of lines, - try to draw the image in multiple tiles rather than falling - back to software. (We can only do this when there is no - transform.) - -commit eeb7b74bb6c813b0e3afa4b704f6ffb0d0aab92b -Author: Owen Taylor -Date: Thu Apr 17 13:14:25 2008 +0200 - - Turn on wrapping when repeating on R100 + R200 - - Actually enable repeats for R100 and R200. This corresponds - to a R300 change made in the patch in: - http://bugs.freedesktop.org/show_bug.cgi?id=15333 - -commit e511f39dfef503006cf249b9f6934091eaade9b5 -Author: Alex Deucher -Date: Thu Apr 17 05:04:34 2008 -0400 - - R300+: move more common code into init3d() - - - pre-load r3xx tex instructions - - setup RS instructions in init3d() - -commit 99435b7c18d931ea620044d0fdb4cc93dfcc6331 -Author: Owen Taylor -Date: Thu Apr 17 02:46:11 2008 -0400 - - Radeon: Omit mask coordinates - - Adapted from Owen's patch on bug 15546 - This fixes the slowness with aatext on r300 - and may speed up other chips marginally. - -commit 37614e1db9a595fbe8a21d7a045895e11d272db9 -Author: Alex Deucher -Date: Tue Apr 15 09:48:16 2008 -0400 - - fix up some things from the last commit - -commit 1286fe5ce1c77453d57817b9b26b1bdb32ca7bc8 -Author: Alex Deucher -Date: Mon Apr 14 20:02:14 2008 -0400 - - R300+: properly setup vap_cntl - - this fixes tcl/pvs on RV515 among other things - -commit f72a4b805db26f10f69330b88459cbeae661189b -Author: Alex Deucher -Date: Mon Apr 14 14:10:40 2008 -0400 - - EXA: Don't wait for 3D idle after each Composite() - - wait in CompositeDone() instead - -commit 4cd4acf1092aeb696b086a382a033aee471d2de9 -Author: Alex Deucher -Date: Mon Apr 14 11:50:59 2008 -0400 - - R300: move more common code to init3d() - -commit 3c523c9a07402e17dff588fad842224c57e98223 -Author: Alex Deucher -Date: Mon Apr 14 11:21:42 2008 -0400 - - R3xx+: 3D engine documentation and minor cleanups - - - document the R300 exa/textured video code - - minor cleanups of textured video code to clarify meaning - -commit ce025bbb2496d4de94b8d4ac450c64441b64ee04 -Author: Alex Deucher -Date: Sat Apr 12 21:22:03 2008 -0400 - - R300+: consolidate some tcl/non-tcl paths - - - Move more code to init3d() - - MMIO textured video seems more reliable now on newer chips - -commit 11b54a319c7c9dd52e3fb13372697059dafe1cd3 -Author: Alex Deucher -Date: Sat Apr 12 16:50:22 2008 -0400 - - R3xx+: fix XAA + textured video on non-TCL path - -commit dd15a2f5906725116b8cd9954243099055e88e37 -Author: Alex Deucher -Date: Sat Apr 12 16:49:03 2008 -0400 - - R3xx+: more fixes to 2D/3D engine init - -commit f3e68d4b7afd2e23675bf6361c496814c9cb4b94 -Author: Alex Deucher -Date: Fri Apr 11 10:59:07 2008 -0400 - - Fix exa glyph corruption on newer chips - -commit b59686d6427cbf8b35e36b020cbbc6a0c5149b22 -Author: Alex Deucher -Date: Fri Apr 11 10:15:25 2008 -0400 - - R300+: pre-load vertex programs in init3D() - -commit acc5833a35ad6c29a57f659607afb27eebdc2ea5 -Author: Alex Deucher -Date: Thu Apr 10 17:52:52 2008 -0400 - - R3xx+: consolidate more tcl code - -commit 6f8f75bd19ef1919c0291141675be2d0e29b3251 -Author: Alex Deucher -Date: Thu Apr 10 17:08:50 2008 -0400 - - R3xx+: consolidate some common 3D code - -commit 4b9234e1c4f7c7f419cb4245d64f3f9756c98bb6 -Author: Alex Deucher -Date: Thu Apr 10 16:58:22 2008 -0400 - - R3xx+: tcl wip - -commit 865c463e3afb4759758f569132be8bf1386da5cc -Author: Alex Deucher -Date: Thu Apr 10 16:51:04 2008 -0400 - - R300+: textured video tcl cleanup - -commit 79c8d4ca36a1c3e5fe759d4ccc379c36af8f1676 -Author: Alex Deucher -Date: Thu Apr 10 16:28:18 2008 -0400 - - RADEON: cleanup - -commit c4821a287d29a65f3bcb7d60dc72ec13c0384008 -Author: Alex Deucher -Date: Thu Apr 10 16:20:17 2008 -0400 - - Revert "R3xx/R5xx: move more VAP, etc. state setup into common init3d() function" - - This reverts commit 305a3310963a5dd07b3495015b06aa8c7c4e6b02. - - Conflicts: - - src/radeon_commonfuncs.c - src/radeon_exa_render.c - src/radeon_textured_videofuncs.c - -commit 0032c80bf30bab189204e3e6929e18a19d753138 -Author: Alex Deucher -Date: Thu Apr 10 14:35:00 2008 -0400 - - RADEON: store tcl status in driver rec - -commit 9e2ffe66d106abe34a670d2edc9905ed62c485e8 -Author: Alex Deucher -Date: Thu Apr 10 14:24:04 2008 -0400 - - R3xx+: use the right register for engine flush - -commit e1a9f26c2d2cbca9ad159e723ec95b95be1ef349 -Author: Alex Deucher -Date: Thu Apr 10 14:12:15 2008 -0400 - - R3xx+: minor textured video fixes - - - set shader output swizzling correctly - - flush the right cache register on r3xx+ - -commit d79040906cd25bd494feb5901f465bbd050aa923 -Author: Alex Deucher -Date: Thu Apr 10 13:59:58 2008 -0400 - - R3xx+: EXA/textured video fixes - - - get pipe config based on GB_PIPE_SELECT where applicable - (adapted from a similar patch from Dave) - - only flush the dst cache after submitting vertices, freeing - the cache lines stalls the pipe - - no need to wait for 3D idle after submitting vertices - - fix PURGE_CACHE() and PURGE_ZCACHE() for r3xx+ - - fix depth 16 with EXA composite - -commit 0a96173cc38e506728d4c3f2dd383ba56e856578 -Author: Michel Dänzer -Date: Mon Apr 7 18:15:34 2008 +0200 - - Increase default CP timeout. - - Helps avoid spurious timeouts causing problems, see - http://bugs.freedesktop.org/show_bug.cgi?id=15203 . - -commit 255fbf465f5e7db2609a5a151bfa810249db52a0 -Author: Owen W. Taylor -Date: Thu Apr 3 02:25:41 2008 -0400 - - Fix rendering of transformed sources for REPEAT_NONE with EXA on >= R300. - - Use the border color when possible, otherwise fall back to software. - -commit bc0407e53237d7968808110bc0243076377acf6e -Author: Alex Deucher -Date: Fri Apr 4 18:40:16 2008 -0400 - - ATOMBIOS: Add support for DynamicClocks option - - This patch adds support for dynamic clock gating and static - power management using the atom command tables. In some cases - the bios may already set this up during post, so YMMV. - - I was only able to test on desktop cards, so I haven't tested - to see how much (if any) power this saves or how it affects the - thermal footprint. - -commit 5f5e21bb50555c56bd371576074c28c929307ff1 -Author: Alex Deucher -Date: Fri Apr 4 14:29:45 2008 -0400 - - RADEON: warning fixes - -commit c8e9a973aaded24aad567a0e36d0c78a05d6b2fd -Author: Alex Deucher -Date: Fri Apr 4 14:26:19 2008 -0400 - - RADEON: add some quirks - -commit 091963a635b79884afe77c026eabb48972fbe175 -Author: Alex Deucher -Date: Thu Apr 3 22:35:16 2008 -0400 - - Minor cleanup - -commit 950e9860643c20acde0eca4e4ff26baacc1f2b69 -Author: Alex Deucher -Date: Thu Apr 3 22:11:48 2008 -0400 - - Revert "RADEON: memmap rework 1" - - This reverts commit dd8ee1b444f4b973a1e0fadca5f943f2162b5e94. - - Conflicts: - - src/radeon.h - src/radeon_driver.c - - This rework seems to have caused more trouble than it was worth. - -commit 88a1fe4a94c5d11aff22734b21c89890e4428cd5 -Author: Alex Deucher -Date: Thu Apr 3 22:04:43 2008 -0400 - - Revert "RADEON: remove driver rec copies of mc info, use save rec directly" - - This reverts commit be0858a84fbdf74c0b844f462933a221d48c707d. - - Conflicts: - - src/radeon_driver.c - -commit c40a7aa3989576a8144213e2f31b892d21df8686 -Author: Owen W. Taylor -Date: Thu Apr 3 14:43:55 2008 -0400 - - R3xx/R5xx: Fix pitch and clamp mode for repeating textures - - - We can always use TXPITCH on a R300 even when repeating, - (previous check for pitch matching width was also wrong) - - Fix clamp mode for repeating textures to be WRAP - -commit a8593482c1f2e0f2dbac06c2e5325ba8c83ed9ff -Author: Dave Airlie -Date: Wed Apr 2 09:58:05 2008 +1000 - - atombios: fix the dual-head hopefully. - - tested on r600 with DVI and VGA - -commit 61d883d116fab3e9b513432d65e705afc5bb39f1 -Author: Dave Airlie -Date: Wed Apr 2 09:57:38 2008 +1000 - - Revert "Revert "atombios: fixup the width/height to use the mode values not the scrn ones"" - - This reverts commit fc9af578997b6f22ee8b17e83f37d98689291b0e. - - I see your revert and raise you one... - -commit fc9af578997b6f22ee8b17e83f37d98689291b0e -Author: Alex Deucher -Date: Tue Apr 1 09:25:45 2008 -0400 - - Revert "atombios: fixup the width/height to use the mode values not the scrn ones" - - This reverts commit c2b1c8b706a6c7c1fd0af80091958473133d54e7. - - These registers hold surface size. Using the mode values - breaks dualhead. - -commit 959509dd54de053f526b534e379a46934127231f -Author: Dave Airlie -Date: Mon Mar 31 14:29:44 2008 +1000 - - radeon: use correct DDC interfaces so quirks get applied - - Radeon seemed to mess up applying certain quirks, hopefully this will fix it. - -commit 18f5f1cd2f52afed89fc11ade0920f3dfea87306 -Author: Dave Airlie -Date: Mon Mar 31 14:11:49 2008 +1000 - - radeon: split quirks into separate function and new quirk for IBM RN50 - - Add a connector table quirk for the IBM RN50. - -commit c2b1c8b706a6c7c1fd0af80091958473133d54e7 -Author: Dave Airlie -Date: Sun Mar 30 11:44:14 2008 +1000 - - atombios: fixup the width/height to use the mode values not the scrn ones - - this fixes it properly, legacy appears to be okay. - -commit c5edea3d8c9254d3a21e390b8309e39e4c9635db -Author: Dave Airlie -Date: Sun Mar 30 11:11:22 2008 +1000 - - r500/r600: fix rotation to fill screen - - I'm not 100% sure this is the correct fix (maybe we shouldn't be using scrn - virtualX/Y)... this will fix it for now until I get more time. - -commit 9c62c820ba45ebc14d5f36f5d7885863800b6adb -Author: Michel Dänzer -Date: Fri Mar 28 12:37:29 2008 +0100 - - Include config.h, so FGL_LINUX can actually be defined when it's tested... - -commit a00d9260a85b94a522c442aee24bc5ea4dc31c5c -Author: Alex Deucher -Date: Thu Mar 27 20:03:13 2008 -0400 - - RADEON: fix lid issues on AVIVO chips for real this time :) - -commit f0e89c09074b2c7e641f73692bb39b0bf68eb49c -Author: Alex Deucher -Date: Thu Mar 27 19:15:18 2008 -0400 - - Revert "RADEON: attempt to fix lid issues" - - This reverts commit 9b4473c1d830b88866dd22e8174a07195bd6fcf4. - This doesn't help. - -commit 1442d396b938049b83f009a78ddabe2bf85641b6 -Author: Dave Airlie -Date: Thu Mar 27 14:02:51 2008 +1000 - - radeon: size bios to max of bar vs 64k. - - reported by dwmw2: rhbz 438299 - -commit de2f609ff0004ef8b74727bfebc2c74fb91205ea -Author: Alex Deucher -Date: Wed Mar 26 18:35:21 2008 -0400 - - AVIVO: no need to call PreinitXv() on AVIVO chips as they have no overlay - -commit 75884c257bc2bcfa5b498a77d4c403f09face036 -Author: Alex Deucher -Date: Wed Mar 26 18:16:47 2008 -0400 - - XAA: update message about render so as to not confuse users - -commit 9b4473c1d830b88866dd22e8174a07195bd6fcf4 -Author: Alex Deucher -Date: Wed Mar 26 18:01:29 2008 -0400 - - RADEON: attempt to fix lid issues - - On some laptops the bios attempts to re-program the chip - when a lid event comes in. This should hopefully prevent - the bios from doing that. - -commit 8b144830fe9b4a0cee4745023de5e7d387070f60 -Author: Alex Deucher -Date: Tue Mar 25 01:15:05 2008 -0400 - - RV250: disable textured video due to HW bug - - The YUV->RGB conversion in the texture engine is broken - on RV250 so the colors come out wrong. - -commit 1789f11ab91633d3928f8b71988d51ff44bda9d1 -Author: Alex Deucher -Date: Mon Mar 24 19:03:30 2008 -0400 - - R3xx/R5xx: flush PVS state before enabling pvs-bypass - -commit 305a3310963a5dd07b3495015b06aa8c7c4e6b02 -Author: Alex Deucher -Date: Mon Mar 24 14:25:03 2008 -0400 - - R3xx/R5xx: move more VAP, etc. state setup into common init3d() function - - Also some minor code cleanups - -commit 399b1d405e602c62d6deebea6d7e1f38886cd8e2 -Author: Alex Deucher -Date: Mon Mar 24 13:04:57 2008 -0400 - - R3xx/R5xx: use non VAP/TCP for textured video - - Just extra state to emit. - -commit cd77ec18f32a7b36acb655c927bbfd7044019f97 -Author: Dave Airlie -Date: Mon Mar 24 18:42:21 2008 +1000 - - r300: don't bother with VAP/TCL for render. - - We just send more data to the card to process per transaction, without getting - any actual gains, as we already pre-compute the vertices without needing - any clipping or transforms from the card. - - Perhaps some stuff could be done on-card, but so far the code is a lot - faster if we avoid sending this extra info. - - pre: 150000 glyphs/sec - post: 185000 glyphs/sec - -commit 301c6739b88676a0c78fc72194e993f894b8dc28 -Author: Alex Deucher -Date: Sun Mar 23 11:14:02 2008 -0400 - - RS4xx: Revert back to previous fifo settings for now - - Setup of these registers needs more investigation. - -commit 9bea60b3eb378de5e1d44cc02a2763f4feae7882 -Author: Alex Deucher -Date: Sat Mar 22 11:46:15 2008 -0400 - - RS4xx: more work on disp/disp2 fifo setup - -commit 90f11c3986c28daa7b600b9662da145af325d264 -Author: Alex Deucher -Date: Sat Mar 22 11:29:51 2008 -0400 - - RS4xx: missed this on the last commit. - -commit 6d5066a451017a2683addc9e2496987626795dda -Author: Alex Deucher -Date: Fri Mar 21 16:21:54 2008 -0400 - - RS4xx: attempt to set up disp/disp2 fifos correctly - - If you have an XPRESS chip, please test!!! - -commit fb1cffac05ae20c8365b25a2042b0ae961880faf -Author: Alex Deucher -Date: Fri Mar 21 15:24:36 2008 -0400 - - RS4xx: attempt to fix TMDS/DVO support - - XPRESS chips added a second set of FP control registers. - I don't have the hw to test however. - -commit 5e3b21284482df9974c9a58f248f0100def2bb0c -Author: Alex Deucher -Date: Wed Mar 19 19:15:05 2008 -0400 - - Disable the setting of HARDWARE_CURSOR_BIT_ORDER_MSBFIRST - - See bug 11796 - -commit 17cd42ed31814ba329a6a68edd0d75390a7da40e -Author: Matt Turner -Date: Wed Mar 19 18:17:10 2008 -0400 - - Enable BSR in Log2 functions - - This patch edits RADEONLog2 and ATILog2 to use the x86 BSR instruction instead - of looping through bits. It should provide a somewhat of a speed increase in - this function on x86 and AMD64 architectures. - - Note: the BSR instruction was added with the 80386 CPU and is therefore not - compatible with earlier CPUs, though I highly doubt it's even possible to use a - 286 in conjunction with a Radeon. - - The inline assembly also works with Intel's compiler (icc). - -commit c83827b4d2b6f03c54429e757a756eb99ff8be6b -Author: Paulo Cesar Pereira de Andrade -Date: Wed Mar 19 17:58:34 2008 -0400 - - [PATCH] Compile warning fixes. - - Minor changes to avoid declarations mixed with code. - Ansified functions with empty prototype to specify they don't - receive arguments. - Added some prototypes to radeon.h, and major reorder on radeon.h - adding prototypes in alphabetical order and specifying to file that - defines it. - -commit bed9754ad21d6c0a7f61067b04ba31c430a7cecb -Merge: 55e446b... f71ac0e... -Author: Alex Deucher -Date: Wed Mar 19 16:06:41 2008 -0400 - - Merge branch 'master' of ssh://agd5f@git.freedesktop.org/git/xorg/driver/xf86-video-ati into r3xx-render - -commit 55e446b5bc091e6c7b3c2e9ae20b45130555c246 -Author: Alex Deucher -Date: Wed Mar 19 13:15:32 2008 -0400 - - R3xx/R5xx: Make sure to clamp the output of the FS - -commit b6aa4279cbe68cc8e4523795e9714fb798b62d98 -Author: Alex Deucher -Date: Wed Mar 19 12:45:01 2008 -0400 - - R5xx: bump textured video limits to 4096 - -commit 4a445a3e8c4c5ecd9d4ef8daa26906c3ceaa94a1 -Author: Alex Deucher -Date: Wed Mar 19 12:31:51 2008 -0400 - - RADEON: add new macros to distinguish between R3xx and R5xx 3D - -commit 85d0c9e8d22ccc72bec87b3fd44da5d7609293e0 -Author: Alex Deucher -Date: Wed Mar 19 12:07:33 2008 -0400 - - RADEON: fixed textured video with XAA and tiling - -commit f5951db7b3522e0fe6af7f46a170c9c9a60a9bff -Author: Alex Deucher -Date: Wed Mar 19 12:01:50 2008 -0400 - - RV515: fix textured video and EXA Composite - - There seems to be an issue with the PVS setup on RV515, but - bypassing it seems to work fine. - -commit 13573879fe56368ad06234712b677c23fabc56c6 -Author: Dave Airlie -Date: Wed Mar 19 15:06:47 2008 +1000 - - r500: make it work from startup. - - I'm not sure why this worked or what is going wrong here, really the - VAP internal architecture escapes me :) - -commit d331dd64d644a18ec99a2136cd0943b5edca1f03 -Author: Alex Deucher -Date: Tue Mar 18 19:44:26 2008 -0400 - - R3xx/R5xx: remove extra return after last commit - -commit bc34df7a9c35cdd38c49d5c22471f3f487a33d6e -Author: Alex Deucher -Date: Tue Mar 18 19:39:47 2008 -0400 - - R3xx/R5xx: switch an ErrorF() to RADEONFALLBACK() - -commit 6f03f8fe0ecf4181dcf125049cf63bece0451fb2 -Author: Alex Deucher -Date: Tue Mar 18 19:36:05 2008 -0400 - - R3xx: we only use 2 temps, not 3 - -commit 8bb71ab4a3eb4fb6ef7f709e87c8df387cb70ee3 -Author: Tilman Sauerbeck -Date: Tue Mar 18 14:36:08 2008 -0400 - - R3xx/R5xx: fix up a8-src-something_with_colors - -commit c362591d9b496df30668543158e4de44de742dc3 -Author: Alex Deucher -Date: Tue Mar 18 11:15:17 2008 -0400 - - R3xx/R5xx: remove some cruft - -commit 89fe6d2c7d7471e6088558130f6e49f46c31dd47 -Author: Dave Airlie -Date: Tue Mar 18 09:43:43 2008 -0400 - - R5xx: fix typ in r5xx render accel - - This gets render working on r5xx - -commit 79b40ebcd8dedfc83e484c1024beeeaccc6124f3 -Author: Alex Deucher -Date: Tue Mar 18 02:46:49 2008 -0400 - - R5xx: first pass at render support (untested) - -commit 71292c8f193230255d1d980c2e996bb01d04fab6 -Author: Alex Deucher -Date: Tue Mar 18 00:45:37 2008 -0400 - - R5xx: bump tex/dst limits to 4096 - -commit 30b52f8aa6a471455284f59b5b27252743892b13 -Author: Alex Deucher -Date: Mon Mar 17 23:20:10 2008 -0400 - - R3xx/R5xx: whitespace cleanup and cruft removal - -commit 9c9f1b538ed710c3066775fba0a8e936b63087b1 -Author: Alex Deucher -Date: Mon Mar 17 23:01:37 2008 -0400 - - R3xx: get masks working and cleanup - - RS offset was wrong for mask texture - -commit ef94febd74f8ee63081b61e42f093a5a2b8fbf1e -Author: Alex Deucher -Date: Mon Mar 17 22:27:19 2008 -0400 - - R3xx: minor adjustments - -commit f71ac0e40b9d950bcb3bba42a75d41f45b6ed1bf -Author: Alban Browaeys -Date: Mon Mar 17 20:48:48 2008 -0400 - - RADEON: Revert to old behavior when resetting the memmap on VT switch - - Not sure why this needs to be done twice. Should fix bug 14980 - Probably needs more investigation. - -commit bedbbf196dc97ee5142e7dfae16fb6f317fca5a7 -Author: Alex Deucher -Date: Mon Mar 17 20:16:25 2008 -0400 - - R3xx: some progress - -commit af0e626c132de2dd9958fec657fcc85d4c0fe5e1 -Author: Alex Deucher -Date: Mon Mar 17 18:07:12 2008 -0400 - - R3xx: fix errant w - -commit 29ea5bfc0eb3194e2454fc3ee863df54f0300880 -Author: Alex Deucher -Date: Mon Mar 17 16:41:57 2008 -0400 - - RADEON: fix typo in RADEONAdjustMemMapRegisters() - -commit ab317e85c5ab1a249a510c34aeb3a908be1a66fc -Author: Alex Deucher -Date: Mon Mar 17 15:28:09 2008 -0400 - - RADEON: make sure var is initialized properly in RADEONAdjustMemMapRegisters() - -commit 208d307227e15f37a6af5194398ed23266ff743a -Author: Dave Airlie -Date: Sun Mar 16 19:39:23 2008 +1000 - - radeon: the 0x5974 appears to be a mobility chip... - - After debugging with partymola on #radeon, adding this allowed his - Dell Vostro 1000 to work properly - -commit 9bc7c2ec4048e1677547c1d60c51ccb954f7589a -Author: Alex Deucher -Date: Fri Mar 14 20:12:22 2008 -0400 - - R3xx: odds and ends... - - still not working. - - swizzle US output for BGR formats - - no need to write to temps in ALU ops, - write to output only - - flush the PVS before updating - -commit 96bea7906c4706fcd57a9cd8f1ce3feab6ac676d -Author: Alex Deucher -Date: Fri Mar 14 15:59:36 2008 -0400 - - R3xx: theoretical support for component alpha - - masks are still broken so... - -commit cffe3dcc8991cd7c457a9c1a9f41055aa9ea3436 -Author: Alex Deucher -Date: Fri Mar 14 14:37:43 2008 -0400 - - R3xx: VS WIP - -commit b73f52a50dfd6ff8d92f04d6b510c39582c6ac67 -Author: Alex Deucher -Date: Fri Mar 14 14:20:49 2008 -0400 - - R3xx/R5xx: enable VS for mask texture - -commit 569a14ca9be1e18fe9921edc816ac3dc32d6cca7 -Author: Alex Deucher -Date: Fri Mar 14 13:32:12 2008 -0400 - - R3xx/R5xx: Fix magic numbers in vertex shaders - -commit 4878997529601d62e257aa1c9112bd460561de73 -Author: Alex Deucher -Date: Thu Mar 13 21:23:40 2008 -0400 - - R3xx: make sure to set the FS code size correctly - -commit 22f46b88ef05afb6a6b6d70007ac4980a446430e -Author: Alex Deucher -Date: Thu Mar 13 20:25:33 2008 -0400 - - R3xx: attempt to setup the rasterizer properly for mask texture - - Not working yet - -commit 081fc9e892fa3d2e07b7db65b2e2719646255463 -Author: Alex Deucher -Date: Thu Mar 13 18:38:26 2008 -0400 - - R3xx: more mask work - -commit 2bf0236c03538ace3ce6d0e68f0829fc47d1385b -Author: Alex Deucher -Date: Thu Mar 13 18:32:00 2008 -0400 - - R3xx: enable composite for non-mask cases - -commit 74286ba41302107d2fc626fee2181f7c4bc18164 -Author: Alex Deucher -Date: Thu Mar 13 18:25:32 2008 -0400 - - R3xx: add basic mask support - -commit a2bbe10d866567911b68f222b4758624bfe9bf84 -Author: Alex Deucher -Date: Thu Mar 13 18:16:53 2008 -0400 - - R300: setup source selects and output swizzling - -commit b9974ecce7d1932595226004858b08a7a6b188dc -Author: Alex Deucher -Date: Thu Mar 13 17:35:38 2008 -0400 - - R3xx: set the texture id and add some register info - -commit 0ef700b7da5e554a0d0d166f3fde85ff45c9eb1f -Author: Alex Deucher -Date: Thu Mar 13 17:02:25 2008 -0400 - - R3xx/R5xx: enable blending - -commit b35c09a597c93a1d9f06ef0091c96822b0653f98 -Author: Dave Airlie -Date: Thu Mar 13 18:42:29 2008 +1000 - - xv: fixup XAA on r500 textured video - - the XAA area should never end up tiled. This may break with nooffscreen pixmaps - -commit d4446461c3630caff166456c351ace34f57cc119 -Author: Matt Turner -Date: Tue Mar 11 21:20:53 2008 -0400 - - Properly fix uninitialized variables warnings - - According to commit 9fd13e6773371c82b9799a5bda7c96ffa5cafe8c to - xf86-video-intel by Kristian Høgsberg, there is a better way to fix the - possibly initialized variables warnings. This patch will use Kristian's fix. - -commit 20adfd7390d9b1f100e0c4a14f175377b8335c82 -Author: Alex Deucher -Date: Tue Mar 11 20:09:35 2008 -0400 - - RADEON: enable output attributes that require a modeset immediately - - This should fix bug 14915 - -commit 53ba7f5771b0b53fb0d3bc29d64bdd3813756d10 -Author: Alex Deucher -Date: Tue Mar 11 19:12:40 2008 -0400 - - RADEON: fix vblank interrupts after VT switch or suspend/resume - -commit e946c097f0438afbea6f3dd37ee39d67d415708c -Author: Matt Turner -Date: Tue Mar 11 19:07:58 2008 -0400 - - [PATCH] Fix a few warnings - -commit 8e160508520c0a24ca90aad182f296461ca0d9b6 -Author: Alex Deucher -Date: Tue Mar 11 18:11:13 2008 -0400 - - DCE3: add support for PCIEPHY (untested) - -commit fbded88a2925f9f049936dad0736721e7b84a6ee -Author: Alex Deucher -Date: Tue Mar 11 14:10:31 2008 -0400 - - ATOM: remove some cruft - -commit 3263f6e4a410281d620c288a92bb4521f7b6fc06 -Author: Alex Deucher -Date: Tue Mar 11 14:05:48 2008 -0400 - - DCE3: enable DPMS on DIG ports - -commit eb90e235b58c94f3d4d75394725ab2fe246a42ff -Author: Alex Deucher -Date: Tue Mar 11 13:53:54 2008 -0400 - - DCE3: adjust PLL for DCE3 chips - - this fixes stability issues on digital outputs and certain modes. - -commit 552615ccc5360baafb8bb41698c1ca27816fd4b2 -Author: Alex Deucher -Date: Tue Mar 11 13:38:29 2008 -0400 - - ATOMBIOS: enable load detection by default on both DACs - - Load detection is reliable with atom, so enable it by default - on both DACA and DACB, rather than just DACA. - -commit 78b10487cf222c96f8944ba25e2ea970506b3535 -Author: Alex Deucher -Date: Tue Mar 11 13:16:00 2008 -0400 - - DCE3: add output attribute to enable/disable coherent mode - - Enabled by default. The TMDS transmitter can be programmed - slightly differently depending on the chips in the panel. If you - have problems with tmds on a particular panel, try disabling it. - -commit d20be31c46fbec623af4c3628a7c603ceacf500f -Author: Alex Deucher -Date: Mon Mar 10 21:05:43 2008 -0400 - - RV550: MC setup is like RV515 not RV530 - -commit 38606b08b68842fbcc81c233009c1117269f3be9 -Author: Matthieu Herrb -Date: Sat Mar 8 23:22:59 2008 +0100 - - Makefile.am: nuke RCS Id - -commit 9d710ee1a44cf2f3a948fbdbe17ef09521cbe744 -Author: Alex Deucher -Date: Fri Mar 7 15:09:14 2008 -0500 - - AVIVO: clean up some unused variables - -commit c28c30c9f3d7bfebfd56a5c982c96f0090982054 -Author: Alex Deucher -Date: Fri Mar 7 14:10:49 2008 -0500 - - RADEON: Fix crash in last commit - -commit c3a3635865e380c784a226c8ead069d4716d6b75 -Author: Dave Airlie -Date: Thu Mar 6 20:17:45 2008 -0500 - - RADEON: fix tiling/interlaced interaction with randr 1.2 - -commit df1b94dc4eb1f35b636dbf2ec0ab1c2da9937c0d -Author: Alex Deucher -Date: Thu Mar 6 19:22:08 2008 -0500 - - DCE3: Ignore outputs with DIN connectors for now - -commit cb2dc19387c7b6494c47c76d683cf38a48700768 -Author: Alex Deucher -Date: Thu Mar 6 18:33:12 2008 -0500 - - AVIVO: fix typo from a previous commit - - Leave tv dpms hook disabled or you may get bad interactions - with the shared DAC - -commit 77355de48057e5e7e0d5b3f3cf5a7a92220a53b1 -Author: Alex Deucher -Date: Thu Mar 6 17:46:00 2008 -0500 - - AVIVO: don't add outputs for invalid connectors - -commit 600dbe080997a01ceaf6be86723189d518bc1281 -Merge: 594743a... 5b7875d... -Author: Alex Deucher -Date: Thu Mar 6 17:31:37 2008 -0500 - - Merge branch 'master' of ssh://agd5f@git.freedesktop.org/git/xorg/driver/xf86-video-ati - -commit 594743a99811a8b0f391412892414fcd158eeb56 -Author: Alex Deucher -Date: Thu Mar 6 17:30:21 2008 -0500 - - AVIVO: fix up memsize detection for IGP chips - -commit 5b7875d0cbfbdbcd1515c4e942d30de298b49dff -Author: Doug Chapman -Date: Thu Mar 6 14:31:06 2008 -0500 - - Bug #14826: Fix a bogus check around xf86SetOperatingState. - -commit 651fe23f4c650ed91843dec48db24e18e8b91219 -Merge: 3de2dc8... 766f464... -Author: Adam Jackson -Date: Thu Mar 6 14:28:27 2008 -0500 - - Merge branch 'master' of git+ssh://git.freedesktop.org/git/xorg/driver/xf86-video-ati - -commit 41171c25cd235bafad26bcbabced16ead4b8c54b -Author: Alex Deucher -Date: Thu Mar 6 14:05:18 2008 -0500 - - DCE3.0: add support for crtc memreq table - -commit 766f464dfdfccadef23e4232f2bce5db22195513 -Author: Alex Deucher -Date: Thu Mar 6 13:35:43 2008 -0500 - - RADEON: take 2 on proper pragma pack support for bsds - - See bug 14594. Based on suggestion by Henry Zhao - -commit a842ce9ca6494e724a7828cead9b61c9ef02b6aa -Author: Alex Deucher -Date: Thu Mar 6 12:32:18 2008 -0500 - - DCE3.0: Minor fixups - -commit 8a1ba374033591c725a78923aa30829e4de2a5ae -Author: Alex Deucher -Date: Thu Mar 6 09:53:51 2008 -0500 - - RADEON: option to override TVDAC adj values from bios with driver defaults - - If you have a washed out image on the tv dac, try this option. - Option "DefaultTVDACAdj" "TRUE" - -commit 0ed48f8f651a28e189f9fee8c6b593da0178d21c -Author: Alex Deucher -Date: Wed Mar 5 18:41:01 2008 -0500 - - AVIVO: Initial support for DCE 3.0 using atombios - - DACs are working well, DIG support (DVI, HDMI, LVDS, etc.) - still has some issues. - -commit 2901e99f1942842856cd39c1dcc8b22f3cf7d9e3 -Author: Alex Deucher -Date: Wed Mar 5 10:40:06 2008 -0500 - - RADEON: fix fetching of dac2 adj values from newer bios tables - -commit 74eb981287d76836327830bd51272f605a07e0cc -Author: Alex Deucher -Date: Mon Mar 3 12:02:44 2008 -0500 - - ATOMBIOS: fix atombios parser support on *bsd - - bsd requires a different pragma pack than Linux. - See bug 14594. - -commit f7769ea86e265f347eb58c517ccb5ef8b35eec27 -Author: Paulo Cesar Pereira de Andrade -Date: Sun Mar 2 14:49:21 2008 -0500 - - [PATCH] Ensure symbols used by other modules are visible. - - The xf86-video-ati drivers are one of the cases where LoaderSymbol is - widely used in some obscure ways. This patch fixes the problem, and - allows compiling with -fvisibility=hidden. - -commit a4398ac3ad77216f2c8aa628425bef5f2912a0a9 -Author: Alex Deucher -Date: Sat Mar 1 18:52:26 2008 -0500 - - RS6xx: change isIGP checks to CHIP_FAMILY_RS690 - - these paths are only relevant on RS6xx chips - -commit 67d4d04836c05293b844bc505f303cfb04c0f8a4 -Author: Alex Deucher -Date: Sat Mar 1 18:33:18 2008 -0500 - - RADEON: use xf86SetDesiredModes() in screeninit and enterVT - - this should restore the proper output state on VT switches - -commit be0858a84fbdf74c0b844f462933a221d48c707d -Author: Maciej Cencora -Date: Sat Mar 1 18:11:58 2008 -0500 - - RADEON: remove driver rec copies of mc info, use save rec directly - - info->mc_* were used and the immediately copied into info->ModeReg - ones. Just use the ModeReg copies directly. - -commit dd8ee1b444f4b973a1e0fadca5f943f2162b5e94 -Author: Alex Deucher -Date: Sat Mar 1 16:23:51 2008 -0500 - - RADEON: memmap rework 1 - - Don't restore memmap regs on every mode switch. - Just do memmap save/restore/setup on server start and VT switch. - -commit 1f6a23000001f3d1c21b5c04f94714a8caa7aa8b -Author: Alex Deucher -Date: Sat Mar 1 15:53:42 2008 -0500 - - RADEON: only restore legacy dac regs on legacy radeons - -commit dee6cef8e62d0651c00319e03eea92940fd24aa4 -Author: Alex Deucher -Date: Sat Mar 1 14:39:32 2008 -0500 - - RS4xx: enable exa render accel and textured video - - RS6xx paths seem to work fine on RS4xx - -commit 129f737efe4e8d1a368e7db4b063bdcd9339cb09 -Author: Alex Deucher -Date: Sat Mar 1 14:32:30 2008 -0500 - - AVIVO: save/restore regs by block - - Save/Restore the entire block for each output. - This should fix VT switch problems. - -commit b069aadaa63a95d7a71b5cfbab83577b49501094 -Author: Alex Deucher -Date: Fri Feb 29 22:36:02 2008 -0500 - - AVIVO: LVDS panels need dithering enabled - - Fixes bug 14760 - -commit fe87bdee815372b4b4d7d4c705e34681625b90f2 -Author: Alex Deucher -Date: Fri Feb 29 13:10:13 2008 -0500 - - AVIVO: disable pageflipping on avivo chips until we have proper drm support - -commit fb3678c7f511d539a51cd090cb8b5041d7d2ba26 -Author: Alex Deucher -Date: Fri Feb 29 13:01:21 2008 -0500 - - R5xx: fix register count when sending fragment program for textured video - -commit a66d37d1a896ec934989592457c2beff8e6f1639 -Author: Alex Deucher -Date: Fri Feb 29 04:07:05 2008 -0500 - - fix off-by-one in last commit - -commit e56062960be0c8d3947861dd5e0691fce6516b99 -Author: Alex Deucher -Date: Thu Feb 28 19:16:39 2008 -0500 - - AVIVO: save/restore scaler regs - -commit ae1c39a9b3e666404d0931679c9078c2e125a8bc -Author: Alex Deucher -Date: Thu Feb 28 18:53:55 2008 -0500 - - RS6xx: rework output parsing - - Turns out it's not as complex as I originially thought. - IGP chips just have non-standard GPIO entires for DDC. - -commit d8d6c9fe4ae7e1ab67dd041a251e901d97c29ed6 -Author: Alex Deucher -Date: Thu Feb 28 17:01:14 2008 -0500 - - RS6xx: fix typos in previous commit - - Noted by Maciej Cencora on IRC - -commit 46547ae8bdbc5c10f1fd028b95ec4c5c31a5b318 -Author: Alex Deucher -Date: Thu Feb 28 14:29:30 2008 -0500 - - AVIVO: disable dithering on DFPs - - This should fix the color banding some people have noticed. - Also save/restore DDIA regs on RS6xx - -commit 72a53d6f20ac29b3baddb7d8af04f19b76d2e04f -Author: Michel Dänzer -Date: Thu Feb 28 17:38:04 2008 +0100 - - Handle EXA coordinate limits more cleverly. - - Generally set the 2D engine limits, and only enforce the 3D engine limits in the - CheckComposite hook. This should still prevent useless migration of pixmaps the - 3D engine can't handle but allows for basic acceleration of bigger ones. - - Fixes http://bugs.freedesktop.org/show_bug.cgi?id=14708 . - -commit 5249f450a2487475a95531603cc8668db2c21c33 -Author: Michel Dänzer -Date: Thu Feb 28 12:23:58 2008 +0100 - - Fix 16 bit packed YUV XVideo playback on big endian systems with DRI disabled. - - http://bugs.freedesktop.org/show_bug.cgi?id=14668 - -commit e40d75fd8b2aece9dae8076fac822a4a83025fb2 -Author: Alex Deucher -Date: Wed Feb 27 22:53:10 2008 -0500 - - R500: fragment program clean up and magic number conversion - -commit 140dadba36b2191f0e18e41dd987785abd5f55d2 -Author: Alex Deucher -Date: Wed Feb 27 22:21:12 2008 -0500 - - R300: fix up magic numbers in fragment program - -commit e521476bb5e2dfabc93747e43eb911a8a101357e -Author: Alex Deucher -Date: Wed Feb 27 21:26:55 2008 -0500 - - R300/R400: bump up the clip limits for textured video - - This allows up to 2560x2560 (hw limit) - -commit 10db46f11d7e1c055c9ad6034c65ad163dad17dc -Author: Alex Deucher -Date: Wed Feb 27 15:28:50 2008 -0500 - - AVIVO: make sure we select the right LUT for each crtc - -commit ea944f38dcfd871b27345698afea1cb986ecb049 -Author: Alex Deucher -Date: Wed Feb 27 14:37:52 2008 -0500 - - R300+: update RADEONCP_REFRESH() to reflect new location of scissor regs - -commit b865faf95666e2172c3eec143f77fe9c524e4983 -Author: Alex Deucher -Date: Wed Feb 27 14:05:44 2008 -0500 - - R100/R200: move r100/r200 specific 3D setup into appropriate blocks - - R3xx+ doesn't have these regs. - -commit 3de2dc88cf26ff5932f11cecdf975777b8aa2a4a -Author: Adam Jackson -Date: Wed Jan 16 14:55:05 2008 -0500 - - Bump CRTC size limits on AVIVO chips so 30" displays work without tweaking. - - Note that the CRTC size limits we're using right now are _not_ the - hardware limits, they're just heuristics until we can resize the front - buffer properly. diff --git a/configure.ac b/configure.ac -index 2412d4f..a63f5e8 100644 +index 2412d4f..9ac46f7 100644 --- a/configure.ac +++ b/configure.ac +@@ -22,7 +22,7 @@ + + AC_PREREQ(2.57) + AC_INIT([xf86-video-ati], +- 6.8.0, ++ 6.8.192, + [https://bugs.freedesktop.org/enter_bug.cgi?product=xorg], + xf86-video-ati) + @@ -176,6 +176,18 @@ AC_CHECK_DECL(xf86_crtc_clip_video_helper, #include "xf86i2c.h" #include "xf86Crtc.h"]) @@ -1513,10 +30,68 @@ index 2412d4f..a63f5e8 100644 AC_CHECK_DECL(XSERVER_LIBPCIACCESS, [XSERVER_LIBPCIACCESS=yes],[XSERVER_LIBPCIACCESS=no], [#include "xorg-server.h"]) -@@ -232,6 +244,11 @@ if test "x$XSERVER_LIBPCIACCESS" = xyes; then +@@ -232,6 +244,69 @@ if test "x$XSERVER_LIBPCIACCESS" = xyes; then fi AM_CONDITIONAL(XSERVER_LIBPCIACCESS, test "x$XSERVER_LIBPCIACCESS" = xyes) ++# Checks for headers/macros for byte swapping ++# Known variants: ++# bswap_16, bswap_32, bswap_64 (glibc) ++# __swap16, __swap32, __swap64 (OpenBSD) ++# bswap16, bswap32, bswap64 (other BSD's) ++# and a fallback to local macros if none of the above are found ++ ++# if is found, assume it's the correct version ++AC_CHECK_HEADERS([byteswap.h]) ++ ++# if is found, have to check which version ++AC_CHECK_HEADER([sys/endian.h], [HAVE_SYS_ENDIAN_H="yes"], [HAVE_SYS_ENDIAN_H="no"]) ++ ++if test "x$HAVE_SYS_ENDIAN_H" = "xyes" ; then ++ AC_MSG_CHECKING([for __swap16 variant of byteswapping macros]) ++ AC_LINK_IFELSE([AC_LANG_PROGRAM([ ++#include ++ ], [ ++int a = 1, b; ++b = __swap16(a); ++ ]) ++], [SYS_ENDIAN__SWAP='yes'], [SYS_ENDIAN__SWAP='no']) ++ AC_MSG_RESULT([$SYS_ENDIAN__SWAP]) ++ ++ AC_MSG_CHECKING([for bswap16 variant of byteswapping macros]) ++ AC_LINK_IFELSE([AC_LANG_PROGRAM([ ++#include ++ ], [ ++int a = 1, b; ++b = bswap16(a); ++ ]) ++], [SYS_ENDIAN_BSWAP='yes'], [SYS_ENDIAN_BSWAP='no']) ++ AC_MSG_RESULT([$SYS_ENDIAN_BSWAP]) ++ ++ if test "$SYS_ENDIAN_BSWAP" = "yes" ; then ++ USE_SYS_ENDIAN_H=yes ++ BSWAP=bswap ++ else ++ if test "$SYS_ENDIAN__SWAP" = "yes" ; then ++ USE_SYS_ENDIAN_H=yes ++ BSWAP=__swap ++ else ++ USE_SYS_ENDIAN_H=no ++ fi ++ fi ++ ++ if test "$USE_SYS_ENDIAN_H" = "yes" ; then ++ AC_DEFINE([USE_SYS_ENDIAN_H], 1, ++ [Define to use byteswap macros from ]) ++ AC_DEFINE_UNQUOTED([bswap_16], ${BSWAP}16, ++ [Define to 16-bit byteswap macro]) ++ AC_DEFINE_UNQUOTED([bswap_32], ${BSWAP}32, ++ [Define to 32-bit byteswap macro]) ++ AC_DEFINE_UNQUOTED([bswap_64], ${BSWAP}64, ++ [Define to 64-bit byteswap macro]) ++ fi ++fi ++ +case $host_os in + *linux*) + AC_DEFINE(FGL_LINUX, 1, [Use linux pragma pack]) ;; @@ -1535,10 +110,61 @@ index 2d11006..93ff52c 100644 # Copyright 2005 Sun Microsystems, Inc. All rights reserved. # diff --git a/man/radeon.man b/man/radeon.man -index 86be965..ac6ea40 100644 +index 86be965..03622a0 100644 --- a/man/radeon.man +++ b/man/radeon.man -@@ -422,6 +422,14 @@ internal TMDS controller. +@@ -52,11 +52,11 @@ Radeon 9100 IGP + .B RS350 + Radeon 9200 IGP + .TP 12 +-.B RS400 +-Radeon XPRESS 200/200M IGP ++.B RS400/RS480 ++Radeon XPRESS 200(M)/1100 IGP + .TP 12 + .B RV280 +-Radeon 9200PRO/9200/9200SE, M9+ ++Radeon 9200PRO/9200/9200SE/9250, M9+ + .TP 12 + .B R300 + Radeon 9700PRO/9700/9500PRO/9500/9600TX, FireGL X1/Z1 +@@ -68,9 +68,9 @@ Radeon 9800PRO/9800SE/9800, FireGL X2 + Radeon 9800XT + .TP 12 + .B RV350 +-Radeon 9600PRO/9600SE/9600, M10/M11, FireGL T2 ++Radeon 9600PRO/9600SE/9600/9550, M10/M11, FireGL T2 + .TP 12 +-.B RV360 ++.B RV360 + Radeon 9600XT + .TP 12 + .B RV370 +@@ -91,8 +91,8 @@ Radeon X800, M28 PCIE + .B R480/R481 + Radeon X850 PCIE/AGP + .TP 12 +-.B RV515 +-Radeon X1300/X1400/X1500 ++.B RV505/RV515/RV516/RV550 ++Radeon X1300/X1400/X1500/X2300 + .TP 12 + .B R520 + Radeon X1800 +@@ -114,6 +114,12 @@ Radeon HD 2400/2600 + .TP 12 + .B RV670 + Radeon HD 3850/3870 ++.TP 12 ++.B RV620/RV635 ++Radeon HD 3450/3470 ++.TP 12 ++.B RS780 ++Radeon HD 3200 + + .SH CONFIGURATION DETAILS + Please refer to __xconfigfile__(__filemansuffix__) for general configuration +@@ -422,6 +428,14 @@ internal TMDS controller. The default is .B off. .TP @@ -1553,6 +179,61 @@ index 86be965..ac6ea40 100644 .BI "Option \*qDRI\*q \*q" boolean \*q Enable DRI support. This option allows you to enable to disable the DRI. The default is +@@ -497,6 +511,12 @@ LVDS as attached. + The default is + .B on. + .TP ++.BI "Option \*qInt10\*q \*q" boolean \*q ++This option allows you to disable int10 initialization. Set this to ++False if you are experiencing a hang when initializing a secondary card. ++The default is ++.B on. ++.TP + + .SH SEE ALSO + __xservername__(__appmansuffix__), __xconfigfile__(__filemansuffix__), xorgconfig(__appmansuffix__), Xserver(__appmansuffix__), X(__miscmansuffix__) +diff --git a/src/AtomBios/CD_Operations.c b/src/AtomBios/CD_Operations.c +index 1e48f81..509aa0c 100644 +--- a/src/AtomBios/CD_Operations.c ++++ b/src/AtomBios/CD_Operations.c +@@ -36,10 +36,15 @@ Revision History: + --*/ + #define __SW_4 + +-#include "Decoder.h" +-#include "atombios.h" ++#ifdef HAVE_CONFIG_H ++#include "config.h" ++#endif + ++#include ++#include "xorg-server.h" + ++#include "Decoder.h" ++#include "atombios.h" + + VOID PutDataRegister(PARSER_TEMP_DATA STACK_BASED * pParserTempData); + VOID PutDataPS(PARSER_TEMP_DATA STACK_BASED * pParserTempData); +diff --git a/src/AtomBios/Decoder.c b/src/AtomBios/Decoder.c +index cdaa9ef..e8b3b6e 100644 +--- a/src/AtomBios/Decoder.c ++++ b/src/AtomBios/Decoder.c +@@ -34,7 +34,14 @@ Revision History: + + NEG:24.09.2002 Initiated. + --*/ +-//#include "AtomBios.h" ++ ++#ifdef HAVE_CONFIG_H ++#include "config.h" ++#endif ++ ++#include ++ ++ + #include "Decoder.h" + #include "atombios.h" + #include "CD_binding.h" diff --git a/src/AtomBios/includes/CD_Common_Types.h b/src/AtomBios/includes/CD_Common_Types.h index 44a0b35..c60b652 100644 --- a/src/AtomBios/includes/CD_Common_Types.h @@ -2515,6 +1196,126 @@ index e6d41fe..4b106cf 100644 + + + +diff --git a/src/AtomBios/includes/atombios.h b/src/AtomBios/includes/atombios.h +index 16fcf2d..17483a6 100644 +--- a/src/AtomBios/includes/atombios.h ++++ b/src/AtomBios/includes/atombios.h +@@ -304,9 +304,15 @@ typedef struct _ATOM_MASTER_COMMAND_TABLE + + typedef struct _ATOM_TABLE_ATTRIBUTE + { ++#if X_BYTE_ORDER == X_BIG_ENDIAN ++ USHORT UpdatedByUtility:1; //[15]=Table updated by utility flag ++ USHORT PS_SizeInBytes:7; //[14:8]=Size of parameter space in Bytes (multiple of a dword), ++ USHORT WS_SizeInBytes:8; //[7:0]=Size of workspace in Bytes (in multiple of a dword), ++#else + USHORT WS_SizeInBytes:8; //[7:0]=Size of workspace in Bytes (in multiple of a dword), + USHORT PS_SizeInBytes:7; //[14:8]=Size of parameter space in Bytes (multiple of a dword), + USHORT UpdatedByUtility:1; //[15]=Table updated by utility flag ++#endif + }ATOM_TABLE_ATTRIBUTE; + + // Common header for all command tables. +@@ -1252,6 +1258,19 @@ typedef struct _ATOM_MULTIMEDIA_CONFIG_INFO + //Please don't add or expand this bitfield structure below, this one will retire soon.! + typedef struct _ATOM_FIRMWARE_CAPABILITY + { ++#if X_BYTE_ORDER == X_BIG_ENDIAN ++ USHORT Reserved:3; ++ USHORT HyperMemory_Size:4; ++ USHORT HyperMemory_Support:1; ++ USHORT PPMode_Assigned:1; ++ USHORT WMI_SUPPORT:1; ++ USHORT GPUControlsBL:1; ++ USHORT EngineClockSS_Support:1; ++ USHORT MemoryClockSS_Support:1; ++ USHORT ExtendedDesktopSupport:1; ++ USHORT DualCRTC_Support:1; ++ USHORT FirmwarePosted:1; ++#else + USHORT FirmwarePosted:1; + USHORT DualCRTC_Support:1; + USHORT ExtendedDesktopSupport:1; +@@ -1263,6 +1282,7 @@ typedef struct _ATOM_FIRMWARE_CAPABILITY + USHORT HyperMemory_Support:1; + USHORT HyperMemory_Size:4; + USHORT Reserved:3; ++#endif + }ATOM_FIRMWARE_CAPABILITY; + + typedef union _ATOM_FIRMWARE_CAPABILITY_ACCESS +@@ -1747,9 +1767,15 @@ for Griffin or Greyhound. SBIOS needs to convert to actual time by: + + typedef struct _ATOM_I2C_ID_CONFIG + { ++#if X_BYTE_ORDER == X_BIG_ENDIAN ++ UCHAR bfHW_Capable:1; ++ UCHAR bfHW_EngineID:3; ++ UCHAR bfI2C_LineMux:4; ++#else + UCHAR bfI2C_LineMux:4; + UCHAR bfHW_EngineID:3; + UCHAR bfHW_Capable:1; ++#endif + }ATOM_I2C_ID_CONFIG; + + typedef union _ATOM_I2C_ID_CONFIG_ACCESS +@@ -1794,6 +1820,19 @@ typedef struct _ATOM_GPIO_I2C_INFO + //Please don't add or expand this bitfield structure below, this one will retire soon.! + typedef struct _ATOM_MODE_MISC_INFO + { ++#if X_BYTE_ORDER == X_BIG_ENDIAN ++ USHORT Reserved:6; ++ USHORT RGB888:1; ++ USHORT DoubleClock:1; ++ USHORT Interlace:1; ++ USHORT CompositeSync:1; ++ USHORT V_ReplicationBy2:1; ++ USHORT H_ReplicationBy2:1; ++ USHORT VerticalCutOff:1; ++ USHORT VSyncPolarity:1; //0=Active High, 1=Active Low ++ USHORT HSyncPolarity:1; //0=Active High, 1=Active Low ++ USHORT HorizontalCutOff:1; ++#else + USHORT HorizontalCutOff:1; + USHORT HSyncPolarity:1; //0=Active High, 1=Active Low + USHORT VSyncPolarity:1; //0=Active High, 1=Active Low +@@ -1805,6 +1844,7 @@ typedef struct _ATOM_MODE_MISC_INFO + USHORT DoubleClock:1; + USHORT RGB888:1; + USHORT Reserved:6; ++#endif + }ATOM_MODE_MISC_INFO; + + typedef union _ATOM_MODE_MISC_INFO_ACCESS +@@ -3386,8 +3426,13 @@ typedef struct _ATOM_MEMORY_VENDOR_BLOCK{ + + + typedef struct _ATOM_MEMORY_SETTING_ID_CONFIG{ ++#if X_BYTE_ORDER == X_BIG_ENDIAN ++ ULONG ucMemBlkId:8; ++ ULONG ulMemClockRange:24; ++#else + ULONG ulMemClockRange:24; + ULONG ucMemBlkId:8; ++#endif + }ATOM_MEMORY_SETTING_ID_CONFIG; + + typedef union _ATOM_MEMORY_SETTING_ID_CONFIG_ACCESS +@@ -4027,8 +4072,13 @@ typedef struct _COMPASSIONATE_DATA + + typedef struct _ATOM_CONNECTOR_INFO + { ++#if X_BYTE_ORDER == X_BIG_ENDIAN ++ UCHAR bfConnectorType:4; ++ UCHAR bfAssociatedDAC:4; ++#else + UCHAR bfAssociatedDAC:4; + UCHAR bfConnectorType:4; ++#endif + }ATOM_CONNECTOR_INFO; + + typedef union _ATOM_CONNECTOR_INFO_ACCESS diff --git a/src/Makefile.am b/src/Makefile.am index 70c05e5..5333495 100644 --- a/src/Makefile.am @@ -2580,9 +1381,25 @@ index 828aae1..86c40a1 100644 + #endif /* ___ATI_H___ */ diff --git a/src/ati_pciids_gen.h b/src/ati_pciids_gen.h -index 330d1a9..eee1d60 100644 +index 330d1a9..a740df8 100644 --- a/src/ati_pciids_gen.h +++ b/src/ati_pciids_gen.h +@@ -173,6 +173,7 @@ + #define PCI_CHIP_RV410_564F 0x564F + #define PCI_CHIP_RV410_5652 0x5652 + #define PCI_CHIP_RV410_5653 0x5653 ++#define PCI_CHIP_RV410_5657 0x5657 + #define PCI_CHIP_MACH64VT 0x5654 + #define PCI_CHIP_MACH64VU 0x5655 + #define PCI_CHIP_MACH64VV 0x5656 +@@ -195,7 +196,6 @@ + #define PCI_CHIP_RV370_5B60 0x5B60 + #define PCI_CHIP_RV370_5B62 0x5B62 + #define PCI_CHIP_RV370_5B63 0x5B63 +-#define PCI_CHIP_RV370_5657 0x5657 + #define PCI_CHIP_RV370_5B64 0x5B64 + #define PCI_CHIP_RV370_5B65 0x5B65 + #define PCI_CHIP_RV280_5C61 0x5C61 @@ -281,9 +281,9 @@ #define PCI_CHIP_RV530_71D6 0x71D6 #define PCI_CHIP_RV530_71DA 0x71DA @@ -2643,7 +1460,7 @@ index c249333..f0eb147 100644 static XF86ModuleVersionInfo ATIVersionRec = diff --git a/src/atombios_crtc.c b/src/atombios_crtc.c -index bc2df18..b5b7ca8 100644 +index bc2df18..363addf 100644 --- a/src/atombios_crtc.c +++ b/src/atombios_crtc.c @@ -1,10 +1,5 @@ @@ -2743,7 +1560,7 @@ index bc2df18..b5b7ca8 100644 break; } } -@@ -151,24 +161,34 @@ atombios_set_crtc_timing(atomBiosHandlePtr atomBIOS, SET_CRTC_TIMING_PARAMETERS_ +@@ -151,24 +161,33 @@ atombios_set_crtc_timing(atomBiosHandlePtr atomBIOS, SET_CRTC_TIMING_PARAMETERS_ } void @@ -2777,14 +1594,13 @@ index bc2df18..b5b7ca8 100644 - RADEONComputePLL(&info->pll, mode->Clock, &temp, &fb_div, &ref_div, &post_div, 0); + uint32_t temp; + -+ if (IS_DCE3_VARIANT) -+ pll_flags |= RADEON_PLL_DCE3; ++ pll_flags |= RADEON_PLL_PREFER_LOW_REF_DIV; + + RADEONComputePLL(&info->pll, mode->Clock, &temp, &fb_div, &ref_div, &post_div, pll_flags); sclock = temp; /* disable spread spectrum clocking for now -- thanks Hedy Lamarr */ -@@ -193,25 +213,86 @@ atombios_crtc_set_pll(xf86CrtcPtr crtc, DisplayModePtr mode) +@@ -193,25 +212,86 @@ atombios_crtc_set_pll(xf86CrtcPtr crtc, DisplayModePtr mode) "crtc(%d) PLL : refdiv %u, fbdiv 0x%X(%u), pdiv %u\n", radeon_crtc->crtc_id, (unsigned int)ref_div, (unsigned int)fb_div, (unsigned int)fb_div, (unsigned int)post_div); @@ -2881,7 +1697,7 @@ index bc2df18..b5b7ca8 100644 default: ErrorF("Unknown table version\n"); exit(-1); -@@ -247,26 +328,16 @@ atombios_crtc_mode_set(xf86CrtcPtr crtc, +@@ -247,26 +327,16 @@ atombios_crtc_mode_set(xf86CrtcPtr crtc, xf86CrtcConfigPtr xf86_config = XF86_CRTC_CONFIG_PTR(pScrn); unsigned char *RADEONMMIO = info->MMIO; unsigned long fb_location = crtc->scrn->fbOffset + info->fbLocation; @@ -2912,7 +1728,7 @@ index bc2df18..b5b7ca8 100644 } for (i = 0; i < xf86_config->num_output; i++) { -@@ -283,6 +354,9 @@ atombios_crtc_mode_set(xf86CrtcPtr crtc, +@@ -283,6 +353,9 @@ atombios_crtc_mode_set(xf86CrtcPtr crtc, need_tv_timings = 2; } @@ -2922,7 +1738,7 @@ index bc2df18..b5b7ca8 100644 } } -@@ -334,27 +408,25 @@ atombios_crtc_mode_set(xf86CrtcPtr crtc, +@@ -334,27 +407,25 @@ atombios_crtc_mode_set(xf86CrtcPtr crtc, RADEONRestoreMemMapRegisters(pScrn, info->ModeReg); if (IS_AVIVO_VARIANT) { @@ -2956,7 +1772,7 @@ index bc2df18..b5b7ca8 100644 } if (radeon_crtc->crtc_id == 0) -@@ -376,17 +448,14 @@ atombios_crtc_mode_set(xf86CrtcPtr crtc, +@@ -376,17 +447,14 @@ atombios_crtc_mode_set(xf86CrtcPtr crtc, OUTREG(AVIVO_D1GRPH_PRIMARY_SURFACE_ADDRESS + radeon_crtc->crtc_offset, fb_location); OUTREG(AVIVO_D1GRPH_SECONDARY_SURFACE_ADDRESS + radeon_crtc->crtc_offset, fb_location); @@ -2979,7 +1795,7 @@ index bc2df18..b5b7ca8 100644 OUTREG(AVIVO_D1GRPH_PITCH + radeon_crtc->crtc_offset, crtc->scrn->displayWidth); OUTREG(AVIVO_D1GRPH_ENABLE + radeon_crtc->crtc_offset, 1); -@@ -398,7 +467,7 @@ atombios_crtc_mode_set(xf86CrtcPtr crtc, +@@ -398,7 +466,7 @@ atombios_crtc_mode_set(xf86CrtcPtr crtc, OUTREG(AVIVO_D1SCL_UPDATE + radeon_crtc->crtc_offset, AVIVO_D1SCL_UPDATE_LOCK); OUTREG(AVIVO_D1MODE_DESKTOP_HEIGHT + radeon_crtc->crtc_offset, @@ -2988,7 +1804,7 @@ index bc2df18..b5b7ca8 100644 OUTREG(AVIVO_D1MODE_VIEWPORT_START + radeon_crtc->crtc_offset, (x << 16) | y); OUTREG(AVIVO_D1MODE_VIEWPORT_SIZE + radeon_crtc->crtc_offset, (mode->HDisplay << 16) | mode->VDisplay); -@@ -407,11 +476,11 @@ atombios_crtc_mode_set(xf86CrtcPtr crtc, +@@ -407,11 +475,11 @@ atombios_crtc_mode_set(xf86CrtcPtr crtc, } @@ -3620,10 +2436,20 @@ index 6197eab..a04baa1 100644 } GENERIC_BUS_Rec; diff --git a/src/legacy_crtc.c b/src/legacy_crtc.c -index 06ad60c..489fecf 100644 +index 06ad60c..3df61a7 100644 --- a/src/legacy_crtc.c +++ b/src/legacy_crtc.c -@@ -78,6 +78,14 @@ RADEONRestoreCommonRegisters(ScrnInfoPtr pScrn, +@@ -51,6 +51,9 @@ + #include "radeon_dri.h" + #include "radeon_sarea.h" + #include "sarea.h" ++#ifdef DRM_IOCTL_MODESET_CTL ++#include ++#endif + #endif + + /* Write common registers */ +@@ -78,6 +81,14 @@ RADEONRestoreCommonRegisters(ScrnInfoPtr pScrn, OUTREG(RADEON_BUS_CNTL, restore->bus_cntl); OUTREG(RADEON_SURFACE_CNTL, restore->surface_cntl); @@ -3638,7 +2464,7 @@ index 06ad60c..489fecf 100644 /* Workaround for the VT switching problem in dual-head mode. This * problem only occurs on RV style chips, typically when a FP and * CRT are connected. -@@ -85,7 +93,7 @@ RADEONRestoreCommonRegisters(ScrnInfoPtr pScrn, +@@ -85,7 +96,7 @@ RADEONRestoreCommonRegisters(ScrnInfoPtr pScrn, if (pRADEONEnt->HasCRTC2 && info->ChipFamily != CHIP_FAMILY_R200 && !IS_R300_VARIANT) { @@ -3647,7 +2473,7 @@ index 06ad60c..489fecf 100644 tmp = INREG(RADEON_DAC_CNTL2); OUTREG(RADEON_DAC_CNTL2, tmp & ~RADEON_DAC2_DAC_CLK_SEL); -@@ -148,7 +156,7 @@ RADEONRestoreCrtc2Registers(ScrnInfoPtr pScrn, +@@ -148,7 +159,7 @@ RADEONRestoreCrtc2Registers(ScrnInfoPtr pScrn, { RADEONInfoPtr info = RADEONPTR(pScrn); unsigned char *RADEONMMIO = info->MMIO; @@ -3656,7 +2482,7 @@ index 06ad60c..489fecf 100644 xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG, "Programming CRTC2, offset: 0x%08x\n", -@@ -178,12 +186,6 @@ RADEONRestoreCrtc2Registers(ScrnInfoPtr pScrn, +@@ -178,12 +189,6 @@ RADEONRestoreCrtc2Registers(ScrnInfoPtr pScrn, OUTREG(RADEON_CRTC2_PITCH, restore->crtc2_pitch); OUTREG(RADEON_DISP2_MERGE_CNTL, restore->disp2_merge_cntl); @@ -3669,7 +2495,7 @@ index 06ad60c..489fecf 100644 OUTREG(RADEON_CRTC2_GEN_CNTL, restore->crtc2_gen_cntl); } -@@ -238,9 +240,9 @@ RADEONPLL2WriteUpdate(ScrnInfoPtr pScrn) +@@ -238,9 +243,9 @@ RADEONPLL2WriteUpdate(ScrnInfoPtr pScrn) ~(RADEON_P2PLL_ATOMIC_UPDATE_W)); } @@ -3682,7 +2508,7 @@ index 06ad60c..489fecf 100644 { unsigned vcoFreq; -@@ -277,7 +279,7 @@ RADEONRestorePLLRegisters(ScrnInfoPtr pScrn, +@@ -277,7 +282,7 @@ RADEONRestorePLLRegisters(ScrnInfoPtr pScrn, { RADEONInfoPtr info = RADEONPTR(pScrn); unsigned char *RADEONMMIO = info->MMIO; @@ -3691,7 +2517,7 @@ index 06ad60c..489fecf 100644 #if defined(__powerpc__) /* apparently restoring the pll causes a hang??? */ -@@ -316,7 +318,7 @@ RADEONRestorePLLRegisters(ScrnInfoPtr pScrn, +@@ -316,7 +321,7 @@ RADEONRestorePLLRegisters(ScrnInfoPtr pScrn, RADEON_PPLL_RESET | RADEON_PPLL_ATOMIC_UPDATE_EN | RADEON_PPLL_VGA_ATOMIC_UPDATE_EN @@ -3700,7 +2526,7 @@ index 06ad60c..489fecf 100644 ~(RADEON_PPLL_RESET | RADEON_PPLL_ATOMIC_UPDATE_EN | RADEON_PPLL_VGA_ATOMIC_UPDATE_EN -@@ -329,7 +331,8 @@ RADEONRestorePLLRegisters(ScrnInfoPtr pScrn, +@@ -329,7 +334,8 @@ RADEONRestorePLLRegisters(ScrnInfoPtr pScrn, if (IS_R300_VARIANT || (info->ChipFamily == CHIP_FAMILY_RS300) || @@ -3710,7 +2536,7 @@ index 06ad60c..489fecf 100644 if (restore->ppll_ref_div & R300_PPLL_REF_DIV_ACC_MASK) { /* When restoring console mode, use saved PPLL_REF_DIV * setting. -@@ -399,7 +402,7 @@ RADEONRestorePLL2Registers(ScrnInfoPtr pScrn, +@@ -399,7 +405,7 @@ RADEONRestorePLL2Registers(ScrnInfoPtr pScrn, RADEONSavePtr restore) { RADEONInfoPtr info = RADEONPTR(pScrn); @@ -3719,7 +2545,7 @@ index 06ad60c..489fecf 100644 pllGain = RADEONComputePLLGain(info->pll.reference_freq, restore->p2pll_ref_div & RADEON_P2PLL_REF_DIV_MASK, -@@ -414,7 +417,7 @@ RADEONRestorePLL2Registers(ScrnInfoPtr pScrn, +@@ -414,7 +420,7 @@ RADEONRestorePLL2Registers(ScrnInfoPtr pScrn, RADEON_P2PLL_CNTL, RADEON_P2PLL_RESET | RADEON_P2PLL_ATOMIC_UPDATE_EN @@ -3728,7 +2554,7 @@ index 06ad60c..489fecf 100644 ~(RADEON_P2PLL_RESET | RADEON_P2PLL_ATOMIC_UPDATE_EN | RADEON_P2PLL_PVG_MASK)); -@@ -489,6 +492,14 @@ RADEONSaveCommonRegisters(ScrnInfoPtr pScrn, RADEONSavePtr save) +@@ -489,6 +495,14 @@ RADEONSaveCommonRegisters(ScrnInfoPtr pScrn, RADEONSavePtr save) save->surface_cntl = INREG(RADEON_SURFACE_CNTL); save->grph_buffer_cntl = INREG(RADEON_GRPH_BUFFER_CNTL); save->grph2_buffer_cntl = INREG(RADEON_GRPH2_BUFFER_CNTL); @@ -3743,7 +2569,7 @@ index 06ad60c..489fecf 100644 } /* Read CRTC registers */ -@@ -550,13 +561,6 @@ RADEONSaveCrtc2Registers(ScrnInfoPtr pScrn, RADEONSavePtr save) +@@ -550,13 +564,6 @@ RADEONSaveCrtc2Registers(ScrnInfoPtr pScrn, RADEONSavePtr save) save->fp_h2_sync_strt_wid = INREG (RADEON_FP_H2_SYNC_STRT_WID); save->fp_v2_sync_strt_wid = INREG (RADEON_FP_V2_SYNC_STRT_WID); @@ -3757,7 +2583,55 @@ index 06ad60c..489fecf 100644 save->disp2_merge_cntl = INREG(RADEON_DISP2_MERGE_CNTL); /* track if the crtc is enabled for text restore */ -@@ -677,6 +681,15 @@ RADEONInitCommonRegisters(RADEONSavePtr save, RADEONInfoPtr info) +@@ -611,16 +618,32 @@ RADEONSavePLL2Registers(ScrnInfoPtr pScrn, RADEONSavePtr save) + } + + void ++radeon_crtc_modeset_ioctl(xf86CrtcPtr crtc, Bool post) ++{ ++#if defined(XF86DRI) && defined(DRM_IOCTL_MODESET_CTL) ++ RADEONInfoPtr info = RADEONPTR(crtc->scrn); ++ RADEONCrtcPrivatePtr radeon_crtc = crtc->driver_private; ++ struct drm_modeset_ctl modeset; ++ ++ modeset.crtc = radeon_crtc->crtc_id; ++ modeset.cmd = post ? _DRM_POST_MODESET : _DRM_PRE_MODESET; ++ ++ ioctl(info->drmFD, DRM_IOCTL_MODESET_CTL, &modeset); ++#endif ++} ++ ++void + legacy_crtc_dpms(xf86CrtcPtr crtc, int mode) + { + int mask; +- ScrnInfoPtr pScrn = crtc->scrn; + RADEONCrtcPrivatePtr radeon_crtc = crtc->driver_private; +- RADEONInfoPtr info = RADEONPTR(pScrn); +- unsigned char *RADEONMMIO = info->MMIO; ++ RADEONEntPtr pRADEONEnt = RADEONEntPriv(crtc->scrn); ++ unsigned char *RADEONMMIO = pRADEONEnt->MMIO; + + mask = radeon_crtc->crtc_id ? (RADEON_CRTC2_DISP_DIS | RADEON_CRTC2_VSYNC_DIS | RADEON_CRTC2_HSYNC_DIS | RADEON_CRTC2_DISP_REQ_EN_B) : (RADEON_CRTC_DISPLAY_DIS | RADEON_CRTC_HSYNC_DIS | RADEON_CRTC_VSYNC_DIS); + ++ if (mode == DPMSModeOff) ++ radeon_crtc_modeset_ioctl(crtc, FALSE); + + switch(mode) { + case DPMSModeOn: +@@ -657,8 +680,10 @@ legacy_crtc_dpms(xf86CrtcPtr crtc, int mode) + break; + } + +- if (mode != DPMSModeOff) ++ if (mode != DPMSModeOff) { ++ radeon_crtc_modeset_ioctl(crtc, TRUE); + radeon_crtc_load_lut(crtc); ++ } + } + + +@@ -677,6 +702,15 @@ RADEONInitCommonRegisters(RADEONSavePtr save, RADEONInfoPtr info) save->cap0_trig_cntl = 0; save->cap1_trig_cntl = 0; save->bus_cntl = info->BusCntl; @@ -3773,7 +2647,7 @@ index 06ad60c..489fecf 100644 /* * If bursts are enabled, turn on discards * Radeon doesn't have write bursts -@@ -1125,13 +1138,6 @@ RADEONInitCrtc2Registers(xf86CrtcPtr crtc, RADEONSavePtr save, +@@ -1125,13 +1159,6 @@ RADEONInitCrtc2Registers(xf86CrtcPtr crtc, RADEONSavePtr save, save->fp_h2_sync_strt_wid = save->crtc2_h_sync_strt_wid; save->fp_v2_sync_strt_wid = save->crtc2_v_sync_strt_wid; @@ -3787,7 +2661,7 @@ index 06ad60c..489fecf 100644 return TRUE; } -@@ -1143,10 +1149,10 @@ RADEONInitPLLRegisters(ScrnInfoPtr pScrn, RADEONSavePtr save, +@@ -1143,10 +1170,10 @@ RADEONInitPLLRegisters(ScrnInfoPtr pScrn, RADEONSavePtr save, int flags) { RADEONInfoPtr info = RADEONPTR(pScrn); @@ -3802,7 +2676,7 @@ index 06ad60c..489fecf 100644 struct { int divider; -@@ -1224,10 +1230,10 @@ RADEONInitPLL2Registers(ScrnInfoPtr pScrn, RADEONSavePtr save, +@@ -1224,10 +1251,10 @@ RADEONInitPLL2Registers(ScrnInfoPtr pScrn, RADEONSavePtr save, int flags) { RADEONInfoPtr info = RADEONPTR(pScrn); @@ -3817,7 +2691,7 @@ index 06ad60c..489fecf 100644 struct { int divider; -@@ -1306,16 +1312,16 @@ RADEONInitDispBandwidth2(ScrnInfoPtr pScrn, RADEONInfoPtr info, int pixel_bytes2 +@@ -1306,16 +1333,16 @@ RADEONInitDispBandwidth2(ScrnInfoPtr pScrn, RADEONInfoPtr info, int pixel_bytes2 RADEONEntPtr pRADEONEnt = RADEONEntPriv(pScrn); unsigned char *RADEONMMIO = info->MMIO; @@ -3841,7 +2715,7 @@ index 06ad60c..489fecf 100644 float MemTcas[8] = {0, 1, 2, 3, 0, 1.5, 2.5, 0}; float MemTcas2[8] = {0, 1, 2, 3, 4, 5, 6, 7}; -@@ -1338,7 +1344,7 @@ RADEONInitDispBandwidth2(ScrnInfoPtr pScrn, RADEONInfoPtr info, int pixel_bytes2 +@@ -1338,7 +1365,7 @@ RADEONInitDispBandwidth2(ScrnInfoPtr pScrn, RADEONInfoPtr info, int pixel_bytes2 * option. */ if ((info->DispPriority == 2) && IS_R300_VARIANT) { @@ -3850,7 +2724,7 @@ index 06ad60c..489fecf 100644 if (pRADEONEnt->pCrtc[1]->enabled) { mc_init_misc_lat_timer |= 0x1100; /* display 0 and 1 */ } else { -@@ -1512,7 +1518,7 @@ RADEONInitDispBandwidth2(ScrnInfoPtr pScrn, RADEONInfoPtr info, int pixel_bytes2 +@@ -1512,7 +1539,7 @@ RADEONInitDispBandwidth2(ScrnInfoPtr pScrn, RADEONInfoPtr info, int pixel_bytes2 /* Find the critical point of the display buffer. */ @@ -3859,7 +2733,7 @@ index 06ad60c..489fecf 100644 /* ???? */ /* -@@ -1554,6 +1560,25 @@ RADEONInitDispBandwidth2(ScrnInfoPtr pScrn, RADEONInfoPtr info, int pixel_bytes2 +@@ -1554,6 +1581,25 @@ RADEONInitDispBandwidth2(ScrnInfoPtr pScrn, RADEONInfoPtr info, int pixel_bytes2 OUTREG(RADEON_GRPH_BUFFER_CNTL, ((temp & ~RADEON_GRPH_CRITICAL_POINT_MASK) | (critical_point << RADEON_GRPH_CRITICAL_POINT_SHIFT))); @@ -3885,7 +2759,7 @@ index 06ad60c..489fecf 100644 xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG, "GRPH_BUFFER_CNTL from %x to %x\n", (unsigned int)info->SavedReg->grph_buffer_cntl, -@@ -1585,7 +1610,7 @@ RADEONInitDispBandwidth2(ScrnInfoPtr pScrn, RADEONInfoPtr info, int pixel_bytes2 +@@ -1585,7 +1631,7 @@ RADEONInitDispBandwidth2(ScrnInfoPtr pScrn, RADEONInfoPtr info, int pixel_bytes2 read_return_rate = MIN(info->sclk, info->mclk*(info->RamWidth*(info->IsDDR+1)/128)); time_disp1_drop_priority = critical_point / (read_return_rate - disp_drain_rate); @@ -3894,7 +2768,7 @@ index 06ad60c..489fecf 100644 disp_latency) * disp_drain_rate2 + 0.5); if (info->DispPriority == 2) { -@@ -1604,6 +1629,29 @@ RADEONInitDispBandwidth2(ScrnInfoPtr pScrn, RADEONInfoPtr info, int pixel_bytes2 +@@ -1604,6 +1650,29 @@ RADEONInitDispBandwidth2(ScrnInfoPtr pScrn, RADEONInfoPtr info, int pixel_bytes2 OUTREG(RADEON_GRPH2_BUFFER_CNTL, ((temp & ~RADEON_GRPH_CRITICAL_POINT_MASK) | (critical_point2 << RADEON_GRPH_CRITICAL_POINT_SHIFT))); @@ -3924,14 +2798,15 @@ index 06ad60c..489fecf 100644 xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG, "GRPH2_BUFFER_CNTL from %x to %x\n", (unsigned int)info->SavedReg->grph2_buffer_cntl, -@@ -1658,26 +1706,15 @@ legacy_crtc_mode_set(xf86CrtcPtr crtc, DisplayModePtr mode, +@@ -1658,26 +1727,15 @@ legacy_crtc_mode_set(xf86CrtcPtr crtc, DisplayModePtr mode, xf86CrtcConfigPtr xf86_config = XF86_CRTC_CONFIG_PTR(pScrn); RADEONCrtcPrivatePtr radeon_crtc = crtc->driver_private; RADEONInfoPtr info = RADEONPTR(pScrn); - Bool tilingOld = info->tilingEnabled; int i = 0; double dot_clock = 0; - int pll_flags = RADEON_PLL_LEGACY; +- int pll_flags = RADEON_PLL_LEGACY; ++ int pll_flags = RADEON_PLL_LEGACY | RADEON_PLL_PREFER_LOW_REF_DIV; Bool update_tv_routing = FALSE; - + Bool tilingChanged = FALSE; @@ -3954,7 +2829,7 @@ index 06ad60c..489fecf 100644 } for (i = 0; i < xf86_config->num_output; i++) { -@@ -1775,7 +1812,7 @@ legacy_crtc_mode_set(xf86CrtcPtr crtc, DisplayModePtr mode, +@@ -1775,7 +1833,7 @@ legacy_crtc_mode_set(xf86CrtcPtr crtc, DisplayModePtr mode, if (info->DispPriority) RADEONInitDispBandwidth(pScrn); @@ -3964,7 +2839,7 @@ index 06ad60c..489fecf 100644 /* if this is called during ScreenInit() we don't have pScrn->pScreen yet */ if (pScrn->pScreen) diff --git a/src/legacy_output.c b/src/legacy_output.c -index 0de13df..4df81ab 100644 +index 0de13df..9c9ebb9 100644 --- a/src/legacy_output.c +++ b/src/legacy_output.c @@ -71,7 +71,7 @@ RADEONRestoreDACRegisters(ScrnInfoPtr pScrn, @@ -4081,7 +2956,22 @@ index 0de13df..4df81ab 100644 if (radeon_output->MonType == MT_CRT) { if (radeon_output->DACType == DAC_PRIMARY) { info->output_crt1 |= (1 << o); -@@ -716,6 +735,14 @@ RADEONEnableDisplay(xf86OutputPtr output, BOOL bEnable) +@@ -708,6 +727,14 @@ RADEONEnableDisplay(xf86OutputPtr output, BOOL bEnable) + save->crtc2_gen_cntl |= RADEON_CRTC2_CRT2_ON; + } + tv_dac_change = 1; ++ /* IGP chips seem to use a mix of Primary and TVDAC controls */ ++ if (info->IsIGP) { ++ tmp = INREG(RADEON_CRTC_EXT_CNTL); ++ tmp |= RADEON_CRTC_CRT_ON; ++ OUTREG(RADEON_CRTC_EXT_CNTL, tmp); ++ save->crtc_ext_cntl |= RADEON_CRTC_CRT_ON; ++ RADEONDacPowerSet(pScrn, bEnable, TRUE); ++ } + } + } else if (radeon_output->MonType == MT_DFP) { + if (radeon_output->TMDSType == TMDS_INT) { +@@ -716,6 +743,14 @@ RADEONEnableDisplay(xf86OutputPtr output, BOOL bEnable) tmp |= (RADEON_FP_FPON | RADEON_FP_TMDS_EN); OUTREG(RADEON_FP_GEN_CNTL, tmp); save->fp_gen_cntl |= (RADEON_FP_FPON | RADEON_FP_TMDS_EN); @@ -4096,7 +2986,7 @@ index 0de13df..4df81ab 100644 } else if (radeon_output->TMDSType == TMDS_EXT) { info->output_dfp2 |= (1 << o); tmp = INREG(RADEON_FP2_GEN_CNTL); -@@ -724,6 +751,15 @@ RADEONEnableDisplay(xf86OutputPtr output, BOOL bEnable) +@@ -724,6 +759,15 @@ RADEONEnableDisplay(xf86OutputPtr output, BOOL bEnable) OUTREG(RADEON_FP2_GEN_CNTL, tmp); save->fp2_gen_cntl |= (RADEON_FP2_ON | RADEON_FP2_DVO_EN); save->fp2_gen_cntl &= ~RADEON_FP2_BLANK_EN; @@ -4112,7 +3002,7 @@ index 0de13df..4df81ab 100644 } } else if (radeon_output->MonType == MT_LCD) { info->output_lcd1 |= (1 << o); -@@ -744,7 +780,7 @@ RADEONEnableDisplay(xf86OutputPtr output, BOOL bEnable) +@@ -744,7 +788,7 @@ RADEONEnableDisplay(xf86OutputPtr output, BOOL bEnable) radeon_output->tv_on = TRUE; } } else { @@ -4121,7 +3011,22 @@ index 0de13df..4df81ab 100644 if (radeon_output->MonType == MT_CRT) { if (radeon_output->DACType == DAC_PRIMARY) { info->output_crt1 &= ~(1 << o); -@@ -780,6 +816,14 @@ RADEONEnableDisplay(xf86OutputPtr output, BOOL bEnable) +@@ -771,6 +815,14 @@ RADEONEnableDisplay(xf86OutputPtr output, BOOL bEnable) + save->crtc2_gen_cntl &= ~RADEON_CRTC2_CRT2_ON; + } + } ++ /* IGP chips seem to use a mix of Primary and TVDAC controls */ ++ if (info->IsIGP) { ++ tmp = INREG(RADEON_CRTC_EXT_CNTL); ++ tmp &= ~RADEON_CRTC_CRT_ON; ++ OUTREG(RADEON_CRTC_EXT_CNTL, tmp); ++ save->crtc_ext_cntl &= ~RADEON_CRTC_CRT_ON; ++ RADEONDacPowerSet(pScrn, bEnable, TRUE); ++ } + } + } else if (radeon_output->MonType == MT_DFP) { + if (radeon_output->TMDSType == TMDS_INT) { +@@ -780,6 +832,14 @@ RADEONEnableDisplay(xf86OutputPtr output, BOOL bEnable) tmp &= ~(RADEON_FP_FPON | RADEON_FP_TMDS_EN); OUTREG(RADEON_FP_GEN_CNTL, tmp); save->fp_gen_cntl &= ~(RADEON_FP_FPON | RADEON_FP_TMDS_EN); @@ -4136,7 +3041,7 @@ index 0de13df..4df81ab 100644 } } else if (radeon_output->TMDSType == TMDS_EXT) { info->output_dfp2 &= ~(1 << o); -@@ -790,6 +834,15 @@ RADEONEnableDisplay(xf86OutputPtr output, BOOL bEnable) +@@ -790,6 +850,15 @@ RADEONEnableDisplay(xf86OutputPtr output, BOOL bEnable) OUTREG(RADEON_FP2_GEN_CNTL, tmp); save->fp2_gen_cntl &= ~(RADEON_FP2_ON | RADEON_FP2_DVO_EN); save->fp2_gen_cntl |= RADEON_FP2_BLANK_EN; @@ -4152,7 +3057,7 @@ index 0de13df..4df81ab 100644 } } } else if (radeon_output->MonType == MT_LCD) { -@@ -862,11 +915,11 @@ RADEONInitFPRegisters(xf86OutputPtr output, RADEONSavePtr save, +@@ -862,11 +931,11 @@ RADEONInitFPRegisters(xf86OutputPtr output, RADEONSavePtr save, RADEONEntPtr pRADEONEnt = RADEONEntPriv(pScrn); RADEONOutputPrivatePtr radeon_output = output->driver_private; int i; @@ -4166,7 +3071,7 @@ index 0de13df..4df81ab 100644 tmp = radeon_output->tmds_pll[i].value ; break; } -@@ -918,6 +971,30 @@ RADEONInitFPRegisters(xf86OutputPtr output, RADEONSavePtr save, +@@ -918,6 +987,30 @@ RADEONInitFPRegisters(xf86OutputPtr output, RADEONSavePtr save, save->fp_gen_cntl |= RADEON_FP_SEL_CRTC2; } @@ -4197,7 +3102,7 @@ index 0de13df..4df81ab 100644 } static void -@@ -954,6 +1031,8 @@ RADEONInitFP2Registers(xf86OutputPtr output, RADEONSavePtr save, +@@ -954,6 +1047,8 @@ RADEONInitFP2Registers(xf86OutputPtr output, RADEONSavePtr save, save->fp2_gen_cntl &= ~R200_FP2_SOURCE_SEL_MASK; if (radeon_output->Flags & RADEON_USE_RMX) save->fp2_gen_cntl |= R200_FP2_SOURCE_SEL_RMX; @@ -4206,7 +3111,7 @@ index 0de13df..4df81ab 100644 } else { save->fp2_gen_cntl &= ~RADEON_FP2_SRC_SEL_CRTC2; } -@@ -966,6 +1045,28 @@ RADEONInitFP2Registers(xf86OutputPtr output, RADEONSavePtr save, +@@ -966,6 +1061,28 @@ RADEONInitFP2Registers(xf86OutputPtr output, RADEONSavePtr save, } } @@ -4235,7 +3140,7 @@ index 0de13df..4df81ab 100644 } static void -@@ -1015,14 +1116,15 @@ RADEONInitRMXRegisters(xf86OutputPtr output, RADEONSavePtr save, +@@ -1015,14 +1132,15 @@ RADEONInitRMXRegisters(xf86OutputPtr output, RADEONSavePtr save, RADEONOutputPrivatePtr radeon_output = output->driver_private; int xres = mode->HDisplay; int yres = mode->VDisplay; @@ -4253,7 +3158,7 @@ index 0de13df..4df81ab 100644 save->fp_horz_stretch = info->SavedReg->fp_horz_stretch & (RADEON_HORZ_FP_LOOP_STRETCH | RADEON_HORZ_AUTO_RATIO_INC); -@@ -1069,34 +1171,41 @@ RADEONInitRMXRegisters(xf86OutputPtr output, RADEONSavePtr save, +@@ -1069,34 +1187,41 @@ RADEONInitRMXRegisters(xf86OutputPtr output, RADEONSavePtr save, return; if (radeon_output->PanelXRes == 0 || radeon_output->PanelYRes == 0) { @@ -4306,7 +3211,25 @@ index 0de13df..4df81ab 100644 RADEON_VERT_STRETCH_ENABLE | RADEON_VERT_STRETCH_BLEND | ((radeon_output->PanelYRes-1)<<12)); -@@ -1310,7 +1419,7 @@ legacy_output_mode_set(xf86OutputPtr output, DisplayModePtr mode, +@@ -1258,6 +1383,7 @@ RADEONInitOutputRegisters(ScrnInfoPtr pScrn, RADEONSavePtr save, + { + Bool IsPrimary = crtc_num == 0 ? TRUE : FALSE; + RADEONOutputPrivatePtr radeon_output = output->driver_private; ++ RADEONInfoPtr info = RADEONPTR(pScrn); + + if (crtc_num == 0) + RADEONInitRMXRegisters(output, save, mode); +@@ -1267,6 +1393,9 @@ RADEONInitOutputRegisters(ScrnInfoPtr pScrn, RADEONSavePtr save, + RADEONInitDACRegisters(output, save, mode, IsPrimary); + } else { + RADEONInitDAC2Registers(output, save, mode, IsPrimary); ++ /* IGP chips seem to use a mix of primary and TVDAC controls */ ++ if (info->IsIGP) ++ RADEONInitDACRegisters(output, save, mode, IsPrimary); + } + } else if (radeon_output->MonType == MT_LCD) { + RADEONInitLVDSRegisters(output, save, mode, IsPrimary); +@@ -1310,7 +1439,7 @@ legacy_output_mode_set(xf86OutputPtr output, DisplayModePtr mode, ErrorF("restore FP2\n"); if (info->IsAtomBios) { unsigned char *RADEONMMIO = info->MMIO; @@ -4315,7 +3238,7 @@ index 0de13df..4df81ab 100644 atombios_external_tmds_setup(output, mode); /* r4xx atom has hard coded crtc mappings in the atom code -@@ -1354,8 +1463,8 @@ radeon_detect_primary_dac(ScrnInfoPtr pScrn, Bool color) +@@ -1354,8 +1483,8 @@ radeon_detect_primary_dac(ScrnInfoPtr pScrn, Bool color) { RADEONInfoPtr info = RADEONPTR(pScrn); unsigned char *RADEONMMIO = info->MMIO; @@ -4326,7 +3249,7 @@ index 0de13df..4df81ab 100644 RADEONMonitorType found = MT_NONE; /* save the regs we need */ -@@ -1421,11 +1530,11 @@ radeon_detect_ext_dac(ScrnInfoPtr pScrn) +@@ -1421,11 +1550,11 @@ radeon_detect_ext_dac(ScrnInfoPtr pScrn) { RADEONInfoPtr info = RADEONPTR(pScrn); unsigned char *RADEONMMIO = info->MMIO; @@ -4343,7 +3266,7 @@ index 0de13df..4df81ab 100644 RADEONMonitorType found = MT_NONE; int connected = 0; int i = 0; -@@ -1517,8 +1626,8 @@ radeon_detect_tv_dac(ScrnInfoPtr pScrn, Bool color) +@@ -1517,8 +1646,8 @@ radeon_detect_tv_dac(ScrnInfoPtr pScrn, Bool color) { RADEONInfoPtr info = RADEONPTR(pScrn); unsigned char *RADEONMMIO = info->MMIO; @@ -4354,7 +3277,7 @@ index 0de13df..4df81ab 100644 RADEONMonitorType found = MT_NONE; /* save the regs we need */ -@@ -1619,8 +1728,8 @@ r300_detect_tv(ScrnInfoPtr pScrn) +@@ -1619,8 +1748,8 @@ r300_detect_tv(ScrnInfoPtr pScrn) { RADEONInfoPtr info = RADEONPTR(pScrn); unsigned char *RADEONMMIO = info->MMIO; @@ -4365,7 +3288,7 @@ index 0de13df..4df81ab 100644 RADEONMonitorType found = MT_NONE; /* save the regs we need */ -@@ -1695,8 +1804,8 @@ radeon_detect_tv(ScrnInfoPtr pScrn) +@@ -1695,8 +1824,8 @@ radeon_detect_tv(ScrnInfoPtr pScrn) { RADEONInfoPtr info = RADEONPTR(pScrn); unsigned char *RADEONMMIO = info->MMIO; @@ -4377,10 +3300,16 @@ index 0de13df..4df81ab 100644 if (IS_R300_VARIANT) diff --git a/src/pcidb/ati_pciids.csv b/src/pcidb/ati_pciids.csv -index 5a2191a..5c89b55 100644 +index 5a2191a..1f6fa82 100644 --- a/src/pcidb/ati_pciids.csv +++ b/src/pcidb/ati_pciids.csv -@@ -179,20 +179,20 @@ +@@ -174,21 +174,22 @@ + "0x564F","RV410_564F","RV410",1,,,,,"ATI Mobility Radeon X700 XL (M26) (PCIE)" + "0x5652","RV410_5652","RV410",1,,,,,"ATI Mobility Radeon X700 (M26) (PCIE)" + "0x5653","RV410_5653","RV410",1,,,,,"ATI Mobility Radeon X700 (M26) (PCIE)" ++"0x5657","RV410_5657","RV410",,,,,,"ATI Radeon X550XTX 5657 (PCIE)" + "0x5654","MACH64VT","MACH64",,,,,, + "0x5655","MACH64VU","MACH64",,,,,, "0x5656","MACH64VV","MACH64",,,,,, "0x5834","RS300_5834","RS300",,1,,,1,"ATI Radeon 9100 IGP (A5) 5834" "0x5835","RS300_5835","RS300",1,1,,,1,"ATI Radeon Mobility 9100 IGP (U3) 5835" @@ -4400,13 +3329,15 @@ index 5a2191a..5c89b55 100644 +"0x5975","RS485_5975","RS480",1,1,,,1,"ATI Radeon XPRESS 200M 5975 (PCIE)" "0x5A41","RS400_5A41","RS400",,1,,,1,"ATI Radeon XPRESS 200 5A41 (PCIE)" "0x5A42","RS400_5A42","RS400",1,1,,,1,"ATI Radeon XPRESS 200M 5A42 (PCIE)" --"0x5A61","RC410_5A61","RS400",,1,,,1,"ATI Radeon XPRESS 200 5A61 (PCIE)" --"0x5A62","RC410_5A62","RS400",1,1,,,1,"ATI Radeon XPRESS 200M 5A62 (PCIE)" -+"0x5A61","RC410_5A61","RS480",,1,,,1,"ATI Radeon XPRESS 200 5A61 (PCIE)" -+"0x5A62","RC410_5A62","RS480",1,1,,,1,"ATI Radeon XPRESS 200M 5A62 (PCIE)" + "0x5A61","RC410_5A61","RS400",,1,,,1,"ATI Radeon XPRESS 200 5A61 (PCIE)" +@@ -196,7 +197,6 @@ "0x5B60","RV370_5B60","RV380",,,,,,"ATI Radeon X300 (RV370) 5B60 (PCIE)" "0x5B62","RV370_5B62","RV380",,,,,,"ATI Radeon X600 (RV370) 5B62 (PCIE)" "0x5B63","RV370_5B63","RV380",,,,,,"ATI Radeon X550 (RV370) 5B63 (PCIE)" +-"0x5657","RV370_5657","RV380",,,,,,"ATI Radeon X550XTX (RV370) 5657 (PCIE)" + "0x5B64","RV370_5B64","RV380",,,,,,"ATI FireGL V3100 (RV370) 5B64 (PCIE)" + "0x5B65","RV370_5B65","RV380",,,,,,"ATI FireMV 2200 PCIE (RV370) 5B65 (PCIE)" + "0x5C61","RV280_5C61","RV280",1,,,,,"ATI Radeon Mobility 9200 (M9+) 5C61 (AGP)" @@ -282,9 +282,9 @@ "0x71D6","RV530_71D6","RV530",1,,,,,"ATI Mobility Radeon X1700 XT" "0x71DA","RV530_71DA","RV530",,,,,,"ATI FireGL V5200" @@ -4483,7 +3414,7 @@ index 5a2191a..5c89b55 100644 +"0x9612","RS780_9612","RS780",,1,,,1,"ATI Radeon HD 3200 Graphics" +"0x9613","RS780_9613","RS780",,1,,,1,"ATI Radeon 3100 Graphics" diff --git a/src/radeon.h b/src/radeon.h -index aba3c0f..9363c29 100644 +index aba3c0f..4f77c3b 100644 --- a/src/radeon.h +++ b/src/radeon.h @@ -98,6 +98,11 @@ @@ -4498,17 +3429,18 @@ index aba3c0f..9363c29 100644 #ifndef HAVE_XF86MODEBANDWIDTH extern unsigned int xf86ModeBandwidth(DisplayModePtr mode, int depth); #define MODE_BANDWIDTH MODE_BAD -@@ -167,7 +172,8 @@ typedef enum { +@@ -167,7 +172,9 @@ typedef enum { OPTION_TVDAC_LOAD_DETECT, OPTION_FORCE_TVOUT, OPTION_TVSTD, - OPTION_IGNORE_LID_STATUS + OPTION_IGNORE_LID_STATUS, -+ OPTION_DEFAULT_TVDAC_ADJ ++ OPTION_DEFAULT_TVDAC_ADJ, ++ OPTION_INT10 } RADEONOpts; -@@ -198,38 +204,39 @@ typedef enum { +@@ -198,38 +205,39 @@ typedef enum { typedef struct { int revision; @@ -4536,7 +3468,7 @@ index aba3c0f..9363c29 100644 #define RADEON_PLL_NO_ODD_POST_DIV (1 << 1) #define RADEON_PLL_USE_REF_DIV (1 << 2) #define RADEON_PLL_LEGACY (1 << 3) -+#define RADEON_PLL_DCE3 (1 << 4) ++#define RADEON_PLL_PREFER_LOW_REF_DIV (1 << 4) typedef struct { - CARD16 reference_freq; @@ -4572,7 +3504,7 @@ index aba3c0f..9363c29 100644 } RADEONPLLRec, *RADEONPLLPtr; typedef struct { -@@ -260,20 +267,25 @@ typedef enum { +@@ -260,20 +268,25 @@ typedef enum { CHIP_FAMILY_RV380, /* RV370/RV380/M22/M24 */ CHIP_FAMILY_R420, /* R420/R423/M18 */ CHIP_FAMILY_RV410, /* RV410, M26 */ @@ -4601,7 +3533,7 @@ index aba3c0f..9363c29 100644 CHIP_FAMILY_LAST } RADEONChipFamily; -@@ -292,10 +304,32 @@ typedef enum { +@@ -292,10 +305,32 @@ typedef enum { (info->ChipFamily == CHIP_FAMILY_RV380) || \ (info->ChipFamily == CHIP_FAMILY_R420) || \ (info->ChipFamily == CHIP_FAMILY_RV410) || \ @@ -4635,7 +3567,7 @@ index aba3c0f..9363c29 100644 /* * Errata workarounds */ -@@ -333,7 +367,7 @@ typedef enum { +@@ -333,7 +368,7 @@ typedef enum { typedef struct _atomBiosHandle *atomBiosHandlePtr; typedef struct { @@ -4644,7 +3576,7 @@ index aba3c0f..9363c29 100644 RADEONChipFamily chip_family; int mobility; int igp; -@@ -353,22 +387,22 @@ typedef struct { +@@ -353,22 +388,22 @@ typedef struct { unsigned long LinearAddr; /* Frame buffer physical address */ unsigned long MMIOAddr; /* MMIO region physical address */ unsigned long BIOSAddr; /* BIOS physical address */ @@ -4675,7 +3607,7 @@ index aba3c0f..9363c29 100644 unsigned long MMIOSize; /* MMIO region physical address */ unsigned long FbMapSize; /* Size of frame buffer, in bytes */ unsigned long FbSecureSize; /* Size of secured fb area at end of -@@ -448,9 +482,9 @@ typedef struct { +@@ -448,9 +483,9 @@ typedef struct { /* Computed values for Radeon */ int pitch; int datatype; @@ -4688,7 +3620,7 @@ index aba3c0f..9363c29 100644 /* Saved values for ScreenToScreenCopy */ int xdir; -@@ -476,7 +510,7 @@ typedef struct { +@@ -476,7 +511,7 @@ typedef struct { #endif /* Saved values for DashedTwoPointLine */ int dashLen; @@ -4697,7 +3629,7 @@ index aba3c0f..9363c29 100644 int dash_fg; int dash_bg; -@@ -487,7 +521,7 @@ typedef struct { +@@ -487,7 +522,7 @@ typedef struct { DGAFunctionRec DGAFuncs; RADEONFBLayout CurrentLayout; @@ -4706,7 +3638,7 @@ index aba3c0f..9363c29 100644 #ifdef XF86DRI Bool noBackBuffer; Bool directRenderingEnabled; -@@ -502,14 +536,14 @@ typedef struct { +@@ -502,14 +537,14 @@ typedef struct { RADEONConfigPrivPtr pVisualConfigsPriv; Bool (*DRICloseScreen)(int, ScreenPtr); @@ -4724,7 +3656,7 @@ index aba3c0f..9363c29 100644 unsigned char *PCI; /* Map */ Bool depthMoves; /* Enable depth moves -- slow! */ -@@ -522,12 +556,12 @@ typedef struct { +@@ -522,12 +557,12 @@ typedef struct { int pciAperSize; drmSize gartSize; @@ -4739,7 +3671,7 @@ index aba3c0f..9363c29 100644 Bool CPRuns; /* CP is running */ Bool CPInUse; /* CP has been used by X server */ -@@ -539,20 +573,20 @@ typedef struct { +@@ -539,20 +574,20 @@ typedef struct { /* CP ring buffer data */ unsigned long ringStart; /* Offset into GART space */ @@ -4763,7 +3695,7 @@ index aba3c0f..9363c29 100644 drmSize bufMapSize; /* Size of map */ int bufSize; /* Size of buffers (in MB) */ drmAddress buf; /* Map */ -@@ -561,7 +595,7 @@ typedef struct { +@@ -561,7 +596,7 @@ typedef struct { /* CP GART Texture data */ unsigned long gartTexStart; /* Offset into GART space */ @@ -4772,7 +3704,7 @@ index aba3c0f..9363c29 100644 drmSize gartTexMapSize; /* Size of map */ int gartTexSize; /* Size of GART tex space (in MB) */ drmAddress gartTex; /* Map */ -@@ -591,12 +625,12 @@ typedef struct { +@@ -591,12 +626,12 @@ typedef struct { int log2TexGran; int pciGartSize; @@ -4789,7 +3721,7 @@ index aba3c0f..9363c29 100644 /* offscreen memory management */ int backLines; -@@ -606,15 +640,15 @@ typedef struct { +@@ -606,15 +641,15 @@ typedef struct { #endif /* Saved scissor values */ @@ -4812,7 +3744,7 @@ index aba3c0f..9363c29 100644 int irq; -@@ -639,22 +673,22 @@ typedef struct { +@@ -639,22 +674,22 @@ typedef struct { int RageTheatreCompositePort; int RageTheatreSVideoPort; int tunerType; @@ -4850,7 +3782,7 @@ index aba3c0f..9363c29 100644 int overlay_scaler_buffer_width; int ecp_div; -@@ -686,15 +720,15 @@ typedef struct { +@@ -686,15 +721,15 @@ typedef struct { DisplayModePtr currentMode, savedCurrentMode; /* special handlings for DELL triple-head server */ @@ -4872,7 +3804,7 @@ index aba3c0f..9363c29 100644 Bool want_vblank_interrupts; RADEONBIOSConnector BiosConnector[RADEON_MAX_BIOS_CONNECTOR]; -@@ -736,6 +770,9 @@ typedef struct { +@@ -736,6 +771,9 @@ typedef struct { Bool r600_shadow_fb; void *fb_shadow; @@ -4882,7 +3814,7 @@ index aba3c0f..9363c29 100644 } RADEONInfoRec, *RADEONInfoPtr; #define RADEONWaitForFifo(pScrn, entries) \ -@@ -745,152 +782,207 @@ do { \ +@@ -745,152 +783,209 @@ do { \ info->fifo_slots -= entries; \ } while (0) @@ -5003,7 +3935,9 @@ index aba3c0f..9363c29 100644 -extern void RADEONChangeSurfaces(ScrnInfoPtr pScrn); +/* radeon_crtc.c */ ++extern void radeon_crtc_dpms(xf86CrtcPtr crtc, int mode); +extern void radeon_crtc_load_lut(xf86CrtcPtr crtc); ++extern void radeon_crtc_modeset_ioctl(xf86CrtcPtr crtc, Bool post); +extern Bool RADEONAllocateControllers(ScrnInfoPtr pScrn, int mask); +extern void RADEONBlank(ScrnInfoPtr pScrn); +extern void RADEONComputePLL(RADEONPLLPtr pll, unsigned long freq, @@ -5224,7 +4158,7 @@ index aba3c0f..9363c29 100644 extern void RADEONAdjustCrtcRegistersForTV(ScrnInfoPtr pScrn, RADEONSavePtr save, DisplayModePtr mode, xf86OutputPtr output); extern void RADEONAdjustPLLRegistersForTV(ScrnInfoPtr pScrn, RADEONSavePtr save, -@@ -901,47 +993,18 @@ extern void RADEONAdjustPLL2RegistersForTV(ScrnInfoPtr pScrn, RADEONSavePtr save +@@ -901,47 +996,18 @@ extern void RADEONAdjustPLL2RegistersForTV(ScrnInfoPtr pScrn, RADEONSavePtr save DisplayModePtr mode, xf86OutputPtr output); extern void RADEONInitTVRegisters(xf86OutputPtr output, RADEONSavePtr save, DisplayModePtr mode, BOOL IsPrimary); @@ -5280,7 +4214,7 @@ index aba3c0f..9363c29 100644 #define RADEONCP_START(pScrn, info) \ do { \ -@@ -998,11 +1061,18 @@ do { \ +@@ -998,11 +1064,18 @@ do { \ info->needCacheFlush = FALSE; \ } \ RADEON_WAIT_UNTIL_IDLE(); \ @@ -5304,7 +4238,7 @@ index aba3c0f..9363c29 100644 info->CPInUse = TRUE; \ } \ } while (0) -@@ -1020,7 +1090,7 @@ do { \ +@@ -1020,7 +1093,7 @@ do { \ #define RADEON_VERBOSE 0 @@ -5313,7 +4247,7 @@ index aba3c0f..9363c29 100644 #define BEGIN_RING(n) do { \ if (RADEON_VERBOSE) { \ -@@ -1038,7 +1108,7 @@ do { \ +@@ -1038,7 +1111,7 @@ do { \ if (!info->indirectBuffer) { \ info->indirectBuffer = RADEONCPGetBuffer(pScrn); \ info->indirectStart = 0; \ @@ -5322,7 +4256,7 @@ index aba3c0f..9363c29 100644 info->indirectBuffer->total) { \ RADEONCPFlushIndirect(pScrn, 1); \ } \ -@@ -1065,9 +1135,9 @@ do { \ +@@ -1065,9 +1138,9 @@ do { \ "ADVANCE_RING() start: %d used: %d count: %d\n", \ info->indirectStart, \ info->indirectBuffer->used, \ @@ -5334,7 +4268,7 @@ index aba3c0f..9363c29 100644 } while (0) #define OUT_RING(x) do { \ -@@ -1130,15 +1200,27 @@ do { \ +@@ -1130,15 +1203,27 @@ do { \ #define RADEON_PURGE_CACHE() \ do { \ BEGIN_RING(2); \ @@ -5367,7 +4301,7 @@ index aba3c0f..9363c29 100644 #endif /* XF86DRI */ diff --git a/src/radeon_accel.c b/src/radeon_accel.c -index 8b2f167..778d43e 100644 +index 8b2f167..d45e932 100644 --- a/src/radeon_accel.c +++ b/src/radeon_accel.c @@ -158,17 +158,32 @@ void RADEONEngineFlush(ScrnInfoPtr pScrn) @@ -5399,17 +4333,17 @@ index 8b2f167..778d43e 100644 + (unsigned int)INREG(RADEON_RB3D_DSTCACHE_CTLSTAT)); + } + } else { -+ OUTREGP(R300_RB2D_DSTCACHE_CTLSTAT, ++ OUTREGP(R300_DSTCACHE_CTLSTAT, + R300_RB2D_DC_FLUSH_ALL, + ~R300_RB2D_DC_FLUSH_ALL); + for (i = 0; i < RADEON_TIMEOUT; i++) { -+ if (!(INREG(R300_RB2D_DSTCACHE_CTLSTAT) & R300_RB2D_DC_BUSY)) ++ if (!(INREG(R300_DSTCACHE_CTLSTAT) & R300_RB2D_DC_BUSY)) + break; + } + if (i == RADEON_TIMEOUT) { + xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG, + "DC flush timeout: %x\n", -+ (unsigned int)INREG(R300_RB2D_DSTCACHE_CTLSTAT)); ++ (unsigned int)INREG(R300_DSTCACHE_CTLSTAT)); + } } } @@ -5471,7 +4405,7 @@ index 8b2f167..778d43e 100644 - OUTREG(RADEON_RB3D_CNTL, 0); +#ifdef XF86DRI -+ if (IS_R300_3D | IS_R500_3D) { ++ if (info->directRenderingEnabled && (IS_R300_3D | IS_R500_3D)) { + drmRadeonGetParam np; + int num_pipes; + @@ -5481,7 +4415,7 @@ index 8b2f167..778d43e 100644 + + if (drmCommandWriteRead(info->drmFD, DRM_RADEON_GETPARAM, &np, + sizeof(np)) < 0) { -+ xf86DrvMsg(pScrn->scrnIndex, X_ERROR, ++ xf86DrvMsg(pScrn->scrnIndex, X_WARNING, + "Failed to determine num pipes from DRM, falling back to " + "manual look-up!\n"); + info->num_gb_pipes = 0; @@ -5659,10 +4593,34 @@ index 8b2f167..778d43e 100644 info->backY = info->backOffset / width_bytes; diff --git a/src/radeon_accelfuncs.c b/src/radeon_accelfuncs.c -index e3b37c1..3c0b8a0 100644 +index e3b37c1..56793cd 100644 --- a/src/radeon_accelfuncs.c +++ b/src/radeon_accelfuncs.c -@@ -284,7 +284,7 @@ FUNC_NAME(RADEONSetupForDashedLine)(ScrnInfoPtr pScrn, +@@ -151,6 +151,11 @@ FUNC_NAME(RADEONSetupForSolidFill)(ScrnInfoPtr pScrn, + | RADEON_DST_Y_TOP_TO_BOTTOM)); + + FINISH_ACCEL(); ++ BEGIN_ACCEL(2); ++ OUT_ACCEL_REG(RADEON_DSTCACHE_CTLSTAT, RADEON_RB2D_DC_FLUSH_ALL); ++ OUT_ACCEL_REG(RADEON_WAIT_UNTIL, ++ RADEON_WAIT_2D_IDLECLEAN | RADEON_WAIT_DMA_GUI_IDLE); ++ FINISH_ACCEL(); + } + + /* Subsequent XAA SolidFillRect +@@ -205,6 +210,11 @@ FUNC_NAME(RADEONSetupForSolidLine)(ScrnInfoPtr pScrn, + OUT_ACCEL_REG(RADEON_DP_WRITE_MASK, planemask); + + FINISH_ACCEL(); ++ BEGIN_ACCEL(2); ++ OUT_ACCEL_REG(RADEON_DSTCACHE_CTLSTAT, RADEON_RB2D_DC_FLUSH_ALL); ++ OUT_ACCEL_REG(RADEON_WAIT_UNTIL, ++ RADEON_WAIT_2D_IDLECLEAN | RADEON_WAIT_DMA_GUI_IDLE); ++ FINISH_ACCEL(); + } + + /* Subsequent XAA solid horizontal and vertical lines */ +@@ -284,7 +294,7 @@ FUNC_NAME(RADEONSetupForDashedLine)(ScrnInfoPtr pScrn, unsigned char *pattern) { RADEONInfoPtr info = RADEONPTR(pScrn); @@ -5671,7 +4629,19 @@ index e3b37c1..3c0b8a0 100644 ACCEL_PREAMBLE(); /* Save for determining whether or not to draw last pixel */ -@@ -333,7 +333,7 @@ FUNC_NAME(RADEONDashedLastPel)(ScrnInfoPtr pScrn, +@@ -324,6 +334,11 @@ FUNC_NAME(RADEONSetupForDashedLine)(ScrnInfoPtr pScrn, + OUT_ACCEL_REG(RADEON_BRUSH_DATA0, pat); + + FINISH_ACCEL(); ++ BEGIN_ACCEL(2); ++ OUT_ACCEL_REG(RADEON_DSTCACHE_CTLSTAT, RADEON_RB2D_DC_FLUSH_ALL); ++ OUT_ACCEL_REG(RADEON_WAIT_UNTIL, ++ RADEON_WAIT_2D_IDLECLEAN | RADEON_WAIT_DMA_GUI_IDLE); ++ FINISH_ACCEL(); + } + + /* Helper function to draw last point for dashed lines */ +@@ -333,7 +348,7 @@ FUNC_NAME(RADEONDashedLastPel)(ScrnInfoPtr pScrn, int fg) { RADEONInfoPtr info = RADEONPTR(pScrn); @@ -5680,7 +4650,31 @@ index e3b37c1..3c0b8a0 100644 ACCEL_PREAMBLE(); dp_gui_master_cntl &= ~RADEON_GMC_BRUSH_DATATYPE_MASK; -@@ -548,8 +548,8 @@ FUNC_NAME(RADEONSetupForMono8x8PatternFill)(ScrnInfoPtr pScrn, +@@ -358,6 +373,11 @@ FUNC_NAME(RADEONDashedLastPel)(ScrnInfoPtr pScrn, + OUT_ACCEL_REG(RADEON_DP_BRUSH_FRGD_CLR, info->dash_fg); + + FINISH_ACCEL(); ++ BEGIN_ACCEL(2); ++ OUT_ACCEL_REG(RADEON_DSTCACHE_CTLSTAT, RADEON_RB2D_DC_FLUSH_ALL); ++ OUT_ACCEL_REG(RADEON_WAIT_UNTIL, ++ RADEON_WAIT_2D_IDLECLEAN | RADEON_WAIT_DMA_GUI_IDLE); ++ FINISH_ACCEL(); + } + + /* Subsequent XAA dashed line */ +@@ -461,6 +481,11 @@ FUNC_NAME(RADEONSetupForScreenToScreenCopy)(ScrnInfoPtr pScrn, + (ydir >= 0 ? RADEON_DST_Y_TOP_TO_BOTTOM : 0))); + + FINISH_ACCEL(); ++ BEGIN_ACCEL(2); ++ OUT_ACCEL_REG(RADEON_DSTCACHE_CTLSTAT, RADEON_RB2D_DC_FLUSH_ALL); ++ OUT_ACCEL_REG(RADEON_WAIT_UNTIL, ++ RADEON_WAIT_2D_IDLECLEAN | RADEON_WAIT_DMA_GUI_IDLE); ++ FINISH_ACCEL(); + + info->trans_color = trans_color; + FUNC_NAME(RADEONSetTransparency)(pScrn, trans_color); +@@ -548,11 +573,16 @@ FUNC_NAME(RADEONSetupForMono8x8PatternFill)(ScrnInfoPtr pScrn, OUT_ACCEL_REG(RADEON_BRUSH_DATA0, patternx); OUT_ACCEL_REG(RADEON_BRUSH_DATA1, patterny); #else @@ -5691,7 +4685,15 @@ index e3b37c1..3c0b8a0 100644 #endif FINISH_ACCEL(); -@@ -829,10 +829,10 @@ FUNC_NAME(RADEONSubsequentScanline)(ScrnInfoPtr pScrn, ++ BEGIN_ACCEL(2); ++ OUT_ACCEL_REG(RADEON_DSTCACHE_CTLSTAT, RADEON_RB2D_DC_FLUSH_ALL); ++ OUT_ACCEL_REG(RADEON_WAIT_UNTIL, ++ RADEON_WAIT_2D_IDLECLEAN | RADEON_WAIT_DMA_GUI_IDLE); ++ FINISH_ACCEL(); + } + + /* Subsequent XAA 8x8 pattern color expansion. Because they are used in +@@ -829,10 +859,10 @@ FUNC_NAME(RADEONSubsequentScanline)(ScrnInfoPtr pScrn, { RADEONInfoPtr info = RADEONPTR(pScrn); #ifdef ACCEL_MMIO @@ -5704,7 +4706,31 @@ index e3b37c1..3c0b8a0 100644 ACCEL_PREAMBLE(); if (info->scanline_direct) return; -@@ -1302,15 +1302,16 @@ FUNC_NAME(RADEONAccelInit)(ScreenPtr pScreen, XAAInfoRecPtr a) +@@ -1086,6 +1116,11 @@ FUNC_NAME(RADEONSetClippingRectangle)(ScrnInfoPtr pScrn, + OUT_ACCEL_REG(RADEON_SC_BOTTOM_RIGHT, tmp2); + + FINISH_ACCEL(); ++ BEGIN_ACCEL(2); ++ OUT_ACCEL_REG(RADEON_DSTCACHE_CTLSTAT, RADEON_RB2D_DC_FLUSH_ALL); ++ OUT_ACCEL_REG(RADEON_WAIT_UNTIL, ++ RADEON_WAIT_2D_IDLECLEAN | RADEON_WAIT_DMA_GUI_IDLE); ++ FINISH_ACCEL(); + + FUNC_NAME(RADEONSetTransparency)(pScrn, info->trans_color); + } +@@ -1105,6 +1140,11 @@ FUNC_NAME(RADEONDisableClipping)(ScrnInfoPtr pScrn) + RADEON_DEFAULT_SC_BOTTOM_MAX)); + + FINISH_ACCEL(); ++ BEGIN_ACCEL(2); ++ OUT_ACCEL_REG(RADEON_DSTCACHE_CTLSTAT, RADEON_RB2D_DC_FLUSH_ALL); ++ OUT_ACCEL_REG(RADEON_WAIT_UNTIL, ++ RADEON_WAIT_2D_IDLECLEAN | RADEON_WAIT_DMA_GUI_IDLE); ++ FINISH_ACCEL(); + + FUNC_NAME(RADEONSetTransparency)(pScrn, info->trans_color); + } +@@ -1302,15 +1342,16 @@ FUNC_NAME(RADEONAccelInit)(ScreenPtr pScreen, XAAInfoRecPtr a) a->CPUToScreenTextureDstFormats = RADEONDstFormats; if (IS_R300_VARIANT || IS_AVIVO_VARIANT) { @@ -5725,7 +4751,7 @@ index e3b37c1..3c0b8a0 100644 a->SetupForCPUToScreenTexture2 = diff --git a/src/radeon_atombios.c b/src/radeon_atombios.c -index 88c220b..5cc21d5 100644 +index 88c220b..20aa722 100644 --- a/src/radeon_atombios.c +++ b/src/radeon_atombios.c @@ -35,6 +35,8 @@ @@ -5737,6 +4763,48 @@ index 88c220b..5cc21d5 100644 #include "xorg-server.h" /* only for testing now */ +@@ -228,7 +230,7 @@ CailDebug(int scrnIndex, const char *format, ...) + static int + rhdAtomAnalyzeCommonHdr(ATOM_COMMON_TABLE_HEADER *hdr) + { +- if (hdr->usStructureSize == 0xaa55) ++ if (le16_to_cpu(hdr->usStructureSize) == 0xaa55) + return FALSE; + + return TRUE; +@@ -244,24 +246,24 @@ rhdAtomAnalyzeRomHdr(unsigned char *rombase, + return FALSE; + } + xf86DrvMsg(-1,X_NONE,"\tSubsystemVendorID: 0x%4.4x SubsystemID: 0x%4.4x\n", +- hdr->usSubsystemVendorID,hdr->usSubsystemID); +- xf86DrvMsg(-1,X_NONE,"\tIOBaseAddress: 0x%4.4x\n",hdr->usIoBaseAddress); +- xf86DrvMsgVerb(-1,X_NONE,3,"\tFilename: %s\n",rombase + hdr->usConfigFilenameOffset); ++ le16_to_cpu(hdr->usSubsystemVendorID),le16_to_cpu(hdr->usSubsystemID)); ++ xf86DrvMsg(-1,X_NONE,"\tIOBaseAddress: 0x%4.4x\n",le16_to_cpu(hdr->usIoBaseAddress)); ++ xf86DrvMsgVerb(-1,X_NONE,3,"\tFilename: %s\n",rombase + le16_to_cpu(hdr->usConfigFilenameOffset)); + xf86DrvMsgVerb(-1,X_NONE,3,"\tBIOS Bootup Message: %s\n", +- rombase + hdr->usBIOS_BootupMessageOffset); ++ rombase + le16_to_cpu(hdr->usBIOS_BootupMessageOffset)); + +- *data_offset = hdr->usMasterDataTableOffset; +- *command_offset = hdr->usMasterCommandTableOffset; ++ *data_offset = le16_to_cpu(hdr->usMasterDataTableOffset); ++ *command_offset = le16_to_cpu(hdr->usMasterCommandTableOffset); + + return TRUE; + } + + static int +-rhdAtomAnalyzeRomDataTable(unsigned char *base, int offset, ++rhdAtomAnalyzeRomDataTable(unsigned char *base, uint16_t offset, + void *ptr,unsigned short *size) + { + ATOM_COMMON_TABLE_HEADER *table = (ATOM_COMMON_TABLE_HEADER *) +- (base + offset); ++ (base + le16_to_cpu(offset)); + + if (!*size || !rhdAtomAnalyzeCommonHdr(table)) { + if (*size) *size -= 2; @@ -275,8 +277,8 @@ rhdAtomAnalyzeRomDataTable(unsigned char *base, int offset, Bool @@ -5748,6 +4816,26 @@ index 88c220b..5cc21d5 100644 unsigned short *size) { if (!hdr) +@@ -284,7 +286,7 @@ rhdAtomGetTableRevisionAndSize(ATOM_COMMON_TABLE_HEADER *hdr, + + if (contentRev) *contentRev = hdr->ucTableContentRevision; + if (formatRev) *formatRev = hdr->ucTableFormatRevision; +- if (size) *size = (short)hdr->usStructureSize ++ if (size) *size = (short)le16_to_cpu(hdr->usStructureSize) + - sizeof(ATOM_COMMON_TABLE_HEADER); + return TRUE; + } +@@ -358,8 +360,8 @@ rhdAtomGetDataTable(int scrnIndex, + unsigned int BIOSImageSize) + { + unsigned int data_offset; +- unsigned int atom_romhdr_off = *(unsigned short*) +- (base + OFFSET_TO_POINTER_TO_ATOM_ROM_HEADER); ++ unsigned int atom_romhdr_off = le16_to_cpu(*(unsigned short*) ++ (base + OFFSET_TO_POINTER_TO_ATOM_ROM_HEADER)); + ATOM_ROM_HEADER *atom_rom_hdr = + (ATOM_ROM_HEADER *)(base + atom_romhdr_off); + @@ -454,7 +456,7 @@ rhdAtomAllocateFbScratch(atomBiosHandlePtr handle, } if (fb_base && fb_size && size) { @@ -5919,7 +5007,7 @@ index 88c220b..5cc21d5 100644 return ATOM_FAILED; } -@@ -658,7 +647,7 @@ rhdAtomVramInfoQuery(atomBiosHandlePtr handle, AtomBiosRequestID func, +@@ -658,19 +647,19 @@ rhdAtomVramInfoQuery(atomBiosHandlePtr handle, AtomBiosRequestID func, AtomBiosArgPtr data) { atomDataTablesPtr atomDataPtr; @@ -5928,6 +5016,22 @@ index 88c220b..5cc21d5 100644 //RHDFUNC(handle); atomDataPtr = handle->atomDataPtr; + + switch (func) { + case GET_FW_FB_START: +- *val = atomDataPtr->VRAM_UsageByFirmware +- ->asFirmwareVramReserveInfo[0].ulStartAddrUsedByFirmware; ++ *val = le32_to_cpu(atomDataPtr->VRAM_UsageByFirmware ++ ->asFirmwareVramReserveInfo[0].ulStartAddrUsedByFirmware); + break; + case GET_FW_FB_SIZE: +- *val = atomDataPtr->VRAM_UsageByFirmware +- ->asFirmwareVramReserveInfo[0].usFirmwareUseInKb; ++ *val = le16_to_cpu(atomDataPtr->VRAM_UsageByFirmware ++ ->asFirmwareVramReserveInfo[0].usFirmwareUseInKb); + break; + default: + return ATOM_NOT_IMPLEMENTED; @@ -683,7 +672,7 @@ rhdAtomTmdsInfoQuery(atomBiosHandlePtr handle, AtomBiosRequestID func, AtomBiosArgPtr data) { @@ -5937,6 +5041,45 @@ index 88c220b..5cc21d5 100644 int idx = *val; atomDataPtr = handle->atomDataPtr; +@@ -697,7 +686,7 @@ rhdAtomTmdsInfoQuery(atomBiosHandlePtr handle, + + switch (func) { + case ATOM_TMDS_FREQUENCY: +- *val = atomDataPtr->TMDS_Info->asMiscInfo[idx].usFrequency; ++ *val = le16_to_cpu(atomDataPtr->TMDS_Info->asMiscInfo[idx].usFrequency); + break; + case ATOM_TMDS_PLL_CHARGE_PUMP: + *val = atomDataPtr->TMDS_Info->asMiscInfo[idx].ucPLL_ChargePump; +@@ -732,20 +721,20 @@ rhdAtomDTDTimings(atomBiosHandlePtr handle, ATOM_DTD_FORMAT *dtd) + if (!(mode = (DisplayModePtr)xcalloc(1,sizeof(DisplayModeRec)))) + return NULL; + +- mode->CrtcHDisplay = mode->HDisplay = dtd->usHActive; +- mode->CrtcVDisplay = mode->VDisplay = dtd->usVActive; ++ mode->CrtcHDisplay = mode->HDisplay = le16_to_cpu(dtd->usHActive); ++ mode->CrtcVDisplay = mode->VDisplay = le16_to_cpu(dtd->usVActive); + mode->CrtcHBlankStart = dtd->usHActive + dtd->ucHBorder; +- mode->CrtcHBlankEnd = mode->CrtcHBlankStart + dtd->usHBlanking_Time; ++ mode->CrtcHBlankEnd = mode->CrtcHBlankStart + le16_to_cpu(dtd->usHBlanking_Time); + mode->CrtcHTotal = mode->HTotal = mode->CrtcHBlankEnd + dtd->ucHBorder; + mode->CrtcVBlankStart = dtd->usVActive + dtd->ucVBorder; +- mode->CrtcVBlankEnd = mode->CrtcVBlankStart + dtd->usVBlanking_Time; ++ mode->CrtcVBlankEnd = mode->CrtcVBlankStart + le16_to_cpu(dtd->usVBlanking_Time); + mode->CrtcVTotal = mode->VTotal = mode->CrtcVBlankEnd + dtd->ucVBorder; +- mode->CrtcHSyncStart = mode->HSyncStart = dtd->usHActive + dtd->usHSyncOffset; +- mode->CrtcHSyncEnd = mode->HSyncEnd = mode->HSyncStart + dtd->usHSyncWidth; +- mode->CrtcVSyncStart = mode->VSyncStart = dtd->usVActive + dtd->usVSyncOffset; +- mode->CrtcVSyncEnd = mode->VSyncEnd = mode->VSyncStart + dtd->usVSyncWidth; ++ mode->CrtcHSyncStart = mode->HSyncStart = dtd->usHActive + le16_to_cpu(dtd->usHSyncOffset); ++ mode->CrtcHSyncEnd = mode->HSyncEnd = mode->HSyncStart + le16_to_cpu(dtd->usHSyncWidth); ++ mode->CrtcVSyncStart = mode->VSyncStart = dtd->usVActive + le16_to_cpu(dtd->usVSyncOffset); ++ mode->CrtcVSyncEnd = mode->VSyncEnd = mode->VSyncStart + le16_to_cpu(dtd->usVSyncWidth); + +- mode->SynthClock = mode->Clock = dtd->usPixClk * 10; ++ mode->SynthClock = mode->Clock = le16_to_cpu(dtd->usPixClk) * 10; + + mode->HSync = ((float) mode->Clock) / ((float)mode->HTotal); + mode->VRefresh = (1000.0 * ((float) mode->Clock)) @@ -778,7 +767,7 @@ rhdAtomDTDTimings(atomBiosHandlePtr handle, ATOM_DTD_FORMAT *dtd) } @@ -5964,6 +5107,26 @@ index 88c220b..5cc21d5 100644 unsigned long offset; //RHDFUNC(handle); +@@ -977,15 +966,15 @@ rhdAtomLvdsGetTimings(atomBiosHandlePtr handle, AtomBiosRequestID func, + case ATOMBIOS_GET_PANEL_EDID: + offset = (unsigned long)&atomDataPtr->LVDS_Info.base + - (unsigned long)handle->BIOSBase +- + atomDataPtr->LVDS_Info +- .LVDS_Info_v12->usExtInfoTableOffset; ++ + le16_to_cpu(atomDataPtr->LVDS_Info ++ .LVDS_Info_v12->usExtInfoTableOffset); + + data->EDIDBlock + = rhdAtomLvdsDDC(handle, offset, + (unsigned char *) + &atomDataPtr->LVDS_Info.base +- + atomDataPtr->LVDS_Info +- .LVDS_Info_v12->usExtInfoTableOffset); ++ + le16_to_cpu(atomDataPtr->LVDS_Info ++ .LVDS_Info_v12->usExtInfoTableOffset)); + if (data->EDIDBlock) + return ATOM_SUCCESS; + default: @@ -1002,8 +991,8 @@ rhdAtomLvdsInfoQuery(atomBiosHandlePtr handle, AtomBiosRequestID func, AtomBiosArgPtr data) { @@ -5975,6 +5138,40 @@ index 88c220b..5cc21d5 100644 //RHDFUNC(handle); +@@ -1019,12 +1008,12 @@ rhdAtomLvdsInfoQuery(atomBiosHandlePtr handle, + case 1: + switch (func) { + case ATOM_LVDS_SUPPORTED_REFRESH_RATE: +- *val = atomDataPtr->LVDS_Info +- .LVDS_Info->usSupportedRefreshRate; ++ *val = le16_to_cpu(atomDataPtr->LVDS_Info ++ .LVDS_Info->usSupportedRefreshRate); + break; + case ATOM_LVDS_OFF_DELAY: +- *val = atomDataPtr->LVDS_Info +- .LVDS_Info->usOffDelayInMs; ++ *val = le16_to_cpu(atomDataPtr->LVDS_Info ++ .LVDS_Info->usOffDelayInMs); + break; + case ATOM_LVDS_SEQ_DIG_ONTO_DE: + *val = atomDataPtr->LVDS_Info +@@ -1061,12 +1050,12 @@ rhdAtomLvdsInfoQuery(atomBiosHandlePtr handle, + case 2: + switch (func) { + case ATOM_LVDS_SUPPORTED_REFRESH_RATE: +- *val = atomDataPtr->LVDS_Info +- .LVDS_Info_v12->usSupportedRefreshRate; ++ *val = le16_to_cpu(atomDataPtr->LVDS_Info ++ .LVDS_Info_v12->usSupportedRefreshRate); + break; + case ATOM_LVDS_OFF_DELAY: +- *val = atomDataPtr->LVDS_Info +- .LVDS_Info_v12->usOffDelayInMs; ++ *val = le16_to_cpu(atomDataPtr->LVDS_Info ++ .LVDS_Info_v12->usOffDelayInMs); + break; + case ATOM_LVDS_SEQ_DIG_ONTO_DE: + *val = atomDataPtr->LVDS_Info @@ -1112,8 +1101,8 @@ rhdAtomCompassionateDataQuery(atomBiosHandlePtr handle, AtomBiosRequestID func, AtomBiosArgPtr data) { @@ -5997,6 +5194,17 @@ index 88c220b..5cc21d5 100644 unsigned short size; //RHDFUNC(handle); +@@ -1194,8 +1183,8 @@ rhdAtomGPIOI2CInfoQuery(atomBiosHandlePtr handle, + return ATOM_FAILED; + } + +- *val = atomDataPtr->GPIO_I2C_Info->asGPIO_Info[*val] +- .usClkMaskRegisterIndex; ++ *val = le16_to_cpu(atomDataPtr->GPIO_I2C_Info->asGPIO_Info[*val] ++ .usClkMaskRegisterIndex); + break; + + default: @@ -1209,8 +1198,8 @@ rhdAtomFirmwareInfoQuery(atomBiosHandlePtr handle, AtomBiosRequestID func, AtomBiosArgPtr data) { @@ -6008,6 +5216,217 @@ index 88c220b..5cc21d5 100644 //RHDFUNC(handle); +@@ -1226,35 +1215,35 @@ rhdAtomFirmwareInfoQuery(atomBiosHandlePtr handle, + case 1: + switch (func) { + case GET_DEFAULT_ENGINE_CLOCK: +- *val = atomDataPtr->FirmwareInfo +- .FirmwareInfo->ulDefaultEngineClock * 10; ++ *val = le32_to_cpu(atomDataPtr->FirmwareInfo ++ .FirmwareInfo->ulDefaultEngineClock) * 10; + break; + case GET_DEFAULT_MEMORY_CLOCK: +- *val = atomDataPtr->FirmwareInfo +- .FirmwareInfo->ulDefaultMemoryClock * 10; ++ *val = le32_to_cpu(atomDataPtr->FirmwareInfo ++ .FirmwareInfo->ulDefaultMemoryClock) * 10; + break; + case GET_MAX_PIXEL_CLOCK_PLL_OUTPUT: +- *val = atomDataPtr->FirmwareInfo +- .FirmwareInfo->ulMaxPixelClockPLL_Output * 10; ++ *val = le32_to_cpu(atomDataPtr->FirmwareInfo ++ .FirmwareInfo->ulMaxPixelClockPLL_Output) * 10; + break; + case GET_MIN_PIXEL_CLOCK_PLL_OUTPUT: +- *val = atomDataPtr->FirmwareInfo +- .FirmwareInfo->usMinPixelClockPLL_Output * 10; ++ *val = le16_to_cpu(atomDataPtr->FirmwareInfo ++ .FirmwareInfo->usMinPixelClockPLL_Output) * 10; + case GET_MAX_PIXEL_CLOCK_PLL_INPUT: +- *val = atomDataPtr->FirmwareInfo +- .FirmwareInfo->usMaxPixelClockPLL_Input * 10; ++ *val = le16_to_cpu(atomDataPtr->FirmwareInfo ++ .FirmwareInfo->usMaxPixelClockPLL_Input) * 10; + break; + case GET_MIN_PIXEL_CLOCK_PLL_INPUT: +- *val = atomDataPtr->FirmwareInfo +- .FirmwareInfo->usMinPixelClockPLL_Input * 10; ++ *val = le16_to_cpu(atomDataPtr->FirmwareInfo ++ .FirmwareInfo->usMinPixelClockPLL_Input) * 10; + break; + case GET_MAX_PIXEL_CLK: +- *val = atomDataPtr->FirmwareInfo +- .FirmwareInfo->usMaxPixelClock * 10; ++ *val = le16_to_cpu(atomDataPtr->FirmwareInfo ++ .FirmwareInfo->usMaxPixelClock) * 10; + break; + case GET_REF_CLOCK: +- *val = atomDataPtr->FirmwareInfo +- .FirmwareInfo->usReferenceClock * 10; ++ *val = le16_to_cpu(atomDataPtr->FirmwareInfo ++ .FirmwareInfo->usReferenceClock) * 10; + break; + default: + return ATOM_NOT_IMPLEMENTED; +@@ -1262,36 +1251,36 @@ rhdAtomFirmwareInfoQuery(atomBiosHandlePtr handle, + case 2: + switch (func) { + case GET_DEFAULT_ENGINE_CLOCK: +- *val = atomDataPtr->FirmwareInfo +- .FirmwareInfo_V_1_2->ulDefaultEngineClock * 10; ++ *val = le32_to_cpu(atomDataPtr->FirmwareInfo ++ .FirmwareInfo_V_1_2->ulDefaultEngineClock) * 10; + break; + case GET_DEFAULT_MEMORY_CLOCK: +- *val = atomDataPtr->FirmwareInfo +- .FirmwareInfo_V_1_2->ulDefaultMemoryClock * 10; ++ *val = le32_to_cpu(atomDataPtr->FirmwareInfo ++ .FirmwareInfo_V_1_2->ulDefaultMemoryClock) * 10; + break; + case GET_MAX_PIXEL_CLOCK_PLL_OUTPUT: +- *val = atomDataPtr->FirmwareInfo +- .FirmwareInfo_V_1_2->ulMaxPixelClockPLL_Output * 10; ++ *val = le32_to_cpu(atomDataPtr->FirmwareInfo ++ .FirmwareInfo_V_1_2->ulMaxPixelClockPLL_Output) * 10; + break; + case GET_MIN_PIXEL_CLOCK_PLL_OUTPUT: +- *val = atomDataPtr->FirmwareInfo +- .FirmwareInfo_V_1_2->usMinPixelClockPLL_Output * 10; ++ *val = le16_to_cpu(atomDataPtr->FirmwareInfo ++ .FirmwareInfo_V_1_2->usMinPixelClockPLL_Output) * 10; + break; + case GET_MAX_PIXEL_CLOCK_PLL_INPUT: +- *val = atomDataPtr->FirmwareInfo +- .FirmwareInfo_V_1_2->usMaxPixelClockPLL_Input * 10; ++ *val = le16_to_cpu(atomDataPtr->FirmwareInfo ++ .FirmwareInfo_V_1_2->usMaxPixelClockPLL_Input) * 10; + break; + case GET_MIN_PIXEL_CLOCK_PLL_INPUT: +- *val = atomDataPtr->FirmwareInfo +- .FirmwareInfo_V_1_2->usMinPixelClockPLL_Input * 10; ++ *val = le16_to_cpu(atomDataPtr->FirmwareInfo ++ .FirmwareInfo_V_1_2->usMinPixelClockPLL_Input) * 10; + break; + case GET_MAX_PIXEL_CLK: +- *val = atomDataPtr->FirmwareInfo +- .FirmwareInfo_V_1_2->usMaxPixelClock * 10; ++ *val = le16_to_cpu(atomDataPtr->FirmwareInfo ++ .FirmwareInfo_V_1_2->usMaxPixelClock) * 10; + break; + case GET_REF_CLOCK: +- *val = atomDataPtr->FirmwareInfo +- .FirmwareInfo_V_1_2->usReferenceClock * 10; ++ *val = le16_to_cpu(atomDataPtr->FirmwareInfo ++ .FirmwareInfo_V_1_2->usReferenceClock) * 10; + break; + default: + return ATOM_NOT_IMPLEMENTED; +@@ -1300,36 +1289,36 @@ rhdAtomFirmwareInfoQuery(atomBiosHandlePtr handle, + case 3: + switch (func) { + case GET_DEFAULT_ENGINE_CLOCK: +- *val = atomDataPtr->FirmwareInfo +- .FirmwareInfo_V_1_3->ulDefaultEngineClock * 10; ++ *val = le32_to_cpu(atomDataPtr->FirmwareInfo ++ .FirmwareInfo_V_1_3->ulDefaultEngineClock) * 10; + break; + case GET_DEFAULT_MEMORY_CLOCK: +- *val = atomDataPtr->FirmwareInfo +- .FirmwareInfo_V_1_3->ulDefaultMemoryClock * 10; ++ *val = le32_to_cpu(atomDataPtr->FirmwareInfo ++ .FirmwareInfo_V_1_3->ulDefaultMemoryClock) * 10; + break; + case GET_MAX_PIXEL_CLOCK_PLL_OUTPUT: +- *val = atomDataPtr->FirmwareInfo +- .FirmwareInfo_V_1_3->ulMaxPixelClockPLL_Output * 10; ++ *val = le32_to_cpu(atomDataPtr->FirmwareInfo ++ .FirmwareInfo_V_1_3->ulMaxPixelClockPLL_Output) * 10; + break; + case GET_MIN_PIXEL_CLOCK_PLL_OUTPUT: +- *val = atomDataPtr->FirmwareInfo +- .FirmwareInfo_V_1_3->usMinPixelClockPLL_Output * 10; ++ *val = le16_to_cpu(atomDataPtr->FirmwareInfo ++ .FirmwareInfo_V_1_3->usMinPixelClockPLL_Output) * 10; + break; + case GET_MAX_PIXEL_CLOCK_PLL_INPUT: +- *val = atomDataPtr->FirmwareInfo +- .FirmwareInfo_V_1_3->usMaxPixelClockPLL_Input * 10; ++ *val = le16_to_cpu(atomDataPtr->FirmwareInfo ++ .FirmwareInfo_V_1_3->usMaxPixelClockPLL_Input) * 10; + break; + case GET_MIN_PIXEL_CLOCK_PLL_INPUT: +- *val = atomDataPtr->FirmwareInfo +- .FirmwareInfo_V_1_3->usMinPixelClockPLL_Input * 10; ++ *val = le16_to_cpu(atomDataPtr->FirmwareInfo ++ .FirmwareInfo_V_1_3->usMinPixelClockPLL_Input) * 10; + break; + case GET_MAX_PIXEL_CLK: +- *val = atomDataPtr->FirmwareInfo +- .FirmwareInfo_V_1_3->usMaxPixelClock * 10; ++ *val = le16_to_cpu(atomDataPtr->FirmwareInfo ++ .FirmwareInfo_V_1_3->usMaxPixelClock) * 10; + break; + case GET_REF_CLOCK: +- *val = atomDataPtr->FirmwareInfo +- .FirmwareInfo_V_1_3->usReferenceClock * 10; ++ *val = le16_to_cpu(atomDataPtr->FirmwareInfo ++ .FirmwareInfo_V_1_3->usReferenceClock) * 10; + break; + default: + return ATOM_NOT_IMPLEMENTED; +@@ -1338,36 +1327,36 @@ rhdAtomFirmwareInfoQuery(atomBiosHandlePtr handle, + case 4: + switch (func) { + case GET_DEFAULT_ENGINE_CLOCK: +- *val = atomDataPtr->FirmwareInfo +- .FirmwareInfo_V_1_4->ulDefaultEngineClock * 10; ++ *val = le32_to_cpu(atomDataPtr->FirmwareInfo ++ .FirmwareInfo_V_1_4->ulDefaultEngineClock) * 10; + break; + case GET_DEFAULT_MEMORY_CLOCK: +- *val = atomDataPtr->FirmwareInfo +- .FirmwareInfo_V_1_4->ulDefaultMemoryClock * 10; ++ *val = le32_to_cpu(atomDataPtr->FirmwareInfo ++ .FirmwareInfo_V_1_4->ulDefaultMemoryClock) * 10; + break; + case GET_MAX_PIXEL_CLOCK_PLL_INPUT: +- *val = atomDataPtr->FirmwareInfo +- .FirmwareInfo_V_1_4->usMaxPixelClockPLL_Input * 10; ++ *val = le16_to_cpu(atomDataPtr->FirmwareInfo ++ .FirmwareInfo_V_1_4->usMaxPixelClockPLL_Input) * 10; + break; + case GET_MIN_PIXEL_CLOCK_PLL_INPUT: +- *val = atomDataPtr->FirmwareInfo +- .FirmwareInfo_V_1_4->usMinPixelClockPLL_Input * 10; ++ *val = le16_to_cpu(atomDataPtr->FirmwareInfo ++ .FirmwareInfo_V_1_4->usMinPixelClockPLL_Input) * 10; + break; + case GET_MAX_PIXEL_CLOCK_PLL_OUTPUT: +- *val = atomDataPtr->FirmwareInfo +- .FirmwareInfo_V_1_4->ulMaxPixelClockPLL_Output * 10; ++ *val = le32_to_cpu(atomDataPtr->FirmwareInfo ++ .FirmwareInfo_V_1_4->ulMaxPixelClockPLL_Output) * 10; + break; + case GET_MIN_PIXEL_CLOCK_PLL_OUTPUT: +- *val = atomDataPtr->FirmwareInfo +- .FirmwareInfo_V_1_4->usMinPixelClockPLL_Output * 10; ++ *val = le16_to_cpu(atomDataPtr->FirmwareInfo ++ .FirmwareInfo_V_1_4->usMinPixelClockPLL_Output) * 10; + break; + case GET_MAX_PIXEL_CLK: +- *val = atomDataPtr->FirmwareInfo +- .FirmwareInfo_V_1_4->usMaxPixelClock * 10; ++ *val = le16_to_cpu(atomDataPtr->FirmwareInfo ++ .FirmwareInfo_V_1_4->usMaxPixelClock) * 10; + break; + case GET_REF_CLOCK: +- *val = atomDataPtr->FirmwareInfo +- .FirmwareInfo_V_1_4->usReferenceClock * 10; ++ *val = le16_to_cpu(atomDataPtr->FirmwareInfo ++ .FirmwareInfo_V_1_4->usReferenceClock) * 10; + break; + default: + return ATOM_NOT_IMPLEMENTED; @@ -1399,7 +1388,7 @@ const int object_connector_convert[] = CONNECTOR_NONE, CONNECTOR_NONE, @@ -6033,6 +5452,25 @@ index 88c220b..5cc21d5 100644 memset(&i2c, 0, sizeof(RADEONI2CBusRec)); i2c.valid = FALSE; +@@ -1455,12 +1444,12 @@ RADEONLookupGPIOLineForDDC(ScrnInfoPtr pScrn, CARD8 id) + } + + gpio = atomDataPtr->GPIO_I2C_Info->asGPIO_Info[id]; +- i2c.mask_clk_reg = gpio.usClkMaskRegisterIndex * 4; +- i2c.mask_data_reg = gpio.usDataMaskRegisterIndex * 4; +- i2c.put_clk_reg = gpio.usClkEnRegisterIndex * 4; +- i2c.put_data_reg = gpio.usDataEnRegisterIndex * 4; +- i2c.get_clk_reg = gpio.usClkY_RegisterIndex * 4; +- i2c.get_data_reg = gpio.usDataY_RegisterIndex * 4; ++ i2c.mask_clk_reg = le16_to_cpu(gpio.usClkMaskRegisterIndex) * 4; ++ i2c.mask_data_reg = le16_to_cpu(gpio.usDataMaskRegisterIndex) * 4; ++ i2c.put_clk_reg = le16_to_cpu(gpio.usClkEnRegisterIndex) * 4; ++ i2c.put_data_reg = le16_to_cpu(gpio.usDataEnRegisterIndex) * 4; ++ i2c.get_clk_reg = le16_to_cpu(gpio.usClkY_RegisterIndex) * 4; ++ i2c.get_data_reg = le16_to_cpu(gpio.usDataY_RegisterIndex) * 4; + i2c.mask_clk_mask = (1 << gpio.ucClkMaskShift); + i2c.mask_data_mask = (1 << gpio.ucDataMaskShift); + i2c.put_clk_mask = (1 << gpio.ucClkEnShift); @@ -1495,10 +1484,11 @@ Bool RADEONGetATOMConnectorInfoFromBIOSObject (ScrnInfoPtr pScrn) { @@ -6046,7 +5484,7 @@ index 88c220b..5cc21d5 100644 int i, j, ddc_line = 0; atomDataPtr = info->atomBIOS->atomDataPtr; -@@ -1507,7 +1497,7 @@ RADEONGetATOMConnectorInfoFromBIOSObject (ScrnInfoPtr pScrn) +@@ -1507,38 +1497,63 @@ RADEONGetATOMConnectorInfoFromBIOSObject (ScrnInfoPtr pScrn) if (crev < 2) return FALSE; @@ -6054,21 +5492,31 @@ index 88c220b..5cc21d5 100644 + con_obj = (ATOM_CONNECTOR_OBJECT_TABLE *) ((char *)&atomDataPtr->Object_Header->sHeader + - atomDataPtr->Object_Header->usConnectorObjectTableOffset); -@@ -1515,7 +1505,7 @@ RADEONGetATOMConnectorInfoFromBIOSObject (ScrnInfoPtr pScrn) +- atomDataPtr->Object_Header->usConnectorObjectTableOffset); ++ le16_to_cpu(atomDataPtr->Object_Header->usConnectorObjectTableOffset)); + for (i = 0; i < con_obj->ucNumberOfObjects; i++) { ATOM_SRC_DST_TABLE_FOR_ONE_OBJECT *SrcDstTable; ATOM_COMMON_RECORD_HEADER *Record; - CARD8 obj_id, num, obj_type; + uint8_t obj_id, num, obj_type; int record_base; ++ uint16_t con_obj_id = le16_to_cpu(con_obj->asObjects[i].usObjectID); + +- obj_id = (con_obj->asObjects[i].usObjectID & OBJECT_ID_MASK) >> OBJECT_ID_SHIFT; +- num = (con_obj->asObjects[i].usObjectID & ENUM_ID_MASK) >> ENUM_ID_SHIFT; +- obj_type = (con_obj->asObjects[i].usObjectID & OBJECT_TYPE_MASK) >> OBJECT_TYPE_SHIFT; ++ obj_id = (con_obj_id & OBJECT_ID_MASK) >> OBJECT_ID_SHIFT; ++ num = (con_obj_id & ENUM_ID_MASK) >> ENUM_ID_SHIFT; ++ obj_type = (con_obj_id & OBJECT_TYPE_MASK) >> OBJECT_TYPE_SHIFT; + if (obj_type != GRAPH_OBJECT_TYPE_CONNECTOR) + continue; - obj_id = (con_obj->asObjects[i].usObjectID & OBJECT_ID_MASK) >> OBJECT_ID_SHIFT; -@@ -1527,18 +1517,42 @@ RADEONGetATOMConnectorInfoFromBIOSObject (ScrnInfoPtr pScrn) SrcDstTable = (ATOM_SRC_DST_TABLE_FOR_ONE_OBJECT *) ((char *)&atomDataPtr->Object_Header->sHeader - + con_obj->asObjects[i].usSrcDstTableOffset); +- + con_obj->asObjects[i].usSrcDstTableOffset); - ++ + le16_to_cpu(con_obj->asObjects[i].usSrcDstTableOffset)); + ErrorF("object id %04x %02x\n", obj_id, SrcDstTable->ucNumberOfSrc); - info->BiosConnector[i].ConnectorType = object_connector_convert[obj_id]; @@ -6112,7 +5560,7 @@ index 88c220b..5cc21d5 100644 switch(sobj_id) { case ENCODER_OBJECT_ID_INTERNAL_LVDS: info->BiosConnector[i].devices |= (1 << ATOM_DEVICE_LCD1_INDEX); -@@ -1548,6 +1562,13 @@ RADEONGetATOMConnectorInfoFromBIOSObject (ScrnInfoPtr pScrn) +@@ -1548,6 +1563,13 @@ RADEONGetATOMConnectorInfoFromBIOSObject (ScrnInfoPtr pScrn) info->BiosConnector[i].devices |= (1 << ATOM_DEVICE_DFP1_INDEX); info->BiosConnector[i].TMDSType = TMDS_INT; break; @@ -6126,7 +5574,7 @@ index 88c220b..5cc21d5 100644 case ENCODER_OBJECT_ID_INTERNAL_TMDS2: case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1: info->BiosConnector[i].devices |= (1 << ATOM_DEVICE_DFP2_INDEX); -@@ -1560,7 +1581,13 @@ RADEONGetATOMConnectorInfoFromBIOSObject (ScrnInfoPtr pScrn) +@@ -1560,7 +1582,13 @@ RADEONGetATOMConnectorInfoFromBIOSObject (ScrnInfoPtr pScrn) break; case ENCODER_OBJECT_ID_INTERNAL_DAC1: case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1: @@ -6141,7 +5589,7 @@ index 88c220b..5cc21d5 100644 info->BiosConnector[i].DACType = DAC_PRIMARY; break; case ENCODER_OBJECT_ID_INTERNAL_DAC2: -@@ -1568,7 +1595,8 @@ RADEONGetATOMConnectorInfoFromBIOSObject (ScrnInfoPtr pScrn) +@@ -1568,7 +1596,8 @@ RADEONGetATOMConnectorInfoFromBIOSObject (ScrnInfoPtr pScrn) if (info->BiosConnector[i].ConnectorType == CONNECTOR_DIN || info->BiosConnector[i].ConnectorType == CONNECTOR_STV || info->BiosConnector[i].ConnectorType == CONNECTOR_CTV) @@ -6151,7 +5599,19 @@ index 88c220b..5cc21d5 100644 else info->BiosConnector[i].devices |= (1 << ATOM_DEVICE_CRT2_INDEX); info->BiosConnector[i].DACType = DAC_TVDAC; -@@ -1588,7 +1616,7 @@ RADEONGetATOMConnectorInfoFromBIOSObject (ScrnInfoPtr pScrn) +@@ -1578,9 +1607,9 @@ RADEONGetATOMConnectorInfoFromBIOSObject (ScrnInfoPtr pScrn) + + Record = (ATOM_COMMON_RECORD_HEADER *) + ((char *)&atomDataPtr->Object_Header->sHeader +- + con_obj->asObjects[i].usRecordOffset); ++ + le16_to_cpu(con_obj->asObjects[i].usRecordOffset)); + +- record_base = con_obj->asObjects[i].usRecordOffset; ++ record_base = le16_to_cpu(con_obj->asObjects[i].usRecordOffset); + + while (Record->ucRecordType > 0 + && Record->ucRecordType <= ATOM_MAX_OBJECT_RECORD_NUMBER ) { +@@ -1588,7 +1617,7 @@ RADEONGetATOMConnectorInfoFromBIOSObject (ScrnInfoPtr pScrn) ErrorF("record type %d\n", Record->ucRecordType); switch (Record->ucRecordType) { case ATOM_I2C_RECORD_TYPE: @@ -6160,7 +5620,41 @@ index 88c220b..5cc21d5 100644 (ATOM_I2C_RECORD *)Record, &ddc_line); info->BiosConnector[i].ddc_i2c = atom_setup_i2c_bus(ddc_line); -@@ -1708,12 +1736,28 @@ RADEONATOMGetTVTimings(ScrnInfoPtr pScrn, int index, SET_CRTC_TIMING_PARAMETERS_ +@@ -1687,33 +1716,49 @@ RADEONATOMGetTVTimings(ScrnInfoPtr pScrn, int index, SET_CRTC_TIMING_PARAMETERS_ + if (index > MAX_SUPPORTED_TV_TIMING) + return FALSE; + +- crtc_timing->usH_Total = tv_info->aModeTimings[index].usCRTC_H_Total; +- crtc_timing->usH_Disp = tv_info->aModeTimings[index].usCRTC_H_Disp; +- crtc_timing->usH_SyncStart = tv_info->aModeTimings[index].usCRTC_H_SyncStart; +- crtc_timing->usH_SyncWidth = tv_info->aModeTimings[index].usCRTC_H_SyncWidth; ++ crtc_timing->usH_Total = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_H_Total); ++ crtc_timing->usH_Disp = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_H_Disp); ++ crtc_timing->usH_SyncStart = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_H_SyncStart); ++ crtc_timing->usH_SyncWidth = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_H_SyncWidth); + +- crtc_timing->usV_Total = tv_info->aModeTimings[index].usCRTC_V_Total; +- crtc_timing->usV_Disp = tv_info->aModeTimings[index].usCRTC_V_Disp; +- crtc_timing->usV_SyncStart = tv_info->aModeTimings[index].usCRTC_V_SyncStart; +- crtc_timing->usV_SyncWidth = tv_info->aModeTimings[index].usCRTC_V_SyncWidth; ++ crtc_timing->usV_Total = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_V_Total); ++ crtc_timing->usV_Disp = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_V_Disp); ++ crtc_timing->usV_SyncStart = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_V_SyncStart); ++ crtc_timing->usV_SyncWidth = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_V_SyncWidth); + + crtc_timing->susModeMiscInfo = tv_info->aModeTimings[index].susModeMiscInfo; + +- crtc_timing->ucOverscanRight = tv_info->aModeTimings[index].usCRTC_OverscanRight; +- crtc_timing->ucOverscanLeft = tv_info->aModeTimings[index].usCRTC_OverscanLeft; +- crtc_timing->ucOverscanBottom = tv_info->aModeTimings[index].usCRTC_OverscanBottom; +- crtc_timing->ucOverscanTop = tv_info->aModeTimings[index].usCRTC_OverscanTop; +- *pixel_clock = tv_info->aModeTimings[index].usPixelClock * 10; ++ crtc_timing->ucOverscanRight = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_OverscanRight); ++ crtc_timing->ucOverscanLeft = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_OverscanLeft); ++ crtc_timing->ucOverscanBottom = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_OverscanBottom); ++ crtc_timing->ucOverscanTop = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_OverscanTop); ++ *pixel_clock = le16_to_cpu(tv_info->aModeTimings[index].usPixelClock) * 10; + return TRUE; } @@ -6190,7 +5684,28 @@ index 88c220b..5cc21d5 100644 int i, j; atomDataPtr = info->atomBIOS->atomDataPtr; -@@ -1745,13 +1789,14 @@ RADEONGetATOMConnectorInfoFromBIOSConnectorTable (ScrnInfoPtr pScrn) +@@ -1729,8 +1774,8 @@ RADEONGetATOMConnectorInfoFromBIOSConnectorTable (ScrnInfoPtr pScrn) + ATOM_CONNECTOR_INFO_I2C ci + = atomDataPtr->SupportedDevicesInfo.SupportedDevicesInfo->asConnInfo[i]; + +- if (!(atomDataPtr->SupportedDevicesInfo +- .SupportedDevicesInfo->usDeviceSupport & (1 << i))) { ++ if (!(le16_to_cpu(atomDataPtr->SupportedDevicesInfo ++ .SupportedDevicesInfo->usDeviceSupport) & (1 << i))) { + info->BiosConnector[i].valid = FALSE; + continue; + } +@@ -1742,16 +1787,24 @@ RADEONGetATOMConnectorInfoFromBIOSConnectorTable (ScrnInfoPtr pScrn) + continue; + } + #endif ++#if 1 ++ if (i == ATOM_DEVICE_TV1_INDEX) { ++ xf86DrvMsg(pScrn->scrnIndex, X_INFO, "Skipping TV-Out\n"); ++ info->BiosConnector[i].valid = FALSE; ++ continue; ++ } ++#endif info->BiosConnector[i].valid = TRUE; info->BiosConnector[i].output_id = ci.sucI2cId.sbfAccess.bfI2C_LineMux; @@ -6211,7 +5726,7 @@ index 88c220b..5cc21d5 100644 info->BiosConnector[i].DACType = ci.sucConnectorInfo.sbfAccess.bfAssociatedDAC; /* don't assign a gpio for tv */ -@@ -1759,14 +1804,16 @@ RADEONGetATOMConnectorInfoFromBIOSConnectorTable (ScrnInfoPtr pScrn) +@@ -1759,14 +1812,16 @@ RADEONGetATOMConnectorInfoFromBIOSConnectorTable (ScrnInfoPtr pScrn) (i == ATOM_DEVICE_TV2_INDEX) || (i == ATOM_DEVICE_CV_INDEX)) info->BiosConnector[i].ddc_i2c.valid = FALSE; @@ -6233,7 +5748,7 @@ index 88c220b..5cc21d5 100644 } else info->BiosConnector[i].ddc_i2c = RADEONLookupGPIOLineForDDC(pScrn, ci.sucI2cId.sbfAccess.bfI2C_LineMux); -@@ -1774,16 +1821,15 @@ RADEONGetATOMConnectorInfoFromBIOSConnectorTable (ScrnInfoPtr pScrn) +@@ -1774,16 +1829,15 @@ RADEONGetATOMConnectorInfoFromBIOSConnectorTable (ScrnInfoPtr pScrn) if (i == ATOM_DEVICE_DFP1_INDEX) info->BiosConnector[i].TMDSType = TMDS_INT; else if (i == ATOM_DEVICE_DFP2_INDEX) { @@ -6257,7 +5772,7 @@ index 88c220b..5cc21d5 100644 info->BiosConnector[i].TMDSType = TMDS_NONE; /* Always set the connector type to VGA for CRT1/CRT2. if they are -@@ -1816,6 +1862,9 @@ RADEONGetATOMConnectorInfoFromBIOSConnectorTable (ScrnInfoPtr pScrn) +@@ -1816,6 +1870,9 @@ RADEONGetATOMConnectorInfoFromBIOSConnectorTable (ScrnInfoPtr pScrn) } else { info->BiosConnector[i].hpd_mask = 0; } @@ -6267,7 +5782,7 @@ index 88c220b..5cc21d5 100644 } /* CRTs/DFPs may share a port */ -@@ -1859,689 +1908,6 @@ RADEONGetATOMConnectorInfoFromBIOSConnectorTable (ScrnInfoPtr pScrn) +@@ -1859,689 +1916,6 @@ RADEONGetATOMConnectorInfoFromBIOSConnectorTable (ScrnInfoPtr pScrn) return TRUE; } @@ -6957,7 +6472,7 @@ index 88c220b..5cc21d5 100644 # ifdef ATOM_BIOS_PARSER static AtomBiosResult rhdAtomExec (atomBiosHandlePtr handle, -@@ -2566,9 +1932,9 @@ rhdAtomExec (atomBiosHandlePtr handle, +@@ -2566,9 +1940,9 @@ rhdAtomExec (atomBiosHandlePtr handle, __func__); return ATOM_FAILED; } @@ -6969,7 +6484,7 @@ index 88c220b..5cc21d5 100644 } ret = ParseTableWrapper(pspace, idx, handle, handle->BIOSBase, -@@ -2673,7 +2039,7 @@ CailDelayMicroSeconds(VOID *CAIL, UINT32 delay) +@@ -2673,20 +2047,20 @@ CailDelayMicroSeconds(VOID *CAIL, UINT32 delay) usleep(delay); @@ -6978,7 +6493,14 @@ index 88c220b..5cc21d5 100644 } UINT32 -@@ -2686,7 +2052,7 @@ CailReadATIRegister(VOID* CAIL, UINT32 idx) + CailReadATIRegister(VOID* CAIL, UINT32 idx) + { + ScrnInfoPtr pScrn = xf86Screens[((atomBiosHandlePtr)CAIL)->scrnIndex]; +- RADEONInfoPtr info = RADEONPTR(pScrn); +- unsigned char *RADEONMMIO = info->MMIO; ++ RADEONEntPtr pRADEONEnt = RADEONEntPriv(pScrn); ++ unsigned char *RADEONMMIO = pRADEONEnt->MMIO; + UINT32 ret; CAILFUNC(CAIL); ret = INREG(idx << 2); @@ -6987,7 +6509,14 @@ index 88c220b..5cc21d5 100644 return ret; } -@@ -2699,7 +2065,7 @@ CailWriteATIRegister(VOID *CAIL, UINT32 idx, UINT32 data) +@@ -2694,12 +2068,12 @@ VOID + CailWriteATIRegister(VOID *CAIL, UINT32 idx, UINT32 data) + { + ScrnInfoPtr pScrn = xf86Screens[((atomBiosHandlePtr)CAIL)->scrnIndex]; +- RADEONInfoPtr info = RADEONPTR(pScrn); +- unsigned char *RADEONMMIO = info->MMIO; ++ RADEONEntPtr pRADEONEnt = RADEONEntPriv(pScrn); ++ unsigned char *RADEONMMIO = pRADEONEnt->MMIO; CAILFUNC(CAIL); OUTREG(idx << 2,data); @@ -6996,7 +6525,7 @@ index 88c220b..5cc21d5 100644 } UINT32 -@@ -2712,12 +2078,12 @@ CailReadFBData(VOID* CAIL, UINT32 idx) +@@ -2712,12 +2086,12 @@ CailReadFBData(VOID* CAIL, UINT32 idx) CAILFUNC(CAIL); if (((atomBiosHandlePtr)CAIL)->fbBase) { @@ -7014,7 +6543,7 @@ index 88c220b..5cc21d5 100644 } else { xf86DrvMsg(((atomBiosHandlePtr)CAIL)->scrnIndex,X_ERROR, "%s: no fbbase set\n",__func__); -@@ -2731,13 +2097,13 @@ CailWriteFBData(VOID *CAIL, UINT32 idx, UINT32 data) +@@ -2731,13 +2105,13 @@ CailWriteFBData(VOID *CAIL, UINT32 idx, UINT32 data) { CAILFUNC(CAIL); @@ -7032,7 +6561,7 @@ index 88c220b..5cc21d5 100644 } else xf86DrvMsg(((atomBiosHandlePtr)CAIL)->scrnIndex,X_ERROR, "%s: no fbbase set\n",__func__); -@@ -2752,7 +2118,7 @@ CailReadMC(VOID *CAIL, ULONG Address) +@@ -2752,7 +2126,7 @@ CailReadMC(VOID *CAIL, ULONG Address) CAILFUNC(CAIL); ret = INMC(pScrn, Address); @@ -7041,7 +6570,7 @@ index 88c220b..5cc21d5 100644 return ret; } -@@ -2762,7 +2128,7 @@ CailWriteMC(VOID *CAIL, ULONG Address, ULONG data) +@@ -2762,7 +2136,7 @@ CailWriteMC(VOID *CAIL, ULONG Address, ULONG data) ScrnInfoPtr pScrn = xf86Screens[((atomBiosHandlePtr)CAIL)->scrnIndex]; CAILFUNC(CAIL); @@ -7050,7 +6579,7 @@ index 88c220b..5cc21d5 100644 OUTMC(pScrn, Address, data); } -@@ -2793,13 +2159,13 @@ CailReadPCIConfigData(VOID*CAIL, VOID* ret, UINT32 idx,UINT16 size) +@@ -2793,13 +2167,13 @@ CailReadPCIConfigData(VOID*CAIL, VOID* ret, UINT32 idx,UINT16 size) switch (size) { case 8: @@ -7067,7 +6596,7 @@ index 88c220b..5cc21d5 100644 break; default: xf86DrvMsg(((atomBiosHandlePtr)CAIL)->scrnIndex, -@@ -2808,7 +2174,7 @@ CailReadPCIConfigData(VOID*CAIL, VOID* ret, UINT32 idx,UINT16 size) +@@ -2808,7 +2182,7 @@ CailReadPCIConfigData(VOID*CAIL, VOID* ret, UINT32 idx,UINT16 size) return; break; } @@ -7076,7 +6605,7 @@ index 88c220b..5cc21d5 100644 } -@@ -2818,16 +2184,16 @@ CailWritePCIConfigData(VOID*CAIL,VOID*src,UINT32 idx,UINT16 size) +@@ -2818,16 +2192,16 @@ CailWritePCIConfigData(VOID*CAIL,VOID*src,UINT32 idx,UINT16 size) PCITAG tag = ((atomBiosHandlePtr)CAIL)->PciTag; CAILFUNC(CAIL); @@ -7097,7 +6626,7 @@ index 88c220b..5cc21d5 100644 break; default: xf86DrvMsg(((atomBiosHandlePtr)CAIL)->scrnIndex,X_ERROR, -@@ -2846,7 +2212,7 @@ CailReadPLL(VOID *CAIL, ULONG Address) +@@ -2846,7 +2220,7 @@ CailReadPLL(VOID *CAIL, ULONG Address) CAILFUNC(CAIL); ret = RADEONINPLL(pScrn, Address); @@ -7106,7 +6635,7 @@ index 88c220b..5cc21d5 100644 return ret; } -@@ -2856,7 +2222,7 @@ CailWritePLL(VOID *CAIL, ULONG Address,ULONG Data) +@@ -2856,7 +2230,7 @@ CailWritePLL(VOID *CAIL, ULONG Address,ULONG Data) ScrnInfoPtr pScrn = xf86Screens[((atomBiosHandlePtr)CAIL)->scrnIndex]; CAILFUNC(CAIL); @@ -7115,6 +6644,14 @@ index 88c220b..5cc21d5 100644 RADEONOUTPLL(pScrn, Address, Data); } +@@ -2874,6 +2248,7 @@ atombios_get_command_table_version(atomBiosHandlePtr atomBIOS, int index, int *m + + offset = *(((unsigned short *)table_start) + index); + ++ offset = le16_to_cpu(offset); + table_hdr = (ATOM_COMMON_ROM_COMMAND_TABLE_HEADER *)(atomBIOS->BIOSBase + offset); + + *major = table_hdr->CommonHeader.ucTableFormatRevision; diff --git a/src/radeon_atombios.h b/src/radeon_atombios.h index 9cb279e..fe7044d 100644 --- a/src/radeon_atombios.h @@ -7174,10 +6711,10 @@ index 259366c..3e7ae01 100644 #define INT32 INT32 #include "CD_Common_Types.h" diff --git a/src/radeon_bios.c b/src/radeon_bios.c -index 8e6bd8d..bc041c3 100644 +index 8e6bd8d..529dda7 100644 --- a/src/radeon_bios.c +++ b/src/radeon_bios.c -@@ -65,17 +65,216 @@ typedef enum +@@ -65,17 +65,218 @@ typedef enum CONNECTOR_UNSUPPORTED_LEGACY } RADEONLegacyConnectorType; @@ -7197,12 +6734,14 @@ index 8e6bd8d..bc041c3 100644 + if (info->VBIOS[0] != 0x55 || info->VBIOS[1] != 0xaa) { + xf86DrvMsg(pScrn->scrnIndex, X_WARNING, + "Video BIOS not detected in PCI space!\n"); -+ xf86DrvMsg(pScrn->scrnIndex, X_WARNING, -+ "Attempting to read Video BIOS from " -+ "legacy ISA space!\n"); -+ info->BIOSAddr = 0x000c0000; -+ xf86ReadDomainMemory(info->PciTag, info->BIOSAddr, -+ RADEON_VBIOS_SIZE, info->VBIOS); ++ if (xf86IsEntityPrimary(info->pEnt->index)) { ++ xf86DrvMsg(pScrn->scrnIndex, X_WARNING, ++ "Attempting to read Video BIOS from " ++ "legacy ISA space!\n"); ++ info->BIOSAddr = 0x000c0000; ++ xf86ReadDomainMemory(info->PciTag, info->BIOSAddr, ++ RADEON_VBIOS_SIZE, info->VBIOS); ++ } + } +#endif + if (info->VBIOS[0] != 0x55 || info->VBIOS[1] != 0xaa) @@ -7397,7 +6936,7 @@ index 8e6bd8d..bc041c3 100644 #else info->VBIOS = xalloc(RADEON_VBIOS_SIZE); #endif -@@ -88,25 +287,8 @@ Bool RADEONGetBIOSInfo(ScrnInfoPtr pScrn, xf86Int10InfoPtr pInt10) +@@ -88,25 +289,8 @@ Bool RADEONGetBIOSInfo(ScrnInfoPtr pScrn, xf86Int10InfoPtr pInt10) info->BIOSAddr = pInt10->BIOSseg << 4; (void)memcpy(info->VBIOS, xf86int10Addr(pInt10, info->BIOSAddr), RADEON_VBIOS_SIZE); @@ -7425,7 +6964,7 @@ index 8e6bd8d..bc041c3 100644 } } -@@ -160,7 +342,6 @@ Bool RADEONGetBIOSInfo(ScrnInfoPtr pScrn, xf86Int10InfoPtr pInt10) +@@ -160,7 +344,6 @@ Bool RADEONGetBIOSInfo(ScrnInfoPtr pScrn, xf86Int10InfoPtr pInt10) info->IsAtomBios ? "ATOM":"Legacy"); if (info->IsAtomBios) { @@ -7433,23 +6972,28 @@ index 8e6bd8d..bc041c3 100644 AtomBiosArgRec atomBiosArg; if (RHDAtomBiosFunc(pScrn->scrnIndex, NULL, ATOMBIOS_INIT, &atomBiosArg) -@@ -194,8 +375,14 @@ Bool RADEONGetBIOSInfo(ScrnInfoPtr pScrn, xf86Int10InfoPtr pInt10) +@@ -194,10 +377,18 @@ Bool RADEONGetBIOSInfo(ScrnInfoPtr pScrn, xf86Int10InfoPtr pInt10) RHDAtomBiosFunc(pScrn->scrnIndex, info->atomBIOS, GET_REF_CLOCK, &atomBiosArg); -#endif info->MasterDataStart = RADEON_BIOS16 (info->ROMHeaderStart + 32); -+ } else { + } +- ++#if 0 ++ else { + /* non-primary card may need posting */ + if (!pInt10) { + xf86DrvMsg(pScrn->scrnIndex, X_INFO, "Attempting to POST via BIOS tables\n"); + RADEONGetBIOSInitTableOffsets(pScrn); + RADEONPostCardFromBIOSTables(pScrn); + } - } - ++ } ++#endif return TRUE; -@@ -216,6 +403,55 @@ static Bool RADEONGetATOMConnectorInfoFromBIOS (ScrnInfoPtr pScrn) + } + +@@ -216,6 +407,55 @@ static Bool RADEONGetATOMConnectorInfoFromBIOS (ScrnInfoPtr pScrn) return FALSE; } @@ -7505,7 +7049,7 @@ index 8e6bd8d..bc041c3 100644 static Bool RADEONGetLegacyConnectorInfoFromBIOS (ScrnInfoPtr pScrn) { RADEONInfoPtr info = RADEONPTR (pScrn); -@@ -297,28 +533,8 @@ static Bool RADEONGetLegacyConnectorInfoFromBIOS (ScrnInfoPtr pScrn) +@@ -297,28 +537,8 @@ static Bool RADEONGetLegacyConnectorInfoFromBIOS (ScrnInfoPtr pScrn) else info->BiosConnector[i].TMDSType = TMDS_INT; @@ -7535,7 +7079,7 @@ index 8e6bd8d..bc041c3 100644 } } else { xf86DrvMsg(pScrn->scrnIndex, X_WARNING, "No Connector Info Table found!\n"); -@@ -541,7 +757,7 @@ Bool RADEONGetClockInfoFromBIOS (ScrnInfoPtr pScrn) +@@ -541,7 +761,7 @@ Bool RADEONGetClockInfoFromBIOS (ScrnInfoPtr pScrn) { RADEONInfoPtr info = RADEONPTR (pScrn); RADEONPLLPtr pll = &info->pll; @@ -7544,7 +7088,7 @@ index 8e6bd8d..bc041c3 100644 if (!info->VBIOS) { return FALSE; -@@ -620,6 +836,9 @@ Bool RADEONGetDAC2InfoFromBIOS (xf86OutputPtr output) +@@ -620,6 +840,9 @@ Bool RADEONGetDAC2InfoFromBIOS (xf86OutputPtr output) if (!info->VBIOS) return FALSE; @@ -7554,7 +7098,7 @@ index 8e6bd8d..bc041c3 100644 if (info->IsAtomBios) { /* not implemented yet */ return FALSE; -@@ -628,7 +847,21 @@ Bool RADEONGetDAC2InfoFromBIOS (xf86OutputPtr output) +@@ -628,7 +851,21 @@ Bool RADEONGetDAC2InfoFromBIOS (xf86OutputPtr output) offset = RADEON_BIOS16(info->ROMHeaderStart + 0x32); if (offset) { rev = RADEON_BIOS8(offset + 0x3); @@ -7577,7 +7121,7 @@ index 8e6bd8d..bc041c3 100644 bg = RADEON_BIOS8(offset + 0xc) & 0xf; dac = (RADEON_BIOS8(offset + 0xc) >> 4) & 0xf; radeon_output->ps2_tvdac_adj = (bg << 16) | (dac << 20); -@@ -656,6 +889,14 @@ Bool RADEONGetDAC2InfoFromBIOS (xf86OutputPtr output) +@@ -656,6 +893,14 @@ Bool RADEONGetDAC2InfoFromBIOS (xf86OutputPtr output) radeon_output->ntsc_tvdac_adj = radeon_output->ps2_tvdac_adj; return TRUE; @@ -7592,7 +7136,7 @@ index 8e6bd8d..bc041c3 100644 } } } -@@ -793,16 +1034,16 @@ Bool RADEONGetHardCodedEDIDFromBIOS (xf86OutputPtr output) +@@ -793,16 +1038,16 @@ Bool RADEONGetHardCodedEDIDFromBIOS (xf86OutputPtr output) memcpy(EDID, (char*)(info->VBIOS + tmp), 256); @@ -7619,7 +7163,7 @@ index 8e6bd8d..bc041c3 100644 xf86DrvMsg(pScrn->scrnIndex, X_INFO, "Hardcoded EDID data will be used for TMDS panel\n"); } return TRUE; -@@ -813,7 +1054,7 @@ Bool RADEONGetTMDSInfoFromBIOS (xf86OutputPtr output) +@@ -813,7 +1058,7 @@ Bool RADEONGetTMDSInfoFromBIOS (xf86OutputPtr output) ScrnInfoPtr pScrn = output->scrn; RADEONInfoPtr info = RADEONPTR(pScrn); RADEONOutputPrivatePtr radeon_output = output->driver_private; @@ -7628,7 +7172,7 @@ index 8e6bd8d..bc041c3 100644 int i, n; if (!info->VBIOS) return FALSE; -@@ -934,7 +1175,7 @@ Bool RADEONInitExtTMDSInfoFromBIOS (xf86OutputPtr output) +@@ -934,7 +1179,7 @@ Bool RADEONInitExtTMDSInfoFromBIOS (xf86OutputPtr output) unsigned char *RADEONMMIO = info->MMIO; RADEONOutputPrivatePtr radeon_output = output->driver_private; int offset, index, id; @@ -7637,7 +7181,7 @@ index 8e6bd8d..bc041c3 100644 if (!info->VBIOS) return FALSE; -@@ -1044,11 +1285,11 @@ Bool RADEONInitExtTMDSInfoFromBIOS (xf86OutputPtr output) +@@ -1044,11 +1289,11 @@ Bool RADEONInitExtTMDSInfoFromBIOS (xf86OutputPtr output) #define RADEON_PLL_WAIT_DLL_READY_MASK 4 #define RADEON_PLL_WAIT_CHK_SET_CLK_PWRMGT_CNTL24 5 @@ -7652,7 +7196,7 @@ index 8e6bd8d..bc041c3 100644 if (revision > 0x10) { xf86DrvMsg(pScrn->scrnIndex, X_WARNING, -@@ -1069,7 +1310,7 @@ Bool +@@ -1069,7 +1314,7 @@ Bool RADEONGetBIOSInitTableOffsets(ScrnInfoPtr pScrn) { RADEONInfoPtr info = RADEONPTR (pScrn); @@ -7661,7 +7205,7 @@ index 8e6bd8d..bc041c3 100644 if (!info->VBIOS) { return FALSE; -@@ -1163,14 +1404,14 @@ RADEONGetBIOSInitTableOffsets(ScrnInfoPtr pScrn) +@@ -1163,14 +1408,14 @@ RADEONGetBIOSInitTableOffsets(ScrnInfoPtr pScrn) } static void @@ -7681,7 +7225,7 @@ index 8e6bd8d..bc041c3 100644 if (offset == 0) return; -@@ -1271,14 +1512,14 @@ RADEONRestoreBIOSRegBlock(ScrnInfoPtr pScrn, CARD16 table_offset) +@@ -1271,14 +1516,14 @@ RADEONRestoreBIOSRegBlock(ScrnInfoPtr pScrn, CARD16 table_offset) } static void @@ -7701,7 +7245,7 @@ index 8e6bd8d..bc041c3 100644 if (offset == 0) return; -@@ -1315,7 +1556,7 @@ RADEONRestoreBIOSMemBlock(ScrnInfoPtr pScrn, CARD16 table_offset) +@@ -1315,7 +1560,7 @@ RADEONRestoreBIOSMemBlock(ScrnInfoPtr pScrn, CARD16 table_offset) val = (val & RADEON_SDRAM_MODE_MASK) | ormask; OUTREG(RADEON_MM_DATA, val); @@ -7710,7 +7254,7 @@ index 8e6bd8d..bc041c3 100644 ErrorF("INDEX RADEON_MEM_SDRAM_MODE_REG %x %x\n", RADEON_B3MEM_RESET_MASK, (unsigned)ormask); -@@ -1330,13 +1571,13 @@ RADEONRestoreBIOSMemBlock(ScrnInfoPtr pScrn, CARD16 table_offset) +@@ -1330,13 +1575,13 @@ RADEONRestoreBIOSMemBlock(ScrnInfoPtr pScrn, CARD16 table_offset) } static void @@ -7729,7 +7273,7 @@ index 8e6bd8d..bc041c3 100644 if (offset == 0) return; -@@ -1398,11 +1639,11 @@ RADEONRestoreBIOSPllBlock(ScrnInfoPtr pScrn, CARD16 table_offset) +@@ -1398,11 +1643,11 @@ RADEONRestoreBIOSPllBlock(ScrnInfoPtr pScrn, CARD16 table_offset) offset++; andmask = @@ -7745,11 +7289,14 @@ index 8e6bd8d..bc041c3 100644 ErrorF("PLL_MASK_BYTE 0x%x 0x%x 0x%x 0x%x\n", diff --git a/src/radeon_chipinfo_gen.h b/src/radeon_chipinfo_gen.h -index 420f5d8..3459002 100644 +index 420f5d8..ed3174a 100644 --- a/src/radeon_chipinfo_gen.h +++ b/src/radeon_chipinfo_gen.h -@@ -98,20 +98,20 @@ RADEONCardInfo RADEONCards[] = { +@@ -96,18 +96,19 @@ RADEONCardInfo RADEONCards[] = { + { 0x564F, CHIP_FAMILY_RV410, 1, 0, 0, 0, 0 }, + { 0x5652, CHIP_FAMILY_RV410, 1, 0, 0, 0, 0 }, { 0x5653, CHIP_FAMILY_RV410, 1, 0, 0, 0, 0 }, ++ { 0x5657, CHIP_FAMILY_RV410, 0, 0, 0, 0, 0 }, { 0x5834, CHIP_FAMILY_RS300, 0, 1, 0, 0, 1 }, { 0x5835, CHIP_FAMILY_RS300, 1, 1, 0, 0, 1 }, - { 0x5954, CHIP_FAMILY_RS400, 0, 1, 0, 0, 1 }, @@ -7768,13 +7315,15 @@ index 420f5d8..3459002 100644 + { 0x5975, CHIP_FAMILY_RS480, 1, 1, 0, 0, 1 }, { 0x5A41, CHIP_FAMILY_RS400, 0, 1, 0, 0, 1 }, { 0x5A42, CHIP_FAMILY_RS400, 1, 1, 0, 0, 1 }, -- { 0x5A61, CHIP_FAMILY_RS400, 0, 1, 0, 0, 1 }, -- { 0x5A62, CHIP_FAMILY_RS400, 1, 1, 0, 0, 1 }, -+ { 0x5A61, CHIP_FAMILY_RS480, 0, 1, 0, 0, 1 }, -+ { 0x5A62, CHIP_FAMILY_RS480, 1, 1, 0, 0, 1 }, + { 0x5A61, CHIP_FAMILY_RS400, 0, 1, 0, 0, 1 }, +@@ -115,7 +116,6 @@ RADEONCardInfo RADEONCards[] = { { 0x5B60, CHIP_FAMILY_RV380, 0, 0, 0, 0, 0 }, { 0x5B62, CHIP_FAMILY_RV380, 0, 0, 0, 0, 0 }, { 0x5B63, CHIP_FAMILY_RV380, 0, 0, 0, 0, 0 }, +- { 0x5657, CHIP_FAMILY_RV380, 0, 0, 0, 0, 0 }, + { 0x5B64, CHIP_FAMILY_RV380, 0, 0, 0, 0, 0 }, + { 0x5B65, CHIP_FAMILY_RV380, 0, 0, 0, 0, 0 }, + { 0x5C61, CHIP_FAMILY_RV280, 1, 0, 0, 0, 0 }, @@ -201,9 +201,9 @@ RADEONCardInfo RADEONCards[] = { { 0x71D6, CHIP_FAMILY_RV530, 1, 0, 0, 0, 0 }, { 0x71DA, CHIP_FAMILY_RV530, 0, 0, 0, 0, 0 }, @@ -7823,9 +7372,25 @@ index 420f5d8..3459002 100644 + { 0x9613, CHIP_FAMILY_RS780, 0, 1, 0, 0, 1 }, }; diff --git a/src/radeon_chipset_gen.h b/src/radeon_chipset_gen.h -index e6890be..b60e7e8 100644 +index e6890be..d1761d2 100644 --- a/src/radeon_chipset_gen.h +++ b/src/radeon_chipset_gen.h +@@ -96,6 +96,7 @@ static SymTabRec RADEONChipsets[] = { + { PCI_CHIP_RV410_564F, "ATI Mobility Radeon X700 XL (M26) (PCIE)" }, + { PCI_CHIP_RV410_5652, "ATI Mobility Radeon X700 (M26) (PCIE)" }, + { PCI_CHIP_RV410_5653, "ATI Mobility Radeon X700 (M26) (PCIE)" }, ++ { PCI_CHIP_RV410_5657, "ATI Radeon X550XTX 5657 (PCIE)" }, + { PCI_CHIP_RS300_5834, "ATI Radeon 9100 IGP (A5) 5834" }, + { PCI_CHIP_RS300_5835, "ATI Radeon Mobility 9100 IGP (U3) 5835" }, + { PCI_CHIP_RS480_5954, "ATI Radeon XPRESS 200 5954 (PCIE)" }, +@@ -115,7 +116,6 @@ static SymTabRec RADEONChipsets[] = { + { PCI_CHIP_RV370_5B60, "ATI Radeon X300 (RV370) 5B60 (PCIE)" }, + { PCI_CHIP_RV370_5B62, "ATI Radeon X600 (RV370) 5B62 (PCIE)" }, + { PCI_CHIP_RV370_5B63, "ATI Radeon X550 (RV370) 5B63 (PCIE)" }, +- { PCI_CHIP_RV370_5657, "ATI Radeon X550XTX (RV370) 5657 (PCIE)" }, + { PCI_CHIP_RV370_5B64, "ATI FireGL V3100 (RV370) 5B64 (PCIE)" }, + { PCI_CHIP_RV370_5B65, "ATI FireMV 2200 PCIE (RV370) 5B65 (PCIE)" }, + { PCI_CHIP_RV280_5C61, "ATI Radeon Mobility 9200 (M9+) 5C61 (AGP)" }, @@ -201,9 +201,9 @@ static SymTabRec RADEONChipsets[] = { { PCI_CHIP_RV530_71D6, "ATI Mobility Radeon X1700 XT" }, { PCI_CHIP_RV530_71DA, "ATI FireGL V5200" }, @@ -7917,7 +7482,7 @@ index 467addf..193c1f9 100644 typedef struct drm_radeon_getparam { int param; diff --git a/src/radeon_commonfuncs.c b/src/radeon_commonfuncs.c -index 0250aef..b1dd6e8 100644 +index 0250aef..58fe306 100644 --- a/src/radeon_commonfuncs.c +++ b/src/radeon_commonfuncs.c @@ -55,53 +55,49 @@ @@ -8428,15 +7993,12 @@ index 0250aef..b1dd6e8 100644 OUT_ACCEL_REG(R300_RB3D_ZSTENCILCNTL, 0); OUT_ACCEL_REG(R300_RB3D_ZCACHE_CTLSTAT, R300_ZC_FLUSH | R300_ZC_FREE); OUT_ACCEL_REG(R300_RB3D_BW_CNTL, 0); -@@ -205,12 +590,15 @@ static void FUNC_NAME(RADEONInit3DEngine)(ScrnInfoPtr pScrn) +@@ -205,12 +590,12 @@ static void FUNC_NAME(RADEONInit3DEngine)(ScrnInfoPtr pScrn) OUT_ACCEL_REG(R300_SC_SCISSOR1, ((8191 << R300_SCISSOR_X_SHIFT) | (8191 << R300_SCISSOR_Y_SHIFT))); - if (IS_R300_VARIANT || (info->ChipFamily == CHIP_FAMILY_RS690)) { -+ if (IS_R300_VARIANT || -+ (info->ChipFamily == CHIP_FAMILY_RS600) || -+ (info->ChipFamily == CHIP_FAMILY_RS690) || -+ (info->ChipFamily == CHIP_FAMILY_RS740)) { ++ if (IS_R300_3D) { /* clip has offset 1440 */ OUT_ACCEL_REG(R300_SC_CLIP_0_A, ((1088 << R300_CLIP_X_SHIFT) | (1088 << R300_CLIP_Y_SHIFT))); @@ -8447,7 +8009,7 @@ index 0250aef..b1dd6e8 100644 } else { OUT_ACCEL_REG(R300_SC_CLIP_0_A, ((0 << R300_CLIP_X_SHIFT) | (0 << R300_CLIP_Y_SHIFT))); -@@ -239,6 +627,19 @@ static void FUNC_NAME(RADEONInit3DEngine)(ScrnInfoPtr pScrn) +@@ -239,6 +624,19 @@ static void FUNC_NAME(RADEONInit3DEngine)(ScrnInfoPtr pScrn) OUT_ACCEL_REG(R200_SE_VAP_CNTL, R200_VAP_FORCE_W_TO_ONE | R200_VAP_VF_MAX_VTX_NUM); FINISH_ACCEL(); @@ -8467,7 +8029,7 @@ index 0250aef..b1dd6e8 100644 } else { BEGIN_ACCEL(2); if ((info->ChipFamily == CHIP_FAMILY_RADEON) || -@@ -252,20 +653,21 @@ static void FUNC_NAME(RADEONInit3DEngine)(ScrnInfoPtr pScrn) +@@ -252,20 +650,21 @@ static void FUNC_NAME(RADEONInit3DEngine)(ScrnInfoPtr pScrn) RADEON_VTX_ST1_NONPARAMETRIC | RADEON_TEX1_W_ROUTING_USE_W0); FINISH_ACCEL(); @@ -8502,10 +8064,10 @@ index 0250aef..b1dd6e8 100644 diff --git a/src/radeon_crtc.c b/src/radeon_crtc.c -index 3524b75..b1e978c 100644 +index 3524b75..c63b650 100644 --- a/src/radeon_crtc.c +++ b/src/radeon_crtc.c -@@ -57,12 +57,7 @@ extern void atombios_crtc_mode_set(xf86CrtcPtr crtc, +@@ -57,14 +57,9 @@ extern void atombios_crtc_mode_set(xf86CrtcPtr crtc, DisplayModePtr mode, DisplayModePtr adjusted_mode, int x, int y); @@ -8516,8 +8078,11 @@ index 3524b75..b1e978c 100644 extern void atombios_crtc_dpms(xf86CrtcPtr crtc, int mode); -extern void legacy_crtc_dpms(xf86CrtcPtr crtc, int mode); - static void +-static void ++void radeon_crtc_dpms(xf86CrtcPtr crtc, int mode) + { + RADEONInfoPtr info = RADEONPTR(crtc->scrn); @@ -72,6 +67,9 @@ radeon_crtc_dpms(xf86CrtcPtr crtc, int mode) RADEONCrtcPrivatePtr radeon_crtc = crtc->driver_private; xf86CrtcPtr crtc0 = pRADEONEnt->pCrtc[0]; @@ -8540,15 +8105,15 @@ index 3524b75..b1e978c 100644 } static Bool -@@ -103,10 +106,14 @@ radeon_crtc_mode_fixup(xf86CrtcPtr crtc, DisplayModePtr mode, +@@ -103,10 +106,13 @@ radeon_crtc_mode_fixup(xf86CrtcPtr crtc, DisplayModePtr mode, static void radeon_crtc_mode_prepare(xf86CrtcPtr crtc) { +- radeon_crtc_dpms(crtc, DPMSModeOff); + RADEONCrtcPrivatePtr radeon_crtc = crtc->driver_private; + + if (radeon_crtc->enabled) + crtc->funcs->hide_cursor(crtc); - radeon_crtc_dpms(crtc, DPMSModeOff); } -static CARD32 RADEONDiv(CARD64 n, CARD32 d) @@ -8556,7 +8121,7 @@ index 3524b75..b1e978c 100644 { return (n + (d / 2)) / d; } -@@ -114,22 +121,22 @@ static CARD32 RADEONDiv(CARD64 n, CARD32 d) +@@ -114,22 +120,22 @@ static CARD32 RADEONDiv(CARD64 n, CARD32 d) void RADEONComputePLL(RADEONPLLPtr pll, unsigned long freq, @@ -8586,60 +8151,170 @@ index 3524b75..b1e978c 100644 + uint32_t best_post_div = 1; + uint32_t best_ref_div = 1; + uint32_t best_feedback_div = 1; -+ uint32_t best_freq = 1; ++ uint32_t best_freq = -1; + uint32_t best_error = 0xffffffff; + uint32_t best_vco_diff = 1; + uint32_t post_div; freq = freq * 1000; -@@ -139,8 +146,8 @@ RADEONComputePLL(RADEONPLLPtr pll, +@@ -137,10 +143,20 @@ RADEONComputePLL(RADEONPLLPtr pll, + + if (flags & RADEON_PLL_USE_REF_DIV) min_ref_div = max_ref_div = pll->reference_div; ++ else { ++ while (min_ref_div < max_ref_div-1) { ++ uint32_t mid=(min_ref_div+max_ref_div)/2; ++ uint32_t pll_in = pll->reference_freq / mid; ++ if (pll_in < pll->pll_in_min) ++ max_ref_div = mid; ++ else if (pll_in > pll->pll_in_max) ++ min_ref_div = mid; ++ else break; ++ } ++ } for (post_div = pll->min_post_div; post_div <= pll->max_post_div; ++post_div) { - CARD32 ref_div; - CARD32 vco = (freq / 10000) * post_div; + uint32_t ref_div; -+ uint32_t vco = (freq / 10000) * post_div; if ((flags & RADEON_PLL_NO_ODD_POST_DIV) && (post_div & 1)) continue; -@@ -159,8 +166,8 @@ RADEONComputePLL(RADEONPLLPtr pll, - continue; +@@ -155,43 +171,71 @@ RADEONComputePLL(RADEONPLLPtr pll, + continue; + } +- if (vco < pll->pll_out_min || vco > pll->pll_out_max) +- continue; +- for (ref_div = min_ref_div; ref_div <= max_ref_div; ++ref_div) { - CARD32 feedback_div, current_freq, error, vco_diff; - CARD32 pll_in = pll->reference_freq / ref_div; + uint32_t feedback_div, current_freq, error, vco_diff; + uint32_t pll_in = pll->reference_freq / ref_div; ++ uint32_t min_feed_div = pll->min_feedback_div; ++ uint32_t max_feed_div = pll->max_feedback_div+1; if (pll_in < pll->pll_in_min || pll_in > pll->pll_in_max) continue; -@@ -190,8 +197,10 @@ RADEONComputePLL(RADEONPLLPtr pll, - best_vco_diff = vco_diff; + +- feedback_div = RADEONDiv((CARD64)freq * ref_div * post_div, +- pll->reference_freq * 10000); ++ while (min_feed_div < max_feed_div) { ++ uint32_t vco; + +- if (feedback_div < pll->min_feedback_div || feedback_div > pll->max_feedback_div) +- continue; ++ feedback_div = (min_feed_div+max_feed_div)/2; ++ ++ vco = RADEONDiv((CARD64)pll->reference_freq * feedback_div, ++ ref_div); + +- current_freq = RADEONDiv((CARD64)pll->reference_freq * 10000 * feedback_div, +- ref_div * post_div); +- +- error = abs(current_freq - freq); +- vco_diff = abs(vco - best_vco); +- +- if ((best_vco == 0 && error < best_error) || +- (ref_div == pll->reference_div) || +- (best_vco != 0 && +- (error < best_error - 100 || +- (abs(error - best_error) < 100 && vco_diff < best_vco_diff )))) { +- best_post_div = post_div; +- best_ref_div = ref_div; +- best_feedback_div = feedback_div; +- best_freq = current_freq; +- best_error = error; +- best_vco_diff = vco_diff; ++ if (vco < pll->pll_out_min) { ++ min_feed_div = feedback_div+1; ++ continue; ++ } else if(vco > pll->pll_out_max) { ++ max_feed_div = feedback_div; ++ continue; ++ } ++ ++ current_freq = RADEONDiv((CARD64)pll->reference_freq * 10000 * feedback_div, ++ ref_div * post_div); ++ ++ error = abs(current_freq - freq); ++ vco_diff = abs(vco - best_vco); ++ ++ if ((best_vco == 0 && error < best_error) || ++ (best_vco != 0 && ++ (error < best_error - 100 || ++ (abs(error - best_error) < 100 && vco_diff < best_vco_diff )))) { ++ best_post_div = post_div; ++ best_ref_div = ref_div; ++ best_feedback_div = feedback_div; ++ best_freq = current_freq; ++ best_error = error; ++ best_vco_diff = vco_diff; ++ } else if (current_freq == freq) { ++ if (best_freq == -1) { ++ best_post_div = post_div; ++ best_ref_div = ref_div; ++ best_feedback_div = feedback_div; ++ best_freq = current_freq; ++ best_error = error; ++ best_vco_diff = vco_diff; ++ } else if ((flags & RADEON_PLL_PREFER_LOW_REF_DIV) && (ref_div < best_ref_div)) { ++ best_post_div = post_div; ++ best_ref_div = ref_div; ++ best_feedback_div = feedback_div; ++ best_freq = current_freq; ++ best_error = error; ++ best_vco_diff = vco_diff; ++ } ++ } ++ ++ if (current_freq < freq) ++ min_feed_div = feedback_div+1; ++ else ++ max_feed_div = feedback_div; } } - if (best_freq == freq) - break; -+ if (!(flags & RADEON_PLL_DCE3)) { -+ if (best_freq == freq) -+ break; -+ } } ErrorF("best_freq: %u\n", (unsigned int)best_freq); -@@ -238,6 +247,10 @@ radeon_crtc_mode_commit(xf86CrtcPtr crtc) - } - - radeon_crtc_dpms(crtc, DPMSModeOn); -+ +@@ -199,6 +243,8 @@ RADEONComputePLL(RADEONPLLPtr pll, + ErrorF("best_ref_div: %u\n", (unsigned int)best_ref_div); + ErrorF("best_post_div: %u\n", (unsigned int)best_post_div); + ++ if (best_freq == -1) ++ FatalError("Couldn't find valid PLL dividers\n"); + *chosen_dot_clock_freq = best_freq / 10000; + *chosen_feedback_div = best_feedback_div; + *chosen_reference_div = best_ref_div; +@@ -223,21 +269,8 @@ radeon_crtc_mode_set(xf86CrtcPtr crtc, DisplayModePtr mode, + static void + radeon_crtc_mode_commit(xf86CrtcPtr crtc) + { +- RADEONInfoPtr info = RADEONPTR(crtc->scrn); +- RADEONEntPtr pRADEONEnt = RADEONEntPriv(crtc->scrn); +- RADEONCrtcPrivatePtr radeon_crtc = crtc->driver_private; +- +- if (info->ChipFamily >= CHIP_FAMILY_R600) { +- xf86CrtcPtr other; +- if (radeon_crtc->crtc_id == 1) +- other = pRADEONEnt->pCrtc[0]; +- else +- other = pRADEONEnt->pCrtc[1]; +- if (other->enabled) +- radeon_crtc_dpms(other, DPMSModeOn); +- } +- +- radeon_crtc_dpms(crtc, DPMSModeOn); + if (crtc->scrn->pScreen != NULL) + xf86_reload_cursors(crtc->scrn->pScreen); -+ } void -@@ -275,12 +288,16 @@ radeon_crtc_load_lut(xf86CrtcPtr crtc) +@@ -275,12 +308,16 @@ radeon_crtc_load_lut(xf86CrtcPtr crtc) OUTPAL(i, radeon_crtc->lut_r[i], radeon_crtc->lut_g[i], radeon_crtc->lut_b[i]); } @@ -8658,7 +8333,7 @@ index 3524b75..b1e978c 100644 { RADEONCrtcPrivatePtr radeon_crtc = crtc->driver_private; ScrnInfoPtr pScrn = crtc->scrn; -@@ -533,11 +550,12 @@ static const xf86CrtcFuncsRec radeon_crtc_funcs = { +@@ -533,11 +570,12 @@ static const xf86CrtcFuncsRec radeon_crtc_funcs = { Bool RADEONAllocateControllers(ScrnInfoPtr pScrn, int mask) { RADEONEntPtr pRADEONEnt = RADEONEntPriv(pScrn); @@ -8672,7 +8347,7 @@ index 3524b75..b1e978c 100644 pRADEONEnt->pCrtc[0] = xf86CrtcCreate(pScrn, &radeon_crtc_funcs); if (!pRADEONEnt->pCrtc[0]) return FALSE; -@@ -549,16 +567,20 @@ Bool RADEONAllocateControllers(ScrnInfoPtr pScrn, int mask) +@@ -549,16 +587,20 @@ Bool RADEONAllocateControllers(ScrnInfoPtr pScrn, int mask) pRADEONEnt->pCrtc[0]->driver_private = pRADEONEnt->Controller[0]; pRADEONEnt->Controller[0]->crtc_id = 0; pRADEONEnt->Controller[0]->crtc_offset = 0; @@ -8695,7 +8370,7 @@ index 3524b75..b1e978c 100644 pRADEONEnt->Controller[1] = xnfcalloc(sizeof(RADEONCrtcPrivateRec), 1); if (!pRADEONEnt->Controller[1]) { -@@ -569,6 +591,10 @@ Bool RADEONAllocateControllers(ScrnInfoPtr pScrn, int mask) +@@ -569,6 +611,10 @@ Bool RADEONAllocateControllers(ScrnInfoPtr pScrn, int mask) pRADEONEnt->pCrtc[1]->driver_private = pRADEONEnt->Controller[1]; pRADEONEnt->Controller[1]->crtc_id = 1; pRADEONEnt->Controller[1]->crtc_offset = AVIVO_D2CRTC_H_TOTAL - AVIVO_D1CRTC_H_TOTAL; @@ -8706,7 +8381,7 @@ index 3524b75..b1e978c 100644 } return TRUE; -@@ -719,3 +745,41 @@ RADEONUnblank(ScrnInfoPtr pScrn) +@@ -719,3 +765,41 @@ RADEONUnblank(ScrnInfoPtr pScrn) } } @@ -8939,7 +8614,7 @@ index ab5d278..d623fe4 100644 info->XAAForceTransBlit = FALSE; diff --git a/src/radeon_dri.c b/src/radeon_dri.c -index ac8d03c..9fdc5b6 100644 +index ac8d03c..0fc03e4 100644 --- a/src/radeon_dri.c +++ b/src/radeon_dri.c @@ -451,17 +451,17 @@ static void RADEONDRISwapContext(ScreenPtr pScreen, DRISyncType syncType, @@ -8982,7 +8657,52 @@ index ac8d03c..9fdc5b6 100644 Bool is_v3 = (agp_status & RADEON_AGPv3_MODE); unsigned int defaultMode; MessageType from; -@@ -1903,7 +1903,7 @@ static void RADEONDRIRefreshArea(ScrnInfoPtr pScrn, RegionPtr pReg) +@@ -820,11 +820,24 @@ static Bool RADEONSetAgpMode(RADEONInfoPtr info, ScreenPtr pScreen) + } + + /* Initialize Radeon's AGP registers */ +-static void RADEONSetAgpBase(RADEONInfoPtr info) ++static void RADEONSetAgpBase(RADEONInfoPtr info, ScreenPtr pScreen) + { ++ ScrnInfoPtr pScrn = xf86Screens[pScreen->myNum]; + unsigned char *RADEONMMIO = info->MMIO; + +- OUTREG(RADEON_AGP_BASE, drmAgpBase(info->drmFD)); ++ /* drm already does this, so we can probably remove this. ++ * agp_base_2 ? ++ */ ++ if (info->ChipFamily == CHIP_FAMILY_RV515) ++ OUTMC(pScrn, RV515_MC_AGP_BASE, drmAgpBase(info->drmFD)); ++ else if ((info->ChipFamily >= CHIP_FAMILY_R520) && ++ (info->ChipFamily <= CHIP_FAMILY_RV570)) ++ OUTMC(pScrn, R520_MC_AGP_BASE, drmAgpBase(info->drmFD)); ++ else if ((info->ChipFamily == CHIP_FAMILY_RS690) || ++ (info->ChipFamily == CHIP_FAMILY_RS740)) ++ OUTMC(pScrn, RS690_MC_AGP_BASE, drmAgpBase(info->drmFD)); ++ else if (info->ChipFamily < CHIP_FAMILY_RV515) ++ OUTREG(RADEON_AGP_BASE, drmAgpBase(info->drmFD)); + } + + /* Initialize the AGP state. Request memory for use in AGP space, and +@@ -940,7 +953,7 @@ static Bool RADEONDRIAgpInit(RADEONInfoPtr info, ScreenPtr pScreen) + "[agp] GART Texture map mapped at 0x%08lx\n", + (unsigned long)info->gartTex); + +- RADEONSetAgpBase(info); ++ RADEONSetAgpBase(info, pScreen); + + return TRUE; + } +@@ -1722,7 +1735,7 @@ void RADEONDRIResume(ScreenPtr pScreen) + if (!RADEONSetAgpMode(info, pScreen)) + return; + +- RADEONSetAgpBase(info); ++ RADEONSetAgpBase(info, pScreen); + } + + _ret = drmCommandNone(info->drmFD, DRM_RADEON_CP_RESUME); +@@ -1903,7 +1916,7 @@ static void RADEONDRIRefreshArea(ScrnInfoPtr pScrn, RegionPtr pReg) #ifdef USE_EXA if (info->useEXA) { @@ -8991,7 +8711,7 @@ index ac8d03c..9fdc5b6 100644 RADEONGetPixmapOffsetPitch(pPix, &src_pitch_offset); dst_pitch_offset = src_pitch_offset + (info->backOffset >> 10); -@@ -1924,7 +1924,7 @@ static void RADEONDRIRefreshArea(ScrnInfoPtr pScrn, RegionPtr pReg) +@@ -1924,7 +1937,7 @@ static void RADEONDRIRefreshArea(ScrnInfoPtr pScrn, RegionPtr pReg) info->dst_pitch_offset |= RADEON_DST_TILE_MACRO; (*info->accel->SetupForScreenToScreenCopy)(pScrn, 1, 1, GXcopy, @@ -9014,7 +8734,7 @@ index 3b54626..67892a6 100644 #define RADEON_DEFAULT_PCI_APER_SIZE 32 /* in MB */ diff --git a/src/radeon_driver.c b/src/radeon_driver.c -index 5cf8d51..91421b5 100644 +index 5cf8d51..f18ad99 100644 --- a/src/radeon_driver.c +++ b/src/radeon_driver.c @@ -126,35 +126,6 @@ static void RADEONSaveMemMapRegisters(ScrnInfoPtr pScrn, RADEONSavePtr save); @@ -9053,11 +8773,12 @@ index 5cf8d51..91421b5 100644 static const OptionInfoRec RADEONOptions[] = { { OPTION_NOACCEL, "NoAccel", OPTV_BOOLEAN, {0}, FALSE }, { OPTION_SW_CURSOR, "SWcursor", OPTV_BOOLEAN, {0}, FALSE }, -@@ -219,24 +190,23 @@ static const OptionInfoRec RADEONOptions[] = { +@@ -219,24 +190,24 @@ static const OptionInfoRec RADEONOptions[] = { { OPTION_FORCE_TVOUT, "ForceTVOut", OPTV_BOOLEAN, {0}, FALSE }, { OPTION_TVSTD, "TVStandard", OPTV_STRING, {0}, FALSE }, { OPTION_IGNORE_LID_STATUS, "IgnoreLidStatus", OPTV_BOOLEAN, {0}, FALSE }, + { OPTION_DEFAULT_TVDAC_ADJ, "DefaultTVDACAdj", OPTV_BOOLEAN, {0}, FALSE }, ++ { OPTION_INT10, "Int10", OPTV_BOOLEAN, {0}, FALSE }, { -1, NULL, OPTV_NONE, {0}, FALSE } }; @@ -9085,15 +8806,16 @@ index 5cf8d51..91421b5 100644 }; static Bool RADEONMapMMIO(ScrnInfoPtr pScrn); -@@ -253,7 +223,7 @@ radeonShadowWindow(ScreenPtr screen, CARD32 row, CARD32 offset, int mode, +@@ -253,8 +224,7 @@ radeonShadowWindow(ScreenPtr screen, CARD32 row, CARD32 offset, int mode, stride = (pScrn->displayWidth * pScrn->bitsPerPixel) / 8; *size = stride; - return ((CARD8 *)info->FB + pScrn->fbOffset + -+ return ((uint8_t *)info->FB + pScrn->fbOffset + - row * stride + offset); +- row * stride + offset); ++ return ((uint8_t *)info->FB + row * stride + offset); } static Bool + RADEONCreateScreenResources (ScreenPtr pScreen) @@ -292,8 +262,8 @@ RADEONPreInt10Save(ScrnInfoPtr pScrn, void **pPtr) { RADEONInfoPtr info = RADEONPTR(pScrn); @@ -9451,16 +9173,113 @@ index 5cf8d51..91421b5 100644 if (info->ChipFamily >= CHIP_FAMILY_R600) { aper0_base = INREG(R600_CONFIG_F0_BASE); -@@ -1338,7 +1358,7 @@ static void RADEONGetVRamType(ScrnInfoPtr pScrn) +@@ -1338,17 +1358,64 @@ static void RADEONGetVRamType(ScrnInfoPtr pScrn) RADEONInfoPtr info = RADEONPTR(pScrn); RADEONEntPtr pRADEONEnt = RADEONEntPriv(pScrn); unsigned char *RADEONMMIO = info->MMIO; - CARD32 tmp; +- +- if (info->IsIGP || (info->ChipFamily >= CHIP_FAMILY_R300) || +- (INREG(RADEON_MEM_SDRAM_MODE_REG) & (1<<30))) + uint32_t tmp; - - if (info->IsIGP || (info->ChipFamily >= CHIP_FAMILY_R300) || - (INREG(RADEON_MEM_SDRAM_MODE_REG) & (1<<30))) -@@ -1379,11 +1399,11 @@ static void RADEONGetVRamType(ScrnInfoPtr pScrn) ++ ++ if (info->IsIGP || (info->ChipFamily >= CHIP_FAMILY_R300)) ++ info->IsDDR = TRUE; ++ else if (INREG(RADEON_MEM_SDRAM_MODE_REG) & RADEON_MEM_CFG_TYPE_DDR) + info->IsDDR = TRUE; + else + info->IsDDR = FALSE; + +- tmp = INREG(RADEON_MEM_CNTL); +- if (IS_R300_VARIANT) { +- tmp &= R300_MEM_NUM_CHANNELS_MASK; ++ if ((info->ChipFamily >= CHIP_FAMILY_R600) && ++ (info->ChipFamily <= CHIP_FAMILY_RV635)) { ++ int chansize; ++ /* r6xx */ ++ tmp = INREG(R600_RAMCFG); ++ if (tmp & R600_CHANSIZE_OVERRIDE) ++ chansize = 16; ++ else if (tmp & R600_CHANSIZE) ++ chansize = 64; ++ else ++ chansize = 32; ++ if (info->ChipFamily == CHIP_FAMILY_R600) ++ info->RamWidth = 8 * chansize; ++ else if (info->ChipFamily == CHIP_FAMILY_RV670) ++ info->RamWidth = 4 * chansize; ++ else if ((info->ChipFamily == CHIP_FAMILY_RV610) || ++ (info->ChipFamily == CHIP_FAMILY_RV620)) ++ info->RamWidth = chansize; ++ else if ((info->ChipFamily == CHIP_FAMILY_RV630) || ++ (info->ChipFamily == CHIP_FAMILY_RV635)) ++ info->RamWidth = 2 * chansize; ++ } else if (info->ChipFamily == CHIP_FAMILY_RV515) { ++ /* rv515/rv550 */ ++ tmp = INMC(pScrn, RV515_MC_CNTL); ++ tmp &= RV515_MEM_NUM_CHANNELS_MASK; ++ switch (tmp) { ++ case 0: info->RamWidth = 64; break; ++ case 1: info->RamWidth = 128; break; ++ default: info->RamWidth = 128; break; ++ } ++ } else if ((info->ChipFamily >= CHIP_FAMILY_R520) && ++ (info->ChipFamily <= CHIP_FAMILY_RV570)){ ++ /* r520/rv530/rv560/rv570/r580 */ ++ tmp = INMC(pScrn, R520_MC_CNTL0); ++ switch ((tmp & R520_MEM_NUM_CHANNELS_MASK) >> R520_MEM_NUM_CHANNELS_SHIFT) { ++ case 0: info->RamWidth = 32; break; ++ case 1: info->RamWidth = 64; break; ++ case 2: info->RamWidth = 128; break; ++ case 3: info->RamWidth = 256; break; ++ default: info->RamWidth = 64; break; ++ } ++ if (tmp & R520_MC_CHANNEL_SIZE) { ++ info->RamWidth *= 2; ++ } ++ } else if ((info->ChipFamily >= CHIP_FAMILY_R300) && ++ (info->ChipFamily <= CHIP_FAMILY_RV410)) { ++ /* r3xx, r4xx */ ++ tmp = INREG(RADEON_MEM_CNTL); ++ tmp &= R300_MEM_NUM_CHANNELS_MASK; + switch (tmp) { + case 0: info->RamWidth = 64; break; + case 1: info->RamWidth = 128; break; +@@ -1358,15 +1425,25 @@ static void RADEONGetVRamType(ScrnInfoPtr pScrn) + } else if ((info->ChipFamily == CHIP_FAMILY_RV100) || + (info->ChipFamily == CHIP_FAMILY_RS100) || + (info->ChipFamily == CHIP_FAMILY_RS200)){ +- if (tmp & RV100_HALF_MODE) info->RamWidth = 32; +- else info->RamWidth = 64; +- if (!pRADEONEnt->HasCRTC2) { +- info->RamWidth /= 4; +- info->IsDDR = TRUE; +- } ++ tmp = INREG(RADEON_MEM_CNTL); ++ if (tmp & RV100_HALF_MODE) ++ info->RamWidth = 32; ++ else ++ info->RamWidth = 64; ++ ++ if (!pRADEONEnt->HasCRTC2) { ++ info->RamWidth /= 4; ++ info->IsDDR = TRUE; ++ } ++ } else if (info->ChipFamily <= CHIP_FAMILY_RV280) { ++ tmp = INREG(RADEON_MEM_CNTL); ++ if (tmp & RADEON_MEM_NUM_CHANNELS_MASK) ++ info->RamWidth = 128; ++ else ++ info->RamWidth = 64; + } else { +- if (tmp & RADEON_MEM_NUM_CHANNELS_MASK) info->RamWidth = 128; +- else info->RamWidth = 64; ++ /* newer IGPs */ ++ info->RamWidth = 128; + } + + /* This may not be correct, as some cards can have half of channel disabled +@@ -1379,11 +1456,11 @@ static void RADEONGetVRamType(ScrnInfoPtr pScrn) * accessible to the CPU can vary. This function is our best shot at figuring * it out. Returns a value in KB. */ @@ -9474,7 +9293,7 @@ index 5cf8d51..91421b5 100644 unsigned char byte; if (info->ChipFamily >= CHIP_FAMILY_R600) -@@ -1456,25 +1476,22 @@ static Bool RADEONPreInitVRAM(ScrnInfoPtr pScrn) +@@ -1456,25 +1533,22 @@ static Bool RADEONPreInitVRAM(ScrnInfoPtr pScrn) GDevPtr dev = pEnt->device; unsigned char *RADEONMMIO = info->MMIO; MessageType from = X_PROBED; @@ -9504,7 +9323,7 @@ index 5cf8d51..91421b5 100644 /* Some production boards of m6 will return 0 if it's 8 MB */ if (pScrn->videoRam == 0) { pScrn->videoRam = 8192; -@@ -1614,7 +1631,7 @@ static Bool RADEONPreInitChipType(ScrnInfoPtr pScrn) +@@ -1614,7 +1688,7 @@ static Bool RADEONPreInitChipType(ScrnInfoPtr pScrn) break; } } @@ -9513,7 +9332,7 @@ index 5cf8d51..91421b5 100644 switch (info->Chipset) { case PCI_CHIP_RN50_515E: /* RN50 is based on the RV100 but 3D isn't guaranteed to work. YMMV. */ case PCI_CHIP_RN50_5969: -@@ -1636,6 +1653,13 @@ static Bool RADEONPreInitChipType(ScrnInfoPtr pScrn) +@@ -1636,6 +1710,13 @@ static Bool RADEONPreInitChipType(ScrnInfoPtr pScrn) xf86DrvMsg(pScrn->scrnIndex, X_INFO, "DELL server detected, force to special setup\n"); } break; @@ -9527,7 +9346,7 @@ index 5cf8d51..91421b5 100644 default: break; } -@@ -1811,6 +1835,21 @@ static Bool RADEONPreInitChipType(ScrnInfoPtr pScrn) +@@ -1811,6 +1892,21 @@ static Bool RADEONPreInitChipType(ScrnInfoPtr pScrn) if (!xf86LoadSubModule(pScrn, "shadow")) return FALSE; } @@ -9549,7 +9368,7 @@ index 5cf8d51..91421b5 100644 return TRUE; } -@@ -1939,7 +1978,21 @@ static Bool RADEONPreInitInt10(ScrnInfoPtr pScrn, xf86Int10InfoPtr *ppInt10) +@@ -1939,7 +2035,22 @@ static Bool RADEONPreInitInt10(ScrnInfoPtr pScrn, xf86Int10InfoPtr *ppInt10) #if !defined(__powerpc__) && !defined(__sparc__) RADEONInfoPtr info = RADEONPTR(pScrn); unsigned char *RADEONMMIO = info->MMIO; @@ -9564,15 +9383,16 @@ index 5cf8d51..91421b5 100644 + /* don't need int10 on atom cards. + * in theory all radeons, but the older stuff + * isn't 100% yet ++ * secondary atom cards tend to hang when initializing int10, ++ * however, on some stom cards, you can't read the bios without ++ * intitializing int10. + */ -+ if ((info->ChipFamily == CHIP_FAMILY_R420) || -+ (info->ChipFamily == CHIP_FAMILY_RV410) || -+ (info->ChipFamily >= CHIP_FAMILY_RV515)) ++ if (!xf86ReturnOptValBool(info->Options, OPTION_INT10, TRUE)) + return TRUE; if (xf86LoadSubModule(pScrn, "int10")) { /* The VGA BIOS on the RV100/QY cannot be read when the digital output -@@ -1952,13 +2005,15 @@ static Bool RADEONPreInitInt10(ScrnInfoPtr pScrn, xf86Int10InfoPtr *ppInt10) +@@ -1952,13 +2063,15 @@ static Bool RADEONPreInitInt10(ScrnInfoPtr pScrn, xf86Int10InfoPtr *ppInt10) OUTREG(RADEON_FP2_GEN_CNTL, fp2_gen_ctl_save & ~RADEON_FP2_ON); } } @@ -9592,7 +9412,7 @@ index 5cf8d51..91421b5 100644 } } #endif -@@ -1996,13 +2051,14 @@ static Bool RADEONPreInitDRI(ScrnInfoPtr pScrn) +@@ -1996,13 +2109,14 @@ static Bool RADEONPreInitDRI(ScrnInfoPtr pScrn) info->Chipset == PCI_CHIP_RC410_5A61 || info->Chipset == PCI_CHIP_RC410_5A62 || info->Chipset == PCI_CHIP_RS485_5975 || @@ -9610,7 +9430,7 @@ index 5cf8d51..91421b5 100644 xf86DrvMsg(pScrn->scrnIndex, X_INFO, "Direct rendering not officially supported on RN50/RC410/R600\n"); return FALSE; -@@ -2163,7 +2219,14 @@ static Bool RADEONPreInitDRI(ScrnInfoPtr pScrn) +@@ -2163,7 +2277,14 @@ static Bool RADEONPreInitDRI(ScrnInfoPtr pScrn) } else { from = xf86GetOptValBool(info->Options, OPTION_PAGE_FLIP, &info->allowPageFlip) ? X_CONFIG : X_DEFAULT; @@ -9626,7 +9446,7 @@ index 5cf8d51..91421b5 100644 } #else from = X_DEFAULT; -@@ -2221,7 +2284,7 @@ static void RADEONPreInitColorTiling(ScrnInfoPtr pScrn) +@@ -2221,7 +2342,7 @@ static void RADEONPreInitColorTiling(ScrnInfoPtr pScrn) info->pKernelDRMVersion->version_minor, info->pKernelDRMVersion->version_patchlevel); info->allowColorTiling = FALSE; @@ -9635,7 +9455,7 @@ index 5cf8d51..91421b5 100644 } #endif /* XF86DRI */ -@@ -2236,9 +2299,9 @@ static void RADEONPreInitColorTiling(ScrnInfoPtr pScrn) +@@ -2236,9 +2357,9 @@ static void RADEONPreInitColorTiling(ScrnInfoPtr pScrn) static Bool RADEONPreInitXv(ScrnInfoPtr pScrn) { RADEONInfoPtr info = RADEONPTR(pScrn); @@ -9648,7 +9468,7 @@ index 5cf8d51..91421b5 100644 #ifdef XvExtension char* microc_path = NULL; char* microc_type = NULL; -@@ -2366,7 +2429,7 @@ static Bool RADEONPreInitXv(ScrnInfoPtr pScrn) +@@ -2366,7 +2487,7 @@ static Bool RADEONPreInitXv(ScrnInfoPtr pScrn) } bios_header=info->VBIOS[0x48]; @@ -9657,18 +9477,31 @@ index 5cf8d51..91421b5 100644 mm_table=info->VBIOS[bios_header+0x38]; if(mm_table==0) -@@ -2423,10 +2486,6 @@ static Bool RADEONPreInitXv(ScrnInfoPtr pScrn) - static void RADEONPreInitBIOS(ScrnInfoPtr pScrn, xf86Int10InfoPtr pInt10) +@@ -2420,13 +2541,17 @@ static Bool RADEONPreInitXv(ScrnInfoPtr pScrn) + return TRUE; + } + +-static void RADEONPreInitBIOS(ScrnInfoPtr pScrn, xf86Int10InfoPtr pInt10) ++static Bool ++RADEONPreInitBIOS(ScrnInfoPtr pScrn, xf86Int10InfoPtr pInt10) { - RADEONGetBIOSInfo(pScrn, pInt10); +- RADEONGetBIOSInfo(pScrn, pInt10); -#if 0 - RADEONGetBIOSInitTableOffsets(pScrn); - RADEONPostCardFromBIOSTables(pScrn); -#endif ++ RADEONInfoPtr info = RADEONPTR(pScrn); ++ ++ if (!RADEONGetBIOSInfo(pScrn, pInt10)) { ++ /* Avivo chips require bios for atom */ ++ if (IS_AVIVO_VARIANT) ++ return FALSE; ++ } ++ return TRUE; } static void RADEONFixZaphodOutputs(ScrnInfoPtr pScrn) -@@ -2636,8 +2695,7 @@ Bool RADEONPreInit(ScrnInfoPtr pScrn, int flags) +@@ -2636,8 +2761,7 @@ Bool RADEONPreInit(ScrnInfoPtr pScrn, int flags) if (xf86RegisterResources(info->pEnt->index, 0, ResExclusive)) goto fail; @@ -9678,7 +9511,7 @@ index 5cf8d51..91421b5 100644 pScrn->racMemFlags = RAC_FB | RAC_COLORMAP | RAC_VIEWPORT | RAC_CURSOR; pScrn->monitor = pScrn->confScreen->monitor; -@@ -2689,7 +2747,7 @@ Bool RADEONPreInit(ScrnInfoPtr pScrn, int flags) +@@ -2689,7 +2813,7 @@ Bool RADEONPreInit(ScrnInfoPtr pScrn, int flags) if (!RADEONPreInitWeight(pScrn)) goto fail; @@ -9687,7 +9520,7 @@ index 5cf8d51..91421b5 100644 if ((s = xf86GetOptValString(info->Options, OPTION_DISP_PRIORITY))) { if (strcmp(s, "AUTO") == 0) { info->DispPriority = 1; -@@ -2698,17 +2756,17 @@ Bool RADEONPreInit(ScrnInfoPtr pScrn, int flags) +@@ -2698,19 +2822,20 @@ Bool RADEONPreInit(ScrnInfoPtr pScrn, int flags) } else if (strcmp(s, "HIGH") == 0) { info->DispPriority = 2; } else @@ -9704,12 +9537,15 @@ index 5cf8d51..91421b5 100644 RADEONPostInt10Check(pScrn, int10_save); - if (!RADEONPreInitChipType(pScrn)) -- goto fail; -- - RADEONPreInitBIOS(pScrn, pInt10); ++ if (!RADEONPreInitBIOS(pScrn, pInt10)) + goto fail; +- RADEONPreInitBIOS(pScrn, pInt10); +- #ifdef XF86DRI -@@ -2739,17 +2797,22 @@ Bool RADEONPreInit(ScrnInfoPtr pScrn, int flags) + /* PreInit DRI first of all since we need that for getting a proper + * memory map +@@ -2739,17 +2864,22 @@ Bool RADEONPreInit(ScrnInfoPtr pScrn, int flags) if (crtc_max_Y > 8192) crtc_max_Y = 8192; } else { @@ -9739,7 +9575,7 @@ index 5cf8d51..91421b5 100644 } } xf86DrvMsg(pScrn->scrnIndex, X_INFO, "Max desktop size set to %dx%d\n", -@@ -2793,14 +2856,16 @@ Bool RADEONPreInit(ScrnInfoPtr pScrn, int flags) +@@ -2793,14 +2923,16 @@ Bool RADEONPreInit(ScrnInfoPtr pScrn, int flags) if (!RADEONPreInitAccel(pScrn)) goto fail; @@ -9759,7 +9595,7 @@ index 5cf8d51..91421b5 100644 if (pScrn->modes == NULL) { xf86DrvMsg(pScrn->scrnIndex, X_ERROR, "No modes.\n"); goto fail; -@@ -2858,7 +2923,7 @@ static void RADEONLoadPalette(ScrnInfoPtr pScrn, int numColors, +@@ -2858,7 +2990,7 @@ static void RADEONLoadPalette(ScrnInfoPtr pScrn, int numColors, xf86CrtcConfigPtr xf86_config = XF86_CRTC_CONFIG_PTR(pScrn); int i; int index, j; @@ -9768,7 +9604,7 @@ index 5cf8d51..91421b5 100644 int c; #ifdef XF86DRI -@@ -3001,7 +3066,8 @@ RADEONInitBIOSRegisters(ScrnInfoPtr pScrn) +@@ -3001,7 +3133,8 @@ RADEONInitBIOSRegisters(ScrnInfoPtr pScrn) /* let the bios control the backlight */ save->bios_2_scratch &= ~ATOM_S2_VRI_BRIGHT_ENABLE; /* tell the bios not to handle mode switching */ @@ -9778,7 +9614,7 @@ index 5cf8d51..91421b5 100644 if (info->ChipFamily >= CHIP_FAMILY_R600) { OUTREG(R600_BIOS_2_SCRATCH, save->bios_2_scratch); -@@ -3014,7 +3080,8 @@ RADEONInitBIOSRegisters(ScrnInfoPtr pScrn) +@@ -3014,7 +3147,8 @@ RADEONInitBIOSRegisters(ScrnInfoPtr pScrn) /* let the bios control the backlight */ save->bios_0_scratch &= ~RADEON_DRIVER_BRIGHTNESS_EN; /* tell the bios not to handle mode switching */ @@ -9788,7 +9624,7 @@ index 5cf8d51..91421b5 100644 /* tell the bios a driver is loaded */ save->bios_7_scratch |= RADEON_DRV_LOADED; -@@ -3032,9 +3099,7 @@ Bool RADEONScreenInit(int scrnIndex, ScreenPtr pScreen, +@@ -3032,9 +3166,7 @@ Bool RADEONScreenInit(int scrnIndex, ScreenPtr pScreen, { ScrnInfoPtr pScrn = xf86Screens[pScreen->myNum]; RADEONInfoPtr info = RADEONPTR(pScrn); @@ -9798,7 +9634,7 @@ index 5cf8d51..91421b5 100644 #ifdef RENDER int subPixelOrder = SubPixelUnknown; char* s; -@@ -3080,11 +3145,16 @@ Bool RADEONScreenInit(int scrnIndex, ScreenPtr pScreen, +@@ -3080,11 +3212,16 @@ Bool RADEONScreenInit(int scrnIndex, ScreenPtr pScreen, RADEONBlank(pScrn); if (info->IsMobility && !IS_AVIVO_VARIANT) { @@ -9818,7 +9654,7 @@ index 5cf8d51..91421b5 100644 } if (IS_R300_VARIANT || IS_RV100_VARIANT) -@@ -3139,12 +3209,14 @@ Bool RADEONScreenInit(int scrnIndex, ScreenPtr pScreen, +@@ -3139,12 +3276,14 @@ Bool RADEONScreenInit(int scrnIndex, ScreenPtr pScreen, RADEONInitMemoryMap(pScrn); /* empty the surfaces */ @@ -9839,7 +9675,7 @@ index 5cf8d51..91421b5 100644 } #ifdef XF86DRI -@@ -3164,9 +3236,11 @@ Bool RADEONScreenInit(int scrnIndex, ScreenPtr pScreen, +@@ -3164,9 +3303,11 @@ Bool RADEONScreenInit(int scrnIndex, ScreenPtr pScreen, #endif /* Initial setup of surfaces */ @@ -9854,7 +9690,7 @@ index 5cf8d51..91421b5 100644 /* Memory manager setup */ -@@ -3340,28 +3414,8 @@ Bool RADEONScreenInit(int scrnIndex, ScreenPtr pScreen, +@@ -3340,28 +3481,8 @@ Bool RADEONScreenInit(int scrnIndex, ScreenPtr pScreen, /* xf86CrtcRotate() accesses pScrn->pScreen */ pScrn->pScreen = pScreen; @@ -9883,7 +9719,7 @@ index 5cf8d51..91421b5 100644 RADEONSaveScreen(pScreen, SCREEN_SAVER_ON); -@@ -3417,10 +3471,12 @@ Bool RADEONScreenInit(int scrnIndex, ScreenPtr pScreen, +@@ -3417,10 +3538,12 @@ Bool RADEONScreenInit(int scrnIndex, ScreenPtr pScreen, #endif /* Make sure surfaces are allright since DRI setup may have changed them */ @@ -9899,7 +9735,7 @@ index 5cf8d51..91421b5 100644 /* Enable aceleration */ -@@ -3544,7 +3600,7 @@ void RADEONRestoreMemMapRegisters(ScrnInfoPtr pScrn, +@@ -3544,7 +3667,7 @@ void RADEONRestoreMemMapRegisters(ScrnInfoPtr pScrn, RADEONEntPtr pRADEONEnt = RADEONEntPriv(pScrn); unsigned char *RADEONMMIO = info->MMIO; int timeout; @@ -9908,7 +9744,7 @@ index 5cf8d51..91421b5 100644 radeon_read_mc_fb_agp_location(pScrn, LOC_FB | LOC_AGP, &mc_fb_loc, &mc_agp_loc, &mc_agp_loc_hi); -@@ -3564,7 +3620,7 @@ void RADEONRestoreMemMapRegisters(ScrnInfoPtr pScrn, +@@ -3564,7 +3687,7 @@ void RADEONRestoreMemMapRegisters(ScrnInfoPtr pScrn, if (mc_fb_loc != restore->mc_fb_location || mc_agp_loc != restore->mc_agp_location) { @@ -9917,7 +9753,7 @@ index 5cf8d51..91421b5 100644 RADEONWaitForIdleMMIO(pScrn); -@@ -3620,8 +3676,8 @@ void RADEONRestoreMemMapRegisters(ScrnInfoPtr pScrn, +@@ -3620,8 +3743,8 @@ void RADEONRestoreMemMapRegisters(ScrnInfoPtr pScrn, */ if (mc_fb_loc != restore->mc_fb_location || mc_agp_loc != restore->mc_agp_location) { @@ -9928,7 +9764,7 @@ index 5cf8d51..91421b5 100644 xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG, " Map Changed ! Applying ...\n"); -@@ -3759,16 +3815,16 @@ void RADEONRestoreMemMapRegisters(ScrnInfoPtr pScrn, +@@ -3759,16 +3882,16 @@ void RADEONRestoreMemMapRegisters(ScrnInfoPtr pScrn, static void RADEONAdjustMemMapRegisters(ScrnInfoPtr pScrn, RADEONSavePtr save) { RADEONInfoPtr info = RADEONPTR(pScrn); @@ -9950,7 +9786,7 @@ index 5cf8d51..91421b5 100644 changed = 1; if (changed) { -@@ -3997,7 +4053,8 @@ void RADEONChangeSurfaces(ScrnInfoPtr pScrn) +@@ -3997,7 +4120,8 @@ void RADEONChangeSurfaces(ScrnInfoPtr pScrn) } /* Update surface images */ @@ -9960,7 +9796,7 @@ index 5cf8d51..91421b5 100644 } /* Read memory map */ -@@ -4039,12 +4096,13 @@ static void RADEONSavePalette(ScrnInfoPtr pScrn, RADEONSavePtr save) +@@ -4039,12 +4163,13 @@ static void RADEONSavePalette(ScrnInfoPtr pScrn, RADEONSavePtr save) } #endif @@ -9975,7 +9811,7 @@ index 5cf8d51..91421b5 100644 // state->vga_memory_base = INREG(AVIVO_VGA_MEMORY_BASE); // state->vga_fb_start = INREG(AVIVO_VGA_FB_START); -@@ -4110,8 +4168,6 @@ avivo_save(ScrnInfoPtr pScrn, RADEONSavePtr save) +@@ -4110,8 +4235,6 @@ avivo_save(ScrnInfoPtr pScrn, RADEONSavePtr save) state->grph1.viewport_start = INREG(AVIVO_D1MODE_VIEWPORT_START); state->grph1.viewport_size = INREG(AVIVO_D1MODE_VIEWPORT_SIZE); @@ -9984,7 +9820,7 @@ index 5cf8d51..91421b5 100644 state->crtc2.pll_source = INREG(AVIVO_PCLK_CRTC2_CNTL); -@@ -4151,57 +4207,208 @@ avivo_save(ScrnInfoPtr pScrn, RADEONSavePtr save) +@@ -4151,57 +4274,208 @@ avivo_save(ScrnInfoPtr pScrn, RADEONSavePtr save) state->grph2.viewport_start = INREG(AVIVO_D2MODE_VIEWPORT_START); state->grph2.viewport_size = INREG(AVIVO_D2MODE_VIEWPORT_SIZE); @@ -10194,12 +10030,12 @@ index 5cf8d51..91421b5 100644 + state->d1scl[j] = INREG(i); + state->d2scl[j] = INREG(i + 0x800); + j++; -+ } + } + for (i = 0x6600; i <= 0x662c; i += 4) { + state->d1scl[j] = INREG(i); + state->d2scl[j] = INREG(i + 0x800); + j++; - } ++ } + j = 0; + for (i = 0x66e8; i <= 0x66fc; i += 4) { + state->dxscl[j] = INREG(i); @@ -10228,7 +10064,7 @@ index 5cf8d51..91421b5 100644 // OUTMC(pScrn, AVIVO_MC_MEMORY_MAP, state->mc_memory_map); // OUTREG(AVIVO_VGA_MEMORY_BASE, state->vga_memory_base); -@@ -4266,8 +4473,6 @@ avivo_restore(ScrnInfoPtr pScrn, RADEONSavePtr restore) +@@ -4266,8 +4540,6 @@ avivo_restore(ScrnInfoPtr pScrn, RADEONSavePtr restore) OUTREG(AVIVO_D1MODE_VIEWPORT_START, state->grph1.viewport_start); OUTREG(AVIVO_D1MODE_VIEWPORT_SIZE, state->grph1.viewport_size); @@ -10237,7 +10073,7 @@ index 5cf8d51..91421b5 100644 OUTREG(AVIVO_PCLK_CRTC2_CNTL, state->crtc2.pll_source); -@@ -4306,49 +4511,200 @@ avivo_restore(ScrnInfoPtr pScrn, RADEONSavePtr restore) +@@ -4306,49 +4578,200 @@ avivo_restore(ScrnInfoPtr pScrn, RADEONSavePtr restore) OUTREG(AVIVO_D2MODE_VIEWPORT_START, state->grph2.viewport_start); OUTREG(AVIVO_D2MODE_VIEWPORT_SIZE, state->grph2.viewport_size); @@ -10440,8 +10276,8 @@ index 5cf8d51..91421b5 100644 + j++; + } + } -+ } -+ + } + + /* scalers */ + j = 0; + for (i = 0x6578; i <= 0x65e4; i += 4) { @@ -10458,10 +10294,10 @@ index 5cf8d51..91421b5 100644 + for (i = 0x66e8; i <= 0x66fc; i += 4) { + OUTREG(i, state->dxscl[j]); + j++; - } ++ } + OUTREG(0x6e30, state->dxscl[6]); + OUTREG(0x6e34, state->dxscl[7]); - ++ OUTREG(AVIVO_D1VGA_CONTROL, state->vga1_cntl); OUTREG(AVIVO_D2VGA_CONTROL, state->vga2_cntl); } @@ -10473,7 +10309,7 @@ index 5cf8d51..91421b5 100644 RADEONInfoPtr info = RADEONPTR(pScrn); unsigned char *RADEONMMIO = info->MMIO; struct avivo_state *state = &restore->avivo; -@@ -4434,6 +4790,9 @@ static void RADEONSave(ScrnInfoPtr pScrn) +@@ -4434,6 +4857,9 @@ static void RADEONSave(ScrnInfoPtr pScrn) * setup in the card at all !! */ vgaHWSave(pScrn, &hwp->SavedReg, VGA_SR_MODE); /* Save mode only */ @@ -10483,7 +10319,7 @@ index 5cf8d51..91421b5 100644 # else /* Save mode * & fonts & cmap */ vgaHWSave(pScrn, &hwp->SavedReg, VGA_SR_ALL); -@@ -4466,12 +4825,13 @@ static void RADEONSave(ScrnInfoPtr pScrn) +@@ -4466,12 +4892,13 @@ static void RADEONSave(ScrnInfoPtr pScrn) } RADEONSaveBIOSRegisters(pScrn, save); @@ -10499,7 +10335,7 @@ index 5cf8d51..91421b5 100644 { RADEONInfoPtr info = RADEONPTR(pScrn); RADEONEntPtr pRADEONEnt = RADEONEntPriv(pScrn); -@@ -4522,9 +4882,9 @@ void RADEONRestore(ScrnInfoPtr pScrn) +@@ -4522,9 +4949,9 @@ void RADEONRestore(ScrnInfoPtr pScrn) } RADEONRestoreBIOSRegisters(pScrn, restore); @@ -10510,7 +10346,7 @@ index 5cf8d51..91421b5 100644 #if 1 /* Temp fix to "solve" VT switch problems. When switching VTs on * some systems, the console can either hang or the fonts can be -@@ -4534,6 +4894,9 @@ void RADEONRestore(ScrnInfoPtr pScrn) +@@ -4534,6 +4961,9 @@ void RADEONRestore(ScrnInfoPtr pScrn) usleep(100000); #endif @@ -10520,7 +10356,7 @@ index 5cf8d51..91421b5 100644 /* need to make sure we don't enable a crtc by accident or we may get a hang */ if (pRADEONEnt->HasCRTC2 && !info->IsSecondary) { if (info->crtc2_on && xf86_config->num_crtc > 1) { -@@ -4555,7 +4918,9 @@ void RADEONRestore(ScrnInfoPtr pScrn) +@@ -4555,7 +4985,9 @@ void RADEONRestore(ScrnInfoPtr pScrn) * write VGA fonts, will find a better solution in the future */ vgaHWRestore(pScrn, &hwp->SavedReg, VGA_SR_MODE ); @@ -10531,7 +10367,7 @@ index 5cf8d51..91421b5 100644 vgaHWRestore(pScrn, &hwp->SavedReg, VGA_SR_ALL ); # endif vgaHWLock(hwp); -@@ -4567,7 +4932,9 @@ void RADEONRestore(ScrnInfoPtr pScrn) +@@ -4567,7 +4999,9 @@ void RADEONRestore(ScrnInfoPtr pScrn) */ if (IS_AVIVO_VARIANT) avivo_restore_vga_regs(pScrn, restore); @@ -10542,13 +10378,14 @@ index 5cf8d51..91421b5 100644 #if 0 RADEONWaitForVerticalSync(pScrn); -@@ -4885,63 +5252,68 @@ Bool RADEONEnterVT(int scrnIndex, int flags) +@@ -4885,63 +5319,73 @@ Bool RADEONEnterVT(int scrnIndex, int flags) ScrnInfoPtr pScrn = xf86Screens[scrnIndex]; RADEONInfoPtr info = RADEONPTR(pScrn); unsigned char *RADEONMMIO = info->MMIO; - xf86CrtcConfigPtr xf86_config = XF86_CRTC_CONFIG_PTR(pScrn); -- int i; + uint32_t mem_size; ++ xf86CrtcConfigPtr config = XF86_CRTC_CONFIG_PTR(pScrn); + int i; xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG, "RADEONEnterVT\n"); @@ -10609,7 +10446,7 @@ index 5cf8d51..91421b5 100644 if (IS_R300_VARIANT || IS_RV100_VARIANT) RADEONForceSomeClocks(pScrn); - pScrn->vtSema = TRUE; +- pScrn->vtSema = TRUE; - for (i = 0; i < xf86_config->num_crtc; i++) { - xf86CrtcPtr crtc = xf86_config->crtc[i]; - /* Mark that we'll need to re-set the mode for sure */ @@ -10620,10 +10457,13 @@ index 5cf8d51..91421b5 100644 - crtc->desiredX = 0; - crtc->desiredY = 0; - } -- ++ for (i = 0; i < config->num_crtc; i++) ++ radeon_crtc_modeset_ioctl(config->crtc[i], TRUE); + - if (!xf86CrtcSetMode (crtc, &crtc->desiredMode, crtc->desiredRotation, - crtc->desiredX, crtc->desiredY)) - return FALSE; ++ pScrn->vtSema = TRUE; - } + if (!xf86SetDesiredModes(pScrn)) @@ -10646,7 +10486,7 @@ index 5cf8d51..91421b5 100644 } /* get the DRI back into shape after resume */ -@@ -4966,8 +5338,6 @@ Bool RADEONEnterVT(int scrnIndex, int flags) +@@ -4966,8 +5410,6 @@ Bool RADEONEnterVT(int scrnIndex, int flags) } #endif @@ -10655,18 +10495,16 @@ index 5cf8d51..91421b5 100644 return TRUE; } -@@ -4978,6 +5348,10 @@ void RADEONLeaveVT(int scrnIndex, int flags) +@@ -4978,6 +5420,8 @@ void RADEONLeaveVT(int scrnIndex, int flags) { ScrnInfoPtr pScrn = xf86Screens[scrnIndex]; RADEONInfoPtr info = RADEONPTR(pScrn); -+#ifndef HAVE_FREE_SHADOW -+ xf86CrtcConfigPtr config = XF86_CRTC_CONFIG_PTR(pScrn); -+ int o; -+#endif ++ xf86CrtcConfigPtr config = XF86_CRTC_CONFIG_PTR(pScrn); ++ int i; xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG, "RADEONLeaveVT\n"); -@@ -4988,8 +5362,9 @@ void RADEONLeaveVT(int scrnIndex, int flags) +@@ -4988,8 +5432,9 @@ void RADEONLeaveVT(int scrnIndex, int flags) DRILock(pScrn->pScreen, 0); RADEONCP_STOP(pScrn, info); @@ -10678,13 +10516,24 @@ index 5cf8d51..91421b5 100644 /* we need to backup the PCIE GART TABLE from fb memory */ memcpy(info->pciGartBackup, (info->FB + info->pciGartOffset), info->pciGartSize); } -@@ -5009,6 +5384,23 @@ void RADEONLeaveVT(int scrnIndex, int flags) +@@ -4999,7 +5444,9 @@ void RADEONLeaveVT(int scrnIndex, int flags) + RADEONSAREAPrivPtr pSAREAPriv = + (RADEONSAREAPrivPtr)DRIGetSAREAPrivate(pScrn->pScreen); + drmTextureRegionPtr list = pSAREAPriv->texList[0]; +- int age = ++pSAREAPriv->texAge[0], i = 0; ++ int age = ++pSAREAPriv->texAge[0]; ++ ++ i = 0; + + do { + list[i].age = age; +@@ -5009,8 +5456,28 @@ void RADEONLeaveVT(int scrnIndex, int flags) } #endif +#ifndef HAVE_FREE_SHADOW -+ for (o = 0; o < config->num_crtc; o++) { -+ xf86CrtcPtr crtc = config->crtc[o]; ++ for (i = 0; i < config->num_crtc; i++) { ++ xf86CrtcPtr crtc = config->crtc[i]; + + if (crtc->rotatedPixmap || crtc->rotatedData) { + crtc->funcs->shadow_destroy(crtc, crtc->rotatedPixmap, @@ -10701,8 +10550,13 @@ index 5cf8d51..91421b5 100644 + RADEONRestore(pScrn); ++ for (i = 0; i < config->num_crtc; i++) ++ radeon_crtc_modeset_ioctl(config->crtc[i], FALSE); ++ xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG, -@@ -5121,7 +5513,7 @@ void RADEONFreeScreen(int scrnIndex, int flags) + "Ok, leaving now...\n"); + } +@@ -5121,7 +5588,7 @@ void RADEONFreeScreen(int scrnIndex, int flags) static void RADEONForceSomeClocks(ScrnInfoPtr pScrn) { /* It appears from r300 and rv100 may need some clocks forced-on */ @@ -10711,7 +10565,7 @@ index 5cf8d51..91421b5 100644 tmp = INPLL(pScrn, RADEON_SCLK_CNTL); tmp |= RADEON_SCLK_FORCE_CP | RADEON_SCLK_FORCE_VIP; -@@ -5133,7 +5525,7 @@ static void RADEONSetDynamicClock(ScrnInfoPtr pScrn, int mode) +@@ -5133,7 +5600,7 @@ static void RADEONSetDynamicClock(ScrnInfoPtr pScrn, int mode) RADEONInfoPtr info = RADEONPTR(pScrn); RADEONEntPtr pRADEONEnt = RADEONEntPriv(pScrn); unsigned char *RADEONMMIO = info->MMIO; @@ -10721,7 +10575,7 @@ index 5cf8d51..91421b5 100644 case 0: /* Turn everything OFF (ForceON to everything)*/ if ( !pRADEONEnt->HasCRTC2 ) { diff --git a/src/radeon_exa.c b/src/radeon_exa.c -index 4da4841..0193a28 100644 +index 4da4841..f461f3c 100644 --- a/src/radeon_exa.c +++ b/src/radeon_exa.c @@ -99,17 +99,24 @@ static __inline__ int @@ -10821,7 +10675,7 @@ index 4da4841..0193a28 100644 BEGIN_ACCEL(1); \ switch (info->engineMode) { \ case EXA_ENGINEMODE_UNKNOWN: \ -@@ -310,7 +317,7 @@ do { \ +@@ -310,13 +317,13 @@ do { \ #define RADEON_SWITCH_TO_3D() \ do { \ @@ -10830,6 +10684,13 @@ index 4da4841..0193a28 100644 BEGIN_ACCEL(1); \ switch (info->engineMode) { \ case EXA_ENGINEMODE_UNKNOWN: \ + wait_until |= RADEON_WAIT_HOST_IDLECLEAN | RADEON_WAIT_3D_IDLECLEAN; \ + case EXA_ENGINEMODE_2D: \ +- wait_until |= RADEON_WAIT_2D_IDLECLEAN; \ ++ wait_until |= RADEON_WAIT_2D_IDLECLEAN | RADEON_WAIT_DMA_GUI_IDLE; \ + case EXA_ENGINEMODE_3D: \ + break; \ + } \ @@ -395,7 +402,7 @@ Bool RADEONSetupMemEXA (ScreenPtr pScreen) else screen_size = pScrn->virtualY * byteStride; @@ -10840,7 +10701,7 @@ index 4da4841..0193a28 100644 info->exa->offScreenBase = screen_size; diff --git a/src/radeon_exa_funcs.c b/src/radeon_exa_funcs.c -index 10221c0..13a7de5 100644 +index 10221c0..56de23e 100644 --- a/src/radeon_exa_funcs.c +++ b/src/radeon_exa_funcs.c @@ -88,7 +88,7 @@ static Bool @@ -10852,7 +10713,28 @@ index 10221c0..13a7de5 100644 ACCEL_PREAMBLE(); TRACE; -@@ -143,8 +143,8 @@ FUNC_NAME(RADEONDoneSolid)(PixmapPtr pPix) +@@ -124,7 +124,6 @@ FUNC_NAME(RADEONPrepareSolid)(PixmapPtr pPix, int alu, Pixel pm, Pixel fg) + static void + FUNC_NAME(RADEONSolid)(PixmapPtr pPix, int x1, int y1, int x2, int y2) + { +- + RINFO_FROM_SCREEN(pPix->drawable.pScreen); + ACCEL_PREAMBLE(); + +@@ -139,12 +138,21 @@ FUNC_NAME(RADEONSolid)(PixmapPtr pPix, int x1, int y1, int x2, int y2) + static void + FUNC_NAME(RADEONDoneSolid)(PixmapPtr pPix) + { ++ RINFO_FROM_SCREEN(pPix->drawable.pScreen); ++ ACCEL_PREAMBLE(); ++ + TRACE; ++ ++ BEGIN_ACCEL(2); ++ OUT_ACCEL_REG(RADEON_DSTCACHE_CTLSTAT, RADEON_RB2D_DC_FLUSH_ALL); ++ OUT_ACCEL_REG(RADEON_WAIT_UNTIL, ++ RADEON_WAIT_2D_IDLECLEAN | RADEON_WAIT_DMA_GUI_IDLE); ++ FINISH_ACCEL(); } void @@ -10863,7 +10745,7 @@ index 10221c0..13a7de5 100644 Pixel planemask) { RADEONInfoPtr info = RADEONPTR(pScrn); -@@ -178,7 +178,7 @@ FUNC_NAME(RADEONPrepareCopy)(PixmapPtr pSrc, PixmapPtr pDst, +@@ -178,7 +186,7 @@ FUNC_NAME(RADEONPrepareCopy)(PixmapPtr pSrc, PixmapPtr pDst, Pixel planemask) { RINFO_FROM_SCREEN(pDst->drawable.pScreen); @@ -10872,7 +10754,32 @@ index 10221c0..13a7de5 100644 TRACE; -@@ -241,12 +241,12 @@ FUNC_NAME(RADEONUploadToScreen)(PixmapPtr pDst, int x, int y, int w, int h, +@@ -206,7 +214,6 @@ FUNC_NAME(RADEONCopy)(PixmapPtr pDst, + int dstX, int dstY, + int w, int h) + { +- + RINFO_FROM_SCREEN(pDst->drawable.pScreen); + ACCEL_PREAMBLE(); + +@@ -233,7 +240,16 @@ FUNC_NAME(RADEONCopy)(PixmapPtr pDst, + static void + FUNC_NAME(RADEONDoneCopy)(PixmapPtr pDst) + { ++ RINFO_FROM_SCREEN(pDst->drawable.pScreen); ++ ACCEL_PREAMBLE(); ++ + TRACE; ++ ++ BEGIN_ACCEL(2); ++ OUT_ACCEL_REG(RADEON_DSTCACHE_CTLSTAT, RADEON_RB2D_DC_FLUSH_ALL); ++ OUT_ACCEL_REG(RADEON_WAIT_UNTIL, ++ RADEON_WAIT_2D_IDLECLEAN | RADEON_WAIT_DMA_GUI_IDLE); ++ FINISH_ACCEL(); + } + + static Bool +@@ -241,12 +257,12 @@ FUNC_NAME(RADEONUploadToScreen)(PixmapPtr pDst, int x, int y, int w, int h, char *src, int src_pitch) { RINFO_FROM_SCREEN(pDst->drawable.pScreen); @@ -10887,7 +10794,7 @@ index 10221c0..13a7de5 100644 #endif #if X_BYTE_ORDER == X_BIG_ENDIAN unsigned char *RADEONMMIO = info->MMIO; -@@ -263,7 +263,7 @@ FUNC_NAME(RADEONUploadToScreen)(PixmapPtr pDst, int x, int y, int w, int h, +@@ -263,7 +279,7 @@ FUNC_NAME(RADEONUploadToScreen)(PixmapPtr pDst, int x, int y, int w, int h, #ifdef ACCEL_CP if (info->directRenderingEnabled && RADEONGetPixmapOffsetPitch(pDst, &dst_pitch_off)) { @@ -10896,7 +10803,7 @@ index 10221c0..13a7de5 100644 int cpp = bpp / 8; ACCEL_PREAMBLE(); -@@ -271,7 +271,7 @@ FUNC_NAME(RADEONUploadToScreen)(PixmapPtr pDst, int x, int y, int w, int h, +@@ -271,7 +287,7 @@ FUNC_NAME(RADEONUploadToScreen)(PixmapPtr pDst, int x, int y, int w, int h, while ((buf = RADEONHostDataBlit(pScrn, cpp, w, dst_pitch_off, &buf_pitch, x, &y, (unsigned int*)&h, &hpass)) != 0) { @@ -10905,7 +10812,7 @@ index 10221c0..13a7de5 100644 hpass, buf_pitch, src_pitch); src += hpass * src_pitch; } -@@ -319,8 +319,8 @@ FUNC_NAME(RADEONUploadToScreen)(PixmapPtr pDst, int x, int y, int w, int h, +@@ -319,8 +335,8 @@ FUNC_NAME(RADEONUploadToScreen)(PixmapPtr pDst, int x, int y, int w, int h, #ifdef ACCEL_CP /* Emit blit with arbitrary source and destination offsets and pitches */ static void @@ -10916,7 +10823,19 @@ index 10221c0..13a7de5 100644 int w, int h) { RADEONInfoPtr info = RADEONPTR(pScrn); -@@ -357,11 +357,11 @@ FUNC_NAME(RADEONDownloadFromScreen)(PixmapPtr pSrc, int x, int y, int w, int h, +@@ -343,6 +359,11 @@ RADEONBlitChunk(ScrnInfoPtr pScrn, CARD32 datatype, CARD32 src_pitch_offset, + OUT_ACCEL_REG(RADEON_DST_Y_X, (dstY << 16) | dstX); + OUT_ACCEL_REG(RADEON_DST_HEIGHT_WIDTH, (h << 16) | w); + FINISH_ACCEL(); ++ BEGIN_ACCEL(2); ++ OUT_ACCEL_REG(RADEON_DSTCACHE_CTLSTAT, RADEON_RB2D_DC_FLUSH_ALL); ++ OUT_ACCEL_REG(RADEON_WAIT_UNTIL, ++ RADEON_WAIT_2D_IDLECLEAN | RADEON_WAIT_DMA_GUI_IDLE); ++ FINISH_ACCEL(); + } + #endif + +@@ -357,11 +378,11 @@ FUNC_NAME(RADEONDownloadFromScreen)(PixmapPtr pSrc, int x, int y, int w, int h, ~(RADEON_NONSURF_AP0_SWP_32BPP | RADEON_NONSURF_AP1_SWP_32BPP | RADEON_NONSURF_AP0_SWP_16BPP | RADEON_NONSURF_AP1_SWP_16BPP); #endif @@ -10930,7 +10849,7 @@ index 10221c0..13a7de5 100644 drmBufPtr scratch; #endif -@@ -379,7 +379,7 @@ FUNC_NAME(RADEONDownloadFromScreen)(PixmapPtr pSrc, int x, int y, int w, int h, +@@ -379,7 +400,7 @@ FUNC_NAME(RADEONDownloadFromScreen)(PixmapPtr pSrc, int x, int y, int w, int h, { int swap = RADEON_HOST_DATA_SWAP_NONE, wpass = w * bpp / 8; int hpass = min(h, scratch->total/2 / scratch_pitch); @@ -10939,7 +10858,7 @@ index 10221c0..13a7de5 100644 | (info->gartLocation + info->bufStart + scratch->idx * scratch->total) >> 10; drmRadeonIndirect indirect; -@@ -406,7 +406,7 @@ FUNC_NAME(RADEONDownloadFromScreen)(PixmapPtr pSrc, int x, int y, int w, int h, +@@ -406,7 +427,7 @@ FUNC_NAME(RADEONDownloadFromScreen)(PixmapPtr pSrc, int x, int y, int w, int h, while (h) { int oldhpass = hpass, i = 0; @@ -10948,7 +10867,7 @@ index 10221c0..13a7de5 100644 y += oldhpass; h -= oldhpass; -@@ -439,10 +439,10 @@ FUNC_NAME(RADEONDownloadFromScreen)(PixmapPtr pSrc, int x, int y, int w, int h, +@@ -439,10 +460,10 @@ FUNC_NAME(RADEONDownloadFromScreen)(PixmapPtr pSrc, int x, int y, int w, int h, /* Copy out data from previous blit */ if (wpass == scratch_pitch && wpass == dst_pitch) { @@ -10961,7 +10880,7 @@ index 10221c0..13a7de5 100644 src += scratch_pitch; dst += dst_pitch; } -@@ -533,21 +533,27 @@ Bool FUNC_NAME(RADEONDrawInit)(ScreenPtr pScreen) +@@ -533,21 +554,27 @@ Bool FUNC_NAME(RADEONDrawInit)(ScreenPtr pScreen) #ifdef RENDER if (info->RenderAccel) { @@ -10998,7 +10917,7 @@ index 10221c0..13a7de5 100644 (info->ChipFamily == CHIP_FAMILY_R200)) { xf86DrvMsg(pScrn->scrnIndex, X_INFO, "Render acceleration " "enabled for R200 type cards.\n"); -@@ -555,7 +561,7 @@ Bool FUNC_NAME(RADEONDrawInit)(ScreenPtr pScreen) +@@ -555,7 +582,7 @@ Bool FUNC_NAME(RADEONDrawInit)(ScreenPtr pScreen) info->exa->PrepareComposite = FUNC_NAME(R200PrepareComposite); info->exa->Composite = FUNC_NAME(RadeonComposite); @@ -11007,7 +10926,7 @@ index 10221c0..13a7de5 100644 } else { xf86DrvMsg(pScrn->scrnIndex, X_INFO, "Render acceleration " "enabled for R100 type cards.\n"); -@@ -563,7 +569,7 @@ Bool FUNC_NAME(RADEONDrawInit)(ScreenPtr pScreen) +@@ -563,7 +590,7 @@ Bool FUNC_NAME(RADEONDrawInit)(ScreenPtr pScreen) info->exa->PrepareComposite = FUNC_NAME(R100PrepareComposite); info->exa->Composite = FUNC_NAME(RadeonComposite); @@ -11016,7 +10935,7 @@ index 10221c0..13a7de5 100644 } } #endif -@@ -572,11 +578,11 @@ Bool FUNC_NAME(RADEONDrawInit)(ScreenPtr pScreen) +@@ -572,11 +599,11 @@ Bool FUNC_NAME(RADEONDrawInit)(ScreenPtr pScreen) xf86DrvMsg(pScrn->scrnIndex, X_INFO, "Setting EXA maxPitchBytes\n"); info->exa->maxPitchBytes = 16320; @@ -11032,7 +10951,7 @@ index 10221c0..13a7de5 100644 RADEONEngineInit(pScrn); diff --git a/src/radeon_exa_render.c b/src/radeon_exa_render.c -index 9bbccb5..2319e3b 100644 +index 9bbccb5..8a1849c 100644 --- a/src/radeon_exa_render.c +++ b/src/radeon_exa_render.c @@ -26,6 +26,7 @@ @@ -11534,7 +11453,7 @@ index 9bbccb5..2319e3b 100644 + RADEON_FALLBACK(("Mask w/h too large (%d,%d).\n", + pMaskPixmap->drawable.width, + pMaskPixmap->drawable.height)); - } ++ } + + if (pMaskPicture->componentAlpha) { + /* Check if it's component alpha that relies on a source alpha and @@ -11547,7 +11466,7 @@ index 9bbccb5..2319e3b 100644 + RADEON_FALLBACK(("Component alpha not supported with source " + "alpha and source value blending.\n")); + } -+ } + } + + if (!R200CheckCompositeTexture(pMaskPicture, 1)) + return FALSE; @@ -12931,7 +12850,7 @@ index 9bbccb5..2319e3b 100644 #ifdef ACCEL_CP ADVANCE_RING(); #else -@@ -1426,14 +2045,90 @@ static void FUNC_NAME(RadeonComposite)(PixmapPtr pDst, +@@ -1426,14 +2045,85 @@ static void FUNC_NAME(RadeonComposite)(PixmapPtr pDst, LEAVE_DRAW(0); } #undef VTX_OUT @@ -12944,7 +12863,7 @@ index 9bbccb5..2319e3b 100644 + int maskX, int maskY, + int dstX, int dstY, + int width, int height) -+{ + { + int tileSrcY, tileMaskY, tileDstY; + int remainingHeight; + @@ -13000,24 +12919,19 @@ index 9bbccb5..2319e3b 100644 +} + +static void FUNC_NAME(RadeonDoneComposite)(PixmapPtr pDst) - { ++{ + RINFO_FROM_SCREEN(pDst->drawable.pScreen); + ACCEL_PREAMBLE(); + ENTER_DRAW(0); + -+ if (IS_R500_3D || ((info->ChipFamily == CHIP_FAMILY_RS400) || -+ (info->ChipFamily == CHIP_FAMILY_RS480) || -+ (info->ChipFamily == CHIP_FAMILY_RS600) || -+ (info->ChipFamily == CHIP_FAMILY_RS690) || -+ (info->ChipFamily == CHIP_FAMILY_RS740))) { -+ /* r500 shows corruption on small things like glyphs without a 3D idle -+ * IGP shows more substantial corruption -+ */ ++ if (IS_R300_3D | IS_R500_3D) { ++ BEGIN_ACCEL(2); ++ OUT_ACCEL_REG(R300_RB3D_DSTCACHE_CTLSTAT, R300_RB3D_DC_FLUSH_ALL); ++ } else + BEGIN_ACCEL(1); -+ OUT_ACCEL_REG(RADEON_WAIT_UNTIL, RADEON_WAIT_3D_IDLECLEAN); -+ FINISH_ACCEL(); -+ } ++ OUT_ACCEL_REG(RADEON_WAIT_UNTIL, RADEON_WAIT_3D_IDLECLEAN); ++ FINISH_ACCEL(); + LEAVE_DRAW(0); } @@ -13026,10 +12940,43 @@ index 9bbccb5..2319e3b 100644 #undef ONLY_ONCE #undef FUNC_NAME diff --git a/src/radeon_macros.h b/src/radeon_macros.h -index 7f532a8..f19bc3e 100644 +index 7f532a8..afe442e 100644 --- a/src/radeon_macros.h +++ b/src/radeon_macros.h -@@ -67,12 +67,12 @@ +@@ -51,6 +51,32 @@ + + #include "compiler.h" + ++#if HAVE_BYTESWAP_H ++#include ++#elif defined(USE_SYS_ENDIAN_H) ++#include ++#else ++#define bswap_16(value) \ ++ ((((value) & 0xff) << 8) | ((value) >> 8)) ++ ++#define bswap_32(value) \ ++ (((uint32_t)bswap_16((uint16_t)((value) & 0xffff)) << 16) | \ ++ (uint32_t)bswap_16((uint16_t)((value) >> 16))) ++ ++#define bswap_64(value) \ ++ (((uint64_t)bswap_32((uint32_t)((value) & 0xffffffff)) \ ++ << 32) | \ ++ (uint64_t)bswap_32((uint32_t)((value) >> 32))) ++#endif ++ ++#if X_BYTE_ORDER == X_BIG_ENDIAN ++#define le32_to_cpu(x) bswap_32(x) ++#define le16_to_cpu(x) bswap_16(x) ++#else ++#define le32_to_cpu(x) (x) ++#define le16_to_cpu(x) (x) ++#endif ++ + #define RADEON_BIOS8(v) (info->VBIOS[v]) + #define RADEON_BIOS16(v) (info->VBIOS[v] | \ + (info->VBIOS[(v) + 1] << 8)) +@@ -67,12 +93,12 @@ #define OUTREG16(addr, val) MMIO_OUT16(RADEONMMIO, addr, val) #define OUTREG(addr, val) MMIO_OUT32(RADEONMMIO, addr, val) @@ -13044,7 +12991,7 @@ index 7f532a8..f19bc3e 100644 tmp &= (mask); \ tmp |= ((val) & ~(mask)); \ OUTREG(addr, tmp); \ -@@ -84,7 +84,7 @@ do { \ +@@ -84,7 +110,7 @@ do { \ #define OUTPLLP(pScrn, addr, val, mask) \ do { \ @@ -13053,7 +13000,7 @@ index 7f532a8..f19bc3e 100644 tmp_ &= (mask); \ tmp_ |= ((val) & ~(mask)); \ OUTPLL(pScrn, addr, tmp_); \ -@@ -108,7 +108,7 @@ do { \ +@@ -108,7 +134,7 @@ do { \ } \ } while (0) @@ -13062,7 +13009,7 @@ index 7f532a8..f19bc3e 100644 do { \ OUTREG(RADEON_PALETTE_DATA, (v & 0x00ffffff)); \ } while (0) -@@ -148,7 +148,7 @@ do { \ +@@ -148,7 +174,7 @@ do { \ } else { \ if (!idx) { \ OUTREG(RADEON_DAC_CNTL2, INREG(RADEON_DAC_CNTL2) & \ @@ -13155,11 +13102,30 @@ index 0524fa9..bb45407 100644 i2c_cntl_1 = (pPriv->radeon_i2c_timing << 24) | RADEON_I2C_EN | RADEON_I2C_SEL | nRead | 0x010; diff --git a/src/radeon_output.c b/src/radeon_output.c -index 62cc5d4..72addef 100644 +index 62cc5d4..7b89d66 100644 --- a/src/radeon_output.c +++ b/src/radeon_output.c -@@ -145,7 +145,7 @@ static const RADEONTMDSPll default_tmds_pll[CHIP_FAMILY_LAST][4] = +@@ -74,12 +74,13 @@ const RADEONMonitorType MonTypeID[10] = { + MT_DP + }; + +-const char *TMDSTypeName[5] = { ++const char *TMDSTypeName[6] = { + "None", + "Internal", + "External", + "LVTMA", +- "DDIA" ++ "DDIA", ++ "UNIPHY" + }; + + const char *DACTypeName[4] = { +@@ -143,9 +144,10 @@ static const RADEONTMDSPll default_tmds_pll[CHIP_FAMILY_LAST][4] = + {{0xffffffff, 0xb01cb}, {0, 0}, {0, 0}, {0, 0}}, /*CHIP_FAMILY_R420*/ + {{0xffffffff, 0xb01cb}, {0, 0}, {0, 0}, {0, 0}}, /*CHIP_FAMILY_RV410*/ /* FIXME: just values from r420 used... */ {{15000, 0xb0155}, {0xffffffff, 0xb01cb}, {0, 0}, {0, 0}}, /*CHIP_FAMILY_RS400*/ /* FIXME: just values from rv380 used... */ ++ {{15000, 0xb0155}, {0xffffffff, 0xb01cb}, {0, 0}, {0, 0}}, /*CHIP_FAMILY_RS480*/ /* FIXME: just values from rv380 used... */ }; -static const CARD32 default_tvdac_adj [CHIP_FAMILY_LAST] = @@ -13167,7 +13133,11 @@ index 62cc5d4..72addef 100644 { 0x00000000, /* unknown */ 0x00000000, /* legacy */ -@@ -168,7 +168,6 @@ static const CARD32 default_tvdac_adj [CHIP_FAMILY_LAST] = +@@ -165,10 +167,10 @@ static const CARD32 default_tvdac_adj [CHIP_FAMILY_LAST] = + 0x01080000, /* r420 */ + 0x01080000, /* rv410 */ /* FIXME: just values from r420 used... */ + 0x00780000, /* rs400 */ /* FIXME: just values from rv380 used... */ ++ 0x00780000, /* rs480 */ /* FIXME: just values from rv380 used... */ }; @@ -13175,7 +13145,7 @@ index 62cc5d4..72addef 100644 static void RADEONUpdatePanelSize(xf86OutputPtr output); static void RADEONGetTMDSInfoFromTable(xf86OutputPtr output); #define AVIVO_I2C_DISABLE 0 -@@ -178,15 +177,9 @@ static Bool AVIVOI2CDoLock(xf86OutputPtr output, int lock_state); +@@ -178,15 +180,9 @@ static Bool AVIVOI2CDoLock(xf86OutputPtr output, int lock_state); extern void atombios_output_mode_set(xf86OutputPtr output, DisplayModePtr mode, DisplayModePtr adjusted_mode); @@ -13191,15 +13161,13 @@ index 62cc5d4..72addef 100644 static void radeon_bios_output_dpms(xf86OutputPtr output, int mode); static void -@@ -217,122 +210,99 @@ void RADEONPrintPortMap(ScrnInfoPtr pScrn) +@@ -217,122 +213,99 @@ void RADEONPrintPortMap(ScrnInfoPtr pScrn) } -static RADEONMonitorType -avivo_display_ddc_connected(ScrnInfoPtr pScrn, xf86OutputPtr output) -+static xf86MonPtr -+radeon_do_ddc(xf86OutputPtr output) - { +-{ - RADEONInfoPtr info = RADEONPTR(pScrn); - RADEONMonitorType MonType = MT_NONE; - xf86MonPtr MonInfo = NULL; @@ -13233,7 +13201,9 @@ index 62cc5d4..72addef 100644 - -static RADEONMonitorType -RADEONDisplayDDCConnected(ScrnInfoPtr pScrn, xf86OutputPtr output) --{ ++static xf86MonPtr ++radeon_do_ddc(xf86OutputPtr output) + { - RADEONInfoPtr info = RADEONPTR(pScrn); + RADEONInfoPtr info = RADEONPTR(output->scrn); unsigned char *RADEONMMIO = info->MMIO; @@ -13357,21 +13327,22 @@ index 62cc5d4..72addef 100644 - OUTREG(DDCReg, INREG(DDCReg) | RADEON_GPIO_EN_0); - usleep(15000); - if (MonInfo) break; -+ OUTREG(DDCReg, INREG(DDCReg) & -+ ~(RADEON_GPIO_EN_0 | RADEON_GPIO_EN_1)); - } +- } - } else if (radeon_output->pI2CBus && info->ddc2 && ((DDCReg == RADEON_LCD_GPIO_MASK) || (DDCReg == RADEON_MDGPIO_EN_REG))) { - MonInfo = xf86DoEDID_DDC2(pScrn->scrnIndex, radeon_output->pI2CBus); - } else { - xf86DrvMsg(pScrn->scrnIndex, X_WARNING, "DDC2/I2C is not properly initialized\n"); - MonType = MT_NONE; ++ OUTREG(DDCReg, INREG(DDCReg) & ++ ~(RADEON_GPIO_EN_0 | RADEON_GPIO_EN_1)); ++ } } - OUTREG(DDCReg, INREG(DDCReg) & - ~(RADEON_GPIO_EN_0 | RADEON_GPIO_EN_1)); + return MonInfo; +} - ++ +static RADEONMonitorType +radeon_ddc_connected(xf86OutputPtr output) +{ @@ -13380,13 +13351,13 @@ index 62cc5d4..72addef 100644 + RADEONMonitorType MonType = MT_NONE; + xf86MonPtr MonInfo = NULL; + RADEONOutputPrivatePtr radeon_output = output->driver_private; -+ + + if (radeon_output->pI2CBus) + MonInfo = radeon_do_ddc(output); if (MonInfo) { if (!xf86ReturnOptValBool(info->Options, OPTION_IGNORE_EDID, FALSE)) xf86OutputSetEDID(output, MonInfo); -@@ -342,67 +312,21 @@ RADEONDisplayDDCConnected(ScrnInfoPtr pScrn, xf86OutputPtr output) +@@ -342,67 +315,21 @@ RADEONDisplayDDCConnected(ScrnInfoPtr pScrn, xf86OutputPtr output) MonType = MT_DFP; else if (radeon_output->type == OUTPUT_HDMI) MonType = MT_DFP; @@ -13459,7 +13430,7 @@ index 62cc5d4..72addef 100644 #ifndef __powerpc__ static RADEONMonitorType -@@ -449,42 +373,58 @@ RADEONDetectLidStatus(ScrnInfoPtr pScrn) +@@ -449,42 +376,58 @@ RADEONDetectLidStatus(ScrnInfoPtr pScrn) #endif /* __powerpc__ */ @@ -13538,7 +13509,7 @@ index 62cc5d4..72addef 100644 if (IS_AVIVO_VARIANT) { atombios_output_dpms(output, mode); -@@ -493,6 +433,11 @@ radeon_dpms(xf86OutputPtr output, int mode) +@@ -493,6 +436,11 @@ radeon_dpms(xf86OutputPtr output, int mode) } radeon_bios_output_dpms(output, mode); @@ -13550,7 +13521,59 @@ index 62cc5d4..72addef 100644 } static void -@@ -673,15 +618,15 @@ radeon_bios_output_lock(xf86OutputPtr output, Bool lock) +@@ -638,8 +586,26 @@ radeon_mode_fixup(xf86OutputPtr output, DisplayModePtr mode, + static void + radeon_mode_prepare(xf86OutputPtr output) + { ++ xf86CrtcConfigPtr config = XF86_CRTC_CONFIG_PTR (output->scrn); ++ int o; ++ ++ for (o = 0; o < config->num_output; o++) { ++ xf86OutputPtr loop_output = config->output[o]; ++ if (loop_output == output) ++ continue; ++ else if (loop_output->crtc) { ++ xf86CrtcPtr other_crtc = loop_output->crtc; ++ if (other_crtc->enabled) { ++ radeon_dpms(loop_output, DPMSModeOff); ++ radeon_crtc_dpms(other_crtc, DPMSModeOff); ++ } ++ } ++ } ++ + radeon_bios_output_lock(output, TRUE); + radeon_dpms(output, DPMSModeOff); ++ radeon_crtc_dpms(output->crtc, DPMSModeOff); ++ + } + + static void +@@ -659,7 +625,24 @@ radeon_mode_set(xf86OutputPtr output, DisplayModePtr mode, + static void + radeon_mode_commit(xf86OutputPtr output) + { ++ xf86CrtcConfigPtr config = XF86_CRTC_CONFIG_PTR (output->scrn); ++ int o; ++ ++ for (o = 0; o < config->num_output; o++) { ++ xf86OutputPtr loop_output = config->output[o]; ++ if (loop_output == output) ++ continue; ++ else if (loop_output->crtc) { ++ xf86CrtcPtr other_crtc = loop_output->crtc; ++ if (other_crtc->enabled) { ++ radeon_dpms(loop_output, DPMSModeOn); ++ radeon_crtc_dpms(other_crtc, DPMSModeOn); ++ } ++ } ++ } ++ + radeon_dpms(output, DPMSModeOn); ++ radeon_crtc_dpms(output->crtc, DPMSModeOn); + radeon_bios_output_lock(output, FALSE); + } + +@@ -673,15 +656,15 @@ radeon_bios_output_lock(xf86OutputPtr output, Bool lock) if (info->IsAtomBios) { if (lock) { @@ -13570,7 +13593,7 @@ index 62cc5d4..72addef 100644 } } if (info->ChipFamily >= CHIP_FAMILY_R600) -@@ -1032,7 +977,7 @@ radeon_detect(xf86OutputPtr output) +@@ -1032,7 +1015,7 @@ radeon_detect(xf86OutputPtr output) radeon_output->MonType = MT_UNKNOWN; radeon_bios_output_connected(output, FALSE); @@ -13579,7 +13602,7 @@ index 62cc5d4..72addef 100644 /* nothing connected, light up some defaults so the server comes up */ if (radeon_output->MonType == MT_NONE && -@@ -1101,24 +1046,6 @@ radeon_detect(xf86OutputPtr output) +@@ -1101,24 +1084,6 @@ radeon_detect(xf86OutputPtr output) break; } @@ -13604,7 +13627,7 @@ index 62cc5d4..72addef 100644 if (connected) return XF86OutputStatusConnected; else -@@ -1149,7 +1076,7 @@ radeon_set_backlight_level(xf86OutputPtr output, int level) +@@ -1149,7 +1114,7 @@ radeon_set_backlight_level(xf86OutputPtr output, int level) ScrnInfoPtr pScrn = output->scrn; RADEONInfoPtr info = RADEONPTR(pScrn); unsigned char * RADEONMMIO = info->MMIO; @@ -13613,7 +13636,7 @@ index 62cc5d4..72addef 100644 lvds_gen_cntl = INREG(RADEON_LVDS_GEN_CNTL); lvds_gen_cntl |= RADEON_LVDS_BL_MOD_EN; -@@ -1168,6 +1095,7 @@ static Atom tmds_pll_atom; +@@ -1168,6 +1133,7 @@ static Atom tmds_pll_atom; static Atom rmx_atom; static Atom monitor_type_atom; static Atom load_detection_atom; @@ -13621,7 +13644,7 @@ index 62cc5d4..72addef 100644 static Atom tv_hsize_atom; static Atom tv_hpos_atom; static Atom tv_vpos_atom; -@@ -1235,6 +1163,30 @@ radeon_create_resources(xf86OutputPtr output) +@@ -1235,6 +1201,30 @@ radeon_create_resources(xf86OutputPtr output) } } @@ -13652,7 +13675,7 @@ index 62cc5d4..72addef 100644 if (OUTPUT_IS_DVI && radeon_output->TMDSType == TMDS_INT) { tmds_pll_atom = MAKE_ATOM("tmds_pll"); -@@ -1413,6 +1365,26 @@ radeon_create_resources(xf86OutputPtr output) +@@ -1413,6 +1403,26 @@ radeon_create_resources(xf86OutputPtr output) } static Bool @@ -13679,7 +13702,7 @@ index 62cc5d4..72addef 100644 radeon_set_property(xf86OutputPtr output, Atom property, RRPropertyValuePtr value) { -@@ -1451,22 +1423,47 @@ radeon_set_property(xf86OutputPtr output, Atom property, +@@ -1451,22 +1461,47 @@ radeon_set_property(xf86OutputPtr output, Atom property, radeon_output->load_detection = val; @@ -13731,7 +13754,7 @@ index 62cc5d4..72addef 100644 } else if (property == tmds_pll_atom) { const char *s; if (value->type != XA_STRING || value->format != 8) -@@ -1475,12 +1472,12 @@ radeon_set_property(xf86OutputPtr output, Atom property, +@@ -1475,12 +1510,12 @@ radeon_set_property(xf86OutputPtr output, Atom property, if (value->size == strlen("bios") && !strncmp("bios", s, strlen("bios"))) { if (!RADEONGetTMDSInfoFromBIOS(output)) RADEONGetTMDSInfoFromTable(output); @@ -13748,7 +13771,7 @@ index 62cc5d4..72addef 100644 } else if (property == monitor_type_atom) { const char *s; if (value->type != XA_STRING || value->format != 8) -@@ -1495,8 +1492,8 @@ radeon_set_property(xf86OutputPtr output, Atom property, +@@ -1495,8 +1530,8 @@ radeon_set_property(xf86OutputPtr output, Atom property, } else if (value->size == strlen("digital") && !strncmp("digital", s, strlen("digital"))) { radeon_output->DVIType = DVI_DIGITAL; return TRUE; @@ -13759,7 +13782,7 @@ index 62cc5d4..72addef 100644 } else if (property == tv_hsize_atom) { if (value->type != XA_INTEGER || value->format != 32 || -@@ -1511,7 +1508,7 @@ radeon_set_property(xf86OutputPtr output, Atom property, +@@ -1511,7 +1546,7 @@ radeon_set_property(xf86OutputPtr output, Atom property, radeon_output->hSize = val; if (radeon_output->tv_on && !IS_AVIVO_VARIANT) RADEONUpdateHVPosition(output, &output->crtc->mode); @@ -13768,7 +13791,7 @@ index 62cc5d4..72addef 100644 } else if (property == tv_hpos_atom) { if (value->type != XA_INTEGER || value->format != 32 || -@@ -1526,7 +1523,7 @@ radeon_set_property(xf86OutputPtr output, Atom property, +@@ -1526,7 +1561,7 @@ radeon_set_property(xf86OutputPtr output, Atom property, radeon_output->hPos = val; if (radeon_output->tv_on && !IS_AVIVO_VARIANT) RADEONUpdateHVPosition(output, &output->crtc->mode); @@ -13777,7 +13800,7 @@ index 62cc5d4..72addef 100644 } else if (property == tv_vpos_atom) { if (value->type != XA_INTEGER || value->format != 32 || -@@ -1541,38 +1538,38 @@ radeon_set_property(xf86OutputPtr output, Atom property, +@@ -1541,38 +1576,38 @@ radeon_set_property(xf86OutputPtr output, Atom property, radeon_output->vPos = val; if (radeon_output->tv_on && !IS_AVIVO_VARIANT) RADEONUpdateHVPosition(output, &output->crtc->mode); @@ -13826,7 +13849,7 @@ index 62cc5d4..72addef 100644 } return TRUE; -@@ -1622,6 +1619,8 @@ void RADEONSetOutputType(ScrnInfoPtr pScrn, RADEONOutputPrivatePtr radeon_output +@@ -1622,6 +1657,8 @@ void RADEONSetOutputType(ScrnInfoPtr pScrn, RADEONOutputPrivatePtr radeon_output case CONNECTOR_HDMI_TYPE_A: case CONNECTOR_HDMI_TYPE_B: output = OUTPUT_HDMI; break; @@ -13835,7 +13858,7 @@ index 62cc5d4..72addef 100644 case CONNECTOR_DIGITAL: case CONNECTOR_NONE: case CONNECTOR_UNSUPPORTED: -@@ -1653,7 +1652,7 @@ Bool AVIVOI2CDoLock(xf86OutputPtr output, int lock_state) +@@ -1653,7 +1690,7 @@ Bool AVIVOI2CDoLock(xf86OutputPtr output, int lock_state) RADEONOutputPrivatePtr radeon_output = output->driver_private; RADEONI2CBusPtr pRADEONI2CBus = radeon_output->pI2CBus->DriverPrivate.ptr; unsigned char *RADEONMMIO = info->MMIO; @@ -13844,7 +13867,7 @@ index 62cc5d4..72addef 100644 temp = INREG(pRADEONI2CBus->mask_clk_reg); if (lock_state == AVIVO_I2C_ENABLE) -@@ -1698,13 +1697,13 @@ static void RADEONI2CPutBits(I2CBusPtr b, int Clock, int data) +@@ -1698,13 +1735,13 @@ static void RADEONI2CPutBits(I2CBusPtr b, int Clock, int data) unsigned char *RADEONMMIO = info->MMIO; RADEONI2CBusPtr pRADEONI2CBus = b->DriverPrivate.ptr; @@ -13860,7 +13883,7 @@ index 62cc5d4..72addef 100644 val |= (data ? 0:pRADEONI2CBus->put_data_mask); OUTREG(pRADEONI2CBus->put_data_reg, val); /* read back to improve reliability on some cards. */ -@@ -1821,8 +1820,8 @@ RADEONGetPanelInfoFromReg (xf86OutputPtr output) +@@ -1821,8 +1858,8 @@ RADEONGetPanelInfoFromReg (xf86OutputPtr output) RADEONInfoPtr info = RADEONPTR(pScrn); RADEONOutputPrivatePtr radeon_output = output->driver_private; unsigned char *RADEONMMIO = info->MMIO; @@ -13871,7 +13894,7 @@ index 62cc5d4..72addef 100644 radeon_output->PanelPwrDly = 200; if (fp_vert_stretch & RADEON_VERT_STRETCH_ENABLE) { -@@ -1845,7 +1844,7 @@ RADEONGetPanelInfoFromReg (xf86OutputPtr output) +@@ -1845,7 +1882,7 @@ RADEONGetPanelInfoFromReg (xf86OutputPtr output) // move this to crtc function if (xf86ReturnOptValBool(info->Options, OPTION_LVDS_PROBE_PLL, TRUE)) { @@ -13880,7 +13903,7 @@ index 62cc5d4..72addef 100644 ppll_div_sel = INREG8(RADEON_CLOCK_CNTL_INDEX + 1) & 0x3; RADEONPllErrataAfterIndex(info); -@@ -2067,9 +2066,8 @@ RADEONGetTMDSInfo(xf86OutputPtr output) +@@ -2067,9 +2104,8 @@ RADEONGetTMDSInfo(xf86OutputPtr output) radeon_output->tmds_pll[i].freq = 0; } @@ -13892,7 +13915,7 @@ index 62cc5d4..72addef 100644 } -@@ -2139,16 +2137,17 @@ void RADEONInitConnector(xf86OutputPtr output) +@@ -2139,16 +2175,17 @@ void RADEONInitConnector(xf86OutputPtr output) RADEONInfoPtr info = RADEONPTR(pScrn); RADEONOutputPrivatePtr radeon_output = output->driver_private; @@ -13915,7 +13938,7 @@ index 62cc5d4..72addef 100644 if (radeon_output->type == OUTPUT_LVDS) { radeon_output->rmx_type = RMX_FULL; -@@ -2179,16 +2178,17 @@ void RADEONInitConnector(xf86OutputPtr output) +@@ -2179,16 +2216,17 @@ void RADEONInitConnector(xf86OutputPtr output) RADEONGetTMDSInfo(output); } @@ -13936,7 +13959,7 @@ index 62cc5d4..72addef 100644 if (radeon_output->ddc_i2c.valid) RADEONI2CInit(output, &radeon_output->pI2CBus, output->name, FALSE); -@@ -2393,7 +2393,8 @@ static void RADEONSetupGenericConnectors(ScrnInfoPtr pScrn) +@@ -2393,7 +2431,8 @@ static void RADEONSetupGenericConnectors(ScrnInfoPtr pScrn) info->BiosConnector[0].valid = TRUE; /* IGP only has TVDAC */ @@ -13946,7 +13969,7 @@ index 62cc5d4..72addef 100644 info->BiosConnector[1].ddc_i2c = legacy_setup_i2c_bus(RADEON_GPIO_CRT2_DDC); else info->BiosConnector[1].ddc_i2c = legacy_setup_i2c_bus(RADEON_GPIO_VGA_DDC); -@@ -2421,7 +2422,8 @@ static void RADEONSetupGenericConnectors(ScrnInfoPtr pScrn) +@@ -2421,7 +2460,8 @@ static void RADEONSetupGenericConnectors(ScrnInfoPtr pScrn) } else { /* Below is the most common setting, but may not be true */ if (info->IsIGP) { @@ -13956,7 +13979,7 @@ index 62cc5d4..72addef 100644 info->BiosConnector[0].ddc_i2c = legacy_setup_i2c_bus(RADEON_GPIO_CRT2_DDC); else info->BiosConnector[0].ddc_i2c = legacy_setup_i2c_bus(RADEON_GPIO_VGA_DDC); -@@ -2595,10 +2597,47 @@ static RADEONMacModel RADEONDetectMacModel(ScrnInfoPtr pScrn) +@@ -2595,10 +2635,47 @@ static RADEONMacModel RADEONDetectMacModel(ScrnInfoPtr pScrn) #endif /* __powerpc__ */ @@ -14004,7 +14027,7 @@ index 62cc5d4..72addef 100644 RADEONInfoPtr info = RADEONPTR(pScrn); RADEONEntPtr pRADEONEnt = RADEONEntPriv(pScrn); xf86OutputPtr output; -@@ -2729,11 +2768,12 @@ Bool RADEONSetupConnectors(ScrnInfoPtr pScrn) +@@ -2729,11 +2806,12 @@ Bool RADEONSetupConnectors(ScrnInfoPtr pScrn) for (i = 0 ; i < RADEON_MAX_BIOS_CONNECTOR; i++) { if (info->BiosConnector[i].valid) { @@ -14018,7 +14041,7 @@ index 62cc5d4..72addef 100644 if (!radeon_output) { return FALSE; } -@@ -2742,6 +2782,7 @@ Bool RADEONSetupConnectors(ScrnInfoPtr pScrn) +@@ -2742,6 +2820,7 @@ Bool RADEONSetupConnectors(ScrnInfoPtr pScrn) radeon_output->devices = info->BiosConnector[i].devices; radeon_output->output_id = info->BiosConnector[i].output_id; radeon_output->ddc_i2c = info->BiosConnector[i].ddc_i2c; @@ -14026,7 +14049,7 @@ index 62cc5d4..72addef 100644 if (radeon_output->ConnectorType == CONNECTOR_DVI_D) radeon_output->DACType = DAC_NONE; -@@ -2798,6 +2839,12 @@ Bool RADEONSetupConnectors(ScrnInfoPtr pScrn) +@@ -2798,6 +2877,12 @@ Bool RADEONSetupConnectors(ScrnInfoPtr pScrn) } } @@ -14040,9 +14063,25 @@ index 62cc5d4..72addef 100644 } diff --git a/src/radeon_pci_chipset_gen.h b/src/radeon_pci_chipset_gen.h -index ab6b62a..7e4cb17 100644 +index ab6b62a..39adb5e 100644 --- a/src/radeon_pci_chipset_gen.h +++ b/src/radeon_pci_chipset_gen.h +@@ -96,6 +96,7 @@ PciChipsets RADEONPciChipsets[] = { + { PCI_CHIP_RV410_564F, PCI_CHIP_RV410_564F, RES_SHARED_VGA }, + { PCI_CHIP_RV410_5652, PCI_CHIP_RV410_5652, RES_SHARED_VGA }, + { PCI_CHIP_RV410_5653, PCI_CHIP_RV410_5653, RES_SHARED_VGA }, ++ { PCI_CHIP_RV410_5657, PCI_CHIP_RV410_5657, RES_SHARED_VGA }, + { PCI_CHIP_RS300_5834, PCI_CHIP_RS300_5834, RES_SHARED_VGA }, + { PCI_CHIP_RS300_5835, PCI_CHIP_RS300_5835, RES_SHARED_VGA }, + { PCI_CHIP_RS480_5954, PCI_CHIP_RS480_5954, RES_SHARED_VGA }, +@@ -115,7 +116,6 @@ PciChipsets RADEONPciChipsets[] = { + { PCI_CHIP_RV370_5B60, PCI_CHIP_RV370_5B60, RES_SHARED_VGA }, + { PCI_CHIP_RV370_5B62, PCI_CHIP_RV370_5B62, RES_SHARED_VGA }, + { PCI_CHIP_RV370_5B63, PCI_CHIP_RV370_5B63, RES_SHARED_VGA }, +- { PCI_CHIP_RV370_5657, PCI_CHIP_RV370_5657, RES_SHARED_VGA }, + { PCI_CHIP_RV370_5B64, PCI_CHIP_RV370_5B64, RES_SHARED_VGA }, + { PCI_CHIP_RV370_5B65, PCI_CHIP_RV370_5B65, RES_SHARED_VGA }, + { PCI_CHIP_RV280_5C61, PCI_CHIP_RV280_5C61, RES_SHARED_VGA }, @@ -201,9 +201,9 @@ PciChipsets RADEONPciChipsets[] = { { PCI_CHIP_RV530_71D6, PCI_CHIP_RV530_71D6, RES_SHARED_VGA }, { PCI_CHIP_RV530_71DA, PCI_CHIP_RV530_71DA, RES_SHARED_VGA }, @@ -14092,9 +14131,25 @@ index ab6b62a..7e4cb17 100644 { -1, -1, RES_UNDEFINED } }; diff --git a/src/radeon_pci_device_match_gen.h b/src/radeon_pci_device_match_gen.h -index 04393da..72ff0d1 100644 +index 04393da..d81cbe3 100644 --- a/src/radeon_pci_device_match_gen.h +++ b/src/radeon_pci_device_match_gen.h +@@ -96,6 +96,7 @@ static const struct pci_id_match radeon_device_match[] = { + ATI_DEVICE_MATCH( PCI_CHIP_RV410_564F, 0 ), + ATI_DEVICE_MATCH( PCI_CHIP_RV410_5652, 0 ), + ATI_DEVICE_MATCH( PCI_CHIP_RV410_5653, 0 ), ++ ATI_DEVICE_MATCH( PCI_CHIP_RV410_5657, 0 ), + ATI_DEVICE_MATCH( PCI_CHIP_RS300_5834, 0 ), + ATI_DEVICE_MATCH( PCI_CHIP_RS300_5835, 0 ), + ATI_DEVICE_MATCH( PCI_CHIP_RS480_5954, 0 ), +@@ -115,7 +116,6 @@ static const struct pci_id_match radeon_device_match[] = { + ATI_DEVICE_MATCH( PCI_CHIP_RV370_5B60, 0 ), + ATI_DEVICE_MATCH( PCI_CHIP_RV370_5B62, 0 ), + ATI_DEVICE_MATCH( PCI_CHIP_RV370_5B63, 0 ), +- ATI_DEVICE_MATCH( PCI_CHIP_RV370_5657, 0 ), + ATI_DEVICE_MATCH( PCI_CHIP_RV370_5B64, 0 ), + ATI_DEVICE_MATCH( PCI_CHIP_RV370_5B65, 0 ), + ATI_DEVICE_MATCH( PCI_CHIP_RV280_5C61, 0 ), @@ -201,9 +201,9 @@ static const struct pci_id_match radeon_device_match[] = { ATI_DEVICE_MATCH( PCI_CHIP_RV530_71D6, 0 ), ATI_DEVICE_MATCH( PCI_CHIP_RV530_71DA, 0 ), @@ -14791,7 +14846,7 @@ index 9c1bdc5..24af52b 100644 /* radeon_probe.c */ diff --git a/src/radeon_reg.h b/src/radeon_reg.h -index 046c52b..b2d6fd1 100644 +index 046c52b..59e2f12 100644 --- a/src/radeon_reg.h +++ b/src/radeon_reg.h @@ -265,6 +265,7 @@ @@ -14852,7 +14907,15 @@ index 046c52b..b2d6fd1 100644 #define RADEON_GPIOPAD_A 0x019c #define RADEON_MDGPIO_Y_REG 0x01b4 #define RADEON_MEM_ADDR_CONFIG 0x0148 -@@ -1056,6 +1087,9 @@ +@@ -1038,6 +1069,7 @@ + #define RADEON_MEM_SDRAM_MODE_REG 0x0158 + # define RADEON_SDRAM_MODE_MASK 0xffff0000 + # define RADEON_B3MEM_RESET_MASK 0x6fffffff ++# define RADEON_MEM_CFG_TYPE_DDR (1 << 30) + #define RADEON_MEM_STR_CNTL 0x0150 + # define RADEON_MEM_PWRUP_COMPL_A (1 << 0) + # define RADEON_MEM_PWRUP_COMPL_B (1 << 1) +@@ -1056,6 +1088,9 @@ #define RADEON_MPLL_CNTL 0x000e /* PLL */ #define RADEON_MPP_TB_CONFIG 0x01c0 /* ? */ #define RADEON_MPP_GP_CONFIG 0x01c8 /* ? */ @@ -14862,7 +14925,15 @@ index 046c52b..b2d6fd1 100644 #define R300_MC_IND_INDEX 0x01f8 # define R300_MC_IND_ADDR_MASK 0x3f # define R300_MC_IND_WR_EN (1 << 8) -@@ -1620,6 +1654,7 @@ +@@ -1423,6 +1458,7 @@ + # define RADEON_RB2D_DC_FLUSH_ALL 0xf + # define RADEON_RB2D_DC_BUSY (1 << 31) + #define RADEON_RB2D_DSTCACHE_MODE 0x3428 ++#define RADEON_DSTCACHE_CTLSTAT 0x1714 + + #define RADEON_RB3D_ZCACHE_MODE 0x3250 + #define RADEON_RB3D_ZCACHE_CTLSTAT 0x3254 +@@ -1620,6 +1656,7 @@ # define RADEON_VIP_BUSY 0 # define RADEON_VIP_IDLE 1 # define RADEON_VIP_RESET 2 @@ -14870,7 +14941,7 @@ index 046c52b..b2d6fd1 100644 #define RADEON_VIPH_DV_LAT 0x0c44 #define RADEON_VIPH_BM_CHUNK 0x0c48 #define RADEON_VIPH_DV_INT 0x0c4c -@@ -1634,9 +1669,25 @@ +@@ -1634,9 +1671,25 @@ #define RADEON_WAIT_UNTIL 0x1720 # define RADEON_WAIT_CRTC_PFLIP (1 << 0) @@ -14896,7 +14967,7 @@ index 046c52b..b2d6fd1 100644 #define RADEON_X_MPLL_REF_FB_DIV 0x000a /* PLL */ #define RADEON_XCLK_CNTL 0x000d /* PLL */ -@@ -3328,10 +3379,32 @@ +@@ -3328,10 +3381,32 @@ # define RADEON_TVPLL_TEST_DIS (1 << 31) # define RADEON_TVCLK_SRC_SEL_TVPLL (1 << 30) @@ -14933,9 +15004,11 @@ index 046c52b..b2d6fd1 100644 #define RS690_MC_INDEX 0x78 # define RS690_MC_INDEX_MASK 0x1ff -@@ -3343,7 +3416,17 @@ +@@ -3342,8 +3417,19 @@ + #define RS690_MC_FB_LOCATION 0x100 #define RS690_MC_AGP_LOCATION 0x101 #define RS690_MC_AGP_BASE 0x102 ++#define RS690_MC_AGP_BASE_2 0x103 #define RS690_MC_STATUS 0x90 -#define RS690_MC_STATUS_IDLE (1 << 0) +#define RS690_MC_STATUS_IDLE (1 << 0) @@ -14952,7 +15025,32 @@ index 046c52b..b2d6fd1 100644 #define AVIVO_MC_INDEX 0x0070 #define R520_MC_STATUS 0x00 -@@ -3359,6 +3442,8 @@ +@@ -3352,13 +3438,29 @@ + #define RV515_MC_STATUS_IDLE (1<<4) + #define AVIVO_MC_DATA 0x0074 + +-#define RV515_MC_FB_LOCATION 0x1 +-#define RV515_MC_AGP_LOCATION 0x2 +-#define R520_MC_FB_LOCATION 0x4 +-#define R520_MC_AGP_LOCATION 0x5 ++#define RV515_MC_FB_LOCATION 0x1 ++#define RV515_MC_AGP_LOCATION 0x2 ++#define RV515_MC_AGP_BASE 0x3 ++#define RV515_MC_AGP_BASE_2 0x4 ++#define RV515_MC_CNTL 0x5 ++# define RV515_MEM_NUM_CHANNELS_MASK 0x3 ++#define R520_MC_FB_LOCATION 0x4 ++#define R520_MC_AGP_LOCATION 0x5 ++#define R520_MC_AGP_BASE 0x6 ++#define R520_MC_AGP_BASE_2 0x7 ++#define R520_MC_CNTL0 0x8 ++# define R520_MEM_NUM_CHANNELS_MASK (0x3 << 24) ++# define R520_MEM_NUM_CHANNELS_SHIFT 24 ++# define R520_MC_CHANNEL_SIZE (1 << 23) ++ ++#define R600_RAMCFG 0x2408 ++# define R600_CHANSIZE (1 << 7) ++# define R600_CHANSIZE_OVERRIDE (1 << 10) #define AVIVO_HDP_FB_LOCATION 0x134 @@ -14961,7 +15059,7 @@ index 046c52b..b2d6fd1 100644 #define AVIVO_D1VGA_CONTROL 0x0330 # define AVIVO_DVGA_CONTROL_MODE_ENABLE (1<<0) # define AVIVO_DVGA_CONTROL_TIMING_SELECT (1<<8) -@@ -3475,6 +3560,8 @@ +@@ -3475,6 +3577,8 @@ #define AVIVO_D1CUR_SIZE 0x6410 #define AVIVO_D1CUR_POSITION 0x6414 #define AVIVO_D1CUR_HOT_SPOT 0x6418 @@ -14970,7 +15068,7 @@ index 046c52b..b2d6fd1 100644 #define AVIVO_DC_LUT_RW_SELECT 0x6480 #define AVIVO_DC_LUT_RW_MODE 0x6484 -@@ -3555,6 +3642,8 @@ +@@ -3555,6 +3659,8 @@ #define AVIVO_D2SCL_SCALER_ENABLE 0x6d90 #define AVIVO_D2SCL_SCALER_TAP_CONTROL 0x6d94 @@ -14979,7 +15077,7 @@ index 046c52b..b2d6fd1 100644 #define AVIVO_DACA_ENABLE 0x7800 # define AVIVO_DAC_ENABLE (1 << 0) #define AVIVO_DACA_SOURCE_SELECT 0x7804 -@@ -3745,6 +3834,8 @@ +@@ -3745,6 +3851,8 @@ # define AVIVO_LVDS_BACKLIGHT_LEVEL_MASK 0x0000ff00 # define AVIVO_LVDS_BACKLIGHT_LEVEL_SHIFT 8 @@ -14988,7 +15086,7 @@ index 046c52b..b2d6fd1 100644 #define AVIVO_GPIO_0 0x7e30 #define AVIVO_GPIO_1 0x7e40 #define AVIVO_GPIO_2 0x7e50 -@@ -3793,6 +3884,15 @@ +@@ -3793,6 +3901,15 @@ # define AVIVO_I2C_EN (1 << 0) # define AVIVO_I2C_RESET (1 << 8) @@ -15004,7 +15102,7 @@ index 046c52b..b2d6fd1 100644 #define R600_MC_VM_FB_LOCATION 0x2180 #define R600_MC_VM_AGP_TOP 0x2184 #define R600_MC_VM_AGP_BOT 0x2188 -@@ -3809,6 +3909,11 @@ +@@ -3809,6 +3926,11 @@ #define R600_CONFIG_F0_BASE 0x542C #define R600_CONFIG_APER_SIZE 0x5430 @@ -15016,7 +15114,7 @@ index 046c52b..b2d6fd1 100644 #define R600_BIOS_0_SCRATCH 0x1724 #define R600_BIOS_1_SCRATCH 0x1728 #define R600_BIOS_2_SCRATCH 0x172c -@@ -3832,6 +3937,7 @@ +@@ -3832,6 +3954,7 @@ #define R300_GB_SELECT 0x401c #define R300_GB_ENABLE 0x4008 #define R300_GB_AA_CONFIG 0x4020 @@ -15024,7 +15122,7 @@ index 046c52b..b2d6fd1 100644 #define R300_GB_MSPOS0 0x4010 # define R300_MS_X0_SHIFT 0 # define R300_MS_Y0_SHIFT 4 -@@ -3850,6 +3956,10 @@ +@@ -3850,6 +3973,10 @@ # define R300_MS_Y5_SHIFT 20 # define R300_MSBD1_SHIFT 24 @@ -15035,7 +15133,7 @@ index 046c52b..b2d6fd1 100644 #define R300_GA_POLY_MODE 0x4288 # define R300_FRONT_PTYPE_POINT (0 << 4) # define R300_FRONT_PTYPE_LINE (1 << 4) -@@ -3889,6 +3999,8 @@ +@@ -3889,6 +4016,8 @@ # define R300_ALPHA3_SHADING_GOURAUD (2 << 14) #define R300_GA_OFFSET 0x4290 @@ -15044,7 +15142,7 @@ index 046c52b..b2d6fd1 100644 #define R300_VAP_CNTL_STATUS 0x2140 # define R300_PVS_BYPASS (1 << 8) #define R300_VAP_PVS_STATE_FLUSH_REG 0x2284 -@@ -3899,6 +4011,7 @@ +@@ -3899,6 +4028,7 @@ # define R300_VF_MAX_VTX_NUM_SHIFT 18 # define R300_GL_CLIP_SPACE_DEF (0 << 22) # define R300_DX_CLIP_SPACE_DEF (1 << 22) @@ -15052,7 +15150,7 @@ index 046c52b..b2d6fd1 100644 #define R300_VAP_VTE_CNTL 0x20B0 # define R300_VPORT_X_SCALE_ENA (1 << 0) # define R300_VPORT_X_OFFSET_ENA (1 << 1) -@@ -3909,6 +4022,7 @@ +@@ -3909,6 +4039,7 @@ # define R300_VTX_XY_FMT (1 << 8) # define R300_VTX_Z_FMT (1 << 9) # define R300_VTX_W0_FMT (1 << 10) @@ -15060,7 +15158,7 @@ index 046c52b..b2d6fd1 100644 #define R300_VAP_PSC_SGN_NORM_CNTL 0x21DC #define R300_VAP_PROG_STREAM_CNTL_0 0x2150 # define R300_DATA_TYPE_0_SHIFT 0 -@@ -3986,6 +4100,123 @@ +@@ -3986,6 +4117,123 @@ # define R300_PVS_LAST_VTX_SRC_INST_SHIFT 0 #define R300_VAP_PVS_VECTOR_INDX_REG 0x2200 #define R300_VAP_PVS_VECTOR_DATA_REG 0x2204 @@ -15184,7 +15282,7 @@ index 046c52b..b2d6fd1 100644 #define R300_VAP_PVS_FLOW_CNTL_OPC 0x22DC #define R300_VAP_OUT_VTX_FMT_0 0x2090 # define R300_VTX_POS_PRESENT (1 << 0) -@@ -4019,6 +4250,9 @@ +@@ -4019,6 +4267,9 @@ # define R300_CLIP_DISABLE (1 << 16) # define R300_UCP_CULL_ONLY_ENA (1 << 17) # define R300_BOUNDARY_EDGE_FLAG_ENA (1 << 18) @@ -15194,7 +15292,7 @@ index 046c52b..b2d6fd1 100644 #define R300_SU_TEX_WRAP 0x42a0 #define R300_SU_POLY_OFFSET_ENABLE 0x42b4 -@@ -4036,6 +4270,7 @@ +@@ -4036,6 +4287,7 @@ # define R300_RS_COUNT_HIRES_EN (1 << 18) #define R300_RS_IP_0 0x4310 @@ -15202,7 +15300,7 @@ index 046c52b..b2d6fd1 100644 # define R300_RS_TEX_PTR(x) (x << 0) # define R300_RS_COL_PTR(x) (x << 6) # define R300_RS_COL_FMT(x) (x << 9) -@@ -4063,7 +4298,10 @@ +@@ -4063,7 +4315,10 @@ # define R300_RS_W_EN (1 << 4) # define R300_TX_OFFSET_RS(x) (x << 5) #define R300_RS_INST_0 0x4330 @@ -15213,7 +15311,7 @@ index 046c52b..b2d6fd1 100644 #define R300_TX_INVALTAGS 0x4100 #define R300_TX_FILTER0_0 0x4400 -@@ -4082,6 +4320,7 @@ +@@ -4082,6 +4337,7 @@ # define R300_TX_MIN_FILTER_NEAREST (1 << 11) # define R300_TX_MAG_FILTER_LINEAR (2 << 9) # define R300_TX_MIN_FILTER_LINEAR (2 << 11) @@ -15221,7 +15319,7 @@ index 046c52b..b2d6fd1 100644 #define R300_TX_FILTER1_0 0x4440 #define R300_TX_FORMAT0_0 0x4480 # define R300_TXWIDTH_SHIFT 0 -@@ -4164,11 +4403,16 @@ +@@ -4164,11 +4420,16 @@ # define R300_TX_FORMAT_SWAP_YUV (1 << 24) #define R300_TX_FORMAT2_0 0x4500 @@ -15239,7 +15337,7 @@ index 046c52b..b2d6fd1 100644 #define R300_TX_ENABLE 0x4104 # define R300_TEX_0_ENABLE (1 << 0) -@@ -4189,7 +4433,7 @@ +@@ -4189,7 +4450,7 @@ # define R300_OUT_FMT_C2_16_MPEG (7 << 0) # define R300_OUT_FMT_C2_4 (8 << 0) # define R300_OUT_FMT_C_3_3_2 (9 << 0) @@ -15248,7 +15346,7 @@ index 046c52b..b2d6fd1 100644 # define R300_OUT_FMT_C_11_11_10 (11 << 0) # define R300_OUT_FMT_C_10_11_11 (12 << 0) # define R300_OUT_FMT_C_2_10_10_10 (13 << 0) -@@ -4227,28 +4471,221 @@ +@@ -4227,28 +4488,223 @@ # define R300_TEX_CODE_OFFSET(x) (x << 13) # define R300_TEX_CODE_SIZE(x) (x << 18) #define R300_US_CODE_ADDR_0 0x4610 @@ -15451,9 +15549,11 @@ index 046c52b..b2d6fd1 100644 +#define R300_DST_PIPE_CONFIG 0x170c +# define R300_PIPE_AUTO_CONFIG (1 << 31) +#define R300_RB2D_DSTCACHE_MODE 0x3428 ++#define R300_RB2D_DSTCACHE_MODE 0x3428 +# define R300_DC_AUTOFLUSH_ENABLE (1 << 8) +# define R300_DC_DC_DISABLE_IGNORE_PE (1 << 17) -+#define R300_RB2D_DSTCACHE_CTLSTAT 0x342c ++#define R300_RB2D_DSTCACHE_CTLSTAT 0x342c /* use DSTCACHE_CTLSTAT instead */ ++#define R300_DSTCACHE_CTLSTAT 0x1714 +# define R300_DC_FLUSH_2D (1 << 0) +# define R300_DC_FREE_2D (1 << 2) +# define R300_RB2D_DC_FLUSH_ALL (R300_DC_FLUSH_2D | R300_DC_FREE_2D) @@ -15473,7 +15573,7 @@ index 046c52b..b2d6fd1 100644 #define R300_RB3D_ZSTENCILCNTL 0x4f04 #define R300_RB3D_ZCACHE_CTLSTAT 0x4f18 #define R300_RB3D_BW_CNTL 0x4f1c -@@ -4256,6 +4693,9 @@ +@@ -4256,6 +4712,9 @@ #define R300_RB3D_ZTOP 0x4f14 #define R300_RB3D_ROPCNTL 0x4e18 #define R300_RB3D_BLENDCNTL 0x4e04 @@ -15483,7 +15583,7 @@ index 046c52b..b2d6fd1 100644 #define R300_RB3D_ABLENDCNTL 0x4e08 #define R300_RB3D_DSTCACHE_CTLSTAT 0x4e4c #define R300_RB3D_COLOROFFSET0 0x4e28 -@@ -4387,7 +4827,7 @@ +@@ -4387,7 +4846,7 @@ # define R500_ALPHA_SRCP_OP_1_MINUS_2A0 (0 << 30) # define R500_ALPHA_SRCP_OP_A1_MINUS_A0 (1 << 30) # define R500_ALPHA_SRCP_OP_A1_PLUS_A0 (2 << 30) @@ -15492,7 +15592,7 @@ index 046c52b..b2d6fd1 100644 #define R500_US_ALU_RGBA_INST_0 0xb000 # define R500_ALU_RGBA_OP_MAD (0 << 0) # define R500_ALU_RGBA_OP_DP3 (1 << 0) -@@ -4540,7 +4980,7 @@ +@@ -4540,7 +4999,7 @@ # define R500_RGB_SRCP_OP_1_MINUS_2RGB0 (0 << 30) # define R500_RGB_SRCP_OP_RGB1_MINUS_RGB0 (1 << 30) # define R500_RGB_SRCP_OP_RGB1_PLUS_RGB0 (2 << 30) @@ -15501,7 +15601,7 @@ index 046c52b..b2d6fd1 100644 #define R500_US_CMN_INST_0 0xb800 # define R500_INST_TYPE_ALU (0 << 0) # define R500_INST_TYPE_OUT (1 << 0) -@@ -4779,17 +5219,18 @@ +@@ -4779,17 +5238,18 @@ #define R500_GA_US_VECTOR_DATA 0x4254 #define R500_RS_INST_0 0x4320 @@ -15531,7 +15631,7 @@ index 046c52b..b2d6fd1 100644 #define R500_US_FC_CTRL 0x4624 #define R500_US_CODE_ADDR 0x4630 -@@ -4797,16 +5238,18 @@ +@@ -4797,16 +5257,18 @@ #define R500_US_CODE_OFFSET 0x4638 #define R500_RS_IP_0 0x4074 @@ -15877,7 +15977,7 @@ index 329a834..cfa349d 100644 adapt->pFormats = Formats; adapt->nPorts = num_texture_ports; diff --git a/src/radeon_textured_videofuncs.c b/src/radeon_textured_videofuncs.c -index e0f3bba..d5d1b1c 100644 +index e0f3bba..f0dad03 100644 --- a/src/radeon_textured_videofuncs.c +++ b/src/radeon_textured_videofuncs.c @@ -74,22 +74,21 @@ FUNC_NAME(RADEONDisplayTexturedVideo)(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv @@ -15910,7 +16010,7 @@ index e0f3bba..d5d1b1c 100644 dst_pitch = exaGetPixmapPitch(pPixmap); } else #endif -@@ -107,28 +106,22 @@ FUNC_NAME(RADEONDisplayTexturedVideo)(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv +@@ -107,28 +106,25 @@ FUNC_NAME(RADEONDisplayTexturedVideo)(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv dstyoff = 0; #endif @@ -15935,7 +16035,11 @@ index e0f3bba..d5d1b1c 100644 + OUT_VIDEO_REG(RADEON_RB3D_DSTCACHE_CTLSTAT, RADEON_RB3D_DC_FLUSH); /* We must wait for 3d to idle, in case source was just written as a dest. */ OUT_VIDEO_REG(RADEON_WAIT_UNTIL, - RADEON_WAIT_HOST_IDLECLEAN | RADEON_WAIT_2D_IDLECLEAN | RADEON_WAIT_3D_IDLECLEAN); +- RADEON_WAIT_HOST_IDLECLEAN | RADEON_WAIT_2D_IDLECLEAN | RADEON_WAIT_3D_IDLECLEAN); ++ RADEON_WAIT_HOST_IDLECLEAN | ++ RADEON_WAIT_2D_IDLECLEAN | ++ RADEON_WAIT_3D_IDLECLEAN | ++ RADEON_WAIT_DMA_GUI_IDLE); FINISH_VIDEO(); - if (IS_R300_VARIANT || IS_AVIVO_VARIANT) { @@ -15945,7 +16049,7 @@ index e0f3bba..d5d1b1c 100644 switch (pPixmap->drawable.bitsPerPixel) { case 16: -@@ -144,6 +137,12 @@ FUNC_NAME(RADEONDisplayTexturedVideo)(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv +@@ -144,6 +140,12 @@ FUNC_NAME(RADEONDisplayTexturedVideo)(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv return; } @@ -15958,7 +16062,7 @@ index e0f3bba..d5d1b1c 100644 colorpitch = dst_pitch >> pixel_shift; colorpitch |= dst_format; -@@ -157,8 +156,8 @@ FUNC_NAME(RADEONDisplayTexturedVideo)(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv +@@ -157,8 +159,8 @@ FUNC_NAME(RADEONDisplayTexturedVideo)(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv txformat1 |= R300_TX_FORMAT_YUV_TO_RGB_CLAMP; @@ -15969,7 +16073,7 @@ index e0f3bba..d5d1b1c 100644 txformat0 |= R300_TXPITCH_EN; -@@ -173,6 +172,12 @@ FUNC_NAME(RADEONDisplayTexturedVideo)(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv +@@ -173,6 +175,12 @@ FUNC_NAME(RADEONDisplayTexturedVideo)(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv txpitch = pPriv->src_pitch / 2; txpitch -= 1; @@ -15982,7 +16086,7 @@ index e0f3bba..d5d1b1c 100644 txoffset = pPriv->src_offset; BEGIN_VIDEO(6); -@@ -187,173 +192,220 @@ FUNC_NAME(RADEONDisplayTexturedVideo)(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv +@@ -187,173 +195,220 @@ FUNC_NAME(RADEONDisplayTexturedVideo)(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv txenable = R300_TEX_0_ENABLE; /* setup the VAP */ @@ -16341,7 +16445,7 @@ index e0f3bba..d5d1b1c 100644 OUT_VIDEO_REG(R300_TX_INVALTAGS, 0); OUT_VIDEO_REG(R300_TX_ENABLE, txenable); -@@ -361,8 +413,8 @@ FUNC_NAME(RADEONDisplayTexturedVideo)(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv +@@ -361,8 +416,8 @@ FUNC_NAME(RADEONDisplayTexturedVideo)(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv OUT_VIDEO_REG(R300_RB3D_COLORPITCH0, colorpitch); blendcntl = RADEON_SRC_BLEND_GL_ONE | RADEON_DST_BLEND_GL_ZERO; @@ -16351,7 +16455,7 @@ index e0f3bba..d5d1b1c 100644 FINISH_VIDEO(); BEGIN_VIDEO(1); -@@ -538,8 +590,8 @@ FUNC_NAME(RADEONDisplayTexturedVideo)(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv +@@ -538,8 +593,8 @@ FUNC_NAME(RADEONDisplayTexturedVideo)(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv RADEON_CP_VC_CNTL_VTX_FMT_RADEON_MODE | (4 << RADEON_CP_VC_CNTL_NUM_SHIFT)); } else { @@ -16362,7 +16466,7 @@ index e0f3bba..d5d1b1c 100644 else BEGIN_RING(4 * VTX_DWORD_COUNT + 2); OUT_RING(CP_PACKET3(R200_CP_PACKET3_3D_DRAW_IMMD_2, -@@ -549,8 +601,8 @@ FUNC_NAME(RADEONDisplayTexturedVideo)(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv +@@ -549,8 +604,8 @@ FUNC_NAME(RADEONDisplayTexturedVideo)(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv (4 << RADEON_CP_VC_CNTL_NUM_SHIFT)); } #else /* ACCEL_CP */ @@ -16373,7 +16477,7 @@ index e0f3bba..d5d1b1c 100644 else BEGIN_VIDEO(1 + VTX_DWORD_COUNT * 4); -@@ -575,10 +627,9 @@ FUNC_NAME(RADEONDisplayTexturedVideo)(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv +@@ -575,10 +630,9 @@ FUNC_NAME(RADEONDisplayTexturedVideo)(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv VTX_OUT((float)(dstX + dstw), (float)dstY, xFixedToFloat(srcTopRight.x) / info->texW[0], xFixedToFloat(srcTopRight.y) / info->texH[0]); @@ -16387,6 +16491,21 @@ index e0f3bba..d5d1b1c 100644 #ifdef ACCEL_CP ADVANCE_RING(); +@@ -589,6 +643,14 @@ FUNC_NAME(RADEONDisplayTexturedVideo)(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv + pBox++; + } + ++ if (IS_R300_3D | IS_R500_3D) { ++ BEGIN_VIDEO(2); ++ OUT_VIDEO_REG(R300_RB3D_DSTCACHE_CTLSTAT, R300_RB3D_DC_FLUSH_ALL); ++ } else ++ BEGIN_VIDEO(1); ++ OUT_VIDEO_REG(RADEON_WAIT_UNTIL, RADEON_WAIT_3D_IDLECLEAN); ++ FINISH_VIDEO(); ++ + DamageDamageRegion(pPriv->pDraw, &pPriv->clip); + } + diff --git a/src/radeon_tv.c b/src/radeon_tv.c index d5d1e9e..90020b3 100644 --- a/src/radeon_tv.c @@ -16644,7 +16763,7 @@ index d5d1e9e..90020b3 100644 /* FIXME: need to revisit this when we add more modes */ diff --git a/src/radeon_video.c b/src/radeon_video.c -index 7502e1e..4a5d6e8 100644 +index 7502e1e..ac60166 100644 --- a/src/radeon_video.c +++ b/src/radeon_video.c @@ -285,14 +285,22 @@ void RADEONInitVideo(ScreenPtr pScreen) @@ -16798,7 +16917,7 @@ index 7502e1e..4a5d6e8 100644 0x00000100, 0x00000080, 0x00000100, 0x00000100, 0x00000100, 0x00000100, -@@ -841,16 +849,19 @@ static GAMMA_CURVE_R200 gamma_curve_r200[8] = +@@ -841,16 +849,18 @@ static GAMMA_CURVE_R200 gamma_curve_r200[8] = }; static void @@ -16808,20 +16927,51 @@ index 7502e1e..4a5d6e8 100644 RADEONInfoPtr info = RADEONPTR(pScrn); unsigned char *RADEONMMIO = info->MMIO; - CARD32 ov0_scale_cntl; -+ uint32_t ov0_scale_cntl; /* Set gamma */ RADEONWaitForIdleMMIO(pScrn); - ov0_scale_cntl = INREG(RADEON_OV0_SCALE_CNTL) & ~RADEON_SCALER_GAMMA_SEL_MASK; +- ov0_scale_cntl = INREG(RADEON_OV0_SCALE_CNTL) & ~RADEON_SCALER_GAMMA_SEL_MASK; - OUTREG(RADEON_OV0_SCALE_CNTL, ov0_scale_cntl | (gamma << 0x00000005)); -+ if (info->ChipFamily < CHIP_FAMILY_R200) ++ ++ if (info->ChipFamily < CHIP_FAMILY_R200) { ++ uint32_t ov0_scale_cntl = INREG(RADEON_OV0_SCALE_CNTL) & ~RADEON_SCALER_GAMMA_SEL_MASK; + OUTREG(RADEON_OV0_SCALE_CNTL, ov0_scale_cntl | (gamma << 5)); -+ else -+ OUTREG(RADEON_OV0_SCALE_CNTL, ov0_scale_cntl); ++ } /* Load gamma curve adjustments */ if (info->ChipFamily >= CHIP_FAMILY_R200) { -@@ -957,8 +968,8 @@ static void RADEONSetTransform (ScrnInfoPtr pScrn, +@@ -931,6 +941,30 @@ RADEONSetOverlayGamma(ScrnInfoPtr pScrn, CARD32 gamma) + + } + ++static uint32_t ++RADEONTranslateUserGamma(uint32_t user_gamma) ++{ ++ /* translate from user_gamma (gamma x 1000) to radeon gamma table index value */ ++ if (user_gamma <= 925) /* 0.85 */ ++ return 1; ++ else if (user_gamma <= 1050) /* 1.0 */ ++ return 0; ++ else if (user_gamma <= 1150) /* 1.1 */ ++ return 2; ++ else if (user_gamma <= 1325) /* 1.2 */ ++ return 3; ++ else if (user_gamma <= 1575) /* 1.45 */ ++ return 4; ++ else if (user_gamma <= 1950) /* 1.7 */ ++ return 5; ++ else if (user_gamma <= 2350) /* 2.2 */ ++ return 6; ++ else if (user_gamma > 2350) /* 2.5 */ ++ return 7; ++ else ++ return 0; ++} ++ + + /**************************************************************************** + * SetTransform * +@@ -957,8 +991,8 @@ static void RADEONSetTransform (ScrnInfoPtr pScrn, float red_intensity, float green_intensity, float blue_intensity, @@ -16832,7 +16982,7 @@ index 7502e1e..4a5d6e8 100644 { RADEONInfoPtr info = RADEONPTR(pScrn); unsigned char *RADEONMMIO = info->MMIO; -@@ -975,11 +986,11 @@ static void RADEONSetTransform (ScrnInfoPtr pScrn, +@@ -975,32 +1009,17 @@ static void RADEONSetTransform (ScrnInfoPtr pScrn, float Loff = 64.0; float Coff = 512.0f; @@ -16849,7 +16999,29 @@ index 7502e1e..4a5d6e8 100644 if (ref >= 2) return; -@@ -1143,16 +1154,16 @@ static void RADEONSetOverlayAlpha(ScrnInfoPtr pScrn, int ov_alpha, int gr_alpha, + + /* translate from user_gamma (gamma x 1000) to radeon gamma table index value */ +- if (user_gamma <= 925) /* 0.85 */ +- gamma = 1; +- else if (user_gamma <= 1050) /* 1.0 */ +- gamma = 0; +- else if (user_gamma <= 1150) /* 1.1 */ +- gamma = 2; +- else if (user_gamma <= 1325) /* 1.2 */ +- gamma = 3; +- else if (user_gamma <= 1575) /* 1.45 */ +- gamma = 4; +- else if (user_gamma <= 1950) /* 1.7 */ +- gamma = 5; +- else if (user_gamma <= 2350) /* 2.2 */ +- gamma = 6; +- else if (user_gamma > 2350) /* 2.5 */ +- gamma = 7; ++ gamma = RADEONTranslateUserGamma(user_gamma); + + if (gamma >= 8) + return; +@@ -1143,16 +1162,16 @@ static void RADEONSetOverlayAlpha(ScrnInfoPtr pScrn, int ov_alpha, int gr_alpha, /* not yet supported */ } @@ -16870,7 +17042,7 @@ index 7502e1e..4a5d6e8 100644 rbits = (colorKey & pScrn->mask.red) >> pScrn->offset.red; gbits = (colorKey & pScrn->mask.green) >> pScrn->offset.green; -@@ -1164,7 +1175,7 @@ static void RADEONSetColorKey(ScrnInfoPtr pScrn, CARD32 colorKey) +@@ -1164,7 +1183,7 @@ static void RADEONSetColorKey(ScrnInfoPtr pScrn, CARD32 colorKey) } else { @@ -16879,7 +17051,7 @@ index 7502e1e..4a5d6e8 100644 bits = colorKey & ((1 << info->CurrentLayout.depth) - 1); r = bits; -@@ -1307,7 +1318,7 @@ static void RADEONSetupTheatre(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv) +@@ -1307,7 +1326,7 @@ static void RADEONSetupTheatre(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv) RADEONPLLPtr pll = &(info->pll); TheatrePtr t; @@ -16888,7 +17060,7 @@ index 7502e1e..4a5d6e8 100644 int i; pPriv->theatre = NULL; -@@ -1401,7 +1412,7 @@ RADEONAllocAdaptor(ScrnInfoPtr pScrn) +@@ -1401,7 +1420,7 @@ RADEONAllocAdaptor(ScrnInfoPtr pScrn) XF86VideoAdaptorPtr adapt; RADEONInfoPtr info = RADEONPTR(pScrn); RADEONPortPrivPtr pPriv; @@ -16897,7 +17069,7 @@ index 7502e1e..4a5d6e8 100644 int ecp; if(!(adapt = xf86XVAllocateVideoAdaptorRec(pScrn))) -@@ -2159,22 +2170,22 @@ RADEONCopyData( +@@ -2159,22 +2178,22 @@ RADEONCopyData( unsigned int bpp ){ RADEONInfoPtr info = RADEONPTR(pScrn); @@ -16929,7 +17101,7 @@ index 7502e1e..4a5d6e8 100644 RADEONHostDataParams( pScrn, dst, dstPitch, bpp, &dstPitchOff, &x, &y ); while ( (buf = RADEONHostDataBlit( pScrn, bpp, w, dstPitchOff, &bufPitch, -@@ -2235,21 +2246,21 @@ RADEONCopyRGB24Data( +@@ -2235,21 +2254,21 @@ RADEONCopyRGB24Data( unsigned int h, unsigned int w ){ @@ -16955,7 +17127,7 @@ index 7502e1e..4a5d6e8 100644 &bufPitch, x, &y, &h, &hpass )) ) { -@@ -2282,7 +2293,7 @@ RADEONCopyRGB24Data( +@@ -2282,7 +2301,7 @@ RADEONCopyRGB24Data( #endif for (j = 0; j < h; j++) { @@ -16964,7 +17136,7 @@ index 7502e1e..4a5d6e8 100644 sptr = src + j * srcPitch; for (i = 0; i < w; i++, sptr += 3) { -@@ -2333,8 +2344,8 @@ RADEONCopyMungedData( +@@ -2333,8 +2352,8 @@ RADEONCopyMungedData( if ( info->directRenderingEnabled && info->DMAForXv ) { @@ -16975,7 +17147,7 @@ index 7502e1e..4a5d6e8 100644 int blitX, blitY; unsigned int hpass; -@@ -2365,8 +2376,8 @@ RADEONCopyMungedData( +@@ -2365,8 +2384,8 @@ RADEONCopyMungedData( else #endif /* XF86DRI */ { @@ -16986,7 +17158,7 @@ index 7502e1e..4a5d6e8 100644 int i, j; #if X_BYTE_ORDER == X_BIG_ENDIAN -@@ -2420,7 +2431,7 @@ RADEONCopyMungedData( +@@ -2420,7 +2439,7 @@ RADEONCopyMungedData( * is measured in bytes, and the offset from the beginning of card space is * returned. */ @@ -16995,7 +17167,7 @@ index 7502e1e..4a5d6e8 100644 RADEONAllocateMemory( ScrnInfoPtr pScrn, void **mem_struct, -@@ -2542,7 +2553,7 @@ RADEONDisplayVideo( +@@ -2542,7 +2561,7 @@ RADEONDisplayVideo( RADEONInfoPtr info = RADEONPTR(pScrn); xf86CrtcConfigPtr xf86_config = XF86_CRTC_CONFIG_PTR(pScrn); unsigned char *RADEONMMIO = info->MMIO; @@ -17004,7 +17176,7 @@ index 7502e1e..4a5d6e8 100644 double h_inc_d; int p1_h_accum_init, p23_h_accum_init; int p1_v_accum_init, p23_v_accum_init; -@@ -2552,12 +2563,12 @@ RADEONDisplayVideo( +@@ -2552,12 +2571,12 @@ RADEONDisplayVideo( int y_mult; int x_off; int y_off; @@ -17020,7 +17192,18 @@ index 7502e1e..4a5d6e8 100644 double dsr; int tap_set; int predownscale=0; -@@ -2873,7 +2884,7 @@ RADEONDisplayVideo( +@@ -2867,13 +2886,18 @@ RADEONDisplayVideo( + break; + } + ++ if (info->ChipFamily < CHIP_FAMILY_R200) { ++ scale_cntl &= ~RADEON_SCALER_GAMMA_SEL_MASK; ++ scale_cntl |= ((RADEONTranslateUserGamma(pPriv->gamma)) << 5); ++ } ++ + OUTREG(RADEON_OV0_SCALE_CNTL, scale_cntl); + OUTREG(RADEON_OV0_REG_LOAD_CNTL, 0); + } static void @@ -17029,7 +17212,7 @@ index 7502e1e..4a5d6e8 100644 { #if HAVE_XV_DRAWABLE_HELPER xf86XVFillKeyHelperDrawable(pDraw, colorKey, clipBoxes); -@@ -2906,7 +2917,7 @@ RADEONPutImage( +@@ -2906,7 +2930,7 @@ RADEONPutImage( int top, left, npixels, nlines, bpp; int idconv = id; BoxRec dstBox; @@ -17038,7 +17221,7 @@ index 7502e1e..4a5d6e8 100644 xf86CrtcPtr crtc; /* -@@ -2979,7 +2990,8 @@ RADEONPutImage( +@@ -2979,7 +3003,8 @@ RADEONPutImage( case FOURCC_I420: /* it seems rs4xx chips (all of them???) either can't handle planar yuv at all or would need some unknown different setup. */ @@ -17048,7 +17231,7 @@ index 7502e1e..4a5d6e8 100644 /* need 16bytes alignment for u,v plane, so 2 times that for width but blitter needs 64bytes alignment. 128byte is a waste but dstpitch for uv planes needs to be dstpitch yplane >> 1 for now. */ -@@ -3462,7 +3474,7 @@ RADEONPutVideo( +@@ -3462,7 +3487,7 @@ RADEONPutVideo( int srcPitch, srcPitch2, dstPitch; int bpp; BoxRec dstBox; diff --git a/xorg-x11-drv-ati.spec b/xorg-x11-drv-ati.spec index 167a4bb..def08f1 100644 --- a/xorg-x11-drv-ati.spec +++ b/xorg-x11-drv-ati.spec @@ -5,7 +5,7 @@ Summary: Xorg X11 ati video driver Name: xorg-x11-drv-ati Version: 6.8.0 -Release: 17%{?dist} +Release: 18%{?dist} URL: http://www.x.org License: MIT Group: User Interface/X Hardware Support @@ -91,6 +91,9 @@ rm -rf $RPM_BUILD_ROOT %{_mandir}/man4/radeon.4* %changelog +* Thu Jun 26 2008 Dave Airlie 6.8.0-18 +- update to latest git 6.8.192 beta + * Wed May 28 2008 Dave Airlie 6.8.0-17 - fix multiple VT switch issues on r600 cards - assorted upstream goodness