diff --git a/.cvsignore b/.cvsignore index 6712842..468a78f 100644 --- a/.cvsignore +++ b/.cvsignore @@ -1 +1 @@ -xf86-video-ati-6.8.0.tar.bz2 +xf86-video-ati-6.9.0.tar.bz2 diff --git a/ati.xinf b/ati.xinf deleted file mode 100644 index b089297..0000000 --- a/ati.xinf +++ /dev/null @@ -1,39 +0,0 @@ -alias pcivideo:v00001002d00004158sv*sd*bc*sc*i* ati -alias pcivideo:v00001002d00004354sv*sd*bc*sc*i* ati -alias pcivideo:v00001002d00004358sv*sd*bc*sc*i* ati -alias pcivideo:v00001002d00004554sv*sd*bc*sc*i* ati -alias pcivideo:v00001002d00004654sv*sd*bc*sc*i* ati -alias pcivideo:v00001002d00004742sv*sd*bc*sc*i* ati -alias pcivideo:v00001002d00004744sv*sd*bc*sc*i* ati -alias pcivideo:v00001002d00004747sv*sd*bc*sc*i* ati -alias pcivideo:v00001002d00004749sv*sd*bc*sc*i* ati -alias pcivideo:v00001002d0000474Csv*sd*bc*sc*i* ati -alias pcivideo:v00001002d0000474Dsv*sd*bc*sc*i* ati -alias pcivideo:v00001002d0000474Esv*sd*bc*sc*i* ati -alias pcivideo:v00001002d0000474Fsv*sd*bc*sc*i* ati -alias pcivideo:v00001002d00004750sv*sd*bc*sc*i* ati -alias pcivideo:v00001002d00004751sv*sd*bc*sc*i* ati -alias pcivideo:v00001002d00004752sv*sd*bc*sc*i* ati -alias pcivideo:v00001002d00004753sv*sd*bc*sc*i* ati -alias pcivideo:v00001002d00004754sv*sd*bc*sc*i* ati -alias pcivideo:v00001002d00004755sv*sd*bc*sc*i* ati -alias pcivideo:v00001002d00004756sv*sd*bc*sc*i* ati -alias pcivideo:v00001002d00004757sv*sd*bc*sc*i* ati -alias pcivideo:v00001002d00004758sv*sd*bc*sc*i* ati -alias pcivideo:v00001002d00004759sv*sd*bc*sc*i* ati -alias pcivideo:v00001002d0000475Asv*sd*bc*sc*i* ati -alias pcivideo:v00001002d00004C42sv*sd*bc*sc*i* ati -alias pcivideo:v00001002d00004C44sv*sd*bc*sc*i* ati -alias pcivideo:v00001002d00004C47sv*sd*bc*sc*i* ati -alias pcivideo:v00001002d00004C49sv*sd*bc*sc*i* ati -alias pcivideo:v00001002d00004C4Dsv*sd*bc*sc*i* ati -alias pcivideo:v00001002d00004C4Esv*sd*bc*sc*i* ati -alias pcivideo:v00001002d00004C50sv*sd*bc*sc*i* ati -alias pcivideo:v00001002d00004C51sv*sd*bc*sc*i* ati -alias pcivideo:v00001002d00004C52sv*sd*bc*sc*i* ati -alias pcivideo:v00001002d00004C53sv*sd*bc*sc*i* ati -alias pcivideo:v00001002d00004C54sv*sd*bc*sc*i* ati -alias pcivideo:v00001002d00005354sv*sd*bc*sc*i* ati -alias pcivideo:v00001002d00005654sv*sd*bc*sc*i* ati -alias pcivideo:v00001002d00005655sv*sd*bc*sc*i* ati -alias pcivideo:v00001002d00005656sv*sd*bc*sc*i* ati diff --git a/import.log b/import.log new file mode 100644 index 0000000..191cc1f --- /dev/null +++ b/import.log @@ -0,0 +1 @@ +xorg-x11-drv-ati-6_9_0-1_fc10:HEAD:xorg-x11-drv-ati-6.9.0-1.fc10.src.rpm:1218428001 diff --git a/mach64-ia64-pagesize.patch b/mach64-ia64-pagesize.patch deleted file mode 100644 index 9ae2504..0000000 --- a/mach64-ia64-pagesize.patch +++ /dev/null @@ -1,54 +0,0 @@ -From 89a9ad75f3e50e25275b803617d5e74709ead269 Mon Sep 17 00:00:00 2001 -From: Yi Zhan -Date: Wed, 26 Mar 2008 16:13:08 +1000 -Subject: [PATCH] mach64: on IA64 systems the pciaccess page size mapping was getting E2BIG - -As the ia64 pagesize was 16k, and aperture was only 4k, this was messing up -on ia64 machines. - -Modified fix from RH BZ 438947 - airlied ---- - src/atividmem.c | 20 +++++++++++++++----- - 1 files changed, 15 insertions(+), 5 deletions(-) - -diff --git a/src/atividmem.c b/src/atividmem.c -index 986ac0f..8950f84 100644 ---- a/src/atividmem.c -+++ b/src/atividmem.c -@@ -146,7 +146,12 @@ ATIUnmapMMIO - #ifndef XSERVER_LIBPCIACCESS - xf86UnMapVidMem(iScreen, pATI->pMMIO, getpagesize()); - #else -- pci_device_unmap_range(pATI->PCIInfo, pATI->pMMIO, getpagesize()); -+ unsigned long size; -+ -+ size = PCI_REGION_SIZE(pATI->PCIInfo, 2); -+ if (!size || size > getpagesize()) -+ size = getpagesize(); -+ pci_device_unmap_range(pATI->PCIInfo, pATI->pMMIO, size); - #endif - } - -@@ -340,10 +345,15 @@ ATIMapApertures - - int mode = PCI_DEV_MAP_FLAG_WRITABLE; - -- int err = pci_device_map_range(pVideo, -- MMIOBase, -- PageSize, -- mode, &pATI->pMMIO); -+ int err; -+ int size; -+ -+ size = PCI_REGION_SIZE(pVideo, 2); -+ if (!size || size > PageSize) -+ size = PageSize; -+ -+ err = pci_device_map_range(pVideo, MMIOBase, -+ size, mode, &pATI->pMMIO); - - if (err) - { --- -1.5.4.4 - diff --git a/r128-bios-size.patch b/r128-bios-size.patch deleted file mode 100644 index ece3528..0000000 --- a/r128-bios-size.patch +++ /dev/null @@ -1,13 +0,0 @@ -diff -up xf86-video-ati-6.8.0/src/r128_driver.c.bios_size xf86-video-ati-6.8.0/src/r128_driver.c ---- xf86-video-ati-6.8.0/src/r128_driver.c.bios_size 2008-04-24 16:12:13.000000000 +1000 -+++ xf86-video-ati-6.8.0/src/r128_driver.c 2008-04-24 16:12:16.000000000 +1000 -@@ -490,7 +490,8 @@ static Bool R128GetBIOSParameters(ScrnIn - (info->VBIOS[(v) + 3] << 24)) - - #ifdef XSERVER_LIBPCIACCESS -- info->VBIOS = xalloc(info->PciInfo->rom_size); -+ int size = info->PciInfo->rom_size > R128_VBIOS_SIZE ? info->PciInfo->rom_size : R128_VBIOS_SIZE; -+ info->VBIOS = xalloc(size); - #else - info->VBIOS = xalloc(R128_VBIOS_SIZE); - #endif diff --git a/r128.xinf b/r128.xinf deleted file mode 100644 index 7101783..0000000 --- a/r128.xinf +++ /dev/null @@ -1,47 +0,0 @@ -alias pcivideo:v00001002d00004C45sv*sd*bc*sc*i* r128 -alias pcivideo:v00001002d00004C46sv*sd*bc*sc*i* r128 -alias pcivideo:v00001002d00004D46sv*sd*bc*sc*i* r128 -alias pcivideo:v00001002d00004D4Csv*sd*bc*sc*i* r128 -alias pcivideo:v00001002d00005041sv*sd*bc*sc*i* r128 -alias pcivideo:v00001002d00005042sv*sd*bc*sc*i* r128 -alias pcivideo:v00001002d00005043sv*sd*bc*sc*i* r128 -alias pcivideo:v00001002d00005044sv*sd*bc*sc*i* r128 -alias pcivideo:v00001002d00005045sv*sd*bc*sc*i* r128 -alias pcivideo:v00001002d00005046sv*sd*bc*sc*i* r128 -alias pcivideo:v00001002d00005047sv*sd*bc*sc*i* r128 -alias pcivideo:v00001002d00005048sv*sd*bc*sc*i* r128 -alias pcivideo:v00001002d00005049sv*sd*bc*sc*i* r128 -alias pcivideo:v00001002d0000504Asv*sd*bc*sc*i* r128 -alias pcivideo:v00001002d0000504Bsv*sd*bc*sc*i* r128 -alias pcivideo:v00001002d0000504Csv*sd*bc*sc*i* r128 -alias pcivideo:v00001002d0000504Dsv*sd*bc*sc*i* r128 -alias pcivideo:v00001002d0000504Esv*sd*bc*sc*i* r128 -alias pcivideo:v00001002d0000504Fsv*sd*bc*sc*i* r128 -alias pcivideo:v00001002d00005050sv*sd*bc*sc*i* r128 -alias pcivideo:v00001002d00005051sv*sd*bc*sc*i* r128 -alias pcivideo:v00001002d00005052sv*sd*bc*sc*i* r128 -alias pcivideo:v00001002d00005053sv*sd*bc*sc*i* r128 -alias pcivideo:v00001002d00005054sv*sd*bc*sc*i* r128 -alias pcivideo:v00001002d00005055sv*sd*bc*sc*i* r128 -alias pcivideo:v00001002d00005056sv*sd*bc*sc*i* r128 -alias pcivideo:v00001002d00005057sv*sd*bc*sc*i* r128 -alias pcivideo:v00001002d00005058sv*sd*bc*sc*i* r128 -alias pcivideo:v00001002d00005245sv*sd*bc*sc*i* r128 -alias pcivideo:v00001002d00005246sv*sd*bc*sc*i* r128 -alias pcivideo:v00001002d00005247sv*sd*bc*sc*i* r128 -alias pcivideo:v00001002d0000524Bsv*sd*bc*sc*i* r128 -alias pcivideo:v00001002d0000524Csv*sd*bc*sc*i* r128 -alias pcivideo:v00001002d00005345sv*sd*bc*sc*i* r128 -alias pcivideo:v00001002d00005346sv*sd*bc*sc*i* r128 -alias pcivideo:v00001002d00005347sv*sd*bc*sc*i* r128 -alias pcivideo:v00001002d00005348sv*sd*bc*sc*i* r128 -alias pcivideo:v00001002d0000534Bsv*sd*bc*sc*i* r128 -alias pcivideo:v00001002d0000534Csv*sd*bc*sc*i* r128 -alias pcivideo:v00001002d0000534Dsv*sd*bc*sc*i* r128 -alias pcivideo:v00001002d0000534Esv*sd*bc*sc*i* r128 -alias pcivideo:v00001002d00005446sv*sd*bc*sc*i* r128 -alias pcivideo:v00001002d0000544Csv*sd*bc*sc*i* r128 -alias pcivideo:v00001002d00005452sv*sd*bc*sc*i* r128 -alias pcivideo:v00001002d00005453sv*sd*bc*sc*i* r128 -alias pcivideo:v00001002d00005454sv*sd*bc*sc*i* r128 -alias pcivideo:v00001002d00005455sv*sd*bc*sc*i* r128 diff --git a/radeon-6.7.196-faster-ddc.patch b/radeon-6.7.196-faster-ddc.patch deleted file mode 100644 index dfb1c71..0000000 --- a/radeon-6.7.196-faster-ddc.patch +++ /dev/null @@ -1,67 +0,0 @@ -diff -up xf86-video-ati-6.7.196/src/radeon_output.c.jx xf86-video-ati-6.7.196/src/radeon_output.c ---- xf86-video-ati-6.7.196/src/radeon_output.c.jx 2007-11-14 15:21:22.000000000 -0500 -+++ xf86-video-ati-6.7.196/src/radeon_output.c 2007-11-14 15:22:39.000000000 -0500 -@@ -278,62 +278,7 @@ RADEONDisplayDDCConnected(ScrnInfoPtr pS - DDCReg = radeon_output->DDCReg; - - /* Read and output monitor info using DDC2 over I2C bus */ -- if (radeon_output->pI2CBus && info->ddc2 && (DDCReg != RADEON_LCD_GPIO_MASK) && (DDCReg != RADEON_MDGPIO_EN_REG)) { -- OUTREG(DDCReg, INREG(DDCReg) & -- (CARD32)~(RADEON_GPIO_A_0 | RADEON_GPIO_A_1)); -- -- /* For some old monitors (like Compaq Presario FP500), we need -- * following process to initialize/stop DDC -- */ -- OUTREG(DDCReg, INREG(DDCReg) & ~(RADEON_GPIO_EN_1)); -- for (j = 0; j < 3; j++) { -- OUTREG(DDCReg, -- INREG(DDCReg) & ~(RADEON_GPIO_EN_0)); -- usleep(13000); -- -- OUTREG(DDCReg, -- INREG(DDCReg) & ~(RADEON_GPIO_EN_1)); -- for (i = 0; i < 10; i++) { -- usleep(15000); -- if (INREG(DDCReg) & RADEON_GPIO_Y_1) -- break; -- } -- if (i == 10) continue; -- -- usleep(15000); -- -- OUTREG(DDCReg, INREG(DDCReg) | RADEON_GPIO_EN_0); -- usleep(15000); -- -- OUTREG(DDCReg, INREG(DDCReg) | RADEON_GPIO_EN_1); -- usleep(15000); -- OUTREG(DDCReg, -- INREG(DDCReg) & ~(RADEON_GPIO_EN_0)); -- usleep(15000); -- -- MonInfo = xf86OutputGetEDID(output, radeon_output->pI2CBus); -- -- OUTREG(DDCReg, INREG(DDCReg) | RADEON_GPIO_EN_1); -- OUTREG(DDCReg, INREG(DDCReg) | RADEON_GPIO_EN_0); -- usleep(15000); -- OUTREG(DDCReg, -- INREG(DDCReg) & ~(RADEON_GPIO_EN_1)); -- for (i = 0; i < 5; i++) { -- usleep(15000); -- if (INREG(DDCReg) & RADEON_GPIO_Y_1) -- break; -- } -- usleep(15000); -- OUTREG(DDCReg, -- INREG(DDCReg) & ~(RADEON_GPIO_EN_0)); -- usleep(15000); -- -- OUTREG(DDCReg, INREG(DDCReg) | RADEON_GPIO_EN_1); -- OUTREG(DDCReg, INREG(DDCReg) | RADEON_GPIO_EN_0); -- usleep(15000); -- if (MonInfo) break; -- } -- } else if (radeon_output->pI2CBus && info->ddc2 && ((DDCReg == RADEON_LCD_GPIO_MASK) || (DDCReg == RADEON_MDGPIO_EN_REG))) { -+ if (radeon_output->pI2CBus && info->ddc2) { - MonInfo = xf86OutputGetEDID(output, radeon_output->pI2CBus); - } else { - xf86DrvMsg(pScrn->scrnIndex, X_WARNING, "DDC2/I2C is not properly initialized\n"); diff --git a/radeon-6.9.0-to-git.patch b/radeon-6.9.0-to-git.patch new file mode 100644 index 0000000..c789d91 --- /dev/null +++ b/radeon-6.9.0-to-git.patch @@ -0,0 +1,4271 @@ +diff --git a/src/AtomBios/CD_Operations.c b/src/AtomBios/CD_Operations.c +index 509aa0c..58c4ae9 100644 +--- a/src/AtomBios/CD_Operations.c ++++ b/src/AtomBios/CD_Operations.c +@@ -44,7 +44,6 @@ Revision History: + #include "xorg-server.h" + + #include "Decoder.h" +-#include "atombios.h" + + VOID PutDataRegister(PARSER_TEMP_DATA STACK_BASED * pParserTempData); + VOID PutDataPS(PARSER_TEMP_DATA STACK_BASED * pParserTempData); +@@ -231,7 +230,7 @@ UINT32 IndirectInputOutput(PARSER_TEMP_DATA STACK_BASED * pParserTempData) + IndirectIOParserCommands[*pParserTempData->IndirectIOTablePointer].func(pParserTempData); + pParserTempData->IndirectIOTablePointer+=IndirectIOParserCommands[*pParserTempData->IndirectIOTablePointer].csize; + } +- pParserTempData->IndirectIOTablePointer-=*(UINT16*)(pParserTempData->IndirectIOTablePointer+1); ++ pParserTempData->IndirectIOTablePointer-=UINT16LE_TO_CPU(*(UINT16*)(pParserTempData->IndirectIOTablePointer+1)); + pParserTempData->IndirectIOTablePointer++; + return pParserTempData->IndirectData; + } else pParserTempData->IndirectIOTablePointer+=IndirectIOParserCommands[*pParserTempData->IndirectIOTablePointer].csize; +@@ -243,7 +242,7 @@ UINT32 IndirectInputOutput(PARSER_TEMP_DATA STACK_BASED * pParserTempData) + + VOID PutDataRegister(PARSER_TEMP_DATA STACK_BASED * pParserTempData) + { +- pParserTempData->Index=(UINT32)pParserTempData->pCmd->Parameters.WordXX.PA_Destination; ++ pParserTempData->Index=(UINT32)UINT16LE_TO_CPU(pParserTempData->pCmd->Parameters.WordXX.PA_Destination); + pParserTempData->Index+=pParserTempData->CurrentRegBlock; + switch(pParserTempData->Multipurpose.CurrentPort){ + case ATI_RegsPort: +@@ -269,16 +268,16 @@ VOID PutDataRegister(PARSER_TEMP_DATA STACK_BASED * pParserTempData) + VOID PutDataPS(PARSER_TEMP_DATA STACK_BASED * pParserTempData) + { + *(pParserTempData->pDeviceData->pParameterSpace+pParserTempData->pCmd->Parameters.ByteXX.PA_Destination)= +- pParserTempData->DestData32; ++ CPU_TO_UINT32LE(pParserTempData->DestData32); + } + + VOID PutDataWS(PARSER_TEMP_DATA STACK_BASED * pParserTempData) + { + if (pParserTempData->pCmd->Parameters.ByteXX.PA_Destination < WS_QUOTIENT_C) +- *(pParserTempData->pWorkingTableData->pWorkSpace+pParserTempData->pCmd->Parameters.ByteXX.PA_Destination) = pParserTempData->DestData32; ++ *(pParserTempData->pWorkingTableData->pWorkSpace+pParserTempData->pCmd->Parameters.ByteXX.PA_Destination) = pParserTempData->DestData32; + else +- switch (pParserTempData->pCmd->Parameters.ByteXX.PA_Destination) +- { ++ switch (pParserTempData->pCmd->Parameters.ByteXX.PA_Destination) ++ { + case WS_REMINDER_C: + pParserTempData->MultiplicationOrDivision.Division.Reminder32=pParserTempData->DestData32; + break; +@@ -339,7 +338,7 @@ VOID SkipParameters16(PARSER_TEMP_DATA STACK_BASED * pParserTempData) + + UINT32 GetParametersRegister(PARSER_TEMP_DATA STACK_BASED * pParserTempData) + { +- pParserTempData->Index=*(UINT16*)pParserTempData->pWorkingTableData->IP; ++ pParserTempData->Index=UINT16LE_TO_CPU(*(UINT16*)pParserTempData->pWorkingTableData->IP); + pParserTempData->pWorkingTableData->IP+=sizeof(UINT16); + pParserTempData->Index+=pParserTempData->CurrentRegBlock; + switch(pParserTempData->Multipurpose.CurrentPort) +@@ -361,9 +360,11 @@ UINT32 GetParametersRegister(PARSER_TEMP_DATA STACK_BASED * pParserTempData) + + UINT32 GetParametersPS(PARSER_TEMP_DATA STACK_BASED * pParserTempData) + { ++ UINT32 data; + pParserTempData->Index=*pParserTempData->pWorkingTableData->IP; + pParserTempData->pWorkingTableData->IP+=sizeof(UINT8); +- return *(pParserTempData->pDeviceData->pParameterSpace+pParserTempData->Index); ++ data = UINT32LE_TO_CPU(*(pParserTempData->pDeviceData->pParameterSpace+pParserTempData->Index)); ++ return data; + } + + UINT32 GetParametersWS(PARSER_TEMP_DATA STACK_BASED * pParserTempData) +@@ -419,9 +420,12 @@ UINT32 GetParametersMC(PARSER_TEMP_DATA STACK_BASED * pParserTempData) + + UINT32 GetParametersIndirect(PARSER_TEMP_DATA STACK_BASED * pParserTempData) + { +- pParserTempData->Index=*(UINT16*)pParserTempData->pWorkingTableData->IP; ++ UINT32 ret; ++ ++ pParserTempData->Index=UINT16LE_TO_CPU(*(UINT16*)pParserTempData->pWorkingTableData->IP); + pParserTempData->pWorkingTableData->IP+=sizeof(UINT16); +- return *(UINT32*)(RELATIVE_TO_BIOS_IMAGE(pParserTempData->Index)+pParserTempData->CurrentDataBlock); ++ ret = UINT32LE_TO_CPU(*(UINT32*)(RELATIVE_TO_BIOS_IMAGE(pParserTempData->Index)+pParserTempData->CurrentDataBlock)); ++ return ret; + } + + UINT32 GetParametersDirect8(PARSER_TEMP_DATA STACK_BASED * pParserTempData) +@@ -435,7 +439,7 @@ UINT32 GetParametersDirect8(PARSER_TEMP_DATA STACK_BASED * pParserTempData) + UINT32 GetParametersDirect16(PARSER_TEMP_DATA STACK_BASED * pParserTempData) + { + pParserTempData->CD_Mask.SrcAlignment=alignmentLowerWord; +- pParserTempData->Index=*(UINT16*)pParserTempData->pWorkingTableData->IP; ++ pParserTempData->Index=UINT16LE_TO_CPU(*(UINT16*)pParserTempData->pWorkingTableData->IP); + pParserTempData->pWorkingTableData->IP+=sizeof(UINT16); + return pParserTempData->Index; + } +@@ -443,7 +447,7 @@ UINT32 GetParametersDirect16(PARSER_TEMP_DATA STACK_BASED * pParserTempData) + UINT32 GetParametersDirect32(PARSER_TEMP_DATA STACK_BASED * pParserTempData) + { + pParserTempData->CD_Mask.SrcAlignment=alignmentDword; +- pParserTempData->Index=*(UINT32*)pParserTempData->pWorkingTableData->IP; ++ pParserTempData->Index=UINT32LE_TO_CPU(*(UINT32*)pParserTempData->pWorkingTableData->IP); + pParserTempData->pWorkingTableData->IP+=sizeof(UINT32); + return pParserTempData->Index; + } +@@ -474,7 +478,7 @@ VOID ProcessMove(PARSER_TEMP_DATA STACK_BASED * pParserTempData) + { + if (pParserTempData->CD_Mask.SrcAlignment!=alignmentDword) + { +- pParserTempData->DestData32=GetDestination[pParserTempData->ParametersType.Destination](pParserTempData); ++ pParserTempData->DestData32=GetDestination[pParserTempData->ParametersType.Destination](pParserTempData); + } else + { + SkipDestination[pParserTempData->ParametersType.Destination](pParserTempData); +@@ -664,7 +668,8 @@ VOID ProcessSwitch(PARSER_TEMP_DATA STACK_BASED * pParserTempData){ + pParserTempData->SourceData32=GetSource[pParserTempData->ParametersType.Source](pParserTempData); + pParserTempData->SourceData32 >>= SourceAlignmentShift[pParserTempData->CD_Mask.SrcAlignment]; + pParserTempData->SourceData32 &= AlignmentMask[pParserTempData->CD_Mask.SrcAlignment]; +- while ( *(UINT16*)pParserTempData->pWorkingTableData->IP != (((UINT16)NOP_OPCODE << 8)+NOP_OPCODE)) ++ ++ while ( UINT16LE_TO_CPU(*(UINT16*)pParserTempData->pWorkingTableData->IP) != (((UINT16)NOP_OPCODE << 8)+NOP_OPCODE)) + { + if (*pParserTempData->pWorkingTableData->IP == 'c') + { +@@ -673,7 +678,7 @@ VOID ProcessSwitch(PARSER_TEMP_DATA STACK_BASED * pParserTempData){ + pParserTempData->Index=GetParametersDirect16(pParserTempData); + if (pParserTempData->SourceData32 == pParserTempData->DestData32) + { +- pParserTempData->pWorkingTableData->IP= RELATIVE_TO_TABLE(pParserTempData->Index); ++ pParserTempData->pWorkingTableData->IP= RELATIVE_TO_TABLE(pParserTempData->Index); + return; + } + } +@@ -695,7 +700,7 @@ VOID cmdSetDataBlock(PARSER_TEMP_DATA STACK_BASED * pParserTempData) + } else + { + pMasterDataTable = GetDataMasterTablePointer(pParserTempData->pDeviceData); +- pParserTempData->CurrentDataBlock= (TABLE_UNIT_TYPE)((PTABLE_UNIT_TYPE)pMasterDataTable)[value]; ++ pParserTempData->CurrentDataBlock= UINT16LE_TO_CPU((TABLE_UNIT_TYPE)((PTABLE_UNIT_TYPE)pMasterDataTable)[value]); + } + } + pParserTempData->pWorkingTableData->IP+=sizeof(COMMAND_TYPE_OPCODE_VALUE_BYTE); +@@ -704,13 +709,13 @@ VOID cmdSetDataBlock(PARSER_TEMP_DATA STACK_BASED * pParserTempData) + VOID cmdSet_ATI_Port(PARSER_TEMP_DATA STACK_BASED * pParserTempData) + { + pParserTempData->Multipurpose.CurrentPort=ATI_RegsPort; +- pParserTempData->CurrentPortID = (UINT8)((COMMAND_TYPE_1*)pParserTempData->pWorkingTableData->IP)->Parameters.WordXX.PA_Destination; ++ pParserTempData->CurrentPortID = (UINT8)UINT16LE_TO_CPU(((COMMAND_TYPE_1*)pParserTempData->pWorkingTableData->IP)->Parameters.WordXX.PA_Destination); + pParserTempData->pWorkingTableData->IP+=sizeof(COMMAND_TYPE_OPCODE_OFFSET16); + } + + VOID cmdSet_Reg_Block(PARSER_TEMP_DATA STACK_BASED * pParserTempData) + { +- pParserTempData->CurrentRegBlock = ((COMMAND_TYPE_1*)pParserTempData->pWorkingTableData->IP)->Parameters.WordXX.PA_Destination; ++ pParserTempData->CurrentRegBlock = UINT16LE_TO_CPU(((COMMAND_TYPE_1*)pParserTempData->pWorkingTableData->IP)->Parameters.WordXX.PA_Destination); + pParserTempData->pWorkingTableData->IP+=sizeof(COMMAND_TYPE_OPCODE_OFFSET16); + } + +@@ -754,19 +759,23 @@ VOID ProcessDebug(PARSER_TEMP_DATA STACK_BASED * pParserTempData) + + VOID ProcessDS(PARSER_TEMP_DATA STACK_BASED * pParserTempData) + { +- pParserTempData->pWorkingTableData->IP+=((COMMAND_TYPE_1*)pParserTempData->pWorkingTableData->IP)->Parameters.WordXX.PA_Destination+sizeof(COMMAND_TYPE_OPCODE_OFFSET16); ++ pParserTempData->pWorkingTableData->IP+=UINT16LE_TO_CPU(((COMMAND_TYPE_1*)pParserTempData->pWorkingTableData->IP)->Parameters.WordXX.PA_Destination)+sizeof(COMMAND_TYPE_OPCODE_OFFSET16); + } + + +-VOID cmdCall_Table(PARSER_TEMP_DATA STACK_BASED * pParserTempData){ ++VOID cmdCall_Table(PARSER_TEMP_DATA STACK_BASED * pParserTempData) ++{ + UINT16* MasterTableOffset; + pParserTempData->pWorkingTableData->IP+=sizeof(COMMAND_TYPE_OPCODE_VALUE_BYTE); + MasterTableOffset = GetCommandMasterTablePointer(pParserTempData->pDeviceData); + if(((PTABLE_UNIT_TYPE)MasterTableOffset)[((COMMAND_TYPE_OPCODE_VALUE_BYTE*)pParserTempData->pCmd)->Value]!=0 ) // if the offset is not ZERO + { ++ ATOM_TABLE_ATTRIBUTE lTableAttr; ++ + pParserTempData->CommandSpecific.IndexInMasterTable=GetTrueIndexInMasterTable(pParserTempData,((COMMAND_TYPE_OPCODE_VALUE_BYTE*)pParserTempData->pCmd)->Value); +- pParserTempData->Multipurpose.PS_SizeInDwordsUsedByCallingTable = +- (((ATOM_COMMON_ROM_COMMAND_TABLE_HEADER *)pParserTempData->pWorkingTableData->pTableHead)->TableAttribute.PS_SizeInBytes>>2); ++ ++ lTableAttr = GetCommandTableAttribute(pParserTempData->pWorkingTableData->pTableHead); ++ pParserTempData->Multipurpose.PS_SizeInDwordsUsedByCallingTable = (lTableAttr.PS_SizeInBytes >>2); + pParserTempData->pDeviceData->pParameterSpace+= + pParserTempData->Multipurpose.PS_SizeInDwordsUsedByCallingTable; + pParserTempData->Status=CD_CALL_TABLE; +@@ -792,7 +801,7 @@ VOID ProcessJump(PARSER_TEMP_DATA STACK_BASED * pParserTempData) + (pParserTempData->ParametersType.Destination == pParserTempData->CompareFlags )) + { + +- pParserTempData->pWorkingTableData->IP= RELATIVE_TO_TABLE(((COMMAND_TYPE_OPCODE_OFFSET16*)pParserTempData->pWorkingTableData->IP)->CD_Offset16); ++ pParserTempData->pWorkingTableData->IP= RELATIVE_TO_TABLE(UINT16LE_TO_CPU(((COMMAND_TYPE_OPCODE_OFFSET16*)pParserTempData->pWorkingTableData->IP)->CD_Offset16)); + } else + { + pParserTempData->pWorkingTableData->IP+=sizeof(COMMAND_TYPE_OPCODE_OFFSET16); +@@ -805,7 +814,7 @@ VOID ProcessJumpE(PARSER_TEMP_DATA STACK_BASED * pParserTempData) + (pParserTempData->CompareFlags == pParserTempData->ParametersType.Destination)) + { + +- pParserTempData->pWorkingTableData->IP= RELATIVE_TO_TABLE(((COMMAND_TYPE_OPCODE_OFFSET16*)pParserTempData->pWorkingTableData->IP)->CD_Offset16); ++ pParserTempData->pWorkingTableData->IP= RELATIVE_TO_TABLE(UINT16LE_TO_CPU(((COMMAND_TYPE_OPCODE_OFFSET16*)pParserTempData->pWorkingTableData->IP)->CD_Offset16)); + } else + { + pParserTempData->pWorkingTableData->IP+=sizeof(COMMAND_TYPE_OPCODE_OFFSET16); +@@ -817,7 +826,7 @@ VOID ProcessJumpNE(PARSER_TEMP_DATA STACK_BASED * pParserTempData) + if (pParserTempData->CompareFlags != Equal) + { + +- pParserTempData->pWorkingTableData->IP= RELATIVE_TO_TABLE(((COMMAND_TYPE_OPCODE_OFFSET16*)pParserTempData->pWorkingTableData->IP)->CD_Offset16); ++ pParserTempData->pWorkingTableData->IP= RELATIVE_TO_TABLE(UINT16LE_TO_CPU(((COMMAND_TYPE_OPCODE_OFFSET16*)pParserTempData->pWorkingTableData->IP)->CD_Offset16)); + } else + { + pParserTempData->pWorkingTableData->IP+=sizeof(COMMAND_TYPE_OPCODE_OFFSET16); +diff --git a/src/AtomBios/Decoder.c b/src/AtomBios/Decoder.c +index e8b3b6e..73aac94 100644 +--- a/src/AtomBios/Decoder.c ++++ b/src/AtomBios/Decoder.c +@@ -40,12 +40,9 @@ Revision History: + #endif + + #include +- ++#include "xorg-server.h" + + #include "Decoder.h" +-#include "atombios.h" +-#include "CD_binding.h" +-#include "CD_Common_Types.h" + + #ifndef DISABLE_EASF + #include "easf.h" +@@ -77,13 +74,13 @@ UINT16* GetCommandMasterTablePointer(DEVICE_DATA STACK_BASED* pDeviceData) + /* + make MasterTableOffset point to EASF_ASIC_SETUP_TABLE structure, including usSize. + */ +- MasterTableOffset = (UINT16 *) (pDeviceData->pBIOS_Image+((EASF_ASIC_DESCRIPTOR*)pDeviceData->pBIOS_Image)->usAsicSetupTable_Offset); ++ MasterTableOffset = (UINT16 *) (pDeviceData->pBIOS_Image+(UINT16LE_TO_CPU(((EASF_ASIC_DESCRIPTOR*)pDeviceData->pBIOS_Image)->usAsicSetupTable_Offset)); + } else + #endif + { + #ifndef UEFI_BUILD +- MasterTableOffset = (UINT16 *)(*(UINT16 *)(pDeviceData->pBIOS_Image+OFFSET_TO_POINTER_TO_ATOM_ROM_HEADER) + pDeviceData->pBIOS_Image); +- MasterTableOffset = (UINT16 *)((ULONG)((ATOM_ROM_HEADER *)MasterTableOffset)->usMasterCommandTableOffset + pDeviceData->pBIOS_Image ); ++ MasterTableOffset = (UINT16 *)(UINT16LE_TO_CPU(*(UINT16 *)(pDeviceData->pBIOS_Image+OFFSET_TO_POINTER_TO_ATOM_ROM_HEADER)) + pDeviceData->pBIOS_Image); ++ MasterTableOffset = (UINT16 *)((ULONG)UINT16LE_TO_CPU(((ATOM_ROM_HEADER *)MasterTableOffset)->usMasterCommandTableOffset) + pDeviceData->pBIOS_Image ); + MasterTableOffset =(UINT16 *) &(((ATOM_MASTER_COMMAND_TABLE *)MasterTableOffset)->ListOfCommandTables); + #else + MasterTableOffset = (UINT16 *)(&(GetCommandMasterTable( )->ListOfCommandTables)); +@@ -97,8 +94,8 @@ UINT16* GetDataMasterTablePointer(DEVICE_DATA STACK_BASED* pDeviceData) + UINT16 *MasterTableOffset; + + #ifndef UEFI_BUILD +- MasterTableOffset = (UINT16 *)(*(UINT16 *)(pDeviceData->pBIOS_Image+OFFSET_TO_POINTER_TO_ATOM_ROM_HEADER) + pDeviceData->pBIOS_Image); +- MasterTableOffset = (UINT16 *)((ULONG)((ATOM_ROM_HEADER *)MasterTableOffset)->usMasterDataTableOffset + pDeviceData->pBIOS_Image ); ++ MasterTableOffset = (UINT16 *)(UINT16LE_TO_CPU(*(UINT16 *)(pDeviceData->pBIOS_Image+OFFSET_TO_POINTER_TO_ATOM_ROM_HEADER)) + pDeviceData->pBIOS_Image); ++ MasterTableOffset = (UINT16 *)((ULONG)(UINT16LE_TO_CPU(((ATOM_ROM_HEADER *)MasterTableOffset)->usMasterDataTableOffset)) + pDeviceData->pBIOS_Image ); + MasterTableOffset =(UINT16 *) &(((ATOM_MASTER_DATA_TABLE *)MasterTableOffset)->ListOfDataTables); + #else + MasterTableOffset = (UINT16 *)(&(GetDataMasterTable( )->ListOfDataTables)); +@@ -129,11 +126,29 @@ UINT8 GetTrueIndexInMasterTable(PARSER_TEMP_DATA STACK_BASED * pParserTempData, + } + } + ++ATOM_TABLE_ATTRIBUTE GetCommandTableAttribute(UINT8 *pTableHeader) ++{ ++ ATOM_TABLE_ATTRIBUTE_ACCESS lTableAccess; ++ ++ /* It's unclear whether this union trick breaks C aliasing rules, ++ * however, it's explicitely permitted by gcc, and we have other ++ * case where the code relies on a union being accessed by either ++ * of the "ways" and stay consistent so if a compiler breaks this ++ * assumption, it will probably need us to compile without strict ++ * aliasing enforcement ++ */ ++ lTableAccess.sbfAccess = ((ATOM_COMMON_ROM_COMMAND_TABLE_HEADER *)pTableHeader)->TableAttribute; ++ lTableAccess.susAccess = UINT16LE_TO_CPU(lTableAccess.susAccess); ++ ++ return lTableAccess.sbfAccess; ++} ++ + CD_STATUS ParseTable(DEVICE_DATA STACK_BASED* pDeviceData, UINT8 IndexInMasterTable) + { + PARSER_TEMP_DATA ParserTempData; + WORKING_TABLE_DATA STACK_BASED* prevWorkingTableData; + ++ memset(&ParserTempData, 0, sizeof(PARSER_TEMP_DATA)); + ParserTempData.pDeviceData=(DEVICE_DATA*)pDeviceData; + #ifndef DISABLE_EASF + if (pDeviceData->format == TABLE_FORMAT_EASF) +@@ -143,7 +158,7 @@ CD_STATUS ParseTable(DEVICE_DATA STACK_BASED* pDeviceData, UINT8 IndexInMasterTa + #endif + { + ParserTempData.pCmd=(GENERIC_ATTRIBUTE_COMMAND*)GetDataMasterTablePointer(pDeviceData); +- ParserTempData.IndirectIOTablePointer=(UINT8*)((ULONG)(((PTABLE_UNIT_TYPE)ParserTempData.pCmd)[INDIRECT_IO_TABLE]) + pDeviceData->pBIOS_Image); ++ ParserTempData.IndirectIOTablePointer=(UINT8*)((ULONG)(UINT16LE_TO_CPU(((PTABLE_UNIT_TYPE)ParserTempData.pCmd)[INDIRECT_IO_TABLE])) + pDeviceData->pBIOS_Image); + ParserTempData.IndirectIOTablePointer+=sizeof(ATOM_COMMON_TABLE_HEADER); + } + +@@ -160,65 +175,66 @@ CD_STATUS ParseTable(DEVICE_DATA STACK_BASED* pDeviceData, UINT8 IndexInMasterTa + ParserTempData.Status=CD_CALL_TABLE; + + do{ +- ++ + if (ParserTempData.Status==CD_CALL_TABLE) +- { ++ { + IndexInMasterTable=ParserTempData.CommandSpecific.IndexInMasterTable; + if(((PTABLE_UNIT_TYPE)ParserTempData.pCmd)[IndexInMasterTable]!=0) // if the offset is not ZERO +- { ++ { ++ ATOM_TABLE_ATTRIBUTE lTableAttr; ++ lTableAttr = GetCommandTableAttribute(UINT16LE_TO_CPU(((PTABLE_UNIT_TYPE)ParserTempData.pCmd)[IndexInMasterTable])+pDeviceData->pBIOS_Image); + #ifndef UEFI_BUILD + ParserTempData.pWorkingTableData =(WORKING_TABLE_DATA STACK_BASED*) AllocateWorkSpace(pDeviceData, +- ((ATOM_COMMON_ROM_COMMAND_TABLE_HEADER*)(((PTABLE_UNIT_TYPE)ParserTempData.pCmd)[IndexInMasterTable]+pDeviceData->pBIOS_Image))->TableAttribute.WS_SizeInBytes+sizeof(WORKING_TABLE_DATA)); ++ lTableAttr.WS_SizeInBytes+sizeof(WORKING_TABLE_DATA)); + #else +- ParserTempData.pWorkingTableData =(WORKING_TABLE_DATA STACK_BASED*) AllocateWorkSpace(pDeviceData, +- ((ATOM_COMMON_ROM_COMMAND_TABLE_HEADER*)(((PTABLE_UNIT_TYPE)ParserTempData.pCmd)[IndexInMasterTable]))->TableAttribute.WS_SizeInBytes+sizeof(WORKING_TABLE_DATA)); ++ ParserTempData.pWorkingTableData =(WORKING_TABLE_DATA STACK_BASED*) AllocateWorkSpace(pDeviceData, ++ lTableAttr.WS_SizeInBytes+sizeof(WORKING_TABLE_DATA)); + #endif +- if (ParserTempData.pWorkingTableData!=NULL) +- { +- ParserTempData.pWorkingTableData->pWorkSpace=(WORKSPACE_POINTER STACK_BASED*)((UINT8*)ParserTempData.pWorkingTableData+sizeof(WORKING_TABLE_DATA)); ++ if (ParserTempData.pWorkingTableData!=NULL) ++ { ++ ParserTempData.pWorkingTableData->pWorkSpace=(WORKSPACE_POINTER STACK_BASED*)((UINT8*)ParserTempData.pWorkingTableData+sizeof(WORKING_TABLE_DATA)); + #ifndef UEFI_BUILD +- ParserTempData.pWorkingTableData->pTableHead = (UINT8 *)(((PTABLE_UNIT_TYPE)ParserTempData.pCmd)[IndexInMasterTable]+pDeviceData->pBIOS_Image); ++ ParserTempData.pWorkingTableData->pTableHead = (UINT8 *)(UINT16LE_TO_CPU(((PTABLE_UNIT_TYPE)ParserTempData.pCmd)[IndexInMasterTable])+pDeviceData->pBIOS_Image); + #else +- ParserTempData.pWorkingTableData->pTableHead = (UINT8 *)(((PTABLE_UNIT_TYPE)ParserTempData.pCmd)[IndexInMasterTable]); ++ ParserTempData.pWorkingTableData->pTableHead = (UINT8 *)(UINT16LE_TO_CPU(((PTABLE_UNIT_TYPE)ParserTempData.pCmd)[IndexInMasterTable])); + #endif +- ParserTempData.pWorkingTableData->IP=((UINT8*)ParserTempData.pWorkingTableData->pTableHead)+sizeof(ATOM_COMMON_ROM_COMMAND_TABLE_HEADER); +- ParserTempData.pWorkingTableData->prevWorkingTableData=prevWorkingTableData; +- prevWorkingTableData=ParserTempData.pWorkingTableData; +- ParserTempData.Status = CD_SUCCESS; +- } else ParserTempData.Status = CD_UNEXPECTED_BEHAVIOR; +- } else ParserTempData.Status = CD_EXEC_TABLE_NOT_FOUND; ++ ParserTempData.pWorkingTableData->IP=((UINT8*)ParserTempData.pWorkingTableData->pTableHead)+sizeof(ATOM_COMMON_ROM_COMMAND_TABLE_HEADER); ++ ParserTempData.pWorkingTableData->prevWorkingTableData=prevWorkingTableData; ++ prevWorkingTableData=ParserTempData.pWorkingTableData; ++ ParserTempData.Status = CD_SUCCESS; ++ } else ParserTempData.Status = CD_UNEXPECTED_BEHAVIOR; ++ } else ParserTempData.Status = CD_EXEC_TABLE_NOT_FOUND; + } + if (!CD_ERROR(ParserTempData.Status)) + { +- ParserTempData.Status = CD_SUCCESS; ++ ParserTempData.Status = CD_SUCCESS; + while (!CD_ERROR_OR_COMPLETED(ParserTempData.Status)) +- { +- ++ { + if (IS_COMMAND_VALID(((COMMAND_HEADER*)ParserTempData.pWorkingTableData->IP)->Opcode)) +- { ++ { + ParserTempData.pCmd = (GENERIC_ATTRIBUTE_COMMAND*)ParserTempData.pWorkingTableData->IP; +- ++ + if (IS_END_OF_TABLE(((COMMAND_HEADER*)ParserTempData.pWorkingTableData->IP)->Opcode)) + { + ParserTempData.Status=CD_COMPLETED; +- prevWorkingTableData=ParserTempData.pWorkingTableData->prevWorkingTableData; +- ++ prevWorkingTableData=ParserTempData.pWorkingTableData->prevWorkingTableData; ++ + FreeWorkSpace(pDeviceData, ParserTempData.pWorkingTableData); +- ParserTempData.pWorkingTableData=prevWorkingTableData; +- if (prevWorkingTableData!=NULL) +- { +- ParserTempData.pDeviceData->pParameterSpace-= +- (((ATOM_COMMON_ROM_COMMAND_TABLE_HEADER*)ParserTempData.pWorkingTableData-> +- pTableHead)->TableAttribute.PS_SizeInBytes>>2); +- } +- // if there is a parent table where to return, then restore PS_pointer to the original state ++ ParserTempData.pWorkingTableData=prevWorkingTableData; ++ if (prevWorkingTableData!=NULL) ++ { ++ ATOM_TABLE_ATTRIBUTE lTableAttr; ++ lTableAttr = GetCommandTableAttribute(ParserTempData.pWorkingTableData->pTableHead); ++ ParserTempData.pDeviceData->pParameterSpace-=(lTableAttr.PS_SizeInBytes>>2); ++ } ++ // if there is a parent table where to return, then restore PS_pointer to the original state + } + else + { +- IndexInMasterTable=ProcessCommandProperties((PARSER_TEMP_DATA STACK_BASED *)&ParserTempData); ++ IndexInMasterTable=ProcessCommandProperties((PARSER_TEMP_DATA STACK_BASED *)&ParserTempData); + (*CallTable[IndexInMasterTable].function)((PARSER_TEMP_DATA STACK_BASED *)&ParserTempData); + #if (PARSER_TYPE!=DRIVER_TYPE_PARSER) +- BIOS_STACK_MODIFIER(); ++ BIOS_STACK_MODIFIER(); + #endif + } + } +@@ -227,13 +243,13 @@ CD_STATUS ParseTable(DEVICE_DATA STACK_BASED* pDeviceData, UINT8 IndexInMasterTa + ParserTempData.Status=CD_INVALID_OPCODE; + break; + } +- ++ + } // while + } // if + else + break; + } while (prevWorkingTableData!=NULL); +- if (ParserTempData.Status == CD_COMPLETED) return CD_SUCCESS; ++ if (ParserTempData.Status == CD_COMPLETED) return CD_SUCCESS; + return ParserTempData.Status; + } else return CD_SUCCESS; + } +diff --git a/src/AtomBios/hwserv_drv.c b/src/AtomBios/hwserv_drv.c +index a5f5a5b..9f2b6b9 100644 +--- a/src/AtomBios/hwserv_drv.c ++++ b/src/AtomBios/hwserv_drv.c +@@ -34,8 +34,14 @@ Revision History: + + NEG:27.09.2002 Initiated. + --*/ +-#include "CD_binding.h" +-#include "CD_hw_services.h" ++#ifdef HAVE_CONFIG_H ++#include "config.h" ++#endif ++ ++#include ++#include "xorg-server.h" ++ ++#include "Decoder.h" + + //trace settings + #if DEBUG_OUTPUT_DEVICE & 1 +@@ -249,12 +255,12 @@ VOID WriteReg32(PARSER_TEMP_DATA STACK_BASED * pWorkingTableData) + + VOID ReadIndReg32 (PARSER_TEMP_DATA STACK_BASED * pWorkingTableData) + { +- pWorkingTableData->IndirectData = CailReadATIRegister(pWorkingTableData->pDeviceData->CAIL,*(UINT16*)(pWorkingTableData->IndirectIOTablePointer+1)); ++ pWorkingTableData->IndirectData = CailReadATIRegister(pWorkingTableData->pDeviceData->CAIL,UINT16LE_TO_CPU(*(UINT16*)(pWorkingTableData->IndirectIOTablePointer+1))); + } + + VOID WriteIndReg32(PARSER_TEMP_DATA STACK_BASED * pWorkingTableData) + { +- CailWriteATIRegister(pWorkingTableData->pDeviceData->CAIL,*(UINT16*)(pWorkingTableData->IndirectIOTablePointer+1),pWorkingTableData->IndirectData ); ++ CailWriteATIRegister(pWorkingTableData->pDeviceData->CAIL,UINT16LE_TO_CPU(*(UINT16*)(pWorkingTableData->IndirectIOTablePointer+1)),pWorkingTableData->IndirectData); + } + + #endif +diff --git a/src/AtomBios/includes/CD_Common_Types.h b/src/AtomBios/includes/CD_Common_Types.h +index c60b652..071b8fd 100644 +--- a/src/AtomBios/includes/CD_Common_Types.h ++++ b/src/AtomBios/includes/CD_Common_Types.h +@@ -155,6 +155,18 @@ typedef unsigned long ULONG_PTR; + #ifndef FGL_LINUX + #pragma warning ( default : 4142 ) + #endif ++ ++#ifndef ATOM_BIG_ENDIAN ++#ifdef X_BYTE_ORDER ++#if X_BYTE_ORDER == X_BIG_ENDIAN ++#define ATOM_BIG_ENDIAN 1 ++#endif ++#endif ++#endif ++#ifndef ATOM_BIG_ENDIAN ++#define ATOM_BIG_ENDIAN 0 ++#endif ++ + #endif // _COMMON_TYPES_H_ + + // EOF +diff --git a/src/AtomBios/includes/CD_Definitions.h b/src/AtomBios/includes/CD_Definitions.h +index 98fd495..c00e93e 100644 +--- a/src/AtomBios/includes/CD_Definitions.h ++++ b/src/AtomBios/includes/CD_Definitions.h +@@ -39,11 +39,12 @@ NEG:27.08.2002 Initiated. + #ifndef _CD_DEFINITIONS_H + #define _CD_DEFINITIONS_H_ + #ifdef DRIVER_PARSER +-VOID *AllocateMemory(VOID *, UINT16); ++VOID *AllocateMemory(DEVICE_DATA *, UINT16); + VOID ReleaseMemory(DEVICE_DATA * , WORKING_TABLE_DATA* ); + #endif + CD_STATUS ParseTable(DEVICE_DATA* pDeviceData, UINT8 IndexInMasterTable); + //CD_STATUS CD_MainLoop(PARSER_TEMP_DATA_POINTER pParserTempData); + CD_STATUS Main_Loop(DEVICE_DATA* pDeviceData,UINT16 *MasterTableOffset,UINT8 IndexInMasterTable); + UINT16* GetCommandMasterTablePointer(DEVICE_DATA* pDeviceData); ++ATOM_TABLE_ATTRIBUTE GetCommandTableAttribute(UINT8 *pTableHeader); + #endif //CD_DEFINITIONS +diff --git a/src/AtomBios/includes/CD_Structs.h b/src/AtomBios/includes/CD_Structs.h +index c43f81d..01fb80e 100644 +--- a/src/AtomBios/includes/CD_Structs.h ++++ b/src/AtomBios/includes/CD_Structs.h +@@ -35,10 +35,18 @@ Revision History: + NEG:26.08.2002 Initiated. + --*/ + +-#include "CD_binding.h" + #ifndef _CD_STRUCTS_H_ + #define _CD_STRUCTS_H_ + ++#include "CD_binding.h" ++ ++/* Endaianness should be specified before inclusion, ++ * default to little endian ++ */ ++#ifndef ATOM_BIG_ENDIAN ++#error Endian not specified ++#endif ++ + #ifdef UEFI_BUILD + typedef UINT16** PTABLE_UNIT_TYPE; + typedef UINTN TABLE_UNIT_TYPE; +@@ -304,9 +312,15 @@ typedef union _PARAMETER_ACCESS { + }PARAMETER_ACCESS; + + typedef struct _COMMAND_ATTRIBUTE { ++#if ATOM_BIG_ENDIAN ++ UINT8 DestinationAlignment:2; ++ UINT8 SourceAlignment:3; ++ UINT8 Source:3; ++#else + UINT8 Source:3; + UINT8 SourceAlignment:3; + UINT8 DestinationAlignment:2; ++#endif + }COMMAND_ATTRIBUTE; + + typedef struct _SOURCE_DESTINATION_ALIGNMENT{ +@@ -363,11 +377,19 @@ typedef union _COMMAND_SPECIFIC_UNION{ + + + typedef struct _CD_GENERIC_BYTE{ ++#if ATOM_BIG_ENDIAN ++ UINT16 PS_SizeInDwordsUsedByCallingTable:5; ++ UINT16 CurrentPort:2; ++ UINT16 CommandAccessType:3; ++ UINT16 CurrentParameterSize:3; ++ UINT16 CommandType:3; ++#else + UINT16 CommandType:3; + UINT16 CurrentParameterSize:3; + UINT16 CommandAccessType:3; + UINT16 CurrentPort:2; + UINT16 PS_SizeInDwordsUsedByCallingTable:5; ++#endif + }CD_GENERIC_BYTE; + + typedef UINT8 COMMAND_TYPE_OPCODE_ONLY; +diff --git a/src/AtomBios/includes/Decoder.h b/src/AtomBios/includes/Decoder.h +index 24c25fc..1e143f0 100644 +--- a/src/AtomBios/includes/Decoder.h ++++ b/src/AtomBios/includes/Decoder.h +@@ -47,12 +47,32 @@ NEG:27.08.2002 Initiated. + #define PARSER_VERSION_MAJOR 0x00000000 + #define PARSER_VERSION_MINOR 0x0000000E + #define PARSER_VERSION (PARSER_VERSION_MAJOR | PARSER_VERSION_MINOR) +-#include "CD_binding.h" ++ + #include "CD_Common_Types.h" ++ ++#include "atombios.h" ++ ++/* these depends on some struct defined in atombios.h */ ++#include "CD_binding.h" + #include "CD_hw_services.h" + #include "CD_Structs.h" +-#include "CD_Definitions.h" + #include "CD_Opcodes.h" ++#include "CD_Definitions.h" ++ ++#if ATOM_BIG_ENDIAN ++extern UINT16 ATOM_BSWAP16(UINT16 x); ++extern UINT32 ATOM_BSWAP32(UINT32 x); ++ ++#define CPU_TO_UINT16LE(x) ATOM_BSWAP16(x) ++#define CPU_TO_UINT32LE(x) ATOM_BSWAP32(x) ++#define UINT16LE_TO_CPU(x) ATOM_BSWAP16(x) ++#define UINT32LE_TO_CPU(x) ATOM_BSWAP32(x) ++#else ++#define CPU_TO_UINT16LE(x) (x) ++#define CPU_TO_UINT32LE(x) (x) ++#define UINT16LE_TO_CPU(x) (x) ++#define UINT32LE_TO_CPU(x) (x) ++#endif + + #define SOURCE_ONLY_CMD_TYPE 0//0xFE + #define SOURCE_DESTINATION_CMD_TYPE 1//0xFD +diff --git a/src/AtomBios/includes/atombios.h b/src/AtomBios/includes/atombios.h +index 17483a6..2e7dc6c 100644 +--- a/src/AtomBios/includes/atombios.h ++++ b/src/AtomBios/includes/atombios.h +@@ -34,6 +34,12 @@ + + #define ATOM_HEADER_VERSION (ATOM_VERSION_MAJOR | ATOM_VERSION_MINOR) + ++/* Endianness should be specified before inclusion, ++ * default to little endian ++ */ ++#ifndef ATOM_BIG_ENDIAN ++#error Endian not specified ++#endif + + #ifdef _H2INC + #ifndef ULONG +@@ -304,7 +310,7 @@ typedef struct _ATOM_MASTER_COMMAND_TABLE + + typedef struct _ATOM_TABLE_ATTRIBUTE + { +-#if X_BYTE_ORDER == X_BIG_ENDIAN ++#if ATOM_BIG_ENDIAN + USHORT UpdatedByUtility:1; //[15]=Table updated by utility flag + USHORT PS_SizeInBytes:7; //[14:8]=Size of parameter space in Bytes (multiple of a dword), + USHORT WS_SizeInBytes:8; //[7:0]=Size of workspace in Bytes (in multiple of a dword), +@@ -315,6 +321,12 @@ typedef struct _ATOM_TABLE_ATTRIBUTE + #endif + }ATOM_TABLE_ATTRIBUTE; + ++typedef union _ATOM_TABLE_ATTRIBUTE_ACCESS ++{ ++ ATOM_TABLE_ATTRIBUTE sbfAccess; ++ USHORT susAccess; ++}ATOM_TABLE_ATTRIBUTE_ACCESS; ++ + // Common header for all command tables. + //Every table pointed by _ATOM_MASTER_COMMAND_TABLE has this common header. + //And the pointer actually points to this header. +@@ -1258,7 +1270,7 @@ typedef struct _ATOM_MULTIMEDIA_CONFIG_INFO + //Please don't add or expand this bitfield structure below, this one will retire soon.! + typedef struct _ATOM_FIRMWARE_CAPABILITY + { +-#if X_BYTE_ORDER == X_BIG_ENDIAN ++#if ATOM_BIG_ENDIAN + USHORT Reserved:3; + USHORT HyperMemory_Size:4; + USHORT HyperMemory_Support:1; +@@ -1767,7 +1779,7 @@ for Griffin or Greyhound. SBIOS needs to convert to actual time by: + + typedef struct _ATOM_I2C_ID_CONFIG + { +-#if X_BYTE_ORDER == X_BIG_ENDIAN ++#if ATOM_BIG_ENDIAN + UCHAR bfHW_Capable:1; + UCHAR bfHW_EngineID:3; + UCHAR bfI2C_LineMux:4; +@@ -1820,7 +1832,7 @@ typedef struct _ATOM_GPIO_I2C_INFO + //Please don't add or expand this bitfield structure below, this one will retire soon.! + typedef struct _ATOM_MODE_MISC_INFO + { +-#if X_BYTE_ORDER == X_BIG_ENDIAN ++#if ATOM_BIG_ENDIAN + USHORT Reserved:6; + USHORT RGB888:1; + USHORT DoubleClock:1; +@@ -3426,7 +3438,7 @@ typedef struct _ATOM_MEMORY_VENDOR_BLOCK{ + + + typedef struct _ATOM_MEMORY_SETTING_ID_CONFIG{ +-#if X_BYTE_ORDER == X_BIG_ENDIAN ++#if ATOM_BIG_ENDIAN + ULONG ucMemBlkId:8; + ULONG ulMemClockRange:24; + #else +@@ -4072,7 +4084,7 @@ typedef struct _COMPASSIONATE_DATA + + typedef struct _ATOM_CONNECTOR_INFO + { +-#if X_BYTE_ORDER == X_BIG_ENDIAN ++#if ATOM_BIG_ENDIAN + UCHAR bfConnectorType:4; + UCHAR bfAssociatedDAC:4; + #else +diff --git a/src/Makefile.am b/src/Makefile.am +index 5333495..97c686b 100644 +--- a/src/Makefile.am ++++ b/src/Makefile.am +@@ -26,8 +26,11 @@ + # _ladir passes a dummy rpath to libtool so the thing will actually link + # TODO: -nostdlib/-Bstatic/-lgcc platform magic, not installing the .a, etc. + ++radeon_drv_la_LIBADD = ++ + if DRI + RADEON_DRI_SRCS = radeon_dri.c ++radeon_drv_la_LIBADD += $(DRI_LIBS) + endif + + RADEON_ATOMBIOS_SOURCES = \ +@@ -70,6 +73,11 @@ AM_CFLAGS = @XORG_CFLAGS@ @DRI_CFLAGS@ @XMODES_CFLAGS@ -DDISABLE_EASF -DENABLE_A + + INCLUDES = -I$(srcdir)/AtomBios/includes + ++if XSERVER_LIBPCIACCESS ++ati_drv_la_LIBADD = $(PCIACCESS_LIBS) ++radeon_drv_la_LIBADD += $(PCIACCESS_LIBS) ++endif ++ + ati_drv_la_LTLIBRARIES = ati_drv.la + ati_drv_la_LDFLAGS = -module -avoid-version + ati_drv_ladir = @moduledir@/drivers +diff --git a/src/ati_pciids_gen.h b/src/ati_pciids_gen.h +index a740df8..1da8f1f 100644 +--- a/src/ati_pciids_gen.h ++++ b/src/ati_pciids_gen.h +@@ -1,4 +1,5 @@ + #define PCI_CHIP_RV380_3150 0x3150 ++#define PCI_CHIP_RV380_3151 0x3151 + #define PCI_CHIP_RV380_3152 0x3152 + #define PCI_CHIP_RV380_3154 0x3154 + #define PCI_CHIP_RV380_3E50 0x3E50 +@@ -330,6 +331,8 @@ + #define PCI_CHIP_R600_940A 0x940A + #define PCI_CHIP_R600_940B 0x940B + #define PCI_CHIP_R600_940F 0x940F ++#define PCI_CHIP_RV770_9440 0x9440 ++#define PCI_CHIP_RV770_9442 0x9442 + #define PCI_CHIP_RV610_94C0 0x94C0 + #define PCI_CHIP_RV610_94C1 0x94C1 + #define PCI_CHIP_RV610_94C3 0x94C3 +@@ -347,6 +350,7 @@ + #define PCI_CHIP_RV670_9507 0x9507 + #define PCI_CHIP_RV670_950F 0x950F + #define PCI_CHIP_RV670_9511 0x9511 ++#define PCI_CHIP_RV670_9515 0x9515 + #define PCI_CHIP_RV630_9580 0x9580 + #define PCI_CHIP_RV630_9581 0x9581 + #define PCI_CHIP_RV630_9583 0x9583 +diff --git a/src/atombios_crtc.c b/src/atombios_crtc.c +index 363addf..70650e1 100644 +--- a/src/atombios_crtc.c ++++ b/src/atombios_crtc.c +@@ -48,6 +48,29 @@ + #include "sarea.h" + #endif + ++AtomBiosResult ++atombios_lock_crtc(atomBiosHandlePtr atomBIOS, int crtc, int lock) ++{ ++ ENABLE_CRTC_PS_ALLOCATION crtc_data; ++ AtomBiosArgRec data; ++ unsigned char *space; ++ ++ crtc_data.ucCRTC = crtc; ++ crtc_data.ucEnable = lock; ++ ++ data.exec.index = GetIndexIntoMasterTable(COMMAND, UpdateCRTC_DoubleBufferRegisters); ++ data.exec.dataSpace = (void *)&space; ++ data.exec.pspace = &crtc_data; ++ ++ if (RHDAtomBiosFunc(atomBIOS->scrnIndex, atomBIOS, ATOMBIOS_EXEC, &data) == ATOM_SUCCESS) { ++ ErrorF("%s CRTC %d success\n", lock? "Lock":"Unlock", crtc); ++ return ATOM_SUCCESS ; ++ } ++ ++ ErrorF("Lock CRTC failed\n"); ++ return ATOM_NOT_IMPLEMENTED; ++} ++ + static AtomBiosResult + atombios_enable_crtc(atomBiosHandlePtr atomBIOS, int crtc, int state) + { +@@ -105,7 +128,7 @@ atombios_blank_crtc(atomBiosHandlePtr atomBIOS, int crtc, int state) + crtc_data.ucCRTC = crtc; + crtc_data.ucBlanking = state; + +- data.exec.index = offsetof(ATOM_MASTER_LIST_OF_COMMAND_TABLES, BlankCRTC) / sizeof(unsigned short); ++ data.exec.index = GetIndexIntoMasterTable(COMMAND, BlankCRTC); + data.exec.dataSpace = (void *)&space; + data.exec.pspace = &crtc_data; + +@@ -146,10 +169,27 @@ atombios_set_crtc_timing(atomBiosHandlePtr atomBIOS, SET_CRTC_TIMING_PARAMETERS_ + { + AtomBiosArgRec data; + unsigned char *space; ++ SET_CRTC_TIMING_PARAMETERS_PS_ALLOCATION conv_param; ++ ++ conv_param.usH_Total = cpu_to_le16(crtc_param->usH_Total); ++ conv_param.usH_Disp = cpu_to_le16(crtc_param->usH_Disp); ++ conv_param.usH_SyncStart = cpu_to_le16(crtc_param->usH_SyncStart); ++ conv_param.usH_SyncWidth = cpu_to_le16(crtc_param->usH_SyncWidth); ++ conv_param.usV_Total = cpu_to_le16(crtc_param->usV_Total); ++ conv_param.usV_Disp = cpu_to_le16(crtc_param->usV_Disp); ++ conv_param.usV_SyncStart = cpu_to_le16(crtc_param->usV_SyncStart); ++ conv_param.usV_SyncWidth = cpu_to_le16(crtc_param->usV_SyncWidth); ++ conv_param.susModeMiscInfo.usAccess = cpu_to_le16(crtc_param->susModeMiscInfo.usAccess); ++ conv_param.ucCRTC = crtc_param->ucCRTC; ++ conv_param.ucOverscanRight = crtc_param->ucOverscanRight; ++ conv_param.ucOverscanLeft = crtc_param->ucOverscanLeft; ++ conv_param.ucOverscanBottom = crtc_param->ucOverscanBottom; ++ conv_param.ucOverscanTop = crtc_param->ucOverscanTop; ++ conv_param.ucReserved = crtc_param->ucReserved; + + data.exec.index = GetIndexIntoMasterTable(COMMAND, SetCRTC_Timing); + data.exec.dataSpace = (void *)&space; +- data.exec.pspace = crtc_param; ++ data.exec.pspace = &conv_param; + + if (RHDAtomBiosFunc(atomBIOS->scrnIndex, atomBIOS, ATOMBIOS_EXEC, &data) == ATOM_SUCCESS) { + ErrorF("Set CRTC Timing success\n"); +@@ -235,9 +275,9 @@ atombios_crtc_set_pll(xf86CrtcPtr crtc, DisplayModePtr mode, int pll_flags) + case 1: + case 2: + spc2_ptr = (PIXEL_CLOCK_PARAMETERS_V2*)&spc_param.sPCLKInput; +- spc2_ptr->usPixelClock = sclock; +- spc2_ptr->usRefDiv = ref_div; +- spc2_ptr->usFbDiv = fb_div; ++ spc2_ptr->usPixelClock = cpu_to_le16(sclock); ++ spc2_ptr->usRefDiv = cpu_to_le16(ref_div); ++ spc2_ptr->usFbDiv = cpu_to_le16(fb_div); + spc2_ptr->ucPostDiv = post_div; + spc2_ptr->ucPpll = radeon_crtc->crtc_id ? ATOM_PPLL2 : ATOM_PPLL1; + spc2_ptr->ucCRTC = radeon_crtc->crtc_id; +@@ -246,9 +286,9 @@ atombios_crtc_set_pll(xf86CrtcPtr crtc, DisplayModePtr mode, int pll_flags) + break; + case 3: + spc3_ptr = (PIXEL_CLOCK_PARAMETERS_V3*)&spc_param.sPCLKInput; +- spc3_ptr->usPixelClock = sclock; +- spc3_ptr->usRefDiv = ref_div; +- spc3_ptr->usFbDiv = fb_div; ++ spc3_ptr->usPixelClock = cpu_to_le16(sclock); ++ spc3_ptr->usRefDiv = cpu_to_le16(ref_div); ++ spc3_ptr->usFbDiv = cpu_to_le16(fb_div); + spc3_ptr->ucPostDiv = post_div; + spc3_ptr->ucPpll = radeon_crtc->crtc_id ? ATOM_PPLL2 : ATOM_PPLL1; + spc3_ptr->ucMiscInfo = (radeon_crtc->crtc_id << 2); +@@ -442,9 +482,6 @@ atombios_crtc_mode_set(xf86CrtcPtr crtc, + fb_location = fb_location + (char *)crtc->rotatedData - (char *)info->FB; + } + +- /* lock the grph regs */ +- OUTREG(AVIVO_D1GRPH_UPDATE + radeon_crtc->crtc_offset, AVIVO_D1GRPH_UPDATE_LOCK); +- + OUTREG(AVIVO_D1GRPH_PRIMARY_SURFACE_ADDRESS + radeon_crtc->crtc_offset, fb_location); + OUTREG(AVIVO_D1GRPH_SECONDARY_SURFACE_ADDRESS + radeon_crtc->crtc_offset, fb_location); + OUTREG(AVIVO_D1GRPH_CONTROL + radeon_crtc->crtc_offset, fb_format); +@@ -459,26 +496,27 @@ atombios_crtc_mode_set(xf86CrtcPtr crtc, + crtc->scrn->displayWidth); + OUTREG(AVIVO_D1GRPH_ENABLE + radeon_crtc->crtc_offset, 1); + +- /* unlock the grph regs */ +- OUTREG(AVIVO_D1GRPH_UPDATE + radeon_crtc->crtc_offset, 0); +- +- /* lock the mode regs */ +- OUTREG(AVIVO_D1SCL_UPDATE + radeon_crtc->crtc_offset, AVIVO_D1SCL_UPDATE_LOCK); +- + OUTREG(AVIVO_D1MODE_DESKTOP_HEIGHT + radeon_crtc->crtc_offset, + mode->VDisplay); + OUTREG(AVIVO_D1MODE_VIEWPORT_START + radeon_crtc->crtc_offset, (x << 16) | y); + OUTREG(AVIVO_D1MODE_VIEWPORT_SIZE + radeon_crtc->crtc_offset, + (mode->HDisplay << 16) | mode->VDisplay); +- /* unlock the mode regs */ +- OUTREG(AVIVO_D1SCL_UPDATE + radeon_crtc->crtc_offset, 0); + ++ if (adjusted_mode->Flags & V_INTERLACE) ++ OUTREG(AVIVO_D1MODE_DATA_FORMAT + radeon_crtc->crtc_offset, ++ AVIVO_D1MODE_INTERLEAVE_EN); ++ else ++ OUTREG(AVIVO_D1MODE_DATA_FORMAT + radeon_crtc->crtc_offset, ++ 0); + } + + atombios_crtc_set_pll(crtc, adjusted_mode, pll_flags); + + atombios_set_crtc_timing(info->atomBIOS, &crtc_timing); + ++ if (info->DispPriority) ++ RADEONInitDispBandwidth(pScrn); ++ + if (tilingChanged) { + /* need to redraw front buffer, I guess this can be considered a hack ? */ + /* if this is called during ScreenInit() we don't have pScrn->pScreen yet */ +@@ -492,3 +530,126 @@ atombios_crtc_mode_set(xf86CrtcPtr crtc, + + } + ++/* Calculate display buffer watermark to prevent buffer underflow */ ++void ++RADEONInitDispBandwidthAVIVO(ScrnInfoPtr pScrn, ++ DisplayModePtr mode1, int pixel_bytes1, ++ DisplayModePtr mode2, int pixel_bytes2) ++{ ++ RADEONInfoPtr info = RADEONPTR(pScrn); ++ RADEONEntPtr pRADEONEnt = RADEONEntPriv(pScrn); ++ unsigned char *RADEONMMIO = info->MMIO; ++ ++ uint32_t dc_lb_memory_split; ++ float mem_bw, peak_disp_bw; ++ float min_mem_eff = 0.8; /* XXX: taken from legacy method */ ++ float pix_clk, pix_clk2; /* in MHz */ ++ ++ /* ++ * Set display0/1 priority up in the memory controller for ++ * modes if the user specifies HIGH for displaypriority ++ * option. ++ */ ++ if (info->DispPriority == 2) { ++ uint32_t mc_init_misc_lat_timer = 0; ++ if (info->ChipFamily == CHIP_FAMILY_RV515) ++ mc_init_misc_lat_timer = INMC(pScrn, RV515_MC_INIT_MISC_LAT_TIMER); ++ else if (info->ChipFamily == CHIP_FAMILY_RS690) ++ mc_init_misc_lat_timer = INMC(pScrn, RS690_MC_INIT_MISC_LAT_TIMER); ++ ++ mc_init_misc_lat_timer &= ~(R300_MC_DISP1R_INIT_LAT_MASK << R300_MC_DISP1R_INIT_LAT_SHIFT); ++ mc_init_misc_lat_timer &= ~(R300_MC_DISP0R_INIT_LAT_MASK << R300_MC_DISP0R_INIT_LAT_SHIFT); ++ ++ if (pRADEONEnt->pCrtc[1]->enabled) ++ mc_init_misc_lat_timer |= (1 << R300_MC_DISP1R_INIT_LAT_SHIFT); /* display 1 */ ++ if (pRADEONEnt->pCrtc[0]->enabled) ++ mc_init_misc_lat_timer |= (1 << R300_MC_DISP0R_INIT_LAT_SHIFT); /* display 0 */ ++ ++ if (info->ChipFamily == CHIP_FAMILY_RV515) ++ OUTMC(pScrn, RV515_MC_INIT_MISC_LAT_TIMER, mc_init_misc_lat_timer); ++ else if (info->ChipFamily == CHIP_FAMILY_RS690) ++ OUTMC(pScrn, RS690_MC_INIT_MISC_LAT_TIMER, mc_init_misc_lat_timer); ++ } ++ ++ /* XXX: fix me for AVIVO ++ * Determine if there is enough bandwidth for current display mode ++ */ ++ mem_bw = info->mclk * (info->RamWidth / 8) * (info->IsDDR ? 2 : 1); ++ ++ pix_clk = 0; ++ pix_clk2 = 0; ++ peak_disp_bw = 0; ++ if (mode1) { ++ pix_clk = mode1->Clock/1000.0; ++ peak_disp_bw += (pix_clk * pixel_bytes1); ++ } ++ if (mode2) { ++ pix_clk2 = mode2->Clock/1000.0; ++ peak_disp_bw += (pix_clk2 * pixel_bytes2); ++ } ++ ++ if (peak_disp_bw >= mem_bw * min_mem_eff) { ++ xf86DrvMsg(pScrn->scrnIndex, X_WARNING, ++ "You may not have enough display bandwidth for current mode\n" ++ "If you have flickering problem, try to lower resolution, refresh rate, or color depth\n"); ++ } ++ ++ /* ++ * Line Buffer Setup ++ * There is a single line buffer shared by both display controllers. ++ * DC_LB_MEMORY_SPLIT controls how that line buffer is shared between the display ++ * controllers. The paritioning can either be done manually or via one of four ++ * preset allocations specified in bits 1:0: ++ * 0 - line buffer is divided in half and shared between each display controller ++ * 1 - D1 gets 3/4 of the line buffer, D2 gets 1/4 ++ * 2 - D1 gets the whole buffer ++ * 3 - D1 gets 1/4 of the line buffer, D2 gets 3/4 ++ * Setting bit 2 of DC_LB_MEMORY_SPLIT controls switches to manual allocation mode. ++ * In manual allocation mode, D1 always starts at 0, D1 end/2 is specified in bits ++ * 14:4; D2 allocation follows D1. ++ */ ++ ++ /* is auto or manual better ? */ ++ dc_lb_memory_split = INREG(AVIVO_DC_LB_MEMORY_SPLIT) & ~AVIVO_DC_LB_MEMORY_SPLIT_MASK; ++ dc_lb_memory_split &= ~AVIVO_DC_LB_MEMORY_SPLIT_SHIFT_MODE; ++#if 1 ++ /* auto */ ++ if (mode1 && mode2) { ++ if (mode1->HDisplay > mode2->HDisplay) { ++ if (mode1->HDisplay > 2560) ++ dc_lb_memory_split |= AVIVO_DC_LB_MEMORY_SPLIT_D1_3Q_D2_1Q; ++ else ++ dc_lb_memory_split |= AVIVO_DC_LB_MEMORY_SPLIT_D1HALF_D2HALF; ++ } else if (mode2->HDisplay > mode1->HDisplay) { ++ if (mode2->HDisplay > 2560) ++ dc_lb_memory_split |= AVIVO_DC_LB_MEMORY_SPLIT_D1_1Q_D2_3Q; ++ else ++ dc_lb_memory_split |= AVIVO_DC_LB_MEMORY_SPLIT_D1HALF_D2HALF; ++ } else ++ dc_lb_memory_split |= AVIVO_DC_LB_MEMORY_SPLIT_D1HALF_D2HALF; ++ } else if (mode1) { ++ dc_lb_memory_split |= AVIVO_DC_LB_MEMORY_SPLIT_D1_ONLY; ++ } else if (mode2) { ++ dc_lb_memory_split |= AVIVO_DC_LB_MEMORY_SPLIT_D1_1Q_D2_3Q; ++ } ++#else ++ /* manual */ ++ dc_lb_memory_split |= AVIVO_DC_LB_MEMORY_SPLIT_SHIFT_MODE; ++ dc_lb_memory_split &= ~(AVIVO_DC_LB_DISP1_END_ADR_MASK << AVIVO_DC_LB_DISP1_END_ADR_SHIFT); ++ if (mode1) { ++ dc_lb_memory_split |= ((((mode1->HDisplay / 2) + 64 /*???*/) & AVIVO_DC_LB_DISP1_END_ADR_MASK) ++ << AVIVO_DC_LB_DISP1_END_ADR_SHIFT); ++ } else if (mode2) { ++ dc_lb_memory_split |= (0 << AVIVO_DC_LB_DISP1_END_ADR_SHIFT); ++ } ++ OUTREG(AVIVO_DC_LB_MEMORY_SPLIT, dc_lb_memory_split); ++#endif ++ ++ /* ++ * Watermark setup ++ * TODO... ++ * Unforunately, I haven't been able to dig up the avivo watermark programming ++ * guide yet. -AGD ++ */ ++ ++} +diff --git a/src/atombios_output.c b/src/atombios_output.c +index 51be301..83b86a7 100644 +--- a/src/atombios_output.c ++++ b/src/atombios_output.c +@@ -78,7 +78,7 @@ atombios_output_dac1_setup(xf86OutputPtr output, DisplayModePtr mode) + } + } + +- disp_data.usPixelClock = mode->Clock / 10; ++ disp_data.usPixelClock = cpu_to_le16(mode->Clock / 10); + data.exec.index = GetIndexIntoMasterTable(COMMAND, DAC1EncoderControl); + data.exec.dataSpace = (void *)&space; + data.exec.pspace = &disp_data; +@@ -128,7 +128,7 @@ atombios_output_dac2_setup(xf86OutputPtr output, DisplayModePtr mode) + } + } + +- disp_data.usPixelClock = mode->Clock / 10; ++ disp_data.usPixelClock = cpu_to_le16(mode->Clock / 10); + data.exec.index = GetIndexIntoMasterTable(COMMAND, DAC2EncoderControl); + data.exec.dataSpace = (void *)&space; + data.exec.pspace = &disp_data; +@@ -188,7 +188,7 @@ atombios_output_tv1_setup(xf86OutputPtr output, DisplayModePtr mode) + } + } + +- disp_data.sTVEncoder.usPixelClock = mode->Clock / 10; ++ disp_data.sTVEncoder.usPixelClock = cpu_to_le16(mode->Clock / 10); + data.exec.index = GetIndexIntoMasterTable(COMMAND, TVEncoderControl); + data.exec.dataSpace = (void *)&space; + data.exec.pspace = &disp_data; +@@ -243,7 +243,7 @@ atombios_output_ddia_setup(xf86OutputPtr output, DisplayModePtr mode) + unsigned char *space; + + disp_data.sDVOEncoder.ucAction = ATOM_ENABLE; +- disp_data.sDVOEncoder.usPixelClock = mode->Clock / 10; ++ disp_data.sDVOEncoder.usPixelClock = cpu_to_le16(mode->Clock / 10); + + if (mode->Clock > 165000) + disp_data.sDVOEncoder.usDevAttr.sDigAttrib.ucAttribute = PANEL_ENCODER_MISC_DUAL; +@@ -276,7 +276,7 @@ atombios_output_tmds1_setup(xf86OutputPtr output, DisplayModePtr mode) + disp_data.ucMisc = 1; + else + disp_data.ucMisc = 0; +- disp_data.usPixelClock = mode->Clock / 10; ++ disp_data.usPixelClock = cpu_to_le16(mode->Clock / 10); + data.exec.index = GetIndexIntoMasterTable(COMMAND, TMDS1EncoderControl); + data.exec.dataSpace = (void *)&space; + data.exec.pspace = &disp_data; +@@ -304,7 +304,7 @@ atombios_output_tmds2_setup(xf86OutputPtr output, DisplayModePtr mode) + disp_data.ucMisc = 1; + else + disp_data.ucMisc = 0; +- disp_data.usPixelClock = mode->Clock / 10; ++ disp_data.usPixelClock = cpu_to_le16(mode->Clock / 10); + data.exec.index = GetIndexIntoMasterTable(COMMAND, TMDS2EncoderControl); + data.exec.dataSpace = (void *)&space; + data.exec.pspace = &disp_data; +@@ -331,7 +331,7 @@ atombios_output_lvds_setup(xf86OutputPtr output, DisplayModePtr mode) + disp_data.ucMisc = 1; + else + disp_data.ucMisc = 0; +- disp_data.usPixelClock = mode->Clock / 10; ++ disp_data.usPixelClock = cpu_to_le16(mode->Clock / 10); + data.exec.index = GetIndexIntoMasterTable(COMMAND, LVDSEncoderControl); + data.exec.dataSpace = (void *)&space; + data.exec.pspace = &disp_data; +@@ -355,7 +355,7 @@ atombios_output_dig1_setup(xf86OutputPtr output, DisplayModePtr mode) + unsigned char *space; + + disp_data.ucAction = 1; +- disp_data.usPixelClock = mode->Clock / 10; ++ disp_data.usPixelClock = cpu_to_le16(mode->Clock / 10); + disp_data.ucConfig = ATOM_ENCODER_CONFIG_TRANSMITTER1; + if (OUTPUT_IS_DVI || (radeon_output->type == OUTPUT_HDMI)) { + if (radeon_output->coherent_mode) { +@@ -406,7 +406,7 @@ atombios_output_dig1_transmitter_setup(xf86OutputPtr output, DisplayModePtr mode + unsigned char *space; + + disp_data.ucAction = ATOM_TRANSMITTER_ACTION_ENABLE; +- disp_data.usPixelClock = mode->Clock / 10; ++ disp_data.usPixelClock = cpu_to_le16(mode->Clock / 10); + disp_data.ucConfig = ATOM_TRANSMITTER_CONFIG_DIG1_ENCODER | ATOM_TRANSMITTER_CONFIG_CLKSRC_PPLL; + + if (info->IsIGP && (radeon_output->TMDSType == TMDS_UNIPHY)) { +@@ -464,7 +464,7 @@ atombios_output_dig2_setup(xf86OutputPtr output, DisplayModePtr mode) + unsigned char *space; + + disp_data.ucAction = 1; +- disp_data.usPixelClock = mode->Clock / 10; ++ disp_data.usPixelClock = cpu_to_le16(mode->Clock / 10); + disp_data.ucConfig = ATOM_ENCODER_CONFIG_TRANSMITTER2; + if (OUTPUT_IS_DVI || (radeon_output->type == OUTPUT_HDMI)) { + if (radeon_output->coherent_mode) { +@@ -515,7 +515,7 @@ atombios_output_dig2_transmitter_setup(xf86OutputPtr output, DisplayModePtr mode + unsigned char *space; + + disp_data.ucAction = ATOM_TRANSMITTER_ACTION_ENABLE; +- disp_data.usPixelClock = mode->Clock / 10; ++ disp_data.usPixelClock = cpu_to_le16(mode->Clock / 10); + disp_data.ucConfig = ATOM_TRANSMITTER_CONFIG_DIG2_ENCODER | ATOM_TRANSMITTER_CONFIG_CLKSRC_PPLL; + + if (info->IsIGP && (radeon_output->TMDSType == TMDS_UNIPHY)) { +@@ -979,19 +979,19 @@ atom_bios_dac_load_detect(atomBiosHandlePtr atomBIOS, xf86OutputPtr output) + dac_data.sDacload.ucMisc = 0; + + if (radeon_output->devices & ATOM_DEVICE_CRT1_SUPPORT) { +- dac_data.sDacload.usDeviceID = ATOM_DEVICE_CRT1_SUPPORT; ++ dac_data.sDacload.usDeviceID = cpu_to_le16(ATOM_DEVICE_CRT1_SUPPORT); + if (radeon_output->DACType == DAC_PRIMARY) + dac_data.sDacload.ucDacType = ATOM_DAC_A; + else if (radeon_output->DACType == DAC_TVDAC) + dac_data.sDacload.ucDacType = ATOM_DAC_B; + } else if (radeon_output->devices & ATOM_DEVICE_CRT2_SUPPORT) { +- dac_data.sDacload.usDeviceID = ATOM_DEVICE_CRT2_SUPPORT; ++ dac_data.sDacload.usDeviceID = cpu_to_le16(ATOM_DEVICE_CRT2_SUPPORT); + if (radeon_output->DACType == DAC_PRIMARY) + dac_data.sDacload.ucDacType = ATOM_DAC_A; + else if (radeon_output->DACType == DAC_TVDAC) + dac_data.sDacload.ucDacType = ATOM_DAC_B; + } else if (radeon_output->devices & ATOM_DEVICE_CV_SUPPORT) { +- dac_data.sDacload.usDeviceID = ATOM_DEVICE_CV_SUPPORT; ++ dac_data.sDacload.usDeviceID = cpu_to_le16(ATOM_DEVICE_CV_SUPPORT); + if (radeon_output->DACType == DAC_PRIMARY) + dac_data.sDacload.ucDacType = ATOM_DAC_A; + else if (radeon_output->DACType == DAC_TVDAC) +@@ -999,7 +999,7 @@ atom_bios_dac_load_detect(atomBiosHandlePtr atomBIOS, xf86OutputPtr output) + if (IS_DCE3_VARIANT) + dac_data.sDacload.ucMisc = 1; + } else if (radeon_output->devices & ATOM_DEVICE_TV1_SUPPORT) { +- dac_data.sDacload.usDeviceID = ATOM_DEVICE_TV1_SUPPORT; ++ dac_data.sDacload.usDeviceID = cpu_to_le16(ATOM_DEVICE_TV1_SUPPORT); + if (radeon_output->DACType == DAC_PRIMARY) + dac_data.sDacload.ucDacType = ATOM_DAC_A; + else if (radeon_output->DACType == DAC_TVDAC) +diff --git a/src/legacy_crtc.c b/src/legacy_crtc.c +index 3df61a7..334194a 100644 +--- a/src/legacy_crtc.c ++++ b/src/legacy_crtc.c +@@ -625,6 +625,9 @@ radeon_crtc_modeset_ioctl(xf86CrtcPtr crtc, Bool post) + RADEONCrtcPrivatePtr radeon_crtc = crtc->driver_private; + struct drm_modeset_ctl modeset; + ++ if (!info->directRenderingEnabled) ++ return; ++ + modeset.crtc = radeon_crtc->crtc_id; + modeset.cmd = post ? _DRM_POST_MODESET : _DRM_PRE_MODESET; + +@@ -1327,9 +1330,12 @@ radeon_update_tv_routing(ScrnInfoPtr pScrn, RADEONSavePtr restore) + } + + /* Calculate display buffer watermark to prevent buffer underflow */ +-static void +-RADEONInitDispBandwidth2(ScrnInfoPtr pScrn, RADEONInfoPtr info, int pixel_bytes2, DisplayModePtr mode1, DisplayModePtr mode2) ++void ++RADEONInitDispBandwidthLegacy(ScrnInfoPtr pScrn, ++ DisplayModePtr mode1, int pixel_bytes1, ++ DisplayModePtr mode2, int pixel_bytes2) + { ++ RADEONInfoPtr info = RADEONPTR(pScrn); + RADEONEntPtr pRADEONEnt = RADEONEntPriv(pScrn); + unsigned char *RADEONMMIO = info->MMIO; + +@@ -1352,10 +1358,10 @@ RADEONInitDispBandwidth2(ScrnInfoPtr pScrn, RADEONInfoPtr info, int pixel_bytes2 + float min_mem_eff = 0.8; + float sclk_eff, sclk_delay; + float mc_latency_mclk, mc_latency_sclk, cur_latency_mclk, cur_latency_sclk; +- float disp_latency, disp_latency_overhead, disp_drain_rate, disp_drain_rate2; ++ float disp_latency, disp_latency_overhead, disp_drain_rate = 0, disp_drain_rate2; + float pix_clk, pix_clk2; /* in MHz */ + int cur_size = 16; /* in octawords */ +- int critical_point, critical_point2; ++ int critical_point = 0, critical_point2; + int stop_req, max_stop_req; + float read_return_rate, time_disp1_drop_priority; + +@@ -1366,15 +1372,15 @@ RADEONInitDispBandwidth2(ScrnInfoPtr pScrn, RADEONInfoPtr info, int pixel_bytes2 + */ + if ((info->DispPriority == 2) && IS_R300_VARIANT) { + uint32_t mc_init_misc_lat_timer = INREG(R300_MC_INIT_MISC_LAT_TIMER); +- if (pRADEONEnt->pCrtc[1]->enabled) { +- mc_init_misc_lat_timer |= 0x1100; /* display 0 and 1 */ +- } else { +- mc_init_misc_lat_timer |= 0x0100; /* display 0 only */ +- } ++ mc_init_misc_lat_timer &= ~(R300_MC_DISP1R_INIT_LAT_MASK << R300_MC_DISP1R_INIT_LAT_SHIFT); ++ mc_init_misc_lat_timer &= ~(R300_MC_DISP0R_INIT_LAT_MASK << R300_MC_DISP0R_INIT_LAT_SHIFT); ++ if (pRADEONEnt->pCrtc[1]->enabled) ++ mc_init_misc_lat_timer |= (1 << R300_MC_DISP1R_INIT_LAT_SHIFT); /* display 1 */ ++ if (pRADEONEnt->pCrtc[0]->enabled) ++ mc_init_misc_lat_timer |= (1 << R300_MC_DISP0R_INIT_LAT_SHIFT); /* display 0 */ + OUTREG(R300_MC_INIT_MISC_LAT_TIMER, mc_init_misc_lat_timer); + } + +- + /* R420 and RV410 family not supported yet */ + if (info->ChipFamily == CHIP_FAMILY_R420 || info->ChipFamily == CHIP_FAMILY_RV410) return; + +@@ -1383,15 +1389,17 @@ RADEONInitDispBandwidth2(ScrnInfoPtr pScrn, RADEONInfoPtr info, int pixel_bytes2 + */ + mem_bw = info->mclk * (info->RamWidth / 8) * (info->IsDDR ? 2 : 1); + +- pix_clk = mode1->Clock/1000.0; +- if (mode2) ++ pix_clk = 0; ++ pix_clk2 = 0; ++ peak_disp_bw = 0; ++ if (mode1) { ++ pix_clk = mode1->Clock/1000.0; ++ peak_disp_bw += (pix_clk * pixel_bytes1); ++ } ++ if (mode2) { + pix_clk2 = mode2->Clock/1000.0; +- else +- pix_clk2 = 0; +- +- peak_disp_bw = (pix_clk * info->CurrentLayout.pixel_bytes); +- if (pixel_bytes2) +- peak_disp_bw += (pix_clk2 * pixel_bytes2); ++ peak_disp_bw += (pix_clk2 * pixel_bytes2); ++ } + + if (peak_disp_bw >= mem_bw * min_mem_eff) { + xf86DrvMsg(pScrn->scrnIndex, X_WARNING, +@@ -1399,20 +1407,6 @@ RADEONInitDispBandwidth2(ScrnInfoPtr pScrn, RADEONInfoPtr info, int pixel_bytes2 + "If you have flickering problem, try to lower resolution, refresh rate, or color depth\n"); + } + +- /* CRTC1 +- Set GRPH_BUFFER_CNTL register using h/w defined optimal values. +- GRPH_STOP_REQ <= MIN[ 0x7C, (CRTC_H_DISP + 1) * (bit depth) / 0x10 ] +- */ +- stop_req = mode1->HDisplay * info->CurrentLayout.pixel_bytes / 16; +- +- /* setup Max GRPH_STOP_REQ default value */ +- if (IS_RV100_VARIANT) +- max_stop_req = 0x5c; +- else +- max_stop_req = 0x7c; +- if (stop_req > max_stop_req) +- stop_req = max_stop_req; +- + /* Get values from the EXT_MEM_CNTL register...converting its contents. */ + temp = INREG(RADEON_MEM_TIMING_CNTL); + if ((info->ChipFamily == CHIP_FAMILY_RV100) || info->IsIGP) { /* RV100, M6, IGPs */ +@@ -1435,9 +1429,8 @@ RADEONInitDispBandwidth2(ScrnInfoPtr pScrn, RADEONInfoPtr info, int pixel_bytes2 + } + + if (IS_R300_VARIANT) { +- + /* on the R300, Tcas is included in Trbs. +- */ ++ */ + temp = INREG(RADEON_MEM_CNTL); + data = (R300_MEM_NUM_CHANNELS_MASK & temp); + if (data == 1) { +@@ -1473,7 +1466,8 @@ RADEONInitDispBandwidth2(ScrnInfoPtr pScrn, RADEONInfoPtr info, int pixel_bytes2 + sclk_eff = info->sclk; + } + +- /* Find the memory controller latency for the display client. ++ /* ++ Find the memory controller latency for the display client. + */ + if (IS_R300_VARIANT) { + /*not enough for R350 ???*/ +@@ -1527,89 +1521,107 @@ RADEONInitDispBandwidth2(ScrnInfoPtr pScrn, RADEONInfoPtr info, int pixel_bytes2 + mc_latency_sclk = mc_latency_sclk + disp_latency_overhead + cur_latency_sclk; + disp_latency = MAX(mc_latency_mclk, mc_latency_sclk); + +- /* +- Find the drain rate of the display buffer. +- */ +- disp_drain_rate = pix_clk / (16.0/info->CurrentLayout.pixel_bytes); +- if (pixel_bytes2) +- disp_drain_rate2 = pix_clk2 / (16.0/pixel_bytes2); ++ /* setup Max GRPH_STOP_REQ default value */ ++ if (IS_RV100_VARIANT) ++ max_stop_req = 0x5c; + else +- disp_drain_rate2 = 0; ++ max_stop_req = 0x7c; + +- /* +- Find the critical point of the display buffer. +- */ +- critical_point= (uint32_t)(disp_drain_rate * disp_latency + 0.5); ++ if (mode1) { ++ /* CRTC1 ++ Set GRPH_BUFFER_CNTL register using h/w defined optimal values. ++ GRPH_STOP_REQ <= MIN[ 0x7C, (CRTC_H_DISP + 1) * (bit depth) / 0x10 ] ++ */ ++ stop_req = mode1->HDisplay * pixel_bytes1 / 16; + +- /* ???? */ +- /* +- temp = (info->SavedReg.grph_buffer_cntl & RADEON_GRPH_CRITICAL_POINT_MASK) >> RADEON_GRPH_CRITICAL_POINT_SHIFT; +- if (critical_point < temp) critical_point = temp; +- */ +- if (info->DispPriority == 2) { +- critical_point = 0; +- } ++ if (stop_req > max_stop_req) ++ stop_req = max_stop_req; + +- /* +- The critical point should never be above max_stop_req-4. Setting +- GRPH_CRITICAL_CNTL = 0 will thus force high priority all the time. +- */ +- if (max_stop_req - critical_point < 4) critical_point = 0; ++ /* ++ Find the drain rate of the display buffer. ++ */ ++ disp_drain_rate = pix_clk / (16.0/pixel_bytes1); + +- if (critical_point == 0 && mode2 && info->ChipFamily == CHIP_FAMILY_R300) { +- /* some R300 cards have problem with this set to 0, when CRTC2 is enabled.*/ +- critical_point = 0x10; +- } ++ /* ++ Find the critical point of the display buffer. ++ */ ++ critical_point= (uint32_t)(disp_drain_rate * disp_latency + 0.5); + +- temp = info->SavedReg->grph_buffer_cntl; +- temp &= ~(RADEON_GRPH_STOP_REQ_MASK); +- temp |= (stop_req << RADEON_GRPH_STOP_REQ_SHIFT); +- temp &= ~(RADEON_GRPH_START_REQ_MASK); +- if ((info->ChipFamily == CHIP_FAMILY_R350) && +- (stop_req > 0x15)) { +- stop_req -= 0x10; +- } +- temp |= (stop_req << RADEON_GRPH_START_REQ_SHIFT); ++ /* ???? */ ++ /* ++ temp = (info->SavedReg.grph_buffer_cntl & RADEON_GRPH_CRITICAL_POINT_MASK) >> RADEON_GRPH_CRITICAL_POINT_SHIFT; ++ if (critical_point < temp) critical_point = temp; ++ */ ++ if (info->DispPriority == 2) { ++ critical_point = 0; ++ } + +- temp |= RADEON_GRPH_BUFFER_SIZE; +- temp &= ~(RADEON_GRPH_CRITICAL_CNTL | +- RADEON_GRPH_CRITICAL_AT_SOF | +- RADEON_GRPH_STOP_CNTL); +- /* +- Write the result into the register. +- */ +- OUTREG(RADEON_GRPH_BUFFER_CNTL, ((temp & ~RADEON_GRPH_CRITICAL_POINT_MASK) | +- (critical_point << RADEON_GRPH_CRITICAL_POINT_SHIFT))); ++ /* ++ The critical point should never be above max_stop_req-4. Setting ++ GRPH_CRITICAL_CNTL = 0 will thus force high priority all the time. ++ */ ++ if (max_stop_req - critical_point < 4) critical_point = 0; ++ ++ if (critical_point == 0 && mode2 && info->ChipFamily == CHIP_FAMILY_R300) { ++ /* some R300 cards have problem with this set to 0, when CRTC2 is enabled.*/ ++ critical_point = 0x10; ++ } ++ ++ temp = info->SavedReg->grph_buffer_cntl; ++ temp &= ~(RADEON_GRPH_STOP_REQ_MASK); ++ temp |= (stop_req << RADEON_GRPH_STOP_REQ_SHIFT); ++ temp &= ~(RADEON_GRPH_START_REQ_MASK); ++ if ((info->ChipFamily == CHIP_FAMILY_R350) && ++ (stop_req > 0x15)) { ++ stop_req -= 0x10; ++ } ++ temp |= (stop_req << RADEON_GRPH_START_REQ_SHIFT); ++ ++ temp |= RADEON_GRPH_BUFFER_SIZE; ++ temp &= ~(RADEON_GRPH_CRITICAL_CNTL | ++ RADEON_GRPH_CRITICAL_AT_SOF | ++ RADEON_GRPH_STOP_CNTL); ++ /* ++ Write the result into the register. ++ */ ++ OUTREG(RADEON_GRPH_BUFFER_CNTL, ((temp & ~RADEON_GRPH_CRITICAL_POINT_MASK) | ++ (critical_point << RADEON_GRPH_CRITICAL_POINT_SHIFT))); + + #if 0 +- if ((info->ChipFamily == CHIP_FAMILY_RS400) || +- (info->ChipFamily == CHIP_FAMILY_RS480)) { +- /* attempt to program RS400 disp regs correctly ??? */ +- temp = info->SavedReg->disp1_req_cntl1; +- temp &= ~(RS400_DISP1_START_REQ_LEVEL_MASK | +- RS400_DISP1_STOP_REQ_LEVEL_MASK); +- OUTREG(RS400_DISP1_REQ_CNTL1, (temp | +- (critical_point << RS400_DISP1_START_REQ_LEVEL_SHIFT) | +- (critical_point << RS400_DISP1_STOP_REQ_LEVEL_SHIFT))); +- temp = info->SavedReg->dmif_mem_cntl1; +- temp &= ~(RS400_DISP1_CRITICAL_POINT_START_MASK | +- RS400_DISP1_CRITICAL_POINT_STOP_MASK); +- OUTREG(RS400_DMIF_MEM_CNTL1, (temp | +- (critical_point << RS400_DISP1_CRITICAL_POINT_START_SHIFT) | +- (critical_point << RS400_DISP1_CRITICAL_POINT_STOP_SHIFT))); +- } ++ if ((info->ChipFamily == CHIP_FAMILY_RS400) || ++ (info->ChipFamily == CHIP_FAMILY_RS480)) { ++ /* attempt to program RS400 disp regs correctly ??? */ ++ temp = info->SavedReg->disp1_req_cntl1; ++ temp &= ~(RS400_DISP1_START_REQ_LEVEL_MASK | ++ RS400_DISP1_STOP_REQ_LEVEL_MASK); ++ OUTREG(RS400_DISP1_REQ_CNTL1, (temp | ++ (critical_point << RS400_DISP1_START_REQ_LEVEL_SHIFT) | ++ (critical_point << RS400_DISP1_STOP_REQ_LEVEL_SHIFT))); ++ temp = info->SavedReg->dmif_mem_cntl1; ++ temp &= ~(RS400_DISP1_CRITICAL_POINT_START_MASK | ++ RS400_DISP1_CRITICAL_POINT_STOP_MASK); ++ OUTREG(RS400_DMIF_MEM_CNTL1, (temp | ++ (critical_point << RS400_DISP1_CRITICAL_POINT_START_SHIFT) | ++ (critical_point << RS400_DISP1_CRITICAL_POINT_STOP_SHIFT))); ++ } + #endif + +- xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG, +- "GRPH_BUFFER_CNTL from %x to %x\n", +- (unsigned int)info->SavedReg->grph_buffer_cntl, +- (unsigned int)INREG(RADEON_GRPH_BUFFER_CNTL)); ++ xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG, ++ "GRPH_BUFFER_CNTL from %x to %x\n", ++ (unsigned int)info->SavedReg->grph_buffer_cntl, ++ (unsigned int)INREG(RADEON_GRPH_BUFFER_CNTL)); ++ } + + if (mode2) { + stop_req = mode2->HDisplay * pixel_bytes2 / 16; + + if (stop_req > max_stop_req) stop_req = max_stop_req; + ++ /* ++ Find the drain rate of the display buffer. ++ */ ++ disp_drain_rate2 = pix_clk2 / (16.0/pixel_bytes2); ++ + temp = info->SavedReg->grph2_buffer_cntl; + temp &= ~(RADEON_GRPH_STOP_REQ_MASK); + temp |= (stop_req << RADEON_GRPH_STOP_REQ_SHIFT); +@@ -1629,7 +1641,10 @@ RADEONInitDispBandwidth2(ScrnInfoPtr pScrn, RADEONInfoPtr info, int pixel_bytes2 + critical_point2 = 0; + else { + read_return_rate = MIN(info->sclk, info->mclk*(info->RamWidth*(info->IsDDR+1)/128)); +- time_disp1_drop_priority = critical_point / (read_return_rate - disp_drain_rate); ++ if (mode1) ++ time_disp1_drop_priority = critical_point / (read_return_rate - disp_drain_rate); ++ else ++ time_disp1_drop_priority = 0; + + critical_point2 = (uint32_t)((disp_latency + time_disp1_drop_priority + + disp_latency) * disp_drain_rate2 + 0.5); +@@ -1681,45 +1696,6 @@ RADEONInitDispBandwidth2(ScrnInfoPtr pScrn, RADEONInfoPtr info, int pixel_bytes2 + } + + void +-RADEONInitDispBandwidth(ScrnInfoPtr pScrn) +-{ +- RADEONInfoPtr info = RADEONPTR(pScrn); +- xf86CrtcConfigPtr xf86_config = XF86_CRTC_CONFIG_PTR(pScrn); +- DisplayModePtr mode1, mode2; +- int pixel_bytes2 = 0; +- +- if (info->IsPrimary || info->IsSecondary) +- mode1 = &xf86_config->crtc[0]->mode; +- else +- mode1 = info->CurrentLayout.mode; +- mode2 = NULL; +- pixel_bytes2 = info->CurrentLayout.pixel_bytes; +- +- if (xf86_config->num_crtc == 2) { +- pixel_bytes2 = 0; +- mode2 = NULL; +- +- if (xf86_config->crtc[1]->enabled && xf86_config->crtc[0]->enabled) { +- pixel_bytes2 = info->CurrentLayout.pixel_bytes; +- mode1 = &xf86_config->crtc[0]->mode; +- mode2 = &xf86_config->crtc[1]->mode; +- } else if (xf86_config->crtc[0]->enabled) { +- mode1 = &xf86_config->crtc[0]->mode; +- } else if (xf86_config->crtc[1]->enabled) { +- mode1 = &xf86_config->crtc[1]->mode; +- } else +- return; +- } else { +- if (xf86_config->crtc[0]->enabled) +- mode1 = &xf86_config->crtc[0]->mode; +- else +- return; +- } +- +- RADEONInitDispBandwidth2(pScrn, info, pixel_bytes2, mode1, mode2); +-} +- +-void + legacy_crtc_mode_set(xf86CrtcPtr crtc, DisplayModePtr mode, + DisplayModePtr adjusted_mode, int x, int y) + { +diff --git a/src/legacy_output.c b/src/legacy_output.c +index 9c9ebb9..e5ddf1f 100644 +--- a/src/legacy_output.c ++++ b/src/legacy_output.c +@@ -48,6 +48,8 @@ + #include "radeon_tv.h" + #include "radeon_atombios.h" + ++#include "ati_pciids_gen.h" ++ + static RADEONMonitorType radeon_detect_tv(ScrnInfoPtr pScrn); + static RADEONMonitorType radeon_detect_primary_dac(ScrnInfoPtr pScrn, Bool color); + static RADEONMonitorType radeon_detect_tv_dac(ScrnInfoPtr pScrn, Bool color); +@@ -277,16 +279,12 @@ static void + RADEONRestoreDVOChip(ScrnInfoPtr pScrn, xf86OutputPtr output) + { + RADEONInfoPtr info = RADEONPTR(pScrn); +- unsigned char *RADEONMMIO = info->MMIO; + RADEONOutputPrivatePtr radeon_output = output->driver_private; + + if (!radeon_output->DVOChip) + return; + +- OUTREG(radeon_output->dvo_i2c.mask_clk_reg, +- INREG(radeon_output->dvo_i2c.mask_clk_reg) & +- (uint32_t)~(RADEON_GPIO_A_0 | RADEON_GPIO_A_1)); +- ++ RADEONI2CDoLock(output, TRUE); + if (!RADEONInitExtTMDSInfoFromBIOS(output)) { + if (radeon_output->DVOChip) { + switch(info->ext_tmds_chip) { +@@ -316,6 +314,7 @@ RADEONRestoreDVOChip(ScrnInfoPtr pScrn, xf86OutputPtr output) + } + } + } ++ RADEONI2CDoLock(output, FALSE); + } + + #if 0 +@@ -727,14 +726,6 @@ RADEONEnableDisplay(xf86OutputPtr output, BOOL bEnable) + save->crtc2_gen_cntl |= RADEON_CRTC2_CRT2_ON; + } + tv_dac_change = 1; +- /* IGP chips seem to use a mix of Primary and TVDAC controls */ +- if (info->IsIGP) { +- tmp = INREG(RADEON_CRTC_EXT_CNTL); +- tmp |= RADEON_CRTC_CRT_ON; +- OUTREG(RADEON_CRTC_EXT_CNTL, tmp); +- save->crtc_ext_cntl |= RADEON_CRTC_CRT_ON; +- RADEONDacPowerSet(pScrn, bEnable, TRUE); +- } + } + } else if (radeon_output->MonType == MT_DFP) { + if (radeon_output->TMDSType == TMDS_INT) { +@@ -815,14 +806,6 @@ RADEONEnableDisplay(xf86OutputPtr output, BOOL bEnable) + save->crtc2_gen_cntl &= ~RADEON_CRTC2_CRT2_ON; + } + } +- /* IGP chips seem to use a mix of Primary and TVDAC controls */ +- if (info->IsIGP) { +- tmp = INREG(RADEON_CRTC_EXT_CNTL); +- tmp &= ~RADEON_CRTC_CRT_ON; +- OUTREG(RADEON_CRTC_EXT_CNTL, tmp); +- save->crtc_ext_cntl &= ~RADEON_CRTC_CRT_ON; +- RADEONDacPowerSet(pScrn, bEnable, TRUE); +- } + } + } else if (radeon_output->MonType == MT_DFP) { + if (radeon_output->TMDSType == TMDS_INT) { +@@ -1033,9 +1016,14 @@ RADEONInitFP2Registers(xf86OutputPtr output, RADEONSavePtr save, + RADEON_FP2_DVO_RATE_SEL_SDR); + + +- /* XXX: these may be oem specific */ ++ /* XXX: these are oem specific */ + if (IS_R300_VARIANT) { +- save->fp2_gen_cntl |= RADEON_FP2_PAD_FLOP_EN | R300_FP2_DVO_CLOCK_MODE_SINGLE; ++ if ((info->Chipset == PCI_CHIP_RV350_NP) && ++ (PCI_SUB_VENDOR_ID(info->PciInfo) == 0x1028) && ++ (PCI_SUB_DEVICE_ID(info->PciInfo) == 0x2001)) ++ save->fp2_gen_cntl |= R300_FP2_DVO_CLOCK_MODE_SINGLE; /* Dell Inspiron 8600 */ ++ else ++ save->fp2_gen_cntl |= RADEON_FP2_PAD_FLOP_EN | R300_FP2_DVO_CLOCK_MODE_SINGLE; + #if 0 + if (mode->Clock > 165000) + save->fp2_gen_cntl |= R300_FP2_DVO_DUAL_CHANNEL_EN; +@@ -1383,7 +1371,6 @@ RADEONInitOutputRegisters(ScrnInfoPtr pScrn, RADEONSavePtr save, + { + Bool IsPrimary = crtc_num == 0 ? TRUE : FALSE; + RADEONOutputPrivatePtr radeon_output = output->driver_private; +- RADEONInfoPtr info = RADEONPTR(pScrn); + + if (crtc_num == 0) + RADEONInitRMXRegisters(output, save, mode); +@@ -1393,9 +1380,6 @@ RADEONInitOutputRegisters(ScrnInfoPtr pScrn, RADEONSavePtr save, + RADEONInitDACRegisters(output, save, mode, IsPrimary); + } else { + RADEONInitDAC2Registers(output, save, mode, IsPrimary); +- /* IGP chips seem to use a mix of primary and TVDAC controls */ +- if (info->IsIGP) +- RADEONInitDACRegisters(output, save, mode, IsPrimary); + } + } else if (radeon_output->MonType == MT_LCD) { + RADEONInitLVDSRegisters(output, save, mode, IsPrimary); +@@ -1456,8 +1440,8 @@ legacy_output_mode_set(xf86OutputPtr output, DisplayModePtr mode, + } + OUTREG(RADEON_FP2_GEN_CNTL, fp2_gen_cntl); + } else { +- RADEONRestoreDVOChip(pScrn, output); + RADEONRestoreFP2Registers(pScrn, info->ModeReg); ++ RADEONRestoreDVOChip(pScrn, output); + } + } + break; +diff --git a/src/pcidb/ati_pciids.csv b/src/pcidb/ati_pciids.csv +index 1f6fa82..364f4e1 100644 +--- a/src/pcidb/ati_pciids.csv ++++ b/src/pcidb/ati_pciids.csv +@@ -1,5 +1,6 @@ + "#pciid","define","family","mobility","igp","nocrtc2","Nointtvout","singledac","name" + "0x3150","RV380_3150","RV380",1,,,,,"ATI Radeon Mobility X600 (M24) 3150 (PCIE)" ++"0x3151","RV380_3151","RV380",,,,,,"ATI FireMV 2400 (PCI)" + "0x3152","RV380_3152","RV380",1,,,,,"ATI Radeon Mobility X300 (M24) 3152 (PCIE)" + "0x3154","RV380_3154","RV380",1,,,,,"ATI FireGL M24 GL 3154 (PCIE)" + "0x3E50","RV380_3E50","RV380",,,,,,"ATI Radeon X600 (RV380) 3E50 (PCIE)" +@@ -331,6 +332,8 @@ + "0x940A","R600_940A","R600",,,,,,"ATI FireGL V8650" + "0x940B","R600_940B","R600",,,,,,"ATI FireGL V8600" + "0x940F","R600_940F","R600",,,,,,"ATI FireGL V7600" ++"0x9440","RV770_9440","RV770",,,,,,"ATI Radeon 4800 Series" ++"0x9442","RV770_9442","RV770",,,,,,"ATI Radeon 4800 Series" + "0x94C0","RV610_94C0","RV610",,,,,,"ATI RV610" + "0x94C1","RV610_94C1","RV610",,,,,,"ATI Radeon HD 2400 XT" + "0x94C3","RV610_94C3","RV610",,,,,,"ATI Radeon HD 2400 Pro" +@@ -348,6 +351,7 @@ + "0x9507","RV670_9507","RV670",,,,,,"ATI RV670" + "0x950F","RV670_950F","RV670",,,,,,"ATI Radeon HD3870 X2" + "0x9511","RV670_9511","RV670",,,,,,"ATI FireGL V7700" ++"0x9515","RV670_9515","RV670",,,,,,"ATI Radeon HD3850" + "0x9580","RV630_9580","RV630",,,,,,"ATI RV630" + "0x9581","RV630_9581","RV630",1,,,,,"ATI Mobility Radeon HD 2600" + "0x9583","RV630_9583","RV630",1,,,,,"ATI Mobility Radeon HD 2600 XT" +diff --git a/src/radeon.h b/src/radeon.h +index 4f77c3b..63655b8 100644 +--- a/src/radeon.h ++++ b/src/radeon.h +@@ -98,6 +98,36 @@ + #define MIN(a,b) ((a)>(b)?(b):(a)) + #endif + ++#if HAVE_BYTESWAP_H ++#include ++#elif defined(USE_SYS_ENDIAN_H) ++#include ++#else ++#define bswap_16(value) \ ++ ((((value) & 0xff) << 8) | ((value) >> 8)) ++ ++#define bswap_32(value) \ ++ (((uint32_t)bswap_16((uint16_t)((value) & 0xffff)) << 16) | \ ++ (uint32_t)bswap_16((uint16_t)((value) >> 16))) ++ ++#define bswap_64(value) \ ++ (((uint64_t)bswap_32((uint32_t)((value) & 0xffffffff)) \ ++ << 32) | \ ++ (uint64_t)bswap_32((uint32_t)((value) >> 32))) ++#endif ++ ++#if X_BYTE_ORDER == X_BIG_ENDIAN ++#define le32_to_cpu(x) bswap_32(x) ++#define le16_to_cpu(x) bswap_16(x) ++#define cpu_to_le32(x) bswap_32(x) ++#define cpu_to_le16(x) bswap_16(x) ++#else ++#define le32_to_cpu(x) (x) ++#define le16_to_cpu(x) (x) ++#define cpu_to_le32(x) (x) ++#define cpu_to_le16(x) (x) ++#endif ++ + /* Provide substitutes for gcc's __FUNCTION__ on other compilers */ + #if !defined(__GNUC__) && !defined(__FUNCTION__) + # define __FUNCTION__ __func__ /* C99 */ +@@ -287,6 +317,7 @@ typedef enum { + CHIP_FAMILY_RV620, + CHIP_FAMILY_RV635, + CHIP_FAMILY_RS780, ++ CHIP_FAMILY_RV770, + CHIP_FAMILY_LAST + } RADEONChipFamily; + +@@ -567,7 +598,6 @@ typedef struct { + Bool CPRuns; /* CP is running */ + Bool CPInUse; /* CP has been used by X server */ + Bool CPStarted; /* CP has started */ +- int CPMode; /* CP mode that server/clients use */ + int CPFifoSize; /* Size of the CP command FIFO */ + int CPusecTimeout; /* CP timeout in usecs */ + Bool needCacheFlush; +@@ -787,7 +817,6 @@ do { \ + extern void legacy_crtc_dpms(xf86CrtcPtr crtc, int mode); + extern void legacy_crtc_mode_set(xf86CrtcPtr crtc, DisplayModePtr mode, + DisplayModePtr adjusted_mode, int x, int y); +-extern void RADEONInitDispBandwidth(ScrnInfoPtr pScrn); + extern void RADEONRestoreCommonRegisters(ScrnInfoPtr pScrn, + RADEONSavePtr restore); + extern void RADEONRestoreCrtcRegisters(ScrnInfoPtr pScrn, +@@ -872,6 +901,7 @@ extern Bool RADEONGetTMDSInfoFromBIOS(xf86OutputPtr output); + extern Bool RADEONGetTVInfoFromBIOS(xf86OutputPtr output); + extern Bool RADEONInitExtTMDSInfoFromBIOS (xf86OutputPtr output); + extern Bool RADEONPostCardFromBIOSTables(ScrnInfoPtr pScrn); ++extern Bool radeon_card_posted(ScrnInfoPtr pScrn); + + /* radeon_commonfuncs.c */ + #ifdef XF86DRI +@@ -894,6 +924,7 @@ extern DisplayModePtr RADEONCrtcFindClosestMode(xf86CrtcPtr crtc, + DisplayModePtr pMode); + extern void RADEONUnblank(ScrnInfoPtr pScrn); + extern Bool RADEONSetTiling(ScrnInfoPtr pScrn); ++extern void RADEONInitDispBandwidth(ScrnInfoPtr pScrn); + + /* radeon_cursor.c */ + extern Bool RADEONCursorInit(ScreenPtr pScreen); +@@ -983,6 +1014,8 @@ extern void RADEONPrintPortMap(ScrnInfoPtr pScrn); + extern void RADEONSetOutputType(ScrnInfoPtr pScrn, + RADEONOutputPrivatePtr radeon_output); + extern Bool RADEONSetupConnectors(ScrnInfoPtr pScrn); ++extern Bool RADEONI2CDoLock(xf86OutputPtr output, Bool lock_state); ++ + + /* radeon_tv.c */ + extern void RADEONSaveTVRegisters(ScrnInfoPtr pScrn, RADEONSavePtr save); +@@ -1046,13 +1079,11 @@ do { \ + + #define RADEONCP_RESET(pScrn, info) \ + do { \ +- if (RADEONCP_USE_RING_BUFFER(info->CPMode)) { \ + int _ret = drmCommandNone(info->drmFD, DRM_RADEON_CP_RESET); \ + if (_ret) { \ + xf86DrvMsg(pScrn->scrnIndex, X_ERROR, \ + "%s: CP reset %d\n", __FUNCTION__, _ret); \ + } \ +- } \ + } while (0) + + #define RADEONCP_REFRESH(pScrn, info) \ +diff --git a/src/radeon_accel.c b/src/radeon_accel.c +index 65ad33d..91f463a 100644 +--- a/src/radeon_accel.c ++++ b/src/radeon_accel.c +@@ -1046,18 +1046,6 @@ RADEONSetupMemXAA_DRI(int scrnIndex, ScreenPtr pScreen) + depthSize = ((((pScrn->virtualY + 15) & ~15) * info->depthPitch + * depthCpp + RADEON_BUFFER_ALIGN) & ~RADEON_BUFFER_ALIGN); + +- switch (info->CPMode) { +- case RADEON_DEFAULT_CP_PIO_MODE: +- xf86DrvMsg(pScrn->scrnIndex, X_INFO, "CP in PIO mode\n"); +- break; +- case RADEON_DEFAULT_CP_BM_MODE: +- xf86DrvMsg(pScrn->scrnIndex, X_INFO, "CP in BM mode\n"); +- break; +- default: +- xf86DrvMsg(pScrn->scrnIndex, X_INFO, "CP in UNKNOWN mode\n"); +- break; +- } +- + xf86DrvMsg(pScrn->scrnIndex, X_INFO, + "Using %d MB GART aperture\n", info->gartSize); + xf86DrvMsg(pScrn->scrnIndex, X_INFO, +diff --git a/src/radeon_atombios.c b/src/radeon_atombios.c +index 20aa722..f0a3a31 100644 +--- a/src/radeon_atombios.c ++++ b/src/radeon_atombios.c +@@ -501,11 +501,11 @@ rhdAtomASICInit(atomBiosHandlePtr handle) + RHDAtomBiosFunc(handle->scrnIndex, handle, + GET_DEFAULT_ENGINE_CLOCK, + &data); +- asicInit.sASICInitClocks.ulDefaultEngineClock = data.val / 10;/*in 10 Khz*/ ++ asicInit.sASICInitClocks.ulDefaultEngineClock = cpu_to_le32(data.val / 10);/*in 10 Khz*/ + RHDAtomBiosFunc(handle->scrnIndex, handle, + GET_DEFAULT_MEMORY_CLOCK, + &data); +- asicInit.sASICInitClocks.ulDefaultMemoryClock = data.val / 10;/*in 10 Khz*/ ++ asicInit.sASICInitClocks.ulDefaultMemoryClock = cpu_to_le32(data.val / 10);/*in 10 Khz*/ + data.exec.dataSpace = NULL; + data.exec.index = 0x0; + data.exec.pspace = &asicInit; +@@ -609,17 +609,6 @@ rhdAtomInit(atomBiosHandlePtr unused1, AtomBiosRequestID unused2, + #endif + handle->BIOSImageSize = BIOSImageSize; + +-# if ATOM_BIOS_PARSER +- /* Try to find out if BIOS has been posted (either by system or int10 */ +- if (!rhdAtomGetFbBaseAndSize(handle, NULL, NULL)) { +- /* run AsicInit */ +- if (!rhdAtomASICInit(handle)) +- xf86DrvMsg(scrnIndex, X_WARNING, +- "%s: AsicInit failed. Won't be able to obtain in VRAM " +- "FB scratch space\n",__func__); +- } +-# endif +- + data->atomhandle = handle; + return ATOM_SUCCESS; + +@@ -654,12 +643,18 @@ rhdAtomVramInfoQuery(atomBiosHandlePtr handle, AtomBiosRequestID func, + + switch (func) { + case GET_FW_FB_START: +- *val = le32_to_cpu(atomDataPtr->VRAM_UsageByFirmware +- ->asFirmwareVramReserveInfo[0].ulStartAddrUsedByFirmware); ++ if (atomDataPtr->VRAM_UsageByFirmware) ++ *val = le32_to_cpu(atomDataPtr->VRAM_UsageByFirmware ++ ->asFirmwareVramReserveInfo[0].ulStartAddrUsedByFirmware); ++ else ++ return ATOM_NOT_IMPLEMENTED; + break; + case GET_FW_FB_SIZE: +- *val = le16_to_cpu(atomDataPtr->VRAM_UsageByFirmware +- ->asFirmwareVramReserveInfo[0].usFirmwareUseInKb); ++ if (atomDataPtr->VRAM_UsageByFirmware) ++ *val = le16_to_cpu(atomDataPtr->VRAM_UsageByFirmware ++ ->asFirmwareVramReserveInfo[0].usFirmwareUseInKb); ++ else ++ return ATOM_NOT_IMPLEMENTED; + break; + default: + return ATOM_NOT_IMPLEMENTED; +@@ -1391,36 +1386,6 @@ const int object_connector_convert[] = + CONNECTOR_DISPLAY_PORT, + }; + +-static void +-rhdAtomParseI2CRecord(atomBiosHandlePtr handle, +- ATOM_I2C_RECORD *Record, int *ddc_line) +-{ +- ErrorF(" %s: I2C Record: %s[%x] EngineID: %x I2CAddr: %x\n", +- __func__, +- Record->sucI2cId.bfHW_Capable ? "HW_Line" : "GPIO_ID", +- Record->sucI2cId.bfI2C_LineMux, +- Record->sucI2cId.bfHW_EngineID, +- Record->ucI2CAddr); +- +- if (!*(unsigned char *)&(Record->sucI2cId)) +- *ddc_line = 0; +- else { +- if (Record->ucI2CAddr != 0) +- return; +- +- if (Record->sucI2cId.bfHW_Capable) { +- switch(Record->sucI2cId.bfI2C_LineMux) { +- case 0: *ddc_line = 0x7e40; break; +- case 1: *ddc_line = 0x7e50; break; +- case 2: *ddc_line = 0x7e30; break; +- default: break; +- } +- return; +- } else { +- /* add GPIO pin parsing */ +- } +- } +-} + + static RADEONI2CBusRec + RADEONLookupGPIOLineForDDC(ScrnInfoPtr pScrn, uint8_t id) +@@ -1450,12 +1415,16 @@ RADEONLookupGPIOLineForDDC(ScrnInfoPtr pScrn, uint8_t id) + i2c.put_data_reg = le16_to_cpu(gpio.usDataEnRegisterIndex) * 4; + i2c.get_clk_reg = le16_to_cpu(gpio.usClkY_RegisterIndex) * 4; + i2c.get_data_reg = le16_to_cpu(gpio.usDataY_RegisterIndex) * 4; ++ i2c.a_clk_reg = le16_to_cpu(gpio.usClkA_RegisterIndex) * 4; ++ i2c.a_data_reg = le16_to_cpu(gpio.usDataA_RegisterIndex) * 4; + i2c.mask_clk_mask = (1 << gpio.ucClkMaskShift); + i2c.mask_data_mask = (1 << gpio.ucDataMaskShift); + i2c.put_clk_mask = (1 << gpio.ucClkEnShift); + i2c.put_data_mask = (1 << gpio.ucDataEnShift); + i2c.get_clk_mask = (1 << gpio.ucClkY_Shift); + i2c.get_data_mask = (1 << gpio.ucDataY_Shift); ++ i2c.a_clk_mask = (1 << gpio.ucClkA_Shift); ++ i2c.a_data_mask = (1 << gpio.ucDataA_Shift); + i2c.valid = TRUE; + + #if 0 +@@ -1465,21 +1434,28 @@ RADEONLookupGPIOLineForDDC(ScrnInfoPtr pScrn, uint8_t id) + ErrorF("put_data_reg: 0x%x\n", gpio.usDataEnRegisterIndex * 4); + ErrorF("get_clk_reg: 0x%x\n", gpio.usClkY_RegisterIndex * 4); + ErrorF("get_data_reg: 0x%x\n", gpio.usDataY_RegisterIndex * 4); +- ErrorF("other_clk_reg: 0x%x\n", gpio.usClkA_RegisterIndex * 4); +- ErrorF("other_data_reg: 0x%x\n", gpio.usDataA_RegisterIndex * 4); ++ ErrorF("a_clk_reg: 0x%x\n", gpio.usClkA_RegisterIndex * 4); ++ ErrorF("a_data_reg: 0x%x\n", gpio.usDataA_RegisterIndex * 4); + ErrorF("mask_clk_mask: %d\n", gpio.ucClkMaskShift); + ErrorF("mask_data_mask: %d\n", gpio.ucDataMaskShift); + ErrorF("put_clk_mask: %d\n", gpio.ucClkEnShift); + ErrorF("put_data_mask: %d\n", gpio.ucDataEnShift); + ErrorF("get_clk_mask: %d\n", gpio.ucClkY_Shift); + ErrorF("get_data_mask: %d\n", gpio.ucDataY_Shift); +- ErrorF("other_clk_mask: %d\n", gpio.ucClkA_Shift); +- ErrorF("other_data_mask: %d\n", gpio.ucDataA_Shift); ++ ErrorF("a_clk_mask: %d\n", gpio.ucClkA_Shift); ++ ErrorF("a_data_mask: %d\n", gpio.ucDataA_Shift); + #endif + + return i2c; + } + ++static RADEONI2CBusRec ++rhdAtomParseI2CRecord(ScrnInfoPtr pScrn, atomBiosHandlePtr handle, ++ ATOM_I2C_RECORD *Record) ++{ ++ return RADEONLookupGPIOLineForDDC(pScrn, Record->sucI2cId.bfI2C_LineMux); ++} ++ + Bool + RADEONGetATOMConnectorInfoFromBIOSObject (ScrnInfoPtr pScrn) + { +@@ -1489,7 +1465,7 @@ RADEONGetATOMConnectorInfoFromBIOSObject (ScrnInfoPtr pScrn) + atomDataTablesPtr atomDataPtr; + ATOM_CONNECTOR_OBJECT_TABLE *con_obj; + ATOM_INTEGRATED_SYSTEM_INFO_V2 *igp_obj = NULL; +- int i, j, ddc_line = 0; ++ int i, j; + + atomDataPtr = info->atomBIOS->atomDataPtr; + if (!rhdAtomGetTableRevisionAndSize((ATOM_COMMON_TABLE_HEADER *)(atomDataPtr->Object_Header), &crev, &frev, &size)) +@@ -1617,10 +1593,8 @@ RADEONGetATOMConnectorInfoFromBIOSObject (ScrnInfoPtr pScrn) + ErrorF("record type %d\n", Record->ucRecordType); + switch (Record->ucRecordType) { + case ATOM_I2C_RECORD_TYPE: +- rhdAtomParseI2CRecord(info->atomBIOS, +- (ATOM_I2C_RECORD *)Record, +- &ddc_line); +- info->BiosConnector[i].ddc_i2c = atom_setup_i2c_bus(ddc_line); ++ info->BiosConnector[i].ddc_i2c = rhdAtomParseI2CRecord(pScrn, info->atomBIOS, ++ (ATOM_I2C_RECORD *)Record); + break; + case ATOM_HPD_INT_RECORD_TYPE: + break; +@@ -1751,6 +1725,15 @@ static void RADEONApplyATOMQuirks(ScrnInfoPtr pScrn, int index) + } + } + ++ /* Falcon NW laptop lists vga ddc line for LVDS */ ++ if ((info->Chipset == PCI_CHIP_RV410_5653) && ++ (PCI_SUB_VENDOR_ID(info->PciInfo) == 0x1462) && ++ (PCI_SUB_DEVICE_ID(info->PciInfo) == 0x0291)) { ++ if (info->BiosConnector[index].ConnectorType == CONNECTOR_LVDS) { ++ info->BiosConnector[index].ddc_i2c.valid = FALSE; ++ } ++ } ++ + } + + Bool +@@ -2027,9 +2010,12 @@ RHDAtomBiosFunc(int scrnIndex, atomBiosHandlePtr handle, + VOID* + CailAllocateMemory(VOID *CAIL,UINT16 size) + { ++ void *ret; + CAILFUNC(CAIL); + +- return malloc(size); ++ ret = malloc(size); ++ memset(ret, 0, size); ++ return ret; + } + + VOID +@@ -2256,4 +2242,15 @@ atombios_get_command_table_version(atomBiosHandlePtr atomBIOS, int index, int *m + } + + ++UINT16 ATOM_BSWAP16(UINT16 x) ++{ ++ return bswap_16(x); ++} ++ ++UINT32 ATOM_BSWAP32(UINT32 x) ++{ ++ return bswap_32(x); ++} ++ ++ + #endif /* ATOM_BIOS */ +diff --git a/src/radeon_atomwrapper.c b/src/radeon_atomwrapper.c +index 3e7ae01..bed1471 100644 +--- a/src/radeon_atomwrapper.c ++++ b/src/radeon_atomwrapper.c +@@ -31,6 +31,7 @@ + + #define INT32 INT32 + #include "CD_Common_Types.h" ++#include "atombios.h" + #include "CD_Definitions.h" + + +diff --git a/src/radeon_bios.c b/src/radeon_bios.c +index 529dda7..b34a421 100644 +--- a/src/radeon_bios.c ++++ b/src/radeon_bios.c +@@ -266,6 +266,26 @@ radeon_read_unposted_bios(ScrnInfoPtr pScrn) + return ret; + } + ++Bool ++radeon_card_posted(ScrnInfoPtr pScrn) ++{ ++ RADEONInfoPtr info = RADEONPTR(pScrn); ++ unsigned char *RADEONMMIO = info->MMIO; ++ uint32_t reg; ++ ++ if (IS_AVIVO_VARIANT) { ++ reg = INREG(AVIVO_D1CRTC_CONTROL) | INREG(AVIVO_D2CRTC_CONTROL); ++ if (reg & AVIVO_CRTC_EN) ++ return TRUE; ++ } else { ++ reg = INREG(RADEON_CRTC_GEN_CNTL) | INREG(RADEON_CRTC2_GEN_CNTL); ++ if (reg & RADEON_CRTC_EN) ++ return TRUE; ++ } ++ ++ return FALSE; ++} ++ + /* Read the Video BIOS block and the FP registers (if applicable). */ + Bool + RADEONGetBIOSInfo(ScrnInfoPtr pScrn, xf86Int10InfoPtr pInt10) +@@ -273,6 +293,7 @@ RADEONGetBIOSInfo(ScrnInfoPtr pScrn, xf86Int10InfoPtr pInt10) + RADEONInfoPtr info = RADEONPTR(pScrn); + int tmp; + unsigned short dptr; ++ Bool posted = TRUE; + + #ifdef XSERVER_LIBPCIACCESS + int size = info->PciInfo->rom_size > RADEON_VBIOS_SIZE ? info->PciInfo->rom_size : RADEON_VBIOS_SIZE; +@@ -291,6 +312,7 @@ RADEONGetBIOSInfo(ScrnInfoPtr pScrn, xf86Int10InfoPtr pInt10) + RADEON_VBIOS_SIZE); + } else if (!radeon_read_bios(pScrn)) { + (void)radeon_read_unposted_bios(pScrn); ++ posted = FALSE; + } + } + +@@ -326,7 +348,7 @@ RADEONGetBIOSInfo(ScrnInfoPtr pScrn, xf86Int10InfoPtr pInt10) + info->VBIOS = NULL; + return FALSE; + } +- ++ + tmp = info->ROMHeaderStart + 4; + if ((RADEON_BIOS8(tmp) == 'A' && + RADEON_BIOS8(tmp+1) == 'T' && +@@ -344,51 +366,65 @@ RADEONGetBIOSInfo(ScrnInfoPtr pScrn, xf86Int10InfoPtr pInt10) + info->IsAtomBios ? "ATOM":"Legacy"); + + if (info->IsAtomBios) { +- AtomBiosArgRec atomBiosArg; ++ AtomBiosArgRec atomBiosArg; + +- if (RHDAtomBiosFunc(pScrn->scrnIndex, NULL, ATOMBIOS_INIT, &atomBiosArg) +- == ATOM_SUCCESS) { +- info->atomBIOS = atomBiosArg.atomhandle; +- } ++ if (RHDAtomBiosFunc(pScrn->scrnIndex, NULL, ATOMBIOS_INIT, &atomBiosArg) ++ == ATOM_SUCCESS) { ++ info->atomBIOS = atomBiosArg.atomhandle; ++ } + +- atomBiosArg.fb.start = info->FbFreeStart; +- atomBiosArg.fb.size = info->FbFreeSize; +- if (RHDAtomBiosFunc(pScrn->scrnIndex, info->atomBIOS, ATOMBIOS_ALLOCATE_FB_SCRATCH, ++ atomBiosArg.fb.start = info->FbFreeStart; ++ atomBiosArg.fb.size = info->FbFreeSize; ++ if (RHDAtomBiosFunc(pScrn->scrnIndex, info->atomBIOS, ATOMBIOS_ALLOCATE_FB_SCRATCH, + &atomBiosArg) == ATOM_SUCCESS) { + + info->FbFreeStart = atomBiosArg.fb.start; + info->FbFreeSize = atomBiosArg.fb.size; +- } +- +- RHDAtomBiosFunc(pScrn->scrnIndex, info->atomBIOS, GET_DEFAULT_ENGINE_CLOCK, +- &atomBiosArg); +- RHDAtomBiosFunc(pScrn->scrnIndex, info->atomBIOS, GET_DEFAULT_MEMORY_CLOCK, +- &atomBiosArg); +- RHDAtomBiosFunc(pScrn->scrnIndex, info->atomBIOS, +- GET_MAX_PIXEL_CLOCK_PLL_OUTPUT, &atomBiosArg); +- RHDAtomBiosFunc(pScrn->scrnIndex, info->atomBIOS, +- GET_MIN_PIXEL_CLOCK_PLL_OUTPUT, &atomBiosArg); +- RHDAtomBiosFunc(pScrn->scrnIndex, info->atomBIOS, +- GET_MAX_PIXEL_CLOCK_PLL_INPUT, &atomBiosArg); +- RHDAtomBiosFunc(pScrn->scrnIndex, info->atomBIOS, ++ } ++ ++ RHDAtomBiosFunc(pScrn->scrnIndex, info->atomBIOS, GET_DEFAULT_ENGINE_CLOCK, ++ &atomBiosArg); ++ RHDAtomBiosFunc(pScrn->scrnIndex, info->atomBIOS, GET_DEFAULT_MEMORY_CLOCK, ++ &atomBiosArg); ++ RHDAtomBiosFunc(pScrn->scrnIndex, info->atomBIOS, ++ GET_MAX_PIXEL_CLOCK_PLL_OUTPUT, &atomBiosArg); ++ RHDAtomBiosFunc(pScrn->scrnIndex, info->atomBIOS, ++ GET_MIN_PIXEL_CLOCK_PLL_OUTPUT, &atomBiosArg); ++ RHDAtomBiosFunc(pScrn->scrnIndex, info->atomBIOS, ++ GET_MAX_PIXEL_CLOCK_PLL_INPUT, &atomBiosArg); ++ RHDAtomBiosFunc(pScrn->scrnIndex, info->atomBIOS, + GET_MIN_PIXEL_CLOCK_PLL_INPUT, &atomBiosArg); +- RHDAtomBiosFunc(pScrn->scrnIndex, info->atomBIOS, ++ RHDAtomBiosFunc(pScrn->scrnIndex, info->atomBIOS, + GET_MAX_PIXEL_CLK, &atomBiosArg); +- RHDAtomBiosFunc(pScrn->scrnIndex, info->atomBIOS, +- GET_REF_CLOCK, &atomBiosArg); ++ RHDAtomBiosFunc(pScrn->scrnIndex, info->atomBIOS, ++ GET_REF_CLOCK, &atomBiosArg); + + info->MasterDataStart = RADEON_BIOS16 (info->ROMHeaderStart + 32); + } ++ ++ /* We are a bit too quick at using this "unposted" to re-post the ++ * card. This causes some problems with VT switch on some machines, ++ * so let's work around this for now by only POSTing if none of the ++ * CRTCs are enabled ++ */ ++ if ((!posted) && info->VBIOS) { ++ posted = radeon_card_posted(pScrn); ++ } ++ ++ if ((!posted) && info->VBIOS) { ++ if (info->IsAtomBios) { ++ if (!rhdAtomASICInit(info->atomBIOS)) ++ xf86DrvMsg(pScrn->scrnIndex, X_WARNING, ++ "%s: AsicInit failed.\n",__func__); ++ } else { + #if 0 +- else { +- /* non-primary card may need posting */ +- if (!pInt10) { +- xf86DrvMsg(pScrn->scrnIndex, X_INFO, "Attempting to POST via BIOS tables\n"); ++ xf86DrvMsg(pScrn->scrnIndex, X_INFO, "Attempting to POST via legacy BIOS tables\n"); + RADEONGetBIOSInitTableOffsets(pScrn); + RADEONPostCardFromBIOSTables(pScrn); ++#endif + } + } +-#endif ++ + return TRUE; + } + +@@ -397,7 +433,7 @@ static Bool RADEONGetATOMConnectorInfoFromBIOS (ScrnInfoPtr pScrn) + RADEONInfoPtr info = RADEONPTR (pScrn); + + if (!info->VBIOS) return FALSE; +- ++ + if (RADEONGetATOMConnectorInfoFromBIOSObject(pScrn)) + return TRUE; + +@@ -411,28 +447,41 @@ static void RADEONApplyLegacyQuirks(ScrnInfoPtr pScrn, int index) + { + RADEONInfoPtr info = RADEONPTR (pScrn); + +- /* on XPRESS chips, CRT2_DDC and MONID_DCC both use the +- * MONID gpio, but use different pins. +- * CRT2_DDC uses the standard pinout, MONID_DDC uses +- * something else. ++ /* For RS300/RS350/RS400 chips, there is no primary DAC. Force VGA port to use TVDAC ++ * Also there is no internal TMDS + */ ++ if ((info->ChipFamily == CHIP_FAMILY_RS300) || ++ (info->ChipFamily == CHIP_FAMILY_RS400) || ++ (info->ChipFamily == CHIP_FAMILY_RS480)) { ++ info->BiosConnector[index].DACType = DAC_TVDAC; ++ info->BiosConnector[index].TMDSType = TMDS_EXT; ++ } ++ ++ /* XPRESS DDC quirks */ + if ((info->ChipFamily == CHIP_FAMILY_RS400 || + info->ChipFamily == CHIP_FAMILY_RS480) && +- info->BiosConnector[index].ConnectorType == CONNECTOR_VGA && + info->BiosConnector[index].ddc_i2c.mask_clk_reg == RADEON_GPIO_CRT2_DDC) { + info->BiosConnector[index].ddc_i2c = legacy_setup_i2c_bus(RADEON_GPIO_MONID); +- } +- +- /* XPRESS desktop chips seem to have a proprietary connector listed for +- * DVI-D, try and do the right thing here. +- */ +- if ((!info->IsMobility) && +- (info->BiosConnector[index].ConnectorType == CONNECTOR_LVDS)) { +- xf86DrvMsg(pScrn->scrnIndex, X_WARNING, +- "Proprietary connector found, assuming DVI-D\n"); +- info->BiosConnector[index].DACType = DAC_NONE; +- info->BiosConnector[index].TMDSType = TMDS_EXT; +- info->BiosConnector[index].ConnectorType = CONNECTOR_DVI_D; ++ } else if ((info->ChipFamily == CHIP_FAMILY_RS400 || ++ info->ChipFamily == CHIP_FAMILY_RS480) && ++ info->BiosConnector[index].ddc_i2c.mask_clk_reg == RADEON_GPIO_MONID) { ++ info->BiosConnector[index].ddc_i2c.valid = TRUE; ++ info->BiosConnector[index].ddc_i2c.mask_clk_mask = (0x20 << 8); ++ info->BiosConnector[index].ddc_i2c.mask_data_mask = 0x80; ++ info->BiosConnector[index].ddc_i2c.a_clk_mask = (0x20 << 8); ++ info->BiosConnector[index].ddc_i2c.a_data_mask = 0x80; ++ info->BiosConnector[index].ddc_i2c.put_clk_mask = (0x20 << 8); ++ info->BiosConnector[index].ddc_i2c.put_data_mask = 0x80; ++ info->BiosConnector[index].ddc_i2c.get_clk_mask = (0x20 << 8); ++ info->BiosConnector[index].ddc_i2c.get_data_mask = 0x80; ++ info->BiosConnector[index].ddc_i2c.mask_clk_reg = RADEON_GPIOPAD_MASK; ++ info->BiosConnector[index].ddc_i2c.mask_data_reg = RADEON_GPIOPAD_MASK; ++ info->BiosConnector[index].ddc_i2c.a_clk_reg = RADEON_GPIOPAD_A; ++ info->BiosConnector[index].ddc_i2c.a_data_reg = RADEON_GPIOPAD_A; ++ info->BiosConnector[index].ddc_i2c.put_clk_reg = RADEON_GPIOPAD_EN; ++ info->BiosConnector[index].ddc_i2c.put_data_reg = RADEON_GPIOPAD_EN; ++ info->BiosConnector[index].ddc_i2c.get_clk_reg = RADEON_LCD_GPIO_Y_REG; ++ info->BiosConnector[index].ddc_i2c.get_data_reg = RADEON_LCD_GPIO_Y_REG; + } + + /* Certain IBM chipset RN50s have a BIOS reporting two VGAs, +@@ -454,6 +503,16 @@ static void RADEONApplyLegacyQuirks(ScrnInfoPtr pScrn, int index) + } + } + ++ /* X300 card with extra non-existent DVI port */ ++ if (info->Chipset == PCI_CHIP_RV370_5B60 && ++ PCI_SUB_VENDOR_ID(info->PciInfo) == 0x17af && ++ PCI_SUB_DEVICE_ID(info->PciInfo) == 0x201e && ++ index == 2) { ++ if (info->BiosConnector[index].ConnectorType == CONNECTOR_DVI_I) { ++ info->BiosConnector[index].valid = FALSE; ++ } ++ } ++ + } + + static Bool RADEONGetLegacyConnectorInfoFromBIOS (ScrnInfoPtr pScrn) +@@ -479,7 +538,7 @@ static Bool RADEONGetLegacyConnectorInfoFromBIOS (ScrnInfoPtr pScrn) + ConnectorType = (tmp >> 12) & 0xf; + switch (ConnectorType) { + case CONNECTOR_PROPRIETARY_LEGACY: +- info->BiosConnector[i].ConnectorType = CONNECTOR_LVDS; ++ info->BiosConnector[i].ConnectorType = CONNECTOR_DVI_D; + break; + case CONNECTOR_CRT_LEGACY: + info->BiosConnector[i].ConnectorType = CONNECTOR_VGA; +@@ -528,10 +587,6 @@ static Bool RADEONGetLegacyConnectorInfoFromBIOS (ScrnInfoPtr pScrn) + else + info->BiosConnector[i].DACType = DAC_PRIMARY; + +- /* For RS300/RS350/RS400 chips, there is no primary DAC. Force VGA port to use TVDAC*/ +- if (info->IsIGP) +- info->BiosConnector[i].DACType = DAC_TVDAC; +- + if ((tmp >> 4) & 0x1) + info->BiosConnector[i].TMDSType = TMDS_EXT; + else +@@ -560,7 +615,10 @@ static Bool RADEONGetLegacyConnectorInfoFromBIOS (ScrnInfoPtr pScrn) + } + + /* check LVDS table */ +- if (info->IsMobility) { ++ /* RS4xx can be mobile or desktop so check the connectors */ ++ if (info->IsMobility || ++ info->ChipFamily == CHIP_FAMILY_RS400 || ++ info->ChipFamily == CHIP_FAMILY_RS480) { + offset = RADEON_BIOS16(info->ROMHeaderStart + 0x40); + if (offset) { + info->BiosConnector[4].valid = TRUE; +@@ -591,10 +649,10 @@ static Bool RADEONGetLegacyConnectorInfoFromBIOS (ScrnInfoPtr pScrn) + break; + case DDC_LCD: + info->BiosConnector[4].ddc_i2c = legacy_setup_i2c_bus(RADEON_LCD_GPIO_MASK); +- info->BiosConnector[4].ddc_i2c.mask_clk_mask = +- RADEON_BIOS32(tmp0 + 0x03) | RADEON_BIOS32(tmp0 + 0x07); +- info->BiosConnector[4].ddc_i2c.mask_data_mask = +- RADEON_BIOS32(tmp0 + 0x03) | RADEON_BIOS32(tmp0 + 0x07); ++ info->BiosConnector[4].ddc_i2c.mask_clk_mask = RADEON_BIOS32(tmp0 + 0x03); ++ info->BiosConnector[4].ddc_i2c.mask_data_mask = RADEON_BIOS32(tmp0 + 0x07); ++ info->BiosConnector[4].ddc_i2c.a_clk_mask = RADEON_BIOS32(tmp0 + 0x03); ++ info->BiosConnector[4].ddc_i2c.a_data_mask = RADEON_BIOS32(tmp0 + 0x07); + info->BiosConnector[4].ddc_i2c.put_clk_mask = RADEON_BIOS32(tmp0 + 0x03); + info->BiosConnector[4].ddc_i2c.put_data_mask = RADEON_BIOS32(tmp0 + 0x07); + info->BiosConnector[4].ddc_i2c.get_clk_mask = RADEON_BIOS32(tmp0 + 0x03); +@@ -602,10 +660,10 @@ static Bool RADEONGetLegacyConnectorInfoFromBIOS (ScrnInfoPtr pScrn) + break; + case DDC_GPIO: + info->BiosConnector[4].ddc_i2c = legacy_setup_i2c_bus(RADEON_MDGPIO_EN_REG); +- info->BiosConnector[4].ddc_i2c.mask_clk_mask = +- RADEON_BIOS32(tmp0 + 0x03) | RADEON_BIOS32(tmp0 + 0x07); +- info->BiosConnector[4].ddc_i2c.mask_data_mask = +- RADEON_BIOS32(tmp0 + 0x03) | RADEON_BIOS32(tmp0 + 0x07); ++ info->BiosConnector[4].ddc_i2c.mask_clk_mask = RADEON_BIOS32(tmp0 + 0x03); ++ info->BiosConnector[4].ddc_i2c.mask_data_mask = RADEON_BIOS32(tmp0 + 0x07); ++ info->BiosConnector[4].ddc_i2c.a_clk_mask = RADEON_BIOS32(tmp0 + 0x03); ++ info->BiosConnector[4].ddc_i2c.a_data_mask = RADEON_BIOS32(tmp0 + 0x07); + info->BiosConnector[4].ddc_i2c.put_clk_mask = RADEON_BIOS32(tmp0 + 0x03); + info->BiosConnector[4].ddc_i2c.put_data_mask = RADEON_BIOS32(tmp0 + 0x07); + info->BiosConnector[4].ddc_i2c.get_clk_mask = RADEON_BIOS32(tmp0 + 0x03); +@@ -1118,6 +1176,50 @@ Bool RADEONGetTMDSInfoFromBIOS (xf86OutputPtr output) + return FALSE; + } + ++static RADEONI2CBusRec ++RADEONLookupI2CBlock(ScrnInfoPtr pScrn, int id) ++{ ++ RADEONInfoPtr info = RADEONPTR (pScrn); ++ int offset, blocks, i; ++ RADEONI2CBusRec i2c; ++ ++ memset(&i2c, 0, sizeof(RADEONI2CBusRec)); ++ i2c.valid = FALSE; ++ ++ offset = RADEON_BIOS16(info->ROMHeaderStart + 0x70); ++ if (offset) { ++ blocks = RADEON_BIOS8(offset + 2); ++ for (i = 0; i < blocks; i++) { ++ int i2c_id = RADEON_BIOS8(offset + 3 + (i * 5) + 0); ++ if (id == i2c_id) { ++ int reg = RADEON_BIOS16(offset + 3 + (i * 5) + 1) * 4; ++ int clock_shift = RADEON_BIOS8(offset + 3 + (i * 5) + 3); ++ int data_shift = RADEON_BIOS8(offset + 3 + (i * 5) + 4); ++ ++ i2c.mask_clk_mask = (1 << clock_shift); ++ i2c.mask_data_mask = (1 << data_shift); ++ i2c.a_clk_mask = (1 << clock_shift); ++ i2c.a_data_mask = (1 << data_shift); ++ i2c.put_clk_mask = (1 << clock_shift); ++ i2c.put_data_mask = (1 << data_shift); ++ i2c.get_clk_mask = (1 << clock_shift); ++ i2c.get_data_mask = (1 << data_shift); ++ i2c.mask_clk_reg = reg; ++ i2c.mask_data_reg = reg; ++ i2c.a_clk_reg = reg; ++ i2c.a_data_reg = reg; ++ i2c.put_clk_reg = reg; ++ i2c.put_data_reg = reg; ++ i2c.get_clk_reg = reg; ++ i2c.get_data_reg = reg; ++ i2c.valid = TRUE; ++ break; ++ } ++ } ++ } ++ return i2c; ++} ++ + Bool RADEONGetExtTMDSInfoFromBIOS (xf86OutputPtr output) + { + ScrnInfoPtr pScrn = output->scrn; +@@ -1129,6 +1231,52 @@ Bool RADEONGetExtTMDSInfoFromBIOS (xf86OutputPtr output) + + if (info->IsAtomBios) { + return FALSE; ++ } else if (info->IsIGP) { ++ /* RS4xx TMDS stuff is in the mobile table */ ++ offset = RADEON_BIOS16(info->ROMHeaderStart + 0x42); ++ if (offset) { ++ int rev = RADEON_BIOS8(offset); ++ if (rev >= 6) { ++ offset = RADEON_BIOS16(offset + 0x17); ++ if (offset) { ++ offset = RADEON_BIOS16(offset + 2); ++ rev = RADEON_BIOS8(offset); ++ if (offset && (rev > 1)) { ++ int blocks = RADEON_BIOS8(offset + 3); ++ int index = offset + 4; ++ radeon_output->dvo_i2c.valid = FALSE; ++ while (blocks > 0) { ++ int id = RADEON_BIOS16(index); ++ index += 2; ++ switch (id >> 13) { ++ case 0: ++ index += 6; ++ break; ++ case 2: ++ index += 10; ++ break; ++ case 3: ++ index += 2; ++ break; ++ case 4: ++ index += 2; ++ break; ++ case 6: ++ radeon_output->dvo_i2c_slave_addr = ++ RADEON_BIOS16(index) & 0xff; ++ index += 2; ++ radeon_output->dvo_i2c = ++ RADEONLookupI2CBlock(pScrn, RADEON_BIOS8(index)); ++ return TRUE; ++ default: ++ break; ++ } ++ blocks--; ++ } ++ } ++ } ++ } ++ } + } else { + offset = RADEON_BIOS16(info->ROMHeaderStart + 0x58); + if (offset) { +@@ -1148,10 +1296,11 @@ Bool RADEONGetExtTMDSInfoFromBIOS (xf86OutputPtr output) + radeon_output->dvo_i2c = legacy_setup_i2c_bus(RADEON_GPIO_VGA_DDC); + else if (gpio_reg == 4) + radeon_output->dvo_i2c = legacy_setup_i2c_bus(RADEON_GPIO_CRT2_DDC); +- else if (gpio_reg == 5) ++ else if (gpio_reg == 5) { + xf86DrvMsg(pScrn->scrnIndex, X_ERROR, + "unsupported MM gpio_reg\n"); +- else { ++ return FALSE; ++ } else { + xf86DrvMsg(pScrn->scrnIndex, X_ERROR, + "Unknown gpio reg: %d\n", gpio_reg); + return FALSE; +@@ -1179,12 +1328,82 @@ Bool RADEONInitExtTMDSInfoFromBIOS (xf86OutputPtr output) + unsigned char *RADEONMMIO = info->MMIO; + RADEONOutputPrivatePtr radeon_output = output->driver_private; + int offset, index, id; +- uint32_t val, reg, andmask, ormask; ++ uint32_t val, reg, and_mask, or_mask; + + if (!info->VBIOS) return FALSE; + + if (info->IsAtomBios) { + return FALSE; ++ } else if (info->IsIGP) { ++ /* RS4xx TMDS stuff is in the mobile table */ ++ offset = RADEON_BIOS16(info->ROMHeaderStart + 0x42); ++ if (offset) { ++ int rev = RADEON_BIOS8(offset); ++ if (rev >= 6) { ++ offset = RADEON_BIOS16(offset + 0x17); ++ if (offset) { ++ offset = RADEON_BIOS16(offset + 2); ++ rev = RADEON_BIOS8(offset); ++ if (offset && (rev > 1)) { ++ int blocks = RADEON_BIOS8(offset + 3); ++ index = offset + 4; ++ while (blocks > 0) { ++ id = RADEON_BIOS16(index); ++ index += 2; ++ switch (id >> 13) { ++ case 0: ++ reg = (id & 0x1fff) * 4; ++ val = RADEON_BIOS32(index); ++ index += 4; ++ ErrorF("MMIO: 0x%x 0x%x\n", ++ (unsigned)reg, (unsigned)val); ++ OUTREG(reg, val); ++ break; ++ case 2: ++ reg = (id & 0x1fff) * 4; ++ and_mask = RADEON_BIOS32(index); ++ index += 4; ++ or_mask = RADEON_BIOS32(index); ++ index += 4; ++ ErrorF("MMIO mask: 0x%x 0x%x 0x%x\n", ++ (unsigned)reg, (unsigned)and_mask, (unsigned)or_mask); ++ val = INREG(reg); ++ val = (val & and_mask) | or_mask; ++ OUTREG(reg, val); ++ break; ++ case 3: ++ val = RADEON_BIOS16(index); ++ index += 2; ++ ErrorF("delay: %u\n", (unsigned)val); ++ usleep(val); ++ break; ++ case 4: ++ val = RADEON_BIOS16(index); ++ index += 2; ++ ErrorF("delay: %u\n", (unsigned)val * 1000); ++ usleep(val * 1000); ++ break; ++ case 6: ++ index++; ++ reg = RADEON_BIOS8(index); ++ index++; ++ val = RADEON_BIOS8(index); ++ index++; ++ ErrorF("i2c write: 0x%x, 0x%x\n", (unsigned)reg, ++ (unsigned)val); ++ RADEONDVOWriteByte(radeon_output->DVOChip, reg, val); ++ break; ++ default: ++ ErrorF("unknown id %d\n", id>>13); ++ return FALSE; ++ } ++ blocks--; ++ } ++ return TRUE; ++ } ++ } ++ } ++ } + } else { + offset = RADEON_BIOS16(info->ROMHeaderStart + 0x58); + if (offset) { +@@ -1194,24 +1413,24 @@ Bool RADEONInitExtTMDSInfoFromBIOS (xf86OutputPtr output) + index += 2; + switch(id >> 13) { + case 0: +- reg = id & 0x1fff; ++ reg = (id & 0x1fff) * 4; + val = RADEON_BIOS32(index); + index += 4; +- ErrorF("WRITE INDEXED: 0x%x 0x%x\n", ++ ErrorF("MMIO: 0x%x 0x%x\n", + (unsigned)reg, (unsigned)val); +- /*OUTREG(reg, val);*/ ++ OUTREG(reg, val); + break; + case 2: +- reg = id & 0x1fff; +- andmask = RADEON_BIOS32(index); ++ reg = (id & 0x1fff) * 4; ++ and_mask = RADEON_BIOS32(index); + index += 4; +- ormask = RADEON_BIOS32(index); ++ or_mask = RADEON_BIOS32(index); + index += 4; + val = INREG(reg); +- val = (val & andmask) | ormask; +- ErrorF("MASK DIRECT: 0x%x 0x%x 0x%x\n", +- (unsigned)reg, (unsigned)andmask, (unsigned)ormask); +- /*OUTREG(reg, val);*/ ++ val = (val & and_mask) | or_mask; ++ ErrorF("MMIO mask: 0x%x 0x%x 0x%x\n", ++ (unsigned)reg, (unsigned)and_mask, (unsigned)or_mask); ++ OUTREG(reg, val); + break; + case 4: + val = RADEON_BIOS16(index); +@@ -1221,15 +1440,15 @@ Bool RADEONInitExtTMDSInfoFromBIOS (xf86OutputPtr output) + break; + case 5: + reg = id & 0x1fff; +- andmask = RADEON_BIOS32(index); ++ and_mask = RADEON_BIOS32(index); + index += 4; +- ormask = RADEON_BIOS32(index); ++ or_mask = RADEON_BIOS32(index); + index += 4; +- ErrorF("MASK PLL: 0x%x 0x%x 0x%x\n", +- (unsigned)reg, (unsigned)andmask, (unsigned)ormask); +- /*val = INPLL(pScrn, reg); +- val = (val & andmask) | ormask; +- OUTPLL(pScrn, reg, val);*/ ++ ErrorF("PLL mask: 0x%x 0x%x 0x%x\n", ++ (unsigned)reg, (unsigned)and_mask, (unsigned)or_mask); ++ val = INPLL(pScrn, reg); ++ val = (val & and_mask) | or_mask; ++ OUTPLL(pScrn, reg, val); + break; + case 6: + reg = id & 0x1fff; +diff --git a/src/radeon_chipinfo_gen.h b/src/radeon_chipinfo_gen.h +index ed3174a..0d7d085 100644 +--- a/src/radeon_chipinfo_gen.h ++++ b/src/radeon_chipinfo_gen.h +@@ -1,6 +1,7 @@ + /* This file is autogenerated please do not edit */ + RADEONCardInfo RADEONCards[] = { + { 0x3150, CHIP_FAMILY_RV380, 1, 0, 0, 0, 0 }, ++ { 0x3151, CHIP_FAMILY_RV380, 0, 0, 0, 0, 0 }, + { 0x3152, CHIP_FAMILY_RV380, 1, 0, 0, 0, 0 }, + { 0x3154, CHIP_FAMILY_RV380, 1, 0, 0, 0, 0 }, + { 0x3E50, CHIP_FAMILY_RV380, 0, 0, 0, 0, 0 }, +@@ -250,6 +251,8 @@ RADEONCardInfo RADEONCards[] = { + { 0x940A, CHIP_FAMILY_R600, 0, 0, 0, 0, 0 }, + { 0x940B, CHIP_FAMILY_R600, 0, 0, 0, 0, 0 }, + { 0x940F, CHIP_FAMILY_R600, 0, 0, 0, 0, 0 }, ++ { 0x9440, CHIP_FAMILY_RV770, 0, 0, 0, 0, 0 }, ++ { 0x9442, CHIP_FAMILY_RV770, 0, 0, 0, 0, 0 }, + { 0x94C0, CHIP_FAMILY_RV610, 0, 0, 0, 0, 0 }, + { 0x94C1, CHIP_FAMILY_RV610, 0, 0, 0, 0, 0 }, + { 0x94C3, CHIP_FAMILY_RV610, 0, 0, 0, 0, 0 }, +@@ -267,6 +270,7 @@ RADEONCardInfo RADEONCards[] = { + { 0x9507, CHIP_FAMILY_RV670, 0, 0, 0, 0, 0 }, + { 0x950F, CHIP_FAMILY_RV670, 0, 0, 0, 0, 0 }, + { 0x9511, CHIP_FAMILY_RV670, 0, 0, 0, 0, 0 }, ++ { 0x9515, CHIP_FAMILY_RV670, 0, 0, 0, 0, 0 }, + { 0x9580, CHIP_FAMILY_RV630, 0, 0, 0, 0, 0 }, + { 0x9581, CHIP_FAMILY_RV630, 1, 0, 0, 0, 0 }, + { 0x9583, CHIP_FAMILY_RV630, 1, 0, 0, 0, 0 }, +diff --git a/src/radeon_chipset_gen.h b/src/radeon_chipset_gen.h +index d1761d2..96b60e9 100644 +--- a/src/radeon_chipset_gen.h ++++ b/src/radeon_chipset_gen.h +@@ -1,6 +1,7 @@ + /* This file is autogenerated please do not edit */ + static SymTabRec RADEONChipsets[] = { + { PCI_CHIP_RV380_3150, "ATI Radeon Mobility X600 (M24) 3150 (PCIE)" }, ++ { PCI_CHIP_RV380_3151, "ATI FireMV 2400 (PCI)" }, + { PCI_CHIP_RV380_3152, "ATI Radeon Mobility X300 (M24) 3152 (PCIE)" }, + { PCI_CHIP_RV380_3154, "ATI FireGL M24 GL 3154 (PCIE)" }, + { PCI_CHIP_RV380_3E50, "ATI Radeon X600 (RV380) 3E50 (PCIE)" }, +@@ -250,6 +251,8 @@ static SymTabRec RADEONChipsets[] = { + { PCI_CHIP_R600_940A, "ATI FireGL V8650" }, + { PCI_CHIP_R600_940B, "ATI FireGL V8600" }, + { PCI_CHIP_R600_940F, "ATI FireGL V7600" }, ++ { PCI_CHIP_RV770_9440, "ATI Radeon 4800 Series" }, ++ { PCI_CHIP_RV770_9442, "ATI Radeon 4800 Series" }, + { PCI_CHIP_RV610_94C0, "ATI RV610" }, + { PCI_CHIP_RV610_94C1, "ATI Radeon HD 2400 XT" }, + { PCI_CHIP_RV610_94C3, "ATI Radeon HD 2400 Pro" }, +@@ -267,6 +270,7 @@ static SymTabRec RADEONChipsets[] = { + { PCI_CHIP_RV670_9507, "ATI RV670" }, + { PCI_CHIP_RV670_950F, "ATI Radeon HD3870 X2" }, + { PCI_CHIP_RV670_9511, "ATI FireGL V7700" }, ++ { PCI_CHIP_RV670_9515, "ATI Radeon HD3850" }, + { PCI_CHIP_RV630_9580, "ATI RV630" }, + { PCI_CHIP_RV630_9581, "ATI Mobility Radeon HD 2600" }, + { PCI_CHIP_RV630_9583, "ATI Mobility Radeon HD 2600 XT" }, +diff --git a/src/radeon_commonfuncs.c b/src/radeon_commonfuncs.c +index 58fe306..d0c5229 100644 +--- a/src/radeon_commonfuncs.c ++++ b/src/radeon_commonfuncs.c +@@ -158,13 +158,14 @@ static void FUNC_NAME(RADEONInit3DEngine)(ScrnInfoPtr pScrn) + if (info->ChipFamily == CHIP_FAMILY_RV515) + vap_cntl |= (2 << R300_PVS_NUM_FPUS_SHIFT); + else if ((info->ChipFamily == CHIP_FAMILY_RV530) || +- (info->ChipFamily == CHIP_FAMILY_RV560)) ++ (info->ChipFamily == CHIP_FAMILY_RV560) || ++ (info->ChipFamily == CHIP_FAMILY_RV570)) + vap_cntl |= (5 << R300_PVS_NUM_FPUS_SHIFT); +- else if (info->ChipFamily == CHIP_FAMILY_R420) ++ else if ((info->ChipFamily == CHIP_FAMILY_RV410) || ++ (info->ChipFamily == CHIP_FAMILY_R420)) + vap_cntl |= (6 << R300_PVS_NUM_FPUS_SHIFT); + else if ((info->ChipFamily == CHIP_FAMILY_R520) || +- (info->ChipFamily == CHIP_FAMILY_R580) || +- (info->ChipFamily == CHIP_FAMILY_RV570)) ++ (info->ChipFamily == CHIP_FAMILY_R580)) + vap_cntl |= (8 << R300_PVS_NUM_FPUS_SHIFT); + else + vap_cntl |= (4 << R300_PVS_NUM_FPUS_SHIFT); +diff --git a/src/radeon_crtc.c b/src/radeon_crtc.c +index c63b650..1316669 100644 +--- a/src/radeon_crtc.c ++++ b/src/radeon_crtc.c +@@ -58,6 +58,14 @@ extern void atombios_crtc_mode_set(xf86CrtcPtr crtc, + DisplayModePtr adjusted_mode, + int x, int y); + extern void atombios_crtc_dpms(xf86CrtcPtr crtc, int mode); ++extern void ++RADEONInitDispBandwidthLegacy(ScrnInfoPtr pScrn, ++ DisplayModePtr mode1, int pixel_bytes1, ++ DisplayModePtr mode2, int pixel_bytes2); ++extern void ++RADEONInitDispBandwidthAVIVO(ScrnInfoPtr pScrn, ++ DisplayModePtr mode1, int pixel_bytes1, ++ DisplayModePtr mode2, int pixel_bytes2); + + void + radeon_crtc_dpms(xf86CrtcPtr crtc, int mode) +@@ -567,6 +575,43 @@ static const xf86CrtcFuncsRec radeon_crtc_funcs = { + .destroy = NULL, /* XXX */ + }; + ++void ++RADEONInitDispBandwidth(ScrnInfoPtr pScrn) ++{ ++ RADEONInfoPtr info = RADEONPTR(pScrn); ++ xf86CrtcConfigPtr xf86_config = XF86_CRTC_CONFIG_PTR(pScrn); ++ DisplayModePtr mode1 = NULL, mode2 = NULL; ++ int pixel_bytes1 = info->CurrentLayout.pixel_bytes; ++ int pixel_bytes2 = info->CurrentLayout.pixel_bytes; ++ ++ if (xf86_config->num_crtc == 2) { ++ if (xf86_config->crtc[1]->enabled && ++ xf86_config->crtc[0]->enabled) { ++ mode1 = &xf86_config->crtc[0]->mode; ++ mode2 = &xf86_config->crtc[1]->mode; ++ } else if (xf86_config->crtc[0]->enabled) { ++ mode1 = &xf86_config->crtc[0]->mode; ++ } else if (xf86_config->crtc[1]->enabled) { ++ mode2 = &xf86_config->crtc[1]->mode; ++ } else ++ return; ++ } else { ++ if (info->IsPrimary) ++ mode1 = &xf86_config->crtc[0]->mode; ++ else if (info->IsSecondary) ++ mode2 = &xf86_config->crtc[0]->mode; ++ else if (xf86_config->crtc[0]->enabled) ++ mode1 = &xf86_config->crtc[0]->mode; ++ else ++ return; ++ } ++ ++ if (IS_AVIVO_VARIANT) ++ RADEONInitDispBandwidthAVIVO(pScrn, mode1, pixel_bytes1, mode2, pixel_bytes2); ++ else ++ RADEONInitDispBandwidthLegacy(pScrn, mode1, pixel_bytes1, mode2, pixel_bytes2); ++} ++ + Bool RADEONAllocateControllers(ScrnInfoPtr pScrn, int mask) + { + RADEONEntPtr pRADEONEnt = RADEONEntPriv(pScrn); +diff --git a/src/radeon_cursor.c b/src/radeon_cursor.c +index c4472db..13c2b9c 100644 +--- a/src/radeon_cursor.c ++++ b/src/radeon_cursor.c +@@ -209,21 +209,23 @@ radeon_crtc_set_cursor_position (xf86CrtcPtr crtc, int x, int y) + if (xorigin >= CURSOR_WIDTH) xorigin = CURSOR_WIDTH - 1; + if (yorigin >= CURSOR_HEIGHT) yorigin = CURSOR_HEIGHT - 1; + +- if (mode->Flags & V_INTERLACE) +- y /= 2; +- else if (mode->Flags & V_DBLSCAN) +- y *= 2; +- + if (IS_AVIVO_VARIANT) { + /* avivo cursor spans the full fb width */ +- x += crtc->x; +- y += crtc->y; ++ if (crtc->rotatedData == NULL) { ++ x += crtc->x; ++ y += crtc->y; ++ } + avivo_lock_cursor(crtc, TRUE); + OUTREG(AVIVO_D1CUR_POSITION + radeon_crtc->crtc_offset, ((xorigin ? 0 : x) << 16) + | (yorigin ? 0 : y)); + OUTREG(AVIVO_D1CUR_HOT_SPOT + radeon_crtc->crtc_offset, (xorigin << 16) | yorigin); + avivo_lock_cursor(crtc, FALSE); + } else { ++ if (mode->Flags & V_INTERLACE) ++ y /= 2; ++ else if (mode->Flags & V_DBLSCAN) ++ y *= 2; ++ + if (crtc_id == 0) { + OUTREG(RADEON_CUR_HORZ_VERT_OFF, (RADEON_CUR_LOCK + | (xorigin << 16) +diff --git a/src/radeon_dri.c b/src/radeon_dri.c +index 0fc03e4..a192811 100644 +--- a/src/radeon_dri.c ++++ b/src/radeon_dri.c +@@ -1103,7 +1103,7 @@ static int RADEONDRIKernelInit(RADEONInfoPtr info, ScreenPtr pScreen) + + drmInfo.sarea_priv_offset = sizeof(XF86DRISAREARec); + drmInfo.is_pci = (info->cardType!=CARD_AGP); +- drmInfo.cp_mode = info->CPMode; ++ drmInfo.cp_mode = RADEON_CSQ_PRIBM_INDBM; + drmInfo.gart_size = info->gartSize*1024*1024; + drmInfo.ring_size = info->ringSize*1024*1024; + drmInfo.usec_timeout = info->CPusecTimeout; +@@ -1211,6 +1211,12 @@ static void RADEONDRIIrqInit(RADEONInfoPtr info, ScreenPtr pScreen) + } else { + unsigned char *RADEONMMIO = info->MMIO; + info->ModeReg->gen_int_cntl = INREG( RADEON_GEN_INT_CNTL ); ++ ++ /* Let the DRM know it can safely disable the vblank interrupts */ ++ radeon_crtc_modeset_ioctl(XF86_CRTC_CONFIG_PTR(pScrn)->crtc[0], ++ FALSE); ++ radeon_crtc_modeset_ioctl(XF86_CRTC_CONFIG_PTR(pScrn)->crtc[0], ++ TRUE); + } + } + +@@ -1453,10 +1459,9 @@ Bool RADEONDRIScreenInit(ScreenPtr pScreen) + PCI_DEV_DEV(info->PciInfo), + PCI_DEV_FUNC(info->PciInfo)); + } +- pDRIInfo->ddxDriverMajorVersion = info->allowColorTiling ? +- RADEON_VERSION_MAJOR_TILED : RADEON_VERSION_MAJOR; +- pDRIInfo->ddxDriverMinorVersion = RADEON_VERSION_MINOR; +- pDRIInfo->ddxDriverPatchVersion = RADEON_VERSION_PATCH; ++ pDRIInfo->ddxDriverMajorVersion = info->allowColorTiling ? 5 : 4; ++ pDRIInfo->ddxDriverMinorVersion = 3; ++ pDRIInfo->ddxDriverPatchVersion = 0; + pDRIInfo->frameBufferPhysicalAddress = (void *)info->LinearAddr + info->frontOffset; + pDRIInfo->frameBufferSize = info->FbMapSize - info->FbSecureSize; + pDRIInfo->frameBufferStride = (pScrn->displayWidth * +diff --git a/src/radeon_dri.h b/src/radeon_dri.h +index 67892a6..6e3ad62 100644 +--- a/src/radeon_dri.h ++++ b/src/radeon_dri.h +@@ -39,9 +39,8 @@ + #include "xf86drm.h" + + /* DRI Driver defaults */ +-#define RADEON_DEFAULT_CP_PIO_MODE RADEON_CSQ_PRIPIO_INDPIO +-#define RADEON_DEFAULT_CP_BM_MODE RADEON_CSQ_PRIBM_INDBM + #define RADEON_DEFAULT_GART_SIZE 8 /* MB (must be 2^n and > 4MB) */ ++#define R300_DEFAULT_GART_SIZE 32 /* MB (for R300 and above) */ + #define RADEON_DEFAULT_RING_SIZE 1 /* MB (must be page aligned) */ + #define RADEON_DEFAULT_BUFFER_SIZE 2 /* MB (must be page aligned) */ + #define RADEON_DEFAULT_GART_TEX_SIZE 1 /* MB (must be page aligned) */ +@@ -52,10 +51,6 @@ + + #define RADEON_CARD_TYPE_RADEON 1 + +-#define RADEONCP_USE_RING_BUFFER(m) \ +- (((m) == RADEON_CSQ_PRIBM_INDDIS) || \ +- ((m) == RADEON_CSQ_PRIBM_INDBM)) +- + typedef struct { + /* DRI screen private data */ + int deviceID; /* PCI device ID */ +diff --git a/src/radeon_driver.c b/src/radeon_driver.c +index f18ad99..45d2c2f 100644 +--- a/src/radeon_driver.c ++++ b/src/radeon_driver.c +@@ -669,7 +669,14 @@ static void radeon_write_mc_fb_agp_location(ScrnInfoPtr pScrn, int mask, uint32_ + RADEONInfoPtr info = RADEONPTR(pScrn); + unsigned char *RADEONMMIO = info->MMIO; + +- if (info->ChipFamily >= CHIP_FAMILY_R600) { ++ if (info->ChipFamily >= CHIP_FAMILY_RV770) { ++ if (mask & LOC_FB) ++ OUTREG(R700_MC_VM_FB_LOCATION, fb_loc); ++ if (mask & LOC_AGP) { ++ OUTREG(R600_MC_VM_AGP_BOT, agp_loc); ++ OUTREG(R600_MC_VM_AGP_TOP, agp_loc_hi); ++ } ++ } else if (info->ChipFamily >= CHIP_FAMILY_R600) { + if (mask & LOC_FB) + OUTREG(R600_MC_VM_FB_LOCATION, fb_loc); + if (mask & LOC_AGP) { +@@ -712,7 +719,14 @@ static void radeon_read_mc_fb_agp_location(ScrnInfoPtr pScrn, int mask, uint32_t + RADEONInfoPtr info = RADEONPTR(pScrn); + unsigned char *RADEONMMIO = info->MMIO; + +- if (info->ChipFamily >= CHIP_FAMILY_R600) { ++ if (info->ChipFamily >= CHIP_FAMILY_RV770) { ++ if (mask & LOC_FB) ++ *fb_loc = INREG(R700_MC_VM_FB_LOCATION); ++ if (mask & LOC_AGP) { ++ *agp_loc = INREG(R600_MC_VM_AGP_BOT); ++ *agp_loc_hi = INREG(R600_MC_VM_AGP_TOP); ++ } ++ } else if (info->ChipFamily >= CHIP_FAMILY_R600) { + if (mask & LOC_FB) + *fb_loc = INREG(R600_MC_VM_FB_LOCATION); + if (mask & LOC_AGP) { +@@ -2032,16 +2046,22 @@ static Bool RADEONPreInitAccel(ScrnInfoPtr pScrn) + + static Bool RADEONPreInitInt10(ScrnInfoPtr pScrn, xf86Int10InfoPtr *ppInt10) + { +-#if !defined(__powerpc__) && !defined(__sparc__) ++#if (!defined(__powerpc__) && !defined(__sparc__)) || \ ++ (defined(XSERVER_LIBPCIACCESS) && HAVE_PCI_DEVICE_ENABLE) + RADEONInfoPtr info = RADEONPTR(pScrn); ++#endif ++#if !defined(__powerpc__) && !defined(__sparc__) + unsigned char *RADEONMMIO = info->MMIO; + uint32_t fp2_gen_ctl_save = 0; ++#endif + + #ifdef XSERVER_LIBPCIACCESS + #if HAVE_PCI_DEVICE_ENABLE + pci_device_enable(info->PciInfo); + #endif + #endif ++ ++#if !defined(__powerpc__) && !defined(__sparc__) + /* don't need int10 on atom cards. + * in theory all radeons, but the older stuff + * isn't 100% yet +@@ -2106,19 +2126,16 @@ static Bool RADEONPreInitDRI(ScrnInfoPtr pScrn) + + if (info->Chipset == PCI_CHIP_RN50_515E || + info->Chipset == PCI_CHIP_RN50_5969 || +- info->Chipset == PCI_CHIP_RC410_5A61 || +- info->Chipset == PCI_CHIP_RC410_5A62 || +- info->Chipset == PCI_CHIP_RS485_5975 || + info->ChipFamily == CHIP_FAMILY_RS600 || + info->ChipFamily >= CHIP_FAMILY_R600) { + if (xf86ReturnOptValBool(info->Options, OPTION_DRI, FALSE)) { + xf86DrvMsg(pScrn->scrnIndex, X_WARNING, +- "Direct rendering for RN50/RC410/RS485/RS600/R600 forced on -- " ++ "Direct rendering for RN50/RS600/R600 forced on -- " + "This is NOT officially supported at the hardware level " + "and may cause instability or lockups\n"); + } else { + xf86DrvMsg(pScrn->scrnIndex, X_INFO, +- "Direct rendering not officially supported on RN50/RC410/R600\n"); ++ "Direct rendering not officially supported on RN50/RS600/R600\n"); + return FALSE; + } + } +@@ -2167,14 +2184,11 @@ static Bool RADEONPreInitDRI(ScrnInfoPtr pScrn) + "Direct rendering experimental on RS400/Xpress 200 enabled\n"); + } + +- if (xf86ReturnOptValBool(info->Options, OPTION_CP_PIO, FALSE)) { +- xf86DrvMsg(pScrn->scrnIndex, X_CONFIG, "Forcing CP into PIO mode\n"); +- info->CPMode = RADEON_DEFAULT_CP_PIO_MODE; +- } else { +- info->CPMode = RADEON_DEFAULT_CP_BM_MODE; +- } ++ if (info->ChipFamily >= CHIP_FAMILY_R300) ++ info->gartSize = R300_DEFAULT_GART_SIZE; ++ else ++ info->gartSize = RADEON_DEFAULT_GART_SIZE; + +- info->gartSize = RADEON_DEFAULT_GART_SIZE; + info->ringSize = RADEON_DEFAULT_RING_SIZE; + info->bufSize = RADEON_DEFAULT_BUFFER_SIZE; + info->gartTexSize = RADEON_DEFAULT_GART_TEX_SIZE; +@@ -4178,6 +4192,7 @@ avivo_save(ScrnInfoPtr pScrn, RADEONSavePtr save) + + state->crtc_master_en = INREG(AVIVO_DC_CRTC_MASTER_EN); + state->crtc_tv_control = INREG(AVIVO_DC_CRTC_TV_CONTROL); ++ state->dc_lb_memory_split = INREG(AVIVO_DC_LB_MEMORY_SPLIT); + + state->pll1.ref_div_src = INREG(AVIVO_EXT1_PPLL_REF_DIV_SRC); + state->pll1.ref_div = INREG(AVIVO_EXT1_PPLL_REF_DIV); +@@ -4233,8 +4248,10 @@ avivo_save(ScrnInfoPtr pScrn, RADEONSavePtr save) + state->grph1.x_end = INREG(AVIVO_D1GRPH_X_END); + state->grph1.y_end = INREG(AVIVO_D1GRPH_Y_END); + ++ state->grph1.desktop_height = INREG(AVIVO_D1MODE_DESKTOP_HEIGHT); + state->grph1.viewport_start = INREG(AVIVO_D1MODE_VIEWPORT_START); + state->grph1.viewport_size = INREG(AVIVO_D1MODE_VIEWPORT_SIZE); ++ state->grph1.mode_data_format = INREG(AVIVO_D1MODE_DATA_FORMAT); + + state->crtc2.pll_source = INREG(AVIVO_PCLK_CRTC2_CNTL); + +@@ -4272,8 +4289,10 @@ avivo_save(ScrnInfoPtr pScrn, RADEONSavePtr save) + state->grph2.x_end = INREG(AVIVO_D2GRPH_X_END); + state->grph2.y_end = INREG(AVIVO_D2GRPH_Y_END); + ++ state->grph2.desktop_height = INREG(AVIVO_D2MODE_DESKTOP_HEIGHT); + state->grph2.viewport_start = INREG(AVIVO_D2MODE_VIEWPORT_START); + state->grph2.viewport_size = INREG(AVIVO_D2MODE_VIEWPORT_SIZE); ++ state->grph2.mode_data_format = INREG(AVIVO_D2MODE_DATA_FORMAT); + + if (IS_DCE3_VARIANT) { + /* save DVOA regs */ +@@ -4477,14 +4496,71 @@ avivo_restore(ScrnInfoPtr pScrn, RADEONSavePtr restore) + struct avivo_state *state = &restore->avivo; + int i, j; + +- // OUTMC(pScrn, AVIVO_MC_MEMORY_MAP, state->mc_memory_map); +- // OUTREG(AVIVO_VGA_MEMORY_BASE, state->vga_memory_base); +- // OUTREG(AVIVO_VGA_FB_START, state->vga_fb_start); ++ xf86DrvMsg(pScrn->scrnIndex, X_INFO, "avivo_restore !\n"); ++ ++ /* Disable VGA control for now.. maybe needs to be changed */ ++ OUTREG(AVIVO_D1VGA_CONTROL, 0); ++ OUTREG(AVIVO_D2VGA_CONTROL, 0); ++ ++ /* Disable CRTCs */ ++ OUTREG(AVIVO_D1CRTC_CONTROL, ++ (INREG(AVIVO_D1CRTC_CONTROL) & ~0x300) | 0x01000000); ++ OUTREG(AVIVO_D2CRTC_CONTROL, ++ (INREG(AVIVO_D2CRTC_CONTROL) & ~0x300) | 0x01000000); ++ OUTREG(AVIVO_D1CRTC_CONTROL, ++ INREG(AVIVO_D1CRTC_CONTROL) & ~0x1); ++ OUTREG(AVIVO_D2CRTC_CONTROL, ++ INREG(AVIVO_D2CRTC_CONTROL) & ~0x1); ++ OUTREG(AVIVO_D1CRTC_CONTROL, ++ INREG(AVIVO_D1CRTC_CONTROL) | 0x100); ++ OUTREG(AVIVO_D2CRTC_CONTROL, ++ INREG(AVIVO_D2CRTC_CONTROL) | 0x100); ++ ++ /* Lock graph registers */ ++ OUTREG(AVIVO_D1GRPH_UPDATE, AVIVO_D1GRPH_UPDATE_LOCK); ++ OUTREG(AVIVO_D1GRPH_PRIMARY_SURFACE_ADDRESS, state->grph1.prim_surf_addr); ++ OUTREG(AVIVO_D1GRPH_SECONDARY_SURFACE_ADDRESS, state->grph1.sec_surf_addr); ++ OUTREG(AVIVO_D1GRPH_CONTROL, state->grph1.control); ++ OUTREG(AVIVO_D1GRPH_SURFACE_OFFSET_X, state->grph1.x_offset); ++ OUTREG(AVIVO_D1GRPH_SURFACE_OFFSET_Y, state->grph1.y_offset); ++ OUTREG(AVIVO_D1GRPH_X_START, state->grph1.x_start); ++ OUTREG(AVIVO_D1GRPH_Y_START, state->grph1.y_start); ++ OUTREG(AVIVO_D1GRPH_X_END, state->grph1.x_end); ++ OUTREG(AVIVO_D1GRPH_Y_END, state->grph1.y_end); ++ OUTREG(AVIVO_D1GRPH_PITCH, state->grph1.pitch); ++ OUTREG(AVIVO_D1GRPH_ENABLE, state->grph1.enable); ++ OUTREG(AVIVO_D1GRPH_UPDATE, 0); ++ ++ OUTREG(AVIVO_D2GRPH_UPDATE, AVIVO_D1GRPH_UPDATE_LOCK); ++ OUTREG(AVIVO_D2GRPH_PRIMARY_SURFACE_ADDRESS, state->grph2.prim_surf_addr); ++ OUTREG(AVIVO_D2GRPH_SECONDARY_SURFACE_ADDRESS, state->grph2.sec_surf_addr); ++ OUTREG(AVIVO_D2GRPH_CONTROL, state->grph2.control); ++ OUTREG(AVIVO_D2GRPH_SURFACE_OFFSET_X, state->grph2.x_offset); ++ OUTREG(AVIVO_D2GRPH_SURFACE_OFFSET_Y, state->grph2.y_offset); ++ OUTREG(AVIVO_D2GRPH_X_START, state->grph2.x_start); ++ OUTREG(AVIVO_D2GRPH_Y_START, state->grph2.y_start); ++ OUTREG(AVIVO_D2GRPH_X_END, state->grph2.x_end); ++ OUTREG(AVIVO_D2GRPH_Y_END, state->grph2.y_end); ++ OUTREG(AVIVO_D2GRPH_PITCH, state->grph2.pitch); ++ OUTREG(AVIVO_D2GRPH_ENABLE, state->grph2.enable); ++ OUTREG(AVIVO_D2GRPH_UPDATE, 0); + ++ /* Whack some mode regs too */ ++ OUTREG(AVIVO_D1SCL_UPDATE, AVIVO_D1SCL_UPDATE_LOCK); ++ OUTREG(AVIVO_D1MODE_DESKTOP_HEIGHT, state->grph1.desktop_height); ++ OUTREG(AVIVO_D1MODE_VIEWPORT_START, state->grph1.viewport_start); ++ OUTREG(AVIVO_D1MODE_VIEWPORT_SIZE, state->grph1.viewport_size); ++ OUTREG(AVIVO_D1MODE_DATA_FORMAT, state->grph1.mode_data_format); ++ OUTREG(AVIVO_D1SCL_UPDATE, 0); + +- OUTREG(AVIVO_DC_CRTC_MASTER_EN, state->crtc_master_en); +- OUTREG(AVIVO_DC_CRTC_TV_CONTROL, state->crtc_tv_control); ++ OUTREG(AVIVO_D2SCL_UPDATE, AVIVO_D1SCL_UPDATE_LOCK); ++ OUTREG(AVIVO_D2MODE_DESKTOP_HEIGHT, state->grph2.desktop_height); ++ OUTREG(AVIVO_D2MODE_VIEWPORT_START, state->grph2.viewport_start); ++ OUTREG(AVIVO_D2MODE_VIEWPORT_SIZE, state->grph2.viewport_size); ++ OUTREG(AVIVO_D2MODE_DATA_FORMAT, state->grph2.mode_data_format); ++ OUTREG(AVIVO_D2SCL_UPDATE, 0); + ++ /* Set the PLL */ + OUTREG(AVIVO_EXT1_PPLL_REF_DIV_SRC, state->pll1.ref_div_src); + OUTREG(AVIVO_EXT1_PPLL_REF_DIV, state->pll1.ref_div); + OUTREG(AVIVO_EXT1_PPLL_FB_DIV, state->pll1.fb_div); +@@ -4504,7 +4580,9 @@ avivo_restore(ScrnInfoPtr pScrn, RADEONSavePtr restore) + OUTREG(AVIVO_P2PLL_INT_SS_CNTL, state->pll2.int_ss_cntl); + + OUTREG(AVIVO_PCLK_CRTC1_CNTL, state->crtc1.pll_source); ++ OUTREG(AVIVO_PCLK_CRTC2_CNTL, state->crtc2.pll_source); + ++ /* Set the CRTC */ + OUTREG(AVIVO_D1CRTC_H_TOTAL, state->crtc1.h_total); + OUTREG(AVIVO_D1CRTC_H_BLANK_START_END, state->crtc1.h_blank_start_end); + OUTREG(AVIVO_D1CRTC_H_SYNC_A, state->crtc1.h_sync_a); +@@ -4519,29 +4597,12 @@ avivo_restore(ScrnInfoPtr pScrn, RADEONSavePtr restore) + OUTREG(AVIVO_D1CRTC_V_SYNC_B, state->crtc1.v_sync_b); + OUTREG(AVIVO_D1CRTC_V_SYNC_B_CNTL, state->crtc1.v_sync_b_cntl); + +- OUTREG(AVIVO_D1CRTC_CONTROL, state->crtc1.control); +- OUTREG(AVIVO_D1CRTC_BLANK_CONTROL, state->crtc1.blank_control); + OUTREG(AVIVO_D1CRTC_INTERLACE_CONTROL, state->crtc1.interlace_control); + OUTREG(AVIVO_D1CRTC_STEREO_CONTROL, state->crtc1.stereo_control); + + OUTREG(AVIVO_D1CUR_CONTROL, state->crtc1.cursor_control); + +- OUTREG(AVIVO_D1GRPH_ENABLE, state->grph1.enable); +- OUTREG(AVIVO_D1GRPH_CONTROL, state->grph1.control); +- OUTREG(AVIVO_D1GRPH_PRIMARY_SURFACE_ADDRESS, state->grph1.prim_surf_addr); +- OUTREG(AVIVO_D1GRPH_SECONDARY_SURFACE_ADDRESS, state->grph1.sec_surf_addr); +- OUTREG(AVIVO_D1GRPH_PITCH, state->grph1.pitch); +- OUTREG(AVIVO_D1GRPH_SURFACE_OFFSET_X, state->grph1.x_offset); +- OUTREG(AVIVO_D1GRPH_SURFACE_OFFSET_Y, state->grph1.y_offset); +- OUTREG(AVIVO_D1GRPH_X_START, state->grph1.x_start); +- OUTREG(AVIVO_D1GRPH_Y_START, state->grph1.y_start); +- OUTREG(AVIVO_D1GRPH_X_END, state->grph1.x_end); +- OUTREG(AVIVO_D1GRPH_Y_END, state->grph1.y_end); +- +- OUTREG(AVIVO_D1MODE_VIEWPORT_START, state->grph1.viewport_start); +- OUTREG(AVIVO_D1MODE_VIEWPORT_SIZE, state->grph1.viewport_size); +- +- OUTREG(AVIVO_PCLK_CRTC2_CNTL, state->crtc2.pll_source); ++ /* XXX Fix scaler */ + + OUTREG(AVIVO_D2CRTC_H_TOTAL, state->crtc2.h_total); + OUTREG(AVIVO_D2CRTC_H_BLANK_START_END, state->crtc2.h_blank_start_end); +@@ -4557,29 +4618,11 @@ avivo_restore(ScrnInfoPtr pScrn, RADEONSavePtr restore) + OUTREG(AVIVO_D2CRTC_V_SYNC_B, state->crtc2.v_sync_b); + OUTREG(AVIVO_D2CRTC_V_SYNC_B_CNTL, state->crtc2.v_sync_b_cntl); + +- OUTREG(AVIVO_D2CRTC_CONTROL, state->crtc2.control); +- OUTREG(AVIVO_D2CRTC_BLANK_CONTROL, state->crtc2.blank_control); + OUTREG(AVIVO_D2CRTC_INTERLACE_CONTROL, state->crtc2.interlace_control); + OUTREG(AVIVO_D2CRTC_STEREO_CONTROL, state->crtc2.stereo_control); + + OUTREG(AVIVO_D2CUR_CONTROL, state->crtc2.cursor_control); + +- OUTREG(AVIVO_D2GRPH_ENABLE, state->grph2.enable); +- OUTREG(AVIVO_D2GRPH_CONTROL, state->grph2.control); +- OUTREG(AVIVO_D2GRPH_PRIMARY_SURFACE_ADDRESS, state->grph2.prim_surf_addr); +- OUTREG(AVIVO_D2GRPH_SECONDARY_SURFACE_ADDRESS, state->grph2.sec_surf_addr); +- OUTREG(AVIVO_D2GRPH_PITCH, state->grph2.pitch); +- OUTREG(AVIVO_D2GRPH_SURFACE_OFFSET_X, state->grph2.x_offset); +- OUTREG(AVIVO_D2GRPH_SURFACE_OFFSET_Y, state->grph2.y_offset); +- OUTREG(AVIVO_D2GRPH_X_START, state->grph2.x_start); +- OUTREG(AVIVO_D2GRPH_Y_START, state->grph2.y_start); +- OUTREG(AVIVO_D2GRPH_X_END, state->grph2.x_end); +- OUTREG(AVIVO_D2GRPH_Y_END, state->grph2.y_end); +- +- OUTREG(AVIVO_D2MODE_VIEWPORT_START, state->grph2.viewport_start); +- OUTREG(AVIVO_D2MODE_VIEWPORT_SIZE, state->grph2.viewport_size); +- +- + if (IS_DCE3_VARIANT) { + /* DVOA regs */ + OUTREG(0x7080, state->dvoa[0]); +@@ -4699,7 +4742,7 @@ avivo_restore(ScrnInfoPtr pScrn, RADEONSavePtr restore) + } + + j = 0; +- /* DAC regs */ ++ /* DAC regs */ /* -- MIGHT NEED ORDERING FIX & DELAYS -- */ + for (i = 0x7800; i <= 0x782c; i += 4) { + OUTREG(i, state->daca[j]); + OUTREG((i + 0x200), state->dacb[j]); +@@ -4766,8 +4809,31 @@ avivo_restore(ScrnInfoPtr pScrn, RADEONSavePtr restore) + OUTREG(0x6e30, state->dxscl[6]); + OUTREG(0x6e34, state->dxscl[7]); + ++ /* Enable CRTCs */ ++ if (state->crtc1.control & 1) { ++ OUTREG(AVIVO_D1CRTC_CONTROL, 0x01000101); ++ INREG(AVIVO_D1CRTC_CONTROL); ++ OUTREG(AVIVO_D1CRTC_CONTROL, 0x00010101); ++ } ++ if (state->crtc2.control & 1) { ++ OUTREG(AVIVO_D2CRTC_CONTROL, 0x01000101); ++ INREG(AVIVO_D2CRTC_CONTROL); ++ OUTREG(AVIVO_D2CRTC_CONTROL, 0x00010101); ++ } ++ ++ /* Where should that go ? */ ++ OUTREG(AVIVO_DC_CRTC_TV_CONTROL, state->crtc_tv_control); ++ OUTREG(AVIVO_DC_LB_MEMORY_SPLIT, state->dc_lb_memory_split); ++ ++ /* Need fixing too ? */ ++ OUTREG(AVIVO_D1CRTC_BLANK_CONTROL, state->crtc1.blank_control); ++ OUTREG(AVIVO_D2CRTC_BLANK_CONTROL, state->crtc2.blank_control); ++ ++ /* Dbl check */ + OUTREG(AVIVO_D1VGA_CONTROL, state->vga1_cntl); + OUTREG(AVIVO_D2VGA_CONTROL, state->vga2_cntl); ++ ++ /* Should only enable outputs here */ + } + + static void avivo_restore_vga_regs(ScrnInfoPtr pScrn, RADEONSavePtr restore) +@@ -5318,26 +5384,18 @@ Bool RADEONEnterVT(int scrnIndex, int flags) + { + ScrnInfoPtr pScrn = xf86Screens[scrnIndex]; + RADEONInfoPtr info = RADEONPTR(pScrn); +- unsigned char *RADEONMMIO = info->MMIO; +- uint32_t mem_size; + xf86CrtcConfigPtr config = XF86_CRTC_CONFIG_PTR(pScrn); + int i; + + xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG, + "RADEONEnterVT\n"); + +- if (info->ChipFamily >= CHIP_FAMILY_R600) +- mem_size = INREG(R600_CONFIG_MEMSIZE); +- else +- mem_size = INREG(RADEON_CONFIG_MEMSIZE); +- +- if (mem_size == 0) { /* Softboot V_BIOS */ ++ if (!radeon_card_posted(pScrn)) { /* Softboot V_BIOS */ + if (info->IsAtomBios) { + rhdAtomASICInit(info->atomBIOS); + } else { + xf86Int10InfoPtr pInt; +- xf86DrvMsg(pScrn->scrnIndex, X_WARNING, +- "zero MEMSIZE, probably at D3cold. Re-POSTing via int10.\n"); ++ + pInt = xf86InitInt10 (info->pEnt->index); + if (pInt) { + pInt->num = 0xe6; +diff --git a/src/radeon_exa.c b/src/radeon_exa.c +index f461f3c..02fd4fc 100644 +--- a/src/radeon_exa.c ++++ b/src/radeon_exa.c +@@ -413,14 +413,16 @@ Bool RADEONSetupMemEXA (ScreenPtr pScreen) + /* Reserve static area for hardware cursor */ + if (!xf86ReturnOptValBool(info->Options, OPTION_SW_CURSOR, FALSE)) { + int cursor_size = 64 * 4 * 64; ++ int align = IS_AVIVO_VARIANT ? 4096 : 256; + int c; + + for (c = 0; c < xf86_config->num_crtc; c++) { + xf86CrtcPtr crtc = xf86_config->crtc[c]; + RADEONCrtcPrivatePtr radeon_crtc = crtc->driver_private; + +- radeon_crtc->cursor_offset = info->exa->offScreenBase; +- info->exa->offScreenBase += cursor_size; ++ radeon_crtc->cursor_offset = ++ RADEON_ALIGN(info->exa->offScreenBase, align); ++ info->exa->offScreenBase = radeon_crtc->cursor_offset + cursor_size; + + xf86DrvMsg(pScrn->scrnIndex, X_INFO, + "Will use %d kb for hardware cursor %d at offset 0x%08x\n", +diff --git a/src/radeon_exa_render.c b/src/radeon_exa_render.c +index 4736e4f..5d28d80 100644 +--- a/src/radeon_exa_render.c ++++ b/src/radeon_exa_render.c +@@ -1962,9 +1962,9 @@ static void FUNC_NAME(RadeonCompositeTile)(PixmapPtr pDst, + + #ifdef ACCEL_CP + if (info->ChipFamily < CHIP_FAMILY_R200) { +- BEGIN_RING(4 * vtx_count + 3); ++ BEGIN_RING(3 * vtx_count + 3); + OUT_RING(CP_PACKET3(RADEON_CP_PACKET3_3D_DRAW_IMMD, +- 4 * vtx_count + 1)); ++ 3 * vtx_count + 1)); + if (has_mask) + OUT_RING(RADEON_CP_VC_FRMT_XY | + RADEON_CP_VC_FRMT_ST0 | +@@ -1972,11 +1972,11 @@ static void FUNC_NAME(RadeonCompositeTile)(PixmapPtr pDst, + else + OUT_RING(RADEON_CP_VC_FRMT_XY | + RADEON_CP_VC_FRMT_ST0); +- OUT_RING(RADEON_CP_VC_CNTL_PRIM_TYPE_TRI_FAN | ++ OUT_RING(RADEON_CP_VC_CNTL_PRIM_TYPE_RECT_LIST | + RADEON_CP_VC_CNTL_PRIM_WALK_RING | + RADEON_CP_VC_CNTL_MAOS_ENABLE | + RADEON_CP_VC_CNTL_VTX_FMT_RADEON_MODE | +- (4 << RADEON_CP_VC_CNTL_NUM_SHIFT)); ++ (3 << RADEON_CP_VC_CNTL_NUM_SHIFT)); + } else { + if (IS_R300_3D || IS_R500_3D) + BEGIN_RING(4 * vtx_count + 4); +@@ -1985,7 +1985,7 @@ static void FUNC_NAME(RadeonCompositeTile)(PixmapPtr pDst, + + OUT_RING(CP_PACKET3(R200_CP_PACKET3_3D_DRAW_IMMD_2, + 4 * vtx_count)); +- OUT_RING(RADEON_CP_VC_CNTL_PRIM_TYPE_TRI_FAN | ++ OUT_RING(RADEON_CP_VC_CNTL_PRIM_TYPE_QUAD_LIST | + RADEON_CP_VC_CNTL_PRIM_WALK_RING | + (4 << RADEON_CP_VC_CNTL_NUM_SHIFT)); + } +@@ -1993,25 +1993,29 @@ static void FUNC_NAME(RadeonCompositeTile)(PixmapPtr pDst, + #else /* ACCEL_CP */ + if (IS_R300_3D || IS_R500_3D) + BEGIN_ACCEL(2 + vtx_count * 4); ++ else if (info->ChipFamily < CHIP_FAMILY_R200) ++ BEGIN_ACCEL(1 + vtx_count * 3); + else + BEGIN_ACCEL(1 + vtx_count * 4); + + if (info->ChipFamily < CHIP_FAMILY_R200) { +- OUT_ACCEL_REG(RADEON_SE_VF_CNTL, (RADEON_VF_PRIM_TYPE_TRIANGLE_FAN | ++ OUT_ACCEL_REG(RADEON_SE_VF_CNTL, (RADEON_VF_PRIM_TYPE_RECTANGLE_LIST | + RADEON_VF_PRIM_WALK_DATA | + RADEON_VF_RADEON_MODE | +- 4 << RADEON_VF_NUM_VERTICES_SHIFT)); ++ (3 << RADEON_VF_NUM_VERTICES_SHIFT))); + } else { + OUT_ACCEL_REG(RADEON_SE_VF_CNTL, (RADEON_VF_PRIM_TYPE_QUAD_LIST | + RADEON_VF_PRIM_WALK_DATA | +- 4 << RADEON_VF_NUM_VERTICES_SHIFT)); ++ (4 << RADEON_VF_NUM_VERTICES_SHIFT))); + } + #endif + + if (has_mask) { +- VTX_OUT_MASK((float)dstX, (float)dstY, +- xFixedToFloat(srcTopLeft.x) / info->texW[0], xFixedToFloat(srcTopLeft.y) / info->texH[0], +- xFixedToFloat(maskTopLeft.x) / info->texW[1], xFixedToFloat(maskTopLeft.y) / info->texH[1]); ++ if (info->ChipFamily >= CHIP_FAMILY_R200) { ++ VTX_OUT_MASK((float)dstX, (float)dstY, ++ xFixedToFloat(srcTopLeft.x) / info->texW[0], xFixedToFloat(srcTopLeft.y) / info->texH[0], ++ xFixedToFloat(maskTopLeft.x) / info->texW[1], xFixedToFloat(maskTopLeft.y) / info->texH[1]); ++ } + VTX_OUT_MASK((float)dstX, (float)(dstY + h), + xFixedToFloat(srcBottomLeft.x) / info->texW[0], xFixedToFloat(srcBottomLeft.y) / info->texH[0], + xFixedToFloat(maskBottomLeft.x) / info->texW[1], xFixedToFloat(maskBottomLeft.y) / info->texH[1]); +@@ -2022,8 +2026,10 @@ static void FUNC_NAME(RadeonCompositeTile)(PixmapPtr pDst, + xFixedToFloat(srcTopRight.x) / info->texW[0], xFixedToFloat(srcTopRight.y) / info->texH[0], + xFixedToFloat(maskTopRight.x) / info->texW[1], xFixedToFloat(maskTopRight.y) / info->texH[1]); + } else { +- VTX_OUT((float)dstX, (float)dstY, +- xFixedToFloat(srcTopLeft.x) / info->texW[0], xFixedToFloat(srcTopLeft.y) / info->texH[0]); ++ if (info->ChipFamily >= CHIP_FAMILY_R200) { ++ VTX_OUT((float)dstX, (float)dstY, ++ xFixedToFloat(srcTopLeft.x) / info->texW[0], xFixedToFloat(srcTopLeft.y) / info->texH[0]); ++ } + VTX_OUT((float)dstX, (float)(dstY + h), + xFixedToFloat(srcBottomLeft.x) / info->texW[0], xFixedToFloat(srcBottomLeft.y) / info->texH[0]); + VTX_OUT((float)(dstX + w), (float)(dstY + h), +diff --git a/src/radeon_macros.h b/src/radeon_macros.h +index afe442e..f19bc3e 100644 +--- a/src/radeon_macros.h ++++ b/src/radeon_macros.h +@@ -51,32 +51,6 @@ + + #include "compiler.h" + +-#if HAVE_BYTESWAP_H +-#include +-#elif defined(USE_SYS_ENDIAN_H) +-#include +-#else +-#define bswap_16(value) \ +- ((((value) & 0xff) << 8) | ((value) >> 8)) +- +-#define bswap_32(value) \ +- (((uint32_t)bswap_16((uint16_t)((value) & 0xffff)) << 16) | \ +- (uint32_t)bswap_16((uint16_t)((value) >> 16))) +- +-#define bswap_64(value) \ +- (((uint64_t)bswap_32((uint32_t)((value) & 0xffffffff)) \ +- << 32) | \ +- (uint64_t)bswap_32((uint32_t)((value) >> 32))) +-#endif +- +-#if X_BYTE_ORDER == X_BIG_ENDIAN +-#define le32_to_cpu(x) bswap_32(x) +-#define le16_to_cpu(x) bswap_16(x) +-#else +-#define le32_to_cpu(x) (x) +-#define le16_to_cpu(x) (x) +-#endif +- + #define RADEON_BIOS8(v) (info->VBIOS[v]) + #define RADEON_BIOS16(v) (info->VBIOS[v] | \ + (info->VBIOS[(v) + 1] << 8)) +diff --git a/src/radeon_output.c b/src/radeon_output.c +index 7b89d66..7d7f88a 100644 +--- a/src/radeon_output.c ++++ b/src/radeon_output.c +@@ -173,9 +173,6 @@ static const uint32_t default_tvdac_adj [CHIP_FAMILY_LAST] = + + static void RADEONUpdatePanelSize(xf86OutputPtr output); + static void RADEONGetTMDSInfoFromTable(xf86OutputPtr output); +-#define AVIVO_I2C_DISABLE 0 +-#define AVIVO_I2C_ENABLE 1 +-static Bool AVIVOI2CDoLock(xf86OutputPtr output, int lock_state); + + extern void atombios_output_mode_set(xf86OutputPtr output, + DisplayModePtr mode, +@@ -183,6 +180,8 @@ extern void atombios_output_mode_set(xf86OutputPtr output, + extern void atombios_output_dpms(xf86OutputPtr output, int mode); + extern RADEONMonitorType atombios_dac_detect(ScrnInfoPtr pScrn, xf86OutputPtr output); + extern int atombios_external_tmds_setup(xf86OutputPtr output, DisplayModePtr mode); ++extern AtomBiosResult ++atombios_lock_crtc(atomBiosHandlePtr atomBIOS, int crtc, int lock); + static void + radeon_bios_output_dpms(xf86OutputPtr output, int mode); + static void +@@ -213,88 +212,6 @@ void RADEONPrintPortMap(ScrnInfoPtr pScrn) + + } + +-static xf86MonPtr +-radeon_do_ddc(xf86OutputPtr output) +-{ +- RADEONInfoPtr info = RADEONPTR(output->scrn); +- unsigned char *RADEONMMIO = info->MMIO; +- uint32_t DDCReg; +- xf86MonPtr MonInfo = NULL; +- RADEONOutputPrivatePtr radeon_output = output->driver_private; +- int i, j; +- +- if (radeon_output->pI2CBus) { +- DDCReg = radeon_output->ddc_i2c.mask_clk_reg; +- +- if (IS_AVIVO_VARIANT) { +- AVIVOI2CDoLock(output, AVIVO_I2C_ENABLE); +- MonInfo = xf86OutputGetEDID(output, radeon_output->pI2CBus); +- AVIVOI2CDoLock(output, AVIVO_I2C_DISABLE); +- } else if ((DDCReg == RADEON_LCD_GPIO_MASK) || (DDCReg == RADEON_MDGPIO_EN_REG)) { +- MonInfo = xf86OutputGetEDID(output, radeon_output->pI2CBus); +- } else { +- OUTREG(DDCReg, INREG(DDCReg) & +- (uint32_t)~(RADEON_GPIO_A_0 | RADEON_GPIO_A_1)); +- +- /* For some old monitors (like Compaq Presario FP500), we need +- * following process to initialize/stop DDC +- */ +- OUTREG(DDCReg, INREG(DDCReg) & ~(RADEON_GPIO_EN_1)); +- for (j = 0; j < 3; j++) { +- OUTREG(DDCReg, +- INREG(DDCReg) & ~(RADEON_GPIO_EN_0)); +- usleep(13000); +- +- OUTREG(DDCReg, +- INREG(DDCReg) & ~(RADEON_GPIO_EN_1)); +- for (i = 0; i < 10; i++) { +- usleep(15000); +- if (INREG(DDCReg) & RADEON_GPIO_Y_1) +- break; +- } +- if (i == 10) continue; +- +- usleep(15000); +- +- OUTREG(DDCReg, INREG(DDCReg) | RADEON_GPIO_EN_0); +- usleep(15000); +- +- OUTREG(DDCReg, INREG(DDCReg) | RADEON_GPIO_EN_1); +- usleep(15000); +- OUTREG(DDCReg, +- INREG(DDCReg) & ~(RADEON_GPIO_EN_0)); +- usleep(15000); +- +- MonInfo = xf86OutputGetEDID(output, radeon_output->pI2CBus); +- +- OUTREG(DDCReg, INREG(DDCReg) | RADEON_GPIO_EN_1); +- OUTREG(DDCReg, INREG(DDCReg) | RADEON_GPIO_EN_0); +- usleep(15000); +- OUTREG(DDCReg, +- INREG(DDCReg) & ~(RADEON_GPIO_EN_1)); +- for (i = 0; i < 5; i++) { +- usleep(15000); +- if (INREG(DDCReg) & RADEON_GPIO_Y_1) +- break; +- } +- usleep(15000); +- OUTREG(DDCReg, +- INREG(DDCReg) & ~(RADEON_GPIO_EN_0)); +- usleep(15000); +- +- OUTREG(DDCReg, INREG(DDCReg) | RADEON_GPIO_EN_1); +- OUTREG(DDCReg, INREG(DDCReg) | RADEON_GPIO_EN_0); +- usleep(15000); +- if (MonInfo) break; +- } +- OUTREG(DDCReg, INREG(DDCReg) & +- ~(RADEON_GPIO_EN_0 | RADEON_GPIO_EN_1)); +- } +- } +- +- return MonInfo; +-} +- + static RADEONMonitorType + radeon_ddc_connected(xf86OutputPtr output) + { +@@ -304,8 +221,11 @@ radeon_ddc_connected(xf86OutputPtr output) + xf86MonPtr MonInfo = NULL; + RADEONOutputPrivatePtr radeon_output = output->driver_private; + +- if (radeon_output->pI2CBus) +- MonInfo = radeon_do_ddc(output); ++ if (radeon_output->pI2CBus) { ++ RADEONI2CDoLock(output, TRUE); ++ MonInfo = xf86OutputGetEDID(output, radeon_output->pI2CBus); ++ RADEONI2CDoLock(output, FALSE); ++ } + if (MonInfo) { + if (!xf86ReturnOptValBool(info->Options, OPTION_IGNORE_EDID, FALSE)) + xf86OutputSetEDID(output, MonInfo); +@@ -317,13 +237,14 @@ radeon_ddc_connected(xf86OutputPtr output) + MonType = MT_DFP; + else if (radeon_output->type == OUTPUT_DP) + MonType = MT_DFP; +- else if (radeon_output->type == OUTPUT_DVI_I && (MonInfo->rawData[0x14] & 0x80)) /* if it's digital and DVI */ ++ else if (radeon_output->type == OUTPUT_DVI_I && ++ (MonInfo->rawData[0x14] & 0x80)) /* if it's digital and DVI */ + MonType = MT_DFP; + else + MonType = MT_CRT; + } else + MonType = MT_NONE; +- ++ + xf86DrvMsg(pScrn->scrnIndex, X_INFO, + "Output: %s, Detected Monitor Type: %d\n", output->name, MonType); + +@@ -537,7 +458,7 @@ radeon_mode_fixup(xf86OutputPtr output, DisplayModePtr mode, + if (IS_AVIVO_VARIANT) { + /* set to the panel's native mode */ + adjusted_mode->HDisplay = radeon_output->PanelXRes; +- adjusted_mode->HDisplay = radeon_output->PanelYRes; ++ adjusted_mode->VDisplay = radeon_output->PanelYRes; + adjusted_mode->HTotal = radeon_output->PanelXRes + radeon_output->HBlank; + adjusted_mode->HSyncStart = radeon_output->PanelXRes + radeon_output->HOverPlus; + adjusted_mode->HSyncEnd = adjusted_mode->HSyncStart + radeon_output->HSyncWidth; +@@ -580,12 +501,20 @@ radeon_mode_fixup(xf86OutputPtr output, DisplayModePtr mode, + } + } + ++ if (IS_AVIVO_VARIANT) { ++ /* hw bug */ ++ if ((mode->Flags & V_INTERLACE) ++ && (mode->CrtcVSyncStart < (mode->CrtcVDisplay + 2))) ++ adjusted_mode->CrtcVSyncStart = adjusted_mode->CrtcVDisplay + 2; ++ } ++ + return TRUE; + } + + static void + radeon_mode_prepare(xf86OutputPtr output) + { ++ RADEONInfoPtr info = RADEONPTR(output->scrn); + xf86CrtcConfigPtr config = XF86_CRTC_CONFIG_PTR (output->scrn); + int o; + +@@ -595,9 +524,12 @@ radeon_mode_prepare(xf86OutputPtr output) + continue; + else if (loop_output->crtc) { + xf86CrtcPtr other_crtc = loop_output->crtc; ++ RADEONCrtcPrivatePtr other_radeon_crtc = other_crtc->driver_private; + if (other_crtc->enabled) { +- radeon_dpms(loop_output, DPMSModeOff); + radeon_crtc_dpms(other_crtc, DPMSModeOff); ++ if (IS_AVIVO_VARIANT) ++ atombios_lock_crtc(info->atomBIOS, other_radeon_crtc->crtc_id, 1); ++ radeon_dpms(loop_output, DPMSModeOff); + } + } + } +@@ -625,6 +557,7 @@ radeon_mode_set(xf86OutputPtr output, DisplayModePtr mode, + static void + radeon_mode_commit(xf86OutputPtr output) + { ++ RADEONInfoPtr info = RADEONPTR(output->scrn); + xf86CrtcConfigPtr config = XF86_CRTC_CONFIG_PTR (output->scrn); + int o; + +@@ -634,9 +567,12 @@ radeon_mode_commit(xf86OutputPtr output) + continue; + else if (loop_output->crtc) { + xf86CrtcPtr other_crtc = loop_output->crtc; ++ RADEONCrtcPrivatePtr other_radeon_crtc = other_crtc->driver_private; + if (other_crtc->enabled) { +- radeon_dpms(loop_output, DPMSModeOn); + radeon_crtc_dpms(other_crtc, DPMSModeOn); ++ if (IS_AVIVO_VARIANT) ++ atombios_lock_crtc(info->atomBIOS, other_radeon_crtc->crtc_id, 0); ++ radeon_dpms(loop_output, DPMSModeOn); + } + } + } +@@ -1682,8 +1618,8 @@ Bool AVIVOI2CReset(ScrnInfoPtr pScrn) + } + #endif + +-static +-Bool AVIVOI2CDoLock(xf86OutputPtr output, int lock_state) ++Bool ++RADEONI2CDoLock(xf86OutputPtr output, int lock_state) + { + ScrnInfoPtr pScrn = output->scrn; + RADEONInfoPtr info = RADEONPTR(pScrn); +@@ -1692,19 +1628,29 @@ Bool AVIVOI2CDoLock(xf86OutputPtr output, int lock_state) + unsigned char *RADEONMMIO = info->MMIO; + uint32_t temp; + ++ if (lock_state) { ++ temp = INREG(pRADEONI2CBus->a_clk_reg); ++ temp &= ~(pRADEONI2CBus->a_clk_mask); ++ OUTREG(pRADEONI2CBus->a_clk_reg, temp); ++ ++ temp = INREG(pRADEONI2CBus->a_data_reg); ++ temp &= ~(pRADEONI2CBus->a_data_mask); ++ OUTREG(pRADEONI2CBus->a_data_reg, temp); ++ } ++ + temp = INREG(pRADEONI2CBus->mask_clk_reg); +- if (lock_state == AVIVO_I2C_ENABLE) +- temp |= (pRADEONI2CBus->put_clk_mask); ++ if (lock_state) ++ temp |= (pRADEONI2CBus->mask_clk_mask); + else +- temp &= ~(pRADEONI2CBus->put_clk_mask); ++ temp &= ~(pRADEONI2CBus->mask_clk_mask); + OUTREG(pRADEONI2CBus->mask_clk_reg, temp); + temp = INREG(pRADEONI2CBus->mask_clk_reg); + + temp = INREG(pRADEONI2CBus->mask_data_reg); +- if (lock_state == AVIVO_I2C_ENABLE) +- temp |= (pRADEONI2CBus->put_data_mask); ++ if (lock_state) ++ temp |= (pRADEONI2CBus->mask_data_mask); + else +- temp &= ~(pRADEONI2CBus->put_data_mask); ++ temp &= ~(pRADEONI2CBus->mask_data_mask); + OUTREG(pRADEONI2CBus->mask_data_reg, temp); + temp = INREG(pRADEONI2CBus->mask_data_reg); + +@@ -1786,8 +1732,10 @@ legacy_setup_i2c_bus(int ddc_line) + { + RADEONI2CBusRec i2c; + +- i2c.mask_clk_mask = RADEON_GPIO_EN_1 | RADEON_GPIO_Y_1; +- i2c.mask_data_mask = RADEON_GPIO_EN_0 | RADEON_GPIO_Y_0; ++ i2c.mask_clk_mask = RADEON_GPIO_EN_1; ++ i2c.mask_data_mask = RADEON_GPIO_EN_0; ++ i2c.a_clk_mask = RADEON_GPIO_A_1; ++ i2c.a_data_mask = RADEON_GPIO_A_0; + i2c.put_clk_mask = RADEON_GPIO_EN_1; + i2c.put_data_mask = RADEON_GPIO_EN_0; + i2c.get_clk_mask = RADEON_GPIO_Y_1; +@@ -1796,6 +1744,8 @@ legacy_setup_i2c_bus(int ddc_line) + (ddc_line == RADEON_MDGPIO_EN_REG)) { + i2c.mask_clk_reg = ddc_line; + i2c.mask_data_reg = ddc_line; ++ i2c.a_clk_reg = ddc_line; ++ i2c.a_data_reg = ddc_line; + i2c.put_clk_reg = ddc_line; + i2c.put_data_reg = ddc_line; + i2c.get_clk_reg = ddc_line + 4; +@@ -1803,6 +1753,8 @@ legacy_setup_i2c_bus(int ddc_line) + } else { + i2c.mask_clk_reg = ddc_line; + i2c.mask_data_reg = ddc_line; ++ i2c.a_clk_reg = ddc_line; ++ i2c.a_data_reg = ddc_line; + i2c.put_clk_reg = ddc_line; + i2c.put_data_reg = ddc_line; + i2c.get_clk_reg = ddc_line; +@@ -1829,6 +1781,8 @@ atom_setup_i2c_bus(int ddc_line) + i2c.get_data_mask = (1 << 18); + i2c.mask_clk_mask = (1 << 19); + i2c.mask_data_mask = (1 << 18); ++ i2c.a_clk_mask = (1 << 19); ++ i2c.a_data_mask = (1 << 18); + } else { + i2c.put_clk_mask = (1 << 0); + i2c.put_data_mask = (1 << 8); +@@ -1836,9 +1790,13 @@ atom_setup_i2c_bus(int ddc_line) + i2c.get_data_mask = (1 << 8); + i2c.mask_clk_mask = (1 << 0); + i2c.mask_data_mask = (1 << 8); ++ i2c.a_clk_mask = (1 << 0); ++ i2c.a_data_mask = (1 << 8); + } + i2c.mask_clk_reg = ddc_line; + i2c.mask_data_reg = ddc_line; ++ i2c.a_clk_reg = ddc_line + 0x4; ++ i2c.a_data_reg = ddc_line + 0x4; + i2c.put_clk_reg = ddc_line + 0x8; + i2c.put_data_reg = ddc_line + 0x8; + i2c.get_clk_reg = ddc_line + 0xc; +@@ -2301,7 +2259,7 @@ static Bool RADEONSetupAppleConnectors(ScrnInfoPtr pScrn) + info->BiosConnector[0].ddc_i2c = legacy_setup_i2c_bus(RADEON_GPIO_DVI_DDC); + info->BiosConnector[0].DACType = DAC_NONE; + info->BiosConnector[0].TMDSType = TMDS_NONE; +- info->BiosConnector[0].ConnectorType = CONNECTOR_VGA; ++ info->BiosConnector[0].ConnectorType = CONNECTOR_LVDS; + info->BiosConnector[0].valid = TRUE; + + info->BiosConnector[1].ddc_i2c = legacy_setup_i2c_bus(RADEON_GPIO_VGA_DDC); +@@ -2677,7 +2635,6 @@ Bool RADEONSetupConnectors(ScrnInfoPtr pScrn) + { + xf86CrtcConfigPtr xf86_config = XF86_CRTC_CONFIG_PTR(pScrn); + RADEONInfoPtr info = RADEONPTR(pScrn); +- RADEONEntPtr pRADEONEnt = RADEONEntPriv(pScrn); + xf86OutputPtr output; + char *optstr; + int i = 0; +@@ -2742,13 +2699,6 @@ Bool RADEONSetupConnectors(ScrnInfoPtr pScrn) + RADEONSetupGenericConnectors(pScrn); + } + +- if (!pRADEONEnt->HasCRTC2) { +- for (i = 0; i < RADEON_MAX_BIOS_CONNECTOR; i++) { +- if (info->BiosConnector[i].ConnectorType == CONNECTOR_VGA) +- info->BiosConnector[i].DACType = DAC_PRIMARY; +- } +- } +- + /* parse connector table option */ + optstr = (char *)xf86GetOptValString(info->Options, OPTION_CONNECTORTABLE); + +diff --git a/src/radeon_pci_chipset_gen.h b/src/radeon_pci_chipset_gen.h +index 39adb5e..f24deb5 100644 +--- a/src/radeon_pci_chipset_gen.h ++++ b/src/radeon_pci_chipset_gen.h +@@ -1,6 +1,7 @@ + /* This file is autogenerated please do not edit */ + PciChipsets RADEONPciChipsets[] = { + { PCI_CHIP_RV380_3150, PCI_CHIP_RV380_3150, RES_SHARED_VGA }, ++ { PCI_CHIP_RV380_3151, PCI_CHIP_RV380_3151, RES_SHARED_VGA }, + { PCI_CHIP_RV380_3152, PCI_CHIP_RV380_3152, RES_SHARED_VGA }, + { PCI_CHIP_RV380_3154, PCI_CHIP_RV380_3154, RES_SHARED_VGA }, + { PCI_CHIP_RV380_3E50, PCI_CHIP_RV380_3E50, RES_SHARED_VGA }, +@@ -250,6 +251,8 @@ PciChipsets RADEONPciChipsets[] = { + { PCI_CHIP_R600_940A, PCI_CHIP_R600_940A, RES_SHARED_VGA }, + { PCI_CHIP_R600_940B, PCI_CHIP_R600_940B, RES_SHARED_VGA }, + { PCI_CHIP_R600_940F, PCI_CHIP_R600_940F, RES_SHARED_VGA }, ++ { PCI_CHIP_RV770_9440, PCI_CHIP_RV770_9440, RES_SHARED_VGA }, ++ { PCI_CHIP_RV770_9442, PCI_CHIP_RV770_9442, RES_SHARED_VGA }, + { PCI_CHIP_RV610_94C0, PCI_CHIP_RV610_94C0, RES_SHARED_VGA }, + { PCI_CHIP_RV610_94C1, PCI_CHIP_RV610_94C1, RES_SHARED_VGA }, + { PCI_CHIP_RV610_94C3, PCI_CHIP_RV610_94C3, RES_SHARED_VGA }, +@@ -267,6 +270,7 @@ PciChipsets RADEONPciChipsets[] = { + { PCI_CHIP_RV670_9507, PCI_CHIP_RV670_9507, RES_SHARED_VGA }, + { PCI_CHIP_RV670_950F, PCI_CHIP_RV670_950F, RES_SHARED_VGA }, + { PCI_CHIP_RV670_9511, PCI_CHIP_RV670_9511, RES_SHARED_VGA }, ++ { PCI_CHIP_RV670_9515, PCI_CHIP_RV670_9515, RES_SHARED_VGA }, + { PCI_CHIP_RV630_9580, PCI_CHIP_RV630_9580, RES_SHARED_VGA }, + { PCI_CHIP_RV630_9581, PCI_CHIP_RV630_9581, RES_SHARED_VGA }, + { PCI_CHIP_RV630_9583, PCI_CHIP_RV630_9583, RES_SHARED_VGA }, +diff --git a/src/radeon_pci_device_match_gen.h b/src/radeon_pci_device_match_gen.h +index d81cbe3..aa19d6a 100644 +--- a/src/radeon_pci_device_match_gen.h ++++ b/src/radeon_pci_device_match_gen.h +@@ -1,6 +1,7 @@ + /* This file is autogenerated please do not edit */ + static const struct pci_id_match radeon_device_match[] = { + ATI_DEVICE_MATCH( PCI_CHIP_RV380_3150, 0 ), ++ ATI_DEVICE_MATCH( PCI_CHIP_RV380_3151, 0 ), + ATI_DEVICE_MATCH( PCI_CHIP_RV380_3152, 0 ), + ATI_DEVICE_MATCH( PCI_CHIP_RV380_3154, 0 ), + ATI_DEVICE_MATCH( PCI_CHIP_RV380_3E50, 0 ), +@@ -250,6 +251,8 @@ static const struct pci_id_match radeon_device_match[] = { + ATI_DEVICE_MATCH( PCI_CHIP_R600_940A, 0 ), + ATI_DEVICE_MATCH( PCI_CHIP_R600_940B, 0 ), + ATI_DEVICE_MATCH( PCI_CHIP_R600_940F, 0 ), ++ ATI_DEVICE_MATCH( PCI_CHIP_RV770_9440, 0 ), ++ ATI_DEVICE_MATCH( PCI_CHIP_RV770_9442, 0 ), + ATI_DEVICE_MATCH( PCI_CHIP_RV610_94C0, 0 ), + ATI_DEVICE_MATCH( PCI_CHIP_RV610_94C1, 0 ), + ATI_DEVICE_MATCH( PCI_CHIP_RV610_94C3, 0 ), +@@ -267,6 +270,7 @@ static const struct pci_id_match radeon_device_match[] = { + ATI_DEVICE_MATCH( PCI_CHIP_RV670_9507, 0 ), + ATI_DEVICE_MATCH( PCI_CHIP_RV670_950F, 0 ), + ATI_DEVICE_MATCH( PCI_CHIP_RV670_9511, 0 ), ++ ATI_DEVICE_MATCH( PCI_CHIP_RV670_9515, 0 ), + ATI_DEVICE_MATCH( PCI_CHIP_RV630_9580, 0 ), + ATI_DEVICE_MATCH( PCI_CHIP_RV630_9581, 0 ), + ATI_DEVICE_MATCH( PCI_CHIP_RV630_9583, 0 ), +diff --git a/src/radeon_probe.h b/src/radeon_probe.h +index 24af52b..3770abf 100644 +--- a/src/radeon_probe.h ++++ b/src/radeon_probe.h +@@ -166,6 +166,8 @@ typedef struct + Bool valid; + uint32_t mask_clk_reg; + uint32_t mask_data_reg; ++ uint32_t a_clk_reg; ++ uint32_t a_data_reg; + uint32_t put_clk_reg; + uint32_t put_data_reg; + uint32_t get_clk_reg; +@@ -176,6 +178,8 @@ typedef struct + uint32_t put_data_mask; + uint32_t get_clk_mask; + uint32_t get_data_mask; ++ uint32_t a_clk_mask; ++ uint32_t a_data_mask; + } RADEONI2CBusRec, *RADEONI2CBusPtr; + + typedef struct _RADEONCrtcPrivateRec { +@@ -310,8 +314,10 @@ struct avivo_grph_state { + uint32_t x_end; + uint32_t y_end; + ++ uint32_t desktop_height; + uint32_t viewport_start; + uint32_t viewport_size; ++ uint32_t mode_data_format; + }; + + struct avivo_state +@@ -326,6 +332,7 @@ struct avivo_state + + uint32_t crtc_master_en; + uint32_t crtc_tv_control; ++ uint32_t dc_lb_memory_split; + + struct avivo_pll_state pll1; + struct avivo_pll_state pll2; +diff --git a/src/radeon_reg.h b/src/radeon_reg.h +index 59e2f12..1d35236 100644 +--- a/src/radeon_reg.h ++++ b/src/radeon_reg.h +@@ -1032,6 +1032,10 @@ + #define RADEON_OV0_BASE_ADDR 0x43c + #define RADEON_NB_TOM 0x15c + #define R300_MC_INIT_MISC_LAT_TIMER 0x180 ++# define R300_MC_DISP0R_INIT_LAT_SHIFT 8 ++# define R300_MC_DISP0R_INIT_LAT_MASK 0xf ++# define R300_MC_DISP1R_INIT_LAT_SHIFT 12 ++# define R300_MC_DISP1R_INIT_LAT_MASK 0xf + #define RADEON_MCLK_CNTL 0x0012 /* PLL */ + # define RADEON_FORCEON_MCLKA (1 << 16) + # define RADEON_FORCEON_MCLKB (1 << 17) +@@ -3185,6 +3189,7 @@ + #define RADEON_CP_VC_CNTL_PRIM_TYPE_RECT_LIST 0x00000008 + #define RADEON_CP_VC_CNTL_PRIM_TYPE_3VRT_POINT_LIST 0x00000009 + #define RADEON_CP_VC_CNTL_PRIM_TYPE_3VRT_LINE_LIST 0x0000000a ++#define RADEON_CP_VC_CNTL_PRIM_TYPE_QUAD_LIST 0x0000000d + #define RADEON_CP_VC_CNTL_PRIM_WALK_IND 0x00000010 + #define RADEON_CP_VC_CNTL_PRIM_WALK_LIST 0x00000020 + #define RADEON_CP_VC_CNTL_PRIM_WALK_RING 0x00000030 +@@ -3418,6 +3423,7 @@ + #define RS690_MC_AGP_LOCATION 0x101 + #define RS690_MC_AGP_BASE 0x102 + #define RS690_MC_AGP_BASE_2 0x103 ++#define RS690_MC_INIT_MISC_LAT_TIMER 0x104 + #define RS690_MC_STATUS 0x90 + #define RS690_MC_STATUS_IDLE (1 << 0) + +@@ -3431,12 +3437,13 @@ + #define RS600_MC_STATUS 0x0 + #define RS600_MC_STATUS_IDLE (1 << 0) + +-#define AVIVO_MC_INDEX 0x0070 +-#define R520_MC_STATUS 0x00 +-#define R520_MC_STATUS_IDLE (1<<1) +-#define RV515_MC_STATUS 0x08 +-#define RV515_MC_STATUS_IDLE (1<<4) +-#define AVIVO_MC_DATA 0x0074 ++#define AVIVO_MC_INDEX 0x0070 ++#define R520_MC_STATUS 0x00 ++# define R520_MC_STATUS_IDLE (1 << 1) ++#define RV515_MC_STATUS 0x08 ++# define RV515_MC_STATUS_IDLE (1 << 4) ++#define RV515_MC_INIT_MISC_LAT_TIMER 0x09 ++#define AVIVO_MC_DATA 0x0074 + + #define RV515_MC_FB_LOCATION 0x1 + #define RV515_MC_AGP_LOCATION 0x2 +@@ -3598,8 +3605,20 @@ + #define AVIVO_DC_LUTA_WHITE_OFFSET_GREEN 0x64d4 + #define AVIVO_DC_LUTA_WHITE_OFFSET_RED 0x64d8 + +- +-#define AVIVO_D1MODE_DESKTOP_HEIGHT 0x652C ++#define AVIVO_DC_LB_MEMORY_SPLIT 0x6520 ++# define AVIVO_DC_LB_MEMORY_SPLIT_MASK 0x3 ++# define AVIVO_DC_LB_MEMORY_SPLIT_SHIFT 0 ++# define AVIVO_DC_LB_MEMORY_SPLIT_D1HALF_D2HALF 0 ++# define AVIVO_DC_LB_MEMORY_SPLIT_D1_3Q_D2_1Q 1 ++# define AVIVO_DC_LB_MEMORY_SPLIT_D1_ONLY 2 ++# define AVIVO_DC_LB_MEMORY_SPLIT_D1_1Q_D2_3Q 3 ++# define AVIVO_DC_LB_MEMORY_SPLIT_SHIFT_MODE (1 << 2) ++# define AVIVO_DC_LB_DISP1_END_ADR_SHIFT 4 ++# define AVIVO_DC_LB_DISP1_END_ADR_MASK 0x7ff ++ ++#define AVIVO_D1MODE_DATA_FORMAT 0x6528 ++# define AVIVO_D1MODE_INTERLEAVE_EN (1 << 0) ++#define AVIVO_D1MODE_DESKTOP_HEIGHT 0x652c + #define AVIVO_D1MODE_VIEWPORT_START 0x6580 + #define AVIVO_D1MODE_VIEWPORT_SIZE 0x6584 + #define AVIVO_D1MODE_EXT_OVERSCAN_LEFT_RIGHT 0x6588 +@@ -3651,6 +3670,8 @@ + #define AVIVO_D2CUR_SIZE 0x6c10 + #define AVIVO_D2CUR_POSITION 0x6c14 + ++#define AVIVO_D2MODE_DATA_FORMAT 0x6d28 ++#define AVIVO_D2MODE_DESKTOP_HEIGHT 0x6d2c + #define AVIVO_D2MODE_VIEWPORT_START 0x6d80 + #define AVIVO_D2MODE_VIEWPORT_SIZE 0x6d84 + #define AVIVO_D2MODE_EXT_OVERSCAN_LEFT_RIGHT 0x6d88 +@@ -3658,6 +3679,7 @@ + + #define AVIVO_D2SCL_SCALER_ENABLE 0x6d90 + #define AVIVO_D2SCL_SCALER_TAP_CONTROL 0x6d94 ++#define AVIVO_D2SCL_UPDATE 0x6dcc + + #define AVIVO_DDIA_BIT_DEPTH_CONTROL 0x7214 + +@@ -3918,6 +3940,8 @@ + #define R600_MC_VM_SYSTEM_APERTURE_HIGH_ADDR 0x2194 + #define R600_MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR 0x2198 + ++#define R700_MC_VM_FB_LOCATION 0x2024 ++ + #define R600_HDP_NONSURFACE_BASE 0x2c04 + + #define R600_BUS_CNTL 0x5420 +diff --git a/src/radeon_textured_videofuncs.c b/src/radeon_textured_videofuncs.c +index 277d9b2..d39f74d 100644 +--- a/src/radeon_textured_videofuncs.c ++++ b/src/radeon_textured_videofuncs.c +@@ -486,6 +486,8 @@ FUNC_NAME(RADEONDisplayTexturedVideo)(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv + OUT_VIDEO_REG(R200_PP_TXFILTER_0, + R200_MAG_FILTER_LINEAR | + R200_MIN_FILTER_LINEAR | ++ R200_CLAMP_S_CLAMP_LAST | ++ R200_CLAMP_T_CLAMP_LAST | + R200_YUV_TO_RGB); + OUT_VIDEO_REG(R200_PP_TXFORMAT_0, txformat); + OUT_VIDEO_REG(R200_PP_TXFORMAT_X_0, 0); +@@ -521,8 +523,11 @@ FUNC_NAME(RADEONDisplayTexturedVideo)(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv + OUT_VIDEO_REG(RADEON_SE_VTX_FMT, RADEON_SE_VTX_FMT_XY | + RADEON_SE_VTX_FMT_ST0); + +- OUT_VIDEO_REG(RADEON_PP_TXFILTER_0, RADEON_MAG_FILTER_LINEAR | ++ OUT_VIDEO_REG(RADEON_PP_TXFILTER_0, ++ RADEON_MAG_FILTER_LINEAR | + RADEON_MIN_FILTER_LINEAR | ++ RADEON_CLAMP_S_CLAMP_LAST | ++ RADEON_CLAMP_T_CLAMP_LAST | + RADEON_YUV_TO_RGB); + OUT_VIDEO_REG(RADEON_PP_TXFORMAT_0, txformat); + OUT_VIDEO_REG(RADEON_PP_TXOFFSET_0, pPriv->src_offset); +@@ -582,16 +587,16 @@ FUNC_NAME(RADEONDisplayTexturedVideo)(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv + + #ifdef ACCEL_CP + if (info->ChipFamily < CHIP_FAMILY_R200) { +- BEGIN_RING(4 * VTX_DWORD_COUNT + 3); ++ BEGIN_RING(3 * VTX_DWORD_COUNT + 3); + OUT_RING(CP_PACKET3(RADEON_CP_PACKET3_3D_DRAW_IMMD, +- 4 * VTX_DWORD_COUNT + 1)); ++ 3 * VTX_DWORD_COUNT + 1)); + OUT_RING(RADEON_CP_VC_FRMT_XY | + RADEON_CP_VC_FRMT_ST0); +- OUT_RING(RADEON_CP_VC_CNTL_PRIM_TYPE_TRI_FAN | ++ OUT_RING(RADEON_CP_VC_CNTL_PRIM_TYPE_RECT_LIST | + RADEON_CP_VC_CNTL_PRIM_WALK_RING | + RADEON_CP_VC_CNTL_MAOS_ENABLE | + RADEON_CP_VC_CNTL_VTX_FMT_RADEON_MODE | +- (4 << RADEON_CP_VC_CNTL_NUM_SHIFT)); ++ (3 << RADEON_CP_VC_CNTL_NUM_SHIFT)); + } else { + if (IS_R300_3D || IS_R500_3D) + BEGIN_RING(4 * VTX_DWORD_COUNT + 4); +@@ -599,30 +604,33 @@ FUNC_NAME(RADEONDisplayTexturedVideo)(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv + BEGIN_RING(4 * VTX_DWORD_COUNT + 2); + OUT_RING(CP_PACKET3(R200_CP_PACKET3_3D_DRAW_IMMD_2, + 4 * VTX_DWORD_COUNT)); +- OUT_RING(RADEON_CP_VC_CNTL_PRIM_TYPE_TRI_FAN | ++ OUT_RING(RADEON_CP_VC_CNTL_PRIM_TYPE_QUAD_LIST | + RADEON_CP_VC_CNTL_PRIM_WALK_RING | + (4 << RADEON_CP_VC_CNTL_NUM_SHIFT)); + } + #else /* ACCEL_CP */ + if (IS_R300_3D || IS_R500_3D) + BEGIN_VIDEO(2 + VTX_DWORD_COUNT * 4); ++ else if (info->ChipFamily < CHIP_FAMILY_R200) ++ BEGIN_VIDEO(1 + VTX_DWORD_COUNT * 3); + else + BEGIN_VIDEO(1 + VTX_DWORD_COUNT * 4); + + if (info->ChipFamily < CHIP_FAMILY_R200) { +- OUT_VIDEO_REG(RADEON_SE_VF_CNTL, (RADEON_VF_PRIM_TYPE_TRIANGLE_FAN | ++ OUT_VIDEO_REG(RADEON_SE_VF_CNTL, (RADEON_VF_PRIM_TYPE_RECTANGLE_LIST | + RADEON_VF_PRIM_WALK_DATA | + RADEON_VF_RADEON_MODE | +- 4 << RADEON_VF_NUM_VERTICES_SHIFT)); ++ (3 << RADEON_VF_NUM_VERTICES_SHIFT))); + } else { + OUT_VIDEO_REG(RADEON_SE_VF_CNTL, (RADEON_VF_PRIM_TYPE_QUAD_LIST | + RADEON_VF_PRIM_WALK_DATA | +- 4 << RADEON_VF_NUM_VERTICES_SHIFT)); ++ (4 << RADEON_VF_NUM_VERTICES_SHIFT))); + } + #endif +- +- VTX_OUT((float)dstX, (float)dstY, +- xFixedToFloat(srcTopLeft.x) / info->texW[0], xFixedToFloat(srcTopLeft.y) / info->texH[0]); ++ if (info->ChipFamily >= CHIP_FAMILY_R200) { ++ VTX_OUT((float)dstX, (float)dstY, ++ xFixedToFloat(srcTopLeft.x) / info->texW[0], xFixedToFloat(srcTopLeft.y) / info->texH[0]); ++ } + VTX_OUT((float)dstX, (float)(dstY + dsth), + xFixedToFloat(srcBottomLeft.x) / info->texW[0], xFixedToFloat(srcBottomLeft.y) / info->texH[0]); + VTX_OUT((float)(dstX + dstw), (float)(dstY + dsth), +diff --git a/src/radeon_tv.c b/src/radeon_tv.c +index 90020b3..90d1ac9 100644 +--- a/src/radeon_tv.c ++++ b/src/radeon_tv.c +@@ -140,7 +140,7 @@ static const uint16_t vert_timing_PAL[] = + **********************************************************************/ + static const TVModeConstants availableTVModes[] = + { +- { ++ { /* NTSC timing for 27 Mhz ref clk */ + 800, /* horResolution */ + 600, /* verResolution */ + TV_STD_NTSC, /* standard */ +@@ -155,7 +155,7 @@ static const TVModeConstants availableTVModes[] = + 4, /* crtcPLL_postDiv */ + 1022, /* pixToTV */ + }, +- { ++ { /* PAL timing for 27 Mhz ref clk */ + 800, /* horResolution */ + 600, /* verResolution */ + TV_STD_PAL, /* standard */ +@@ -169,7 +169,22 @@ static const TVModeConstants availableTVModes[] = + 231, /* crtcPLL_M */ + 4, /* crtcPLL_postDiv */ + 759, /* pixToTV */ +- } ++ }, ++ { /* NTSC timing for 14 Mhz ref clk */ ++ 800, /* horResolution */ ++ 600, /* verResolution */ ++ TV_STD_NTSC, /* standard */ ++ 1018, /* horTotal */ ++ 727, /* verTotal */ ++ 813, /* horStart */ ++ 840, /* horSyncStart */ ++ 633, /* verSyncStart */ ++ 630627, /* defRestart */ ++ 347, /* crtcPLL_N */ ++ 14, /* crtcPLL_M */ ++ 8, /* crtcPLL_postDiv */ ++ 1022, /* pixToTV */ ++ }, + }; + + #define N_AVAILABLE_MODES (sizeof(availableModes) / sizeof(availableModes[ 0 ])) +@@ -582,6 +597,8 @@ static Bool RADEONInitTVRestarts(xf86OutputPtr output, RADEONSavePtr save, + DisplayModePtr mode) + { + RADEONOutputPrivatePtr radeon_output = output->driver_private; ++ RADEONInfoPtr info = RADEONPTR(output->scrn); ++ RADEONPLLPtr pll = &info->pll; + int restart; + unsigned hTotal; + unsigned vTotal; +@@ -597,14 +614,21 @@ static Bool RADEONInitTVRestarts(xf86OutputPtr output, RADEONSavePtr save, + /* FIXME: need to revisit this when we add more modes */ + if (radeon_output->tvStd == TV_STD_NTSC || + radeon_output->tvStd == TV_STD_NTSC_J || +- radeon_output->tvStd == TV_STD_PAL_M) +- constPtr = &availableTVModes[0]; +- else +- constPtr = &availableTVModes[1]; ++ radeon_output->tvStd == TV_STD_PAL_M) { ++ if (pll->reference_freq == 2700) ++ constPtr = &availableTVModes[0]; ++ else ++ constPtr = &availableTVModes[2]; ++ } else { ++ if (pll->reference_freq == 2700) ++ constPtr = &availableTVModes[1]; ++ else ++ constPtr = &availableTVModes[1]; /* FIXME */ ++ } + + hTotal = constPtr->horTotal; + vTotal = constPtr->verTotal; +- ++ + if (radeon_output->tvStd == TV_STD_NTSC || + radeon_output->tvStd == TV_STD_NTSC_J || + radeon_output->tvStd == TV_STD_PAL_M || +@@ -696,6 +720,8 @@ void RADEONInitTVRegisters(xf86OutputPtr output, RADEONSavePtr save, + ScrnInfoPtr pScrn = output->scrn; + RADEONOutputPrivatePtr radeon_output = output->driver_private; + RADEONInfoPtr info = RADEONPTR(pScrn); ++ RADEONPLLPtr pll = &info->pll; ++ unsigned m, n, p; + unsigned i; + unsigned long vert_space, flicker_removal; + uint32_t tmp; +@@ -703,14 +729,20 @@ void RADEONInitTVRegisters(xf86OutputPtr output, RADEONSavePtr save, + const uint16_t *hor_timing; + const uint16_t *vert_timing; + +- + /* FIXME: need to revisit this when we add more modes */ + if (radeon_output->tvStd == TV_STD_NTSC || + radeon_output->tvStd == TV_STD_NTSC_J || +- radeon_output->tvStd == TV_STD_PAL_M) +- constPtr = &availableTVModes[0]; +- else +- constPtr = &availableTVModes[1]; ++ radeon_output->tvStd == TV_STD_PAL_M) { ++ if (pll->reference_freq == 2700) ++ constPtr = &availableTVModes[0]; ++ else ++ constPtr = &availableTVModes[2]; ++ } else { ++ if (pll->reference_freq == 2700) ++ constPtr = &availableTVModes[1]; ++ else ++ constPtr = &availableTVModes[1]; /* FIXME */ ++ } + + save->tv_crc_cntl = 0; + +@@ -796,7 +828,10 @@ void RADEONInitTVRegisters(xf86OutputPtr output, RADEONSavePtr save, + save->tv_vscaler_cntl1 = RADEON_Y_W_EN; + save->tv_vscaler_cntl1 = + (save->tv_vscaler_cntl1 & 0xe3ff0000) | (vert_space * (1 << FRAC_BITS) / 10000); +- save->tv_vscaler_cntl1 |= RADEON_RESTART_FIELD; ++ ++ if (pll->reference_freq == 2700) ++ save->tv_vscaler_cntl1 |= RADEON_RESTART_FIELD; ++ + if (constPtr->horResolution == 1024) + save->tv_vscaler_cntl1 |= (4 << RADEON_Y_DEL_W_SIG_SHIFT); + else +@@ -873,18 +908,33 @@ void RADEONInitTVRegisters(xf86OutputPtr output, RADEONSavePtr save, + #endif + + if (radeon_output->tvStd == TV_STD_NTSC || +- radeon_output->tvStd == TV_STD_NTSC_J) +- save->tv_pll_cntl = (NTSC_TV_PLL_M & RADEON_TV_M0LO_MASK) | +- (((NTSC_TV_PLL_M >> 8) & RADEON_TV_M0HI_MASK) << RADEON_TV_M0HI_SHIFT) | +- ((NTSC_TV_PLL_N & RADEON_TV_N0LO_MASK) << RADEON_TV_N0LO_SHIFT) | +- (((NTSC_TV_PLL_N >> 9) & RADEON_TV_N0HI_MASK) << RADEON_TV_N0HI_SHIFT) | +- ((NTSC_TV_PLL_P & RADEON_TV_P_MASK) << RADEON_TV_P_SHIFT); +- else +- save->tv_pll_cntl = (PAL_TV_PLL_M & RADEON_TV_M0LO_MASK) | +- (((PAL_TV_PLL_M >> 8) & RADEON_TV_M0HI_MASK) << RADEON_TV_M0HI_SHIFT) | +- ((PAL_TV_PLL_N & RADEON_TV_N0LO_MASK) << RADEON_TV_N0LO_SHIFT) | +- (((PAL_TV_PLL_N >> 9) & RADEON_TV_N0HI_MASK) << RADEON_TV_N0HI_SHIFT) | +- ((PAL_TV_PLL_P & RADEON_TV_P_MASK) << RADEON_TV_P_SHIFT); ++ radeon_output->tvStd == TV_STD_NTSC_J) { ++ if (pll->reference_freq == 2700) { ++ m = NTSC_TV_PLL_M_27; ++ n = NTSC_TV_PLL_N_27; ++ p = NTSC_TV_PLL_P_27; ++ } else { ++ m = NTSC_TV_PLL_M_14; ++ n = NTSC_TV_PLL_N_14; ++ p = NTSC_TV_PLL_P_14; ++ } ++ } else { ++ if (pll->reference_freq == 2700) { ++ m = PAL_TV_PLL_M_27; ++ n = PAL_TV_PLL_N_27; ++ p = PAL_TV_PLL_P_27; ++ } else { ++ /* FIXME */ ++ m = PAL_TV_PLL_M_27; ++ n = PAL_TV_PLL_N_27; ++ p = PAL_TV_PLL_P_27; ++ } ++ } ++ save->tv_pll_cntl = (m & RADEON_TV_M0LO_MASK) | ++ (((m >> 8) & RADEON_TV_M0HI_MASK) << RADEON_TV_M0HI_SHIFT) | ++ ((n & RADEON_TV_N0LO_MASK) << RADEON_TV_N0LO_SHIFT) | ++ (((n >> 9) & RADEON_TV_N0HI_MASK) << RADEON_TV_N0HI_SHIFT) | ++ ((p & RADEON_TV_P_MASK) << RADEON_TV_P_SHIFT); + + save->tv_pll_cntl1 = (((4 & RADEON_TVPCP_MASK)<< RADEON_TVPCP_SHIFT) | + ((4 & RADEON_TVPVG_MASK) << RADEON_TVPVG_SHIFT) | +@@ -999,14 +1049,23 @@ void RADEONAdjustCrtcRegistersForTV(ScrnInfoPtr pScrn, RADEONSavePtr save, + { + const TVModeConstants *constPtr; + RADEONOutputPrivatePtr radeon_output = output->driver_private; ++ RADEONInfoPtr info = RADEONPTR(pScrn); ++ RADEONPLLPtr pll = &info->pll; + + /* FIXME: need to revisit this when we add more modes */ + if (radeon_output->tvStd == TV_STD_NTSC || + radeon_output->tvStd == TV_STD_NTSC_J || +- radeon_output->tvStd == TV_STD_PAL_M) +- constPtr = &availableTVModes[0]; +- else +- constPtr = &availableTVModes[1]; ++ radeon_output->tvStd == TV_STD_PAL_M) { ++ if (pll->reference_freq == 2700) ++ constPtr = &availableTVModes[0]; ++ else ++ constPtr = &availableTVModes[2]; ++ } else { ++ if (pll->reference_freq == 2700) ++ constPtr = &availableTVModes[1]; ++ else ++ constPtr = &availableTVModes[1]; /* FIXME */ ++ } + + save->crtc_h_total_disp = (((constPtr->horResolution / 8) - 1) << RADEON_CRTC_H_DISP_SHIFT) | + (((constPtr->horTotal / 8) - 1) << RADEON_CRTC_H_TOTAL_SHIFT); +@@ -1030,14 +1089,23 @@ void RADEONAdjustPLLRegistersForTV(ScrnInfoPtr pScrn, RADEONSavePtr save, + unsigned postDiv; + const TVModeConstants *constPtr; + RADEONOutputPrivatePtr radeon_output = output->driver_private; ++ RADEONInfoPtr info = RADEONPTR(pScrn); ++ RADEONPLLPtr pll = &info->pll; + + /* FIXME: need to revisit this when we add more modes */ + if (radeon_output->tvStd == TV_STD_NTSC || + radeon_output->tvStd == TV_STD_NTSC_J || +- radeon_output->tvStd == TV_STD_PAL_M) +- constPtr = &availableTVModes[0]; +- else +- constPtr = &availableTVModes[1]; ++ radeon_output->tvStd == TV_STD_PAL_M) { ++ if (pll->reference_freq == 2700) ++ constPtr = &availableTVModes[0]; ++ else ++ constPtr = &availableTVModes[2]; ++ } else { ++ if (pll->reference_freq == 2700) ++ constPtr = &availableTVModes[1]; ++ else ++ constPtr = &availableTVModes[1]; /* FIXME */ ++ } + + save->htotal_cntl = (constPtr->horTotal & 0x7 /*0xf*/) | RADEON_HTOT_CNTL_VGA_EN; + +@@ -1083,14 +1151,23 @@ void RADEONAdjustCrtc2RegistersForTV(ScrnInfoPtr pScrn, RADEONSavePtr save, + { + const TVModeConstants *constPtr; + RADEONOutputPrivatePtr radeon_output = output->driver_private; ++ RADEONInfoPtr info = RADEONPTR(pScrn); ++ RADEONPLLPtr pll = &info->pll; + + /* FIXME: need to revisit this when we add more modes */ + if (radeon_output->tvStd == TV_STD_NTSC || + radeon_output->tvStd == TV_STD_NTSC_J || +- radeon_output->tvStd == TV_STD_PAL_M) +- constPtr = &availableTVModes[0]; +- else +- constPtr = &availableTVModes[1]; ++ radeon_output->tvStd == TV_STD_PAL_M) { ++ if (pll->reference_freq == 2700) ++ constPtr = &availableTVModes[0]; ++ else ++ constPtr = &availableTVModes[2]; ++ } else { ++ if (pll->reference_freq == 2700) ++ constPtr = &availableTVModes[1]; ++ else ++ constPtr = &availableTVModes[1]; /* FIXME */ ++ } + + save->crtc2_h_total_disp = (((constPtr->horResolution / 8) - 1) << RADEON_CRTC_H_DISP_SHIFT) | + (((constPtr->horTotal / 8) - 1) << RADEON_CRTC_H_TOTAL_SHIFT); +@@ -1114,14 +1191,23 @@ void RADEONAdjustPLL2RegistersForTV(ScrnInfoPtr pScrn, RADEONSavePtr save, + unsigned postDiv; + const TVModeConstants *constPtr; + RADEONOutputPrivatePtr radeon_output = output->driver_private; ++ RADEONInfoPtr info = RADEONPTR(pScrn); ++ RADEONPLLPtr pll = &info->pll; + + /* FIXME: need to revisit this when we add more modes */ + if (radeon_output->tvStd == TV_STD_NTSC || + radeon_output->tvStd == TV_STD_NTSC_J || +- radeon_output->tvStd == TV_STD_PAL_M) +- constPtr = &availableTVModes[0]; +- else +- constPtr = &availableTVModes[1]; ++ radeon_output->tvStd == TV_STD_PAL_M) { ++ if (pll->reference_freq == 2700) ++ constPtr = &availableTVModes[0]; ++ else ++ constPtr = &availableTVModes[2]; ++ } else { ++ if (pll->reference_freq == 2700) ++ constPtr = &availableTVModes[1]; ++ else ++ constPtr = &availableTVModes[1]; /* FIXME */ ++ } + + save->htotal_cntl2 = (constPtr->horTotal & 0x7); /* 0xf */ + +diff --git a/src/radeon_tv.h b/src/radeon_tv.h +index c4b7838..8d77a77 100644 +--- a/src/radeon_tv.h ++++ b/src/radeon_tv.h +@@ -27,24 +27,31 @@ + #define MAX_H_SIZE 5 /* Range: [-5..5], negative is smaller, positive is larger */ + + /* tv standard constants */ +-#define NTSC_TV_PLL_M 22 +-#define NTSC_TV_PLL_N 175 +-#define NTSC_TV_PLL_P 5 + #define NTSC_TV_CLOCK_T 233 + #define NTSC_TV_VFTOTAL 1 + #define NTSC_TV_LINES_PER_FRAME 525 + #define NTSC_TV_ZERO_H_SIZE 479166 + #define NTSC_TV_H_SIZE_UNIT 9478 + +-#define PAL_TV_PLL_M 113 +-#define PAL_TV_PLL_N 668 +-#define PAL_TV_PLL_P 3 + #define PAL_TV_CLOCK_T 188 + #define PAL_TV_VFTOTAL 3 + #define PAL_TV_LINES_PER_FRAME 625 + #define PAL_TV_ZERO_H_SIZE 473200 + #define PAL_TV_H_SIZE_UNIT 9360 + ++/* tv pll setting for 27 mhz ref clk */ ++#define NTSC_TV_PLL_M_27 22 ++#define NTSC_TV_PLL_N_27 175 ++#define NTSC_TV_PLL_P_27 5 ++ ++#define PAL_TV_PLL_M_27 113 ++#define PAL_TV_PLL_N_27 668 ++#define PAL_TV_PLL_P_27 3 ++ ++/* tv pll setting for 14 mhz ref clk */ ++#define NTSC_TV_PLL_M_14 33 ++#define NTSC_TV_PLL_N_14 693 ++#define NTSC_TV_PLL_P_14 7 + + #define VERT_LEAD_IN_LINES 2 + #define FRAC_BITS 0xe +diff --git a/src/radeon_version.h b/src/radeon_version.h +index ccc1367..5717ead 100644 +--- a/src/radeon_version.h ++++ b/src/radeon_version.h +@@ -39,10 +39,9 @@ + #define R200_DRIVER_NAME "r200" + #define R300_DRIVER_NAME "r300" + +-#define RADEON_VERSION_MAJOR 4 +-#define RADEON_VERSION_MAJOR_TILED 5 +-#define RADEON_VERSION_MINOR 3 +-#define RADEON_VERSION_PATCH 0 ++#define RADEON_VERSION_MAJOR PACKAGE_VERSION_MAJOR ++#define RADEON_VERSION_MINOR PACKAGE_VERSION_MINOR ++#define RADEON_VERSION_PATCH PACKAGE_VERSION_PATCHLEVEL + + #ifndef RADEON_VERSION_EXTRA + #define RADEON_VERSION_EXTRA "" diff --git a/radeon-git-upstream-fixes.patch b/radeon-git-upstream-fixes.patch deleted file mode 100644 index 41d689d..0000000 --- a/radeon-git-upstream-fixes.patch +++ /dev/null @@ -1,3472 +0,0 @@ -commit 68888189cf8d460ef6f8f2f1431a6ffe9fcd8134 -Author: Alex Deucher -Date: Wed Feb 27 03:09:28 2008 -0500 - - RADEON: fix textured video uploads - -commit 7cfad216a3f1486be194c972b9b6bcf070358586 -Author: Alex Deucher -Date: Wed Feb 27 02:13:10 2008 -0500 - - RADEON: fix clipping for textured video - -commit a2dca1d68d751def34ef3c6f836574173737bf76 -Author: Alex Deucher -Date: Tue Feb 26 16:38:29 2008 -0500 - - RADEON: Convert textured video to use pipelined uploads - -commit b4fa1ce9d2da04d94521a82d3c2e95f0fe985ccc -Author: Alex Deucher -Date: Tue Feb 26 14:45:25 2008 -0500 - - R300/R500: fix up clipping - - Based on patch from Peter Zubaj. - -commit 44e527a117ab0a363135ff066c7f7e0c12e3dc89 -Author: Alex Deucher -Date: Tue Feb 26 14:33:24 2008 -0500 - - R300: fix cordinate clamping in render code - - Based on Peter's fix for textured video - -commit 00ec17ad53d7ad43f19c9b723794ac1b8ef86826 -Author: Peter Zubaj -Date: Tue Feb 26 14:26:14 2008 -0500 - - R300: Fix clamping and pitch for textured video - -commit 4207793f9b6c891cb17ba715223d2002668885e3 -Author: Alex Deucher -Date: Tue Feb 26 13:16:22 2008 -0500 - - R300/R500: set the number graphics pipes properly - - This should fix the checkerboard issues on r300/r350 cards. - -commit 823d8bf49e4c0a8c839354179942c5a1944c178d -Author: Alex Deucher -Date: Tue Feb 26 12:25:14 2008 -0500 - - R300/R500: clean up magic numbers in textured video - -commit 8ea75b268f11794f4a7e7bac52cb256490ed3fd2 -Author: Dave Airlie -Date: Tue Feb 26 16:29:19 2008 +1000 - - regs: fix spelling properly - -commit f2816064a6c2c4c35ccba74b9aa80547e25c012e -Author: Dave Airlie -Date: Tue Feb 26 16:28:24 2008 +1000 - - regs: fix spelling mistake - - pointed out by plaes on irc - -commit 9d2ca30b90607085578dde1f314db663bd5f82ec -Author: Alex Deucher -Date: Mon Feb 25 17:34:00 2008 -0500 - - R300/R500: clean up magic numbers in render code - -commit 153ad6fcf704cbf9f811d9986cd4baf04e82c9d2 -Author: Dave Airlie -Date: Mon Feb 25 07:10:48 2008 +1000 - - fixup check for EXA composite pointed out by Alan Swanson - -commit 85e470e64f629de72e361c77770e2e29998d1bf4 -Merge: 27ddb39... 1b84c76... -Author: Alex Deucher -Date: Sun Feb 24 05:37:22 2008 -0500 - - Merge master and fix conflicts - - Merge branch 'master' of ssh://agd5f@git.freedesktop.org/git/xorg/driver/xf86-video-ati - - Conflicts: - - src/radeon_commonfuncs.c - -commit 27ddb39b12a0b54e099fd5274c4c91f08e2d2822 -Author: Alex Deucher -Date: Sun Feb 24 05:30:11 2008 -0500 - - R300: clean up magic numbers in RADEONInit3DEngine - -commit d4c20f33ad6a1f88615cd7e09ad3638896873f9e -Author: Alex Deucher -Date: Sun Feb 24 04:46:10 2008 -0500 - - R300: replace magic numbers in cache flush - -commit e52f1c8d2647b81d891ec0728dd582941a76c83f -Author: Alex Deucher -Date: Sun Feb 24 04:43:18 2008 -0500 - - R300: fill in some more 3D bitfields - -commit 1b84c76f27c8d24cb42beae26abf000721901c1c -Author: Dave Airlie -Date: Sun Feb 24 19:20:36 2008 +1100 - - rs690: initial textured video support - -commit 68158124366db883a901e960fe5f05f8df5efa42 -Author: Dave Airlie -Date: Tue Feb 19 19:51:18 2008 +1100 - - rs690: initial rs690 rotate - - suffers same problem as r500 with clipping - -commit e614bb6965588bf09dcb87f5e08e67120ec9847f -Author: Dave Airlie -Date: Sun Feb 24 01:46:05 2008 -0500 - - r500: convert fragprog to use register values - -commit 6ce9ee47c75620b2e5d211c5d59d17271a6a7b19 -Author: Dave Airlie -Date: Sat Feb 23 22:49:34 2008 -0500 - - r500: add textured video Xv adapter support - -commit 9aaf8b33b22b6ba112869558ae54e021b9487ad2 -Author: Dave Airlie -Date: Sat Feb 23 22:16:25 2008 -0500 - - r500: initial rotate support - not fully working yet. - - Just an example of how to setup and run the r500 3D engine for rotation. - this rotates for me but I get some strange clipping on the bottom of my screen - -commit 05dc3e4fc19d056ce99a7b110665adab2ca1ea21 -Author: Adam Jackson -Date: Sat Feb 23 20:29:51 2008 -0500 - - Clarify R500 US setup. - -commit 080606ad528972623e1ed1124d8efe7705a73446 -Author: Adam Jackson -Date: Sat Feb 23 20:21:17 2008 -0500 - - Add the R500 US index/data pair. - -commit edfb3b6bbf0ee17ace8e6ba704a6f54e249fec63 -Author: Alex Deucher -Date: Sat Feb 23 19:59:33 2008 -0500 - - RADEON: no textured video yet on XPRESS chips - - Still need to sort out the VAP and PVS stuff - -commit 4146bfe5d00e40a86d17826fac50d04b2469621d -Author: Alex Deucher -Date: Sat Feb 23 19:21:52 2008 -0500 - - R500: fix typo in new r5xx regs - -commit d9be9f34b0d3313e7b22b2a8bb0a8924ad3116bf -Author: Alex Deucher -Date: Sat Feb 23 19:06:30 2008 -0500 - - RADEON: add textured video support for r1xx-r4xx radeons - - Based on the kdrive ati video code by Eric Anholt. - R3xx/R4xx still have some clipping issues in certain situations - -commit 9dc4acad79196e9d5d94dd710773bfa83456d47f -Author: Alex Deucher -Date: Sat Feb 23 18:29:00 2008 -0500 - - RS6xx: gpio entry for DDIA varies depending on the number of DFP ports - -commit ed0a93edf28155308e7ab9d8705581bb38455ea0 -Author: Adam Jackson -Date: Sat Feb 23 15:02:17 2008 -0500 - - Fix R500_US_CONFIG. - -commit bc2bd6f841b51aeed3b6b4a47dbe758c200bc5a6 -Author: Adam Jackson -Date: Sat Feb 23 14:34:18 2008 -0500 - - Add R500 unified shader register block. - -commit a7b5c3bb74fc4de5e38a75ac31656445ce823464 -Author: Alex Deucher -Date: Fri Feb 22 19:35:11 2008 -0500 - - RS6xx: fix DDC on DDIA output (usually HDMI port) - -commit 3327a681e21101cc6f6e162f4e29f9937b69ccc3 -Author: Alex Deucher -Date: Fri Feb 22 17:05:56 2008 -0500 - - ATOM: properly set up DDIA output on RS6xx boards - -commit 1d0e9ab8b9451101b1b91943546f6c5833c21b3f -Author: Michel Dänzer -Date: Wed Feb 20 10:21:49 2008 +0100 - - radeon: Fix typo flagged by gcc -Wall. - -commit b5bd442b60dbc72fe4c1e928ab864aeb0fd7a3cb -Author: Alex Deucher -Date: Tue Feb 19 20:47:40 2008 -0500 - - R100: fix render accel for transforms - - Not sure why we had a separate broken path for r100 vertex - submission. - -commit a0a73208a21546ac120fb9a463261836c9ea7b55 -Author: Alex Deucher -Date: Tue Feb 19 20:11:19 2008 -0500 - - RADEON: restore clock gating and CP clock errata on VT switch - - This may help people with hangs on resume - -commit b77e2aff7453a9f370beba37ca3c25b92b3f97ff -Author: Alex Deucher -Date: Tue Feb 19 19:55:41 2008 -0500 - - RADEON: fix DDC types 5 and 6 - -commit af82172a82f2bdf96e571def659a1c70f92dfdbf -Author: Alex Deucher -Date: Tue Feb 19 19:39:35 2008 -0500 - - RADEON: update man page with supported chips -diff --git a/man/radeon.man b/man/radeon.man -index b4ade32..86be965 100644 ---- a/man/radeon.man -+++ b/man/radeon.man -@@ -53,7 +53,7 @@ Radeon 9100 IGP - Radeon 9200 IGP - .TP 12 - .B RS400 --Radeon XPRESS 200/200M IGP (2d only) -+Radeon XPRESS 200/200M IGP - .TP 12 - .B RV280 - Radeon 9200PRO/9200/9200SE, M9+ -@@ -90,6 +90,30 @@ Radeon X800, M28 PCIE - .TP 12 - .B R480/R481 - Radeon X850 PCIE/AGP -+.TP 12 -+.B RV515 -+Radeon X1300/X1400/X1500 -+.TP 12 -+.B R520 -+Radeon X1800 -+.TP 12 -+.B RV530/RV560 -+Radeon X1600/X1650/X1700 -+.TP 12 -+.B RV570/R580 -+Radeon X1900/X1950 -+.TP 12 -+.B RS600/RS690 -+Radeon X1200 -+.TP 12 -+.B R600 -+Radeon HD 2900 -+.TP 12 -+.B RV610/RV630 -+Radeon HD 2400/2600 -+.TP 12 -+.B RV670 -+Radeon HD 3850/3870 - - .SH CONFIGURATION DETAILS - Please refer to __xconfigfile__(__filemansuffix__) for general configuration -diff --git a/src/Makefile.am b/src/Makefile.am -index a146df3..e0799a5 100644 ---- a/src/Makefile.am -+++ b/src/Makefile.am -@@ -114,6 +114,7 @@ radeon_drv_la_SOURCES = \ - radeon_driver.c radeon_video.c radeon_bios.c radeon_mm_i2c.c \ - radeon_vip.c radeon_misc.c radeon_probe.c \ - legacy_crtc.c legacy_output.c \ -+ radeon_textured_video.c \ - radeon_crtc.c radeon_output.c radeon_modes.c radeon_tv.c \ - $(RADEON_ATOMBIOS_SOURCES) radeon_atombios.c radeon_atomwrapper.c \ - $(RADEON_DRI_SRCS) $(RADEON_EXA_SOURCES) atombios_output.c atombios_crtc.c -diff --git a/src/atombios_output.c b/src/atombios_output.c -index 6c638b1..07d212f 100644 ---- a/src/atombios_output.c -+++ b/src/atombios_output.c -@@ -235,6 +235,35 @@ atombios_external_tmds_setup(xf86OutputPtr output, DisplayModePtr mode) - } - - static int -+atombios_ddia_setup(xf86OutputPtr output, DisplayModePtr mode) -+{ -+ RADEONInfoPtr info = RADEONPTR(output->scrn); -+ DVO_ENCODER_CONTROL_PS_ALLOCATION disp_data; -+ AtomBiosArgRec data; -+ unsigned char *space; -+ -+ disp_data.sDVOEncoder.ucAction = ATOM_ENABLE; -+ disp_data.sDVOEncoder.usPixelClock = mode->Clock / 10; -+ -+ if (mode->Clock > 165000) -+ disp_data.sDVOEncoder.usDevAttr.sDigAttrib.ucAttribute = PANEL_ENCODER_MISC_DUAL; -+ else -+ disp_data.sDVOEncoder.usDevAttr.sDigAttrib.ucAttribute = 0; -+ -+ data.exec.index = GetIndexIntoMasterTable(COMMAND, DVOEncoderControl); -+ data.exec.dataSpace = (void *)&space; -+ data.exec.pspace = &disp_data; -+ -+ if (RHDAtomBiosFunc(info->atomBIOS->scrnIndex, info->atomBIOS, ATOMBIOS_EXEC, &data) == ATOM_SUCCESS) { -+ ErrorF("DDIA setup success\n"); -+ return ATOM_SUCCESS; -+ } -+ -+ ErrorF("DDIA setup failed\n"); -+ return ATOM_NOT_IMPLEMENTED; -+} -+ -+static int - atombios_output_tmds1_setup(xf86OutputPtr output, DisplayModePtr mode) - { - RADEONInfoPtr info = RADEONPTR(output->scrn); -@@ -536,6 +565,7 @@ atombios_output_mode_set(xf86OutputPtr output, - DisplayModePtr adjusted_mode) - { - RADEONOutputPrivatePtr radeon_output = output->driver_private; -+ RADEONInfoPtr info = RADEONPTR(output->scrn); - - atombios_output_scaler_setup(output, mode); - atombios_set_output_crtc_source(output); -@@ -551,9 +581,12 @@ atombios_output_mode_set(xf86OutputPtr output, - } else if (radeon_output->MonType == MT_DFP) { - if (radeon_output->devices & ATOM_DEVICE_DFP1_SUPPORT) - atombios_output_tmds1_setup(output, adjusted_mode); -- else if (radeon_output->devices & ATOM_DEVICE_DFP2_SUPPORT) -- atombios_external_tmds_setup(output, adjusted_mode); -- else if (radeon_output->devices & ATOM_DEVICE_DFP3_SUPPORT) -+ else if (radeon_output->devices & ATOM_DEVICE_DFP2_SUPPORT) { -+ if (info->IsIGP) -+ atombios_ddia_setup(output, adjusted_mode); -+ else -+ atombios_external_tmds_setup(output, adjusted_mode); -+ } else if (radeon_output->devices & ATOM_DEVICE_DFP3_SUPPORT) - atombios_output_tmds2_setup(output, adjusted_mode); - } else if (radeon_output->MonType == MT_LCD) { - if (radeon_output->devices & ATOM_DEVICE_LCD1_SUPPORT) -diff --git a/src/radeon.h b/src/radeon.h -index 7d63f28..aba3c0f 100644 ---- a/src/radeon.h -+++ b/src/radeon.h -@@ -184,6 +184,8 @@ typedef enum { - * for something else. - */ - -+#define xFixedToFloat(f) (((float) (f)) / 65536) -+ - #define RADEON_LOGLEVEL_DEBUG 4 - - /* for Xv, outputs */ -diff --git a/src/radeon_atombios.c b/src/radeon_atombios.c -index ddd332f..88c220b 100644 ---- a/src/radeon_atombios.c -+++ b/src/radeon_atombios.c -@@ -1759,7 +1759,15 @@ RADEONGetATOMConnectorInfoFromBIOSConnectorTable (ScrnInfoPtr pScrn) - (i == ATOM_DEVICE_TV2_INDEX) || - (i == ATOM_DEVICE_CV_INDEX)) - info->BiosConnector[i].ddc_i2c.valid = FALSE; -- else -+ else if ((i == ATOM_DEVICE_DFP3_INDEX) && info->IsIGP) { -+ /* DDIA port uses non-standard gpio entry */ -+ if (info->BiosConnector[ATOM_DEVICE_DFP2_INDEX].valid) -+ info->BiosConnector[i].ddc_i2c = -+ RADEONLookupGPIOLineForDDC(pScrn, ci.sucI2cId.sbfAccess.bfI2C_LineMux + 2); -+ else -+ info->BiosConnector[i].ddc_i2c = -+ RADEONLookupGPIOLineForDDC(pScrn, ci.sucI2cId.sbfAccess.bfI2C_LineMux + 1); -+ } else - info->BiosConnector[i].ddc_i2c = - RADEONLookupGPIOLineForDDC(pScrn, ci.sucI2cId.sbfAccess.bfI2C_LineMux); - -@@ -1772,7 +1780,7 @@ RADEONGetATOMConnectorInfoFromBIOSConnectorTable (ScrnInfoPtr pScrn) - info->BiosConnector[i].TMDSType = TMDS_EXT; - } else if (i == ATOM_DEVICE_DFP3_INDEX) { - if (info->IsIGP) -- info->BiosConnector[i].TMDSType = TMDS_EXT; -+ info->BiosConnector[i].TMDSType = TMDS_DDIA; - else - info->BiosConnector[i].TMDSType = TMDS_LVTMA; - } else -diff --git a/src/radeon_commonfuncs.c b/src/radeon_commonfuncs.c -index 8c4b598..0250aef 100644 ---- a/src/radeon_commonfuncs.c -+++ b/src/radeon_commonfuncs.c -@@ -30,6 +30,8 @@ - #include "config.h" - #endif - -+#include "ati_pciids_gen.h" -+ - #if defined(ACCEL_MMIO) && defined(ACCEL_CP) - #error Cannot define both MMIO and CP acceleration! - #endif -@@ -53,142 +55,182 @@ - static void FUNC_NAME(RADEONInit3DEngine)(ScrnInfoPtr pScrn) - { - RADEONInfoPtr info = RADEONPTR(pScrn); -+ CARD32 gb_tile_config; - ACCEL_PREAMBLE(); - - info->texW[0] = info->texH[0] = info->texW[1] = info->texH[1] = 1; - -- if (IS_R300_VARIANT) { -+ if (IS_R300_VARIANT || IS_AVIVO_VARIANT || info->ChipFamily == CHIP_FAMILY_RS690) { -+ - BEGIN_ACCEL(3); -- OUT_ACCEL_REG(R300_RB3D_DSTCACHE_CTLSTAT, 0xA); -- OUT_ACCEL_REG(R300_RB3D_ZCACHE_CTLSTAT, 0x3); -- OUT_ACCEL_REG(R300_WAIT_UNTIL, 0x30000); -+ OUT_ACCEL_REG(R300_RB3D_DSTCACHE_CTLSTAT, R300_DC_FLUSH_3D | R300_DC_FREE_3D); -+ OUT_ACCEL_REG(R300_RB3D_ZCACHE_CTLSTAT, R300_ZC_FLUSH | R300_ZC_FREE); -+ OUT_ACCEL_REG(R300_WAIT_UNTIL, R300_WAIT_2D_IDLECLEAN | R300_WAIT_3D_IDLECLEAN); - FINISH_ACCEL(); - -+ gb_tile_config = (R300_ENABLE_TILING | R300_TILE_SIZE_16 | R300_SUBPIXEL_1_16); -+ -+ if ((info->Chipset == PCI_CHIP_RV410_5E4C) || -+ (info->Chipset == PCI_CHIP_RV410_5E4F)) { -+ /* RV410 SE chips */ -+ gb_tile_config |= R300_PIPE_COUNT_RV350; -+ } else if ((info->ChipFamily == CHIP_FAMILY_RV350) || -+ (info->ChipFamily == CHIP_FAMILY_RV380) || -+ (info->ChipFamily == CHIP_FAMILY_RS400)) { -+ /* RV3xx, RS4xx chips */ -+ gb_tile_config |= R300_PIPE_COUNT_RV350; -+ } else if ((info->ChipFamily == CHIP_FAMILY_R300) || -+ (info->ChipFamily == CHIP_FAMILY_R350)) { -+ /* R3xx chips */ -+ gb_tile_config |= R300_PIPE_COUNT_R300; -+ } else if ((info->ChipFamily == CHIP_FAMILY_RV410) || -+ (info->ChipFamily == CHIP_FAMILY_RS690)) { -+ /* RV4xx, RS6xx chips */ -+ gb_tile_config |= R300_PIPE_COUNT_R420_3P; -+ } else { -+ /* R4xx, R5xx chips */ -+ gb_tile_config |= R300_PIPE_COUNT_R420; -+ } -+ - BEGIN_ACCEL(3); -- OUT_ACCEL_REG(R300_GB_TILE_CONFIG, 0x10011); -- OUT_ACCEL_REG(R300_GB_SELECT,0x0); -- OUT_ACCEL_REG(R300_GB_ENABLE, 0x0); -+ OUT_ACCEL_REG(R300_GB_TILE_CONFIG, gb_tile_config); -+ OUT_ACCEL_REG(R300_GB_SELECT, 0); -+ OUT_ACCEL_REG(R300_GB_ENABLE, 0); - FINISH_ACCEL(); - - BEGIN_ACCEL(3); -- OUT_ACCEL_REG(R300_RB3D_DSTCACHE_CTLSTAT, 0xA); -- OUT_ACCEL_REG(R300_RB3D_ZCACHE_CTLSTAT, 0x3); -- OUT_ACCEL_REG(R300_WAIT_UNTIL, 0x30000); -+ OUT_ACCEL_REG(R300_RB3D_DSTCACHE_CTLSTAT, R300_DC_FLUSH_3D | R300_DC_FREE_3D); -+ OUT_ACCEL_REG(R300_RB3D_ZCACHE_CTLSTAT, R300_ZC_FLUSH | R300_ZC_FREE); -+ OUT_ACCEL_REG(R300_WAIT_UNTIL, R300_WAIT_2D_IDLECLEAN | R300_WAIT_3D_IDLECLEAN); - FINISH_ACCEL(); - - BEGIN_ACCEL(5); -- OUT_ACCEL_REG(R300_GB_AA_CONFIG, 0x0); -- OUT_ACCEL_REG(R300_RB3D_DSTCACHE_CTLSTAT, 0xA); -- OUT_ACCEL_REG(R300_RB3D_ZCACHE_CTLSTAT, 0x3); -- OUT_ACCEL_REG(R300_GB_MSPOS0, 0x78888888); -- OUT_ACCEL_REG(R300_GB_MSPOS1, 0x08888888); -+ OUT_ACCEL_REG(R300_GB_AA_CONFIG, 0); -+ OUT_ACCEL_REG(R300_RB3D_DSTCACHE_CTLSTAT, R300_DC_FLUSH_3D | R300_DC_FREE_3D); -+ OUT_ACCEL_REG(R300_RB3D_ZCACHE_CTLSTAT, R300_ZC_FLUSH | R300_ZC_FREE); -+ OUT_ACCEL_REG(R300_GB_MSPOS0, ((8 << R300_MS_X0_SHIFT) | -+ (8 << R300_MS_Y0_SHIFT) | -+ (8 << R300_MS_X1_SHIFT) | -+ (8 << R300_MS_Y1_SHIFT) | -+ (8 << R300_MS_X2_SHIFT) | -+ (8 << R300_MS_Y2_SHIFT) | -+ (8 << R300_MSBD0_Y_SHIFT) | -+ (7 << R300_MSBD0_X_SHIFT))); -+ OUT_ACCEL_REG(R300_GB_MSPOS1, ((8 << R300_MS_X3_SHIFT) | -+ (8 << R300_MS_Y3_SHIFT) | -+ (8 << R300_MS_X4_SHIFT) | -+ (8 << R300_MS_Y4_SHIFT) | -+ (8 << R300_MS_X5_SHIFT) | -+ (8 << R300_MS_Y5_SHIFT) | -+ (8 << R300_MSBD1_SHIFT))); - FINISH_ACCEL(); - - BEGIN_ACCEL(4); -- OUT_ACCEL_REG(R300_GA_POLY_MODE, 0x120); -- OUT_ACCEL_REG(R300_GA_ROUND_MODE, 0x5); -- OUT_ACCEL_REG(R300_GA_COLOR_CONTROL, 0xAAAA); -- OUT_ACCEL_REG(R300_GA_OFFSET, 0x0); -- FINISH_ACCEL(); -- -- BEGIN_ACCEL(26); -- OUT_ACCEL_REG(R300_VAP_CNTL_STATUS, 0x0); -- OUT_ACCEL_REG(R300_VAP_PVS_STATE_FLUSH_REG, 0x0); -- OUT_ACCEL_REG(R300_VAP_CNTL, 0x300456); -- OUT_ACCEL_REG(R300_VAP_VTE_CNTL, 0x300); -- OUT_ACCEL_REG(R300_VAP_PSC_SGN_NORM_CNTL, 0x0); -- OUT_ACCEL_REG(R300_VAP_PROG_STREAM_CNTL_0, 0x4a014001); -- OUT_ACCEL_REG(R300_VAP_PROG_STREAM_CNTL_1, 0x6b01); -- OUT_ACCEL_REG(R300_VAP_PROG_STREAM_CNTL_EXT_0, 0xf688f688); -- OUT_ACCEL_REG(R300_VAP_PROG_STREAM_CNTL_EXT_1, 0xf688); -- OUT_ACCEL_REG(R300_VAP_PVS_CODE_CNTL_0, 0x100400); -- OUT_ACCEL_REG(R300_VAP_PVS_CODE_CNTL_1, 0x1); -- OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_INDX_REG, 0); -- OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_DATA_REG,0x00f00203); -- OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_DATA_REG,0x00d10001); -- OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_DATA_REG,0x01248001); -- OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_DATA_REG,0x01248001); -- OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_DATA_REG,0x00f02203); -- OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_DATA_REG,0x00d10141); -- OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_DATA_REG,0x01248141); -- OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_DATA_REG,0x01248141); -- -- OUT_ACCEL_REG(R300_VAP_PVS_FLOW_CNTL_OPC, 0x0); -- OUT_ACCEL_REG(R300_VAP_OUT_VTX_FMT_0, 0x1); -- OUT_ACCEL_REG(R300_VAP_OUT_VTX_FMT_1, (0x2 << 3) | 0x2); -- -- OUT_ACCEL_REG(R300_VAP_GB_VERT_CLIP_ADJ, 0x3f800000); -- OUT_ACCEL_REG(R300_VAP_GB_VERT_DISC_ADJ, 0x3f800000); -- OUT_ACCEL_REG(R300_VAP_GB_HORZ_CLIP_ADJ, 0x3f800000); -- OUT_ACCEL_REG(R300_VAP_GB_HORZ_DISC_ADJ, 0x3f800000); -- OUT_ACCEL_REG(R300_VAP_CLIP_CNTL, 0x10000); -+ OUT_ACCEL_REG(R300_GA_POLY_MODE, R300_FRONT_PTYPE_TRIANGE | R300_BACK_PTYPE_TRIANGE); -+ OUT_ACCEL_REG(R300_GA_ROUND_MODE, (R300_GEOMETRY_ROUND_NEAREST | -+ R300_COLOR_ROUND_NEAREST)); -+ OUT_ACCEL_REG(R300_GA_COLOR_CONTROL, (R300_RGB0_SHADING_GOURAUD | -+ R300_ALPHA0_SHADING_GOURAUD | -+ R300_RGB1_SHADING_GOURAUD | -+ R300_ALPHA1_SHADING_GOURAUD | -+ R300_RGB2_SHADING_GOURAUD | -+ R300_ALPHA2_SHADING_GOURAUD | -+ R300_RGB3_SHADING_GOURAUD | -+ R300_ALPHA3_SHADING_GOURAUD)); -+ OUT_ACCEL_REG(R300_GA_OFFSET, 0); - FINISH_ACCEL(); - -- BEGIN_ACCEL(7); -- OUT_ACCEL_REG(R300_SU_TEX_WRAP, 0x0); -- OUT_ACCEL_REG(R300_SU_POLY_OFFSET_ENABLE, 0x0); -- OUT_ACCEL_REG(R300_SU_CULL_MODE, 0x4); -+ BEGIN_ACCEL(5); -+ OUT_ACCEL_REG(R300_SU_TEX_WRAP, 0); -+ OUT_ACCEL_REG(R300_SU_POLY_OFFSET_ENABLE, 0); -+ OUT_ACCEL_REG(R300_SU_CULL_MODE, R300_FACE_NEG); - OUT_ACCEL_REG(R300_SU_DEPTH_SCALE, 0x4b7fffff); -- OUT_ACCEL_REG(R300_SU_DEPTH_OFFSET, 0x0); -- OUT_ACCEL_REG(R300_RS_COUNT, 0x40002); -- OUT_ACCEL_REG(R300_RS_IP_0, 0x1610000); -+ OUT_ACCEL_REG(R300_SU_DEPTH_OFFSET, 0); - FINISH_ACCEL(); - - BEGIN_ACCEL(5); -- OUT_ACCEL_REG(R300_US_W_FMT, 0x0); -- OUT_ACCEL_REG(R300_US_OUT_FMT_1, 0x1B0F); -- OUT_ACCEL_REG(R300_US_OUT_FMT_2, 0x1B0F); -- OUT_ACCEL_REG(R300_US_OUT_FMT_3, 0x1B0F); -- OUT_ACCEL_REG(R300_US_OUT_FMT_0, 0x1B01); -+ OUT_ACCEL_REG(R300_US_W_FMT, 0); -+ OUT_ACCEL_REG(R300_US_OUT_FMT_1, (R300_OUT_FMT_UNUSED | -+ R300_OUT_FMT_C0_SEL_BLUE | -+ R300_OUT_FMT_C1_SEL_GREEN | -+ R300_OUT_FMT_C2_SEL_RED | -+ R300_OUT_FMT_C3_SEL_ALPHA)); -+ OUT_ACCEL_REG(R300_US_OUT_FMT_2, (R300_OUT_FMT_UNUSED | -+ R300_OUT_FMT_C0_SEL_BLUE | -+ R300_OUT_FMT_C1_SEL_GREEN | -+ R300_OUT_FMT_C2_SEL_RED | -+ R300_OUT_FMT_C3_SEL_ALPHA)); -+ OUT_ACCEL_REG(R300_US_OUT_FMT_3, (R300_OUT_FMT_UNUSED | -+ R300_OUT_FMT_C0_SEL_BLUE | -+ R300_OUT_FMT_C1_SEL_GREEN | -+ R300_OUT_FMT_C2_SEL_RED | -+ R300_OUT_FMT_C3_SEL_ALPHA)); -+ OUT_ACCEL_REG(R300_US_OUT_FMT_0, (R300_OUT_FMT_C4_10 | -+ R300_OUT_FMT_C0_SEL_BLUE | -+ R300_OUT_FMT_C1_SEL_GREEN | -+ R300_OUT_FMT_C2_SEL_RED | -+ R300_OUT_FMT_C3_SEL_ALPHA)); - FINISH_ACCEL(); - -- BEGIN_ACCEL(2); -- OUT_ACCEL_REG(R300_RS_INST_COUNT, 0xC0); -- OUT_ACCEL_REG(R300_RS_INST_0, 0x8); -- FINISH_ACCEL(); - - BEGIN_ACCEL(3); -- OUT_ACCEL_REG(R300_FG_DEPTH_SRC, 0x0); -- OUT_ACCEL_REG(R300_FG_FOG_BLEND, 0x0); -- OUT_ACCEL_REG(R300_FG_ALPHA_FUNC, 0x0); -+ OUT_ACCEL_REG(R300_FG_DEPTH_SRC, 0); -+ OUT_ACCEL_REG(R300_FG_FOG_BLEND, 0); -+ OUT_ACCEL_REG(R300_FG_ALPHA_FUNC, 0); - FINISH_ACCEL(); - - BEGIN_ACCEL(12); -- OUT_ACCEL_REG(R300_RB3D_ZSTENCILCNTL, 0x0); -- OUT_ACCEL_REG(R300_RB3D_ZCACHE_CTLSTAT, 0x3); -- OUT_ACCEL_REG(R300_RB3D_BW_CNTL, 0x0); -- OUT_ACCEL_REG(R300_RB3D_ZCNTL, 0x0); -- OUT_ACCEL_REG(R300_RB3D_ZTOP, 0x0); -- OUT_ACCEL_REG(R300_RB3D_ROPCNTL, 0x0); -- -- OUT_ACCEL_REG(R300_RB3D_AARESOLVE_CTL, 0x0); -- OUT_ACCEL_REG(R300_RB3D_COLOR_CHANNEL_MASK, 0xf); -- OUT_ACCEL_REG(R300_RB3D_DSTCACHE_CTLSTAT, 0xA); -- OUT_ACCEL_REG(R300_RB3D_CCTL, 0x0); -- OUT_ACCEL_REG(R300_RB3D_DITHER_CTL, 0x0); -- OUT_ACCEL_REG(R300_RB3D_DSTCACHE_CTLSTAT, 0xA); -+ OUT_ACCEL_REG(R300_RB3D_ZSTENCILCNTL, 0); -+ OUT_ACCEL_REG(R300_RB3D_ZCACHE_CTLSTAT, R300_ZC_FLUSH | R300_ZC_FREE); -+ OUT_ACCEL_REG(R300_RB3D_BW_CNTL, 0); -+ OUT_ACCEL_REG(R300_RB3D_ZCNTL, 0); -+ OUT_ACCEL_REG(R300_RB3D_ZTOP, 0); -+ OUT_ACCEL_REG(R300_RB3D_ROPCNTL, 0); -+ -+ OUT_ACCEL_REG(R300_RB3D_AARESOLVE_CTL, 0); -+ OUT_ACCEL_REG(R300_RB3D_COLOR_CHANNEL_MASK, (R300_BLUE_MASK_EN | -+ R300_GREEN_MASK_EN | -+ R300_RED_MASK_EN | -+ R300_ALPHA_MASK_EN)); -+ OUT_ACCEL_REG(R300_RB3D_DSTCACHE_CTLSTAT, R300_DC_FLUSH_3D | R300_DC_FREE_3D); -+ OUT_ACCEL_REG(R300_RB3D_CCTL, 0); -+ OUT_ACCEL_REG(R300_RB3D_DITHER_CTL, 0); -+ OUT_ACCEL_REG(R300_RB3D_DSTCACHE_CTLSTAT, R300_DC_FLUSH_3D | R300_DC_FREE_3D); - FINISH_ACCEL(); - - BEGIN_ACCEL(7); - OUT_ACCEL_REG(R300_SC_EDGERULE, 0xA5294A5); -- OUT_ACCEL_REG(R300_SC_SCISSOR0, 0x0); -- OUT_ACCEL_REG(R300_SC_SCISSOR1, 0x3ffffff); -- OUT_ACCEL_REG(R300_SC_CLIP_0_A, 0x880440); -- OUT_ACCEL_REG(R300_SC_CLIP_0_B, 0xff0ff0); -+ OUT_ACCEL_REG(R300_SC_SCISSOR0, ((0 << R300_SCISSOR_X_SHIFT) | -+ (0 << R300_SCISSOR_Y_SHIFT))); -+ OUT_ACCEL_REG(R300_SC_SCISSOR1, ((8191 << R300_SCISSOR_X_SHIFT) | -+ (8191 << R300_SCISSOR_Y_SHIFT))); -+ -+ if (IS_R300_VARIANT || (info->ChipFamily == CHIP_FAMILY_RS690)) { -+ /* clip has offset 1440 */ -+ OUT_ACCEL_REG(R300_SC_CLIP_0_A, ((1088 << R300_CLIP_X_SHIFT) | -+ (1088 << R300_CLIP_Y_SHIFT))); -+ OUT_ACCEL_REG(R300_SC_CLIP_0_B, (((1080 + 2048) << R300_CLIP_X_SHIFT) | -+ ((1080 + 2048) << R300_CLIP_Y_SHIFT))); -+ } else { -+ OUT_ACCEL_REG(R300_SC_CLIP_0_A, ((0 << R300_CLIP_X_SHIFT) | -+ (0 << R300_CLIP_Y_SHIFT))); -+ OUT_ACCEL_REG(R300_SC_CLIP_0_B, ((4080 << R300_CLIP_X_SHIFT) | -+ (4080 << R300_CLIP_Y_SHIFT))); -+ } - OUT_ACCEL_REG(R300_SC_CLIP_RULE, 0xAAAA); - OUT_ACCEL_REG(R300_SC_SCREENDOOR, 0xffffff); - FINISH_ACCEL(); -- } else if ((info->ChipFamily == CHIP_FAMILY_RV250) || -- (info->ChipFamily == CHIP_FAMILY_RV280) || -- (info->ChipFamily == CHIP_FAMILY_RS300) || -+ } else if ((info->ChipFamily == CHIP_FAMILY_RV250) || -+ (info->ChipFamily == CHIP_FAMILY_RV280) || -+ (info->ChipFamily == CHIP_FAMILY_RS300) || - (info->ChipFamily == CHIP_FAMILY_R200)) { - - BEGIN_ACCEL(7); -- if (info->ChipFamily == CHIP_FAMILY_RS300) { -- OUT_ACCEL_REG(R200_SE_VAP_CNTL_STATUS, RADEON_TCL_BYPASS); -- } else { -- OUT_ACCEL_REG(R200_SE_VAP_CNTL_STATUS, 0); -- } -+ if (info->ChipFamily == CHIP_FAMILY_RS300) { -+ OUT_ACCEL_REG(R200_SE_VAP_CNTL_STATUS, RADEON_TCL_BYPASS); -+ } else { -+ OUT_ACCEL_REG(R200_SE_VAP_CNTL_STATUS, 0); -+ } - OUT_ACCEL_REG(R200_PP_CNTL_X, 0); - OUT_ACCEL_REG(R200_PP_TXMULTI_CTL_0, 0); - OUT_ACCEL_REG(R200_SE_VTX_STATE_CNTL, 0); -@@ -199,11 +241,11 @@ static void FUNC_NAME(RADEONInit3DEngine)(ScrnInfoPtr pScrn) - FINISH_ACCEL(); - } else { - BEGIN_ACCEL(2); -- if ((info->ChipFamily == CHIP_FAMILY_RADEON) || -- (info->ChipFamily == CHIP_FAMILY_RV200)) -- OUT_ACCEL_REG(RADEON_SE_CNTL_STATUS, 0); -- else -- OUT_ACCEL_REG(RADEON_SE_CNTL_STATUS, RADEON_TCL_BYPASS); -+ if ((info->ChipFamily == CHIP_FAMILY_RADEON) || -+ (info->ChipFamily == CHIP_FAMILY_RV200)) -+ OUT_ACCEL_REG(RADEON_SE_CNTL_STATUS, 0); -+ else -+ OUT_ACCEL_REG(RADEON_SE_CNTL_STATUS, RADEON_TCL_BYPASS); - OUT_ACCEL_REG(RADEON_SE_COORD_FMT, - RADEON_VTX_XY_PRE_MULT_1_OVER_W0 | - RADEON_VTX_ST0_NONPARAMETRIC | -@@ -217,12 +259,12 @@ static void FUNC_NAME(RADEONInit3DEngine)(ScrnInfoPtr pScrn) - OUT_ACCEL_REG(RADEON_RE_WIDTH_HEIGHT, 0x07ff07ff); - OUT_ACCEL_REG(RADEON_AUX_SC_CNTL, 0); - OUT_ACCEL_REG(RADEON_RB3D_PLANEMASK, 0xffffffff); -- OUT_ACCEL_REG(RADEON_SE_CNTL, RADEON_DIFFUSE_SHADE_GOURAUD | -- RADEON_BFACE_SOLID | -- RADEON_FFACE_SOLID | -- RADEON_VTX_PIX_CENTER_OGL | -- RADEON_ROUND_MODE_ROUND | -- RADEON_ROUND_PREC_4TH_PIX); -+ OUT_ACCEL_REG(RADEON_SE_CNTL, (RADEON_DIFFUSE_SHADE_GOURAUD | -+ RADEON_BFACE_SOLID | -+ RADEON_FFACE_SOLID | -+ RADEON_VTX_PIX_CENTER_OGL | -+ RADEON_ROUND_MODE_ROUND | -+ RADEON_ROUND_PREC_4TH_PIX)); - FINISH_ACCEL(); - } - -diff --git a/src/radeon_driver.c b/src/radeon_driver.c -index 9c5fce6..5cf8d51 100644 ---- a/src/radeon_driver.c -+++ b/src/radeon_driver.c -@@ -3485,7 +3485,7 @@ Bool RADEONScreenInit(int scrnIndex, ScreenPtr pScreen, - RADEONDGAInit(pScreen); - - /* Init Xv */ -- if (!IS_AVIVO_VARIANT) { -+ if (info->ChipFamily < CHIP_FAMILY_R600) { - xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG, - "Initializing Xv\n"); - RADEONInitVideo(pScreen); -@@ -4906,6 +4906,17 @@ Bool RADEONEnterVT(int scrnIndex, int flags) - /* Makes sure the engine is idle before doing anything */ - RADEONWaitForIdleMMIO(pScrn); - -+ if (info->IsMobility && !IS_AVIVO_VARIANT) { -+ if (xf86ReturnOptValBool(info->Options, OPTION_DYNAMIC_CLOCKS, FALSE)) { -+ RADEONSetDynamicClock(pScrn, 1); -+ } else { -+ RADEONSetDynamicClock(pScrn, 0); -+ } -+ } -+ -+ if (IS_R300_VARIANT || IS_RV100_VARIANT) -+ RADEONForceSomeClocks(pScrn); -+ - pScrn->vtSema = TRUE; - for (i = 0; i < xf86_config->num_crtc; i++) { - xf86CrtcPtr crtc = xf86_config->crtc[i]; -diff --git a/src/radeon_exa.c b/src/radeon_exa.c -index 3b0c734..4da4841 100644 ---- a/src/radeon_exa.c -+++ b/src/radeon_exa.c -@@ -105,23 +105,6 @@ RADEONLog2(int val) - return bits - 1; - } - --static __inline__ int --RADEONPow2(int num) --{ -- int pot = 2; -- -- if (num <= 2) -- return num; -- -- while (pot < num) { -- pot *= 2; -- } -- -- return pot; --} -- -- -- - static __inline__ CARD32 F_TO_DW(float val) - { - union { -diff --git a/src/radeon_exa_funcs.c b/src/radeon_exa_funcs.c -index 20b96a5..10221c0 100644 ---- a/src/radeon_exa_funcs.c -+++ b/src/radeon_exa_funcs.c -@@ -533,11 +533,11 @@ Bool FUNC_NAME(RADEONDrawInit)(ScreenPtr pScreen) - - #ifdef RENDER - if (info->RenderAccel) { -- if ((info->ChipFamily >= CHIP_FAMILY_RV515) || -+ if ((info->ChipFamily >= CHIP_FAMILY_R600) || - (info->ChipFamily == CHIP_FAMILY_RS400)) - xf86DrvMsg(pScrn->scrnIndex, X_INFO, "Render acceleration " - "unsupported on XPRESS, R500 and newer cards.\n"); -- else if (IS_R300_VARIANT) { -+ else if (IS_R300_VARIANT || (IS_AVIVO_VARIANT && info->ChipFamily <= CHIP_FAMILY_RS690)) { - xf86DrvMsg(pScrn->scrnIndex, X_INFO, "Render acceleration " - "enabled for R300 type cards.\n"); - info->exa->CheckComposite = R300CheckComposite; -diff --git a/src/radeon_exa_render.c b/src/radeon_exa_render.c -index 6003587..9bbccb5 100644 ---- a/src/radeon_exa_render.c -+++ b/src/radeon_exa_render.c -@@ -809,8 +809,8 @@ static Bool FUNC_NAME(R300TextureSetup)(PicturePtr pPict, PixmapPtr pPix, - - txformat1 = R300TexFormats[i].card_fmt; - -- txformat0 = (((RADEONPow2(w) - 1) << R300_TXWIDTH_SHIFT) | -- ((RADEONPow2(h) - 1) << R300_TXHEIGHT_SHIFT)); -+ txformat0 = (((w - 1) << R300_TXWIDTH_SHIFT) | -+ ((h - 1) << R300_TXHEIGHT_SHIFT)); - - if (pPict->repeat) { - ErrorF("repeat\n"); -@@ -822,15 +822,18 @@ static Bool FUNC_NAME(R300TextureSetup)(PicturePtr pPict, PixmapPtr pPix, - txformat0 |= R300_TXPITCH_EN; - - -- info->texW[unit] = RADEONPow2(w); -- info->texH[unit] = RADEONPow2(h); -+ info->texW[unit] = w; -+ info->texH[unit] = h; -+ -+ txfilter = (R300_TX_CLAMP_S(R300_TX_CLAMP_CLAMP_LAST) | -+ R300_TX_CLAMP_T(R300_TX_CLAMP_CLAMP_LAST)); - - switch (pPict->filter) { - case PictFilterNearest: -- txfilter = (R300_TX_MAG_FILTER_NEAREST | R300_TX_MIN_FILTER_NEAREST); -+ txfilter |= (R300_TX_MAG_FILTER_NEAREST | R300_TX_MIN_FILTER_NEAREST); - break; - case PictFilterBilinear: -- txfilter = (R300_TX_MAG_FILTER_LINEAR | R300_TX_MIN_FILTER_LINEAR); -+ txfilter |= (R300_TX_MAG_FILTER_LINEAR | R300_TX_MIN_FILTER_LINEAR); - break; - default: - RADEON_FALLBACK(("Bad filter 0x%x\n", pPict->filter)); -@@ -937,6 +940,7 @@ static Bool FUNC_NAME(R300PrepareComposite)(int op, PicturePtr pSrcPicture, - CARD32 txenable, colorpitch; - CARD32 blendcntl; - int pixel_shift; -+ int has_tcl = (info->ChipFamily != CHIP_FAMILY_RS690 && info->ChipFamily != CHIP_FAMILY_RS400); - ACCEL_PREAMBLE(); - - TRACE; -@@ -975,22 +979,223 @@ static Bool FUNC_NAME(R300PrepareComposite)(int op, PicturePtr pSrcPicture, - - RADEON_SWITCH_TO_3D(); - -- /* setup pixel shader */ -- BEGIN_ACCEL(12); -- OUT_ACCEL_REG(R300_US_CONFIG, 0x8); -- OUT_ACCEL_REG(R300_US_PIXSIZE, 0x0); -- OUT_ACCEL_REG(R300_US_CODE_OFFSET, 0x40040); -- OUT_ACCEL_REG(R300_US_CODE_ADDR_0, 0x0); -- OUT_ACCEL_REG(R300_US_CODE_ADDR_1, 0x0); -- OUT_ACCEL_REG(R300_US_CODE_ADDR_2, 0x0); -- OUT_ACCEL_REG(R300_US_CODE_ADDR_3, 0x400000); -- OUT_ACCEL_REG(R300_US_TEX_INST_0, 0x8000); -- OUT_ACCEL_REG(R300_US_ALU_RGB_ADDR_0, 0x1f800000); -- OUT_ACCEL_REG(R300_US_ALU_RGB_INST_0, 0x50a80); -- OUT_ACCEL_REG(R300_US_ALU_ALPHA_ADDR_0, 0x1800000); -- OUT_ACCEL_REG(R300_US_ALU_ALPHA_INST_0, 0x00040889); -+ /* setup the VAP */ -+ -+ if (has_tcl) { -+ BEGIN_ACCEL(28); -+ OUT_ACCEL_REG(R300_VAP_CNTL_STATUS, 0); -+ OUT_ACCEL_REG(R300_VAP_PVS_STATE_FLUSH_REG, 0); -+ OUT_ACCEL_REG(R300_VAP_CNTL, ((6 << R300_PVS_NUM_SLOTS_SHIFT) | -+ (5 << R300_PVS_NUM_CNTLRS_SHIFT) | -+ (4 << R300_PVS_NUM_FPUS_SHIFT) | -+ (12 << R300_VF_MAX_VTX_NUM_SHIFT))); -+ } else { -+ BEGIN_ACCEL(10); -+ OUT_ACCEL_REG(R300_VAP_CNTL_STATUS, R300_PVS_BYPASS); -+ OUT_ACCEL_REG(R300_VAP_CNTL, ((10 << R300_PVS_NUM_SLOTS_SHIFT) | -+ (5 << R300_PVS_NUM_CNTLRS_SHIFT) | -+ (4 << R300_PVS_NUM_FPUS_SHIFT) | -+ (5 << R300_VF_MAX_VTX_NUM_SHIFT))); -+ } -+ -+ OUT_ACCEL_REG(R300_VAP_VTE_CNTL, R300_VTX_XY_FMT | R300_VTX_Z_FMT); -+ OUT_ACCEL_REG(R300_VAP_PSC_SGN_NORM_CNTL, 0); -+ -+ if (has_tcl) { -+ OUT_ACCEL_REG(R300_VAP_PROG_STREAM_CNTL_0, -+ ((R300_DATA_TYPE_FLOAT_2 << R300_DATA_TYPE_0_SHIFT) | -+ (0 << R300_SKIP_DWORDS_0_SHIFT) | -+ (0 << R300_DST_VEC_LOC_0_SHIFT) | -+ R300_SIGNED_0 | -+ (R300_DATA_TYPE_FLOAT_2 << R300_DATA_TYPE_1_SHIFT) | -+ (0 << R300_SKIP_DWORDS_1_SHIFT) | -+ (10 << R300_DST_VEC_LOC_1_SHIFT) | -+ R300_SIGNED_1)); -+ OUT_ACCEL_REG(R300_VAP_PROG_STREAM_CNTL_1, -+ ((R300_DATA_TYPE_FLOAT_2 << R300_DATA_TYPE_2_SHIFT) | -+ (0 << R300_SKIP_DWORDS_2_SHIFT) | -+ (11 << R300_DST_VEC_LOC_2_SHIFT) | -+ R300_LAST_VEC_2 | -+ R300_SIGNED_2)); -+ OUT_ACCEL_REG(R300_VAP_PROG_STREAM_CNTL_EXT_0, -+ ((R300_SWIZZLE_SELECT_X << R300_SWIZZLE_SELECT_X_0_SHIFT) | -+ (R300_SWIZZLE_SELECT_Y << R300_SWIZZLE_SELECT_Y_0_SHIFT) | -+ (R300_SWIZZLE_SELECT_Z << R300_SWIZZLE_SELECT_Z_0_SHIFT) | -+ (R300_SWIZZLE_SELECT_W << R300_SWIZZLE_SELECT_W_0_SHIFT) | -+ ((R300_WRITE_ENA_X | R300_WRITE_ENA_Y | R300_WRITE_ENA_Z | R300_WRITE_ENA_W) -+ << R300_WRITE_ENA_0_SHIFT) | -+ (R300_SWIZZLE_SELECT_X << R300_SWIZZLE_SELECT_X_1_SHIFT) | -+ (R300_SWIZZLE_SELECT_Y << R300_SWIZZLE_SELECT_Y_1_SHIFT) | -+ (R300_SWIZZLE_SELECT_Z << R300_SWIZZLE_SELECT_Z_1_SHIFT) | -+ (R300_SWIZZLE_SELECT_W << R300_SWIZZLE_SELECT_W_1_SHIFT) | -+ ((R300_WRITE_ENA_X | R300_WRITE_ENA_Y | R300_WRITE_ENA_Z | R300_WRITE_ENA_W) -+ << R300_WRITE_ENA_1_SHIFT))); -+ OUT_ACCEL_REG(R300_VAP_PROG_STREAM_CNTL_EXT_1, -+ ((R300_SWIZZLE_SELECT_X << R300_SWIZZLE_SELECT_X_2_SHIFT) | -+ (R300_SWIZZLE_SELECT_Y << R300_SWIZZLE_SELECT_Y_2_SHIFT) | -+ (R300_SWIZZLE_SELECT_Z << R300_SWIZZLE_SELECT_Z_2_SHIFT) | -+ (R300_SWIZZLE_SELECT_W << R300_SWIZZLE_SELECT_W_2_SHIFT) | -+ ((R300_WRITE_ENA_X | R300_WRITE_ENA_Y | R300_WRITE_ENA_Z | R300_WRITE_ENA_W) -+ << R300_WRITE_ENA_2_SHIFT))); -+ } else { -+ OUT_ACCEL_REG(R300_VAP_PROG_STREAM_CNTL_0, -+ ((R300_DATA_TYPE_FLOAT_2 << R300_DATA_TYPE_0_SHIFT) | -+ (0 << R300_SKIP_DWORDS_0_SHIFT) | -+ (0 << R300_DST_VEC_LOC_0_SHIFT) | -+ R300_SIGNED_0 | -+ (R300_DATA_TYPE_FLOAT_2 << R300_DATA_TYPE_1_SHIFT) | -+ (0 << R300_SKIP_DWORDS_1_SHIFT) | -+ (6 << R300_DST_VEC_LOC_1_SHIFT) | -+ R300_SIGNED_1)); -+ OUT_ACCEL_REG(R300_VAP_PROG_STREAM_CNTL_1, -+ ((R300_DATA_TYPE_FLOAT_2 << R300_DATA_TYPE_2_SHIFT) | -+ (0 << R300_SKIP_DWORDS_2_SHIFT) | -+ (7 << R300_DST_VEC_LOC_2_SHIFT) | -+ R300_LAST_VEC_2 | -+ R300_SIGNED_2)); -+ OUT_ACCEL_REG(R300_VAP_PROG_STREAM_CNTL_EXT_0, -+ ((R300_SWIZZLE_SELECT_X << R300_SWIZZLE_SELECT_X_0_SHIFT) | -+ (R300_SWIZZLE_SELECT_Y << R300_SWIZZLE_SELECT_Y_0_SHIFT) | -+ (R300_SWIZZLE_SELECT_FP_ZERO << R300_SWIZZLE_SELECT_Z_0_SHIFT) | -+ (R300_SWIZZLE_SELECT_FP_ONE << R300_SWIZZLE_SELECT_W_0_SHIFT) | -+ ((R300_WRITE_ENA_X | R300_WRITE_ENA_Y) -+ << R300_WRITE_ENA_0_SHIFT) | -+ (R300_SWIZZLE_SELECT_X << R300_SWIZZLE_SELECT_X_1_SHIFT) | -+ (R300_SWIZZLE_SELECT_Y << R300_SWIZZLE_SELECT_Y_1_SHIFT) | -+ (R300_SWIZZLE_SELECT_FP_ZERO << R300_SWIZZLE_SELECT_Z_1_SHIFT) | -+ (R300_SWIZZLE_SELECT_FP_ONE << R300_SWIZZLE_SELECT_W_1_SHIFT) | -+ ((R300_WRITE_ENA_X | R300_WRITE_ENA_Y) -+ << R300_WRITE_ENA_1_SHIFT))); -+ OUT_ACCEL_REG(R300_VAP_PROG_STREAM_CNTL_EXT_1, -+ ((R300_SWIZZLE_SELECT_X << R300_SWIZZLE_SELECT_X_2_SHIFT) | -+ (R300_SWIZZLE_SELECT_Y << R300_SWIZZLE_SELECT_Y_2_SHIFT) | -+ (R300_SWIZZLE_SELECT_FP_ZERO << R300_SWIZZLE_SELECT_Z_2_SHIFT) | -+ (R300_SWIZZLE_SELECT_FP_ONE << R300_SWIZZLE_SELECT_W_2_SHIFT) | -+ ((R300_WRITE_ENA_X | R300_WRITE_ENA_Y) -+ << R300_WRITE_ENA_2_SHIFT))); -+ } -+ -+ /* setup the vertex shader */ -+ if (has_tcl) { -+ OUT_ACCEL_REG(R300_VAP_PVS_CODE_CNTL_0, -+ ((0 << R300_PVS_FIRST_INST_SHIFT) | -+ (1 << R300_PVS_XYZW_VALID_INST_SHIFT) | -+ (1 << R300_PVS_LAST_INST_SHIFT))); -+ OUT_ACCEL_REG(R300_VAP_PVS_CODE_CNTL_1, -+ (1 << R300_PVS_LAST_VTX_SRC_INST_SHIFT)); -+ OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_INDX_REG, 0); -+ OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_DATA_REG,0x00f00203); -+ OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_DATA_REG,0x00d10001); -+ OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_DATA_REG,0x01248001); -+ OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_DATA_REG,0x01248001); -+ OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_DATA_REG,0x00f02203); -+ OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_DATA_REG,0x00d10141); -+ OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_DATA_REG,0x01248141); -+ OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_DATA_REG,0x01248141); -+ -+ OUT_ACCEL_REG(R300_VAP_PVS_FLOW_CNTL_OPC, 0); -+ -+ OUT_ACCEL_REG(R300_VAP_GB_VERT_CLIP_ADJ, 0x3f800000); -+ OUT_ACCEL_REG(R300_VAP_GB_VERT_DISC_ADJ, 0x3f800000); -+ OUT_ACCEL_REG(R300_VAP_GB_HORZ_CLIP_ADJ, 0x3f800000); -+ OUT_ACCEL_REG(R300_VAP_GB_HORZ_DISC_ADJ, 0x3f800000); -+ OUT_ACCEL_REG(R300_VAP_CLIP_CNTL, R300_CLIP_DISABLE); -+ } -+ OUT_ACCEL_REG(R300_VAP_OUT_VTX_FMT_0, R300_VTX_POS_PRESENT); -+ OUT_ACCEL_REG(R300_VAP_OUT_VTX_FMT_1, -+ ((2 << R300_TEX_0_COMP_CNT_SHIFT) | -+ (2 << R300_TEX_1_COMP_CNT_SHIFT))); -+ - FINISH_ACCEL(); - -+ /* setup pixel shader */ -+ if (IS_R300_VARIANT || info->ChipFamily == CHIP_FAMILY_RS690) { -+ BEGIN_ACCEL(16); -+ OUT_ACCEL_REG(R300_RS_COUNT, -+ ((2 << R300_RS_COUNT_IT_COUNT_SHIFT) | -+ R300_RS_COUNT_HIRES_EN)); -+ OUT_ACCEL_REG(R300_RS_IP_0, -+ (R300_RS_TEX_PTR(0) | -+ R300_RS_COL_PTR(0) | -+ R300_RS_COL_FMT(R300_RS_COL_FMT_RGBA) | -+ R300_RS_SEL_S(R300_RS_SEL_C0) | -+ R300_RS_SEL_T(R300_RS_SEL_C1) | -+ R300_RS_SEL_R(R300_RS_SEL_K0) | -+ R300_RS_SEL_Q(R300_RS_SEL_K1))); -+ OUT_ACCEL_REG(R300_RS_INST_COUNT, R300_TX_OFFSET_RS(6)); -+ OUT_ACCEL_REG(R300_RS_INST_0, R300_RS_INST_TEX_CN_WRITE); -+ OUT_ACCEL_REG(R300_US_CONFIG, (0 << R300_NLEVEL_SHIFT) | R300_FIRST_TEX); -+ OUT_ACCEL_REG(R300_US_PIXSIZE, 0); -+ OUT_ACCEL_REG(R300_US_CODE_OFFSET, -+ (R300_ALU_CODE_OFFSET(0) | -+ R300_ALU_CODE_SIZE(1) | -+ R300_TEX_CODE_OFFSET(0) | -+ R300_TEX_CODE_SIZE(1))); -+ OUT_ACCEL_REG(R300_US_CODE_ADDR_0, 0); -+ OUT_ACCEL_REG(R300_US_CODE_ADDR_1, 0); -+ OUT_ACCEL_REG(R300_US_CODE_ADDR_2, 0); -+ OUT_ACCEL_REG(R300_US_CODE_ADDR_3, 0x400000); -+ OUT_ACCEL_REG(R300_US_TEX_INST_0, 0x8000); -+ OUT_ACCEL_REG(R300_US_ALU_RGB_ADDR_0, 0x1f800000); -+ OUT_ACCEL_REG(R300_US_ALU_RGB_INST_0, 0x50a80); -+ OUT_ACCEL_REG(R300_US_ALU_ALPHA_ADDR_0, 0x1800000); -+ OUT_ACCEL_REG(R300_US_ALU_ALPHA_INST_0, 0x00040889); -+ FINISH_ACCEL(); -+ } else { -+ BEGIN_ACCEL(23); -+ OUT_ACCEL_REG(R300_RS_COUNT, -+ ((2 << R300_RS_COUNT_IT_COUNT_SHIFT) | -+ R300_RS_COUNT_HIRES_EN)); -+ OUT_ACCEL_REG(R500_RS_IP_0, (0 << R500_RS_IP_TEX_PTR_S_SHIFT) | (1 << R500_RS_IP_TEX_PTR_T_SHIFT) | -+ (R500_RS_IP_PTR_K0 << R500_RS_IP_TEX_PTR_R_SHIFT) | (R500_RS_IP_PTR_K1 << R500_RS_IP_TEX_PTR_Q_SHIFT)); -+ -+ OUT_ACCEL_REG(R300_RS_INST_COUNT, 0); -+ OUT_ACCEL_REG(R500_RS_INST_0, R500_RS_INST_TEX_CN_WRITE); -+ OUT_ACCEL_REG(R300_US_CONFIG, R500_ZERO_TIMES_ANYTHING_EQUALS_ZERO); -+ OUT_ACCEL_REG(R300_US_PIXSIZE, 0); -+ OUT_ACCEL_REG(R500_US_FC_CTRL, 0); -+ OUT_ACCEL_REG(R500_US_CODE_ADDR, R500_US_CODE_START_ADDR(0) | R500_US_CODE_END_ADDR(1)); -+ OUT_ACCEL_REG(R500_US_CODE_RANGE, R500_US_CODE_RANGE_ADDR(0) | R500_US_CODE_RANGE_SIZE(1)); -+ OUT_ACCEL_REG(R500_US_CODE_OFFSET, 0); -+ OUT_ACCEL_REG(R500_GA_US_VECTOR_INDEX, 0); -+ // 7807 -+ OUT_ACCEL_REG(R500_GA_US_VECTOR_DATA, R500_INST_TYPE_TEX | R500_INST_TEX_SEM_WAIT | -+ R500_INST_RGB_WMASK_R | R500_INST_RGB_WMASK_G | R500_INST_RGB_WMASK_B | R500_INST_ALPHA_WMASK); -+ -+ OUT_ACCEL_REG(R500_GA_US_VECTOR_DATA, R500_TEX_ID(0) | R500_TEX_INST_LD | R500_TEX_SEM_ACQUIRE | -+ R500_TEX_IGNORE_UNCOVERED); -+ -+ OUT_ACCEL_REG(R500_GA_US_VECTOR_DATA, R500_TEX_SRC_ADDR(0) | R500_TEX_SRC_S_SWIZ_R | R500_TEX_SRC_T_SWIZ_G | -+ R500_TEX_DST_ADDR(0) | R500_TEX_DST_R_SWIZ_R | R500_TEX_DST_G_SWIZ_G | R500_TEX_DST_B_SWIZ_B | -+ R500_TEX_DST_A_SWIZ_A); -+ OUT_ACCEL_REG(R500_GA_US_VECTOR_DATA, 0x00000000); // TEX_ADDR_DXDY -+ OUT_ACCEL_REG(R500_GA_US_VECTOR_DATA, 0x00000000); // mbz -+ OUT_ACCEL_REG(R500_GA_US_VECTOR_DATA, 0x00000000); // mbz -+ -+ // 0x78105 -+ OUT_ACCEL_REG(R500_GA_US_VECTOR_DATA, R500_INST_TYPE_OUT | R500_INST_TEX_SEM_WAIT | R500_INST_LAST | -+ R500_INST_RGB_OMASK_R | R500_INST_RGB_OMASK_G | R500_INST_RGB_OMASK_B | R500_INST_ALPHA_OMASK); -+ -+ OUT_ACCEL_REG(R500_GA_US_VECTOR_DATA, R500_RGB_ADDR0(0) | R500_RGB_ADDR1(0) | R500_RGB_ADDR1_CONST | -+ R500_RGB_ADDR2(0) | R500_RGB_ADDR2_CONST | R500_RGB_SRCP_OP_1_MINUS_2RGB0); //0x10040000 -+ OUT_ACCEL_REG(R500_GA_US_VECTOR_DATA, R500_ALPHA_ADDR0(0) | R500_ALPHA_ADDR1(0) | R500_ALPHA_ADDR1_CONST | -+ R500_ALPHA_ADDR2(0) | R500_ALPHA_ADDR2_CONST | R500_ALPHA_SRCP_OP_1_MINUS_2A0); //0x10040000 -+ -+ OUT_ACCEL_REG(R500_GA_US_VECTOR_DATA, -+ R500_ALU_RGB_SEL_A_SRC0 | -+ R500_ALU_RGB_R_SWIZ_A_R | R500_ALU_RGB_G_SWIZ_A_G | R500_ALU_RGB_B_SWIZ_A_B | -+ R500_ALU_RGB_SEL_B_SRC0 | -+ R500_ALU_RGB_R_SWIZ_B_1 | R500_ALU_RGB_B_SWIZ_B_1 | R500_ALU_RGB_G_SWIZ_B_1);//0x00db0220 -+ -+ OUT_ACCEL_REG(R500_GA_US_VECTOR_DATA, R500_ALPHA_OP_MAD | -+ R500_ALPHA_SWIZ_A_A | R500_ALPHA_SWIZ_B_1);//0x00c0c000) -+ -+ OUT_ACCEL_REG(R500_GA_US_VECTOR_DATA, R500_ALU_RGBA_OP_MAD | -+ R500_ALU_RGBA_R_SWIZ_0 | R500_ALU_RGBA_G_SWIZ_0 | R500_ALU_RGBA_B_SWIZ_0 | -+ R500_ALU_RGBA_A_SWIZ_0);//0x20490000 -+ FINISH_ACCEL(); -+ } -+ - BEGIN_ACCEL(6); - OUT_ACCEL_REG(R300_TX_INVALTAGS, 0x0); - OUT_ACCEL_REG(R300_TX_ENABLE, txenable); -@@ -1000,7 +1205,7 @@ static Bool FUNC_NAME(R300PrepareComposite)(int op, PicturePtr pSrcPicture, - - blendcntl = RADEONGetBlendCntl(op, pMaskPicture, pDstPicture->format); - OUT_ACCEL_REG(R300_RB3D_BLENDCNTL, blendcntl); -- OUT_ACCEL_REG(R300_RB3D_ABLENDCNTL, 0x0); -+ OUT_ACCEL_REG(R300_RB3D_ABLENDCNTL, 0); - - #if 0 - /* IN operator: Multiply src by mask components or mask alpha. -@@ -1094,8 +1299,6 @@ static inline void transformPoint(PictTransform *transform, xPointFixed *point) - } - #endif - --#define xFixedToFloat(f) (((float) (f)) / 65536) -- - static void FUNC_NAME(RadeonComposite)(PixmapPtr pDst, - int srcX, int srcY, - int maskX, int maskY, -@@ -1103,7 +1306,6 @@ static void FUNC_NAME(RadeonComposite)(PixmapPtr pDst, - int w, int h) - { - RINFO_FROM_SCREEN(pDst->drawable.pScreen); -- int srcXend, srcYend, maskXend, maskYend; - int vtx_count; - xPointFixed srcTopLeft, srcTopRight, srcBottomLeft, srcBottomRight; - xPointFixed maskTopLeft, maskTopRight, maskBottomLeft, maskBottomRight; -@@ -1114,11 +1316,6 @@ static void FUNC_NAME(RadeonComposite)(PixmapPtr pDst, - /* ErrorF("RadeonComposite (%d,%d) (%d,%d) (%d,%d) (%d,%d)\n", - srcX, srcY, maskX, maskY,dstX, dstY, w, h); */ - -- srcXend = srcX + w; -- srcYend = srcY + h; -- maskXend = maskX + w; -- maskYend = maskY + h; -- - srcTopLeft.x = IntToxFixed(srcX); - srcTopLeft.y = IntToxFixed(srcY); - srcTopRight.x = IntToxFixed(srcX + w); -@@ -1152,7 +1349,7 @@ static void FUNC_NAME(RadeonComposite)(PixmapPtr pDst, - - vtx_count = VTX_COUNT; - -- if (IS_R300_VARIANT) { -+ if (IS_R300_VARIANT || IS_AVIVO_VARIANT) { - BEGIN_ACCEL(1); - OUT_ACCEL_REG(R300_VAP_VTX_SIZE, vtx_count); - FINISH_ACCEL(); -@@ -1172,7 +1369,7 @@ static void FUNC_NAME(RadeonComposite)(PixmapPtr pDst, - RADEON_CP_VC_CNTL_VTX_FMT_RADEON_MODE | - (4 << RADEON_CP_VC_CNTL_NUM_SHIFT)); - } else { -- if (IS_R300_VARIANT) -+ if (IS_R300_VARIANT || IS_AVIVO_VARIANT) - BEGIN_RING(4 * vtx_count + 6); - else - BEGIN_RING(4 * vtx_count + 2); -@@ -1185,7 +1382,7 @@ static void FUNC_NAME(RadeonComposite)(PixmapPtr pDst, - } - - #else /* ACCEL_CP */ -- if (IS_R300_VARIANT) -+ if (IS_R300_VARIANT || IS_AVIVO_VARIANT) - BEGIN_ACCEL(3 + vtx_count * 4); - else - BEGIN_ACCEL(1 + vtx_count * 4); -@@ -1202,29 +1399,21 @@ static void FUNC_NAME(RadeonComposite)(PixmapPtr pDst, - } - #endif - -- if (info->texW[0] == 1 && info->texH[0] == 1 && -- info->texW[1] == 1 && info->texH[1] == 1) { -- VTX_OUT(dstX, dstY, srcX, srcY, maskX, maskY); -- VTX_OUT(dstX, dstY + h, srcX, srcYend, maskX, maskYend); -- VTX_OUT(dstX + w, dstY + h, srcXend, srcYend, maskXend, maskYend); -- VTX_OUT(dstX + w, dstY, srcXend, srcY, maskXend, maskY); -- } else { -- VTX_OUT((float)dstX, (float)dstY, -- xFixedToFloat(srcTopLeft.x) / info->texW[0], xFixedToFloat(srcTopLeft.y) / info->texH[0], -- xFixedToFloat(maskTopLeft.x) / info->texW[1], xFixedToFloat(maskTopLeft.y) / info->texH[1]); -- VTX_OUT((float)dstX, (float)(dstY + h), -- xFixedToFloat(srcBottomLeft.x) / info->texW[0], xFixedToFloat(srcBottomLeft.y) / info->texH[0], -- xFixedToFloat(maskBottomLeft.x) / info->texW[1], xFixedToFloat(maskBottomLeft.y) / info->texH[1]); -- VTX_OUT((float)(dstX + w), (float)(dstY + h), -- xFixedToFloat(srcBottomRight.x) / info->texW[0], xFixedToFloat(srcBottomRight.y) / info->texH[0], -- xFixedToFloat(maskBottomRight.x) / info->texW[1], xFixedToFloat(maskBottomRight.y) / info->texH[1]); -- VTX_OUT((float)(dstX + w), (float)dstY, -- xFixedToFloat(srcTopRight.x) / info->texW[0], xFixedToFloat(srcTopRight.y) / info->texH[0], -- xFixedToFloat(maskTopRight.x) / info->texW[1], xFixedToFloat(maskTopRight.y) / info->texH[1]); -- } -- -- if (IS_R300_VARIANT) { -- OUT_ACCEL_REG(R300_RB3D_DSTCACHE_CTLSTAT, 0xA); -+ VTX_OUT((float)dstX, (float)dstY, -+ xFixedToFloat(srcTopLeft.x) / info->texW[0], xFixedToFloat(srcTopLeft.y) / info->texH[0], -+ xFixedToFloat(maskTopLeft.x) / info->texW[1], xFixedToFloat(maskTopLeft.y) / info->texH[1]); -+ VTX_OUT((float)dstX, (float)(dstY + h), -+ xFixedToFloat(srcBottomLeft.x) / info->texW[0], xFixedToFloat(srcBottomLeft.y) / info->texH[0], -+ xFixedToFloat(maskBottomLeft.x) / info->texW[1], xFixedToFloat(maskBottomLeft.y) / info->texH[1]); -+ VTX_OUT((float)(dstX + w), (float)(dstY + h), -+ xFixedToFloat(srcBottomRight.x) / info->texW[0], xFixedToFloat(srcBottomRight.y) / info->texH[0], -+ xFixedToFloat(maskBottomRight.x) / info->texW[1], xFixedToFloat(maskBottomRight.y) / info->texH[1]); -+ VTX_OUT((float)(dstX + w), (float)dstY, -+ xFixedToFloat(srcTopRight.x) / info->texW[0], xFixedToFloat(srcTopRight.y) / info->texH[0], -+ xFixedToFloat(maskTopRight.x) / info->texW[1], xFixedToFloat(maskTopRight.y) / info->texH[1]); -+ -+ if (IS_R300_VARIANT || IS_AVIVO_VARIANT) { -+ OUT_ACCEL_REG(R300_RB3D_DSTCACHE_CTLSTAT, R300_DC_FLUSH_3D | R300_DC_FREE_3D); - OUT_ACCEL_REG(RADEON_WAIT_UNTIL, RADEON_WAIT_3D_IDLECLEAN); - } - -@@ -1237,7 +1426,6 @@ static void FUNC_NAME(RadeonComposite)(PixmapPtr pDst, - LEAVE_DRAW(0); - } - #undef VTX_OUT --#undef VTX_OUT4 - - #ifdef ONLY_ONCE - static void RadeonDoneComposite(PixmapPtr pDst) -@@ -1248,3 +1436,4 @@ static void RadeonDoneComposite(PixmapPtr pDst) - #endif /* ONLY_ONCE */ - - #undef ONLY_ONCE -+#undef FUNC_NAME -diff --git a/src/radeon_output.c b/src/radeon_output.c -index aceb3d8..62cc5d4 100644 ---- a/src/radeon_output.c -+++ b/src/radeon_output.c -@@ -74,11 +74,12 @@ const RADEONMonitorType MonTypeID[10] = { - MT_DP - }; - --const char *TMDSTypeName[4] = { -+const char *TMDSTypeName[5] = { - "None", - "Internal", - "External", - "LVTMA", -+ "DDIA" - }; - - const char *DACTypeName[4] = { -@@ -393,7 +394,7 @@ void RADEONConnectorFindMonitor(ScrnInfoPtr pScrn, xf86OutputPtr output) - /* panel is probably busted or not connected */ - if ((radeon_output->MonType == MT_LCD) && - ((radeon_output->PanelXRes == 0) || (radeon_output->PanelYRes == 0))) -- radeon_output->MonType == MT_NONE; -+ radeon_output->MonType = MT_NONE; - - if (output->MonInfo) { - xf86DrvMsg(pScrn->scrnIndex, X_INFO, "EDID data from the display on output: %s ----------------------\n", -@@ -1754,12 +1755,23 @@ legacy_setup_i2c_bus(int ddc_line) - i2c.put_data_mask = RADEON_GPIO_EN_0; - i2c.get_clk_mask = RADEON_GPIO_Y_1; - i2c.get_data_mask = RADEON_GPIO_Y_0; -- i2c.mask_clk_reg = ddc_line; -- i2c.mask_data_reg = ddc_line; -- i2c.put_clk_reg = ddc_line; -- i2c.put_data_reg = ddc_line; -- i2c.get_clk_reg = ddc_line; -- i2c.get_data_reg = ddc_line; -+ if ((ddc_line == RADEON_LCD_GPIO_MASK) || -+ (ddc_line == RADEON_MDGPIO_EN_REG)) { -+ i2c.mask_clk_reg = ddc_line; -+ i2c.mask_data_reg = ddc_line; -+ i2c.put_clk_reg = ddc_line; -+ i2c.put_data_reg = ddc_line; -+ i2c.get_clk_reg = ddc_line + 4; -+ i2c.get_data_reg = ddc_line + 4; -+ } else { -+ i2c.mask_clk_reg = ddc_line; -+ i2c.mask_data_reg = ddc_line; -+ i2c.put_clk_reg = ddc_line; -+ i2c.put_data_reg = ddc_line; -+ i2c.get_clk_reg = ddc_line; -+ i2c.get_data_reg = ddc_line; -+ } -+ - if (ddc_line) - i2c.valid = TRUE; - else -diff --git a/src/radeon_probe.h b/src/radeon_probe.h -index a3cf1fc..9c1bdc5 100644 ---- a/src/radeon_probe.h -+++ b/src/radeon_probe.h -@@ -103,7 +103,8 @@ typedef enum - TMDS_NONE = 0, - TMDS_INT = 1, - TMDS_EXT = 2, -- TMDS_LVTMA = 3 -+ TMDS_LVTMA = 3, -+ TMDS_DDIA = 4 - } RADEONTmdsType; - - typedef enum -diff --git a/src/radeon_reg.h b/src/radeon_reg.h -index 61cdb15..046c52b 100644 ---- a/src/radeon_reg.h -+++ b/src/radeon_reg.h -@@ -3819,53 +3819,265 @@ - #define R600_BIOS_7_SCRATCH 0x1740 - - #define R300_GB_TILE_CONFIG 0x4018 -+# define R300_ENABLE_TILING (1 << 0) -+# define R300_PIPE_COUNT_RV350 (0 << 1) -+# define R300_PIPE_COUNT_R300 (3 << 1) -+# define R300_PIPE_COUNT_R420_3P (6 << 1) -+# define R300_PIPE_COUNT_R420 (7 << 1) -+# define R300_TILE_SIZE_8 (0 << 4) -+# define R300_TILE_SIZE_16 (1 << 4) -+# define R300_TILE_SIZE_32 (2 << 4) -+# define R300_SUBPIXEL_1_12 (0 << 16) -+# define R300_SUBPIXEL_1_16 (1 << 16) - #define R300_GB_SELECT 0x401c - #define R300_GB_ENABLE 0x4008 - #define R300_GB_AA_CONFIG 0x4020 - #define R300_GB_MSPOS0 0x4010 -+# define R300_MS_X0_SHIFT 0 -+# define R300_MS_Y0_SHIFT 4 -+# define R300_MS_X1_SHIFT 8 -+# define R300_MS_Y1_SHIFT 12 -+# define R300_MS_X2_SHIFT 16 -+# define R300_MS_Y2_SHIFT 20 -+# define R300_MSBD0_Y_SHIFT 24 -+# define R300_MSBD0_X_SHIFT 28 - #define R300_GB_MSPOS1 0x4014 -+# define R300_MS_X3_SHIFT 0 -+# define R300_MS_Y3_SHIFT 4 -+# define R300_MS_X4_SHIFT 8 -+# define R300_MS_Y4_SHIFT 12 -+# define R300_MS_X5_SHIFT 16 -+# define R300_MS_Y5_SHIFT 20 -+# define R300_MSBD1_SHIFT 24 - - #define R300_GA_POLY_MODE 0x4288 -+# define R300_FRONT_PTYPE_POINT (0 << 4) -+# define R300_FRONT_PTYPE_LINE (1 << 4) -+# define R300_FRONT_PTYPE_TRIANGE (2 << 4) -+# define R300_BACK_PTYPE_POINT (0 << 7) -+# define R300_BACK_PTYPE_LINE (1 << 7) -+# define R300_BACK_PTYPE_TRIANGE (2 << 7) - #define R300_GA_ROUND_MODE 0x428c -+# define R300_GEOMETRY_ROUND_TRUNC (0 << 0) -+# define R300_GEOMETRY_ROUND_NEAREST (1 << 0) -+# define R300_COLOR_ROUND_TRUNC (0 << 2) -+# define R300_COLOR_ROUND_NEAREST (1 << 2) - #define R300_GA_COLOR_CONTROL 0x4278 -+# define R300_RGB0_SHADING_SOLID (0 << 0) -+# define R300_RGB0_SHADING_FLAT (1 << 0) -+# define R300_RGB0_SHADING_GOURAUD (2 << 0) -+# define R300_ALPHA0_SHADING_SOLID (0 << 2) -+# define R300_ALPHA0_SHADING_FLAT (1 << 2) -+# define R300_ALPHA0_SHADING_GOURAUD (2 << 2) -+# define R300_RGB1_SHADING_SOLID (0 << 4) -+# define R300_RGB1_SHADING_FLAT (1 << 4) -+# define R300_RGB1_SHADING_GOURAUD (2 << 4) -+# define R300_ALPHA1_SHADING_SOLID (0 << 6) -+# define R300_ALPHA1_SHADING_FLAT (1 << 6) -+# define R300_ALPHA1_SHADING_GOURAUD (2 << 6) -+# define R300_RGB2_SHADING_SOLID (0 << 8) -+# define R300_RGB2_SHADING_FLAT (1 << 8) -+# define R300_RGB2_SHADING_GOURAUD (2 << 8) -+# define R300_ALPHA2_SHADING_SOLID (0 << 10) -+# define R300_ALPHA2_SHADING_FLAT (1 << 10) -+# define R300_ALPHA2_SHADING_GOURAUD (2 << 10) -+# define R300_RGB3_SHADING_SOLID (0 << 12) -+# define R300_RGB3_SHADING_FLAT (1 << 12) -+# define R300_RGB3_SHADING_GOURAUD (2 << 12) -+# define R300_ALPHA3_SHADING_SOLID (0 << 14) -+# define R300_ALPHA3_SHADING_FLAT (1 << 14) -+# define R300_ALPHA3_SHADING_GOURAUD (2 << 14) - #define R300_GA_OFFSET 0x4290 - - #define R300_VAP_CNTL_STATUS 0x2140 -+# define R300_PVS_BYPASS (1 << 8) - #define R300_VAP_PVS_STATE_FLUSH_REG 0x2284 - #define R300_VAP_CNTL 0x2080 -+# define R300_PVS_NUM_SLOTS_SHIFT 0 -+# define R300_PVS_NUM_CNTLRS_SHIFT 4 -+# define R300_PVS_NUM_FPUS_SHIFT 8 -+# define R300_VF_MAX_VTX_NUM_SHIFT 18 -+# define R300_GL_CLIP_SPACE_DEF (0 << 22) -+# define R300_DX_CLIP_SPACE_DEF (1 << 22) - #define R300_VAP_VTE_CNTL 0x20B0 -+# define R300_VPORT_X_SCALE_ENA (1 << 0) -+# define R300_VPORT_X_OFFSET_ENA (1 << 1) -+# define R300_VPORT_Y_SCALE_ENA (1 << 2) -+# define R300_VPORT_Y_OFFSET_ENA (1 << 3) -+# define R300_VPORT_Z_SCALE_ENA (1 << 4) -+# define R300_VPORT_Z_OFFSET_ENA (1 << 5) -+# define R300_VTX_XY_FMT (1 << 8) -+# define R300_VTX_Z_FMT (1 << 9) -+# define R300_VTX_W0_FMT (1 << 10) - #define R300_VAP_PSC_SGN_NORM_CNTL 0x21DC - #define R300_VAP_PROG_STREAM_CNTL_0 0x2150 -+# define R300_DATA_TYPE_0_SHIFT 0 -+# define R300_DATA_TYPE_FLOAT_1 0 -+# define R300_DATA_TYPE_FLOAT_2 1 -+# define R300_DATA_TYPE_FLOAT_3 2 -+# define R300_DATA_TYPE_FLOAT_4 3 -+# define R300_DATA_TYPE_BYTE 4 -+# define R300_DATA_TYPE_D3DCOLOR 5 -+# define R300_DATA_TYPE_SHORT_2 6 -+# define R300_DATA_TYPE_SHORT_4 7 -+# define R300_DATA_TYPE_VECTOR_3_TTT 8 -+# define R300_DATA_TYPE_VECTOR_3_EET 9 -+# define R300_SKIP_DWORDS_0_SHIFT 4 -+# define R300_DST_VEC_LOC_0_SHIFT 8 -+# define R300_LAST_VEC_0 (1 << 13) -+# define R300_SIGNED_0 (1 << 14) -+# define R300_NORMALIZE_0 (1 << 15) -+# define R300_DATA_TYPE_1_SHIFT 16 -+# define R300_SKIP_DWORDS_1_SHIFT 20 -+# define R300_DST_VEC_LOC_1_SHIFT 24 -+# define R300_LAST_VEC_1 (1 << 29) -+# define R300_SIGNED_1 (1 << 30) -+# define R300_NORMALIZE_1 (1 << 31) - #define R300_VAP_PROG_STREAM_CNTL_1 0x2154 -+# define R300_DATA_TYPE_2_SHIFT 0 -+# define R300_SKIP_DWORDS_2_SHIFT 4 -+# define R300_DST_VEC_LOC_2_SHIFT 8 -+# define R300_LAST_VEC_2 (1 << 13) -+# define R300_SIGNED_2 (1 << 14) -+# define R300_NORMALIZE_2 (1 << 15) -+# define R300_DATA_TYPE_3_SHIFT 16 -+# define R300_SKIP_DWORDS_3_SHIFT 20 -+# define R300_DST_VEC_LOC_3_SHIFT 24 -+# define R300_LAST_VEC_3 (1 << 29) -+# define R300_SIGNED_3 (1 << 30) -+# define R300_NORMALIZE_3 (1 << 31) - #define R300_VAP_PROG_STREAM_CNTL_EXT_0 0x21e0 -+# define R300_SWIZZLE_SELECT_X_0_SHIFT 0 -+# define R300_SWIZZLE_SELECT_Y_0_SHIFT 3 -+# define R300_SWIZZLE_SELECT_Z_0_SHIFT 6 -+# define R300_SWIZZLE_SELECT_W_0_SHIFT 9 -+# define R300_SWIZZLE_SELECT_X 0 -+# define R300_SWIZZLE_SELECT_Y 1 -+# define R300_SWIZZLE_SELECT_Z 2 -+# define R300_SWIZZLE_SELECT_W 3 -+# define R300_SWIZZLE_SELECT_FP_ZERO 4 -+# define R300_SWIZZLE_SELECT_FP_ONE 5 -+# define R300_WRITE_ENA_0_SHIFT 12 -+# define R300_WRITE_ENA_X 1 -+# define R300_WRITE_ENA_Y 2 -+# define R300_WRITE_ENA_Z 4 -+# define R300_WRITE_ENA_W 8 -+# define R300_SWIZZLE_SELECT_X_1_SHIFT 16 -+# define R300_SWIZZLE_SELECT_Y_1_SHIFT 19 -+# define R300_SWIZZLE_SELECT_Z_1_SHIFT 22 -+# define R300_SWIZZLE_SELECT_W_1_SHIFT 25 -+# define R300_WRITE_ENA_1_SHIFT 28 - #define R300_VAP_PROG_STREAM_CNTL_EXT_1 0x21e4 -+# define R300_SWIZZLE_SELECT_X_2_SHIFT 0 -+# define R300_SWIZZLE_SELECT_Y_2_SHIFT 3 -+# define R300_SWIZZLE_SELECT_Z_2_SHIFT 6 -+# define R300_SWIZZLE_SELECT_W_2_SHIFT 9 -+# define R300_WRITE_ENA_2_SHIFT 12 -+# define R300_SWIZZLE_SELECT_X_3_SHIFT 16 -+# define R300_SWIZZLE_SELECT_Y_3_SHIFT 19 -+# define R300_SWIZZLE_SELECT_Z_3_SHIFT 22 -+# define R300_SWIZZLE_SELECT_W_3_SHIFT 25 -+# define R300_WRITE_ENA_3_SHIFT 28 - #define R300_VAP_PVS_CODE_CNTL_0 0x22D0 -+# define R300_PVS_FIRST_INST_SHIFT 0 -+# define R300_PVS_XYZW_VALID_INST_SHIFT 10 -+# define R300_PVS_LAST_INST_SHIFT 20 - #define R300_VAP_PVS_CODE_CNTL_1 0x22D8 -+# define R300_PVS_LAST_VTX_SRC_INST_SHIFT 0 - #define R300_VAP_PVS_VECTOR_INDX_REG 0x2200 - #define R300_VAP_PVS_VECTOR_DATA_REG 0x2204 - #define R300_VAP_PVS_FLOW_CNTL_OPC 0x22DC - #define R300_VAP_OUT_VTX_FMT_0 0x2090 -+# define R300_VTX_POS_PRESENT (1 << 0) -+# define R300_VTX_COLOR_0_PRESENT (1 << 1) -+# define R300_VTX_COLOR_1_PRESENT (1 << 2) -+# define R300_VTX_COLOR_2_PRESENT (1 << 3) -+# define R300_VTX_COLOR_3_PRESENT (1 << 4) -+# define R300_VTX_PT_SIZE_PRESENT (1 << 16) - #define R300_VAP_OUT_VTX_FMT_1 0x2094 -+# define R300_TEX_0_COMP_CNT_SHIFT 0 -+# define R300_TEX_1_COMP_CNT_SHIFT 3 -+# define R300_TEX_2_COMP_CNT_SHIFT 6 -+# define R300_TEX_3_COMP_CNT_SHIFT 9 -+# define R300_TEX_4_COMP_CNT_SHIFT 12 -+# define R300_TEX_5_COMP_CNT_SHIFT 15 -+# define R300_TEX_6_COMP_CNT_SHIFT 18 -+# define R300_TEX_7_COMP_CNT_SHIFT 21 - #define R300_VAP_VTX_SIZE 0x20b4 - #define R300_VAP_GB_VERT_CLIP_ADJ 0x2220 - #define R300_VAP_GB_VERT_DISC_ADJ 0x2224 - #define R300_VAP_GB_HORZ_CLIP_ADJ 0x2228 - #define R300_VAP_GB_HORZ_DISC_ADJ 0x222c - #define R300_VAP_CLIP_CNTL 0x221c -+# define R300_UCP_ENA_0 (1 << 0) -+# define R300_UCP_ENA_1 (1 << 1) -+# define R300_UCP_ENA_2 (1 << 2) -+# define R300_UCP_ENA_3 (1 << 3) -+# define R300_UCP_ENA_4 (1 << 4) -+# define R300_UCP_ENA_5 (1 << 5) -+# define R300_PS_UCP_MODE_SHIFT 14 -+# define R300_CLIP_DISABLE (1 << 16) -+# define R300_UCP_CULL_ONLY_ENA (1 << 17) -+# define R300_BOUNDARY_EDGE_FLAG_ENA (1 << 18) - - #define R300_SU_TEX_WRAP 0x42a0 - #define R300_SU_POLY_OFFSET_ENABLE 0x42b4 - #define R300_SU_CULL_MODE 0x42b8 -+# define R300_CULL_FRONT (1 << 0) -+# define R300_CULL_BACK (1 << 1) -+# define R300_FACE_POS (0 << 2) -+# define R300_FACE_NEG (1 << 2) - #define R300_SU_DEPTH_SCALE 0x42c0 - #define R300_SU_DEPTH_OFFSET 0x42c4 - - #define R300_RS_COUNT 0x4300 -+# define R300_RS_COUNT_IT_COUNT_SHIFT 0 -+# define R300_RS_COUNT_IC_COUNT_SHIFT 7 -+# define R300_RS_COUNT_HIRES_EN (1 << 18) -+ - #define R300_RS_IP_0 0x4310 -+# define R300_RS_TEX_PTR(x) (x << 0) -+# define R300_RS_COL_PTR(x) (x << 6) -+# define R300_RS_COL_FMT(x) (x << 9) -+# define R300_RS_COL_FMT_RGBA 0 -+# define R300_RS_COL_FMT_RGB0 2 -+# define R300_RS_COL_FMT_RGB1 3 -+# define R300_RS_COL_FMT_000A 4 -+# define R300_RS_COL_FMT_0000 5 -+# define R300_RS_COL_FMT_0001 6 -+# define R300_RS_COL_FMT_111A 8 -+# define R300_RS_COL_FMT_1110 9 -+# define R300_RS_COL_FMT_1111 10 -+# define R300_RS_SEL_S(x) (x << 13) -+# define R300_RS_SEL_T(x) (x << 16) -+# define R300_RS_SEL_R(x) (x << 19) -+# define R300_RS_SEL_Q(x) (x << 22) -+# define R300_RS_SEL_C0 0 -+# define R300_RS_SEL_C1 1 -+# define R300_RS_SEL_C2 2 -+# define R300_RS_SEL_C3 3 -+# define R300_RS_SEL_K0 4 -+# define R300_RS_SEL_K1 5 - #define R300_RS_INST_COUNT 0x4304 -+# define R300_INST_COUNT_RS(x) (x << 0) -+# define R300_RS_W_EN (1 << 4) -+# define R300_TX_OFFSET_RS(x) (x << 5) - #define R300_RS_INST_0 0x4330 -+# define R300_RS_INST_TEX_CN_WRITE (1 << 3) - - #define R300_TX_INVALTAGS 0x4100 - #define R300_TX_FILTER0_0 0x4400 -+# define R300_TX_CLAMP_S(x) (x << 0) -+# define R300_TX_CLAMP_T(x) (x << 3) -+# define R300_TX_CLAMP_R(x) (x << 6) -+# define R300_TX_CLAMP_WRAP 0 -+# define R300_TX_CLAMP_MIRROR 1 -+# define R300_TX_CLAMP_CLAMP_LAST 2 -+# define R300_TX_CLAMP_MIRROR_CLAMP_LAST 3 -+# define R300_TX_CLAMP_CLAMP_BORDER 4 -+# define R300_TX_CLAMP_MIRROR_CLAMP_BORDER 5 -+# define R300_TX_CLAMP_CLAMP_GL 6 -+# define R300_TX_CLAMP_MIRROR_CLAMP_GL 7 - # define R300_TX_MAG_FILTER_NEAREST (1 << 9) - # define R300_TX_MIN_FILTER_NEAREST (1 << 11) - # define R300_TX_MAG_FILTER_LINEAR (2 << 9) -@@ -3901,6 +4113,8 @@ - # define R300_TX_FORMAT_A8R8G8B8 0x13 /* no swizzle */ - # define R300_TX_FORMAT_B8G8_B8G8 0x14 /* no swizzle */ - # define R300_TX_FORMAT_G8R8_G8B8 0x15 /* no swizzle */ -+# define R300_TX_FORMAT_VYUY422 0x14 /* no swizzle */ -+# define R300_TX_FORMAT_YVYU422 0x15 /* no swizzle */ - # define R300_TX_FORMAT_X24_Y8 0x1e - # define R300_TX_FORMAT_X32 0x1e - /* Floating point formats */ -@@ -3945,6 +4159,10 @@ - | (R300_TX_FORMAT_##FMT) \ - ) - -+# define R300_TX_FORMAT_YUV_TO_RGB_CLAMP (1 << 22) -+# define R300_TX_FORMAT_YUV_TO_RGB_NO_CLAMP (2 << 22) -+# define R300_TX_FORMAT_SWAP_YUV (1 << 24) -+ - #define R300_TX_FORMAT2_0 0x4500 - #define R300_TX_OFFSET_0 0x4540 - # define R300_ENDIAN_SWAP_16_BIT (1 << 0) -@@ -3961,9 +4179,53 @@ - #define R300_US_OUT_FMT_2 0x46ac - #define R300_US_OUT_FMT_3 0x46b0 - #define R300_US_OUT_FMT_0 0x46a4 -+# define R300_OUT_FMT_C4_8 (0 << 0) -+# define R300_OUT_FMT_C4_10 (1 << 0) -+# define R300_OUT_FMT_C4_10_GAMMA (2 << 0) -+# define R300_OUT_FMT_C_16 (3 << 0) -+# define R300_OUT_FMT_C2_16 (4 << 0) -+# define R300_OUT_FMT_C4_16 (5 << 0) -+# define R300_OUT_FMT_C_16_MPEG (6 << 0) -+# define R300_OUT_FMT_C2_16_MPEG (7 << 0) -+# define R300_OUT_FMT_C2_4 (8 << 0) -+# define R300_OUT_FMT_C_3_3_2 (9 << 0) -+# define R300_OUT_FMT_C_6_5_6 (10 << 0) -+# define R300_OUT_FMT_C_11_11_10 (11 << 0) -+# define R300_OUT_FMT_C_10_11_11 (12 << 0) -+# define R300_OUT_FMT_C_2_10_10_10 (13 << 0) -+# define R300_OUT_FMT_UNUSED (15 << 0) -+# define R300_OUT_FMT_C_16_FP (16 << 0) -+# define R300_OUT_FMT_C2_16_FP (17 << 0) -+# define R300_OUT_FMT_C4_16_FP (18 << 0) -+# define R300_OUT_FMT_C_32_FP (19 << 0) -+# define R300_OUT_FMT_C2_32_FP (20 << 0) -+# define R300_OUT_FMT_C4_32_FP (21 << 0) -+# define R300_OUT_FMT_C0_SEL_ALPHA (0 << 8) -+# define R300_OUT_FMT_C0_SEL_RED (1 << 8) -+# define R300_OUT_FMT_C0_SEL_GREEN (2 << 8) -+# define R300_OUT_FMT_C0_SEL_BLUE (3 << 8) -+# define R300_OUT_FMT_C1_SEL_ALPHA (0 << 10) -+# define R300_OUT_FMT_C1_SEL_RED (1 << 10) -+# define R300_OUT_FMT_C1_SEL_GREEN (2 << 10) -+# define R300_OUT_FMT_C1_SEL_BLUE (3 << 10) -+# define R300_OUT_FMT_C2_SEL_ALPHA (0 << 12) -+# define R300_OUT_FMT_C2_SEL_RED (1 << 12) -+# define R300_OUT_FMT_C2_SEL_GREEN (2 << 12) -+# define R300_OUT_FMT_C2_SEL_BLUE (3 << 12) -+# define R300_OUT_FMT_C3_SEL_ALPHA (0 << 14) -+# define R300_OUT_FMT_C3_SEL_RED (1 << 14) -+# define R300_OUT_FMT_C3_SEL_GREEN (2 << 14) -+# define R300_OUT_FMT_C3_SEL_BLUE (3 << 14) - #define R300_US_CONFIG 0x4600 -+# define R300_NLEVEL_SHIFT 0 -+# define R300_FIRST_TEX (1 << 3) -+# define R500_ZERO_TIMES_ANYTHING_EQUALS_ZERO (1 << 1) - #define R300_US_PIXSIZE 0x4604 - #define R300_US_CODE_OFFSET 0x4608 -+# define R300_ALU_CODE_OFFSET(x) (x << 0) -+# define R300_ALU_CODE_SIZE(x) (x << 6) -+# define R300_TEX_CODE_OFFSET(x) (x << 13) -+# define R300_TEX_CODE_SIZE(x) (x << 18) - #define R300_US_CODE_ADDR_0 0x4610 - #define R300_US_CODE_ADDR_1 0x4614 - #define R300_US_CODE_ADDR_2 0x4618 -@@ -3979,8 +4241,14 @@ - #define R300_FG_ALPHA_FUNC 0x4bd4 - - #define R300_RB3D_DSTCACHE_CTLSTAT 0x4e4c -+# define R300_DC_FLUSH_3D (2 << 0) -+# define R300_DC_FREE_3D (2 << 2) - #define R300_RB3D_ZCACHE_CTLSTAT 0x4f18 -+# define R300_ZC_FLUSH (1 << 0) -+# define R300_ZC_FREE (1 << 1) - #define R300_WAIT_UNTIL 0x1720 -+# define R300_WAIT_2D_IDLECLEAN (1 << 16) -+# define R300_WAIT_3D_IDLECLEAN (1 << 17) - #define R300_RB3D_ZSTENCILCNTL 0x4f04 - #define R300_RB3D_ZCACHE_CTLSTAT 0x4f18 - #define R300_RB3D_BW_CNTL 0x4f1c -@@ -4009,6 +4277,10 @@ - - #define R300_RB3D_AARESOLVE_CTL 0x4e88 - #define R300_RB3D_COLOR_CHANNEL_MASK 0x4e0c -+# define R300_BLUE_MASK_EN (1 << 0) -+# define R300_GREEN_MASK_EN (1 << 1) -+# define R300_RED_MASK_EN (1 << 2) -+# define R300_ALPHA_MASK_EN (1 << 3) - #define R300_RB3D_COLOR_CLEAR_VALUE 0x4e14 - #define R300_RB3D_DSTCACHE_CTLSTAT 0x4e4c - #define R300_RB3D_CCTL 0x4e00 -@@ -4017,9 +4289,524 @@ - #define R300_SC_EDGERULE 0x43a8 - #define R300_SC_SCISSOR0 0x43e0 - #define R300_SC_SCISSOR1 0x43e4 -+# define R300_SCISSOR_X_SHIFT 0 -+# define R300_SCISSOR_Y_SHIFT 13 - #define R300_SC_CLIP_0_A 0x43b0 - #define R300_SC_CLIP_0_B 0x43b4 -+# define R300_CLIP_X_SHIFT 0 -+# define R300_CLIP_Y_SHIFT 13 - #define R300_SC_CLIP_RULE 0x43d0 - #define R300_SC_SCREENDOOR 0x43e8 - -+/* R500 US has to be loaded through an index/data pair */ -+#define R500_GA_US_VECTOR_INDEX 0x4250 -+# define R500_US_VECTOR_INDEX(x) (x << 0) -+# define R500_US_VECTOR_TYPE_INST (0 << 16) -+# define R500_US_VECTOR_TYPE_CONST (1 << 16) -+# define R500_US_VECTOR_CLAMP (1 << 17) -+#define R500_GA_US_VECTOR_DATA 0x4254 -+ -+/* -+ * The R500 unified shader (US) registers come in banks of 512 each, one -+ * for each instruction slot in the shader. You can't touch them directly. -+ * R500_US_VECTOR_INDEX() sets the base instruction to modify; successive -+ * writes to R500_GA_US_VECTOR_DATA autoincrement the index after the -+ * instruction is fully specified. -+ */ -+#define R500_US_ALU_ALPHA_INST_0 0xa800 -+# define R500_ALPHA_OP_MAD 0 -+# define R500_ALPHA_OP_DP 1 -+# define R500_ALPHA_OP_MIN 2 -+# define R500_ALPHA_OP_MAX 3 -+/* #define R500_ALPHA_OP_RESERVED 4 */ -+# define R500_ALPHA_OP_CND 5 -+# define R500_ALPHA_OP_CMP 6 -+# define R500_ALPHA_OP_FRC 7 -+# define R500_ALPHA_OP_EX2 8 -+# define R500_ALPHA_OP_LN2 9 -+# define R500_ALPHA_OP_RCP 10 -+# define R500_ALPHA_OP_RSQ 11 -+# define R500_ALPHA_OP_SIN 12 -+# define R500_ALPHA_OP_COS 13 -+# define R500_ALPHA_OP_MDH 14 -+# define R500_ALPHA_OP_MDV 15 -+# define R500_ALPHA_ADDRD(x) (x << 4) -+# define R500_ALPHA_ADDRD_REL (1 << 11) -+# define R500_ALPHA_SEL_A_SRC0 (0 << 12) -+# define R500_ALPHA_SEL_A_SRC1 (1 << 12) -+# define R500_ALPHA_SEL_A_SRC2 (2 << 12) -+# define R500_ALPHA_SEL_A_SRCP (3 << 12) -+# define R500_ALPHA_SWIZ_A_R (0 << 14) -+# define R500_ALPHA_SWIZ_A_G (1 << 14) -+# define R500_ALPHA_SWIZ_A_B (2 << 14) -+# define R500_ALPHA_SWIZ_A_A (3 << 14) -+# define R500_ALPHA_SWIZ_A_0 (4 << 14) -+# define R500_ALPHA_SWIZ_A_HALF (5 << 14) -+# define R500_ALPHA_SWIZ_A_1 (6 << 14) -+/* #define R500_ALPHA_SWIZ_A_UNUSED (7 << 14) */ -+# define R500_ALPHA_MOD_A_NOP (0 << 17) -+# define R500_ALPHA_MOD_A_NEG (1 << 17) -+# define R500_ALPHA_MOD_A_ABS (2 << 17) -+# define R500_ALPHA_MOD_A_NAB (3 << 17) -+# define R500_ALPHA_SEL_B_SRC0 (0 << 19) -+# define R500_ALPHA_SEL_B_SRC1 (1 << 19) -+# define R500_ALPHA_SEL_B_SRC2 (2 << 19) -+# define R500_ALPHA_SEL_B_SRCP (3 << 19) -+# define R500_ALPHA_SWIZ_B_R (0 << 21) -+# define R500_ALPHA_SWIZ_B_G (1 << 21) -+# define R500_ALPHA_SWIZ_B_B (2 << 21) -+# define R500_ALPHA_SWIZ_B_A (3 << 21) -+# define R500_ALPHA_SWIZ_B_0 (4 << 21) -+# define R500_ALPHA_SWIZ_B_HALF (5 << 21) -+# define R500_ALPHA_SWIZ_B_1 (6 << 21) -+/* #define R500_ALPHA_SWIZ_B_UNUSED (7 << 21) */ -+# define R500_ALPHA_MOD_B_NOP (0 << 24) -+# define R500_ALPHA_MOD_B_NEG (1 << 24) -+# define R500_ALPHA_MOD_B_ABS (2 << 24) -+# define R500_ALPHA_MOD_B_NAB (3 << 24) -+# define R500_ALPHA_OMOD_IDENTITY (0 << 26) -+# define R500_ALPHA_OMOD_MUL_2 (1 << 26) -+# define R500_ALPHA_OMOD_MUL_4 (2 << 26) -+# define R500_ALPHA_OMOD_MUL_8 (3 << 26) -+# define R500_ALPHA_OMOD_DIV_2 (4 << 26) -+# define R500_ALPHA_OMOD_DIV_4 (5 << 26) -+# define R500_ALPHA_OMOD_DIV_8 (6 << 26) -+# define R500_ALPHA_OMOD_DISABLE (7 << 26) -+# define R500_ALPHA_TARGET(x) (x << 29) -+# define R500_ALPHA_W_OMASK (1 << 31) -+#define R500_US_ALU_ALPHA_ADDR_0 0x9800 -+# define R500_ALPHA_ADDR0(x) (x << 0) -+# define R500_ALPHA_ADDR0_CONST (1 << 8) -+# define R500_ALPHA_ADDR0_REL (1 << 9) -+# define R500_ALPHA_ADDR1(x) (x << 10) -+# define R500_ALPHA_ADDR1_CONST (1 << 18) -+# define R500_ALPHA_ADDR1_REL (1 << 19) -+# define R500_ALPHA_ADDR2(x) (x << 20) -+# define R500_ALPHA_ADDR2_CONST (1 << 28) -+# define R500_ALPHA_ADDR2_REL (1 << 29) -+# define R500_ALPHA_SRCP_OP_1_MINUS_2A0 (0 << 30) -+# define R500_ALPHA_SRCP_OP_A1_MINUS_A0 (1 << 30) -+# define R500_ALPHA_SRCP_OP_A1_PLUS_A0 (2 << 30) -+# define R500_ALPHA_SRCP_OP_1_PLUS_A0 (3 << 30) -+#define R500_US_ALU_RGBA_INST_0 0xb000 -+# define R500_ALU_RGBA_OP_MAD (0 << 0) -+# define R500_ALU_RGBA_OP_DP3 (1 << 0) -+# define R500_ALU_RGBA_OP_DP4 (2 << 0) -+# define R500_ALU_RGBA_OP_D2A (3 << 0) -+# define R500_ALU_RGBA_OP_MIN (4 << 0) -+# define R500_ALU_RGBA_OP_MAX (5 << 0) -+/* #define R500_ALU_RGBA_OP_RESERVED (6 << 0) */ -+# define R500_ALU_RGBA_OP_CND (7 << 0) -+# define R500_ALU_RGBA_OP_CMP (8 << 0) -+# define R500_ALU_RGBA_OP_FRC (9 << 0) -+# define R500_ALU_RGBA_OP_SOP (10 << 0) -+# define R500_ALU_RGBA_OP_MDH (11 << 0) -+# define R500_ALU_RGBA_OP_MDV (12 << 0) -+# define R500_ALU_RGBA_ADDRD(x) (x << 4) -+# define R500_ALU_RGBA_ADDRD_REL (1 << 11) -+# define R500_ALU_RGBA_SEL_C_SRC0 (0 << 12) -+# define R500_ALU_RGBA_SEL_C_SRC1 (1 << 12) -+# define R500_ALU_RGBA_SEL_C_SRC2 (2 << 12) -+# define R500_ALU_RGBA_SEL_C_SRCP (3 << 12) -+# define R500_ALU_RGBA_R_SWIZ_R (0 << 14) -+# define R500_ALU_RGBA_R_SWIZ_G (1 << 14) -+# define R500_ALU_RGBA_R_SWIZ_B (2 << 14) -+# define R500_ALU_RGBA_R_SWIZ_A (3 << 14) -+# define R500_ALU_RGBA_R_SWIZ_0 (4 << 14) -+# define R500_ALU_RGBA_R_SWIZ_HALF (5 << 14) -+# define R500_ALU_RGBA_R_SWIZ_1 (6 << 14) -+/* #define R500_ALU_RGBA_R_SWIZ_UNUSED (7 << 14) */ -+# define R500_ALU_RGBA_G_SWIZ_R (0 << 17) -+# define R500_ALU_RGBA_G_SWIZ_G (1 << 17) -+# define R500_ALU_RGBA_G_SWIZ_B (2 << 17) -+# define R500_ALU_RGBA_G_SWIZ_A (3 << 17) -+# define R500_ALU_RGBA_G_SWIZ_0 (4 << 17) -+# define R500_ALU_RGBA_G_SWIZ_HALF (5 << 17) -+# define R500_ALU_RGBA_G_SWIZ_1 (6 << 17) -+/* #define R500_ALU_RGBA_G_SWIZ_UNUSED (7 << 17) */ -+# define R500_ALU_RGBA_B_SWIZ_R (0 << 20) -+# define R500_ALU_RGBA_B_SWIZ_G (1 << 20) -+# define R500_ALU_RGBA_B_SWIZ_B (2 << 20) -+# define R500_ALU_RGBA_B_SWIZ_A (3 << 20) -+# define R500_ALU_RGBA_B_SWIZ_0 (4 << 20) -+# define R500_ALU_RGBA_B_SWIZ_HALF (5 << 20) -+# define R500_ALU_RGBA_B_SWIZ_1 (6 << 20) -+/* #define R500_ALU_RGBA_B_SWIZ_UNUSED (7 << 20) */ -+# define R500_ALU_RGBA_MOD_C_NOP (0 << 23) -+# define R500_ALU_RGBA_MOD_C_NEG (1 << 23) -+# define R500_ALU_RGBA_MOD_C_ABS (2 << 23) -+# define R500_ALU_RGBA_MOD_C_NAB (3 << 23) -+# define R500_ALU_RGBA_ALPHA_SEL_C_SRC0 (0 << 25) -+# define R500_ALU_RGBA_ALPHA_SEL_C_SRC1 (1 << 25) -+# define R500_ALU_RGBA_ALPHA_SEL_C_SRC2 (2 << 25) -+# define R500_ALU_RGBA_ALPHA_SEL_C_SRCP (3 << 25) -+# define R500_ALU_RGBA_A_SWIZ_R (0 << 27) -+# define R500_ALU_RGBA_A_SWIZ_G (1 << 27) -+# define R500_ALU_RGBA_A_SWIZ_B (2 << 27) -+# define R500_ALU_RGBA_A_SWIZ_A (3 << 27) -+# define R500_ALU_RGBA_A_SWIZ_0 (4 << 27) -+# define R500_ALU_RGBA_A_SWIZ_HALF (5 << 27) -+# define R500_ALU_RGBA_A_SWIZ_1 (6 << 27) -+/* #define R500_ALU_RGBA_A_SWIZ_UNUSED (7 << 27) */ -+# define R500_ALU_RGBA_ALPHA_MOD_C_NOP (0 << 30) -+# define R500_ALU_RGBA_ALPHA_MOD_C_NEG (1 << 30) -+# define R500_ALU_RGBA_ALPHA_MOD_C_ABS (2 << 30) -+# define R500_ALU_RGBA_ALPHA_MOD_C_NAB (3 << 30) -+#define R500_US_ALU_RGB_INST_0 0xa000 -+# define R500_ALU_RGB_SEL_A_SRC0 (0 << 0) -+# define R500_ALU_RGB_SEL_A_SRC1 (1 << 0) -+# define R500_ALU_RGB_SEL_A_SRC2 (2 << 0) -+# define R500_ALU_RGB_SEL_A_SRCP (3 << 0) -+# define R500_ALU_RGB_R_SWIZ_A_R (0 << 2) -+# define R500_ALU_RGB_R_SWIZ_A_G (1 << 2) -+# define R500_ALU_RGB_R_SWIZ_A_B (2 << 2) -+# define R500_ALU_RGB_R_SWIZ_A_A (3 << 2) -+# define R500_ALU_RGB_R_SWIZ_A_0 (4 << 2) -+# define R500_ALU_RGB_R_SWIZ_A_HALF (5 << 2) -+# define R500_ALU_RGB_R_SWIZ_A_1 (6 << 2) -+/* #define R500_ALU_RGB_R_SWIZ_A_UNUSED (7 << 2) */ -+# define R500_ALU_RGB_G_SWIZ_A_R (0 << 5) -+# define R500_ALU_RGB_G_SWIZ_A_G (1 << 5) -+# define R500_ALU_RGB_G_SWIZ_A_B (2 << 5) -+# define R500_ALU_RGB_G_SWIZ_A_A (3 << 5) -+# define R500_ALU_RGB_G_SWIZ_A_0 (4 << 5) -+# define R500_ALU_RGB_G_SWIZ_A_HALF (5 << 5) -+# define R500_ALU_RGB_G_SWIZ_A_1 (6 << 5) -+/* #define R500_ALU_RGB_G_SWIZ_A_UNUSED (7 << 5) */ -+# define R500_ALU_RGB_B_SWIZ_A_R (0 << 8) -+# define R500_ALU_RGB_B_SWIZ_A_G (1 << 8) -+# define R500_ALU_RGB_B_SWIZ_A_B (2 << 8) -+# define R500_ALU_RGB_B_SWIZ_A_A (3 << 8) -+# define R500_ALU_RGB_B_SWIZ_A_0 (4 << 8) -+# define R500_ALU_RGB_B_SWIZ_A_HALF (5 << 8) -+# define R500_ALU_RGB_B_SWIZ_A_1 (6 << 8) -+/* #define R500_ALU_RGB_B_SWIZ_A_UNUSED (7 << 8) */ -+# define R500_ALU_RGB_MOD_A_NOP (0 << 11) -+# define R500_ALU_RGB_MOD_A_NEG (1 << 11) -+# define R500_ALU_RGB_MOD_A_ABS (2 << 11) -+# define R500_ALU_RGB_MOD_A_NAB (3 << 11) -+# define R500_ALU_RGB_SEL_B_SRC0 (0 << 13) -+# define R500_ALU_RGB_SEL_B_SRC1 (1 << 13) -+# define R500_ALU_RGB_SEL_B_SRC2 (2 << 13) -+# define R500_ALU_RGB_SEL_B_SRCP (3 << 13) -+# define R500_ALU_RGB_R_SWIZ_B_R (0 << 15) -+# define R500_ALU_RGB_R_SWIZ_B_G (1 << 15) -+# define R500_ALU_RGB_R_SWIZ_B_B (2 << 15) -+# define R500_ALU_RGB_R_SWIZ_B_A (3 << 15) -+# define R500_ALU_RGB_R_SWIZ_B_0 (4 << 15) -+# define R500_ALU_RGB_R_SWIZ_B_HALF (5 << 15) -+# define R500_ALU_RGB_R_SWIZ_B_1 (6 << 15) -+/* #define R500_ALU_RGB_R_SWIZ_B_UNUSED (7 << 15) */ -+# define R500_ALU_RGB_G_SWIZ_B_R (0 << 18) -+# define R500_ALU_RGB_G_SWIZ_B_G (1 << 18) -+# define R500_ALU_RGB_G_SWIZ_B_B (2 << 18) -+# define R500_ALU_RGB_G_SWIZ_B_A (3 << 18) -+# define R500_ALU_RGB_G_SWIZ_B_0 (4 << 18) -+# define R500_ALU_RGB_G_SWIZ_B_HALF (5 << 18) -+# define R500_ALU_RGB_G_SWIZ_B_1 (6 << 18) -+/* #define R500_ALU_RGB_G_SWIZ_B_UNUSED (7 << 18) */ -+# define R500_ALU_RGB_B_SWIZ_B_R (0 << 21) -+# define R500_ALU_RGB_B_SWIZ_B_G (1 << 21) -+# define R500_ALU_RGB_B_SWIZ_B_B (2 << 21) -+# define R500_ALU_RGB_B_SWIZ_B_A (3 << 21) -+# define R500_ALU_RGB_B_SWIZ_B_0 (4 << 21) -+# define R500_ALU_RGB_B_SWIZ_B_HALF (5 << 21) -+# define R500_ALU_RGB_B_SWIZ_B_1 (6 << 21) -+/* #define R500_ALU_RGB_B_SWIZ_B_UNUSED (7 << 21) */ -+# define R500_ALU_RGB_MOD_B_NOP (0 << 24) -+# define R500_ALU_RGB_MOD_B_NEG (1 << 24) -+# define R500_ALU_RGB_MOD_B_ABS (2 << 24) -+# define R500_ALU_RGB_MOD_B_NAB (3 << 24) -+# define R500_ALU_RGB_OMOD_IDENTITY (0 << 26) -+# define R500_ALU_RGB_OMOD_MUL_2 (1 << 26) -+# define R500_ALU_RGB_OMOD_MUL_4 (2 << 26) -+# define R500_ALU_RGB_OMOD_MUL_8 (3 << 26) -+# define R500_ALU_RGB_OMOD_DIV_2 (4 << 26) -+# define R500_ALU_RGB_OMOD_DIV_4 (5 << 26) -+# define R500_ALU_RGB_OMOD_DIV_8 (6 << 26) -+# define R500_ALU_RGB_OMOD_DISABLE (7 << 26) -+# define R500_ALU_RGB_TARGET(x) (x << 29) -+# define R500_ALU_RGB_WMASK (1 << 31) -+#define R500_US_ALU_RGB_ADDR_0 0x9000 -+# define R500_RGB_ADDR0(x) (x << 0) -+# define R500_RGB_ADDR0_CONST (1 << 8) -+# define R500_RGB_ADDR0_REL (1 << 9) -+# define R500_RGB_ADDR1(x) (x << 10) -+# define R500_RGB_ADDR1_CONST (1 << 18) -+# define R500_RGB_ADDR1_REL (1 << 19) -+# define R500_RGB_ADDR2(x) (x << 20) -+# define R500_RGB_ADDR2_CONST (1 << 28) -+# define R500_RGB_ADDR2_REL (1 << 29) -+# define R500_RGB_SRCP_OP_1_MINUS_2RGB0 (0 << 30) -+# define R500_RGB_SRCP_OP_RGB1_MINUS_RGB0 (1 << 30) -+# define R500_RGB_SRCP_OP_RGB1_PLUS_RGB0 (2 << 30) -+# define R500_RGB_SRCP_OP_1_PLUS_RGB0 (3 << 30) -+#define R500_US_CMN_INST_0 0xb800 -+# define R500_INST_TYPE_ALU (0 << 0) -+# define R500_INST_TYPE_OUT (1 << 0) -+# define R500_INST_TYPE_FC (2 << 0) -+# define R500_INST_TYPE_TEX (3 << 0) -+# define R500_INST_TEX_SEM_WAIT (1 << 2) -+# define R500_INST_RGB_PRED_SEL_NONE (0 << 3) -+# define R500_INST_RGB_PRED_SEL_RGBA (1 << 3) -+# define R500_INST_RGB_PRED_SEL_RRRR (2 << 3) -+# define R500_INST_RGB_PRED_SEL_GGGG (3 << 3) -+# define R500_INST_RGB_PRED_SEL_BBBB (4 << 3) -+# define R500_INST_RGB_PRED_SEL_AAAA (5 << 3) -+# define R500_INST_RGB_PRED_INV (1 << 6) -+# define R500_INST_WRITE_INACTIVE (1 << 7) -+# define R500_INST_LAST (1 << 8) -+# define R500_INST_NOP (1 << 9) -+# define R500_INST_ALU_WAIT (1 << 10) -+# define R500_INST_RGB_WMASK_R (1 << 11) -+# define R500_INST_RGB_WMASK_G (1 << 12) -+# define R500_INST_RGB_WMASK_B (1 << 13) -+# define R500_INST_ALPHA_WMASK (1 << 14) -+# define R500_INST_RGB_OMASK_R (1 << 15) -+# define R500_INST_RGB_OMASK_G (1 << 16) -+# define R500_INST_RGB_OMASK_B (1 << 17) -+# define R500_INST_ALPHA_OMASK (1 << 18) -+# define R500_INST_RGB_CLAMP (1 << 19) -+# define R500_INST_ALPHA_CLAMP (1 << 20) -+# define R500_INST_ALU_RESULT_SEL (1 << 21) -+# define R500_INST_ALPHA_PRED_INV (1 << 22) -+# define R500_INST_ALU_RESULT_OP_EQ (0 << 23) -+# define R500_INST_ALU_RESULT_OP_LT (1 << 23) -+# define R500_INST_ALU_RESULT_OP_GE (2 << 23) -+# define R500_INST_ALU_RESULT_OP_NE (3 << 23) -+# define R500_INST_ALPHA_PRED_SEL_NONE (0 << 25) -+# define R500_INST_ALPHA_PRED_SEL_RGBA (1 << 25) -+# define R500_INST_ALPHA_PRED_SEL_RRRR (2 << 25) -+# define R500_INST_ALPHA_PRED_SEL_GGGG (3 << 25) -+# define R500_INST_ALPHA_PRED_SEL_BBBB (4 << 25) -+# define R500_INST_ALPHA_PRED_SEL_AAAA (5 << 25) -+/* XXX next four are kind of guessed */ -+# define R500_INST_STAT_WE_R (1 << 28) -+# define R500_INST_STAT_WE_G (1 << 29) -+# define R500_INST_STAT_WE_B (1 << 30) -+# define R500_INST_STAT_WE_A (1 << 31) -+/* note that these are 8 bit lengths, despite the offsets, at least for R500 */ -+#define R500_US_CODE_ADDR 0x4630 -+# define R500_US_CODE_START_ADDR(x) (x << 0) -+# define R500_US_CODE_END_ADDR(x) (x << 16) -+#define R500_US_CODE_OFFSET 0x4638 -+# define R500_US_CODE_OFFSET_ADDR(x) (x << 0) -+#define R500_US_CODE_RANGE 0x4634 -+# define R500_US_CODE_RANGE_ADDR(x) (x << 0) -+# define R500_US_CODE_RANGE_SIZE(x) (x << 16) -+#define R500_US_CONFIG 0x4600 -+# define R500_ZERO_TIMES_ANYTHING_EQUALS_ZERO (1 << 1) -+#define R500_US_FC_ADDR_0 0xa000 -+# define R500_FC_BOOL_ADDR(x) (x << 0) -+# define R500_FC_INT_ADDR(x) (x << 8) -+# define R500_FC_JUMP_ADDR(x) (x << 16) -+# define R500_FC_JUMP_GLOBAL (1 << 31) -+#define R500_US_FC_BOOL_CONST 0x4620 -+# define R500_FC_KBOOL(x) (x) -+#define R500_US_FC_CTRL 0x4624 -+# define R500_FC_TEST_EN (1 << 30) -+# define R500_FC_FULL_FC_EN (1 << 31) -+#define R500_US_FC_INST_0 0x9800 -+# define R500_FC_OP_JUMP (0 << 0) -+# define R500_FC_OP_LOOP (1 << 0) -+# define R500_FC_OP_ENDLOOP (2 << 0) -+# define R500_FC_OP_REP (3 << 0) -+# define R500_FC_OP_ENDREP (4 << 0) -+# define R500_FC_OP_BREAKLOOP (5 << 0) -+# define R500_FC_OP_BREAKREP (6 << 0) -+# define R500_FC_OP_CONTINUE (7 << 0) -+# define R500_FC_B_ELSE (1 << 4) -+# define R500_FC_JUMP_ANY (1 << 5) -+# define R500_FC_A_OP_NONE (0 << 6) -+# define R500_FC_A_OP_POP (1 << 6) -+# define R500_FC_A_OP_PUSH (2 << 6) -+# define R500_FC_JUMP_FUNC(x) (x << 8) -+# define R500_FC_B_POP_CNT(x) (x << 16) -+# define R500_FC_B_OP0_NONE (0 << 24) -+# define R500_FC_B_OP0_DECR (1 << 24) -+# define R500_FC_B_OP0_INCR (2 << 24) -+# define R500_FC_B_OP1_DECR (0 << 26) -+# define R500_FC_B_OP1_NONE (1 << 26) -+# define R500_FC_B_OP1_INCR (2 << 26) -+# define R500_FC_IGNORE_UNCOVERED (1 << 28) -+#define R500_US_FC_INT_CONST_0 0x4c00 -+# define R500_FC_INT_CONST_KR(x) (x << 0) -+# define R500_FC_INT_CONST_KG(x) (x << 8) -+# define R500_FC_INT_CONST_KB(x) (x << 16) -+/* _0 through _15 */ -+#define R500_US_FORMAT0_0 0x4640 -+# define R500_FORMAT_TXWIDTH(x) (x << 0) -+# define R500_FORMAT_TXHEIGHT(x) (x << 11) -+# define R500_FORMAT_TXDEPTH(x) (x << 22) -+/* _0 through _3 */ -+#define R500_US_OUT_FMT_0 0x46a4 -+# define R500_OUT_FMT_C4_8 (0 << 0) -+# define R500_OUT_FMT_C4_10 (1 << 0) -+# define R500_OUT_FMT_C4_10_GAMMA (2 << 0) -+# define R500_OUT_FMT_C_16 (3 << 0) -+# define R500_OUT_FMT_C2_16 (4 << 0) -+# define R500_OUT_FMT_C4_16 (5 << 0) -+# define R500_OUT_FMT_C_16_MPEG (6 << 0) -+# define R500_OUT_FMT_C2_16_MPEG (7 << 0) -+# define R500_OUT_FMT_C2_4 (8 << 0) -+# define R500_OUT_FMT_C_3_3_2 (9 << 0) -+# define R500_OUT_FMT_C_6_5_6 (10 << 0) -+# define R500_OUT_FMT_C_11_11_10 (11 << 0) -+# define R500_OUT_FMT_C_10_11_11 (12 << 0) -+# define R500_OUT_FMT_C_2_10_10_10 (13 << 0) -+/* #define R500_OUT_FMT_RESERVED (14 << 0) */ -+# define R500_OUT_FMT_UNUSED (15 << 0) -+# define R500_OUT_FMT_C_16_FP (16 << 0) -+# define R500_OUT_FMT_C2_16_FP (17 << 0) -+# define R500_OUT_FMT_C4_16_FP (18 << 0) -+# define R500_OUT_FMT_C_32_FP (19 << 0) -+# define R500_OUT_FMT_C2_32_FP (20 << 0) -+# define R500_OUT_FMT_C4_32_FP (21 << 0) -+# define R500_C0_SEL_A (0 << 8) -+# define R500_C0_SEL_R (1 << 8) -+# define R500_C0_SEL_G (2 << 8) -+# define R500_C0_SEL_B (3 << 8) -+# define R500_C1_SEL_A (0 << 10) -+# define R500_C1_SEL_R (1 << 10) -+# define R500_C1_SEL_G (2 << 10) -+# define R500_C1_SEL_B (3 << 10) -+# define R500_C2_SEL_A (0 << 12) -+# define R500_C2_SEL_R (1 << 12) -+# define R500_C2_SEL_G (2 << 12) -+# define R500_C2_SEL_B (3 << 12) -+# define R500_C3_SEL_A (0 << 14) -+# define R500_C3_SEL_R (1 << 14) -+# define R500_C3_SEL_G (2 << 14) -+# define R500_C3_SEL_B (3 << 14) -+# define R500_OUT_SIGN(x) (x << 16) -+# define R500_ROUND_ADJ (1 << 20) -+#define R500_US_PIXSIZE 0x4604 -+# define R500_PIX_SIZE(x) (x) -+#define R500_US_TEX_ADDR_0 0x9800 -+# define R500_TEX_SRC_ADDR(x) (x << 0) -+# define R500_TEX_SRC_ADDR_REL (1 << 7) -+# define R500_TEX_SRC_S_SWIZ_R (0 << 8) -+# define R500_TEX_SRC_S_SWIZ_G (1 << 8) -+# define R500_TEX_SRC_S_SWIZ_B (2 << 8) -+# define R500_TEX_SRC_S_SWIZ_A (3 << 8) -+# define R500_TEX_SRC_T_SWIZ_R (0 << 10) -+# define R500_TEX_SRC_T_SWIZ_G (1 << 10) -+# define R500_TEX_SRC_T_SWIZ_B (2 << 10) -+# define R500_TEX_SRC_T_SWIZ_A (3 << 10) -+# define R500_TEX_SRC_R_SWIZ_R (0 << 12) -+# define R500_TEX_SRC_R_SWIZ_G (1 << 12) -+# define R500_TEX_SRC_R_SWIZ_B (2 << 12) -+# define R500_TEX_SRC_R_SWIZ_A (3 << 12) -+# define R500_TEX_SRC_Q_SWIZ_R (0 << 14) -+# define R500_TEX_SRC_Q_SWIZ_G (1 << 14) -+# define R500_TEX_SRC_Q_SWIZ_B (2 << 14) -+# define R500_TEX_SRC_Q_SWIZ_A (3 << 14) -+# define R500_TEX_DST_ADDR(x) (x << 16) -+# define R500_TEX_DST_ADDR_REL (1 << 23) -+# define R500_TEX_DST_R_SWIZ_R (0 << 24) -+# define R500_TEX_DST_R_SWIZ_G (1 << 24) -+# define R500_TEX_DST_R_SWIZ_B (2 << 24) -+# define R500_TEX_DST_R_SWIZ_A (3 << 24) -+# define R500_TEX_DST_G_SWIZ_R (0 << 26) -+# define R500_TEX_DST_G_SWIZ_G (1 << 26) -+# define R500_TEX_DST_G_SWIZ_B (2 << 26) -+# define R500_TEX_DST_G_SWIZ_A (3 << 26) -+# define R500_TEX_DST_B_SWIZ_R (0 << 28) -+# define R500_TEX_DST_B_SWIZ_G (1 << 28) -+# define R500_TEX_DST_B_SWIZ_B (2 << 28) -+# define R500_TEX_DST_B_SWIZ_A (3 << 28) -+# define R500_TEX_DST_A_SWIZ_R (0 << 30) -+# define R500_TEX_DST_A_SWIZ_G (1 << 30) -+# define R500_TEX_DST_A_SWIZ_B (2 << 30) -+# define R500_TEX_DST_A_SWIZ_A (3 << 30) -+#define R500_US_TEX_ADDR_DXDY_0 0xa000 -+# define R500_DX_ADDR(x) (x << 0) -+# define R500_DX_ADDR_REL (1 << 7) -+# define R500_DX_S_SWIZ_R (0 << 8) -+# define R500_DX_S_SWIZ_G (1 << 8) -+# define R500_DX_S_SWIZ_B (2 << 8) -+# define R500_DX_S_SWIZ_A (3 << 8) -+# define R500_DX_T_SWIZ_R (0 << 10) -+# define R500_DX_T_SWIZ_G (1 << 10) -+# define R500_DX_T_SWIZ_B (2 << 10) -+# define R500_DX_T_SWIZ_A (3 << 10) -+# define R500_DX_R_SWIZ_R (0 << 12) -+# define R500_DX_R_SWIZ_G (1 << 12) -+# define R500_DX_R_SWIZ_B (2 << 12) -+# define R500_DX_R_SWIZ_A (3 << 12) -+# define R500_DX_Q_SWIZ_R (0 << 14) -+# define R500_DX_Q_SWIZ_G (1 << 14) -+# define R500_DX_Q_SWIZ_B (2 << 14) -+# define R500_DX_Q_SWIZ_A (3 << 14) -+# define R500_DY_ADDR(x) (x << 16) -+# define R500_DY_ADDR_REL (1 << 17) -+# define R500_DY_S_SWIZ_R (0 << 24) -+# define R500_DY_S_SWIZ_G (1 << 24) -+# define R500_DY_S_SWIZ_B (2 << 24) -+# define R500_DY_S_SWIZ_A (3 << 24) -+# define R500_DY_T_SWIZ_R (0 << 26) -+# define R500_DY_T_SWIZ_G (1 << 26) -+# define R500_DY_T_SWIZ_B (2 << 26) -+# define R500_DY_T_SWIZ_A (3 << 26) -+# define R500_DY_R_SWIZ_R (0 << 28) -+# define R500_DY_R_SWIZ_G (1 << 28) -+# define R500_DY_R_SWIZ_B (2 << 28) -+# define R500_DY_R_SWIZ_A (3 << 28) -+# define R500_DY_Q_SWIZ_R (0 << 30) -+# define R500_DY_Q_SWIZ_G (1 << 30) -+# define R500_DY_Q_SWIZ_B (2 << 30) -+# define R500_DY_Q_SWIZ_A (3 << 30) -+#define R500_US_TEX_INST_0 0x9000 -+# define R500_TEX_ID(x) (x << 16) -+# define R500_TEX_INST_NOP (0 << 22) -+# define R500_TEX_INST_LD (1 << 22) -+# define R500_TEX_INST_TEXKILL (2 << 22) -+# define R500_TEX_INST_PROJ (3 << 22) -+# define R500_TEX_INST_LODBIAS (4 << 22) -+# define R500_TEX_INST_LOD (5 << 22) -+# define R500_TEX_INST_DXDY (6 << 22) -+# define R500_TEX_SEM_ACQUIRE (1 << 25) -+# define R500_TEX_IGNORE_UNCOVERED (1 << 26) -+# define R500_TEX_UNSCALED (1 << 27) -+#define R500_US_W_FMT 0x46b4 -+# define R500_W_FMT_W0 (0 << 0) -+# define R500_W_FMT_W24 (1 << 0) -+# define R500_W_FMT_W24FP (2 << 0) -+# define R500_W_SRC_US (0 << 2) -+# define R500_W_SRC_RAS (1 << 2) -+ -+#define R500_GA_US_VECTOR_INDEX 0x4250 -+#define R500_GA_US_VECTOR_DATA 0x4254 -+ -+#define R500_RS_INST_0 0x4320 -+#define R500_RS_INST_TEX_ID_SHIFT 0 -+#define R500_RS_INST_TEX_CN_WRITE (1 << 4) -+#define R500_RS_INST_TEX_ADDR_SHIFT 5 -+#define R500_RS_INST_COL_ID_SHIFT 12 -+#define R500_RS_INST_COL_CN_NO_WRITE (0 << 16) -+#define R500_RS_INST_COL_CN_WRITE (1 << 16) -+#define R500_RS_INST_COL_CN_WRITE_FBUFFER (2 << 16) -+#define R500_RS_INST_COL_CN_WRITE_BACKFACE (3 << 16) -+#define R500_RS_INST_COL_COL_ADDR_SHIFT 18 -+#define R500_RS_INST_TEX_ADJ (1 << 25) -+#define R500_RS_INST_W_CN (1 << 26) -+ -+#define R500_US_FC_CTRL 0x4624 -+#define R500_US_CODE_ADDR 0x4630 -+#define R500_US_CODE_RANGE 0x4634 -+#define R500_US_CODE_OFFSET 0x4638 -+ -+#define R500_RS_IP_0 0x4074 -+#define R500_RS_IP_PTR_K0 62 -+#define R500_RS_IP_PTR_K1 63 -+#define R500_RS_IP_TEX_PTR_S_SHIFT 0 -+#define R500_RS_IP_TEX_PTR_T_SHIFT 6 -+#define R500_RS_IP_TEX_PTR_R_SHIFT 12 -+#define R500_RS_IP_TEX_PTR_Q_SHIFT 18 -+#define R500_RS_IP_COL_PTR_SHIFT 24 -+#define R500_RS_IP_COL_FMT_SHIFT 27 -+#define R500_RS_IP_COL_FMT_RGBA (0<<27) -+#define R500_RS_IP_OFFSET_EN (1 << 31) -+ -+ - #endif -diff --git a/src/radeon_textured_video.c b/src/radeon_textured_video.c -new file mode 100644 -index 0000000..329a834 ---- /dev/null -+++ b/src/radeon_textured_video.c -@@ -0,0 +1,383 @@ -+/* -+ * Copyright 2008 Alex Deucher -+ * -+ * Permission is hereby granted, free of charge, to any person obtaining a -+ * copy of this software and associated documentation files (the "Software"), -+ * to deal in the Software without restriction, including without limitation -+ * the rights to use, copy, modify, merge, publish, distribute, sublicense, -+ * and/or sell copies of the Software, and to permit persons to whom the -+ * Software is furnished to do so, subject to the following conditions: -+ * -+ * The above copyright notice and this permission notice (including the next -+ * paragraph) shall be included in all copies or substantial portions of the -+ * Software. -+ * -+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR -+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, -+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL -+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER -+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, -+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE -+ * SOFTWARE. -+ * -+ * -+ * Based on radeon_exa_render.c and kdrive ati_video.c by Eric Anholt, et al. -+ * -+ */ -+ -+#ifdef HAVE_CONFIG_H -+#include "config.h" -+#endif -+ -+#include -+#include -+#include -+#include -+ -+#include "radeon.h" -+#include "radeon_reg.h" -+#include "radeon_macros.h" -+#include "radeon_probe.h" -+#include "radeon_video.h" -+ -+#include -+#include "fourcc.h" -+ -+#define IMAGE_MAX_WIDTH 2048 -+#define IMAGE_MAX_HEIGHT 2048 -+ -+static Bool -+RADEONTilingEnabled(ScrnInfoPtr pScrn, PixmapPtr pPix) -+{ -+ RADEONInfoPtr info = RADEONPTR(pScrn); -+ -+#ifdef USE_EXA -+ if (info->useEXA) { -+ if (info->tilingEnabled && exaGetPixmapOffset(pPix) == 0) -+ return TRUE; -+ else -+ return FALSE; -+ } else -+#endif -+ { -+ if (info->tilingEnabled) -+ return TRUE; -+ else -+ return FALSE; -+ } -+} -+ -+static __inline__ CARD32 F_TO_DW(float val) -+{ -+ union { -+ float f; -+ CARD32 l; -+ } tmp; -+ tmp.f = val; -+ return tmp.l; -+} -+ -+#define ACCEL_MMIO -+#define VIDEO_PREAMBLE() unsigned char *RADEONMMIO = info->MMIO -+#define BEGIN_VIDEO(n) RADEONWaitForFifo(pScrn, (n)) -+#define OUT_VIDEO_REG(reg, val) OUTREG(reg, val) -+#define OUT_VIDEO_REG_F(reg, val) OUTREG(reg, F_TO_DW(val)) -+#define FINISH_VIDEO() -+ -+#include "radeon_textured_videofuncs.c" -+ -+#undef ACCEL_MMIO -+#undef VIDEO_PREAMBLE -+#undef BEGIN_VIDEO -+#undef OUT_VIDEO_REG -+#undef FINISH_VIDEO -+ -+#ifdef XF86DRI -+ -+#define ACCEL_CP -+#define VIDEO_PREAMBLE() \ -+ RING_LOCALS; \ -+ RADEONCP_REFRESH(pScrn, info) -+#define BEGIN_VIDEO(n) BEGIN_RING(2*(n)) -+#define OUT_VIDEO_REG(reg, val) OUT_RING_REG(reg, val) -+#define FINISH_VIDEO() ADVANCE_RING() -+#define OUT_VIDEO_RING_F(x) OUT_RING(F_TO_DW(x)) -+ -+#include "radeon_textured_videofuncs.c" -+ -+#endif /* XF86DRI */ -+ -+static int -+RADEONPutImageTextured(ScrnInfoPtr pScrn, -+ short src_x, short src_y, -+ short drw_x, short drw_y, -+ short src_w, short src_h, -+ short drw_w, short drw_h, -+ int id, -+ unsigned char *buf, -+ short width, -+ short height, -+ Bool sync, -+ RegionPtr clipBoxes, -+ pointer data, -+ DrawablePtr pDraw) -+{ -+ ScreenPtr pScreen = pScrn->pScreen; -+ RADEONInfoPtr info = RADEONPTR(pScrn); -+ RADEONPortPrivPtr pPriv = (RADEONPortPrivPtr)data; -+ INT32 x1, x2, y1, y2; -+ int srcPitch, srcPitch2, dstPitch; -+ int s2offset, s3offset, tmp; -+ int top, left, npixels, nlines, size; -+ BoxRec dstBox; -+ int dst_width = width, dst_height = height; -+ -+ /* make the compiler happy */ -+ s2offset = s3offset = srcPitch2 = 0; -+ -+ /* Clip */ -+ x1 = src_x; -+ x2 = src_x + src_w; -+ y1 = src_y; -+ y2 = src_y + src_h; -+ -+ dstBox.x1 = drw_x; -+ dstBox.x2 = drw_x + drw_w; -+ dstBox.y1 = drw_y; -+ dstBox.y2 = drw_y + drw_h; -+ -+ if (!xf86XVClipVideoHelper(&dstBox, &x1, &x2, &y1, &y2, clipBoxes, width, height)) -+ return Success; -+ -+ src_w = (x2 - x1) >> 16; -+ src_h = (y2 - y1) >> 16; -+ drw_w = dstBox.x2 - dstBox.x1; -+ drw_h = dstBox.y2 - dstBox.y1; -+ -+ if ((x1 >= x2) || (y1 >= y2)) -+ return Success; -+ -+ switch(id) { -+ case FOURCC_YV12: -+ case FOURCC_I420: -+ dstPitch = ((dst_width << 1) + 15) & ~15; -+ srcPitch = (width + 3) & ~3; -+ srcPitch2 = ((width >> 1) + 3) & ~3; -+ size = dstPitch * dst_height; -+ break; -+ case FOURCC_UYVY: -+ case FOURCC_YUY2: -+ default: -+ dstPitch = ((dst_width << 1) + 15) & ~15; -+ srcPitch = (width << 1); -+ srcPitch2 = 0; -+ size = dstPitch * dst_height; -+ break; -+ } -+ -+#ifdef XF86DRI -+ if (info->directRenderingEnabled && info->DMAForXv) -+ /* The upload blit only supports multiples of 64 bytes */ -+ dstPitch = (dstPitch + 63) & ~63; -+ else -+#endif -+ dstPitch = (dstPitch + 15) & ~15; -+ -+ if (pPriv->video_memory != NULL && size != pPriv->size) { -+ RADEONFreeMemory(pScrn, pPriv->video_memory); -+ pPriv->video_memory = NULL; -+ } -+ -+ if (pPriv->video_memory == NULL) { -+ pPriv->video_offset = RADEONAllocateMemory(pScrn, -+ &pPriv->video_memory, -+ size * 2); -+ if (pPriv->video_offset == 0) -+ return BadAlloc; -+ } -+ -+ if (pDraw->type == DRAWABLE_WINDOW) -+ pPriv->pPixmap = (*pScreen->GetWindowPixmap)((WindowPtr)pDraw); -+ else -+ pPriv->pPixmap = (PixmapPtr)pDraw; -+ -+#ifdef USE_EXA -+ if (info->useEXA) { -+ /* Force the pixmap into framebuffer so we can draw to it. */ -+ exaMoveInPixmap(pPriv->pPixmap); -+ } -+#endif -+ -+ if (!info->useEXA && -+ (((char *)pPriv->pPixmap->devPrivate.ptr < (char *)info->FB) || -+ ((char *)pPriv->pPixmap->devPrivate.ptr >= (char *)info->FB + -+ info->FbMapSize))) { -+ /* If the pixmap wasn't in framebuffer, then we have no way in XAA to -+ * force it there. So, we simply refuse to draw and fail. -+ */ -+ return BadAlloc; -+ } -+ -+ /* copy data */ -+ top = y1 >> 16; -+ left = (x1 >> 16) & ~1; -+ npixels = ((((x2 + 0xffff) >> 16) + 1) & ~1) - left; -+ -+ pPriv->src_offset = pPriv->video_offset + info->fbLocation; -+ pPriv->src_addr = (CARD8 *)(info->FB + pPriv->video_offset + (top * dstPitch)); -+ pPriv->src_pitch = dstPitch; -+ pPriv->size = size; -+ pPriv->pDraw = pDraw; -+ -+#if 0 -+ ErrorF("src_offset: 0x%x\n", pPriv->src_offset); -+ ErrorF("src_addr: 0x%x\n", pPriv->src_addr); -+ ErrorF("src_pitch: 0x%x\n", pPriv->src_pitch); -+#endif -+ -+ switch(id) { -+ case FOURCC_YV12: -+ case FOURCC_I420: -+ top &= ~1; -+ nlines = ((((y2 + 0xffff) >> 16) + 1) & ~1) - top; -+ s2offset = srcPitch * height; -+ s3offset = (srcPitch2 * (height >> 1)) + s2offset; -+ top &= ~1; -+ pPriv->src_addr += left << 1; -+ tmp = ((top >> 1) * srcPitch2) + (left >> 1); -+ s2offset += tmp; -+ s3offset += tmp; -+ if (id == FOURCC_I420) { -+ tmp = s2offset; -+ s2offset = s3offset; -+ s3offset = tmp; -+ } -+ RADEONCopyMungedData(pScrn, buf + (top * srcPitch) + left, -+ buf + s2offset, buf + s3offset, pPriv->src_addr, -+ srcPitch, srcPitch2, dstPitch, nlines, npixels); -+ break; -+ case FOURCC_UYVY: -+ case FOURCC_YUY2: -+ default: -+ nlines = ((y2 + 0xffff) >> 16) - top; -+ RADEONCopyData(pScrn, buf, pPriv->src_addr, srcPitch, dstPitch, nlines, npixels, 2); -+ break; -+ } -+ -+ /* update cliplist */ -+ if (!REGION_EQUAL(pScrn->pScreen, &pPriv->clip, clipBoxes)) { -+ REGION_COPY(pScrn->pScreen, &pPriv->clip, clipBoxes); -+ } -+ -+ pPriv->id = id; -+ pPriv->src_w = src_w; -+ pPriv->src_h = src_h; -+ pPriv->drw_x = drw_x; -+ pPriv->drw_y = drw_y; -+ pPriv->dst_w = drw_w; -+ pPriv->dst_h = drw_h; -+ pPriv->w = width; -+ pPriv->h = height; -+ -+#ifdef XF86DRI -+ if (info->directRenderingEnabled) -+ RADEONDisplayTexturedVideoCP(pScrn, pPriv); -+ else -+#endif -+ RADEONDisplayTexturedVideoMMIO(pScrn, pPriv); -+ -+ return Success; -+} -+ -+/* client libraries expect an encoding */ -+static XF86VideoEncodingRec DummyEncoding[1] = -+{ -+ { -+ 0, -+ "XV_IMAGE", -+ IMAGE_MAX_WIDTH, IMAGE_MAX_HEIGHT, -+ {1, 1} -+ } -+}; -+ -+#define NUM_FORMATS 3 -+ -+static XF86VideoFormatRec Formats[NUM_FORMATS] = -+{ -+ {15, TrueColor}, {16, TrueColor}, {24, TrueColor} -+}; -+ -+#define NUM_ATTRIBUTES 0 -+ -+static XF86AttributeRec Attributes[NUM_ATTRIBUTES] = -+{ -+}; -+ -+#define NUM_IMAGES 4 -+ -+static XF86ImageRec Images[NUM_IMAGES] = -+{ -+ XVIMAGE_YUY2, -+ XVIMAGE_YV12, -+ XVIMAGE_I420, -+ XVIMAGE_UYVY -+}; -+ -+XF86VideoAdaptorPtr -+RADEONSetupImageTexturedVideo(ScreenPtr pScreen) -+{ -+ RADEONPortPrivPtr pPortPriv; -+ XF86VideoAdaptorPtr adapt; -+ int i; -+ int num_texture_ports = 16; -+ -+ adapt = xcalloc(1, sizeof(XF86VideoAdaptorRec) + num_texture_ports * -+ (sizeof(RADEONPortPrivRec) + sizeof(DevUnion))); -+ if (adapt == NULL) -+ return NULL; -+ -+ adapt->type = XvWindowMask | XvInputMask | XvImageMask; -+ adapt->flags = 0; -+ adapt->name = "Radeon Textured Video"; -+ adapt->nEncodings = 1; -+ adapt->pEncodings = DummyEncoding; -+ adapt->nFormats = NUM_FORMATS; -+ adapt->pFormats = Formats; -+ adapt->nPorts = num_texture_ports; -+ adapt->pPortPrivates = (DevUnion*)(&adapt[1]); -+ -+ pPortPriv = -+ (RADEONPortPrivPtr)(&adapt->pPortPrivates[num_texture_ports]); -+ -+ adapt->nAttributes = NUM_ATTRIBUTES; -+ adapt->pAttributes = Attributes; -+ adapt->pImages = Images; -+ adapt->nImages = NUM_IMAGES; -+ adapt->PutVideo = NULL; -+ adapt->PutStill = NULL; -+ adapt->GetVideo = NULL; -+ adapt->GetStill = NULL; -+ adapt->StopVideo = RADEONStopVideo; -+ adapt->SetPortAttribute = RADEONSetPortAttribute; -+ adapt->GetPortAttribute = RADEONGetPortAttribute; -+ adapt->QueryBestSize = RADEONQueryBestSize; -+ adapt->PutImage = RADEONPutImageTextured; -+ adapt->ReputImage = NULL; -+ adapt->QueryImageAttributes = RADEONQueryImageAttributes; -+ -+ for (i = 0; i < num_texture_ports; i++) { -+ RADEONPortPrivPtr pPriv = &pPortPriv[i]; -+ -+ pPriv->textured = TRUE; -+ pPriv->videoStatus = 0; -+ pPriv->currentBuffer = 0; -+ pPriv->doubleBuffer = 0; -+ -+ /* gotta uninit this someplace, XXX: shouldn't be necessary for textured */ -+ REGION_NULL(pScreen, &pPriv->clip); -+ adapt->pPortPrivates[i].ptr = (pointer) (pPriv); -+ } -+ -+ return adapt; -+} -+ -diff --git a/src/radeon_textured_videofuncs.c b/src/radeon_textured_videofuncs.c -new file mode 100644 -index 0000000..e0f3bba ---- /dev/null -+++ b/src/radeon_textured_videofuncs.c -@@ -0,0 +1,596 @@ -+/* -+ * Copyright 2008 Alex Deucher -+ * -+ * Permission is hereby granted, free of charge, to any person obtaining a -+ * copy of this software and associated documentation files (the "Software"), -+ * to deal in the Software without restriction, including without limitation -+ * the rights to use, copy, modify, merge, publish, distribute, sublicense, -+ * and/or sell copies of the Software, and to permit persons to whom the -+ * Software is furnished to do so, subject to the following conditions: -+ * -+ * The above copyright notice and this permission notice (including the next -+ * paragraph) shall be included in all copies or substantial portions of the -+ * Software. -+ * -+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR -+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, -+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL -+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER -+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, -+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE -+ * SOFTWARE. -+ * -+ * -+ * Based on radeon_exa_render.c and kdrive ati_video.c by Eric Anholt, et al. -+ * -+ */ -+ -+#if defined(ACCEL_MMIO) && defined(ACCEL_CP) -+#error Cannot define both MMIO and CP acceleration! -+#endif -+ -+#if !defined(UNIXCPP) || defined(ANSICPP) -+#define FUNC_NAME_CAT(prefix,suffix) prefix##suffix -+#else -+#define FUNC_NAME_CAT(prefix,suffix) prefix/**/suffix -+#endif -+ -+#ifdef ACCEL_MMIO -+#define FUNC_NAME(prefix) FUNC_NAME_CAT(prefix,MMIO) -+#else -+#ifdef ACCEL_CP -+#define FUNC_NAME(prefix) FUNC_NAME_CAT(prefix,CP) -+#else -+#error No accel type defined! -+#endif -+#endif -+ -+#define VTX_DWORD_COUNT 4 -+ -+#ifdef ACCEL_CP -+ -+#define VTX_OUT(_dstX, _dstY, _srcX, _srcY) \ -+do { \ -+ OUT_VIDEO_RING_F(_dstX); \ -+ OUT_VIDEO_RING_F(_dstY); \ -+ OUT_VIDEO_RING_F(_srcX); \ -+ OUT_VIDEO_RING_F(_srcY); \ -+} while (0) -+ -+#else /* ACCEL_CP */ -+ -+#define VTX_OUT(_dstX, _dstY, _srcX, _srcY) \ -+do { \ -+ OUT_VIDEO_REG_F(RADEON_SE_PORT_DATA0, _dstX); \ -+ OUT_VIDEO_REG_F(RADEON_SE_PORT_DATA0, _dstY); \ -+ OUT_VIDEO_REG_F(RADEON_SE_PORT_DATA0, _srcX); \ -+ OUT_VIDEO_REG_F(RADEON_SE_PORT_DATA0, _srcY); \ -+} while (0) -+ -+#endif /* !ACCEL_CP */ -+ -+static void -+FUNC_NAME(RADEONDisplayTexturedVideo)(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv) -+{ -+ RADEONInfoPtr info = RADEONPTR(pScrn); -+ PixmapPtr pPixmap = pPriv->pPixmap; -+ CARD32 txformat; -+ CARD32 txfilter, txformat0, txformat1, txoffset, txpitch; -+ CARD32 dst_offset, dst_pitch, dst_format; -+ CARD32 txenable, colorpitch; -+ CARD32 blendcntl; -+ int dstxoff, dstyoff, pixel_shift; -+ VIDEO_PREAMBLE(); -+ -+ BoxPtr pBox = REGION_RECTS(&pPriv->clip); -+ int nBox = REGION_NUM_RECTS(&pPriv->clip); -+ -+ pixel_shift = pPixmap->drawable.bitsPerPixel >> 4; -+ -+#ifdef USE_EXA -+ if (info->useEXA) { -+ dst_offset = exaGetPixmapOffset(pPixmap) + info->fbLocation; -+ dst_pitch = exaGetPixmapPitch(pPixmap); -+ } else -+#endif -+ { -+ dst_offset = (pPixmap->devPrivate.ptr - info->FB) + -+ info->fbLocation + pScrn->fbOffset; -+ dst_pitch = pPixmap->devKind; -+ } -+ -+#ifdef COMPOSITE -+ dstxoff = -pPixmap->screen_x + pPixmap->drawable.x; -+ dstyoff = -pPixmap->screen_y + pPixmap->drawable.y; -+#else -+ dstxoff = 0; -+ dstyoff = 0; -+#endif -+ -+#if 0 -+ ErrorF("dst_offset: 0x%x\n", dst_offset); -+ ErrorF("dst_pitch: 0x%x\n", dst_pitch); -+ ErrorF("dstxoff: 0x%x\n", dstxoff); -+ ErrorF("dstyoff: 0x%x\n", dstyoff); -+ ErrorF("src_offset: 0x%x\n", pPriv->src_offset); -+ ErrorF("src_pitch: 0x%x\n", pPriv->src_pitch); -+#endif -+ -+ if (!info->XInited3D) -+ RADEONInit3DEngine(pScrn); -+ -+ /* we can probably improve this */ -+ BEGIN_VIDEO(2); -+ OUT_VIDEO_REG(RADEON_RB3D_DSTCACHE_CTLSTAT, RADEON_RB3D_DC_FLUSH); -+ /* We must wait for 3d to idle, in case source was just written as a dest. */ -+ OUT_VIDEO_REG(RADEON_WAIT_UNTIL, -+ RADEON_WAIT_HOST_IDLECLEAN | RADEON_WAIT_2D_IDLECLEAN | RADEON_WAIT_3D_IDLECLEAN); -+ FINISH_VIDEO(); -+ -+ if (IS_R300_VARIANT || IS_AVIVO_VARIANT) { -+ int has_tcl = (info->ChipFamily != CHIP_FAMILY_RS690 && info->ChipFamily != CHIP_FAMILY_RS400); -+ -+ switch (pPixmap->drawable.bitsPerPixel) { -+ case 16: -+ if (pPixmap->drawable.depth == 15) -+ dst_format = R300_COLORFORMAT_ARGB1555; -+ else -+ dst_format = R300_COLORFORMAT_RGB565; -+ break; -+ case 32: -+ dst_format = R300_COLORFORMAT_ARGB8888; -+ break; -+ default: -+ return; -+ } -+ -+ colorpitch = dst_pitch >> pixel_shift; -+ colorpitch |= dst_format; -+ -+ if (RADEONTilingEnabled(pScrn, pPixmap)) -+ colorpitch |= R300_COLORTILE; -+ -+ if (pPriv->id == FOURCC_UYVY) -+ txformat1 = R300_TX_FORMAT_YVYU422; -+ else -+ txformat1 = R300_TX_FORMAT_VYUY422; -+ -+ txformat1 |= R300_TX_FORMAT_YUV_TO_RGB_CLAMP; -+ -+ txformat0 = (((pPriv->w - 1) << R300_TXWIDTH_SHIFT) | -+ ((pPriv->h - 1) << R300_TXHEIGHT_SHIFT)); -+ -+ txformat0 |= R300_TXPITCH_EN; -+ -+ info->texW[0] = pPriv->w; -+ info->texH[0] = pPriv->h; -+ -+ txfilter = (R300_TX_CLAMP_S(R300_TX_CLAMP_CLAMP_LAST) | -+ R300_TX_CLAMP_T(R300_TX_CLAMP_CLAMP_LAST) | -+ R300_TX_MAG_FILTER_LINEAR | R300_TX_MIN_FILTER_LINEAR); -+ -+ /* pitch is in pixels */ -+ txpitch = pPriv->src_pitch / 2; -+ txpitch -= 1; -+ -+ txoffset = pPriv->src_offset; -+ -+ BEGIN_VIDEO(6); -+ OUT_VIDEO_REG(R300_TX_FILTER0_0, txfilter); -+ OUT_VIDEO_REG(R300_TX_FILTER1_0, 0); -+ OUT_VIDEO_REG(R300_TX_FORMAT0_0, txformat0); -+ OUT_VIDEO_REG(R300_TX_FORMAT1_0, txformat1); -+ OUT_VIDEO_REG(R300_TX_FORMAT2_0, txpitch); -+ OUT_VIDEO_REG(R300_TX_OFFSET_0, txoffset); -+ FINISH_VIDEO(); -+ -+ txenable = R300_TEX_0_ENABLE; -+ -+ /* setup the VAP */ -+ if (has_tcl) { -+ BEGIN_VIDEO(26); -+ OUT_VIDEO_REG(R300_VAP_CNTL_STATUS, 0); -+ OUT_VIDEO_REG(R300_VAP_PVS_STATE_FLUSH_REG, 0); -+ OUT_VIDEO_REG(R300_VAP_CNTL, ((6 << R300_PVS_NUM_SLOTS_SHIFT) | -+ (5 << R300_PVS_NUM_CNTLRS_SHIFT) | -+ (4 << R300_PVS_NUM_FPUS_SHIFT) | -+ (12 << R300_VF_MAX_VTX_NUM_SHIFT))); -+ } else { -+ BEGIN_VIDEO(8); -+ OUT_VIDEO_REG(R300_VAP_CNTL_STATUS, R300_PVS_BYPASS); -+ OUT_VIDEO_REG(R300_VAP_CNTL, ((10 << R300_PVS_NUM_SLOTS_SHIFT) | -+ (5 << R300_PVS_NUM_CNTLRS_SHIFT) | -+ (4 << R300_PVS_NUM_FPUS_SHIFT) | -+ (5 << R300_VF_MAX_VTX_NUM_SHIFT))); -+ } -+ -+ OUT_VIDEO_REG(R300_VAP_VTE_CNTL, R300_VTX_XY_FMT | R300_VTX_Z_FMT); -+ OUT_VIDEO_REG(R300_VAP_PSC_SGN_NORM_CNTL, 0); -+ -+ if (has_tcl) { -+ OUT_VIDEO_REG(R300_VAP_PROG_STREAM_CNTL_0, -+ ((R300_DATA_TYPE_FLOAT_2 << R300_DATA_TYPE_0_SHIFT) | -+ (0 << R300_SKIP_DWORDS_0_SHIFT) | -+ (0 << R300_DST_VEC_LOC_0_SHIFT) | -+ R300_SIGNED_0 | -+ (R300_DATA_TYPE_FLOAT_2 << R300_DATA_TYPE_1_SHIFT) | -+ (0 << R300_SKIP_DWORDS_1_SHIFT) | -+ (10 << R300_DST_VEC_LOC_1_SHIFT) | -+ R300_LAST_VEC_1 | -+ R300_SIGNED_1)); -+ OUT_VIDEO_REG(R300_VAP_PROG_STREAM_CNTL_EXT_0, -+ ((R300_SWIZZLE_SELECT_X << R300_SWIZZLE_SELECT_X_0_SHIFT) | -+ (R300_SWIZZLE_SELECT_Y << R300_SWIZZLE_SELECT_Y_0_SHIFT) | -+ (R300_SWIZZLE_SELECT_Z << R300_SWIZZLE_SELECT_Z_0_SHIFT) | -+ (R300_SWIZZLE_SELECT_W << R300_SWIZZLE_SELECT_W_0_SHIFT) | -+ ((R300_WRITE_ENA_X | R300_WRITE_ENA_Y | R300_WRITE_ENA_Z | R300_WRITE_ENA_W) -+ << R300_WRITE_ENA_0_SHIFT) | -+ (R300_SWIZZLE_SELECT_X << R300_SWIZZLE_SELECT_X_1_SHIFT) | -+ (R300_SWIZZLE_SELECT_Y << R300_SWIZZLE_SELECT_Y_1_SHIFT) | -+ (R300_SWIZZLE_SELECT_Z << R300_SWIZZLE_SELECT_Z_1_SHIFT) | -+ (R300_SWIZZLE_SELECT_W << R300_SWIZZLE_SELECT_W_1_SHIFT) | -+ ((R300_WRITE_ENA_X | R300_WRITE_ENA_Y | R300_WRITE_ENA_Z | R300_WRITE_ENA_W) -+ << R300_WRITE_ENA_1_SHIFT))); -+ } else { -+ OUT_VIDEO_REG(R300_VAP_PROG_STREAM_CNTL_0, -+ ((R300_DATA_TYPE_FLOAT_2 << R300_DATA_TYPE_0_SHIFT) | -+ (0 << R300_SKIP_DWORDS_0_SHIFT) | -+ (0 << R300_DST_VEC_LOC_0_SHIFT) | -+ R300_SIGNED_0 | -+ (R300_DATA_TYPE_FLOAT_2 << R300_DATA_TYPE_1_SHIFT) | -+ (0 << R300_SKIP_DWORDS_1_SHIFT) | -+ (6 << R300_DST_VEC_LOC_1_SHIFT) | -+ R300_LAST_VEC_1 | -+ R300_SIGNED_1)); -+ OUT_VIDEO_REG(R300_VAP_PROG_STREAM_CNTL_EXT_0, -+ ((R300_SWIZZLE_SELECT_X << R300_SWIZZLE_SELECT_X_0_SHIFT) | -+ (R300_SWIZZLE_SELECT_Y << R300_SWIZZLE_SELECT_Y_0_SHIFT) | -+ (R300_SWIZZLE_SELECT_FP_ZERO << R300_SWIZZLE_SELECT_Z_0_SHIFT) | -+ (R300_SWIZZLE_SELECT_FP_ONE << R300_SWIZZLE_SELECT_W_0_SHIFT) | -+ ((R300_WRITE_ENA_X | R300_WRITE_ENA_Y) -+ << R300_WRITE_ENA_0_SHIFT) | -+ (R300_SWIZZLE_SELECT_X << R300_SWIZZLE_SELECT_X_1_SHIFT) | -+ (R300_SWIZZLE_SELECT_Y << R300_SWIZZLE_SELECT_Y_1_SHIFT) | -+ (R300_SWIZZLE_SELECT_FP_ZERO << R300_SWIZZLE_SELECT_Z_1_SHIFT) | -+ (R300_SWIZZLE_SELECT_FP_ONE << R300_SWIZZLE_SELECT_W_1_SHIFT) | -+ ((R300_WRITE_ENA_X | R300_WRITE_ENA_Y) -+ << R300_WRITE_ENA_1_SHIFT))); -+ } -+ -+ /* setup vertex shader */ -+ if (has_tcl) { -+ OUT_VIDEO_REG(R300_VAP_PVS_CODE_CNTL_0, -+ ((0 << R300_PVS_FIRST_INST_SHIFT) | -+ (1 << R300_PVS_XYZW_VALID_INST_SHIFT) | -+ (1 << R300_PVS_LAST_INST_SHIFT))); -+ OUT_VIDEO_REG(R300_VAP_PVS_CODE_CNTL_1, -+ (1 << R300_PVS_LAST_VTX_SRC_INST_SHIFT)); -+ OUT_VIDEO_REG(R300_VAP_PVS_VECTOR_INDX_REG, 0); -+ OUT_VIDEO_REG(R300_VAP_PVS_VECTOR_DATA_REG,0x00f00203); -+ OUT_VIDEO_REG(R300_VAP_PVS_VECTOR_DATA_REG,0x00d10001); -+ OUT_VIDEO_REG(R300_VAP_PVS_VECTOR_DATA_REG,0x01248001); -+ OUT_VIDEO_REG(R300_VAP_PVS_VECTOR_DATA_REG,0x01248001); -+ OUT_VIDEO_REG(R300_VAP_PVS_VECTOR_DATA_REG,0x00f02203); -+ OUT_VIDEO_REG(R300_VAP_PVS_VECTOR_DATA_REG,0x00d10141); -+ OUT_VIDEO_REG(R300_VAP_PVS_VECTOR_DATA_REG,0x01248141); -+ OUT_VIDEO_REG(R300_VAP_PVS_VECTOR_DATA_REG,0x01248141); -+ OUT_VIDEO_REG(R300_VAP_PVS_FLOW_CNTL_OPC, 0); -+ -+ -+ OUT_VIDEO_REG(R300_VAP_GB_VERT_CLIP_ADJ, 0x3f800000); -+ OUT_VIDEO_REG(R300_VAP_GB_VERT_DISC_ADJ, 0x3f800000); -+ OUT_VIDEO_REG(R300_VAP_GB_HORZ_CLIP_ADJ, 0x3f800000); -+ OUT_VIDEO_REG(R300_VAP_GB_HORZ_DISC_ADJ, 0x3f800000); -+ OUT_VIDEO_REG(R300_VAP_CLIP_CNTL, R300_CLIP_DISABLE); -+ } -+ -+ OUT_VIDEO_REG(R300_VAP_OUT_VTX_FMT_0, R300_VTX_POS_PRESENT); -+ OUT_VIDEO_REG(R300_VAP_OUT_VTX_FMT_1, (2 << R300_TEX_0_COMP_CNT_SHIFT)); -+ FINISH_VIDEO(); -+ -+ /* setup pixel shader */ -+ if (IS_R300_VARIANT || info->ChipFamily == CHIP_FAMILY_RS690) { -+ BEGIN_VIDEO(16); -+ OUT_VIDEO_REG(R300_RS_COUNT, -+ ((2 << R300_RS_COUNT_IT_COUNT_SHIFT) | -+ R300_RS_COUNT_HIRES_EN)); -+ OUT_VIDEO_REG(R300_RS_IP_0, -+ (R300_RS_TEX_PTR(0) | -+ R300_RS_COL_PTR(0) | -+ R300_RS_COL_FMT(R300_RS_COL_FMT_RGBA) | -+ R300_RS_SEL_S(R300_RS_SEL_C0) | -+ R300_RS_SEL_T(R300_RS_SEL_C1) | -+ R300_RS_SEL_R(R300_RS_SEL_K0) | -+ R300_RS_SEL_Q(R300_RS_SEL_K1))); -+ OUT_VIDEO_REG(R300_RS_INST_COUNT, R300_TX_OFFSET_RS(6)); -+ OUT_VIDEO_REG(R300_RS_INST_0, R300_RS_INST_TEX_CN_WRITE); -+ OUT_VIDEO_REG(R300_US_CONFIG, (0 << R300_NLEVEL_SHIFT) | R300_FIRST_TEX); -+ OUT_VIDEO_REG(R300_US_PIXSIZE, 0); -+ OUT_VIDEO_REG(R300_US_CODE_OFFSET, -+ (R300_ALU_CODE_OFFSET(0) | -+ R300_ALU_CODE_SIZE(1) | -+ R300_TEX_CODE_OFFSET(0) | -+ R300_TEX_CODE_SIZE(1))); -+ OUT_VIDEO_REG(R300_US_CODE_ADDR_0, 0); -+ OUT_VIDEO_REG(R300_US_CODE_ADDR_1, 0); -+ OUT_VIDEO_REG(R300_US_CODE_ADDR_2, 0); -+ OUT_VIDEO_REG(R300_US_CODE_ADDR_3, 0x400000); -+ OUT_VIDEO_REG(R300_US_TEX_INST_0, 0x8000); -+ OUT_VIDEO_REG(R300_US_ALU_RGB_ADDR_0, 0x1f800000); -+ OUT_VIDEO_REG(R300_US_ALU_RGB_INST_0, 0x50a80); -+ OUT_VIDEO_REG(R300_US_ALU_ALPHA_ADDR_0, 0x1800000); -+ OUT_VIDEO_REG(R300_US_ALU_ALPHA_INST_0, 0x00040889); -+ FINISH_VIDEO(); -+ } else { -+ BEGIN_VIDEO(22); -+ OUT_VIDEO_REG(R300_RS_COUNT, -+ ((2 << R300_RS_COUNT_IT_COUNT_SHIFT) | -+ R300_RS_COUNT_HIRES_EN)); -+ OUT_VIDEO_REG(R500_RS_IP_0, (0 << R500_RS_IP_TEX_PTR_S_SHIFT) | (1 << R500_RS_IP_TEX_PTR_T_SHIFT) | -+ (R500_RS_IP_PTR_K0 << R500_RS_IP_TEX_PTR_R_SHIFT) | (R500_RS_IP_PTR_K1 << R500_RS_IP_TEX_PTR_Q_SHIFT)); -+ -+ OUT_VIDEO_REG(R300_RS_INST_COUNT, 0); -+ OUT_VIDEO_REG(R500_RS_INST_0, R500_RS_INST_TEX_CN_WRITE); -+ OUT_VIDEO_REG(R300_US_CONFIG, R500_ZERO_TIMES_ANYTHING_EQUALS_ZERO); -+ OUT_VIDEO_REG(R300_US_PIXSIZE, 0); -+ OUT_VIDEO_REG(R500_US_FC_CTRL, 0); -+ OUT_VIDEO_REG(R500_US_CODE_ADDR, R500_US_CODE_START_ADDR(0) | R500_US_CODE_END_ADDR(1)); -+ OUT_VIDEO_REG(R500_US_CODE_RANGE, R500_US_CODE_RANGE_ADDR(0) | R500_US_CODE_RANGE_SIZE(1)); -+ OUT_VIDEO_REG(R500_US_CODE_OFFSET, 0); -+ OUT_VIDEO_REG(R500_GA_US_VECTOR_INDEX, 0); -+ OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, 0x00007807); -+ OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, 0x06400000); -+ OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, 0xe4000400); -+ OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, 0x00000000); -+ OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, 0x00000000); -+ OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, 0x00000000); -+ OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, 0x00078105); -+ OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, 0x10040000); -+ OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, 0x10040000); -+ OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, 0x00db0220); -+ OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, 0x00c0c000); -+ OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, 0x20490000); -+ FINISH_VIDEO(); -+ } -+ -+ BEGIN_VIDEO(6); -+ OUT_VIDEO_REG(R300_TX_INVALTAGS, 0); -+ OUT_VIDEO_REG(R300_TX_ENABLE, txenable); -+ -+ OUT_VIDEO_REG(R300_RB3D_COLOROFFSET0, dst_offset); -+ OUT_VIDEO_REG(R300_RB3D_COLORPITCH0, colorpitch); -+ -+ blendcntl = RADEON_SRC_BLEND_GL_ONE | RADEON_DST_BLEND_GL_ZERO; -+ OUT_VIDEO_REG(R300_RB3D_BLENDCNTL, blendcntl); -+ OUT_VIDEO_REG(R300_RB3D_ABLENDCNTL, 0); -+ FINISH_VIDEO(); -+ -+ BEGIN_VIDEO(1); -+ OUT_VIDEO_REG(R300_VAP_VTX_SIZE, VTX_DWORD_COUNT); -+ FINISH_VIDEO(); -+ -+ } else { -+ -+ /* Same for R100/R200 */ -+ switch (pPixmap->drawable.bitsPerPixel) { -+ case 16: -+ if (pPixmap->drawable.depth == 15) -+ dst_format = RADEON_COLOR_FORMAT_ARGB1555; -+ else -+ dst_format = RADEON_COLOR_FORMAT_RGB565; -+ break; -+ case 32: -+ dst_format = RADEON_COLOR_FORMAT_ARGB8888; -+ break; -+ default: -+ return; -+ } -+ -+ if (pPriv->id == FOURCC_UYVY) -+ txformat = RADEON_TXFORMAT_YVYU422; -+ else -+ txformat = RADEON_TXFORMAT_VYUY422; -+ -+ txformat |= RADEON_TXFORMAT_NON_POWER2; -+ -+ colorpitch = dst_pitch >> pixel_shift; -+ -+ if (RADEONTilingEnabled(pScrn, pPixmap)) -+ colorpitch |= RADEON_COLOR_TILE_ENABLE; -+ -+ BEGIN_VIDEO(5); -+ -+ OUT_VIDEO_REG(RADEON_PP_CNTL, -+ RADEON_TEX_0_ENABLE | RADEON_TEX_BLEND_0_ENABLE); -+ OUT_VIDEO_REG(RADEON_RB3D_CNTL, -+ dst_format | RADEON_ALPHA_BLEND_ENABLE); -+ OUT_VIDEO_REG(RADEON_RB3D_COLOROFFSET, dst_offset); -+ -+ OUT_VIDEO_REG(RADEON_RB3D_COLORPITCH, colorpitch); -+ -+ OUT_VIDEO_REG(RADEON_RB3D_BLENDCNTL, -+ RADEON_SRC_BLEND_GL_ONE | RADEON_DST_BLEND_GL_ZERO); -+ -+ FINISH_VIDEO(); -+ -+ -+ if ((info->ChipFamily == CHIP_FAMILY_RV250) || -+ (info->ChipFamily == CHIP_FAMILY_RV280) || -+ (info->ChipFamily == CHIP_FAMILY_RS300) || -+ (info->ChipFamily == CHIP_FAMILY_R200)) { -+ -+ info->texW[0] = pPriv->w; -+ info->texH[0] = pPriv->h; -+ -+ BEGIN_VIDEO(12); -+ -+ OUT_VIDEO_REG(R200_SE_VTX_FMT_0, R200_VTX_XY); -+ OUT_VIDEO_REG(R200_SE_VTX_FMT_1, -+ (2 << R200_VTX_TEX0_COMP_CNT_SHIFT)); -+ -+ OUT_VIDEO_REG(R200_PP_TXFILTER_0, -+ R200_MAG_FILTER_LINEAR | -+ R200_MIN_FILTER_LINEAR | -+ R200_YUV_TO_RGB); -+ OUT_VIDEO_REG(R200_PP_TXFORMAT_0, txformat); -+ OUT_VIDEO_REG(R200_PP_TXFORMAT_X_0, 0); -+ OUT_VIDEO_REG(R200_PP_TXSIZE_0, -+ (pPriv->w - 1) | -+ ((pPriv->h - 1) << RADEON_TEX_VSIZE_SHIFT)); -+ OUT_VIDEO_REG(R200_PP_TXPITCH_0, pPriv->src_pitch - 32); -+ -+ OUT_VIDEO_REG(R200_PP_TXOFFSET_0, pPriv->src_offset); -+ -+ OUT_VIDEO_REG(R200_PP_TXCBLEND_0, -+ R200_TXC_ARG_A_ZERO | -+ R200_TXC_ARG_B_ZERO | -+ R200_TXC_ARG_C_R0_COLOR | -+ R200_TXC_OP_MADD); -+ OUT_VIDEO_REG(R200_PP_TXCBLEND2_0, -+ R200_TXC_CLAMP_0_1 | R200_TXC_OUTPUT_REG_R0); -+ OUT_VIDEO_REG(R200_PP_TXABLEND_0, -+ R200_TXA_ARG_A_ZERO | -+ R200_TXA_ARG_B_ZERO | -+ R200_TXA_ARG_C_R0_ALPHA | -+ R200_TXA_OP_MADD); -+ OUT_VIDEO_REG(R200_PP_TXABLEND2_0, -+ R200_TXA_CLAMP_0_1 | R200_TXA_OUTPUT_REG_R0); -+ FINISH_VIDEO(); -+ } else { -+ -+ info->texW[0] = 1; -+ info->texH[0] = 1; -+ -+ BEGIN_VIDEO(8); -+ -+ OUT_VIDEO_REG(RADEON_SE_VTX_FMT, RADEON_SE_VTX_FMT_XY | -+ RADEON_SE_VTX_FMT_ST0); -+ -+ OUT_VIDEO_REG(RADEON_PP_TXFILTER_0, RADEON_MAG_FILTER_LINEAR | -+ RADEON_MIN_FILTER_LINEAR | -+ RADEON_YUV_TO_RGB); -+ OUT_VIDEO_REG(RADEON_PP_TXFORMAT_0, txformat); -+ OUT_VIDEO_REG(RADEON_PP_TXOFFSET_0, pPriv->src_offset); -+ OUT_VIDEO_REG(RADEON_PP_TXCBLEND_0, -+ RADEON_COLOR_ARG_A_ZERO | -+ RADEON_COLOR_ARG_B_ZERO | -+ RADEON_COLOR_ARG_C_T0_COLOR | -+ RADEON_BLEND_CTL_ADD | -+ RADEON_CLAMP_TX); -+ OUT_VIDEO_REG(RADEON_PP_TXABLEND_0, -+ RADEON_ALPHA_ARG_A_ZERO | -+ RADEON_ALPHA_ARG_B_ZERO | -+ RADEON_ALPHA_ARG_C_T0_ALPHA | -+ RADEON_BLEND_CTL_ADD | -+ RADEON_CLAMP_TX); -+ -+ OUT_VIDEO_REG(RADEON_PP_TEX_SIZE_0, -+ (pPriv->w - 1) | -+ ((pPriv->h - 1) << RADEON_TEX_VSIZE_SHIFT)); -+ OUT_VIDEO_REG(RADEON_PP_TEX_PITCH_0, -+ pPriv->src_pitch - 32); -+ FINISH_VIDEO(); -+ } -+ } -+ -+ while (nBox--) { -+ int srcX, srcY, srcw, srch; -+ int dstX, dstY, dstw, dsth; -+ xPointFixed srcTopLeft, srcTopRight, srcBottomLeft, srcBottomRight; -+ dstX = pBox->x1 + dstxoff; -+ dstY = pBox->y1 + dstyoff; -+ dstw = pBox->x2 - pBox->x1; -+ dsth = pBox->y2 - pBox->y1; -+ -+ srcX = ((pBox->x1 - pPriv->drw_x) * -+ pPriv->src_w) / pPriv->dst_w; -+ srcY = ((pBox->y1 - pPriv->drw_y) * -+ pPriv->src_h) / pPriv->dst_h; -+ -+ srcw = (pPriv->src_w * dstw) / pPriv->dst_w; -+ srch = (pPriv->src_h * dsth) / pPriv->dst_h; -+ -+ srcTopLeft.x = IntToxFixed(srcX); -+ srcTopLeft.y = IntToxFixed(srcY); -+ srcTopRight.x = IntToxFixed(srcX + srcw); -+ srcTopRight.y = IntToxFixed(srcY); -+ srcBottomLeft.x = IntToxFixed(srcX); -+ srcBottomLeft.y = IntToxFixed(srcY + srch); -+ srcBottomRight.x = IntToxFixed(srcX + srcw); -+ srcBottomRight.y = IntToxFixed(srcY + srch); -+ -+ -+#if 0 -+ ErrorF("dst: %d, %d, %d, %d\n", dstX, dstY, dstw, dsth); -+ ErrorF("src: %d, %d, %d, %d\n", srcX, srcY, srcw, srch); -+#endif -+ -+#ifdef ACCEL_CP -+ if (info->ChipFamily < CHIP_FAMILY_R200) { -+ BEGIN_RING(4 * VTX_DWORD_COUNT + 3); -+ OUT_RING(CP_PACKET3(RADEON_CP_PACKET3_3D_DRAW_IMMD, -+ 4 * VTX_DWORD_COUNT + 1)); -+ OUT_RING(RADEON_CP_VC_FRMT_XY | -+ RADEON_CP_VC_FRMT_ST0); -+ OUT_RING(RADEON_CP_VC_CNTL_PRIM_TYPE_TRI_FAN | -+ RADEON_CP_VC_CNTL_PRIM_WALK_RING | -+ RADEON_CP_VC_CNTL_MAOS_ENABLE | -+ RADEON_CP_VC_CNTL_VTX_FMT_RADEON_MODE | -+ (4 << RADEON_CP_VC_CNTL_NUM_SHIFT)); -+ } else { -+ if (IS_R300_VARIANT || IS_AVIVO_VARIANT) -+ BEGIN_RING(4 * VTX_DWORD_COUNT + 6); -+ else -+ BEGIN_RING(4 * VTX_DWORD_COUNT + 2); -+ OUT_RING(CP_PACKET3(R200_CP_PACKET3_3D_DRAW_IMMD_2, -+ 4 * VTX_DWORD_COUNT)); -+ OUT_RING(RADEON_CP_VC_CNTL_PRIM_TYPE_TRI_FAN | -+ RADEON_CP_VC_CNTL_PRIM_WALK_RING | -+ (4 << RADEON_CP_VC_CNTL_NUM_SHIFT)); -+ } -+#else /* ACCEL_CP */ -+ if (IS_R300_VARIANT || IS_AVIVO_VARIANT) -+ BEGIN_VIDEO(3 + VTX_DWORD_COUNT * 4); -+ else -+ BEGIN_VIDEO(1 + VTX_DWORD_COUNT * 4); -+ -+ if (info->ChipFamily < CHIP_FAMILY_R200) { -+ OUT_VIDEO_REG(RADEON_SE_VF_CNTL, (RADEON_VF_PRIM_TYPE_TRIANGLE_FAN | -+ RADEON_VF_PRIM_WALK_DATA | -+ RADEON_VF_RADEON_MODE | -+ 4 << RADEON_VF_NUM_VERTICES_SHIFT)); -+ } else { -+ OUT_VIDEO_REG(RADEON_SE_VF_CNTL, (RADEON_VF_PRIM_TYPE_QUAD_LIST | -+ RADEON_VF_PRIM_WALK_DATA | -+ 4 << RADEON_VF_NUM_VERTICES_SHIFT)); -+ } -+#endif -+ -+ VTX_OUT((float)dstX, (float)dstY, -+ xFixedToFloat(srcTopLeft.x) / info->texW[0], xFixedToFloat(srcTopLeft.y) / info->texH[0]); -+ VTX_OUT((float)dstX, (float)(dstY + dsth), -+ xFixedToFloat(srcBottomLeft.x) / info->texW[0], xFixedToFloat(srcBottomLeft.y) / info->texH[0]); -+ VTX_OUT((float)(dstX + dstw), (float)(dstY + dsth), -+ xFixedToFloat(srcBottomRight.x) / info->texW[0], xFixedToFloat(srcBottomRight.y) / info->texH[0]); -+ VTX_OUT((float)(dstX + dstw), (float)dstY, -+ xFixedToFloat(srcTopRight.x) / info->texW[0], xFixedToFloat(srcTopRight.y) / info->texH[0]); -+ -+ if (IS_R300_VARIANT || IS_AVIVO_VARIANT) { -+ OUT_VIDEO_REG(R300_RB3D_DSTCACHE_CTLSTAT, R300_DC_FLUSH_3D | R300_DC_FREE_3D); -+ OUT_VIDEO_REG(RADEON_WAIT_UNTIL, RADEON_WAIT_3D_IDLECLEAN); -+ } -+ -+#ifdef ACCEL_CP -+ ADVANCE_RING(); -+#else -+ FINISH_VIDEO(); -+#endif /* !ACCEL_CP */ -+ -+ pBox++; -+ } -+ -+ DamageDamageRegion(pPriv->pDraw, &pPriv->clip); -+} -+ -+#undef VTX_OUT -+#undef FUNC_NAME -diff --git a/src/radeon_video.c b/src/radeon_video.c -index 0b3f6ca..7502e1e 100644 ---- a/src/radeon_video.c -+++ b/src/radeon_video.c -@@ -74,19 +74,10 @@ - static void RADEONInitOffscreenImages(ScreenPtr); - - static XF86VideoAdaptorPtr RADEONSetupImageVideo(ScreenPtr); --static int RADEONSetPortAttribute(ScrnInfoPtr, Atom, INT32, pointer); --static int RADEONGetPortAttribute(ScrnInfoPtr, Atom ,INT32 *, pointer); --static void RADEONStopVideo(ScrnInfoPtr, pointer, Bool); --static void RADEONQueryBestSize(ScrnInfoPtr, Bool, short, short, short, short, -- unsigned int *, unsigned int *, pointer); - static int RADEONPutImage(ScrnInfoPtr, short, short, short, short, short, - short, short, short, int, unsigned char*, short, - short, Bool, RegionPtr, pointer, - DrawablePtr); --static int RADEONQueryImageAttributes(ScrnInfoPtr, int, unsigned short *, -- unsigned short *, int *, int *); --static void RADEONFreeMemory(ScrnInfoPtr pScrn, void *mem_struct); -- - static void RADEONVideoTimerCallback(ScrnInfoPtr pScrn, Time now); - static int RADEONPutVideo(ScrnInfoPtr pScrn, short src_x, short src_y, short drw_x, short drw_y, - short src_w, short src_h, short drw_w, short drw_h, -@@ -270,29 +261,37 @@ ATIVideoSave(ScreenPtr pScreen, ExaOffscreenArea *area) - void RADEONInitVideo(ScreenPtr pScreen) - { - ScrnInfoPtr pScrn = xf86Screens[pScreen->myNum]; -+ RADEONInfoPtr info = RADEONPTR(pScrn); - XF86VideoAdaptorPtr *adaptors, *newAdaptors = NULL; -- XF86VideoAdaptorPtr newAdaptor = NULL; -+ XF86VideoAdaptorPtr overlayAdaptor = NULL, texturedAdaptor = NULL; - int num_adaptors; - -- newAdaptor = RADEONSetupImageVideo(pScreen); -- RADEONInitOffscreenImages(pScreen); -+ - num_adaptors = xf86XVListGenericAdaptors(pScrn, &adaptors); -+ newAdaptors = xalloc((num_adaptors + 2) * sizeof(XF86VideoAdaptorPtr *)); -+ if (newAdaptors == NULL) -+ return; - -- if(newAdaptor) { -- if(!num_adaptors) { -- num_adaptors = 1; -- adaptors = &newAdaptor; -- } else { -- newAdaptors = /* need to free this someplace */ -- xalloc((num_adaptors + 1) * sizeof(XF86VideoAdaptorPtr*)); -- if(newAdaptors) { -- memcpy(newAdaptors, adaptors, num_adaptors * -- sizeof(XF86VideoAdaptorPtr)); -- newAdaptors[num_adaptors] = newAdaptor; -- adaptors = newAdaptors; -- num_adaptors++; -- } -- } -+ memcpy(newAdaptors, adaptors, num_adaptors * sizeof(XF86VideoAdaptorPtr)); -+ adaptors = newAdaptors; -+ -+ if (!IS_AVIVO_VARIANT) { -+ overlayAdaptor = RADEONSetupImageVideo(pScreen); -+ if (overlayAdaptor != NULL) { -+ adaptors[num_adaptors++] = overlayAdaptor; -+ xf86DrvMsg(pScrn->scrnIndex, X_INFO, "Set up overlay video\n"); -+ } else -+ xf86DrvMsg(pScrn->scrnIndex, X_ERROR, "Failed to set up overlay video\n"); -+ RADEONInitOffscreenImages(pScreen); -+ } -+ -+ if (info->ChipFamily != CHIP_FAMILY_RS400) { -+ texturedAdaptor = RADEONSetupImageTexturedVideo(pScreen); -+ if (texturedAdaptor != NULL) { -+ adaptors[num_adaptors++] = texturedAdaptor; -+ xf86DrvMsg(pScrn->scrnIndex, X_INFO, "Set up textured video\n"); -+ } else -+ xf86DrvMsg(pScrn->scrnIndex, X_ERROR, "Failed to set up textured video\n"); - } - - if(num_adaptors) -@@ -300,6 +299,7 @@ void RADEONInitVideo(ScreenPtr pScreen) - - if(newAdaptors) - xfree(newAdaptors); -+ - } - - /* client libraries expect an encoding */ -@@ -1611,6 +1611,8 @@ RADEONSetupImageVideo(ScreenPtr pScreen) - pPriv = (RADEONPortPrivPtr)(adapt->pPortPrivates[0].ptr); - REGION_NULL(pScreen, &(pPriv->clip)); - -+ pPriv->textured = FALSE; -+ - if(pPriv->theatre != NULL) - { - /* video decoder is present, extend capabilities */ -@@ -1626,13 +1628,16 @@ RADEONSetupImageVideo(ScreenPtr pScreen) - return adapt; - } - --static void -+void - RADEONStopVideo(ScrnInfoPtr pScrn, pointer data, Bool cleanup) - { - RADEONInfoPtr info = RADEONPTR(pScrn); - unsigned char *RADEONMMIO = info->MMIO; - RADEONPortPrivPtr pPriv = (RADEONPortPrivPtr)data; - -+ if (pPriv->textured) -+ return; -+ - REGION_EMPTY(pScrn->pScreen, &pPriv->clip); - - if(cleanup) { -@@ -1663,7 +1668,7 @@ RADEONStopVideo(ScrnInfoPtr pScrn, pointer data, Bool cleanup) - } - } - --static int -+int - RADEONSetPortAttribute(ScrnInfoPtr pScrn, - Atom attribute, - INT32 value, -@@ -1675,6 +1680,9 @@ RADEONSetPortAttribute(ScrnInfoPtr pScrn, - Bool setAlpha = FALSE; - unsigned char *RADEONMMIO = info->MMIO; - -+ if (pPriv->textured) -+ return BadMatch; -+ - RADEON_SYNC(info, pScrn); - - #define RTFSaturation(a) (1.0 + ((a)*1.0)/1000.0) -@@ -1937,7 +1945,7 @@ RADEONSetPortAttribute(ScrnInfoPtr pScrn, - return Success; - } - --static int -+int - RADEONGetPortAttribute(ScrnInfoPtr pScrn, - Atom attribute, - INT32 *value, -@@ -1946,6 +1954,9 @@ RADEONGetPortAttribute(ScrnInfoPtr pScrn, - RADEONInfoPtr info = RADEONPTR(pScrn); - RADEONPortPrivPtr pPriv = (RADEONPortPrivPtr)data; - -+ if (pPriv->textured) -+ return BadMatch; -+ - if (info->accelOn) RADEON_SYNC(info, pScrn); - - if(attribute == xvAutopaintColorkey) -@@ -2031,7 +2042,7 @@ RADEONGetPortAttribute(ScrnInfoPtr pScrn, - return Success; - } - --static void -+void - RADEONQueryBestSize( - ScrnInfoPtr pScrn, - Bool motion, -@@ -2040,10 +2051,14 @@ RADEONQueryBestSize( - unsigned int *p_w, unsigned int *p_h, - pointer data - ){ -- if(vid_w > (drw_w << 4)) -- drw_w = vid_w >> 4; -- if(vid_h > (drw_h << 4)) -- drw_h = vid_h >> 4; -+ RADEONPortPrivPtr pPriv = (RADEONPortPrivPtr)data; -+ -+ if (!pPriv->textured) { -+ if (vid_w > (drw_w << 4)) -+ drw_w = vid_w >> 4; -+ if (vid_h > (drw_h << 4)) -+ drw_h = vid_h >> 4; -+ } - - *p_w = drw_w; - *p_h = drw_h; -@@ -2132,7 +2147,7 @@ static struct { - {1.00, {{ 0, 32, 0, 0}, {-2, 29, 5, 0}, {-3, 27, 9, -1}, {-4, 24, 14, -2}, {-3, 19, 19, -3}, }} - }; - --static void -+void - RADEONCopyData( - ScrnInfoPtr pScrn, - unsigned char *src, -@@ -2300,7 +2315,7 @@ static void RADEON_420_422( - } - #endif - --static void -+void - RADEONCopyMungedData( - ScrnInfoPtr pScrn, - unsigned char *src1, -@@ -2405,7 +2420,7 @@ RADEONCopyMungedData( - * is measured in bytes, and the offset from the beginning of card space is - * returned. - */ --static CARD32 -+CARD32 - RADEONAllocateMemory( - ScrnInfoPtr pScrn, - void **mem_struct, -@@ -2482,7 +2497,7 @@ RADEONAllocateMemory( - return offset; - } - --static void -+void - RADEONFreeMemory( - ScrnInfoPtr pScrn, - void *mem_struct -@@ -3122,7 +3137,7 @@ RADEONPutImage( - } - - --static int -+int - RADEONQueryImageAttributes( - ScrnInfoPtr pScrn, - int id, -diff --git a/src/radeon_video.h b/src/radeon_video.h -index 072f40e..f897e07 100644 ---- a/src/radeon_video.h -+++ b/src/radeon_video.h -@@ -81,8 +81,8 @@ typedef struct { - Bool autopaint_colorkey; - xf86CrtcPtr desired_crtc; - --#ifdef USE_EXA - int size; -+#ifdef USE_EXA - ExaOffscreenArea *off_screen; - #endif - -@@ -90,6 +90,20 @@ typedef struct { - int video_offset; - - Atom device_id, location_id, instance_id; -+ -+ /* textured video */ -+ Bool textured; -+ DrawablePtr pDraw; -+ PixmapPtr pPixmap; -+ -+ CARD32 src_offset; -+ CARD32 src_pitch; -+ CARD8 *src_addr; -+ -+ int id; -+ int src_w, src_h, dst_w, dst_h; -+ int w, h; -+ int drw_x, drw_y; - } RADEONPortPrivRec, *RADEONPortPrivPtr; - - -@@ -99,5 +113,33 @@ void RADEONResetI2C(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv); - void RADEONVIP_init(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv); - void RADEONVIP_reset(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv); - -+CARD32 -+RADEONAllocateMemory(ScrnInfoPtr pScrn, void **mem_struct, int size); -+void -+RADEONFreeMemory(ScrnInfoPtr pScrn, void *mem_struct); -+ -+int RADEONSetPortAttribute(ScrnInfoPtr, Atom, INT32, pointer); -+int RADEONGetPortAttribute(ScrnInfoPtr, Atom ,INT32 *, pointer); -+void RADEONStopVideo(ScrnInfoPtr, pointer, Bool); -+void RADEONQueryBestSize(ScrnInfoPtr, Bool, short, short, short, short, -+ unsigned int *, unsigned int *, pointer); -+int RADEONQueryImageAttributes(ScrnInfoPtr, int, unsigned short *, -+ unsigned short *, int *, int *); -+ -+XF86VideoAdaptorPtr -+RADEONSetupImageTexturedVideo(ScreenPtr pScreen); -+ -+void -+RADEONCopyData(ScrnInfoPtr pScrn, -+ unsigned char *src, unsigned char *dst, -+ unsigned int srcPitch, unsigned int dstPitch, -+ unsigned int h, unsigned int w, unsigned int bpp); -+ -+void -+RADEONCopyMungedData(ScrnInfoPtr pScrn, -+ unsigned char *src1, unsigned char *src2, -+ unsigned char *src3, unsigned char *dst1, -+ unsigned int srcPitch, unsigned int srcPitch2, -+ unsigned int dstPitch, unsigned int h, unsigned int w); - - #endif diff --git a/radeon-git-upstream-fixes2.patch b/radeon-git-upstream-fixes2.patch deleted file mode 100644 index b6268b2..0000000 --- a/radeon-git-upstream-fixes2.patch +++ /dev/null @@ -1,23810 +0,0 @@ -commit 1f3eee3682f3598a303c9c3accfbe01b245cacf9 -Author: Alex Deucher -Date: Tue Jul 29 20:29:32 2008 -0400 - - Change prim types for exa and textured video to help avoid tearing - - - r1xx - switch from tri fan to rect list - - r2xx/r3xx/r4xx/r5xx - switch from tri fan to quad list - -commit 5b5441f8cc119db0d1e03dd35bd06015a26270dd -Author: Brice Goglin -Date: Tue Jul 29 23:31:14 2008 +0200 - - Increase default GART size to 32MB on >=R300 - -commit 0a505297f09aefb1b4432176a263bfdf6f256f77 -Author: Alex Deucher -Date: Mon Jul 28 17:12:41 2008 -0400 - - Fix error in driver connector table for powerbook w/ vga - -commit d5799ac53c3e1b2ca1da97780b171a44060c3aad -Author: Alex Deucher -Date: Mon Jul 28 11:09:10 2008 -0400 - - Add quirk for oem x300 card - - - debian bug 492457 - -commit 64dbadddcf6d069c0472f37afeab89d3e31e937d -Author: Owain Gordon Ainsworth -Date: Mon Jul 28 10:40:58 2008 +1000 - - radeon: don't call ioctl unless DRI is initialised - -commit 1c5858484da4fb1c9bc3ac3b4d7a97863ab99730 -Author: Alex Deucher -Date: Mon Jul 21 23:47:45 2008 -0400 - - First pass at InitDispBandwidth() for AVIVO chips - - - support for LB allocation - - MC priority bumps for display1/2 on RV515 variants and RS690 - If you are having display underflow problems (flickering on sides of - screen in high res modes, etc.) on RV515 or RS690 boards, try setting: - Option "DisplayPriority" "HIGH" in your config. - - still no support for full display watermark programming yet - - Something similar might be useful in rhd as well. - -commit b0378bb145c8a915c943bef7d17f2cdecfccc891 -Author: Alex Deucher -Date: Mon Jul 21 13:47:09 2008 -0400 - - Interlaced mode fixups for AVIVO chips - -commit c18fad622a3c4f9572051120d83af68b625b5686 -Author: Alex Deucher -Date: Mon Jul 21 10:36:48 2008 -0400 - - Clear display priority bits before resetting them - -commit dc231ff8e063313d2bcf5acccad67a9f8a7e3314 -Author: Alex Deucher -Date: Mon Jul 21 10:30:41 2008 -0400 - - Clean up legacy display watermark setup - - - makes crtc1 and crtc2 watermark setup independant. - - fixes the case where only crtc2 is active - -commit f9034214f070fe3054cd9cefd7034252de234f38 -Author: Michel Dänzer -Date: Mon Jul 21 09:09:02 2008 +0200 - - Call DRM modeset ioctl after the IRQ has been initialized. - - This lets the DRM know it can safely disable the vblank interrupts. - -commit ecb6347a3d7071890600c98c2addef3a8ca260ee -Author: Alex Deucher -Date: Sat Jul 19 11:34:16 2008 -0400 - - Add oem quirk for external tmds setup on Dell Inspiron 8600 - - Noticed by fnord42 on IRC. - -commit df53d12a06fad41f00cff849458cb358ab5e2098 -Author: Benjamin Herrenschmidt -Date: Thu Jul 17 14:37:05 2008 +1000 - - Fix console switch on R500 - - This patch fixes the console switch for me on R5xx. - - There are two aspects to it: - - - Fix the ordering of avivo_restore() to better match what's - happening in the driver & ATOM, properly locking/unlocking and - only enabling the CRTCs after everything has been properly - programmed. - - - Don't ASIC_INIT if the card has any CRTC enabled. This is the - best I came up with for avoiding spurrious ASIC_INIT on cards that - -are- POSTed but don't have the BIOS coming from c0000 on x86. The - problem with spurrious ASIC_INIT is that we do it before we do - RADEONSave(), so that screws up the console switch. - - Note that I think we also should save/restore the palette, I don't think - we do. right now, it's a minor issue for me because I fixed offb to be - able to set it on AVIVO's but it might still have to be done in the long - run. - - Tested with a VGA analog setup on DACA and a DVI setup on TMDS 0. I - haven't tested any other combo but that should get us going. - - Cheers, - Ben. - - Signed-off-by: Dave Airlie - -commit e8c07270e1fc2ee455320370692aaf90abac2773 -Author: Alex Deucher -Date: Tue Jul 15 17:50:32 2008 -0400 - - ATOM: fix for r4xx cards with no VRAM_Usage tables - - fixes bug 15954 - -commit da41e71efd41907d9347a902720bce60b32550e5 -Author: Alex Deucher -Date: Mon Jul 14 13:21:38 2008 -0400 - - ATOM: Add support for UpdateCRTC_DoubleBufferRegisters cmd table - - locks/unlocks the crtc/grph/mode regs before updating the crtc - -commit a5e0cf13dc7ace6cf0e44e18b73b9a9266e740ab -Author: Julien Cristau -Date: Sun Jul 6 12:17:28 2008 +0200 - - Link with -lpciaccess and -ldrm if needed - - This makes sure the driver ends up with a DT_NEEDED reference to - the libraries it's using. - -commit f8da849fd89322a54cc4d722767da755358eab70 -Author: Michel Dänzer -Date: Sun Jul 13 11:31:03 2008 +0200 - - Only declare local variable when it's used. - -commit a6db4dc65aec560f3b1f37ff73ec6b0bd8207295 -Author: Dave Airlie -Date: Sat Jul 12 18:47:07 2008 +1000 - - atombios: fix typo in mode conversion for panel - -commit 19a0d5879851eff23a3e7d5cdea55bd784051115 -Author: Dave Airlie -Date: Sat Jul 12 17:04:25 2008 +1000 - - atombios: use macro to get offset into table - -commit a9746114369d516072d841ec356ec3ba3d0be71a -Author: Dave Airlie -Date: Sat Jul 12 10:46:36 2008 +1000 - - pciid: add radeon HD3850. - - pci id from legume on #radeon - -commit ab14f725676e4d4e45278c64b03fe2d328a3e439 -Author: Alex Deucher -Date: Fri Jul 11 19:05:00 2008 -0400 - - R300: NUM_FPU adjustments for VAP_CNTL - -commit 810c28cc2660b73e03e4d27be97988fc5321a06f -Author: Alex Deucher -Date: Fri Jul 11 15:31:57 2008 -0400 - - Make sure cursor offsets are properly aligned when using EXA - -commit 7e67d0163579a44f104e8f354a929ac9b33e4c21 -Author: Alex Deucher -Date: Fri Jul 11 14:30:17 2008 -0400 - - Fix cursor with multi-head and rotation - -commit 9086d008fb8c3cde0633b90ce19ffbf4eded388d -Author: Alex Deucher -Date: Tue Jul 8 09:57:04 2008 -0400 - - Add quirk for Falcon NW laptop - -commit 61f82ace0210251beb0bcc492218a75a193e1deb -Author: Benjamin Herrenschmidt -Date: Tue Jul 8 21:58:43 2008 +1000 - - atombios: add support for other endians. - - This is a cleaned up (in as much as atombios can be..) of benh's patch. - - airlied - removed benh's debugging for now, it might need to be put back later.. - -commit b4d1a47b5c6eafda5e274398eebe2701b030f22e -Author: Dave Airlie -Date: Tue Jul 8 11:09:01 2008 +1000 - - rv770 initial support - - adds pci ids and one register from AMD code - -commit 7ae4cec8cc8c90aee5dc4fa7abcce22321d4f4eb -Author: Roland Scheidegger -Date: Mon Jul 7 14:39:47 2008 -0400 - - clamp tex coords (r100/r200) for textured video - - fixes bug 14904 - -commit 879f9a37856642b337e3c0233e38fd5443338eef -Author: Alex Deucher -Date: Fri Jul 4 13:54:49 2008 -0400 - - Revert "rotate: fix rotation in conf file." - - This reverts commit 22c6ca0d5d226c725ba448e5db63fdba9e32332c. - - There seems to be an ordering issue in that causes a nasty hang - if the DRI is enabled. This needs more investigation. - -commit 22c6ca0d5d226c725ba448e5db63fdba9e32332c -Author: Dave Airlie -Date: Thu Jul 3 20:14:59 2008 +1000 - - rotate: fix rotation in conf file. - - need to set modes after init accel architecture - - reported-by: Christoph Bartoschek - -commit ce1a3edd52b647744cfa4433301befb437d211bb -Author: Dave Airlie -Date: Thu Jul 3 20:05:54 2008 +1000 - - radeon: drop all use of CPMode. - - We never test the other codepath and I don't think I've ever recommended it - for anyone. - -commit c037b4ce8769ad840a257e22b1e4ad58b8ed96fa -Author: Wolke Liu -Date: Tue Jul 1 10:45:39 2008 -0400 - - Add pci id for FireMV 2400 - -commit 72992668ca96717bf69bcea95a5deeaf7c57e826 -Author: Alex Deucher -Date: Mon Jun 30 14:09:09 2008 -0400 - - RS4xx: enable the DRI by default on all variants - - Some RS4xx chips had the DRI disabled by default. - With the recent drm and ddx changes these chips have been - reported to work now with the DRI. - -commit 0378c8ed88c829f09b5c6d51314325eaf2685fdb -Author: Michel Dänzer -Date: Sat Jun 28 14:06:45 2008 +0200 - - Restore versioning of interface for Mesa DRI driver. - - This doesn't have anything to do with the package version. - -commit cfaa23d925e3c062cf87ea844566ac11ea02d69e -Author: Alex Deucher -Date: Fri Jun 27 20:36:54 2008 -0400 - - RADEON: IGP VGA fixes take 2 - - It seems only RS300/350/400/480 are missing the primary dac - See bug 15708 - -commit 31c27ffcb3c4c5334cf726ecd4e293a678b2a1ea -Author: Alex Deucher -Date: Fri Jun 27 20:29:04 2008 -0400 - - Revert "IGP: attempt to fix VGA on IGP chips" - - This reverts commit e78e8a21b4040cd7f1983c241c860d9209398396. - -commit af79a77e6d8206b18bba97cf4e0770921dc439a7 -Author: Brice Goglin -Date: Fri Jun 27 17:09:13 2008 +0200 - - use PACKAGE_VERSION_* for radeon version - - now radeon shows verion 6.9.0 instead of 4.3.0. - - RADEON_VERSION_MAJOR_TILED is dropped from ddxDriverMajorVersion - since RADEON_VERSION_MAJOR is bigger now. - -commit c83fbdfa076c107012b7dfbbfbbb2feede00542b -Author: Alex Deucher -Date: Thu Jun 26 19:48:45 2008 -0400 - - Bump for 6.9.0 release - -commit 32e1d1daf4f68ea37624afaa2bc1ea7742e1163b -Author: Brad Smith -Date: Thu Jun 26 10:22:03 2008 -0400 - - RADEON: sys/endian.h needs sys/types.h on BSDs - - See bug 16512 - -commit dca522355a9039eca6efaba3b36397b246800f94 -Author: Brad Smith -Date: Thu Jun 26 10:13:59 2008 -0400 - - RADEON: fix copy/paste error in accel code - -commit f4292e110105910d0c19bf2db28e2682b27af2c7 -Author: Dave Airlie -Date: Fri Jun 20 15:31:43 2008 +1000 - - Revert "Revert "ATOM: disable TV-out for now"" - - Oops I really didn't mean to do this, I was testing something and it slipped - past. - - This reverts commit dd18caa4b2efc430eaae0c4362b65641f9bef440. - -commit bb1cfcbfbc1ace1f257fc3bf6401501f1a6da827 -Author: Alex Deucher -Date: Wed Jun 25 15:50:16 2008 -0400 - - RADEON: adjustments to Jerome's last commit - - - Flush caches and wait for idle after drawing - - Make sure 3D is idle too (after composite or textured video) - -commit 07be302f6dba61dd15918963fae66502230c74b7 -Merge: 8c9b8de... 5245974... -Author: Jerome Glisse -Date: Wed Jun 25 10:30:45 2008 +0200 - - Merge branch 'master' of git://anongit.freedesktop.org/xorg/driver/xf86-video-ati - -commit 8c9b8de0373797cba6f0a27e6b6f461e1070fef9 -Author: Jerome Glisse -Date: Wed Jun 25 10:28:26 2008 +0200 - - radeon: flush & wait for 2d & dma idle after 2d blit - - This should help to avoid 2d & 3d engine to step on each - other dma transaction. - -commit 52459745ec05de88adbc087e9566fe6d97ef424b -Author: Dave Airlie -Date: Wed Jun 25 17:09:11 2008 +1000 - - ati: hopefully fix byteswap mess for those other OSes. - -commit 67a6ac0001bc9d062aa426384a11a41fa7a1c09a -Author: Alex Deucher -Date: Tue Jun 24 21:06:37 2008 -0400 - - bump for rc release - -commit bd68507d2d66e03d8bcde5f6e7ea9b2dbfe8b8a0 -Author: Alex Deucher -Date: Tue Jun 24 20:59:58 2008 -0400 - - RADEON: warning fix - -commit 8e534d69c9b19fc085f7c5ca9e18f5ea04f6fc12 -Author: Alex Deucher -Date: Tue Jun 24 20:08:35 2008 -0400 - - RADEON: cleanups - - - fix some warnings - - RS400 and RS480 are separate families now (update default tmds and dac2 - tables) - -commit e78e8a21b4040cd7f1983c241c860d9209398396 -Author: Alex Deucher -Date: Tue Jun 24 19:53:28 2008 -0400 - - IGP: attempt to fix VGA on IGP chips - - VGA has never worked on some IGP chips. While the chip only has - one DAC, it appears to use a mix of Primary DAC and TVDAC controls. - - See bug 15708 - -commit faa4b4b8dbe9b8a452cfa60d53874350bb04e0cb -Author: Jiří Paleček -Date: Tue Jun 24 19:20:50 2008 -0400 - - RADEON: remove extraneous line from new pll code - -commit 72feaa37ea07620f5f2ead438dbc72a1c8883cd3 -Author: Jiří Paleček -Date: Mon Jun 23 15:53:58 2008 -0400 - - RADEON: PLL tweaks - - Patch from Jiří Paleček (see debian bug 465864) with some tweaks - by me. - - - abort rather than programming bad dividers if no pll dividers can be found - - improve the pll selection algorithm - - in general, prefer lower ref dividers - - I've tested this patch on a wide variety of chips (r1xx-r6xx) and clocks. - -commit 9c2f909ea437a63a408d2398ecabe0b378dbb982 -Author: Alex Deucher -Date: Mon Jun 23 10:38:15 2008 -0400 - - RADEON: adjust randr crtc/output prepare/commit ordering - - This fixes some occasional mode change problems with multiple heads active. - It seems radeons generally like to turn on the whole output/crtc setup - in one shot. - -commit aea9bf75cf0774afd3e65fcf3fd3851f5fb21ca3 -Author: Alex Deucher -Date: Sat Jun 21 10:57:05 2008 -0400 - - 0x1002 0x5657 is actually RV410 - - See bug 14289 - - com_bios_scratch.diff - -commit 38ce8a984f96056b7345bcc06505ba27e0e6d5b4 -Author: Dave Airlie -Date: Fri Jun 20 14:16:22 2008 +1000 - - legacy: use entity MMIO for dpms as this can crossover between zaphod infos - -commit 1a7d9bc53512b0a5240176c949e6abf1ae2fb1fd -Author: Dave Airlie -Date: Fri Jun 20 14:14:21 2008 +1000 - - atombios: use MMIO from the entity not the info - -commit ef624b88903b1a87ef5b6388e18291f75776b93d -Author: Alex Deucher -Date: Thu Jun 19 18:20:52 2008 -0400 - - RADEON: fix read past the end of an array - -commit cfe814a481d8cf2005d738a0ca9782f1ed4177f5 -Author: Dave Airlie -Date: Fri Jun 20 07:51:27 2008 +1000 - - r600: don't add fb offset here to make shadowfb work. - - discovered on irc with wpwrak. - -commit 5b323a2cbbc412b6dd4e782438b64ee996558d05 -Merge: dd18caa... eed2415... -Author: Dave Airlie -Date: Fri Jun 20 07:49:16 2008 +1000 - - Merge branch 'master' of ssh://git.freedesktop.org/git/xorg/driver/xf86-video-ati - -commit eed241553748125e902c44dcc8cf8e0605be071b -Author: Alex Deucher -Date: Tue Jun 17 17:42:31 2008 -0400 - - radeon: X_ERROR -> X_WARNING for num gb pipes - - This just means your drm is old, not fatal or anything - -commit dd18caa4b2efc430eaae0c4362b65641f9bef440 -Author: Dave Airlie -Date: Sat Jun 14 18:37:56 2008 +1000 - - Revert "ATOM: disable TV-out for now" - - This reverts commit effa245914823371e052cd9aa1143a02350891e7. - -commit b416e97a1f16ef700ba1aaca317dee82b7a3cf64 -Author: Alex Deucher -Date: Fri Jun 13 02:21:31 2008 -0400 - - RADEON: man page updates - -commit 88ce87d79069662de28ecb3c10c140919927d584 -Author: Alex Deucher -Date: Thu Jun 12 15:10:47 2008 -0400 - - Bump for 6.9.0rc1 release - -commit ada41723fdc8cbeeda12bb4ae2d16e8d1ba215de -Author: Alex Deucher -Date: Wed Jun 11 14:29:36 2008 -0400 - - R3xx: use DSTCACHE_CTLSTAT rather than RB2D_DSTCACHE_CTLSTAT - - According to the hw guys, you should use DSTCACHE_CTLSTAT to - flush the 2D dst cache rather than RB2D_DSTCACHE_CTLSTAT. - -commit 3d70c398afa0831387af81559453b77c218a54f9 -Author: Dave Airlie -Date: Thu Jun 12 06:18:26 2008 +1000 - - atom: fix another endian define - -commit f1794e4c34d801371461afed37e7bb7d1fc79305 -Author: Dave Airlie -Date: Thu Jun 12 06:10:30 2008 +1000 - - atom: fixup includes in cd operations to get correct endian bits in atombios.h - -commit f29976d12cc2020cd80c90fa3fd4b25c031559ba -Author: Dave Airlie -Date: Wed Jun 11 19:33:02 2008 +1000 - - radeon: add lots of endian bits into the atombios parser - -commit 09eb220971b5d2bfd7d1ff6f552060967a133152 -Author: Dave Airlie -Date: Wed Jun 11 19:21:22 2008 +1000 - - atombios: fixup atombios bitfields for endianness - - reverse the bits for big endian - -commit b80a3e85bf9dbfc8d96a745876d75d38bea97c1a -Author: Alex Deucher -Date: Mon Jun 9 20:29:47 2008 -0400 - - R5xx: fix RADEONSetAgpBase() for R5xx chips - - Is there any reason to still do this in the ddx? - Maybe real old drms? - -commit ab7936708dfbee4d3676262f8010e001b73a4a38 -Author: Alex Deucher -Date: Mon Jun 9 17:05:04 2008 -0400 - - RS4xx: RC410 chips are actually RS400 based - -commit a54ca3c699c103e2e3df87101dca929a3eee4377 -Author: Dave Airlie -Date: Thu Jun 5 18:31:53 2008 +1000 - - radeon: fix typo in memory calcs - - noticed by ghepeu on irc. - -commit 6e4e6d2a8f29f92efc219dca24ea31d1f37d5a0f -Author: Alex Deucher -Date: Tue Jun 3 20:32:20 2008 -0400 - - RADEON: minor cleanups - -commit 9d3afbf5fa4110928a9f965df2733c79db92ea99 -Author: Michel Dänzer -Date: Tue Jun 3 11:40:49 2008 +0200 - - Call DRM_IOCTL_MODESET_CTL ioctl to avoid problems with DRM post vblank-rework. - -commit effa245914823371e052cd9aa1143a02350891e7 -Author: Alex Deucher -Date: Sun Jun 1 20:47:50 2008 -0400 - - ATOM: disable TV-out for now - - It only sort of works in NTSC mode and isn't handled correctly - in all cases yet. Until we sort out the remaining details leave it - disabled. - See bugs: 16186, 16178, 16185 - -commit 8504c6b0e40477ee544ad7f5366d569bdc53d6f0 -Author: Alex Deucher -Date: Fri May 30 11:19:03 2008 -0400 - - RADEON: update RADEONGetVRAMType() for newer chips - -commit 7cb695a329a9b543ad61af08c2d7d6eaf56de35e -Author: Alex Deucher -Date: Fri May 30 10:10:56 2008 -0400 - - RADEON: add Int10 option - - On some radeons you can't read the bios without initializing int10. - On ATOM-based secondary cards, intitializing int10 tends to hang the card. - -commit 714b2c63ec1c4a1410a6d521c03e9d1f90937c01 -Author: Alex Deucher -Date: Thu May 29 02:31:00 2008 -0400 - - RADEON: don't enable legacy bios table based init yet - - Needs more work and we need to figure out how best to decide - when to use it. - -commit e20b08525a64888287ec4a369d8f7dbde95c655d -Author: Alex Deucher -Date: Wed May 28 14:43:47 2008 -0400 - - ATOM: fail of we are not able to get a bios image - -commit d4fa17b426b0cafac3184b2ea9b675e2ff154ee9 -Author: Alex Deucher -Date: Wed May 28 09:50:02 2008 -0400 - - R1xx: Gamma fixes for overlay - -commit c7e6a50f60a04bbbf1c1ddbf4738a5f75c94f950 -Author: Alex Deucher -Date: Wed May 28 09:05:19 2008 -0400 - - RADEON: only attempt to read vbios from legacy ISA space if it's primary - -commit faea008806802ec0e045754ec1eca492ebae320e -Author: Alex Deucher -Date: Tue May 27 18:36:01 2008 -0400 - - R3/4/5xx: use get_param to get the num_gb_pipes from the drm - -commit 965a5dbcd9dc4bf1cdd7f2bbdec15e9733b2e090 -Author: Alex Deucher -Date: Tue May 27 16:48:41 2008 -0400 - - RADEON: improve support for secondary cards - - this should fix bugs 16115, 16035 - -commit 5f951a5573f0c7572230c9aa4d3f75d67f91ed71 -Author: Alex Deucher -Date: Wed May 21 00:35:14 2008 -0400 - - ATOM: remove duplicate code - -commit edce33e87fb79a540d8c285f205d4c3f2c2bc9f4 -Author: Dave Airlie -Date: Wed May 28 06:43:40 2008 +1000 - - radeon: fix surface access on avivo chips. - - This should fix VT switch on vesafb - -commit 307bd65a25ee425d8359dd30572b002ce2338f91 -Author: Michael Babej -Date: Tue May 27 19:13:49 2008 +1000 - - r600: fix vt switch issue - - RH BZ 441492 - -commit bf48c9eb8ec592515be9d1732d60283af715674d -Author: Dave Airlie -Date: Sat May 24 11:51:20 2008 +1000 - - atombios: for LVDS set use ref div as per legacy - -commit 04500c8419b1aeaeac7968492b82e1d7cad1d05b -Author: Alan Coopersmith -Date: Tue May 20 20:34:31 2008 -0700 - - Strip ^M's from src/AtomBios/includes/ObjectID.h - -commit 521a0488d1c414209c3534dc242000faa332a441 -Author: Alan Coopersmith -Date: Tue May 20 20:33:37 2008 -0700 - - On non-gcc compilers, use C99's __func__ instead of gcc's __FUNCTION__ - -commit b7c80d0c86646105d2bce5d4d59ba6c45aa7cafc -Author: Tobias Diedrich -Date: Tue May 20 19:16:54 2008 -0400 - - R200/R300: fix gamma setup for overlay - - More pending. See bug 16001 - -commit 69423482e2e94637142a9ba675589a1449a346a8 -Author: Alex Deucher -Date: Tue May 20 18:57:13 2008 -0400 - - RADEON: cleanup connection detection and remove duplicate code - -commit 55e4469f59c82bb5762673de5f3f27d18b0bd9a3 -Author: Alex Deucher -Date: Tue May 20 17:46:58 2008 -0400 - - RADEON: enable cloning on multi-crtc cards - -commit 12f185634071980041aaac6265d89708b181b215 -Author: Alex Deucher -Date: Tue May 20 16:05:41 2008 -0400 - - ATOM: Ignore invalid connector entries - -commit 19e97f74e39fc2b35727708ac429de33d0b70162 -Author: Egbert Eich -Date: Tue May 20 11:16:15 2008 +0200 - - Change RMX code to follow the programming algorithm suggested by ATI. - - ATI provides the following algorithm to calculate the RMX scaling ratios - in its programming specs: - when RMX_AUTO_RATIO_HORZ_INC set to 1,Horizontal auto ratio result trucated, - and then incremented by 1. - Horz_Ratio = ( ((Active display width in characters (including overscan) + 1) - / (Panel width in characters)) x 4096 + 1 ) - else - Horz_Ratio = ( ((Active display width in characters (including overscan)) - / (Panel width in characters)) x 4096 + 1 ) - - when RMX_AUTO_RATIO_VERT_INC set to 1, Vertical auto ratio result trucated, - and then incremented by 1. - Vert_Ration = ( ((Active display width in characters (including overscan) + 1) - / (Panel width in characters)) x 4096 + 1) - else - Vert_Ration = ( ((Active display width in characters (including overscan)) - / (Panel width in characters)) x 4096 + 1) - - This patch implements this behavor. Additionally it avoids the use of floats. - -commit a4f3d0088ba763ed8eab1d331959b5ecde8262e8 -Author: Alex Deucher -Date: Tue May 20 11:42:53 2008 -0400 - - R3/4/5xx: fixup logic from last commit - - Spotted by otaylor and MrCooper - -commit 130e55738047f2a073bcc47e3e1400f7b694a81b -Author: Alex Deucher -Date: Tue May 20 11:32:42 2008 -0400 - - R3/4/5xx: fix EXA rotation - - xrandr uses PictOpSrc for rotation which we were falling back on since - render semanties require alpha=0 for REPEAT_NONE when there is no alpha - channel and there is a transform. If the dst has no alpha channel we - should be ok I think. - - Otayler and I discussed this on IRC. the more general fix would be - to clip the dst to the src and mask for bounded ops like in/add/over - in the pixel exact transform case. - -commit cc9f510770700228e5d597c872e926a4e99bd950 -Author: Corbin Simpson -Date: Wed May 14 16:49:01 2008 -0400 - - RADEON: missing stdint.h includes - -commit 71fa57f871dba03260dba2180ce1dab44048ac1a -Author: Alex Deucher -Date: Wed May 14 13:36:38 2008 -0400 - - Add RS600 support - -commit 582c1a1b2c7b1032e9f9f54ca36100c57f580c5c -Author: Alex Deucher -Date: Tue May 13 20:50:25 2008 -0400 - - RS4xx: Split out RS400 and RS480 as separate families - - RS400 (intel based IGP) and RS480 (AMD based IGP) have different - MC setups and need to be handled differently - -commit 708e7c98f636738fbcc47a597bc94b309a4dc1c4 -Author: Michel Dänzer -Date: Tue May 13 11:00:38 2008 +0200 - - Reinstate CARD* types that are part of external interfaces. - - The compiler pointed this out... - -commit 908b7b940e3ef296836bc94680ebb8ab67650e31 -Author: Matt Turner -Date: Mon May 12 12:06:33 2008 -0400 - - Replace CARD{8,16,32} with uint{8,16,32}_t - - As has been done with xf86-video-intel, replace all CARD* datatypes with - uint*_t datatypes available from stdint.h. - -commit 87e66ce76430890ab4939ffcd42f72b9288eb598 -Author: Avi Rozen -Date: Mon May 12 08:33:38 2008 -0400 - - RADEON: fix lockup on start - - see debian bug 480312 - -commit 94bf8f01bd43cb103fffecfe04d04a214f892baf -Author: Dave Airlie -Date: Mon May 12 20:02:51 2008 +1000 - - radeon: fix set_cursor_colours remove fb offset - -commit 1d0f1d31e2ed1d91ee87cb3e02ce48c8c07aa418 -Author: Dave Airlie -Date: Mon May 12 15:44:35 2008 +1000 - - radeon: rs485 vs rs485m.. mobile? non-mobile? bi? - - So it appears we have in the wild two chipsets with the same PCI ID (0x1002:0x5974) - that are mobile and non-mobile. - - the RH bug references is a desktop system. - The Dell Vostro 1100 also has this chipset with LVDS bits. - -commit 25e0c3945a51ae8c14b3a847ec75a256e1397f24 -Author: Alex Deucher -Date: Mon May 12 10:28:33 2008 +1000 - - radeon: add initial support for cloning outputs. (single-CRTC cards only) - - airlied - This code was originally written by Alex, and I've modified it to - only run on single-CRTC cards for now until we can test it some more. - -commit 94405eb1c9e4e0ababc6aef03b753d6ed9eb7838 -Author: Alex Deucher -Date: Fri May 9 05:28:44 2008 -0400 - - RADEON: fixup ifdef from last commit - -commit 18e20bc22a55ecfee9798c01079d7b24d19f0051 -Author: Alex Deucher -Date: Thu May 8 08:45:51 2008 -0400 - - RADEON: disable MMIO paths for EXA composite/texvid on IGP/R5xx - - The MMIO paths eventually lead to a hang on r5xx/IGP. I haven't - been able to find out why yet. - -commit c3532268875fd24e6519bea2fb1b814d612bbdb4 -Author: Dave Airlie -Date: Wed May 7 02:37:18 2008 +1000 - - radeon: fix zaphod EXA with texture video - -commit ffc437f3606ab8ceba1ff152e4bb08988a58b54c -Author: Dave Airlie -Date: Wed May 7 02:30:28 2008 +1000 - - avivo: fix zaphod cursor in theory - -commit e36ef14e3a1087e1fe41baa26ade2937f396001f -Author: Dave Airlie -Date: Wed May 7 01:39:28 2008 +1000 - - radeon: fix textured-xv on zaphod - -commit 8fc19bee27c0f151d2ab3354f6ac0992b358436d -Author: Dave Airlie -Date: Wed May 7 01:38:24 2008 +1000 - - radeon: zaphod: fix render accel for EXA - -commit fc41b9042a5220a8419cc7b69ca3850cae6b903c -Author: Dave Airlie -Date: Wed May 7 01:32:23 2008 +1000 - - radeon: fix EXA pixmap offset on zaphod - -commit 4568cb820d567c6909a4be956d7e79b91232535e -Author: Dave Airlie -Date: Wed May 7 01:19:39 2008 +1000 - - radeon: zaphod fixes for pciaccess not allowing multiple MMIO maps - -commit ca81fa086b21633a7fd926833fb6d1d4fa080646 -Author: Dave Airlie -Date: Wed May 7 01:12:01 2008 +1000 - - radeon: zaphod fix for cursor on second head - - We don't need to add fbOffset here as the mmap we have of the framebuffer - starts half way. - -commit 24b60c8965f6a0b3f0c2bb1e7236b4d6642c5918 -Author: Julien Cristau -Date: Fri May 2 15:30:45 2008 -0400 - - Add a test for __GLIBC__ to CD_Common_Types.h. - - Atombios redefines the standard types but the definitions conflict - with the ones from glibc (causes build failures on GNU/Hurd - and GNU/kFreeBSD). - -commit f051359ac09c6b9416e39b9ca7d9dc0880aa1557 -Author: thegraze -Date: Fri May 2 14:02:16 2008 -0400 - - ATOM: add support for DragonFlyBSD - -commit 3d469cbc3225d890a895dac7cbc1ab7e08054b48 -Author: Alex Deucher -Date: Wed Apr 30 18:33:04 2008 -0400 - - RADEON: lock the cursors when updating - - this should fix occasional corruption seen when updating - the cursor. - -commit 445b71021843665ba32f37b2ce5c9d2857c07cc7 -Author: Alex Deucher -Date: Tue Apr 29 21:01:41 2008 -0400 - - RADEON: assorted fixes - - - free rotate pixmaps on VT switch - - save crtc/output status so we only turn on - crtcs/outputs if they are off - - show/hide cursors when changing modes - -commit 070cce5255a5c311f9d8b85ec54bd56655014933 -Author: Stephan Wolf -Date: Mon Apr 28 11:26:37 2008 -0400 - - R3xx+: further fix for IGP chips - - see bug 15538 - -commit 211e0041c7fc2df494b77428553943a2b526ee4e -Author: Alex Deucher -Date: Sun Apr 27 21:08:00 2008 -0400 - - IGP: fix EXA composite corruption - -commit 656b06bdde129ca4fc370f5a2cf7311c9179b0ff -Author: Alex Deucher -Date: Sun Apr 27 20:20:49 2008 -0400 - - RADEON: remove duplicate register define - - Also add more bit defs to wait_until register - -commit 8a9820a3aa49bc667f90ac291a27e4d7b4ae38b3 -Author: Alex Deucher -Date: Sun Apr 27 19:02:22 2008 -0400 - - RADEON: decrease crtc/output verbosity - -commit c5d62fa0e8f52c3264ff9db3ff10cdf5a806bfc0 -Author: Owen Taylor -Date: Thu Apr 17 13:14:53 2008 +0200 - - Emulate repeats by drawing in tiles - - When we can't turn on hardware repeats, because the texture - is non-power-of-two, or has padding at the ends of lines, - try to draw the image in multiple tiles rather than falling - back to software. (We can only do this when there is no - transform.) - -commit eeb7b74bb6c813b0e3afa4b704f6ffb0d0aab92b -Author: Owen Taylor -Date: Thu Apr 17 13:14:25 2008 +0200 - - Turn on wrapping when repeating on R100 + R200 - - Actually enable repeats for R100 and R200. This corresponds - to a R300 change made in the patch in: - http://bugs.freedesktop.org/show_bug.cgi?id=15333 - -commit e511f39dfef503006cf249b9f6934091eaade9b5 -Author: Alex Deucher -Date: Thu Apr 17 05:04:34 2008 -0400 - - R300+: move more common code into init3d() - - - pre-load r3xx tex instructions - - setup RS instructions in init3d() - -commit 99435b7c18d931ea620044d0fdb4cc93dfcc6331 -Author: Owen Taylor -Date: Thu Apr 17 02:46:11 2008 -0400 - - Radeon: Omit mask coordinates - - Adapted from Owen's patch on bug 15546 - This fixes the slowness with aatext on r300 - and may speed up other chips marginally. - -commit 37614e1db9a595fbe8a21d7a045895e11d272db9 -Author: Alex Deucher -Date: Tue Apr 15 09:48:16 2008 -0400 - - fix up some things from the last commit - -commit 1286fe5ce1c77453d57817b9b26b1bdb32ca7bc8 -Author: Alex Deucher -Date: Mon Apr 14 20:02:14 2008 -0400 - - R300+: properly setup vap_cntl - - this fixes tcl/pvs on RV515 among other things - -commit f72a4b805db26f10f69330b88459cbeae661189b -Author: Alex Deucher -Date: Mon Apr 14 14:10:40 2008 -0400 - - EXA: Don't wait for 3D idle after each Composite() - - wait in CompositeDone() instead - -commit 4cd4acf1092aeb696b086a382a033aee471d2de9 -Author: Alex Deucher -Date: Mon Apr 14 11:50:59 2008 -0400 - - R300: move more common code to init3d() - -commit 3c523c9a07402e17dff588fad842224c57e98223 -Author: Alex Deucher -Date: Mon Apr 14 11:21:42 2008 -0400 - - R3xx+: 3D engine documentation and minor cleanups - - - document the R300 exa/textured video code - - minor cleanups of textured video code to clarify meaning - -commit ce025bbb2496d4de94b8d4ac450c64441b64ee04 -Author: Alex Deucher -Date: Sat Apr 12 21:22:03 2008 -0400 - - R300+: consolidate some tcl/non-tcl paths - - - Move more code to init3d() - - MMIO textured video seems more reliable now on newer chips - -commit 11b54a319c7c9dd52e3fb13372697059dafe1cd3 -Author: Alex Deucher -Date: Sat Apr 12 16:50:22 2008 -0400 - - R3xx+: fix XAA + textured video on non-TCL path - -commit dd15a2f5906725116b8cd9954243099055e88e37 -Author: Alex Deucher -Date: Sat Apr 12 16:49:03 2008 -0400 - - R3xx+: more fixes to 2D/3D engine init - -commit f3e68d4b7afd2e23675bf6361c496814c9cb4b94 -Author: Alex Deucher -Date: Fri Apr 11 10:59:07 2008 -0400 - - Fix exa glyph corruption on newer chips - -commit b59686d6427cbf8b35e36b020cbbc6a0c5149b22 -Author: Alex Deucher -Date: Fri Apr 11 10:15:25 2008 -0400 - - R300+: pre-load vertex programs in init3D() - -commit acc5833a35ad6c29a57f659607afb27eebdc2ea5 -Author: Alex Deucher -Date: Thu Apr 10 17:52:52 2008 -0400 - - R3xx+: consolidate more tcl code - -commit 6f8f75bd19ef1919c0291141675be2d0e29b3251 -Author: Alex Deucher -Date: Thu Apr 10 17:08:50 2008 -0400 - - R3xx+: consolidate some common 3D code - -commit 4b9234e1c4f7c7f419cb4245d64f3f9756c98bb6 -Author: Alex Deucher -Date: Thu Apr 10 16:58:22 2008 -0400 - - R3xx+: tcl wip - -commit 865c463e3afb4759758f569132be8bf1386da5cc -Author: Alex Deucher -Date: Thu Apr 10 16:51:04 2008 -0400 - - R300+: textured video tcl cleanup - -commit 79c8d4ca36a1c3e5fe759d4ccc379c36af8f1676 -Author: Alex Deucher -Date: Thu Apr 10 16:28:18 2008 -0400 - - RADEON: cleanup - -commit c4821a287d29a65f3bcb7d60dc72ec13c0384008 -Author: Alex Deucher -Date: Thu Apr 10 16:20:17 2008 -0400 - - Revert "R3xx/R5xx: move more VAP, etc. state setup into common init3d() function" - - This reverts commit 305a3310963a5dd07b3495015b06aa8c7c4e6b02. - - Conflicts: - - src/radeon_commonfuncs.c - src/radeon_exa_render.c - src/radeon_textured_videofuncs.c - -commit 0032c80bf30bab189204e3e6929e18a19d753138 -Author: Alex Deucher -Date: Thu Apr 10 14:35:00 2008 -0400 - - RADEON: store tcl status in driver rec - -commit 9e2ffe66d106abe34a670d2edc9905ed62c485e8 -Author: Alex Deucher -Date: Thu Apr 10 14:24:04 2008 -0400 - - R3xx+: use the right register for engine flush - -commit e1a9f26c2d2cbca9ad159e723ec95b95be1ef349 -Author: Alex Deucher -Date: Thu Apr 10 14:12:15 2008 -0400 - - R3xx+: minor textured video fixes - - - set shader output swizzling correctly - - flush the right cache register on r3xx+ - -commit d79040906cd25bd494feb5901f465bbd050aa923 -Author: Alex Deucher -Date: Thu Apr 10 13:59:58 2008 -0400 - - R3xx+: EXA/textured video fixes - - - get pipe config based on GB_PIPE_SELECT where applicable - (adapted from a similar patch from Dave) - - only flush the dst cache after submitting vertices, freeing - the cache lines stalls the pipe - - no need to wait for 3D idle after submitting vertices - - fix PURGE_CACHE() and PURGE_ZCACHE() for r3xx+ - - fix depth 16 with EXA composite - -commit 0a96173cc38e506728d4c3f2dd383ba56e856578 -Author: Michel Dänzer -Date: Mon Apr 7 18:15:34 2008 +0200 - - Increase default CP timeout. - - Helps avoid spurious timeouts causing problems, see - http://bugs.freedesktop.org/show_bug.cgi?id=15203 . - -commit 255fbf465f5e7db2609a5a151bfa810249db52a0 -Author: Owen W. Taylor -Date: Thu Apr 3 02:25:41 2008 -0400 - - Fix rendering of transformed sources for REPEAT_NONE with EXA on >= R300. - - Use the border color when possible, otherwise fall back to software. - -commit bc0407e53237d7968808110bc0243076377acf6e -Author: Alex Deucher -Date: Fri Apr 4 18:40:16 2008 -0400 - - ATOMBIOS: Add support for DynamicClocks option - - This patch adds support for dynamic clock gating and static - power management using the atom command tables. In some cases - the bios may already set this up during post, so YMMV. - - I was only able to test on desktop cards, so I haven't tested - to see how much (if any) power this saves or how it affects the - thermal footprint. - -commit 5f5e21bb50555c56bd371576074c28c929307ff1 -Author: Alex Deucher -Date: Fri Apr 4 14:29:45 2008 -0400 - - RADEON: warning fixes - -commit c8e9a973aaded24aad567a0e36d0c78a05d6b2fd -Author: Alex Deucher -Date: Fri Apr 4 14:26:19 2008 -0400 - - RADEON: add some quirks - -commit 091963a635b79884afe77c026eabb48972fbe175 -Author: Alex Deucher -Date: Thu Apr 3 22:35:16 2008 -0400 - - Minor cleanup - -commit 950e9860643c20acde0eca4e4ff26baacc1f2b69 -Author: Alex Deucher -Date: Thu Apr 3 22:11:48 2008 -0400 - - Revert "RADEON: memmap rework 1" - - This reverts commit dd8ee1b444f4b973a1e0fadca5f943f2162b5e94. - - Conflicts: - - src/radeon.h - src/radeon_driver.c - - This rework seems to have caused more trouble than it was worth. - -commit 88a1fe4a94c5d11aff22734b21c89890e4428cd5 -Author: Alex Deucher -Date: Thu Apr 3 22:04:43 2008 -0400 - - Revert "RADEON: remove driver rec copies of mc info, use save rec directly" - - This reverts commit be0858a84fbdf74c0b844f462933a221d48c707d. - - Conflicts: - - src/radeon_driver.c - -commit c40a7aa3989576a8144213e2f31b892d21df8686 -Author: Owen W. Taylor -Date: Thu Apr 3 14:43:55 2008 -0400 - - R3xx/R5xx: Fix pitch and clamp mode for repeating textures - - - We can always use TXPITCH on a R300 even when repeating, - (previous check for pitch matching width was also wrong) - - Fix clamp mode for repeating textures to be WRAP - -commit a8593482c1f2e0f2dbac06c2e5325ba8c83ed9ff -Author: Dave Airlie -Date: Wed Apr 2 09:58:05 2008 +1000 - - atombios: fix the dual-head hopefully. - - tested on r600 with DVI and VGA - -commit 61d883d116fab3e9b513432d65e705afc5bb39f1 -Author: Dave Airlie -Date: Wed Apr 2 09:57:38 2008 +1000 - - Revert "Revert "atombios: fixup the width/height to use the mode values not the scrn ones"" - - This reverts commit fc9af578997b6f22ee8b17e83f37d98689291b0e. - - I see your revert and raise you one... - -commit fc9af578997b6f22ee8b17e83f37d98689291b0e -Author: Alex Deucher -Date: Tue Apr 1 09:25:45 2008 -0400 - - Revert "atombios: fixup the width/height to use the mode values not the scrn ones" - - This reverts commit c2b1c8b706a6c7c1fd0af80091958473133d54e7. - - These registers hold surface size. Using the mode values - breaks dualhead. - -commit 959509dd54de053f526b534e379a46934127231f -Author: Dave Airlie -Date: Mon Mar 31 14:29:44 2008 +1000 - - radeon: use correct DDC interfaces so quirks get applied - - Radeon seemed to mess up applying certain quirks, hopefully this will fix it. - -commit 18f5f1cd2f52afed89fc11ade0920f3dfea87306 -Author: Dave Airlie -Date: Mon Mar 31 14:11:49 2008 +1000 - - radeon: split quirks into separate function and new quirk for IBM RN50 - - Add a connector table quirk for the IBM RN50. - -commit c2b1c8b706a6c7c1fd0af80091958473133d54e7 -Author: Dave Airlie -Date: Sun Mar 30 11:44:14 2008 +1000 - - atombios: fixup the width/height to use the mode values not the scrn ones - - this fixes it properly, legacy appears to be okay. - -commit c5edea3d8c9254d3a21e390b8309e39e4c9635db -Author: Dave Airlie -Date: Sun Mar 30 11:11:22 2008 +1000 - - r500/r600: fix rotation to fill screen - - I'm not 100% sure this is the correct fix (maybe we shouldn't be using scrn - virtualX/Y)... this will fix it for now until I get more time. - -commit 9c62c820ba45ebc14d5f36f5d7885863800b6adb -Author: Michel Dänzer -Date: Fri Mar 28 12:37:29 2008 +0100 - - Include config.h, so FGL_LINUX can actually be defined when it's tested... - -commit a00d9260a85b94a522c442aee24bc5ea4dc31c5c -Author: Alex Deucher -Date: Thu Mar 27 20:03:13 2008 -0400 - - RADEON: fix lid issues on AVIVO chips for real this time :) - -commit f0e89c09074b2c7e641f73692bb39b0bf68eb49c -Author: Alex Deucher -Date: Thu Mar 27 19:15:18 2008 -0400 - - Revert "RADEON: attempt to fix lid issues" - - This reverts commit 9b4473c1d830b88866dd22e8174a07195bd6fcf4. - This doesn't help. - -commit 1442d396b938049b83f009a78ddabe2bf85641b6 -Author: Dave Airlie -Date: Thu Mar 27 14:02:51 2008 +1000 - - radeon: size bios to max of bar vs 64k. - - reported by dwmw2: rhbz 438299 - -commit de2f609ff0004ef8b74727bfebc2c74fb91205ea -Author: Alex Deucher -Date: Wed Mar 26 18:35:21 2008 -0400 - - AVIVO: no need to call PreinitXv() on AVIVO chips as they have no overlay - -commit 75884c257bc2bcfa5b498a77d4c403f09face036 -Author: Alex Deucher -Date: Wed Mar 26 18:16:47 2008 -0400 - - XAA: update message about render so as to not confuse users - -commit 9b4473c1d830b88866dd22e8174a07195bd6fcf4 -Author: Alex Deucher -Date: Wed Mar 26 18:01:29 2008 -0400 - - RADEON: attempt to fix lid issues - - On some laptops the bios attempts to re-program the chip - when a lid event comes in. This should hopefully prevent - the bios from doing that. - -commit 8b144830fe9b4a0cee4745023de5e7d387070f60 -Author: Alex Deucher -Date: Tue Mar 25 01:15:05 2008 -0400 - - RV250: disable textured video due to HW bug - - The YUV->RGB conversion in the texture engine is broken - on RV250 so the colors come out wrong. - -commit 1789f11ab91633d3928f8b71988d51ff44bda9d1 -Author: Alex Deucher -Date: Mon Mar 24 19:03:30 2008 -0400 - - R3xx/R5xx: flush PVS state before enabling pvs-bypass - -commit 305a3310963a5dd07b3495015b06aa8c7c4e6b02 -Author: Alex Deucher -Date: Mon Mar 24 14:25:03 2008 -0400 - - R3xx/R5xx: move more VAP, etc. state setup into common init3d() function - - Also some minor code cleanups - -commit 399b1d405e602c62d6deebea6d7e1f38886cd8e2 -Author: Alex Deucher -Date: Mon Mar 24 13:04:57 2008 -0400 - - R3xx/R5xx: use non VAP/TCP for textured video - - Just extra state to emit. - -commit cd77ec18f32a7b36acb655c927bbfd7044019f97 -Author: Dave Airlie -Date: Mon Mar 24 18:42:21 2008 +1000 - - r300: don't bother with VAP/TCL for render. - - We just send more data to the card to process per transaction, without getting - any actual gains, as we already pre-compute the vertices without needing - any clipping or transforms from the card. - - Perhaps some stuff could be done on-card, but so far the code is a lot - faster if we avoid sending this extra info. - - pre: 150000 glyphs/sec - post: 185000 glyphs/sec - -commit 301c6739b88676a0c78fc72194e993f894b8dc28 -Author: Alex Deucher -Date: Sun Mar 23 11:14:02 2008 -0400 - - RS4xx: Revert back to previous fifo settings for now - - Setup of these registers needs more investigation. - -commit 9bea60b3eb378de5e1d44cc02a2763f4feae7882 -Author: Alex Deucher -Date: Sat Mar 22 11:46:15 2008 -0400 - - RS4xx: more work on disp/disp2 fifo setup - -commit 90f11c3986c28daa7b600b9662da145af325d264 -Author: Alex Deucher -Date: Sat Mar 22 11:29:51 2008 -0400 - - RS4xx: missed this on the last commit. - -commit 6d5066a451017a2683addc9e2496987626795dda -Author: Alex Deucher -Date: Fri Mar 21 16:21:54 2008 -0400 - - RS4xx: attempt to set up disp/disp2 fifos correctly - - If you have an XPRESS chip, please test!!! - -commit fb1cffac05ae20c8365b25a2042b0ae961880faf -Author: Alex Deucher -Date: Fri Mar 21 15:24:36 2008 -0400 - - RS4xx: attempt to fix TMDS/DVO support - - XPRESS chips added a second set of FP control registers. - I don't have the hw to test however. - -commit 5e3b21284482df9974c9a58f248f0100def2bb0c -Author: Alex Deucher -Date: Wed Mar 19 19:15:05 2008 -0400 - - Disable the setting of HARDWARE_CURSOR_BIT_ORDER_MSBFIRST - - See bug 11796 - -commit 17cd42ed31814ba329a6a68edd0d75390a7da40e -Author: Matt Turner -Date: Wed Mar 19 18:17:10 2008 -0400 - - Enable BSR in Log2 functions - - This patch edits RADEONLog2 and ATILog2 to use the x86 BSR instruction instead - of looping through bits. It should provide a somewhat of a speed increase in - this function on x86 and AMD64 architectures. - - Note: the BSR instruction was added with the 80386 CPU and is therefore not - compatible with earlier CPUs, though I highly doubt it's even possible to use a - 286 in conjunction with a Radeon. - - The inline assembly also works with Intel's compiler (icc). - -commit c83827b4d2b6f03c54429e757a756eb99ff8be6b -Author: Paulo Cesar Pereira de Andrade -Date: Wed Mar 19 17:58:34 2008 -0400 - - [PATCH] Compile warning fixes. - - Minor changes to avoid declarations mixed with code. - Ansified functions with empty prototype to specify they don't - receive arguments. - Added some prototypes to radeon.h, and major reorder on radeon.h - adding prototypes in alphabetical order and specifying to file that - defines it. - -commit bed9754ad21d6c0a7f61067b04ba31c430a7cecb -Merge: 55e446b... f71ac0e... -Author: Alex Deucher -Date: Wed Mar 19 16:06:41 2008 -0400 - - Merge branch 'master' of ssh://agd5f@git.freedesktop.org/git/xorg/driver/xf86-video-ati into r3xx-render - -commit 55e446b5bc091e6c7b3c2e9ae20b45130555c246 -Author: Alex Deucher -Date: Wed Mar 19 13:15:32 2008 -0400 - - R3xx/R5xx: Make sure to clamp the output of the FS - -commit b6aa4279cbe68cc8e4523795e9714fb798b62d98 -Author: Alex Deucher -Date: Wed Mar 19 12:45:01 2008 -0400 - - R5xx: bump textured video limits to 4096 - -commit 4a445a3e8c4c5ecd9d4ef8daa26906c3ceaa94a1 -Author: Alex Deucher -Date: Wed Mar 19 12:31:51 2008 -0400 - - RADEON: add new macros to distinguish between R3xx and R5xx 3D - -commit 85d0c9e8d22ccc72bec87b3fd44da5d7609293e0 -Author: Alex Deucher -Date: Wed Mar 19 12:07:33 2008 -0400 - - RADEON: fixed textured video with XAA and tiling - -commit f5951db7b3522e0fe6af7f46a170c9c9a60a9bff -Author: Alex Deucher -Date: Wed Mar 19 12:01:50 2008 -0400 - - RV515: fix textured video and EXA Composite - - There seems to be an issue with the PVS setup on RV515, but - bypassing it seems to work fine. - -commit 13573879fe56368ad06234712b677c23fabc56c6 -Author: Dave Airlie -Date: Wed Mar 19 15:06:47 2008 +1000 - - r500: make it work from startup. - - I'm not sure why this worked or what is going wrong here, really the - VAP internal architecture escapes me :) - -commit d331dd64d644a18ec99a2136cd0943b5edca1f03 -Author: Alex Deucher -Date: Tue Mar 18 19:44:26 2008 -0400 - - R3xx/R5xx: remove extra return after last commit - -commit bc34df7a9c35cdd38c49d5c22471f3f487a33d6e -Author: Alex Deucher -Date: Tue Mar 18 19:39:47 2008 -0400 - - R3xx/R5xx: switch an ErrorF() to RADEONFALLBACK() - -commit 6f03f8fe0ecf4181dcf125049cf63bece0451fb2 -Author: Alex Deucher -Date: Tue Mar 18 19:36:05 2008 -0400 - - R3xx: we only use 2 temps, not 3 - -commit 8bb71ab4a3eb4fb6ef7f709e87c8df387cb70ee3 -Author: Tilman Sauerbeck -Date: Tue Mar 18 14:36:08 2008 -0400 - - R3xx/R5xx: fix up a8-src-something_with_colors - -commit c362591d9b496df30668543158e4de44de742dc3 -Author: Alex Deucher -Date: Tue Mar 18 11:15:17 2008 -0400 - - R3xx/R5xx: remove some cruft - -commit 89fe6d2c7d7471e6088558130f6e49f46c31dd47 -Author: Dave Airlie -Date: Tue Mar 18 09:43:43 2008 -0400 - - R5xx: fix typ in r5xx render accel - - This gets render working on r5xx - -commit 79b40ebcd8dedfc83e484c1024beeeaccc6124f3 -Author: Alex Deucher -Date: Tue Mar 18 02:46:49 2008 -0400 - - R5xx: first pass at render support (untested) - -commit 71292c8f193230255d1d980c2e996bb01d04fab6 -Author: Alex Deucher -Date: Tue Mar 18 00:45:37 2008 -0400 - - R5xx: bump tex/dst limits to 4096 - -commit 30b52f8aa6a471455284f59b5b27252743892b13 -Author: Alex Deucher -Date: Mon Mar 17 23:20:10 2008 -0400 - - R3xx/R5xx: whitespace cleanup and cruft removal - -commit 9c9f1b538ed710c3066775fba0a8e936b63087b1 -Author: Alex Deucher -Date: Mon Mar 17 23:01:37 2008 -0400 - - R3xx: get masks working and cleanup - - RS offset was wrong for mask texture - -commit ef94febd74f8ee63081b61e42f093a5a2b8fbf1e -Author: Alex Deucher -Date: Mon Mar 17 22:27:19 2008 -0400 - - R3xx: minor adjustments - -commit f71ac0e40b9d950bcb3bba42a75d41f45b6ed1bf -Author: Alban Browaeys -Date: Mon Mar 17 20:48:48 2008 -0400 - - RADEON: Revert to old behavior when resetting the memmap on VT switch - - Not sure why this needs to be done twice. Should fix bug 14980 - Probably needs more investigation. - -commit bedbbf196dc97ee5142e7dfae16fb6f317fca5a7 -Author: Alex Deucher -Date: Mon Mar 17 20:16:25 2008 -0400 - - R3xx: some progress - -commit af0e626c132de2dd9958fec657fcc85d4c0fe5e1 -Author: Alex Deucher -Date: Mon Mar 17 18:07:12 2008 -0400 - - R3xx: fix errant w - -commit 29ea5bfc0eb3194e2454fc3ee863df54f0300880 -Author: Alex Deucher -Date: Mon Mar 17 16:41:57 2008 -0400 - - RADEON: fix typo in RADEONAdjustMemMapRegisters() - -commit ab317e85c5ab1a249a510c34aeb3a908be1a66fc -Author: Alex Deucher -Date: Mon Mar 17 15:28:09 2008 -0400 - - RADEON: make sure var is initialized properly in RADEONAdjustMemMapRegisters() - -commit 208d307227e15f37a6af5194398ed23266ff743a -Author: Dave Airlie -Date: Sun Mar 16 19:39:23 2008 +1000 - - radeon: the 0x5974 appears to be a mobility chip... - - After debugging with partymola on #radeon, adding this allowed his - Dell Vostro 1000 to work properly - -commit 9bc7c2ec4048e1677547c1d60c51ccb954f7589a -Author: Alex Deucher -Date: Fri Mar 14 20:12:22 2008 -0400 - - R3xx: odds and ends... - - still not working. - - swizzle US output for BGR formats - - no need to write to temps in ALU ops, - write to output only - - flush the PVS before updating - -commit 96bea7906c4706fcd57a9cd8f1ce3feab6ac676d -Author: Alex Deucher -Date: Fri Mar 14 15:59:36 2008 -0400 - - R3xx: theoretical support for component alpha - - masks are still broken so... - -commit cffe3dcc8991cd7c457a9c1a9f41055aa9ea3436 -Author: Alex Deucher -Date: Fri Mar 14 14:37:43 2008 -0400 - - R3xx: VS WIP - -commit b73f52a50dfd6ff8d92f04d6b510c39582c6ac67 -Author: Alex Deucher -Date: Fri Mar 14 14:20:49 2008 -0400 - - R3xx/R5xx: enable VS for mask texture - -commit 569a14ca9be1e18fe9921edc816ac3dc32d6cca7 -Author: Alex Deucher -Date: Fri Mar 14 13:32:12 2008 -0400 - - R3xx/R5xx: Fix magic numbers in vertex shaders - -commit 4878997529601d62e257aa1c9112bd460561de73 -Author: Alex Deucher -Date: Thu Mar 13 21:23:40 2008 -0400 - - R3xx: make sure to set the FS code size correctly - -commit 22f46b88ef05afb6a6b6d70007ac4980a446430e -Author: Alex Deucher -Date: Thu Mar 13 20:25:33 2008 -0400 - - R3xx: attempt to setup the rasterizer properly for mask texture - - Not working yet - -commit 081fc9e892fa3d2e07b7db65b2e2719646255463 -Author: Alex Deucher -Date: Thu Mar 13 18:38:26 2008 -0400 - - R3xx: more mask work - -commit 2bf0236c03538ace3ce6d0e68f0829fc47d1385b -Author: Alex Deucher -Date: Thu Mar 13 18:32:00 2008 -0400 - - R3xx: enable composite for non-mask cases - -commit 74286ba41302107d2fc626fee2181f7c4bc18164 -Author: Alex Deucher -Date: Thu Mar 13 18:25:32 2008 -0400 - - R3xx: add basic mask support - -commit a2bbe10d866567911b68f222b4758624bfe9bf84 -Author: Alex Deucher -Date: Thu Mar 13 18:16:53 2008 -0400 - - R300: setup source selects and output swizzling - -commit b9974ecce7d1932595226004858b08a7a6b188dc -Author: Alex Deucher -Date: Thu Mar 13 17:35:38 2008 -0400 - - R3xx: set the texture id and add some register info - -commit 0ef700b7da5e554a0d0d166f3fde85ff45c9eb1f -Author: Alex Deucher -Date: Thu Mar 13 17:02:25 2008 -0400 - - R3xx/R5xx: enable blending - -commit b35c09a597c93a1d9f06ef0091c96822b0653f98 -Author: Dave Airlie -Date: Thu Mar 13 18:42:29 2008 +1000 - - xv: fixup XAA on r500 textured video - - the XAA area should never end up tiled. This may break with nooffscreen pixmaps - -commit d4446461c3630caff166456c351ace34f57cc119 -Author: Matt Turner -Date: Tue Mar 11 21:20:53 2008 -0400 - - Properly fix uninitialized variables warnings - - According to commit 9fd13e6773371c82b9799a5bda7c96ffa5cafe8c to - xf86-video-intel by Kristian Høgsberg, there is a better way to fix the - possibly initialized variables warnings. This patch will use Kristian's fix. - -commit 20adfd7390d9b1f100e0c4a14f175377b8335c82 -Author: Alex Deucher -Date: Tue Mar 11 20:09:35 2008 -0400 - - RADEON: enable output attributes that require a modeset immediately - - This should fix bug 14915 - -commit 53ba7f5771b0b53fb0d3bc29d64bdd3813756d10 -Author: Alex Deucher -Date: Tue Mar 11 19:12:40 2008 -0400 - - RADEON: fix vblank interrupts after VT switch or suspend/resume - -commit e946c097f0438afbea6f3dd37ee39d67d415708c -Author: Matt Turner -Date: Tue Mar 11 19:07:58 2008 -0400 - - [PATCH] Fix a few warnings - -commit 8e160508520c0a24ca90aad182f296461ca0d9b6 -Author: Alex Deucher -Date: Tue Mar 11 18:11:13 2008 -0400 - - DCE3: add support for PCIEPHY (untested) - -commit fbded88a2925f9f049936dad0736721e7b84a6ee -Author: Alex Deucher -Date: Tue Mar 11 14:10:31 2008 -0400 - - ATOM: remove some cruft - -commit 3263f6e4a410281d620c288a92bb4521f7b6fc06 -Author: Alex Deucher -Date: Tue Mar 11 14:05:48 2008 -0400 - - DCE3: enable DPMS on DIG ports - -commit eb90e235b58c94f3d4d75394725ab2fe246a42ff -Author: Alex Deucher -Date: Tue Mar 11 13:53:54 2008 -0400 - - DCE3: adjust PLL for DCE3 chips - - this fixes stability issues on digital outputs and certain modes. - -commit 552615ccc5360baafb8bb41698c1ca27816fd4b2 -Author: Alex Deucher -Date: Tue Mar 11 13:38:29 2008 -0400 - - ATOMBIOS: enable load detection by default on both DACs - - Load detection is reliable with atom, so enable it by default - on both DACA and DACB, rather than just DACA. - -commit 78b10487cf222c96f8944ba25e2ea970506b3535 -Author: Alex Deucher -Date: Tue Mar 11 13:16:00 2008 -0400 - - DCE3: add output attribute to enable/disable coherent mode - - Enabled by default. The TMDS transmitter can be programmed - slightly differently depending on the chips in the panel. If you - have problems with tmds on a particular panel, try disabling it. - -commit d20be31c46fbec623af4c3628a7c603ceacf500f -Author: Alex Deucher -Date: Mon Mar 10 21:05:43 2008 -0400 - - RV550: MC setup is like RV515 not RV530 - -commit 38606b08b68842fbcc81c233009c1117269f3be9 -Author: Matthieu Herrb -Date: Sat Mar 8 23:22:59 2008 +0100 - - Makefile.am: nuke RCS Id - -commit 9d710ee1a44cf2f3a948fbdbe17ef09521cbe744 -Author: Alex Deucher -Date: Fri Mar 7 15:09:14 2008 -0500 - - AVIVO: clean up some unused variables - -commit c28c30c9f3d7bfebfd56a5c982c96f0090982054 -Author: Alex Deucher -Date: Fri Mar 7 14:10:49 2008 -0500 - - RADEON: Fix crash in last commit - -commit c3a3635865e380c784a226c8ead069d4716d6b75 -Author: Dave Airlie -Date: Thu Mar 6 20:17:45 2008 -0500 - - RADEON: fix tiling/interlaced interaction with randr 1.2 - -commit df1b94dc4eb1f35b636dbf2ec0ab1c2da9937c0d -Author: Alex Deucher -Date: Thu Mar 6 19:22:08 2008 -0500 - - DCE3: Ignore outputs with DIN connectors for now - -commit cb2dc19387c7b6494c47c76d683cf38a48700768 -Author: Alex Deucher -Date: Thu Mar 6 18:33:12 2008 -0500 - - AVIVO: fix typo from a previous commit - - Leave tv dpms hook disabled or you may get bad interactions - with the shared DAC - -commit 77355de48057e5e7e0d5b3f3cf5a7a92220a53b1 -Author: Alex Deucher -Date: Thu Mar 6 17:46:00 2008 -0500 - - AVIVO: don't add outputs for invalid connectors - -commit 600dbe080997a01ceaf6be86723189d518bc1281 -Merge: 594743a... 5b7875d... -Author: Alex Deucher -Date: Thu Mar 6 17:31:37 2008 -0500 - - Merge branch 'master' of ssh://agd5f@git.freedesktop.org/git/xorg/driver/xf86-video-ati - -commit 594743a99811a8b0f391412892414fcd158eeb56 -Author: Alex Deucher -Date: Thu Mar 6 17:30:21 2008 -0500 - - AVIVO: fix up memsize detection for IGP chips - -commit 5b7875d0cbfbdbcd1515c4e942d30de298b49dff -Author: Doug Chapman -Date: Thu Mar 6 14:31:06 2008 -0500 - - Bug #14826: Fix a bogus check around xf86SetOperatingState. - -commit 651fe23f4c650ed91843dec48db24e18e8b91219 -Merge: 3de2dc8... 766f464... -Author: Adam Jackson -Date: Thu Mar 6 14:28:27 2008 -0500 - - Merge branch 'master' of git+ssh://git.freedesktop.org/git/xorg/driver/xf86-video-ati - -commit 41171c25cd235bafad26bcbabced16ead4b8c54b -Author: Alex Deucher -Date: Thu Mar 6 14:05:18 2008 -0500 - - DCE3.0: add support for crtc memreq table - -commit 766f464dfdfccadef23e4232f2bce5db22195513 -Author: Alex Deucher -Date: Thu Mar 6 13:35:43 2008 -0500 - - RADEON: take 2 on proper pragma pack support for bsds - - See bug 14594. Based on suggestion by Henry Zhao - -commit a842ce9ca6494e724a7828cead9b61c9ef02b6aa -Author: Alex Deucher -Date: Thu Mar 6 12:32:18 2008 -0500 - - DCE3.0: Minor fixups - -commit 8a1ba374033591c725a78923aa30829e4de2a5ae -Author: Alex Deucher -Date: Thu Mar 6 09:53:51 2008 -0500 - - RADEON: option to override TVDAC adj values from bios with driver defaults - - If you have a washed out image on the tv dac, try this option. - Option "DefaultTVDACAdj" "TRUE" - -commit 0ed48f8f651a28e189f9fee8c6b593da0178d21c -Author: Alex Deucher -Date: Wed Mar 5 18:41:01 2008 -0500 - - AVIVO: Initial support for DCE 3.0 using atombios - - DACs are working well, DIG support (DVI, HDMI, LVDS, etc.) - still has some issues. - -commit 2901e99f1942842856cd39c1dcc8b22f3cf7d9e3 -Author: Alex Deucher -Date: Wed Mar 5 10:40:06 2008 -0500 - - RADEON: fix fetching of dac2 adj values from newer bios tables - -commit 74eb981287d76836327830bd51272f605a07e0cc -Author: Alex Deucher -Date: Mon Mar 3 12:02:44 2008 -0500 - - ATOMBIOS: fix atombios parser support on *bsd - - bsd requires a different pragma pack than Linux. - See bug 14594. - -commit f7769ea86e265f347eb58c517ccb5ef8b35eec27 -Author: Paulo Cesar Pereira de Andrade -Date: Sun Mar 2 14:49:21 2008 -0500 - - [PATCH] Ensure symbols used by other modules are visible. - - The xf86-video-ati drivers are one of the cases where LoaderSymbol is - widely used in some obscure ways. This patch fixes the problem, and - allows compiling with -fvisibility=hidden. - -commit a4398ac3ad77216f2c8aa628425bef5f2912a0a9 -Author: Alex Deucher -Date: Sat Mar 1 18:52:26 2008 -0500 - - RS6xx: change isIGP checks to CHIP_FAMILY_RS690 - - these paths are only relevant on RS6xx chips - -commit 67d4d04836c05293b844bc505f303cfb04c0f8a4 -Author: Alex Deucher -Date: Sat Mar 1 18:33:18 2008 -0500 - - RADEON: use xf86SetDesiredModes() in screeninit and enterVT - - this should restore the proper output state on VT switches - -commit be0858a84fbdf74c0b844f462933a221d48c707d -Author: Maciej Cencora -Date: Sat Mar 1 18:11:58 2008 -0500 - - RADEON: remove driver rec copies of mc info, use save rec directly - - info->mc_* were used and the immediately copied into info->ModeReg - ones. Just use the ModeReg copies directly. - -commit dd8ee1b444f4b973a1e0fadca5f943f2162b5e94 -Author: Alex Deucher -Date: Sat Mar 1 16:23:51 2008 -0500 - - RADEON: memmap rework 1 - - Don't restore memmap regs on every mode switch. - Just do memmap save/restore/setup on server start and VT switch. - -commit 1f6a23000001f3d1c21b5c04f94714a8caa7aa8b -Author: Alex Deucher -Date: Sat Mar 1 15:53:42 2008 -0500 - - RADEON: only restore legacy dac regs on legacy radeons - -commit dee6cef8e62d0651c00319e03eea92940fd24aa4 -Author: Alex Deucher -Date: Sat Mar 1 14:39:32 2008 -0500 - - RS4xx: enable exa render accel and textured video - - RS6xx paths seem to work fine on RS4xx - -commit 129f737efe4e8d1a368e7db4b063bdcd9339cb09 -Author: Alex Deucher -Date: Sat Mar 1 14:32:30 2008 -0500 - - AVIVO: save/restore regs by block - - Save/Restore the entire block for each output. - This should fix VT switch problems. - -commit b069aadaa63a95d7a71b5cfbab83577b49501094 -Author: Alex Deucher -Date: Fri Feb 29 22:36:02 2008 -0500 - - AVIVO: LVDS panels need dithering enabled - - Fixes bug 14760 - -commit fe87bdee815372b4b4d7d4c705e34681625b90f2 -Author: Alex Deucher -Date: Fri Feb 29 13:10:13 2008 -0500 - - AVIVO: disable pageflipping on avivo chips until we have proper drm support - -commit fb3678c7f511d539a51cd090cb8b5041d7d2ba26 -Author: Alex Deucher -Date: Fri Feb 29 13:01:21 2008 -0500 - - R5xx: fix register count when sending fragment program for textured video - -commit a66d37d1a896ec934989592457c2beff8e6f1639 -Author: Alex Deucher -Date: Fri Feb 29 04:07:05 2008 -0500 - - fix off-by-one in last commit - -commit e56062960be0c8d3947861dd5e0691fce6516b99 -Author: Alex Deucher -Date: Thu Feb 28 19:16:39 2008 -0500 - - AVIVO: save/restore scaler regs - -commit ae1c39a9b3e666404d0931679c9078c2e125a8bc -Author: Alex Deucher -Date: Thu Feb 28 18:53:55 2008 -0500 - - RS6xx: rework output parsing - - Turns out it's not as complex as I originially thought. - IGP chips just have non-standard GPIO entires for DDC. - -commit d8d6c9fe4ae7e1ab67dd041a251e901d97c29ed6 -Author: Alex Deucher -Date: Thu Feb 28 17:01:14 2008 -0500 - - RS6xx: fix typos in previous commit - - Noted by Maciej Cencora on IRC - -commit 46547ae8bdbc5c10f1fd028b95ec4c5c31a5b318 -Author: Alex Deucher -Date: Thu Feb 28 14:29:30 2008 -0500 - - AVIVO: disable dithering on DFPs - - This should fix the color banding some people have noticed. - Also save/restore DDIA regs on RS6xx - -commit 72a53d6f20ac29b3baddb7d8af04f19b76d2e04f -Author: Michel Dänzer -Date: Thu Feb 28 17:38:04 2008 +0100 - - Handle EXA coordinate limits more cleverly. - - Generally set the 2D engine limits, and only enforce the 3D engine limits in the - CheckComposite hook. This should still prevent useless migration of pixmaps the - 3D engine can't handle but allows for basic acceleration of bigger ones. - - Fixes http://bugs.freedesktop.org/show_bug.cgi?id=14708 . - -commit 5249f450a2487475a95531603cc8668db2c21c33 -Author: Michel Dänzer -Date: Thu Feb 28 12:23:58 2008 +0100 - - Fix 16 bit packed YUV XVideo playback on big endian systems with DRI disabled. - - http://bugs.freedesktop.org/show_bug.cgi?id=14668 - -commit e40d75fd8b2aece9dae8076fac822a4a83025fb2 -Author: Alex Deucher -Date: Wed Feb 27 22:53:10 2008 -0500 - - R500: fragment program clean up and magic number conversion - -commit 140dadba36b2191f0e18e41dd987785abd5f55d2 -Author: Alex Deucher -Date: Wed Feb 27 22:21:12 2008 -0500 - - R300: fix up magic numbers in fragment program - -commit e521476bb5e2dfabc93747e43eb911a8a101357e -Author: Alex Deucher -Date: Wed Feb 27 21:26:55 2008 -0500 - - R300/R400: bump up the clip limits for textured video - - This allows up to 2560x2560 (hw limit) - -commit 10db46f11d7e1c055c9ad6034c65ad163dad17dc -Author: Alex Deucher -Date: Wed Feb 27 15:28:50 2008 -0500 - - AVIVO: make sure we select the right LUT for each crtc - -commit ea944f38dcfd871b27345698afea1cb986ecb049 -Author: Alex Deucher -Date: Wed Feb 27 14:37:52 2008 -0500 - - R300+: update RADEONCP_REFRESH() to reflect new location of scissor regs - -commit b865faf95666e2172c3eec143f77fe9c524e4983 -Author: Alex Deucher -Date: Wed Feb 27 14:05:44 2008 -0500 - - R100/R200: move r100/r200 specific 3D setup into appropriate blocks - - R3xx+ doesn't have these regs. - -commit 3de2dc88cf26ff5932f11cecdf975777b8aa2a4a -Author: Adam Jackson -Date: Wed Jan 16 14:55:05 2008 -0500 - - Bump CRTC size limits on AVIVO chips so 30" displays work without tweaking. - - Note that the CRTC size limits we're using right now are _not_ the - hardware limits, they're just heuristics until we can resize the front - buffer properly. -diff --git a/configure.ac b/configure.ac -index 2412d4f..b8c18a6 100644 ---- a/configure.ac -+++ b/configure.ac -@@ -22,7 +22,7 @@ - - AC_PREREQ(2.57) - AC_INIT([xf86-video-ati], -- 6.8.0, -+ 6.9.0, - [https://bugs.freedesktop.org/enter_bug.cgi?product=xorg], - xf86-video-ati) - -@@ -176,6 +176,18 @@ AC_CHECK_DECL(xf86_crtc_clip_video_helper, - #include "xf86i2c.h" - #include "xf86Crtc.h"]) - -+AC_CHECK_DECL(xf86RotateFreeShadow, -+ [AC_DEFINE(HAVE_FREE_SHADOW, 1, [have new FreeShadow API])], -+ [], -+ [#include -+ #include -+ #include ]) -+ -+AC_CHECK_DECL(pci_device_enable, -+ [AC_DEFINE(HAVE_PCI_DEVICE_ENABLE, 1, [Have pci_device_enable prototype])], -+ [], -+ [#include ]) -+ - AC_CHECK_DECL(XSERVER_LIBPCIACCESS, - [XSERVER_LIBPCIACCESS=yes],[XSERVER_LIBPCIACCESS=no], - [#include "xorg-server.h"]) -@@ -232,6 +244,71 @@ if test "x$XSERVER_LIBPCIACCESS" = xyes; then - fi - AM_CONDITIONAL(XSERVER_LIBPCIACCESS, test "x$XSERVER_LIBPCIACCESS" = xyes) - -+# Checks for headers/macros for byte swapping -+# Known variants: -+# bswap_16, bswap_32, bswap_64 (glibc) -+# __swap16, __swap32, __swap64 (OpenBSD) -+# bswap16, bswap32, bswap64 (other BSD's) -+# and a fallback to local macros if none of the above are found -+ -+# if is found, assume it's the correct version -+AC_CHECK_HEADERS([byteswap.h]) -+ -+# if is found, have to check which version -+AC_CHECK_HEADER([sys/endian.h], [HAVE_SYS_ENDIAN_H="yes"], [HAVE_SYS_ENDIAN_H="no"]) -+ -+if test "x$HAVE_SYS_ENDIAN_H" = "xyes" ; then -+ AC_MSG_CHECKING([for __swap16 variant of byteswapping macros]) -+ AC_LINK_IFELSE([AC_LANG_PROGRAM([ -+#include -+#include -+ ], [ -+int a = 1, b; -+b = __swap16(a); -+ ]) -+], [SYS_ENDIAN__SWAP='yes'], [SYS_ENDIAN__SWAP='no']) -+ AC_MSG_RESULT([$SYS_ENDIAN__SWAP]) -+ -+ AC_MSG_CHECKING([for bswap16 variant of byteswapping macros]) -+ AC_LINK_IFELSE([AC_LANG_PROGRAM([ -+#include -+#include -+ ], [ -+int a = 1, b; -+b = bswap16(a); -+ ]) -+], [SYS_ENDIAN_BSWAP='yes'], [SYS_ENDIAN_BSWAP='no']) -+ AC_MSG_RESULT([$SYS_ENDIAN_BSWAP]) -+ -+ if test "$SYS_ENDIAN_BSWAP" = "yes" ; then -+ USE_SYS_ENDIAN_H=yes -+ BSWAP=bswap -+ else -+ if test "$SYS_ENDIAN__SWAP" = "yes" ; then -+ USE_SYS_ENDIAN_H=yes -+ BSWAP=__swap -+ else -+ USE_SYS_ENDIAN_H=no -+ fi -+ fi -+ -+ if test "$USE_SYS_ENDIAN_H" = "yes" ; then -+ AC_DEFINE([USE_SYS_ENDIAN_H], 1, -+ [Define to use byteswap macros from ]) -+ AC_DEFINE_UNQUOTED([bswap_16], ${BSWAP}16, -+ [Define to 16-bit byteswap macro]) -+ AC_DEFINE_UNQUOTED([bswap_32], ${BSWAP}32, -+ [Define to 32-bit byteswap macro]) -+ AC_DEFINE_UNQUOTED([bswap_64], ${BSWAP}64, -+ [Define to 64-bit byteswap macro]) -+ fi -+fi -+ -+case $host_os in -+ *linux*) -+ AC_DEFINE(FGL_LINUX, 1, [Use linux pragma pack]) ;; -+esac -+ - AC_SUBST([XORG_CFLAGS]) - AC_SUBST([DRI_CFLAGS]) - AC_SUBST([moduledir]) -diff --git a/man/Makefile.am b/man/Makefile.am -index 2d11006..93ff52c 100644 ---- a/man/Makefile.am -+++ b/man/Makefile.am -@@ -1,4 +1,3 @@ --# $Id$ - # - # Copyright 2005 Sun Microsystems, Inc. All rights reserved. - # -diff --git a/man/radeon.man b/man/radeon.man -index 86be965..03622a0 100644 ---- a/man/radeon.man -+++ b/man/radeon.man -@@ -52,11 +52,11 @@ Radeon 9100 IGP - .B RS350 - Radeon 9200 IGP - .TP 12 --.B RS400 --Radeon XPRESS 200/200M IGP -+.B RS400/RS480 -+Radeon XPRESS 200(M)/1100 IGP - .TP 12 - .B RV280 --Radeon 9200PRO/9200/9200SE, M9+ -+Radeon 9200PRO/9200/9200SE/9250, M9+ - .TP 12 - .B R300 - Radeon 9700PRO/9700/9500PRO/9500/9600TX, FireGL X1/Z1 -@@ -68,9 +68,9 @@ Radeon 9800PRO/9800SE/9800, FireGL X2 - Radeon 9800XT - .TP 12 - .B RV350 --Radeon 9600PRO/9600SE/9600, M10/M11, FireGL T2 -+Radeon 9600PRO/9600SE/9600/9550, M10/M11, FireGL T2 - .TP 12 --.B RV360 -+.B RV360 - Radeon 9600XT - .TP 12 - .B RV370 -@@ -91,8 +91,8 @@ Radeon X800, M28 PCIE - .B R480/R481 - Radeon X850 PCIE/AGP - .TP 12 --.B RV515 --Radeon X1300/X1400/X1500 -+.B RV505/RV515/RV516/RV550 -+Radeon X1300/X1400/X1500/X2300 - .TP 12 - .B R520 - Radeon X1800 -@@ -114,6 +114,12 @@ Radeon HD 2400/2600 - .TP 12 - .B RV670 - Radeon HD 3850/3870 -+.TP 12 -+.B RV620/RV635 -+Radeon HD 3450/3470 -+.TP 12 -+.B RS780 -+Radeon HD 3200 - - .SH CONFIGURATION DETAILS - Please refer to __xconfigfile__(__filemansuffix__) for general configuration -@@ -422,6 +428,14 @@ internal TMDS controller. - The default is - .B off. - .TP -+.BI "Option \*qDefaultTVDACAdj\*q \*q" boolean \*q -+Use the default driver provided TVDAC Adj values rather than the ones -+provided by the bios. This option has no effect on Mac cards. Enable -+this option if you are having problems with a washed out display on -+the secondary DAC. -+The default is -+.B off. -+.TP - .BI "Option \*qDRI\*q \*q" boolean \*q - Enable DRI support. This option allows you to enable to disable the DRI. - The default is -@@ -497,6 +511,12 @@ LVDS as attached. - The default is - .B on. - .TP -+.BI "Option \*qInt10\*q \*q" boolean \*q -+This option allows you to disable int10 initialization. Set this to -+False if you are experiencing a hang when initializing a secondary card. -+The default is -+.B on. -+.TP - - .SH SEE ALSO - __xservername__(__appmansuffix__), __xconfigfile__(__filemansuffix__), xorgconfig(__appmansuffix__), Xserver(__appmansuffix__), X(__miscmansuffix__) -diff --git a/src/AtomBios/CD_Operations.c b/src/AtomBios/CD_Operations.c -index 1e48f81..58c4ae9 100644 ---- a/src/AtomBios/CD_Operations.c -+++ b/src/AtomBios/CD_Operations.c -@@ -36,10 +36,14 @@ Revision History: - --*/ - #define __SW_4 - --#include "Decoder.h" --#include "atombios.h" -+#ifdef HAVE_CONFIG_H -+#include "config.h" -+#endif - -+#include -+#include "xorg-server.h" - -+#include "Decoder.h" - - VOID PutDataRegister(PARSER_TEMP_DATA STACK_BASED * pParserTempData); - VOID PutDataPS(PARSER_TEMP_DATA STACK_BASED * pParserTempData); -@@ -226,7 +230,7 @@ UINT32 IndirectInputOutput(PARSER_TEMP_DATA STACK_BASED * pParserTempData) - IndirectIOParserCommands[*pParserTempData->IndirectIOTablePointer].func(pParserTempData); - pParserTempData->IndirectIOTablePointer+=IndirectIOParserCommands[*pParserTempData->IndirectIOTablePointer].csize; - } -- pParserTempData->IndirectIOTablePointer-=*(UINT16*)(pParserTempData->IndirectIOTablePointer+1); -+ pParserTempData->IndirectIOTablePointer-=UINT16LE_TO_CPU(*(UINT16*)(pParserTempData->IndirectIOTablePointer+1)); - pParserTempData->IndirectIOTablePointer++; - return pParserTempData->IndirectData; - } else pParserTempData->IndirectIOTablePointer+=IndirectIOParserCommands[*pParserTempData->IndirectIOTablePointer].csize; -@@ -238,7 +242,7 @@ UINT32 IndirectInputOutput(PARSER_TEMP_DATA STACK_BASED * pParserTempData) - - VOID PutDataRegister(PARSER_TEMP_DATA STACK_BASED * pParserTempData) - { -- pParserTempData->Index=(UINT32)pParserTempData->pCmd->Parameters.WordXX.PA_Destination; -+ pParserTempData->Index=(UINT32)UINT16LE_TO_CPU(pParserTempData->pCmd->Parameters.WordXX.PA_Destination); - pParserTempData->Index+=pParserTempData->CurrentRegBlock; - switch(pParserTempData->Multipurpose.CurrentPort){ - case ATI_RegsPort: -@@ -264,16 +268,16 @@ VOID PutDataRegister(PARSER_TEMP_DATA STACK_BASED * pParserTempData) - VOID PutDataPS(PARSER_TEMP_DATA STACK_BASED * pParserTempData) - { - *(pParserTempData->pDeviceData->pParameterSpace+pParserTempData->pCmd->Parameters.ByteXX.PA_Destination)= -- pParserTempData->DestData32; -+ CPU_TO_UINT32LE(pParserTempData->DestData32); - } - - VOID PutDataWS(PARSER_TEMP_DATA STACK_BASED * pParserTempData) - { - if (pParserTempData->pCmd->Parameters.ByteXX.PA_Destination < WS_QUOTIENT_C) -- *(pParserTempData->pWorkingTableData->pWorkSpace+pParserTempData->pCmd->Parameters.ByteXX.PA_Destination) = pParserTempData->DestData32; -+ *(pParserTempData->pWorkingTableData->pWorkSpace+pParserTempData->pCmd->Parameters.ByteXX.PA_Destination) = pParserTempData->DestData32; - else -- switch (pParserTempData->pCmd->Parameters.ByteXX.PA_Destination) -- { -+ switch (pParserTempData->pCmd->Parameters.ByteXX.PA_Destination) -+ { - case WS_REMINDER_C: - pParserTempData->MultiplicationOrDivision.Division.Reminder32=pParserTempData->DestData32; - break; -@@ -334,7 +338,7 @@ VOID SkipParameters16(PARSER_TEMP_DATA STACK_BASED * pParserTempData) - - UINT32 GetParametersRegister(PARSER_TEMP_DATA STACK_BASED * pParserTempData) - { -- pParserTempData->Index=*(UINT16*)pParserTempData->pWorkingTableData->IP; -+ pParserTempData->Index=UINT16LE_TO_CPU(*(UINT16*)pParserTempData->pWorkingTableData->IP); - pParserTempData->pWorkingTableData->IP+=sizeof(UINT16); - pParserTempData->Index+=pParserTempData->CurrentRegBlock; - switch(pParserTempData->Multipurpose.CurrentPort) -@@ -356,9 +360,11 @@ UINT32 GetParametersRegister(PARSER_TEMP_DATA STACK_BASED * pParserTempData) - - UINT32 GetParametersPS(PARSER_TEMP_DATA STACK_BASED * pParserTempData) - { -+ UINT32 data; - pParserTempData->Index=*pParserTempData->pWorkingTableData->IP; - pParserTempData->pWorkingTableData->IP+=sizeof(UINT8); -- return *(pParserTempData->pDeviceData->pParameterSpace+pParserTempData->Index); -+ data = UINT32LE_TO_CPU(*(pParserTempData->pDeviceData->pParameterSpace+pParserTempData->Index)); -+ return data; - } - - UINT32 GetParametersWS(PARSER_TEMP_DATA STACK_BASED * pParserTempData) -@@ -414,9 +420,12 @@ UINT32 GetParametersMC(PARSER_TEMP_DATA STACK_BASED * pParserTempData) - - UINT32 GetParametersIndirect(PARSER_TEMP_DATA STACK_BASED * pParserTempData) - { -- pParserTempData->Index=*(UINT16*)pParserTempData->pWorkingTableData->IP; -+ UINT32 ret; -+ -+ pParserTempData->Index=UINT16LE_TO_CPU(*(UINT16*)pParserTempData->pWorkingTableData->IP); - pParserTempData->pWorkingTableData->IP+=sizeof(UINT16); -- return *(UINT32*)(RELATIVE_TO_BIOS_IMAGE(pParserTempData->Index)+pParserTempData->CurrentDataBlock); -+ ret = UINT32LE_TO_CPU(*(UINT32*)(RELATIVE_TO_BIOS_IMAGE(pParserTempData->Index)+pParserTempData->CurrentDataBlock)); -+ return ret; - } - - UINT32 GetParametersDirect8(PARSER_TEMP_DATA STACK_BASED * pParserTempData) -@@ -430,7 +439,7 @@ UINT32 GetParametersDirect8(PARSER_TEMP_DATA STACK_BASED * pParserTempData) - UINT32 GetParametersDirect16(PARSER_TEMP_DATA STACK_BASED * pParserTempData) - { - pParserTempData->CD_Mask.SrcAlignment=alignmentLowerWord; -- pParserTempData->Index=*(UINT16*)pParserTempData->pWorkingTableData->IP; -+ pParserTempData->Index=UINT16LE_TO_CPU(*(UINT16*)pParserTempData->pWorkingTableData->IP); - pParserTempData->pWorkingTableData->IP+=sizeof(UINT16); - return pParserTempData->Index; - } -@@ -438,7 +447,7 @@ UINT32 GetParametersDirect16(PARSER_TEMP_DATA STACK_BASED * pParserTempData) - UINT32 GetParametersDirect32(PARSER_TEMP_DATA STACK_BASED * pParserTempData) - { - pParserTempData->CD_Mask.SrcAlignment=alignmentDword; -- pParserTempData->Index=*(UINT32*)pParserTempData->pWorkingTableData->IP; -+ pParserTempData->Index=UINT32LE_TO_CPU(*(UINT32*)pParserTempData->pWorkingTableData->IP); - pParserTempData->pWorkingTableData->IP+=sizeof(UINT32); - return pParserTempData->Index; - } -@@ -469,7 +478,7 @@ VOID ProcessMove(PARSER_TEMP_DATA STACK_BASED * pParserTempData) - { - if (pParserTempData->CD_Mask.SrcAlignment!=alignmentDword) - { -- pParserTempData->DestData32=GetDestination[pParserTempData->ParametersType.Destination](pParserTempData); -+ pParserTempData->DestData32=GetDestination[pParserTempData->ParametersType.Destination](pParserTempData); - } else - { - SkipDestination[pParserTempData->ParametersType.Destination](pParserTempData); -@@ -659,7 +668,8 @@ VOID ProcessSwitch(PARSER_TEMP_DATA STACK_BASED * pParserTempData){ - pParserTempData->SourceData32=GetSource[pParserTempData->ParametersType.Source](pParserTempData); - pParserTempData->SourceData32 >>= SourceAlignmentShift[pParserTempData->CD_Mask.SrcAlignment]; - pParserTempData->SourceData32 &= AlignmentMask[pParserTempData->CD_Mask.SrcAlignment]; -- while ( *(UINT16*)pParserTempData->pWorkingTableData->IP != (((UINT16)NOP_OPCODE << 8)+NOP_OPCODE)) -+ -+ while ( UINT16LE_TO_CPU(*(UINT16*)pParserTempData->pWorkingTableData->IP) != (((UINT16)NOP_OPCODE << 8)+NOP_OPCODE)) - { - if (*pParserTempData->pWorkingTableData->IP == 'c') - { -@@ -668,7 +678,7 @@ VOID ProcessSwitch(PARSER_TEMP_DATA STACK_BASED * pParserTempData){ - pParserTempData->Index=GetParametersDirect16(pParserTempData); - if (pParserTempData->SourceData32 == pParserTempData->DestData32) - { -- pParserTempData->pWorkingTableData->IP= RELATIVE_TO_TABLE(pParserTempData->Index); -+ pParserTempData->pWorkingTableData->IP= RELATIVE_TO_TABLE(pParserTempData->Index); - return; - } - } -@@ -690,7 +700,7 @@ VOID cmdSetDataBlock(PARSER_TEMP_DATA STACK_BASED * pParserTempData) - } else - { - pMasterDataTable = GetDataMasterTablePointer(pParserTempData->pDeviceData); -- pParserTempData->CurrentDataBlock= (TABLE_UNIT_TYPE)((PTABLE_UNIT_TYPE)pMasterDataTable)[value]; -+ pParserTempData->CurrentDataBlock= UINT16LE_TO_CPU((TABLE_UNIT_TYPE)((PTABLE_UNIT_TYPE)pMasterDataTable)[value]); - } - } - pParserTempData->pWorkingTableData->IP+=sizeof(COMMAND_TYPE_OPCODE_VALUE_BYTE); -@@ -699,13 +709,13 @@ VOID cmdSetDataBlock(PARSER_TEMP_DATA STACK_BASED * pParserTempData) - VOID cmdSet_ATI_Port(PARSER_TEMP_DATA STACK_BASED * pParserTempData) - { - pParserTempData->Multipurpose.CurrentPort=ATI_RegsPort; -- pParserTempData->CurrentPortID = (UINT8)((COMMAND_TYPE_1*)pParserTempData->pWorkingTableData->IP)->Parameters.WordXX.PA_Destination; -+ pParserTempData->CurrentPortID = (UINT8)UINT16LE_TO_CPU(((COMMAND_TYPE_1*)pParserTempData->pWorkingTableData->IP)->Parameters.WordXX.PA_Destination); - pParserTempData->pWorkingTableData->IP+=sizeof(COMMAND_TYPE_OPCODE_OFFSET16); - } - - VOID cmdSet_Reg_Block(PARSER_TEMP_DATA STACK_BASED * pParserTempData) - { -- pParserTempData->CurrentRegBlock = ((COMMAND_TYPE_1*)pParserTempData->pWorkingTableData->IP)->Parameters.WordXX.PA_Destination; -+ pParserTempData->CurrentRegBlock = UINT16LE_TO_CPU(((COMMAND_TYPE_1*)pParserTempData->pWorkingTableData->IP)->Parameters.WordXX.PA_Destination); - pParserTempData->pWorkingTableData->IP+=sizeof(COMMAND_TYPE_OPCODE_OFFSET16); - } - -@@ -749,19 +759,23 @@ VOID ProcessDebug(PARSER_TEMP_DATA STACK_BASED * pParserTempData) - - VOID ProcessDS(PARSER_TEMP_DATA STACK_BASED * pParserTempData) - { -- pParserTempData->pWorkingTableData->IP+=((COMMAND_TYPE_1*)pParserTempData->pWorkingTableData->IP)->Parameters.WordXX.PA_Destination+sizeof(COMMAND_TYPE_OPCODE_OFFSET16); -+ pParserTempData->pWorkingTableData->IP+=UINT16LE_TO_CPU(((COMMAND_TYPE_1*)pParserTempData->pWorkingTableData->IP)->Parameters.WordXX.PA_Destination)+sizeof(COMMAND_TYPE_OPCODE_OFFSET16); - } - - --VOID cmdCall_Table(PARSER_TEMP_DATA STACK_BASED * pParserTempData){ -+VOID cmdCall_Table(PARSER_TEMP_DATA STACK_BASED * pParserTempData) -+{ - UINT16* MasterTableOffset; - pParserTempData->pWorkingTableData->IP+=sizeof(COMMAND_TYPE_OPCODE_VALUE_BYTE); - MasterTableOffset = GetCommandMasterTablePointer(pParserTempData->pDeviceData); - if(((PTABLE_UNIT_TYPE)MasterTableOffset)[((COMMAND_TYPE_OPCODE_VALUE_BYTE*)pParserTempData->pCmd)->Value]!=0 ) // if the offset is not ZERO - { -+ ATOM_TABLE_ATTRIBUTE lTableAttr; -+ - pParserTempData->CommandSpecific.IndexInMasterTable=GetTrueIndexInMasterTable(pParserTempData,((COMMAND_TYPE_OPCODE_VALUE_BYTE*)pParserTempData->pCmd)->Value); -- pParserTempData->Multipurpose.PS_SizeInDwordsUsedByCallingTable = -- (((ATOM_COMMON_ROM_COMMAND_TABLE_HEADER *)pParserTempData->pWorkingTableData->pTableHead)->TableAttribute.PS_SizeInBytes>>2); -+ -+ lTableAttr = GetCommandTableAttribute(pParserTempData->pWorkingTableData->pTableHead); -+ pParserTempData->Multipurpose.PS_SizeInDwordsUsedByCallingTable = (lTableAttr.PS_SizeInBytes >>2); - pParserTempData->pDeviceData->pParameterSpace+= - pParserTempData->Multipurpose.PS_SizeInDwordsUsedByCallingTable; - pParserTempData->Status=CD_CALL_TABLE; -@@ -787,7 +801,7 @@ VOID ProcessJump(PARSER_TEMP_DATA STACK_BASED * pParserTempData) - (pParserTempData->ParametersType.Destination == pParserTempData->CompareFlags )) - { - -- pParserTempData->pWorkingTableData->IP= RELATIVE_TO_TABLE(((COMMAND_TYPE_OPCODE_OFFSET16*)pParserTempData->pWorkingTableData->IP)->CD_Offset16); -+ pParserTempData->pWorkingTableData->IP= RELATIVE_TO_TABLE(UINT16LE_TO_CPU(((COMMAND_TYPE_OPCODE_OFFSET16*)pParserTempData->pWorkingTableData->IP)->CD_Offset16)); - } else - { - pParserTempData->pWorkingTableData->IP+=sizeof(COMMAND_TYPE_OPCODE_OFFSET16); -@@ -800,7 +814,7 @@ VOID ProcessJumpE(PARSER_TEMP_DATA STACK_BASED * pParserTempData) - (pParserTempData->CompareFlags == pParserTempData->ParametersType.Destination)) - { - -- pParserTempData->pWorkingTableData->IP= RELATIVE_TO_TABLE(((COMMAND_TYPE_OPCODE_OFFSET16*)pParserTempData->pWorkingTableData->IP)->CD_Offset16); -+ pParserTempData->pWorkingTableData->IP= RELATIVE_TO_TABLE(UINT16LE_TO_CPU(((COMMAND_TYPE_OPCODE_OFFSET16*)pParserTempData->pWorkingTableData->IP)->CD_Offset16)); - } else - { - pParserTempData->pWorkingTableData->IP+=sizeof(COMMAND_TYPE_OPCODE_OFFSET16); -@@ -812,7 +826,7 @@ VOID ProcessJumpNE(PARSER_TEMP_DATA STACK_BASED * pParserTempData) - if (pParserTempData->CompareFlags != Equal) - { - -- pParserTempData->pWorkingTableData->IP= RELATIVE_TO_TABLE(((COMMAND_TYPE_OPCODE_OFFSET16*)pParserTempData->pWorkingTableData->IP)->CD_Offset16); -+ pParserTempData->pWorkingTableData->IP= RELATIVE_TO_TABLE(UINT16LE_TO_CPU(((COMMAND_TYPE_OPCODE_OFFSET16*)pParserTempData->pWorkingTableData->IP)->CD_Offset16)); - } else - { - pParserTempData->pWorkingTableData->IP+=sizeof(COMMAND_TYPE_OPCODE_OFFSET16); -diff --git a/src/AtomBios/Decoder.c b/src/AtomBios/Decoder.c -index cdaa9ef..73aac94 100644 ---- a/src/AtomBios/Decoder.c -+++ b/src/AtomBios/Decoder.c -@@ -34,11 +34,15 @@ Revision History: - - NEG:24.09.2002 Initiated. - --*/ --//#include "AtomBios.h" -+ -+#ifdef HAVE_CONFIG_H -+#include "config.h" -+#endif -+ -+#include -+#include "xorg-server.h" -+ - #include "Decoder.h" --#include "atombios.h" --#include "CD_binding.h" --#include "CD_Common_Types.h" - - #ifndef DISABLE_EASF - #include "easf.h" -@@ -70,13 +74,13 @@ UINT16* GetCommandMasterTablePointer(DEVICE_DATA STACK_BASED* pDeviceData) - /* - make MasterTableOffset point to EASF_ASIC_SETUP_TABLE structure, including usSize. - */ -- MasterTableOffset = (UINT16 *) (pDeviceData->pBIOS_Image+((EASF_ASIC_DESCRIPTOR*)pDeviceData->pBIOS_Image)->usAsicSetupTable_Offset); -+ MasterTableOffset = (UINT16 *) (pDeviceData->pBIOS_Image+(UINT16LE_TO_CPU(((EASF_ASIC_DESCRIPTOR*)pDeviceData->pBIOS_Image)->usAsicSetupTable_Offset)); - } else - #endif - { - #ifndef UEFI_BUILD -- MasterTableOffset = (UINT16 *)(*(UINT16 *)(pDeviceData->pBIOS_Image+OFFSET_TO_POINTER_TO_ATOM_ROM_HEADER) + pDeviceData->pBIOS_Image); -- MasterTableOffset = (UINT16 *)((ULONG)((ATOM_ROM_HEADER *)MasterTableOffset)->usMasterCommandTableOffset + pDeviceData->pBIOS_Image ); -+ MasterTableOffset = (UINT16 *)(UINT16LE_TO_CPU(*(UINT16 *)(pDeviceData->pBIOS_Image+OFFSET_TO_POINTER_TO_ATOM_ROM_HEADER)) + pDeviceData->pBIOS_Image); -+ MasterTableOffset = (UINT16 *)((ULONG)UINT16LE_TO_CPU(((ATOM_ROM_HEADER *)MasterTableOffset)->usMasterCommandTableOffset) + pDeviceData->pBIOS_Image ); - MasterTableOffset =(UINT16 *) &(((ATOM_MASTER_COMMAND_TABLE *)MasterTableOffset)->ListOfCommandTables); - #else - MasterTableOffset = (UINT16 *)(&(GetCommandMasterTable( )->ListOfCommandTables)); -@@ -90,8 +94,8 @@ UINT16* GetDataMasterTablePointer(DEVICE_DATA STACK_BASED* pDeviceData) - UINT16 *MasterTableOffset; - - #ifndef UEFI_BUILD -- MasterTableOffset = (UINT16 *)(*(UINT16 *)(pDeviceData->pBIOS_Image+OFFSET_TO_POINTER_TO_ATOM_ROM_HEADER) + pDeviceData->pBIOS_Image); -- MasterTableOffset = (UINT16 *)((ULONG)((ATOM_ROM_HEADER *)MasterTableOffset)->usMasterDataTableOffset + pDeviceData->pBIOS_Image ); -+ MasterTableOffset = (UINT16 *)(UINT16LE_TO_CPU(*(UINT16 *)(pDeviceData->pBIOS_Image+OFFSET_TO_POINTER_TO_ATOM_ROM_HEADER)) + pDeviceData->pBIOS_Image); -+ MasterTableOffset = (UINT16 *)((ULONG)(UINT16LE_TO_CPU(((ATOM_ROM_HEADER *)MasterTableOffset)->usMasterDataTableOffset)) + pDeviceData->pBIOS_Image ); - MasterTableOffset =(UINT16 *) &(((ATOM_MASTER_DATA_TABLE *)MasterTableOffset)->ListOfDataTables); - #else - MasterTableOffset = (UINT16 *)(&(GetDataMasterTable( )->ListOfDataTables)); -@@ -122,11 +126,29 @@ UINT8 GetTrueIndexInMasterTable(PARSER_TEMP_DATA STACK_BASED * pParserTempData, - } - } - -+ATOM_TABLE_ATTRIBUTE GetCommandTableAttribute(UINT8 *pTableHeader) -+{ -+ ATOM_TABLE_ATTRIBUTE_ACCESS lTableAccess; -+ -+ /* It's unclear whether this union trick breaks C aliasing rules, -+ * however, it's explicitely permitted by gcc, and we have other -+ * case where the code relies on a union being accessed by either -+ * of the "ways" and stay consistent so if a compiler breaks this -+ * assumption, it will probably need us to compile without strict -+ * aliasing enforcement -+ */ -+ lTableAccess.sbfAccess = ((ATOM_COMMON_ROM_COMMAND_TABLE_HEADER *)pTableHeader)->TableAttribute; -+ lTableAccess.susAccess = UINT16LE_TO_CPU(lTableAccess.susAccess); -+ -+ return lTableAccess.sbfAccess; -+} -+ - CD_STATUS ParseTable(DEVICE_DATA STACK_BASED* pDeviceData, UINT8 IndexInMasterTable) - { - PARSER_TEMP_DATA ParserTempData; - WORKING_TABLE_DATA STACK_BASED* prevWorkingTableData; - -+ memset(&ParserTempData, 0, sizeof(PARSER_TEMP_DATA)); - ParserTempData.pDeviceData=(DEVICE_DATA*)pDeviceData; - #ifndef DISABLE_EASF - if (pDeviceData->format == TABLE_FORMAT_EASF) -@@ -136,7 +158,7 @@ CD_STATUS ParseTable(DEVICE_DATA STACK_BASED* pDeviceData, UINT8 IndexInMasterTa - #endif - { - ParserTempData.pCmd=(GENERIC_ATTRIBUTE_COMMAND*)GetDataMasterTablePointer(pDeviceData); -- ParserTempData.IndirectIOTablePointer=(UINT8*)((ULONG)(((PTABLE_UNIT_TYPE)ParserTempData.pCmd)[INDIRECT_IO_TABLE]) + pDeviceData->pBIOS_Image); -+ ParserTempData.IndirectIOTablePointer=(UINT8*)((ULONG)(UINT16LE_TO_CPU(((PTABLE_UNIT_TYPE)ParserTempData.pCmd)[INDIRECT_IO_TABLE])) + pDeviceData->pBIOS_Image); - ParserTempData.IndirectIOTablePointer+=sizeof(ATOM_COMMON_TABLE_HEADER); - } - -@@ -153,65 +175,66 @@ CD_STATUS ParseTable(DEVICE_DATA STACK_BASED* pDeviceData, UINT8 IndexInMasterTa - ParserTempData.Status=CD_CALL_TABLE; - - do{ -- -+ - if (ParserTempData.Status==CD_CALL_TABLE) -- { -+ { - IndexInMasterTable=ParserTempData.CommandSpecific.IndexInMasterTable; - if(((PTABLE_UNIT_TYPE)ParserTempData.pCmd)[IndexInMasterTable]!=0) // if the offset is not ZERO -- { -+ { -+ ATOM_TABLE_ATTRIBUTE lTableAttr; -+ lTableAttr = GetCommandTableAttribute(UINT16LE_TO_CPU(((PTABLE_UNIT_TYPE)ParserTempData.pCmd)[IndexInMasterTable])+pDeviceData->pBIOS_Image); - #ifndef UEFI_BUILD - ParserTempData.pWorkingTableData =(WORKING_TABLE_DATA STACK_BASED*) AllocateWorkSpace(pDeviceData, -- ((ATOM_COMMON_ROM_COMMAND_TABLE_HEADER*)(((PTABLE_UNIT_TYPE)ParserTempData.pCmd)[IndexInMasterTable]+pDeviceData->pBIOS_Image))->TableAttribute.WS_SizeInBytes+sizeof(WORKING_TABLE_DATA)); -+ lTableAttr.WS_SizeInBytes+sizeof(WORKING_TABLE_DATA)); - #else -- ParserTempData.pWorkingTableData =(WORKING_TABLE_DATA STACK_BASED*) AllocateWorkSpace(pDeviceData, -- ((ATOM_COMMON_ROM_COMMAND_TABLE_HEADER*)(((PTABLE_UNIT_TYPE)ParserTempData.pCmd)[IndexInMasterTable]))->TableAttribute.WS_SizeInBytes+sizeof(WORKING_TABLE_DATA)); -+ ParserTempData.pWorkingTableData =(WORKING_TABLE_DATA STACK_BASED*) AllocateWorkSpace(pDeviceData, -+ lTableAttr.WS_SizeInBytes+sizeof(WORKING_TABLE_DATA)); - #endif -- if (ParserTempData.pWorkingTableData!=NULL) -- { -- ParserTempData.pWorkingTableData->pWorkSpace=(WORKSPACE_POINTER STACK_BASED*)((UINT8*)ParserTempData.pWorkingTableData+sizeof(WORKING_TABLE_DATA)); -+ if (ParserTempData.pWorkingTableData!=NULL) -+ { -+ ParserTempData.pWorkingTableData->pWorkSpace=(WORKSPACE_POINTER STACK_BASED*)((UINT8*)ParserTempData.pWorkingTableData+sizeof(WORKING_TABLE_DATA)); - #ifndef UEFI_BUILD -- ParserTempData.pWorkingTableData->pTableHead = (UINT8 *)(((PTABLE_UNIT_TYPE)ParserTempData.pCmd)[IndexInMasterTable]+pDeviceData->pBIOS_Image); -+ ParserTempData.pWorkingTableData->pTableHead = (UINT8 *)(UINT16LE_TO_CPU(((PTABLE_UNIT_TYPE)ParserTempData.pCmd)[IndexInMasterTable])+pDeviceData->pBIOS_Image); - #else -- ParserTempData.pWorkingTableData->pTableHead = (UINT8 *)(((PTABLE_UNIT_TYPE)ParserTempData.pCmd)[IndexInMasterTable]); -+ ParserTempData.pWorkingTableData->pTableHead = (UINT8 *)(UINT16LE_TO_CPU(((PTABLE_UNIT_TYPE)ParserTempData.pCmd)[IndexInMasterTable])); - #endif -- ParserTempData.pWorkingTableData->IP=((UINT8*)ParserTempData.pWorkingTableData->pTableHead)+sizeof(ATOM_COMMON_ROM_COMMAND_TABLE_HEADER); -- ParserTempData.pWorkingTableData->prevWorkingTableData=prevWorkingTableData; -- prevWorkingTableData=ParserTempData.pWorkingTableData; -- ParserTempData.Status = CD_SUCCESS; -- } else ParserTempData.Status = CD_UNEXPECTED_BEHAVIOR; -- } else ParserTempData.Status = CD_EXEC_TABLE_NOT_FOUND; -+ ParserTempData.pWorkingTableData->IP=((UINT8*)ParserTempData.pWorkingTableData->pTableHead)+sizeof(ATOM_COMMON_ROM_COMMAND_TABLE_HEADER); -+ ParserTempData.pWorkingTableData->prevWorkingTableData=prevWorkingTableData; -+ prevWorkingTableData=ParserTempData.pWorkingTableData; -+ ParserTempData.Status = CD_SUCCESS; -+ } else ParserTempData.Status = CD_UNEXPECTED_BEHAVIOR; -+ } else ParserTempData.Status = CD_EXEC_TABLE_NOT_FOUND; - } - if (!CD_ERROR(ParserTempData.Status)) - { -- ParserTempData.Status = CD_SUCCESS; -+ ParserTempData.Status = CD_SUCCESS; - while (!CD_ERROR_OR_COMPLETED(ParserTempData.Status)) -- { -- -+ { - if (IS_COMMAND_VALID(((COMMAND_HEADER*)ParserTempData.pWorkingTableData->IP)->Opcode)) -- { -+ { - ParserTempData.pCmd = (GENERIC_ATTRIBUTE_COMMAND*)ParserTempData.pWorkingTableData->IP; -- -+ - if (IS_END_OF_TABLE(((COMMAND_HEADER*)ParserTempData.pWorkingTableData->IP)->Opcode)) - { - ParserTempData.Status=CD_COMPLETED; -- prevWorkingTableData=ParserTempData.pWorkingTableData->prevWorkingTableData; -- -+ prevWorkingTableData=ParserTempData.pWorkingTableData->prevWorkingTableData; -+ - FreeWorkSpace(pDeviceData, ParserTempData.pWorkingTableData); -- ParserTempData.pWorkingTableData=prevWorkingTableData; -- if (prevWorkingTableData!=NULL) -- { -- ParserTempData.pDeviceData->pParameterSpace-= -- (((ATOM_COMMON_ROM_COMMAND_TABLE_HEADER*)ParserTempData.pWorkingTableData-> -- pTableHead)->TableAttribute.PS_SizeInBytes>>2); -- } -- // if there is a parent table where to return, then restore PS_pointer to the original state -+ ParserTempData.pWorkingTableData=prevWorkingTableData; -+ if (prevWorkingTableData!=NULL) -+ { -+ ATOM_TABLE_ATTRIBUTE lTableAttr; -+ lTableAttr = GetCommandTableAttribute(ParserTempData.pWorkingTableData->pTableHead); -+ ParserTempData.pDeviceData->pParameterSpace-=(lTableAttr.PS_SizeInBytes>>2); -+ } -+ // if there is a parent table where to return, then restore PS_pointer to the original state - } - else - { -- IndexInMasterTable=ProcessCommandProperties((PARSER_TEMP_DATA STACK_BASED *)&ParserTempData); -+ IndexInMasterTable=ProcessCommandProperties((PARSER_TEMP_DATA STACK_BASED *)&ParserTempData); - (*CallTable[IndexInMasterTable].function)((PARSER_TEMP_DATA STACK_BASED *)&ParserTempData); - #if (PARSER_TYPE!=DRIVER_TYPE_PARSER) -- BIOS_STACK_MODIFIER(); -+ BIOS_STACK_MODIFIER(); - #endif - } - } -@@ -220,13 +243,13 @@ CD_STATUS ParseTable(DEVICE_DATA STACK_BASED* pDeviceData, UINT8 IndexInMasterTa - ParserTempData.Status=CD_INVALID_OPCODE; - break; - } -- -+ - } // while - } // if - else - break; - } while (prevWorkingTableData!=NULL); -- if (ParserTempData.Status == CD_COMPLETED) return CD_SUCCESS; -+ if (ParserTempData.Status == CD_COMPLETED) return CD_SUCCESS; - return ParserTempData.Status; - } else return CD_SUCCESS; - } -diff --git a/src/AtomBios/hwserv_drv.c b/src/AtomBios/hwserv_drv.c -index a5f5a5b..9f2b6b9 100644 ---- a/src/AtomBios/hwserv_drv.c -+++ b/src/AtomBios/hwserv_drv.c -@@ -34,8 +34,14 @@ Revision History: - - NEG:27.09.2002 Initiated. - --*/ --#include "CD_binding.h" --#include "CD_hw_services.h" -+#ifdef HAVE_CONFIG_H -+#include "config.h" -+#endif -+ -+#include -+#include "xorg-server.h" -+ -+#include "Decoder.h" - - //trace settings - #if DEBUG_OUTPUT_DEVICE & 1 -@@ -249,12 +255,12 @@ VOID WriteReg32(PARSER_TEMP_DATA STACK_BASED * pWorkingTableData) - - VOID ReadIndReg32 (PARSER_TEMP_DATA STACK_BASED * pWorkingTableData) - { -- pWorkingTableData->IndirectData = CailReadATIRegister(pWorkingTableData->pDeviceData->CAIL,*(UINT16*)(pWorkingTableData->IndirectIOTablePointer+1)); -+ pWorkingTableData->IndirectData = CailReadATIRegister(pWorkingTableData->pDeviceData->CAIL,UINT16LE_TO_CPU(*(UINT16*)(pWorkingTableData->IndirectIOTablePointer+1))); - } - - VOID WriteIndReg32(PARSER_TEMP_DATA STACK_BASED * pWorkingTableData) - { -- CailWriteATIRegister(pWorkingTableData->pDeviceData->CAIL,*(UINT16*)(pWorkingTableData->IndirectIOTablePointer+1),pWorkingTableData->IndirectData ); -+ CailWriteATIRegister(pWorkingTableData->pDeviceData->CAIL,UINT16LE_TO_CPU(*(UINT16*)(pWorkingTableData->IndirectIOTablePointer+1)),pWorkingTableData->IndirectData); - } - - #endif -diff --git a/src/AtomBios/includes/CD_Common_Types.h b/src/AtomBios/includes/CD_Common_Types.h -index 44a0b35..071b8fd 100644 ---- a/src/AtomBios/includes/CD_Common_Types.h -+++ b/src/AtomBios/includes/CD_Common_Types.h -@@ -37,6 +37,10 @@ Revision History: - #ifndef _COMMON_TYPES_H_ - #define _COMMON_TYPES_H_ - -+#ifdef HAVE_CONFIG_H -+#include "config.h" -+#endif -+ - #ifndef LINUX - #if _MSC_EXTENSIONS - -@@ -47,7 +51,9 @@ Revision History: - // typedef __int64 int64_t; - typedef unsigned __int32 uint32_t; - typedef __int32 int32_t; --#elif defined (__linux__) || defined (__NetBSD__) || defined(__sun) || defined(__OpenBSD__) || defined (__FreeBSD__) -+#elif defined (__linux__) || defined (__NetBSD__) \ -+ || defined(__sun) || defined(__OpenBSD__) \ -+ || defined (__FreeBSD__) || defined(__DragonFly__) || defined(__GLIBC__) - typedef unsigned int uint32_t; - typedef int int32_t; - #else -@@ -149,6 +155,18 @@ typedef unsigned long ULONG_PTR; - #ifndef FGL_LINUX - #pragma warning ( default : 4142 ) - #endif -+ -+#ifndef ATOM_BIG_ENDIAN -+#ifdef X_BYTE_ORDER -+#if X_BYTE_ORDER == X_BIG_ENDIAN -+#define ATOM_BIG_ENDIAN 1 -+#endif -+#endif -+#endif -+#ifndef ATOM_BIG_ENDIAN -+#define ATOM_BIG_ENDIAN 0 -+#endif -+ - #endif // _COMMON_TYPES_H_ - - // EOF -diff --git a/src/AtomBios/includes/CD_Definitions.h b/src/AtomBios/includes/CD_Definitions.h -index 98fd495..c00e93e 100644 ---- a/src/AtomBios/includes/CD_Definitions.h -+++ b/src/AtomBios/includes/CD_Definitions.h -@@ -39,11 +39,12 @@ NEG:27.08.2002 Initiated. - #ifndef _CD_DEFINITIONS_H - #define _CD_DEFINITIONS_H_ - #ifdef DRIVER_PARSER --VOID *AllocateMemory(VOID *, UINT16); -+VOID *AllocateMemory(DEVICE_DATA *, UINT16); - VOID ReleaseMemory(DEVICE_DATA * , WORKING_TABLE_DATA* ); - #endif - CD_STATUS ParseTable(DEVICE_DATA* pDeviceData, UINT8 IndexInMasterTable); - //CD_STATUS CD_MainLoop(PARSER_TEMP_DATA_POINTER pParserTempData); - CD_STATUS Main_Loop(DEVICE_DATA* pDeviceData,UINT16 *MasterTableOffset,UINT8 IndexInMasterTable); - UINT16* GetCommandMasterTablePointer(DEVICE_DATA* pDeviceData); -+ATOM_TABLE_ATTRIBUTE GetCommandTableAttribute(UINT8 *pTableHeader); - #endif //CD_DEFINITIONS -diff --git a/src/AtomBios/includes/CD_Structs.h b/src/AtomBios/includes/CD_Structs.h -index c43f81d..01fb80e 100644 ---- a/src/AtomBios/includes/CD_Structs.h -+++ b/src/AtomBios/includes/CD_Structs.h -@@ -35,10 +35,18 @@ Revision History: - NEG:26.08.2002 Initiated. - --*/ - --#include "CD_binding.h" - #ifndef _CD_STRUCTS_H_ - #define _CD_STRUCTS_H_ - -+#include "CD_binding.h" -+ -+/* Endaianness should be specified before inclusion, -+ * default to little endian -+ */ -+#ifndef ATOM_BIG_ENDIAN -+#error Endian not specified -+#endif -+ - #ifdef UEFI_BUILD - typedef UINT16** PTABLE_UNIT_TYPE; - typedef UINTN TABLE_UNIT_TYPE; -@@ -304,9 +312,15 @@ typedef union _PARAMETER_ACCESS { - }PARAMETER_ACCESS; - - typedef struct _COMMAND_ATTRIBUTE { -+#if ATOM_BIG_ENDIAN -+ UINT8 DestinationAlignment:2; -+ UINT8 SourceAlignment:3; -+ UINT8 Source:3; -+#else - UINT8 Source:3; - UINT8 SourceAlignment:3; - UINT8 DestinationAlignment:2; -+#endif - }COMMAND_ATTRIBUTE; - - typedef struct _SOURCE_DESTINATION_ALIGNMENT{ -@@ -363,11 +377,19 @@ typedef union _COMMAND_SPECIFIC_UNION{ - - - typedef struct _CD_GENERIC_BYTE{ -+#if ATOM_BIG_ENDIAN -+ UINT16 PS_SizeInDwordsUsedByCallingTable:5; -+ UINT16 CurrentPort:2; -+ UINT16 CommandAccessType:3; -+ UINT16 CurrentParameterSize:3; -+ UINT16 CommandType:3; -+#else - UINT16 CommandType:3; - UINT16 CurrentParameterSize:3; - UINT16 CommandAccessType:3; - UINT16 CurrentPort:2; - UINT16 PS_SizeInDwordsUsedByCallingTable:5; -+#endif - }CD_GENERIC_BYTE; - - typedef UINT8 COMMAND_TYPE_OPCODE_ONLY; -diff --git a/src/AtomBios/includes/Decoder.h b/src/AtomBios/includes/Decoder.h -index 24c25fc..1e143f0 100644 ---- a/src/AtomBios/includes/Decoder.h -+++ b/src/AtomBios/includes/Decoder.h -@@ -47,12 +47,32 @@ NEG:27.08.2002 Initiated. - #define PARSER_VERSION_MAJOR 0x00000000 - #define PARSER_VERSION_MINOR 0x0000000E - #define PARSER_VERSION (PARSER_VERSION_MAJOR | PARSER_VERSION_MINOR) --#include "CD_binding.h" -+ - #include "CD_Common_Types.h" -+ -+#include "atombios.h" -+ -+/* these depends on some struct defined in atombios.h */ -+#include "CD_binding.h" - #include "CD_hw_services.h" - #include "CD_Structs.h" --#include "CD_Definitions.h" - #include "CD_Opcodes.h" -+#include "CD_Definitions.h" -+ -+#if ATOM_BIG_ENDIAN -+extern UINT16 ATOM_BSWAP16(UINT16 x); -+extern UINT32 ATOM_BSWAP32(UINT32 x); -+ -+#define CPU_TO_UINT16LE(x) ATOM_BSWAP16(x) -+#define CPU_TO_UINT32LE(x) ATOM_BSWAP32(x) -+#define UINT16LE_TO_CPU(x) ATOM_BSWAP16(x) -+#define UINT32LE_TO_CPU(x) ATOM_BSWAP32(x) -+#else -+#define CPU_TO_UINT16LE(x) (x) -+#define CPU_TO_UINT32LE(x) (x) -+#define UINT16LE_TO_CPU(x) (x) -+#define UINT32LE_TO_CPU(x) (x) -+#endif - - #define SOURCE_ONLY_CMD_TYPE 0//0xFE - #define SOURCE_DESTINATION_CMD_TYPE 1//0xFD -diff --git a/src/AtomBios/includes/ObjectID.h b/src/AtomBios/includes/ObjectID.h -index e6d41fe..4b106cf 100644 ---- a/src/AtomBios/includes/ObjectID.h -+++ b/src/AtomBios/includes/ObjectID.h -@@ -18,467 +18,467 @@ - * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, - * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. --*/ --/* based on stg/asic_reg/drivers/inc/asic_reg/ObjectID.h ver 23 */ -- --#ifndef _OBJECTID_H --#define _OBJECTID_H -- --#if defined(_X86_) --#pragma pack(1) --#endif -- --/****************************************************/ --/* Graphics Object Type Definition */ --/****************************************************/ --#define GRAPH_OBJECT_TYPE_NONE 0x0 --#define GRAPH_OBJECT_TYPE_GPU 0x1 --#define GRAPH_OBJECT_TYPE_ENCODER 0x2 --#define GRAPH_OBJECT_TYPE_CONNECTOR 0x3 --#define GRAPH_OBJECT_TYPE_ROUTER 0x4 --/* deleted */ -- --/****************************************************/ --/* Encoder Object ID Definition */ --/****************************************************/ --#define ENCODER_OBJECT_ID_NONE 0x00 -- --/* Radeon Class Display Hardware */ --#define ENCODER_OBJECT_ID_INTERNAL_LVDS 0x01 --#define ENCODER_OBJECT_ID_INTERNAL_TMDS1 0x02 --#define ENCODER_OBJECT_ID_INTERNAL_TMDS2 0x03 --#define ENCODER_OBJECT_ID_INTERNAL_DAC1 0x04 --#define ENCODER_OBJECT_ID_INTERNAL_DAC2 0x05 /* TV/CV DAC */ --#define ENCODER_OBJECT_ID_INTERNAL_SDVOA 0x06 --#define ENCODER_OBJECT_ID_INTERNAL_SDVOB 0x07 -- --/* External Third Party Encoders */ --#define ENCODER_OBJECT_ID_SI170B 0x08 --#define ENCODER_OBJECT_ID_CH7303 0x09 --#define ENCODER_OBJECT_ID_CH7301 0x0A --#define ENCODER_OBJECT_ID_INTERNAL_DVO1 0x0B /* This belongs to Radeon Class Display Hardware */ --#define ENCODER_OBJECT_ID_EXTERNAL_SDVOA 0x0C --#define ENCODER_OBJECT_ID_EXTERNAL_SDVOB 0x0D --#define ENCODER_OBJECT_ID_TITFP513 0x0E --#define ENCODER_OBJECT_ID_INTERNAL_LVTM1 0x0F /* not used for Radeon */ --#define ENCODER_OBJECT_ID_VT1623 0x10 --#define ENCODER_OBJECT_ID_HDMI_SI1930 0x11 --#define ENCODER_OBJECT_ID_HDMI_INTERNAL 0x12 --/* Kaleidoscope (KLDSCP) Class Display Hardware (internal) */ --#define ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1 0x13 --#define ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1 0x14 --#define ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1 0x15 --#define ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2 0x16 /* Shared with CV/TV and CRT */ --#define ENCODER_OBJECT_ID_SI178 0X17 /* External TMDS (dual link, no HDCP.) */ --#define ENCODER_OBJECT_ID_MVPU_FPGA 0x18 /* MVPU FPGA chip */ --#define ENCODER_OBJECT_ID_INTERNAL_DDI 0x19 --#define ENCODER_OBJECT_ID_VT1625 0x1A --#define ENCODER_OBJECT_ID_HDMI_SI1932 0x1B --#define ENCODER_OBJECT_ID_DP_AN9801 0x1C --#define ENCODER_OBJECT_ID_DP_DP501 0x1D --#define ENCODER_OBJECT_ID_INTERNAL_UNIPHY 0x1E --#define ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA 0x1F -- --/****************************************************/ --/* Connector Object ID Definition */ --/****************************************************/ --#define CONNECTOR_OBJECT_ID_NONE 0x00 --#define CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I 0x01 --#define CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_I 0x02 --#define CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_D 0x03 --#define CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_D 0x04 --#define CONNECTOR_OBJECT_ID_VGA 0x05 --#define CONNECTOR_OBJECT_ID_COMPOSITE 0x06 --#define CONNECTOR_OBJECT_ID_SVIDEO 0x07 --#define CONNECTOR_OBJECT_ID_YPbPr 0x08 --#define CONNECTOR_OBJECT_ID_D_CONNECTOR 0x09 --#define CONNECTOR_OBJECT_ID_9PIN_DIN 0x0A /* Supports both CV & TV */ --#define CONNECTOR_OBJECT_ID_SCART 0x0B --#define CONNECTOR_OBJECT_ID_HDMI_TYPE_A 0x0C --#define CONNECTOR_OBJECT_ID_HDMI_TYPE_B 0x0D --#define CONNECTOR_OBJECT_ID_LVDS 0x0E --#define CONNECTOR_OBJECT_ID_7PIN_DIN 0x0F --#define CONNECTOR_OBJECT_ID_PCIE_CONNECTOR 0x10 --#define CONNECTOR_OBJECT_ID_CROSSFIRE 0x11 --#define CONNECTOR_OBJECT_ID_HARDCODE_DVI 0x12 --#define CONNECTOR_OBJECT_ID_DISPLAYPORT 0x13 -- --/* deleted */ -- --/****************************************************/ --/* Router Object ID Definition */ --/****************************************************/ --#define ROUTER_OBJECT_ID_NONE 0x00 --#define ROUTER_OBJECT_ID_I2C_EXTENDER_CNTL 0x01 -- --/****************************************************/ --// Graphics Object ENUM ID Definition */ --/****************************************************/ --#define GRAPH_OBJECT_ENUM_ID1 0x01 --#define GRAPH_OBJECT_ENUM_ID2 0x02 --#define GRAPH_OBJECT_ENUM_ID3 0x03 --#define GRAPH_OBJECT_ENUM_ID4 0x04 -- --/****************************************************/ --/* Graphics Object ID Bit definition */ --/****************************************************/ --#define OBJECT_ID_MASK 0x00FF --#define ENUM_ID_MASK 0x0700 --#define RESERVED1_ID_MASK 0x0800 --#define OBJECT_TYPE_MASK 0x7000 --#define RESERVED2_ID_MASK 0x8000 -- --#define OBJECT_ID_SHIFT 0x00 --#define ENUM_ID_SHIFT 0x08 --#define OBJECT_TYPE_SHIFT 0x0C -- -- --/****************************************************/ --/* Graphics Object family definition */ --/****************************************************/ --#define CONSTRUCTOBJECTFAMILYID(GRAPHICS_OBJECT_TYPE, GRAPHICS_OBJECT_ID) (GRAPHICS_OBJECT_TYPE << OBJECT_TYPE_SHIFT | \ -- GRAPHICS_OBJECT_ID << OBJECT_ID_SHIFT) --/****************************************************/ --/* GPU Object ID definition - Shared with BIOS */ --/****************************************************/ --#define GPU_ENUM_ID1 ( GRAPH_OBJECT_TYPE_GPU << OBJECT_TYPE_SHIFT |\ -- GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT) -- --/****************************************************/ --/* Encoder Object ID definition - Shared with BIOS */ --/****************************************************/ --/* --#define ENCODER_INTERNAL_LVDS_ENUM_ID1 0x2101 --#define ENCODER_INTERNAL_TMDS1_ENUM_ID1 0x2102 --#define ENCODER_INTERNAL_TMDS2_ENUM_ID1 0x2103 --#define ENCODER_INTERNAL_DAC1_ENUM_ID1 0x2104 --#define ENCODER_INTERNAL_DAC2_ENUM_ID1 0x2105 --#define ENCODER_INTERNAL_SDVOA_ENUM_ID1 0x2106 --#define ENCODER_INTERNAL_SDVOB_ENUM_ID1 0x2107 --#define ENCODER_SIL170B_ENUM_ID1 0x2108 --#define ENCODER_CH7303_ENUM_ID1 0x2109 --#define ENCODER_CH7301_ENUM_ID1 0x210A --#define ENCODER_INTERNAL_DVO1_ENUM_ID1 0x210B --#define ENCODER_EXTERNAL_SDVOA_ENUM_ID1 0x210C --#define ENCODER_EXTERNAL_SDVOB_ENUM_ID1 0x210D --#define ENCODER_TITFP513_ENUM_ID1 0x210E --#define ENCODER_INTERNAL_LVTM1_ENUM_ID1 0x210F --#define ENCODER_VT1623_ENUM_ID1 0x2110 --#define ENCODER_HDMI_SI1930_ENUM_ID1 0x2111 --#define ENCODER_HDMI_INTERNAL_ENUM_ID1 0x2112 --#define ENCODER_INTERNAL_KLDSCP_TMDS1_ENUM_ID1 0x2113 --#define ENCODER_INTERNAL_KLDSCP_DVO1_ENUM_ID1 0x2114 --#define ENCODER_INTERNAL_KLDSCP_DAC1_ENUM_ID1 0x2115 --#define ENCODER_INTERNAL_KLDSCP_DAC2_ENUM_ID1 0x2116 --#define ENCODER_SI178_ENUM_ID1 0x2117 --#define ENCODER_MVPU_FPGA_ENUM_ID1 0x2118 --#define ENCODER_INTERNAL_DDI_ENUM_ID1 0x2119 --#define ENCODER_VT1625_ENUM_ID1 0x211A --#define ENCODER_HDMI_SI1932_ENUM_ID1 0x211B --#define ENCODER_ENCODER_DP_AN9801_ENUM_ID1 0x211C --#define ENCODER_DP_DP501_ENUM_ID1 0x211D --#define ENCODER_INTERNAL_UNIPHY_ENUM_ID1 0x211E --*/ --#define ENCODER_INTERNAL_LVDS_ENUM_ID1 ( GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\ -- GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\ -- ENCODER_OBJECT_ID_INTERNAL_LVDS << OBJECT_ID_SHIFT) -- --#define ENCODER_INTERNAL_TMDS1_ENUM_ID1 ( GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\ -- GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\ -- ENCODER_OBJECT_ID_INTERNAL_TMDS1 << OBJECT_ID_SHIFT) -- --#define ENCODER_INTERNAL_TMDS2_ENUM_ID1 ( GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\ -- GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\ -- ENCODER_OBJECT_ID_INTERNAL_TMDS2 << OBJECT_ID_SHIFT) -- --#define ENCODER_INTERNAL_DAC1_ENUM_ID1 ( GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\ -- GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\ -- ENCODER_OBJECT_ID_INTERNAL_DAC1 << OBJECT_ID_SHIFT) -- --#define ENCODER_INTERNAL_DAC2_ENUM_ID1 ( GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\ -- GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\ -- ENCODER_OBJECT_ID_INTERNAL_DAC2 << OBJECT_ID_SHIFT) -- --#define ENCODER_INTERNAL_SDVOA_ENUM_ID1 ( GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\ -- GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\ -- ENCODER_OBJECT_ID_INTERNAL_SDVOA << OBJECT_ID_SHIFT) -- --#define ENCODER_INTERNAL_SDVOA_ENUM_ID2 ( GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\ -- GRAPH_OBJECT_ENUM_ID2 << ENUM_ID_SHIFT |\ -- ENCODER_OBJECT_ID_INTERNAL_SDVOA << OBJECT_ID_SHIFT) -- --#define ENCODER_INTERNAL_SDVOB_ENUM_ID1 ( GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\ -- GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\ -- ENCODER_OBJECT_ID_INTERNAL_SDVOB << OBJECT_ID_SHIFT) -- --#define ENCODER_SIL170B_ENUM_ID1 ( GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\ -- GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\ -- ENCODER_OBJECT_ID_SI170B << OBJECT_ID_SHIFT) -- --#define ENCODER_CH7303_ENUM_ID1 ( GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\ -- GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\ -- ENCODER_OBJECT_ID_CH7303 << OBJECT_ID_SHIFT) -- --#define ENCODER_CH7301_ENUM_ID1 ( GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\ -- GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\ -- ENCODER_OBJECT_ID_CH7301 << OBJECT_ID_SHIFT) -- --#define ENCODER_INTERNAL_DVO1_ENUM_ID1 ( GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\ -- GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\ -- ENCODER_OBJECT_ID_INTERNAL_DVO1 << OBJECT_ID_SHIFT) -- --#define ENCODER_EXTERNAL_SDVOA_ENUM_ID1 ( GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\ -- GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\ -- ENCODER_OBJECT_ID_EXTERNAL_SDVOA << OBJECT_ID_SHIFT) -- --#define ENCODER_EXTERNAL_SDVOA_ENUM_ID2 ( GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\ -- GRAPH_OBJECT_ENUM_ID2 << ENUM_ID_SHIFT |\ -- ENCODER_OBJECT_ID_EXTERNAL_SDVOA << OBJECT_ID_SHIFT) -- -- --#define ENCODER_EXTERNAL_SDVOB_ENUM_ID1 ( GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\ -- GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\ -- ENCODER_OBJECT_ID_EXTERNAL_SDVOB << OBJECT_ID_SHIFT) -- -- --#define ENCODER_TITFP513_ENUM_ID1 ( GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\ -- GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\ -- ENCODER_OBJECT_ID_TITFP513 << OBJECT_ID_SHIFT) -- --#define ENCODER_INTERNAL_LVTM1_ENUM_ID1 ( GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\ -- GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\ -- ENCODER_OBJECT_ID_INTERNAL_LVTM1 << OBJECT_ID_SHIFT) -- --#define ENCODER_VT1623_ENUM_ID1 ( GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\ -- GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\ -- ENCODER_OBJECT_ID_VT1623 << OBJECT_ID_SHIFT) -- --#define ENCODER_HDMI_SI1930_ENUM_ID1 ( GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\ -- GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\ -- ENCODER_OBJECT_ID_HDMI_SI1930 << OBJECT_ID_SHIFT) -- --#define ENCODER_HDMI_INTERNAL_ENUM_ID1 ( GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\ -- GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\ -- ENCODER_OBJECT_ID_HDMI_INTERNAL << OBJECT_ID_SHIFT) -- --#define ENCODER_INTERNAL_KLDSCP_TMDS1_ENUM_ID1 ( GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\ -- GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\ -- ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1 << OBJECT_ID_SHIFT) -- -- --#define ENCODER_INTERNAL_KLDSCP_TMDS1_ENUM_ID2 ( GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\ -- GRAPH_OBJECT_ENUM_ID2 << ENUM_ID_SHIFT |\ -- ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1 << OBJECT_ID_SHIFT) -- -- --#define ENCODER_INTERNAL_KLDSCP_DVO1_ENUM_ID1 ( GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\ -- GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\ -- ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1 << OBJECT_ID_SHIFT) -- --#define ENCODER_INTERNAL_KLDSCP_DAC1_ENUM_ID1 ( GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\ -- GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\ -- ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1 << OBJECT_ID_SHIFT) -- --#define ENCODER_INTERNAL_KLDSCP_DAC2_ENUM_ID1 ( GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\ -- GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\ -- ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2 << OBJECT_ID_SHIFT) // Shared with CV/TV and CRT -- --#define ENCODER_SI178_ENUM_ID1 ( GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\ -- GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\ -- ENCODER_OBJECT_ID_SI178 << OBJECT_ID_SHIFT) -- --#define ENCODER_MVPU_FPGA_ENUM_ID1 ( GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\ -- GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\ -- ENCODER_OBJECT_ID_MVPU_FPGA << OBJECT_ID_SHIFT) -- --#define ENCODER_INTERNAL_DDI_ENUM_ID1 ( GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\ -- GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\ -- ENCODER_OBJECT_ID_INTERNAL_DDI << OBJECT_ID_SHIFT) -- --#define ENCODER_VT1625_ENUM_ID1 ( GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\ -- GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\ -- ENCODER_OBJECT_ID_VT1625 << OBJECT_ID_SHIFT) -- --#define ENCODER_HDMI_SI1932_ENUM_ID1 ( GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\ -- GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\ -- ENCODER_OBJECT_ID_HDMI_SI1932 << OBJECT_ID_SHIFT) -- --#define ENCODER_DP_DP501_ENUM_ID1 ( GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\ -- GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\ -- ENCODER_OBJECT_ID_DP_DP501 << OBJECT_ID_SHIFT) -- --#define ENCODER_DP_AN9801_ENUM_ID1 ( GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\ -- GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\ -- ENCODER_OBJECT_ID_DP_AN9801 << OBJECT_ID_SHIFT) -- --#define ENCODER_INTERNAL_UNIPHY_ENUM_ID1 ( GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\ -- GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\ -- ENCODER_OBJECT_ID_INTERNAL_UNIPHY << OBJECT_ID_SHIFT) -- --#define ENCODER_INTERNAL_UNIPHY_ENUM_ID2 ( GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\ -- GRAPH_OBJECT_ENUM_ID2 << ENUM_ID_SHIFT |\ -- ENCODER_OBJECT_ID_INTERNAL_UNIPHY << OBJECT_ID_SHIFT) -- --#define ENCODER_INTERNAL_KLDSCP_LVTMA_ENUM_ID1 ( GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\ -- GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\ -- ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA << OBJECT_ID_SHIFT) -- --/****************************************************/ --/* Connector Object ID definition - Shared with BIOS */ --/****************************************************/ --/* --#define CONNECTOR_SINGLE_LINK_DVI_I_ENUM_ID1 0x3101 --#define CONNECTOR_DUAL_LINK_DVI_I_ENUM_ID1 0x3102 --#define CONNECTOR_SINGLE_LINK_DVI_D_ENUM_ID1 0x3103 --#define CONNECTOR_DUAL_LINK_DVI_D_ENUM_ID1 0x3104 --#define CONNECTOR_VGA_ENUM_ID1 0x3105 --#define CONNECTOR_COMPOSITE_ENUM_ID1 0x3106 --#define CONNECTOR_SVIDEO_ENUM_ID1 0x3107 --#define CONNECTOR_YPbPr_ENUM_ID1 0x3108 --#define CONNECTOR_D_CONNECTORE_ENUM_ID1 0x3109 --#define CONNECTOR_9PIN_DIN_ENUM_ID1 0x310A --#define CONNECTOR_SCART_ENUM_ID1 0x310B --#define CONNECTOR_HDMI_TYPE_A_ENUM_ID1 0x310C --#define CONNECTOR_HDMI_TYPE_B_ENUM_ID1 0x310D --#define CONNECTOR_LVDS_ENUM_ID1 0x310E --#define CONNECTOR_7PIN_DIN_ENUM_ID1 0x310F --#define CONNECTOR_PCIE_CONNECTOR_ENUM_ID1 0x3110 --*/ --#define CONNECTOR_LVDS_ENUM_ID1 ( GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\ -- GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\ -- CONNECTOR_OBJECT_ID_LVDS << OBJECT_ID_SHIFT) -- --#define CONNECTOR_SINGLE_LINK_DVI_I_ENUM_ID1 ( GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\ -- GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\ -- CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I << OBJECT_ID_SHIFT) -- --#define CONNECTOR_SINGLE_LINK_DVI_I_ENUM_ID2 ( GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\ -- GRAPH_OBJECT_ENUM_ID2 << ENUM_ID_SHIFT |\ -- CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I << OBJECT_ID_SHIFT) -- --#define CONNECTOR_DUAL_LINK_DVI_I_ENUM_ID1 ( GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\ -- GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\ -- CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_I << OBJECT_ID_SHIFT) -- --#define CONNECTOR_DUAL_LINK_DVI_I_ENUM_ID2 ( GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\ -- GRAPH_OBJECT_ENUM_ID2 << ENUM_ID_SHIFT |\ -- CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_I << OBJECT_ID_SHIFT) -- --#define CONNECTOR_SINGLE_LINK_DVI_D_ENUM_ID1 ( GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\ -- GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\ -- CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_D << OBJECT_ID_SHIFT) -- --#define CONNECTOR_SINGLE_LINK_DVI_D_ENUM_ID2 ( GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\ -- GRAPH_OBJECT_ENUM_ID2 << ENUM_ID_SHIFT |\ -- CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_D << OBJECT_ID_SHIFT) -- --#define CONNECTOR_DUAL_LINK_DVI_D_ENUM_ID1 ( GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\ -- GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\ -- CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_D << OBJECT_ID_SHIFT) -- --#define CONNECTOR_VGA_ENUM_ID1 ( GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\ -- GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\ -- CONNECTOR_OBJECT_ID_VGA << OBJECT_ID_SHIFT) -- --#define CONNECTOR_VGA_ENUM_ID2 ( GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\ -- GRAPH_OBJECT_ENUM_ID2 << ENUM_ID_SHIFT |\ -- CONNECTOR_OBJECT_ID_VGA << OBJECT_ID_SHIFT) -- --#define CONNECTOR_COMPOSITE_ENUM_ID1 ( GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\ -- GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\ -- CONNECTOR_OBJECT_ID_COMPOSITE << OBJECT_ID_SHIFT) -- --#define CONNECTOR_SVIDEO_ENUM_ID1 ( GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\ -- GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\ -- CONNECTOR_OBJECT_ID_SVIDEO << OBJECT_ID_SHIFT) -- --#define CONNECTOR_YPbPr_ENUM_ID1 ( GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\ -- GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\ -- CONNECTOR_OBJECT_ID_YPbPr << OBJECT_ID_SHIFT) -- --#define CONNECTOR_D_CONNECTOR_ENUM_ID1 ( GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\ -- GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\ -- CONNECTOR_OBJECT_ID_D_CONNECTOR << OBJECT_ID_SHIFT) -- --#define CONNECTOR_9PIN_DIN_ENUM_ID1 ( GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\ -- GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\ -- CONNECTOR_OBJECT_ID_9PIN_DIN << OBJECT_ID_SHIFT) -- --#define CONNECTOR_SCART_ENUM_ID1 ( GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\ -- GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\ -- CONNECTOR_OBJECT_ID_SCART << OBJECT_ID_SHIFT) -- --#define CONNECTOR_HDMI_TYPE_A_ENUM_ID1 ( GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\ -- GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\ -- CONNECTOR_OBJECT_ID_HDMI_TYPE_A << OBJECT_ID_SHIFT) -- --#define CONNECTOR_HDMI_TYPE_B_ENUM_ID1 ( GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\ -- GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\ -- CONNECTOR_OBJECT_ID_HDMI_TYPE_B << OBJECT_ID_SHIFT) -- --#define CONNECTOR_7PIN_DIN_ENUM_ID1 ( GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\ -- GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\ -- CONNECTOR_OBJECT_ID_7PIN_DIN << OBJECT_ID_SHIFT) -- --#define CONNECTOR_PCIE_CONNECTOR_ENUM_ID1 ( GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\ -- GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\ -- CONNECTOR_OBJECT_ID_PCIE_CONNECTOR << OBJECT_ID_SHIFT) -- --#define CONNECTOR_PCIE_CONNECTOR_ENUM_ID2 ( GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\ -- GRAPH_OBJECT_ENUM_ID2 << ENUM_ID_SHIFT |\ -- CONNECTOR_OBJECT_ID_PCIE_CONNECTOR << OBJECT_ID_SHIFT) -- --#define CONNECTOR_CROSSFIRE_ENUM_ID1 ( GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\ -- GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\ -- CONNECTOR_OBJECT_ID_CROSSFIRE << OBJECT_ID_SHIFT) -- --#define CONNECTOR_CROSSFIRE_ENUM_ID2 ( GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\ -- GRAPH_OBJECT_ENUM_ID2 << ENUM_ID_SHIFT |\ -- CONNECTOR_OBJECT_ID_CROSSFIRE << OBJECT_ID_SHIFT) -- -- --#define CONNECTOR_HARDCODE_DVI_ENUM_ID1 ( GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\ -- GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\ -- CONNECTOR_OBJECT_ID_HARDCODE_DVI << OBJECT_ID_SHIFT) -- --#define CONNECTOR_HARDCODE_DVI_ENUM_ID2 ( GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\ -- GRAPH_OBJECT_ENUM_ID2 << ENUM_ID_SHIFT |\ -- CONNECTOR_OBJECT_ID_HARDCODE_DVI << OBJECT_ID_SHIFT) -- --#define CONNECTOR_DISPLAYPORT_ENUM_ID1 ( GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\ -- GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\ -- CONNECTOR_OBJECT_ID_DISPLAYPORT << OBJECT_ID_SHIFT) -- --#define CONNECTOR_DISPLAYPORT_ENUM_ID2 ( GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\ -- GRAPH_OBJECT_ENUM_ID2 << ENUM_ID_SHIFT |\ -- CONNECTOR_OBJECT_ID_DISPLAYPORT << OBJECT_ID_SHIFT) -- --/****************************************************/ --/* Router Object ID definition - Shared with BIOS */ --/****************************************************/ --#define ROUTER_I2C_EXTENDER_CNTL_ENUM_ID1 ( GRAPH_OBJECT_TYPE_ROUTER << OBJECT_TYPE_SHIFT |\ -- GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\ -- ROUTER_OBJECT_ID_I2C_EXTENDER_CNTL << OBJECT_ID_SHIFT) -- --/* deleted */ -- --/****************************************************/ --/* Object Cap definition - Shared with BIOS */ --/****************************************************/ --#define GRAPHICS_OBJECT_CAP_I2C 0x00000001L --#define GRAPHICS_OBJECT_CAP_TABLE_ID 0x00000002L -- -- --#define GRAPHICS_OBJECT_I2CCOMMAND_TABLE_ID 0x01 --#define GRAPHICS_OBJECT_HOTPLUGDETECTIONINTERUPT_TABLE_ID 0x02 --#define GRAPHICS_OBJECT_ENCODER_OUTPUT_PROTECTION_TABLE_ID 0x03 -- --#if defined(_X86_) --#pragma pack() --#endif -- --#endif /*GRAPHICTYPE */ -- -- -- -- -+*/ -+/* based on stg/asic_reg/drivers/inc/asic_reg/ObjectID.h ver 23 */ -+ -+#ifndef _OBJECTID_H -+#define _OBJECTID_H -+ -+#if defined(_X86_) -+#pragma pack(1) -+#endif -+ -+/****************************************************/ -+/* Graphics Object Type Definition */ -+/****************************************************/ -+#define GRAPH_OBJECT_TYPE_NONE 0x0 -+#define GRAPH_OBJECT_TYPE_GPU 0x1 -+#define GRAPH_OBJECT_TYPE_ENCODER 0x2 -+#define GRAPH_OBJECT_TYPE_CONNECTOR 0x3 -+#define GRAPH_OBJECT_TYPE_ROUTER 0x4 -+/* deleted */ -+ -+/****************************************************/ -+/* Encoder Object ID Definition */ -+/****************************************************/ -+#define ENCODER_OBJECT_ID_NONE 0x00 -+ -+/* Radeon Class Display Hardware */ -+#define ENCODER_OBJECT_ID_INTERNAL_LVDS 0x01 -+#define ENCODER_OBJECT_ID_INTERNAL_TMDS1 0x02 -+#define ENCODER_OBJECT_ID_INTERNAL_TMDS2 0x03 -+#define ENCODER_OBJECT_ID_INTERNAL_DAC1 0x04 -+#define ENCODER_OBJECT_ID_INTERNAL_DAC2 0x05 /* TV/CV DAC */ -+#define ENCODER_OBJECT_ID_INTERNAL_SDVOA 0x06 -+#define ENCODER_OBJECT_ID_INTERNAL_SDVOB 0x07 -+ -+/* External Third Party Encoders */ -+#define ENCODER_OBJECT_ID_SI170B 0x08 -+#define ENCODER_OBJECT_ID_CH7303 0x09 -+#define ENCODER_OBJECT_ID_CH7301 0x0A -+#define ENCODER_OBJECT_ID_INTERNAL_DVO1 0x0B /* This belongs to Radeon Class Display Hardware */ -+#define ENCODER_OBJECT_ID_EXTERNAL_SDVOA 0x0C -+#define ENCODER_OBJECT_ID_EXTERNAL_SDVOB 0x0D -+#define ENCODER_OBJECT_ID_TITFP513 0x0E -+#define ENCODER_OBJECT_ID_INTERNAL_LVTM1 0x0F /* not used for Radeon */ -+#define ENCODER_OBJECT_ID_VT1623 0x10 -+#define ENCODER_OBJECT_ID_HDMI_SI1930 0x11 -+#define ENCODER_OBJECT_ID_HDMI_INTERNAL 0x12 -+/* Kaleidoscope (KLDSCP) Class Display Hardware (internal) */ -+#define ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1 0x13 -+#define ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1 0x14 -+#define ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1 0x15 -+#define ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2 0x16 /* Shared with CV/TV and CRT */ -+#define ENCODER_OBJECT_ID_SI178 0X17 /* External TMDS (dual link, no HDCP.) */ -+#define ENCODER_OBJECT_ID_MVPU_FPGA 0x18 /* MVPU FPGA chip */ -+#define ENCODER_OBJECT_ID_INTERNAL_DDI 0x19 -+#define ENCODER_OBJECT_ID_VT1625 0x1A -+#define ENCODER_OBJECT_ID_HDMI_SI1932 0x1B -+#define ENCODER_OBJECT_ID_DP_AN9801 0x1C -+#define ENCODER_OBJECT_ID_DP_DP501 0x1D -+#define ENCODER_OBJECT_ID_INTERNAL_UNIPHY 0x1E -+#define ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA 0x1F -+ -+/****************************************************/ -+/* Connector Object ID Definition */ -+/****************************************************/ -+#define CONNECTOR_OBJECT_ID_NONE 0x00 -+#define CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I 0x01 -+#define CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_I 0x02 -+#define CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_D 0x03 -+#define CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_D 0x04 -+#define CONNECTOR_OBJECT_ID_VGA 0x05 -+#define CONNECTOR_OBJECT_ID_COMPOSITE 0x06 -+#define CONNECTOR_OBJECT_ID_SVIDEO 0x07 -+#define CONNECTOR_OBJECT_ID_YPbPr 0x08 -+#define CONNECTOR_OBJECT_ID_D_CONNECTOR 0x09 -+#define CONNECTOR_OBJECT_ID_9PIN_DIN 0x0A /* Supports both CV & TV */ -+#define CONNECTOR_OBJECT_ID_SCART 0x0B -+#define CONNECTOR_OBJECT_ID_HDMI_TYPE_A 0x0C -+#define CONNECTOR_OBJECT_ID_HDMI_TYPE_B 0x0D -+#define CONNECTOR_OBJECT_ID_LVDS 0x0E -+#define CONNECTOR_OBJECT_ID_7PIN_DIN 0x0F -+#define CONNECTOR_OBJECT_ID_PCIE_CONNECTOR 0x10 -+#define CONNECTOR_OBJECT_ID_CROSSFIRE 0x11 -+#define CONNECTOR_OBJECT_ID_HARDCODE_DVI 0x12 -+#define CONNECTOR_OBJECT_ID_DISPLAYPORT 0x13 -+ -+/* deleted */ -+ -+/****************************************************/ -+/* Router Object ID Definition */ -+/****************************************************/ -+#define ROUTER_OBJECT_ID_NONE 0x00 -+#define ROUTER_OBJECT_ID_I2C_EXTENDER_CNTL 0x01 -+ -+/****************************************************/ -+// Graphics Object ENUM ID Definition */ -+/****************************************************/ -+#define GRAPH_OBJECT_ENUM_ID1 0x01 -+#define GRAPH_OBJECT_ENUM_ID2 0x02 -+#define GRAPH_OBJECT_ENUM_ID3 0x03 -+#define GRAPH_OBJECT_ENUM_ID4 0x04 -+ -+/****************************************************/ -+/* Graphics Object ID Bit definition */ -+/****************************************************/ -+#define OBJECT_ID_MASK 0x00FF -+#define ENUM_ID_MASK 0x0700 -+#define RESERVED1_ID_MASK 0x0800 -+#define OBJECT_TYPE_MASK 0x7000 -+#define RESERVED2_ID_MASK 0x8000 -+ -+#define OBJECT_ID_SHIFT 0x00 -+#define ENUM_ID_SHIFT 0x08 -+#define OBJECT_TYPE_SHIFT 0x0C -+ -+ -+/****************************************************/ -+/* Graphics Object family definition */ -+/****************************************************/ -+#define CONSTRUCTOBJECTFAMILYID(GRAPHICS_OBJECT_TYPE, GRAPHICS_OBJECT_ID) (GRAPHICS_OBJECT_TYPE << OBJECT_TYPE_SHIFT | \ -+ GRAPHICS_OBJECT_ID << OBJECT_ID_SHIFT) -+/****************************************************/ -+/* GPU Object ID definition - Shared with BIOS */ -+/****************************************************/ -+#define GPU_ENUM_ID1 ( GRAPH_OBJECT_TYPE_GPU << OBJECT_TYPE_SHIFT |\ -+ GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT) -+ -+/****************************************************/ -+/* Encoder Object ID definition - Shared with BIOS */ -+/****************************************************/ -+/* -+#define ENCODER_INTERNAL_LVDS_ENUM_ID1 0x2101 -+#define ENCODER_INTERNAL_TMDS1_ENUM_ID1 0x2102 -+#define ENCODER_INTERNAL_TMDS2_ENUM_ID1 0x2103 -+#define ENCODER_INTERNAL_DAC1_ENUM_ID1 0x2104 -+#define ENCODER_INTERNAL_DAC2_ENUM_ID1 0x2105 -+#define ENCODER_INTERNAL_SDVOA_ENUM_ID1 0x2106 -+#define ENCODER_INTERNAL_SDVOB_ENUM_ID1 0x2107 -+#define ENCODER_SIL170B_ENUM_ID1 0x2108 -+#define ENCODER_CH7303_ENUM_ID1 0x2109 -+#define ENCODER_CH7301_ENUM_ID1 0x210A -+#define ENCODER_INTERNAL_DVO1_ENUM_ID1 0x210B -+#define ENCODER_EXTERNAL_SDVOA_ENUM_ID1 0x210C -+#define ENCODER_EXTERNAL_SDVOB_ENUM_ID1 0x210D -+#define ENCODER_TITFP513_ENUM_ID1 0x210E -+#define ENCODER_INTERNAL_LVTM1_ENUM_ID1 0x210F -+#define ENCODER_VT1623_ENUM_ID1 0x2110 -+#define ENCODER_HDMI_SI1930_ENUM_ID1 0x2111 -+#define ENCODER_HDMI_INTERNAL_ENUM_ID1 0x2112 -+#define ENCODER_INTERNAL_KLDSCP_TMDS1_ENUM_ID1 0x2113 -+#define ENCODER_INTERNAL_KLDSCP_DVO1_ENUM_ID1 0x2114 -+#define ENCODER_INTERNAL_KLDSCP_DAC1_ENUM_ID1 0x2115 -+#define ENCODER_INTERNAL_KLDSCP_DAC2_ENUM_ID1 0x2116 -+#define ENCODER_SI178_ENUM_ID1 0x2117 -+#define ENCODER_MVPU_FPGA_ENUM_ID1 0x2118 -+#define ENCODER_INTERNAL_DDI_ENUM_ID1 0x2119 -+#define ENCODER_VT1625_ENUM_ID1 0x211A -+#define ENCODER_HDMI_SI1932_ENUM_ID1 0x211B -+#define ENCODER_ENCODER_DP_AN9801_ENUM_ID1 0x211C -+#define ENCODER_DP_DP501_ENUM_ID1 0x211D -+#define ENCODER_INTERNAL_UNIPHY_ENUM_ID1 0x211E -+*/ -+#define ENCODER_INTERNAL_LVDS_ENUM_ID1 ( GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\ -+ GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\ -+ ENCODER_OBJECT_ID_INTERNAL_LVDS << OBJECT_ID_SHIFT) -+ -+#define ENCODER_INTERNAL_TMDS1_ENUM_ID1 ( GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\ -+ GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\ -+ ENCODER_OBJECT_ID_INTERNAL_TMDS1 << OBJECT_ID_SHIFT) -+ -+#define ENCODER_INTERNAL_TMDS2_ENUM_ID1 ( GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\ -+ GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\ -+ ENCODER_OBJECT_ID_INTERNAL_TMDS2 << OBJECT_ID_SHIFT) -+ -+#define ENCODER_INTERNAL_DAC1_ENUM_ID1 ( GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\ -+ GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\ -+ ENCODER_OBJECT_ID_INTERNAL_DAC1 << OBJECT_ID_SHIFT) -+ -+#define ENCODER_INTERNAL_DAC2_ENUM_ID1 ( GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\ -+ GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\ -+ ENCODER_OBJECT_ID_INTERNAL_DAC2 << OBJECT_ID_SHIFT) -+ -+#define ENCODER_INTERNAL_SDVOA_ENUM_ID1 ( GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\ -+ GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\ -+ ENCODER_OBJECT_ID_INTERNAL_SDVOA << OBJECT_ID_SHIFT) -+ -+#define ENCODER_INTERNAL_SDVOA_ENUM_ID2 ( GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\ -+ GRAPH_OBJECT_ENUM_ID2 << ENUM_ID_SHIFT |\ -+ ENCODER_OBJECT_ID_INTERNAL_SDVOA << OBJECT_ID_SHIFT) -+ -+#define ENCODER_INTERNAL_SDVOB_ENUM_ID1 ( GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\ -+ GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\ -+ ENCODER_OBJECT_ID_INTERNAL_SDVOB << OBJECT_ID_SHIFT) -+ -+#define ENCODER_SIL170B_ENUM_ID1 ( GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\ -+ GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\ -+ ENCODER_OBJECT_ID_SI170B << OBJECT_ID_SHIFT) -+ -+#define ENCODER_CH7303_ENUM_ID1 ( GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\ -+ GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\ -+ ENCODER_OBJECT_ID_CH7303 << OBJECT_ID_SHIFT) -+ -+#define ENCODER_CH7301_ENUM_ID1 ( GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\ -+ GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\ -+ ENCODER_OBJECT_ID_CH7301 << OBJECT_ID_SHIFT) -+ -+#define ENCODER_INTERNAL_DVO1_ENUM_ID1 ( GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\ -+ GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\ -+ ENCODER_OBJECT_ID_INTERNAL_DVO1 << OBJECT_ID_SHIFT) -+ -+#define ENCODER_EXTERNAL_SDVOA_ENUM_ID1 ( GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\ -+ GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\ -+ ENCODER_OBJECT_ID_EXTERNAL_SDVOA << OBJECT_ID_SHIFT) -+ -+#define ENCODER_EXTERNAL_SDVOA_ENUM_ID2 ( GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\ -+ GRAPH_OBJECT_ENUM_ID2 << ENUM_ID_SHIFT |\ -+ ENCODER_OBJECT_ID_EXTERNAL_SDVOA << OBJECT_ID_SHIFT) -+ -+ -+#define ENCODER_EXTERNAL_SDVOB_ENUM_ID1 ( GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\ -+ GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\ -+ ENCODER_OBJECT_ID_EXTERNAL_SDVOB << OBJECT_ID_SHIFT) -+ -+ -+#define ENCODER_TITFP513_ENUM_ID1 ( GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\ -+ GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\ -+ ENCODER_OBJECT_ID_TITFP513 << OBJECT_ID_SHIFT) -+ -+#define ENCODER_INTERNAL_LVTM1_ENUM_ID1 ( GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\ -+ GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\ -+ ENCODER_OBJECT_ID_INTERNAL_LVTM1 << OBJECT_ID_SHIFT) -+ -+#define ENCODER_VT1623_ENUM_ID1 ( GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\ -+ GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\ -+ ENCODER_OBJECT_ID_VT1623 << OBJECT_ID_SHIFT) -+ -+#define ENCODER_HDMI_SI1930_ENUM_ID1 ( GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\ -+ GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\ -+ ENCODER_OBJECT_ID_HDMI_SI1930 << OBJECT_ID_SHIFT) -+ -+#define ENCODER_HDMI_INTERNAL_ENUM_ID1 ( GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\ -+ GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\ -+ ENCODER_OBJECT_ID_HDMI_INTERNAL << OBJECT_ID_SHIFT) -+ -+#define ENCODER_INTERNAL_KLDSCP_TMDS1_ENUM_ID1 ( GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\ -+ GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\ -+ ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1 << OBJECT_ID_SHIFT) -+ -+ -+#define ENCODER_INTERNAL_KLDSCP_TMDS1_ENUM_ID2 ( GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\ -+ GRAPH_OBJECT_ENUM_ID2 << ENUM_ID_SHIFT |\ -+ ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1 << OBJECT_ID_SHIFT) -+ -+ -+#define ENCODER_INTERNAL_KLDSCP_DVO1_ENUM_ID1 ( GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\ -+ GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\ -+ ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1 << OBJECT_ID_SHIFT) -+ -+#define ENCODER_INTERNAL_KLDSCP_DAC1_ENUM_ID1 ( GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\ -+ GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\ -+ ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1 << OBJECT_ID_SHIFT) -+ -+#define ENCODER_INTERNAL_KLDSCP_DAC2_ENUM_ID1 ( GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\ -+ GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\ -+ ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2 << OBJECT_ID_SHIFT) // Shared with CV/TV and CRT -+ -+#define ENCODER_SI178_ENUM_ID1 ( GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\ -+ GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\ -+ ENCODER_OBJECT_ID_SI178 << OBJECT_ID_SHIFT) -+ -+#define ENCODER_MVPU_FPGA_ENUM_ID1 ( GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\ -+ GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\ -+ ENCODER_OBJECT_ID_MVPU_FPGA << OBJECT_ID_SHIFT) -+ -+#define ENCODER_INTERNAL_DDI_ENUM_ID1 ( GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\ -+ GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\ -+ ENCODER_OBJECT_ID_INTERNAL_DDI << OBJECT_ID_SHIFT) -+ -+#define ENCODER_VT1625_ENUM_ID1 ( GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\ -+ GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\ -+ ENCODER_OBJECT_ID_VT1625 << OBJECT_ID_SHIFT) -+ -+#define ENCODER_HDMI_SI1932_ENUM_ID1 ( GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\ -+ GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\ -+ ENCODER_OBJECT_ID_HDMI_SI1932 << OBJECT_ID_SHIFT) -+ -+#define ENCODER_DP_DP501_ENUM_ID1 ( GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\ -+ GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\ -+ ENCODER_OBJECT_ID_DP_DP501 << OBJECT_ID_SHIFT) -+ -+#define ENCODER_DP_AN9801_ENUM_ID1 ( GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\ -+ GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\ -+ ENCODER_OBJECT_ID_DP_AN9801 << OBJECT_ID_SHIFT) -+ -+#define ENCODER_INTERNAL_UNIPHY_ENUM_ID1 ( GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\ -+ GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\ -+ ENCODER_OBJECT_ID_INTERNAL_UNIPHY << OBJECT_ID_SHIFT) -+ -+#define ENCODER_INTERNAL_UNIPHY_ENUM_ID2 ( GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\ -+ GRAPH_OBJECT_ENUM_ID2 << ENUM_ID_SHIFT |\ -+ ENCODER_OBJECT_ID_INTERNAL_UNIPHY << OBJECT_ID_SHIFT) -+ -+#define ENCODER_INTERNAL_KLDSCP_LVTMA_ENUM_ID1 ( GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\ -+ GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\ -+ ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA << OBJECT_ID_SHIFT) -+ -+/****************************************************/ -+/* Connector Object ID definition - Shared with BIOS */ -+/****************************************************/ -+/* -+#define CONNECTOR_SINGLE_LINK_DVI_I_ENUM_ID1 0x3101 -+#define CONNECTOR_DUAL_LINK_DVI_I_ENUM_ID1 0x3102 -+#define CONNECTOR_SINGLE_LINK_DVI_D_ENUM_ID1 0x3103 -+#define CONNECTOR_DUAL_LINK_DVI_D_ENUM_ID1 0x3104 -+#define CONNECTOR_VGA_ENUM_ID1 0x3105 -+#define CONNECTOR_COMPOSITE_ENUM_ID1 0x3106 -+#define CONNECTOR_SVIDEO_ENUM_ID1 0x3107 -+#define CONNECTOR_YPbPr_ENUM_ID1 0x3108 -+#define CONNECTOR_D_CONNECTORE_ENUM_ID1 0x3109 -+#define CONNECTOR_9PIN_DIN_ENUM_ID1 0x310A -+#define CONNECTOR_SCART_ENUM_ID1 0x310B -+#define CONNECTOR_HDMI_TYPE_A_ENUM_ID1 0x310C -+#define CONNECTOR_HDMI_TYPE_B_ENUM_ID1 0x310D -+#define CONNECTOR_LVDS_ENUM_ID1 0x310E -+#define CONNECTOR_7PIN_DIN_ENUM_ID1 0x310F -+#define CONNECTOR_PCIE_CONNECTOR_ENUM_ID1 0x3110 -+*/ -+#define CONNECTOR_LVDS_ENUM_ID1 ( GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\ -+ GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\ -+ CONNECTOR_OBJECT_ID_LVDS << OBJECT_ID_SHIFT) -+ -+#define CONNECTOR_SINGLE_LINK_DVI_I_ENUM_ID1 ( GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\ -+ GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\ -+ CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I << OBJECT_ID_SHIFT) -+ -+#define CONNECTOR_SINGLE_LINK_DVI_I_ENUM_ID2 ( GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\ -+ GRAPH_OBJECT_ENUM_ID2 << ENUM_ID_SHIFT |\ -+ CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I << OBJECT_ID_SHIFT) -+ -+#define CONNECTOR_DUAL_LINK_DVI_I_ENUM_ID1 ( GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\ -+ GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\ -+ CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_I << OBJECT_ID_SHIFT) -+ -+#define CONNECTOR_DUAL_LINK_DVI_I_ENUM_ID2 ( GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\ -+ GRAPH_OBJECT_ENUM_ID2 << ENUM_ID_SHIFT |\ -+ CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_I << OBJECT_ID_SHIFT) -+ -+#define CONNECTOR_SINGLE_LINK_DVI_D_ENUM_ID1 ( GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\ -+ GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\ -+ CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_D << OBJECT_ID_SHIFT) -+ -+#define CONNECTOR_SINGLE_LINK_DVI_D_ENUM_ID2 ( GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\ -+ GRAPH_OBJECT_ENUM_ID2 << ENUM_ID_SHIFT |\ -+ CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_D << OBJECT_ID_SHIFT) -+ -+#define CONNECTOR_DUAL_LINK_DVI_D_ENUM_ID1 ( GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\ -+ GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\ -+ CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_D << OBJECT_ID_SHIFT) -+ -+#define CONNECTOR_VGA_ENUM_ID1 ( GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\ -+ GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\ -+ CONNECTOR_OBJECT_ID_VGA << OBJECT_ID_SHIFT) -+ -+#define CONNECTOR_VGA_ENUM_ID2 ( GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\ -+ GRAPH_OBJECT_ENUM_ID2 << ENUM_ID_SHIFT |\ -+ CONNECTOR_OBJECT_ID_VGA << OBJECT_ID_SHIFT) -+ -+#define CONNECTOR_COMPOSITE_ENUM_ID1 ( GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\ -+ GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\ -+ CONNECTOR_OBJECT_ID_COMPOSITE << OBJECT_ID_SHIFT) -+ -+#define CONNECTOR_SVIDEO_ENUM_ID1 ( GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\ -+ GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\ -+ CONNECTOR_OBJECT_ID_SVIDEO << OBJECT_ID_SHIFT) -+ -+#define CONNECTOR_YPbPr_ENUM_ID1 ( GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\ -+ GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\ -+ CONNECTOR_OBJECT_ID_YPbPr << OBJECT_ID_SHIFT) -+ -+#define CONNECTOR_D_CONNECTOR_ENUM_ID1 ( GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\ -+ GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\ -+ CONNECTOR_OBJECT_ID_D_CONNECTOR << OBJECT_ID_SHIFT) -+ -+#define CONNECTOR_9PIN_DIN_ENUM_ID1 ( GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\ -+ GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\ -+ CONNECTOR_OBJECT_ID_9PIN_DIN << OBJECT_ID_SHIFT) -+ -+#define CONNECTOR_SCART_ENUM_ID1 ( GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\ -+ GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\ -+ CONNECTOR_OBJECT_ID_SCART << OBJECT_ID_SHIFT) -+ -+#define CONNECTOR_HDMI_TYPE_A_ENUM_ID1 ( GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\ -+ GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\ -+ CONNECTOR_OBJECT_ID_HDMI_TYPE_A << OBJECT_ID_SHIFT) -+ -+#define CONNECTOR_HDMI_TYPE_B_ENUM_ID1 ( GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\ -+ GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\ -+ CONNECTOR_OBJECT_ID_HDMI_TYPE_B << OBJECT_ID_SHIFT) -+ -+#define CONNECTOR_7PIN_DIN_ENUM_ID1 ( GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\ -+ GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\ -+ CONNECTOR_OBJECT_ID_7PIN_DIN << OBJECT_ID_SHIFT) -+ -+#define CONNECTOR_PCIE_CONNECTOR_ENUM_ID1 ( GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\ -+ GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\ -+ CONNECTOR_OBJECT_ID_PCIE_CONNECTOR << OBJECT_ID_SHIFT) -+ -+#define CONNECTOR_PCIE_CONNECTOR_ENUM_ID2 ( GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\ -+ GRAPH_OBJECT_ENUM_ID2 << ENUM_ID_SHIFT |\ -+ CONNECTOR_OBJECT_ID_PCIE_CONNECTOR << OBJECT_ID_SHIFT) -+ -+#define CONNECTOR_CROSSFIRE_ENUM_ID1 ( GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\ -+ GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\ -+ CONNECTOR_OBJECT_ID_CROSSFIRE << OBJECT_ID_SHIFT) -+ -+#define CONNECTOR_CROSSFIRE_ENUM_ID2 ( GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\ -+ GRAPH_OBJECT_ENUM_ID2 << ENUM_ID_SHIFT |\ -+ CONNECTOR_OBJECT_ID_CROSSFIRE << OBJECT_ID_SHIFT) -+ -+ -+#define CONNECTOR_HARDCODE_DVI_ENUM_ID1 ( GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\ -+ GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\ -+ CONNECTOR_OBJECT_ID_HARDCODE_DVI << OBJECT_ID_SHIFT) -+ -+#define CONNECTOR_HARDCODE_DVI_ENUM_ID2 ( GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\ -+ GRAPH_OBJECT_ENUM_ID2 << ENUM_ID_SHIFT |\ -+ CONNECTOR_OBJECT_ID_HARDCODE_DVI << OBJECT_ID_SHIFT) -+ -+#define CONNECTOR_DISPLAYPORT_ENUM_ID1 ( GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\ -+ GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\ -+ CONNECTOR_OBJECT_ID_DISPLAYPORT << OBJECT_ID_SHIFT) -+ -+#define CONNECTOR_DISPLAYPORT_ENUM_ID2 ( GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\ -+ GRAPH_OBJECT_ENUM_ID2 << ENUM_ID_SHIFT |\ -+ CONNECTOR_OBJECT_ID_DISPLAYPORT << OBJECT_ID_SHIFT) -+ -+/****************************************************/ -+/* Router Object ID definition - Shared with BIOS */ -+/****************************************************/ -+#define ROUTER_I2C_EXTENDER_CNTL_ENUM_ID1 ( GRAPH_OBJECT_TYPE_ROUTER << OBJECT_TYPE_SHIFT |\ -+ GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\ -+ ROUTER_OBJECT_ID_I2C_EXTENDER_CNTL << OBJECT_ID_SHIFT) -+ -+/* deleted */ -+ -+/****************************************************/ -+/* Object Cap definition - Shared with BIOS */ -+/****************************************************/ -+#define GRAPHICS_OBJECT_CAP_I2C 0x00000001L -+#define GRAPHICS_OBJECT_CAP_TABLE_ID 0x00000002L -+ -+ -+#define GRAPHICS_OBJECT_I2CCOMMAND_TABLE_ID 0x01 -+#define GRAPHICS_OBJECT_HOTPLUGDETECTIONINTERUPT_TABLE_ID 0x02 -+#define GRAPHICS_OBJECT_ENCODER_OUTPUT_PROTECTION_TABLE_ID 0x03 -+ -+#if defined(_X86_) -+#pragma pack() -+#endif -+ -+#endif /*GRAPHICTYPE */ -+ -+ -+ -+ -diff --git a/src/AtomBios/includes/atombios.h b/src/AtomBios/includes/atombios.h -index 16fcf2d..2e7dc6c 100644 ---- a/src/AtomBios/includes/atombios.h -+++ b/src/AtomBios/includes/atombios.h -@@ -34,6 +34,12 @@ - - #define ATOM_HEADER_VERSION (ATOM_VERSION_MAJOR | ATOM_VERSION_MINOR) - -+/* Endianness should be specified before inclusion, -+ * default to little endian -+ */ -+#ifndef ATOM_BIG_ENDIAN -+#error Endian not specified -+#endif - - #ifdef _H2INC - #ifndef ULONG -@@ -304,11 +310,23 @@ typedef struct _ATOM_MASTER_COMMAND_TABLE - - typedef struct _ATOM_TABLE_ATTRIBUTE - { -+#if ATOM_BIG_ENDIAN -+ USHORT UpdatedByUtility:1; //[15]=Table updated by utility flag -+ USHORT PS_SizeInBytes:7; //[14:8]=Size of parameter space in Bytes (multiple of a dword), -+ USHORT WS_SizeInBytes:8; //[7:0]=Size of workspace in Bytes (in multiple of a dword), -+#else - USHORT WS_SizeInBytes:8; //[7:0]=Size of workspace in Bytes (in multiple of a dword), - USHORT PS_SizeInBytes:7; //[14:8]=Size of parameter space in Bytes (multiple of a dword), - USHORT UpdatedByUtility:1; //[15]=Table updated by utility flag -+#endif - }ATOM_TABLE_ATTRIBUTE; - -+typedef union _ATOM_TABLE_ATTRIBUTE_ACCESS -+{ -+ ATOM_TABLE_ATTRIBUTE sbfAccess; -+ USHORT susAccess; -+}ATOM_TABLE_ATTRIBUTE_ACCESS; -+ - // Common header for all command tables. - //Every table pointed by _ATOM_MASTER_COMMAND_TABLE has this common header. - //And the pointer actually points to this header. -@@ -1252,6 +1270,19 @@ typedef struct _ATOM_MULTIMEDIA_CONFIG_INFO - //Please don't add or expand this bitfield structure below, this one will retire soon.! - typedef struct _ATOM_FIRMWARE_CAPABILITY - { -+#if ATOM_BIG_ENDIAN -+ USHORT Reserved:3; -+ USHORT HyperMemory_Size:4; -+ USHORT HyperMemory_Support:1; -+ USHORT PPMode_Assigned:1; -+ USHORT WMI_SUPPORT:1; -+ USHORT GPUControlsBL:1; -+ USHORT EngineClockSS_Support:1; -+ USHORT MemoryClockSS_Support:1; -+ USHORT ExtendedDesktopSupport:1; -+ USHORT DualCRTC_Support:1; -+ USHORT FirmwarePosted:1; -+#else - USHORT FirmwarePosted:1; - USHORT DualCRTC_Support:1; - USHORT ExtendedDesktopSupport:1; -@@ -1263,6 +1294,7 @@ typedef struct _ATOM_FIRMWARE_CAPABILITY - USHORT HyperMemory_Support:1; - USHORT HyperMemory_Size:4; - USHORT Reserved:3; -+#endif - }ATOM_FIRMWARE_CAPABILITY; - - typedef union _ATOM_FIRMWARE_CAPABILITY_ACCESS -@@ -1747,9 +1779,15 @@ for Griffin or Greyhound. SBIOS needs to convert to actual time by: - - typedef struct _ATOM_I2C_ID_CONFIG - { -+#if ATOM_BIG_ENDIAN -+ UCHAR bfHW_Capable:1; -+ UCHAR bfHW_EngineID:3; -+ UCHAR bfI2C_LineMux:4; -+#else - UCHAR bfI2C_LineMux:4; - UCHAR bfHW_EngineID:3; - UCHAR bfHW_Capable:1; -+#endif - }ATOM_I2C_ID_CONFIG; - - typedef union _ATOM_I2C_ID_CONFIG_ACCESS -@@ -1794,6 +1832,19 @@ typedef struct _ATOM_GPIO_I2C_INFO - //Please don't add or expand this bitfield structure below, this one will retire soon.! - typedef struct _ATOM_MODE_MISC_INFO - { -+#if ATOM_BIG_ENDIAN -+ USHORT Reserved:6; -+ USHORT RGB888:1; -+ USHORT DoubleClock:1; -+ USHORT Interlace:1; -+ USHORT CompositeSync:1; -+ USHORT V_ReplicationBy2:1; -+ USHORT H_ReplicationBy2:1; -+ USHORT VerticalCutOff:1; -+ USHORT VSyncPolarity:1; //0=Active High, 1=Active Low -+ USHORT HSyncPolarity:1; //0=Active High, 1=Active Low -+ USHORT HorizontalCutOff:1; -+#else - USHORT HorizontalCutOff:1; - USHORT HSyncPolarity:1; //0=Active High, 1=Active Low - USHORT VSyncPolarity:1; //0=Active High, 1=Active Low -@@ -1805,6 +1856,7 @@ typedef struct _ATOM_MODE_MISC_INFO - USHORT DoubleClock:1; - USHORT RGB888:1; - USHORT Reserved:6; -+#endif - }ATOM_MODE_MISC_INFO; - - typedef union _ATOM_MODE_MISC_INFO_ACCESS -@@ -3386,8 +3438,13 @@ typedef struct _ATOM_MEMORY_VENDOR_BLOCK{ - - - typedef struct _ATOM_MEMORY_SETTING_ID_CONFIG{ -+#if ATOM_BIG_ENDIAN -+ ULONG ucMemBlkId:8; -+ ULONG ulMemClockRange:24; -+#else - ULONG ulMemClockRange:24; - ULONG ucMemBlkId:8; -+#endif - }ATOM_MEMORY_SETTING_ID_CONFIG; - - typedef union _ATOM_MEMORY_SETTING_ID_CONFIG_ACCESS -@@ -4027,8 +4084,13 @@ typedef struct _COMPASSIONATE_DATA - - typedef struct _ATOM_CONNECTOR_INFO - { -+#if ATOM_BIG_ENDIAN -+ UCHAR bfConnectorType:4; -+ UCHAR bfAssociatedDAC:4; -+#else - UCHAR bfAssociatedDAC:4; - UCHAR bfConnectorType:4; -+#endif - }ATOM_CONNECTOR_INFO; - - typedef union _ATOM_CONNECTOR_INFO_ACCESS -diff --git a/src/Makefile.am b/src/Makefile.am -index 70c05e5..97c686b 100644 ---- a/src/Makefile.am -+++ b/src/Makefile.am -@@ -26,10 +26,13 @@ - # _ladir passes a dummy rpath to libtool so the thing will actually link - # TODO: -nostdlib/-Bstatic/-lgcc platform magic, not installing the .a, etc. - -+radeon_drv_la_LIBADD = -+ - if DRI - ATIMISC_DRI_SRCS = atidri.c - R128_DRI_SRCS = r128_dri.c - RADEON_DRI_SRCS = radeon_dri.c -+radeon_drv_la_LIBADD += $(DRI_LIBS) - endif - - RADEON_ATOMBIOS_SOURCES = \ -@@ -66,9 +69,15 @@ if USE_EXA - RADEON_EXA_SOURCES = radeon_exa.c - endif - --AM_CFLAGS = @XORG_CFLAGS@ @DRI_CFLAGS@ @XMODES_CFLAGS@ -DDISABLE_EASF -DENABLE_ALL_SERVICE_FUNCTIONS -DATOM_BIOS -DATOM_BIOS_PARSER -DFGL_LINUX -DDRIVER_PARSER -+AM_CFLAGS = @XORG_CFLAGS@ @DRI_CFLAGS@ @XMODES_CFLAGS@ -DDISABLE_EASF -DENABLE_ALL_SERVICE_FUNCTIONS -DATOM_BIOS -DATOM_BIOS_PARSER -DDRIVER_PARSER -+ - INCLUDES = -I$(srcdir)/AtomBios/includes - -+if XSERVER_LIBPCIACCESS -+ati_drv_la_LIBADD = $(PCIACCESS_LIBS) -+radeon_drv_la_LIBADD += $(PCIACCESS_LIBS) -+endif -+ - ati_drv_la_LTLIBRARIES = ati_drv.la - ati_drv_la_LDFLAGS = -module -avoid-version - ati_drv_ladir = @moduledir@/drivers -diff --git a/src/ati.c b/src/ati.c -index b3f07ca..387aaca 100644 ---- a/src/ati.c -+++ b/src/ati.c -@@ -78,7 +78,7 @@ enum - ATI_CHIP_FAMILY_Radeon - }; - --static int ATIChipID(const CARD16); -+static int ATIChipID(const uint16_t); - - #ifdef XSERVER_LIBPCIACCESS - -@@ -102,7 +102,7 @@ ati_device_get_from_busid(int bus, int dev, int func) - } - - static struct pci_device* --ati_device_get_primary() -+ati_device_get_primary(void) - { - struct pci_device *device = NULL; - struct pci_device_iterator *device_iter; -@@ -249,7 +249,7 @@ ati_gdev_subdriver(pointer options) - * This returns the ATI_CHIP_FAMILY_* value associated with a particular ChipID. - */ - static int --ATIChipID(const CARD16 ChipID) -+ATIChipID(const uint16_t ChipID) - { - switch (ChipID) - { -diff --git a/src/ati.h b/src/ati.h -index 828aae1..86c40a1 100644 ---- a/src/ati.h -+++ b/src/ati.h -@@ -24,6 +24,7 @@ - #define ___ATI_H___ 1 - - #include -+#include - #include "xf86Pci.h" - #include "xf86PciInfo.h" - -@@ -31,4 +32,6 @@ - - #include "xf86_OSproc.h" - -+extern void ati_gdev_subdriver(pointer options); -+ - #endif /* ___ATI_H___ */ -diff --git a/src/ati_pciids_gen.h b/src/ati_pciids_gen.h -index 330d1a9..1da8f1f 100644 ---- a/src/ati_pciids_gen.h -+++ b/src/ati_pciids_gen.h -@@ -1,4 +1,5 @@ - #define PCI_CHIP_RV380_3150 0x3150 -+#define PCI_CHIP_RV380_3151 0x3151 - #define PCI_CHIP_RV380_3152 0x3152 - #define PCI_CHIP_RV380_3154 0x3154 - #define PCI_CHIP_RV380_3E50 0x3E50 -@@ -173,6 +174,7 @@ - #define PCI_CHIP_RV410_564F 0x564F - #define PCI_CHIP_RV410_5652 0x5652 - #define PCI_CHIP_RV410_5653 0x5653 -+#define PCI_CHIP_RV410_5657 0x5657 - #define PCI_CHIP_MACH64VT 0x5654 - #define PCI_CHIP_MACH64VU 0x5655 - #define PCI_CHIP_MACH64VV 0x5656 -@@ -195,7 +197,6 @@ - #define PCI_CHIP_RV370_5B60 0x5B60 - #define PCI_CHIP_RV370_5B62 0x5B62 - #define PCI_CHIP_RV370_5B63 0x5B63 --#define PCI_CHIP_RV370_5657 0x5657 - #define PCI_CHIP_RV370_5B64 0x5B64 - #define PCI_CHIP_RV370_5B65 0x5B65 - #define PCI_CHIP_RV280_5C61 0x5C61 -@@ -281,9 +282,9 @@ - #define PCI_CHIP_RV530_71D6 0x71D6 - #define PCI_CHIP_RV530_71DA 0x71DA - #define PCI_CHIP_RV530_71DE 0x71DE --#define PCI_CHIP_RV530_7200 0x7200 --#define PCI_CHIP_RV530_7210 0x7210 --#define PCI_CHIP_RV530_7211 0x7211 -+#define PCI_CHIP_RV515_7200 0x7200 -+#define PCI_CHIP_RV515_7210 0x7210 -+#define PCI_CHIP_RV515_7211 0x7211 - #define PCI_CHIP_R580_7240 0x7240 - #define PCI_CHIP_R580_7243 0x7243 - #define PCI_CHIP_R580_7244 0x7244 -@@ -315,6 +316,9 @@ - #define PCI_CHIP_RS350_7835 0x7835 - #define PCI_CHIP_RS690_791E 0x791E - #define PCI_CHIP_RS690_791F 0x791F -+#define PCI_CHIP_RS600_793F 0x793F -+#define PCI_CHIP_RS600_7941 0x7941 -+#define PCI_CHIP_RS600_7942 0x7942 - #define PCI_CHIP_RS740_796C 0x796C - #define PCI_CHIP_RS740_796D 0x796D - #define PCI_CHIP_RS740_796E 0x796E -@@ -327,6 +331,8 @@ - #define PCI_CHIP_R600_940A 0x940A - #define PCI_CHIP_R600_940B 0x940B - #define PCI_CHIP_R600_940F 0x940F -+#define PCI_CHIP_RV770_9440 0x9440 -+#define PCI_CHIP_RV770_9442 0x9442 - #define PCI_CHIP_RV610_94C0 0x94C0 - #define PCI_CHIP_RV610_94C1 0x94C1 - #define PCI_CHIP_RV610_94C3 0x94C3 -@@ -344,6 +350,7 @@ - #define PCI_CHIP_RV670_9507 0x9507 - #define PCI_CHIP_RV670_950F 0x950F - #define PCI_CHIP_RV670_9511 0x9511 -+#define PCI_CHIP_RV670_9515 0x9515 - #define PCI_CHIP_RV630_9580 0x9580 - #define PCI_CHIP_RV630_9581 0x9581 - #define PCI_CHIP_RV630_9583 0x9583 -@@ -356,3 +363,22 @@ - #define PCI_CHIP_RV630_958C 0x958C - #define PCI_CHIP_RV630_958D 0x958D - #define PCI_CHIP_RV630_958E 0x958E -+#define PCI_CHIP_RV620_95C0 0x95C0 -+#define PCI_CHIP_RV620_95C5 0x95C5 -+#define PCI_CHIP_RV620_95C7 0x95C7 -+#define PCI_CHIP_RV620_95C2 0x95C2 -+#define PCI_CHIP_RV620_95C4 0x95C4 -+#define PCI_CHIP_RV620_95CD 0x95CD -+#define PCI_CHIP_RV620_95CE 0x95CE -+#define PCI_CHIP_RV620_95CF 0x95CF -+#define PCI_CHIP_RV635_9590 0x9590 -+#define PCI_CHIP_RV635_9596 0x9596 -+#define PCI_CHIP_RV635_9597 0x9597 -+#define PCI_CHIP_RV635_9598 0x9598 -+#define PCI_CHIP_RV635_9599 0x9599 -+#define PCI_CHIP_RV635_9591 0x9591 -+#define PCI_CHIP_RV635_9593 0x9593 -+#define PCI_CHIP_RS780_9610 0x9610 -+#define PCI_CHIP_RS780_9611 0x9611 -+#define PCI_CHIP_RS780_9612 0x9612 -+#define PCI_CHIP_RS780_9613 0x9613 -diff --git a/src/atimodule.c b/src/atimodule.c -index c249333..f0eb147 100644 ---- a/src/atimodule.c -+++ b/src/atimodule.c -@@ -27,8 +27,6 @@ - #include "ati.h" - #include "ativersion.h" - --extern void ati_gdev_subdriver(pointer options); -- - /* Module loader interface */ - - static XF86ModuleVersionInfo ATIVersionRec = -diff --git a/src/atombios_crtc.c b/src/atombios_crtc.c -index bc2df18..70650e1 100644 ---- a/src/atombios_crtc.c -+++ b/src/atombios_crtc.c -@@ -1,10 +1,5 @@ - /* - * Copyright © 2007 Red Hat, Inc. -- * -- * PLL code is: -- * Copyright 2007 Luc Verhaegen -- * Copyright 2007 Matthias Hopf -- * Copyright 2007 Egbert Eich - * Copyright 2007 Advanced Micro Devices, Inc. - * - * Permission is hereby granted, free of charge, to any person obtaining a -@@ -28,6 +23,7 @@ - * - * Authors: - * Dave Airlie -+ * Alex Deucher - * - */ - /* -@@ -53,6 +49,29 @@ - #endif - - AtomBiosResult -+atombios_lock_crtc(atomBiosHandlePtr atomBIOS, int crtc, int lock) -+{ -+ ENABLE_CRTC_PS_ALLOCATION crtc_data; -+ AtomBiosArgRec data; -+ unsigned char *space; -+ -+ crtc_data.ucCRTC = crtc; -+ crtc_data.ucEnable = lock; -+ -+ data.exec.index = GetIndexIntoMasterTable(COMMAND, UpdateCRTC_DoubleBufferRegisters); -+ data.exec.dataSpace = (void *)&space; -+ data.exec.pspace = &crtc_data; -+ -+ if (RHDAtomBiosFunc(atomBIOS->scrnIndex, atomBIOS, ATOMBIOS_EXEC, &data) == ATOM_SUCCESS) { -+ ErrorF("%s CRTC %d success\n", lock? "Lock":"Unlock", crtc); -+ return ATOM_SUCCESS ; -+ } -+ -+ ErrorF("Lock CRTC failed\n"); -+ return ATOM_NOT_IMPLEMENTED; -+} -+ -+static AtomBiosResult - atombios_enable_crtc(atomBiosHandlePtr atomBIOS, int crtc, int state) - { - ENABLE_CRTC_PS_ALLOCATION crtc_data; -@@ -75,7 +94,30 @@ atombios_enable_crtc(atomBiosHandlePtr atomBIOS, int crtc, int state) - return ATOM_NOT_IMPLEMENTED; - } - --AtomBiosResult -+static AtomBiosResult -+atombios_enable_crtc_memreq(atomBiosHandlePtr atomBIOS, int crtc, int state) -+{ -+ ENABLE_CRTC_PS_ALLOCATION crtc_data; -+ AtomBiosArgRec data; -+ unsigned char *space; -+ -+ crtc_data.ucCRTC = crtc; -+ crtc_data.ucEnable = state; -+ -+ data.exec.index = GetIndexIntoMasterTable(COMMAND, EnableCRTCMemReq); -+ data.exec.dataSpace = (void *)&space; -+ data.exec.pspace = &crtc_data; -+ -+ if (RHDAtomBiosFunc(atomBIOS->scrnIndex, atomBIOS, ATOMBIOS_EXEC, &data) == ATOM_SUCCESS) { -+ ErrorF("%s CRTC memreq %d success\n", state? "Enable":"Disable", crtc); -+ return ATOM_SUCCESS ; -+ } -+ -+ ErrorF("Enable CRTC memreq failed\n"); -+ return ATOM_NOT_IMPLEMENTED; -+} -+ -+static AtomBiosResult - atombios_blank_crtc(atomBiosHandlePtr atomBIOS, int crtc, int state) - { - BLANK_CRTC_PS_ALLOCATION crtc_data; -@@ -86,7 +128,7 @@ atombios_blank_crtc(atomBiosHandlePtr atomBIOS, int crtc, int state) - crtc_data.ucCRTC = crtc; - crtc_data.ucBlanking = state; - -- data.exec.index = offsetof(ATOM_MASTER_LIST_OF_COMMAND_TABLES, BlankCRTC) / sizeof(unsigned short); -+ data.exec.index = GetIndexIntoMasterTable(COMMAND, BlankCRTC); - data.exec.dataSpace = (void *)&space; - data.exec.pspace = &crtc_data; - -@@ -99,19 +141,6 @@ atombios_blank_crtc(atomBiosHandlePtr atomBIOS, int crtc, int state) - return ATOM_NOT_IMPLEMENTED; - } - --#if 0 --static void --atombios_crtc_enable(xf86CrtcPtr crtc, int enable) --{ -- RADEONCrtcPrivatePtr radeon_crtc = crtc->driver_private; -- RADEONInfoPtr info = RADEONPTR(crtc->scrn); -- -- atombios_enable_crtc(info->atomBIOS, radeon_crtc->crtc_id, enable); -- -- //TODOavivo_wait_idle(avivo); --} --#endif -- - void - atombios_crtc_dpms(xf86CrtcPtr crtc, int mode) - { -@@ -121,12 +150,16 @@ atombios_crtc_dpms(xf86CrtcPtr crtc, int mode) - case DPMSModeOn: - case DPMSModeStandby: - case DPMSModeSuspend: -+ if (IS_DCE3_VARIANT) -+ atombios_enable_crtc_memreq(info->atomBIOS, radeon_crtc->crtc_id, 1); - atombios_enable_crtc(info->atomBIOS, radeon_crtc->crtc_id, 1); - atombios_blank_crtc(info->atomBIOS, radeon_crtc->crtc_id, 0); - break; - case DPMSModeOff: - atombios_blank_crtc(info->atomBIOS, radeon_crtc->crtc_id, 1); - atombios_enable_crtc(info->atomBIOS, radeon_crtc->crtc_id, 0); -+ if (IS_DCE3_VARIANT) -+ atombios_enable_crtc_memreq(info->atomBIOS, radeon_crtc->crtc_id, 0); - break; - } - } -@@ -136,10 +169,27 @@ atombios_set_crtc_timing(atomBiosHandlePtr atomBIOS, SET_CRTC_TIMING_PARAMETERS_ - { - AtomBiosArgRec data; - unsigned char *space; -+ SET_CRTC_TIMING_PARAMETERS_PS_ALLOCATION conv_param; -+ -+ conv_param.usH_Total = cpu_to_le16(crtc_param->usH_Total); -+ conv_param.usH_Disp = cpu_to_le16(crtc_param->usH_Disp); -+ conv_param.usH_SyncStart = cpu_to_le16(crtc_param->usH_SyncStart); -+ conv_param.usH_SyncWidth = cpu_to_le16(crtc_param->usH_SyncWidth); -+ conv_param.usV_Total = cpu_to_le16(crtc_param->usV_Total); -+ conv_param.usV_Disp = cpu_to_le16(crtc_param->usV_Disp); -+ conv_param.usV_SyncStart = cpu_to_le16(crtc_param->usV_SyncStart); -+ conv_param.usV_SyncWidth = cpu_to_le16(crtc_param->usV_SyncWidth); -+ conv_param.susModeMiscInfo.usAccess = cpu_to_le16(crtc_param->susModeMiscInfo.usAccess); -+ conv_param.ucCRTC = crtc_param->ucCRTC; -+ conv_param.ucOverscanRight = crtc_param->ucOverscanRight; -+ conv_param.ucOverscanLeft = crtc_param->ucOverscanLeft; -+ conv_param.ucOverscanBottom = crtc_param->ucOverscanBottom; -+ conv_param.ucOverscanTop = crtc_param->ucOverscanTop; -+ conv_param.ucReserved = crtc_param->ucReserved; - - data.exec.index = GetIndexIntoMasterTable(COMMAND, SetCRTC_Timing); - data.exec.dataSpace = (void *)&space; -- data.exec.pspace = crtc_param; -+ data.exec.pspace = &conv_param; - - if (RHDAtomBiosFunc(atomBIOS->scrnIndex, atomBIOS, ATOMBIOS_EXEC, &data) == ATOM_SUCCESS) { - ErrorF("Set CRTC Timing success\n"); -@@ -151,24 +201,33 @@ atombios_set_crtc_timing(atomBiosHandlePtr atomBIOS, SET_CRTC_TIMING_PARAMETERS_ - } - - void --atombios_crtc_set_pll(xf86CrtcPtr crtc, DisplayModePtr mode) -+atombios_crtc_set_pll(xf86CrtcPtr crtc, DisplayModePtr mode, int pll_flags) - { - RADEONCrtcPrivatePtr radeon_crtc = crtc->driver_private; - RADEONInfoPtr info = RADEONPTR(crtc->scrn); -+ xf86CrtcConfigPtr xf86_config = XF86_CRTC_CONFIG_PTR(crtc->scrn); - unsigned char *RADEONMMIO = info->MMIO; - int index = GetIndexIntoMasterTable(COMMAND, SetPixelClock); -- CARD32 sclock = mode->Clock; -- CARD32 ref_div = 0, fb_div = 0, post_div = 0; -- int major, minor; -+ uint32_t sclock = mode->Clock; -+ uint32_t ref_div = 0, fb_div = 0, post_div = 0; -+ int major, minor, i; - SET_PIXEL_CLOCK_PS_ALLOCATION spc_param; -+ PIXEL_CLOCK_PARAMETERS_V2 *spc2_ptr; -+ PIXEL_CLOCK_PARAMETERS_V3 *spc3_ptr; -+ xf86OutputPtr output; -+ RADEONOutputPrivatePtr radeon_output = NULL; -+ - void *ptr; - AtomBiosArgRec data; - unsigned char *space; - RADEONSavePtr save = info->ModeReg; - - if (IS_AVIVO_VARIANT) { -- CARD32 temp; -- RADEONComputePLL(&info->pll, mode->Clock, &temp, &fb_div, &ref_div, &post_div, 0); -+ uint32_t temp; -+ -+ pll_flags |= RADEON_PLL_PREFER_LOW_REF_DIV; -+ -+ RADEONComputePLL(&info->pll, mode->Clock, &temp, &fb_div, &ref_div, &post_div, pll_flags); - sclock = temp; - - /* disable spread spectrum clocking for now -- thanks Hedy Lamarr */ -@@ -193,25 +252,86 @@ atombios_crtc_set_pll(xf86CrtcPtr crtc, DisplayModePtr mode) - "crtc(%d) PLL : refdiv %u, fbdiv 0x%X(%u), pdiv %u\n", - radeon_crtc->crtc_id, (unsigned int)ref_div, (unsigned int)fb_div, (unsigned int)fb_div, (unsigned int)post_div); - -+ /* Can't really do cloning easily on DCE3 cards */ -+ for (i = 0; i < xf86_config->num_output; i++) { -+ output = xf86_config->output[i]; -+ if (output->crtc == crtc) { -+ radeon_output = output->driver_private; -+ break; -+ } -+ } -+ -+ if (radeon_output == NULL) { -+ xf86DrvMsg(crtc->scrn->scrnIndex, X_ERROR, "No output assigned to crtc!\n"); -+ return; -+ } -+ - atombios_get_command_table_version(info->atomBIOS, index, &major, &minor); - -- ErrorF("table is %d %d\n", major, minor); -+ /*ErrorF("table is %d %d\n", major, minor);*/ - switch(major) { - case 1: - switch(minor) { - case 1: -- case 2: { -- spc_param.sPCLKInput.usPixelClock = sclock; -- spc_param.sPCLKInput.usRefDiv = ref_div; -- spc_param.sPCLKInput.usFbDiv = fb_div; -- spc_param.sPCLKInput.ucPostDiv = post_div; -- spc_param.sPCLKInput.ucPpll = radeon_crtc->crtc_id ? ATOM_PPLL2 : ATOM_PPLL1; -- spc_param.sPCLKInput.ucCRTC = radeon_crtc->crtc_id; -- spc_param.sPCLKInput.ucRefDivSrc = 1; -+ case 2: -+ spc2_ptr = (PIXEL_CLOCK_PARAMETERS_V2*)&spc_param.sPCLKInput; -+ spc2_ptr->usPixelClock = cpu_to_le16(sclock); -+ spc2_ptr->usRefDiv = cpu_to_le16(ref_div); -+ spc2_ptr->usFbDiv = cpu_to_le16(fb_div); -+ spc2_ptr->ucPostDiv = post_div; -+ spc2_ptr->ucPpll = radeon_crtc->crtc_id ? ATOM_PPLL2 : ATOM_PPLL1; -+ spc2_ptr->ucCRTC = radeon_crtc->crtc_id; -+ spc2_ptr->ucRefDivSrc = 1; -+ ptr = &spc_param; -+ break; -+ case 3: -+ spc3_ptr = (PIXEL_CLOCK_PARAMETERS_V3*)&spc_param.sPCLKInput; -+ spc3_ptr->usPixelClock = cpu_to_le16(sclock); -+ spc3_ptr->usRefDiv = cpu_to_le16(ref_div); -+ spc3_ptr->usFbDiv = cpu_to_le16(fb_div); -+ spc3_ptr->ucPostDiv = post_div; -+ spc3_ptr->ucPpll = radeon_crtc->crtc_id ? ATOM_PPLL2 : ATOM_PPLL1; -+ spc3_ptr->ucMiscInfo = (radeon_crtc->crtc_id << 2); -+ -+ if (radeon_output->MonType == MT_CRT) { -+ if (radeon_output->DACType == DAC_PRIMARY) -+ spc3_ptr->ucTransmitterId = ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1; -+ else if (radeon_output->DACType == DAC_TVDAC) -+ spc3_ptr->ucTransmitterId = ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2; -+ spc3_ptr->ucEncoderMode = ATOM_ENCODER_MODE_CRT; -+ } else if (radeon_output->MonType == MT_DFP) { -+ if (radeon_output->devices & ATOM_DEVICE_DFP1_SUPPORT) -+ spc3_ptr->ucTransmitterId = ENCODER_OBJECT_ID_INTERNAL_UNIPHY; -+ else if (radeon_output->devices & ATOM_DEVICE_DFP2_SUPPORT) -+ spc3_ptr->ucTransmitterId = ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1; -+ else if (radeon_output->devices & ATOM_DEVICE_DFP3_SUPPORT) -+ spc3_ptr->ucTransmitterId = ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA; -+ if (OUTPUT_IS_DVI) -+ spc3_ptr->ucEncoderMode = ATOM_ENCODER_MODE_DVI; -+ else if (radeon_output->type == OUTPUT_HDMI) -+ spc3_ptr->ucEncoderMode = ATOM_ENCODER_MODE_HDMI; -+ else if (radeon_output->type == OUTPUT_DP) -+ spc3_ptr->ucEncoderMode = ATOM_ENCODER_MODE_DP; -+ } else if (radeon_output->MonType == MT_LCD) { -+ if (radeon_output->devices & ATOM_DEVICE_LCD1_SUPPORT) -+ spc3_ptr->ucTransmitterId = ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA; -+ spc3_ptr->ucEncoderMode = ATOM_ENCODER_MODE_LVDS; -+ } else if (OUTPUT_IS_TV) { -+ if (radeon_output->DACType == DAC_PRIMARY) -+ spc3_ptr->ucTransmitterId = ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1; -+ else if (radeon_output->DACType == DAC_TVDAC) -+ spc3_ptr->ucTransmitterId = ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2; -+ spc3_ptr->ucEncoderMode = ATOM_ENCODER_MODE_TV; -+ } else if (radeon_output->MonType == MT_CV) { -+ if (radeon_output->DACType == DAC_PRIMARY) -+ spc3_ptr->ucTransmitterId = ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1; -+ else if (radeon_output->DACType == DAC_TVDAC) -+ spc3_ptr->ucTransmitterId = ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2; -+ spc3_ptr->ucEncoderMode = ATOM_ENCODER_MODE_CV; -+ } - - ptr = &spc_param; - break; -- } - default: - ErrorF("Unknown table version\n"); - exit(-1); -@@ -247,26 +367,16 @@ atombios_crtc_mode_set(xf86CrtcPtr crtc, - xf86CrtcConfigPtr xf86_config = XF86_CRTC_CONFIG_PTR(pScrn); - unsigned char *RADEONMMIO = info->MMIO; - unsigned long fb_location = crtc->scrn->fbOffset + info->fbLocation; -- Bool tilingOld = info->tilingEnabled; - int need_tv_timings = 0; - int i, ret; - SET_CRTC_TIMING_PARAMETERS_PS_ALLOCATION crtc_timing; -- -+ Bool tilingChanged = FALSE; -+ int pll_flags = 0; - memset(&crtc_timing, 0, sizeof(crtc_timing)); - - if (info->allowColorTiling) { -- info->tilingEnabled = (adjusted_mode->Flags & (V_DBLSCAN | V_INTERLACE)) ? FALSE : TRUE; --#ifdef XF86DRI -- if (info->directRenderingEnabled && (info->tilingEnabled != tilingOld)) { -- RADEONSAREAPrivPtr pSAREAPriv; -- if (RADEONDRISetParam(pScrn, RADEON_SETPARAM_SWITCH_TILING, (info->tilingEnabled ? 1 : 0)) < 0) -- xf86DrvMsg(pScrn->scrnIndex, X_ERROR, -- "[drm] failed changing tiling status\n"); -- /* if this is called during ScreenInit() we don't have pScrn->pScreen yet */ -- pSAREAPriv = DRIGetSAREAPrivate(screenInfo.screens[pScrn->scrnIndex]); -- info->tilingEnabled = pSAREAPriv->tiling_enabled ? TRUE : FALSE; -- } --#endif -+ radeon_crtc->can_tile = (adjusted_mode->Flags & (V_DBLSCAN | V_INTERLACE)) ? FALSE : TRUE; -+ tilingChanged = RADEONSetTiling(pScrn); - } - - for (i = 0; i < xf86_config->num_output; i++) { -@@ -283,6 +393,9 @@ atombios_crtc_mode_set(xf86CrtcPtr crtc, - need_tv_timings = 2; - - } -+ -+ if (radeon_output->MonType == MT_LCD) -+ pll_flags |= RADEON_PLL_USE_REF_DIV; - } - } - -@@ -334,27 +447,25 @@ atombios_crtc_mode_set(xf86CrtcPtr crtc, - RADEONRestoreMemMapRegisters(pScrn, info->ModeReg); - - if (IS_AVIVO_VARIANT) { -- radeon_crtc->fb_width = mode->CrtcHDisplay; -- radeon_crtc->fb_height = pScrn->virtualY; -- radeon_crtc->fb_pitch = mode->CrtcHDisplay; -- radeon_crtc->fb_length = radeon_crtc->fb_pitch * radeon_crtc->fb_height * 4; -+ uint32_t fb_format; -+ - switch (crtc->scrn->bitsPerPixel) { - case 15: -- radeon_crtc->fb_format = AVIVO_D1GRPH_CONTROL_DEPTH_16BPP | AVIVO_D1GRPH_CONTROL_16BPP_ARGB1555; -+ fb_format = AVIVO_D1GRPH_CONTROL_DEPTH_16BPP | AVIVO_D1GRPH_CONTROL_16BPP_ARGB1555; - break; - case 16: -- radeon_crtc->fb_format = AVIVO_D1GRPH_CONTROL_DEPTH_16BPP | AVIVO_D1GRPH_CONTROL_16BPP_RGB565; -+ fb_format = AVIVO_D1GRPH_CONTROL_DEPTH_16BPP | AVIVO_D1GRPH_CONTROL_16BPP_RGB565; - break; - case 24: - case 32: -- radeon_crtc->fb_format = AVIVO_D1GRPH_CONTROL_DEPTH_32BPP | AVIVO_D1GRPH_CONTROL_32BPP_ARGB8888; -+ fb_format = AVIVO_D1GRPH_CONTROL_DEPTH_32BPP | AVIVO_D1GRPH_CONTROL_32BPP_ARGB8888; - break; - default: - FatalError("Unsupported screen depth: %d\n", xf86GetDepth()); - } - - if (info->tilingEnabled && (crtc->rotatedData == NULL)) { -- radeon_crtc->fb_format |= AVIVO_D1GRPH_MACRO_ADDRESS_MODE; -+ fb_format |= AVIVO_D1GRPH_MACRO_ADDRESS_MODE; - } - - if (radeon_crtc->crtc_id == 0) -@@ -371,47 +482,42 @@ atombios_crtc_mode_set(xf86CrtcPtr crtc, - fb_location = fb_location + (char *)crtc->rotatedData - (char *)info->FB; - } - -- /* lock the grph regs */ -- OUTREG(AVIVO_D1GRPH_UPDATE + radeon_crtc->crtc_offset, AVIVO_D1GRPH_UPDATE_LOCK); -- - OUTREG(AVIVO_D1GRPH_PRIMARY_SURFACE_ADDRESS + radeon_crtc->crtc_offset, fb_location); - OUTREG(AVIVO_D1GRPH_SECONDARY_SURFACE_ADDRESS + radeon_crtc->crtc_offset, fb_location); -- OUTREG(AVIVO_D1GRPH_CONTROL + radeon_crtc->crtc_offset, -- radeon_crtc->fb_format); -+ OUTREG(AVIVO_D1GRPH_CONTROL + radeon_crtc->crtc_offset, fb_format); - - OUTREG(AVIVO_D1GRPH_SURFACE_OFFSET_X + radeon_crtc->crtc_offset, 0); - OUTREG(AVIVO_D1GRPH_SURFACE_OFFSET_Y + radeon_crtc->crtc_offset, 0); -- OUTREG(AVIVO_D1GRPH_X_START + radeon_crtc->crtc_offset, 0); -- OUTREG(AVIVO_D1GRPH_Y_START + radeon_crtc->crtc_offset, 0); -- OUTREG(AVIVO_D1GRPH_X_END + radeon_crtc->crtc_offset, -- crtc->scrn->virtualX); -- OUTREG(AVIVO_D1GRPH_Y_END + radeon_crtc->crtc_offset, -- crtc->scrn->virtualY); -+ OUTREG(AVIVO_D1GRPH_X_START + radeon_crtc->crtc_offset, x); -+ OUTREG(AVIVO_D1GRPH_Y_START + radeon_crtc->crtc_offset, y); -+ OUTREG(AVIVO_D1GRPH_X_END + radeon_crtc->crtc_offset, x + mode->HDisplay); -+ OUTREG(AVIVO_D1GRPH_Y_END + radeon_crtc->crtc_offset, y + mode->VDisplay); - OUTREG(AVIVO_D1GRPH_PITCH + radeon_crtc->crtc_offset, - crtc->scrn->displayWidth); - OUTREG(AVIVO_D1GRPH_ENABLE + radeon_crtc->crtc_offset, 1); - -- /* unlock the grph regs */ -- OUTREG(AVIVO_D1GRPH_UPDATE + radeon_crtc->crtc_offset, 0); -- -- /* lock the mode regs */ -- OUTREG(AVIVO_D1SCL_UPDATE + radeon_crtc->crtc_offset, AVIVO_D1SCL_UPDATE_LOCK); -- - OUTREG(AVIVO_D1MODE_DESKTOP_HEIGHT + radeon_crtc->crtc_offset, -- crtc->scrn->virtualY); -+ mode->VDisplay); - OUTREG(AVIVO_D1MODE_VIEWPORT_START + radeon_crtc->crtc_offset, (x << 16) | y); - OUTREG(AVIVO_D1MODE_VIEWPORT_SIZE + radeon_crtc->crtc_offset, - (mode->HDisplay << 16) | mode->VDisplay); -- /* unlock the mode regs */ -- OUTREG(AVIVO_D1SCL_UPDATE + radeon_crtc->crtc_offset, 0); - -+ if (adjusted_mode->Flags & V_INTERLACE) -+ OUTREG(AVIVO_D1MODE_DATA_FORMAT + radeon_crtc->crtc_offset, -+ AVIVO_D1MODE_INTERLEAVE_EN); -+ else -+ OUTREG(AVIVO_D1MODE_DATA_FORMAT + radeon_crtc->crtc_offset, -+ 0); - } - -- atombios_crtc_set_pll(crtc, adjusted_mode); -+ atombios_crtc_set_pll(crtc, adjusted_mode, pll_flags); - - atombios_set_crtc_timing(info->atomBIOS, &crtc_timing); - -- if (info->tilingEnabled != tilingOld) { -+ if (info->DispPriority) -+ RADEONInitDispBandwidth(pScrn); -+ -+ if (tilingChanged) { - /* need to redraw front buffer, I guess this can be considered a hack ? */ - /* if this is called during ScreenInit() we don't have pScrn->pScreen yet */ - if (pScrn->pScreen) -@@ -424,3 +530,126 @@ atombios_crtc_mode_set(xf86CrtcPtr crtc, - - } - -+/* Calculate display buffer watermark to prevent buffer underflow */ -+void -+RADEONInitDispBandwidthAVIVO(ScrnInfoPtr pScrn, -+ DisplayModePtr mode1, int pixel_bytes1, -+ DisplayModePtr mode2, int pixel_bytes2) -+{ -+ RADEONInfoPtr info = RADEONPTR(pScrn); -+ RADEONEntPtr pRADEONEnt = RADEONEntPriv(pScrn); -+ unsigned char *RADEONMMIO = info->MMIO; -+ -+ uint32_t dc_lb_memory_split; -+ float mem_bw, peak_disp_bw; -+ float min_mem_eff = 0.8; /* XXX: taken from legacy method */ -+ float pix_clk, pix_clk2; /* in MHz */ -+ -+ /* -+ * Set display0/1 priority up in the memory controller for -+ * modes if the user specifies HIGH for displaypriority -+ * option. -+ */ -+ if (info->DispPriority == 2) { -+ uint32_t mc_init_misc_lat_timer = 0; -+ if (info->ChipFamily == CHIP_FAMILY_RV515) -+ mc_init_misc_lat_timer = INMC(pScrn, RV515_MC_INIT_MISC_LAT_TIMER); -+ else if (info->ChipFamily == CHIP_FAMILY_RS690) -+ mc_init_misc_lat_timer = INMC(pScrn, RS690_MC_INIT_MISC_LAT_TIMER); -+ -+ mc_init_misc_lat_timer &= ~(R300_MC_DISP1R_INIT_LAT_MASK << R300_MC_DISP1R_INIT_LAT_SHIFT); -+ mc_init_misc_lat_timer &= ~(R300_MC_DISP0R_INIT_LAT_MASK << R300_MC_DISP0R_INIT_LAT_SHIFT); -+ -+ if (pRADEONEnt->pCrtc[1]->enabled) -+ mc_init_misc_lat_timer |= (1 << R300_MC_DISP1R_INIT_LAT_SHIFT); /* display 1 */ -+ if (pRADEONEnt->pCrtc[0]->enabled) -+ mc_init_misc_lat_timer |= (1 << R300_MC_DISP0R_INIT_LAT_SHIFT); /* display 0 */ -+ -+ if (info->ChipFamily == CHIP_FAMILY_RV515) -+ OUTMC(pScrn, RV515_MC_INIT_MISC_LAT_TIMER, mc_init_misc_lat_timer); -+ else if (info->ChipFamily == CHIP_FAMILY_RS690) -+ OUTMC(pScrn, RS690_MC_INIT_MISC_LAT_TIMER, mc_init_misc_lat_timer); -+ } -+ -+ /* XXX: fix me for AVIVO -+ * Determine if there is enough bandwidth for current display mode -+ */ -+ mem_bw = info->mclk * (info->RamWidth / 8) * (info->IsDDR ? 2 : 1); -+ -+ pix_clk = 0; -+ pix_clk2 = 0; -+ peak_disp_bw = 0; -+ if (mode1) { -+ pix_clk = mode1->Clock/1000.0; -+ peak_disp_bw += (pix_clk * pixel_bytes1); -+ } -+ if (mode2) { -+ pix_clk2 = mode2->Clock/1000.0; -+ peak_disp_bw += (pix_clk2 * pixel_bytes2); -+ } -+ -+ if (peak_disp_bw >= mem_bw * min_mem_eff) { -+ xf86DrvMsg(pScrn->scrnIndex, X_WARNING, -+ "You may not have enough display bandwidth for current mode\n" -+ "If you have flickering problem, try to lower resolution, refresh rate, or color depth\n"); -+ } -+ -+ /* -+ * Line Buffer Setup -+ * There is a single line buffer shared by both display controllers. -+ * DC_LB_MEMORY_SPLIT controls how that line buffer is shared between the display -+ * controllers. The paritioning can either be done manually or via one of four -+ * preset allocations specified in bits 1:0: -+ * 0 - line buffer is divided in half and shared between each display controller -+ * 1 - D1 gets 3/4 of the line buffer, D2 gets 1/4 -+ * 2 - D1 gets the whole buffer -+ * 3 - D1 gets 1/4 of the line buffer, D2 gets 3/4 -+ * Setting bit 2 of DC_LB_MEMORY_SPLIT controls switches to manual allocation mode. -+ * In manual allocation mode, D1 always starts at 0, D1 end/2 is specified in bits -+ * 14:4; D2 allocation follows D1. -+ */ -+ -+ /* is auto or manual better ? */ -+ dc_lb_memory_split = INREG(AVIVO_DC_LB_MEMORY_SPLIT) & ~AVIVO_DC_LB_MEMORY_SPLIT_MASK; -+ dc_lb_memory_split &= ~AVIVO_DC_LB_MEMORY_SPLIT_SHIFT_MODE; -+#if 1 -+ /* auto */ -+ if (mode1 && mode2) { -+ if (mode1->HDisplay > mode2->HDisplay) { -+ if (mode1->HDisplay > 2560) -+ dc_lb_memory_split |= AVIVO_DC_LB_MEMORY_SPLIT_D1_3Q_D2_1Q; -+ else -+ dc_lb_memory_split |= AVIVO_DC_LB_MEMORY_SPLIT_D1HALF_D2HALF; -+ } else if (mode2->HDisplay > mode1->HDisplay) { -+ if (mode2->HDisplay > 2560) -+ dc_lb_memory_split |= AVIVO_DC_LB_MEMORY_SPLIT_D1_1Q_D2_3Q; -+ else -+ dc_lb_memory_split |= AVIVO_DC_LB_MEMORY_SPLIT_D1HALF_D2HALF; -+ } else -+ dc_lb_memory_split |= AVIVO_DC_LB_MEMORY_SPLIT_D1HALF_D2HALF; -+ } else if (mode1) { -+ dc_lb_memory_split |= AVIVO_DC_LB_MEMORY_SPLIT_D1_ONLY; -+ } else if (mode2) { -+ dc_lb_memory_split |= AVIVO_DC_LB_MEMORY_SPLIT_D1_1Q_D2_3Q; -+ } -+#else -+ /* manual */ -+ dc_lb_memory_split |= AVIVO_DC_LB_MEMORY_SPLIT_SHIFT_MODE; -+ dc_lb_memory_split &= ~(AVIVO_DC_LB_DISP1_END_ADR_MASK << AVIVO_DC_LB_DISP1_END_ADR_SHIFT); -+ if (mode1) { -+ dc_lb_memory_split |= ((((mode1->HDisplay / 2) + 64 /*???*/) & AVIVO_DC_LB_DISP1_END_ADR_MASK) -+ << AVIVO_DC_LB_DISP1_END_ADR_SHIFT); -+ } else if (mode2) { -+ dc_lb_memory_split |= (0 << AVIVO_DC_LB_DISP1_END_ADR_SHIFT); -+ } -+ OUTREG(AVIVO_DC_LB_MEMORY_SPLIT, dc_lb_memory_split); -+#endif -+ -+ /* -+ * Watermark setup -+ * TODO... -+ * Unforunately, I haven't been able to dig up the avivo watermark programming -+ * guide yet. -AGD -+ */ -+ -+} -diff --git a/src/atombios_output.c b/src/atombios_output.c -index 07d212f..83b86a7 100644 ---- a/src/atombios_output.c -+++ b/src/atombios_output.c -@@ -78,7 +78,7 @@ atombios_output_dac1_setup(xf86OutputPtr output, DisplayModePtr mode) - } - } - -- disp_data.usPixelClock = mode->Clock / 10; -+ disp_data.usPixelClock = cpu_to_le16(mode->Clock / 10); - data.exec.index = GetIndexIntoMasterTable(COMMAND, DAC1EncoderControl); - data.exec.dataSpace = (void *)&space; - data.exec.pspace = &disp_data; -@@ -128,7 +128,7 @@ atombios_output_dac2_setup(xf86OutputPtr output, DisplayModePtr mode) - } - } - -- disp_data.usPixelClock = mode->Clock / 10; -+ disp_data.usPixelClock = cpu_to_le16(mode->Clock / 10); - data.exec.index = GetIndexIntoMasterTable(COMMAND, DAC2EncoderControl); - data.exec.dataSpace = (void *)&space; - data.exec.pspace = &disp_data; -@@ -188,7 +188,7 @@ atombios_output_tv1_setup(xf86OutputPtr output, DisplayModePtr mode) - } - } - -- disp_data.sTVEncoder.usPixelClock = mode->Clock / 10; -+ disp_data.sTVEncoder.usPixelClock = cpu_to_le16(mode->Clock / 10); - data.exec.index = GetIndexIntoMasterTable(COMMAND, TVEncoderControl); - data.exec.dataSpace = (void *)&space; - data.exec.pspace = &disp_data; -@@ -235,7 +235,7 @@ atombios_external_tmds_setup(xf86OutputPtr output, DisplayModePtr mode) - } - - static int --atombios_ddia_setup(xf86OutputPtr output, DisplayModePtr mode) -+atombios_output_ddia_setup(xf86OutputPtr output, DisplayModePtr mode) - { - RADEONInfoPtr info = RADEONPTR(output->scrn); - DVO_ENCODER_CONTROL_PS_ALLOCATION disp_data; -@@ -243,7 +243,7 @@ atombios_ddia_setup(xf86OutputPtr output, DisplayModePtr mode) - unsigned char *space; - - disp_data.sDVOEncoder.ucAction = ATOM_ENABLE; -- disp_data.sDVOEncoder.usPixelClock = mode->Clock / 10; -+ disp_data.sDVOEncoder.usPixelClock = cpu_to_le16(mode->Clock / 10); - - if (mode->Clock > 165000) - disp_data.sDVOEncoder.usDevAttr.sDigAttrib.ucAttribute = PANEL_ENCODER_MISC_DUAL; -@@ -276,7 +276,7 @@ atombios_output_tmds1_setup(xf86OutputPtr output, DisplayModePtr mode) - disp_data.ucMisc = 1; - else - disp_data.ucMisc = 0; -- disp_data.usPixelClock = mode->Clock / 10; -+ disp_data.usPixelClock = cpu_to_le16(mode->Clock / 10); - data.exec.index = GetIndexIntoMasterTable(COMMAND, TMDS1EncoderControl); - data.exec.dataSpace = (void *)&space; - data.exec.pspace = &disp_data; -@@ -304,7 +304,7 @@ atombios_output_tmds2_setup(xf86OutputPtr output, DisplayModePtr mode) - disp_data.ucMisc = 1; - else - disp_data.ucMisc = 0; -- disp_data.usPixelClock = mode->Clock / 10; -+ disp_data.usPixelClock = cpu_to_le16(mode->Clock / 10); - data.exec.index = GetIndexIntoMasterTable(COMMAND, TMDS2EncoderControl); - data.exec.dataSpace = (void *)&space; - data.exec.pspace = &disp_data; -@@ -331,7 +331,7 @@ atombios_output_lvds_setup(xf86OutputPtr output, DisplayModePtr mode) - disp_data.ucMisc = 1; - else - disp_data.ucMisc = 0; -- disp_data.usPixelClock = mode->Clock / 10; -+ disp_data.usPixelClock = cpu_to_le16(mode->Clock / 10); - data.exec.index = GetIndexIntoMasterTable(COMMAND, LVDSEncoderControl); - data.exec.dataSpace = (void *)&space; - data.exec.pspace = &disp_data; -@@ -346,6 +346,224 @@ atombios_output_lvds_setup(xf86OutputPtr output, DisplayModePtr mode) - } - - static int -+atombios_output_dig1_setup(xf86OutputPtr output, DisplayModePtr mode) -+{ -+ RADEONOutputPrivatePtr radeon_output = output->driver_private; -+ RADEONInfoPtr info = RADEONPTR(output->scrn); -+ DIG_ENCODER_CONTROL_PS_ALLOCATION disp_data; -+ AtomBiosArgRec data; -+ unsigned char *space; -+ -+ disp_data.ucAction = 1; -+ disp_data.usPixelClock = cpu_to_le16(mode->Clock / 10); -+ disp_data.ucConfig = ATOM_ENCODER_CONFIG_TRANSMITTER1; -+ if (OUTPUT_IS_DVI || (radeon_output->type == OUTPUT_HDMI)) { -+ if (radeon_output->coherent_mode) { -+ disp_data.ucConfig |= ATOM_TRANSMITTER_CONFIG_COHERENT; -+ xf86DrvMsg(output->scrn->scrnIndex, X_INFO, "DIG1: Coherent Mode enabled\n"); -+ } else -+ xf86DrvMsg(output->scrn->scrnIndex, X_INFO, "DIG1: Coherent Mode disabled\n"); -+ } -+ -+ if (mode->Clock > 165000) { -+ disp_data.ucConfig |= ATOM_ENCODER_CONFIG_LINKA_B; -+ disp_data.ucLaneNum = 8; -+ } else { -+ disp_data.ucConfig |= ATOM_ENCODER_CONFIG_LINKA; -+ disp_data.ucLaneNum = 4; -+ } -+ -+ if (OUTPUT_IS_DVI) -+ disp_data.ucEncoderMode = ATOM_ENCODER_MODE_DVI; -+ else if (radeon_output->type == OUTPUT_HDMI) -+ disp_data.ucEncoderMode = ATOM_ENCODER_MODE_HDMI; -+ else if (radeon_output->type == OUTPUT_DP) -+ disp_data.ucEncoderMode = ATOM_ENCODER_MODE_DP; -+ else if (radeon_output->type == OUTPUT_LVDS) -+ disp_data.ucEncoderMode = ATOM_ENCODER_MODE_LVDS; -+ -+ data.exec.index = GetIndexIntoMasterTable(COMMAND, DIG1EncoderControl); -+ data.exec.dataSpace = (void *)&space; -+ data.exec.pspace = &disp_data; -+ -+ if (RHDAtomBiosFunc(info->atomBIOS->scrnIndex, info->atomBIOS, ATOMBIOS_EXEC, &data) == ATOM_SUCCESS) { -+ ErrorF("Output DIG1 setup success\n"); -+ return ATOM_SUCCESS; -+ } -+ -+ ErrorF("Output DIG1 setup failed\n"); -+ return ATOM_NOT_IMPLEMENTED; -+ -+} -+ -+static int -+atombios_output_dig1_transmitter_setup(xf86OutputPtr output, DisplayModePtr mode) -+{ -+ RADEONOutputPrivatePtr radeon_output = output->driver_private; -+ RADEONInfoPtr info = RADEONPTR(output->scrn); -+ DIG_TRANSMITTER_CONTROL_PS_ALLOCATION disp_data; -+ AtomBiosArgRec data; -+ unsigned char *space; -+ -+ disp_data.ucAction = ATOM_TRANSMITTER_ACTION_ENABLE; -+ disp_data.usPixelClock = cpu_to_le16(mode->Clock / 10); -+ disp_data.ucConfig = ATOM_TRANSMITTER_CONFIG_DIG1_ENCODER | ATOM_TRANSMITTER_CONFIG_CLKSRC_PPLL; -+ -+ if (info->IsIGP && (radeon_output->TMDSType == TMDS_UNIPHY)) { -+ if (mode->Clock > 165000) { -+ disp_data.ucConfig |= (ATOM_TRANSMITTER_CONFIG_8LANE_LINK | -+ ATOM_TRANSMITTER_CONFIG_LINKA_B); -+ /* guess */ -+ if (radeon_output->igp_lane_info & 0x3) -+ disp_data.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_0_7; -+ else if (radeon_output->igp_lane_info & 0xc) -+ disp_data.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_8_15; -+ } else { -+ disp_data.ucConfig |= ATOM_TRANSMITTER_CONFIG_LINKA; -+ if (radeon_output->igp_lane_info & 0x1) -+ disp_data.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_0_3; -+ else if (radeon_output->igp_lane_info & 0x2) -+ disp_data.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_4_7; -+ else if (radeon_output->igp_lane_info & 0x4) -+ disp_data.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_8_11; -+ else if (radeon_output->igp_lane_info & 0x8) -+ disp_data.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_12_15; -+ } -+ } else { -+ if (mode->Clock > 165000) -+ disp_data.ucConfig |= (ATOM_TRANSMITTER_CONFIG_8LANE_LINK | -+ ATOM_TRANSMITTER_CONFIG_LINKA_B | -+ ATOM_TRANSMITTER_CONFIG_LANE_0_7); -+ else -+ disp_data.ucConfig |= ATOM_TRANSMITTER_CONFIG_LINKA | ATOM_TRANSMITTER_CONFIG_LANE_0_3; -+ } -+ -+ radeon_output->transmitter_config = disp_data.ucConfig; -+ -+ data.exec.index = GetIndexIntoMasterTable(COMMAND, DIG1TransmitterControl); -+ data.exec.dataSpace = (void *)&space; -+ data.exec.pspace = &disp_data; -+ -+ if (RHDAtomBiosFunc(info->atomBIOS->scrnIndex, info->atomBIOS, ATOMBIOS_EXEC, &data) == ATOM_SUCCESS) { -+ ErrorF("Output DIG1 transmitter setup success\n"); -+ return ATOM_SUCCESS; -+ } -+ -+ ErrorF("Output DIG1 transmitter setup failed\n"); -+ return ATOM_NOT_IMPLEMENTED; -+ -+} -+ -+static int -+atombios_output_dig2_setup(xf86OutputPtr output, DisplayModePtr mode) -+{ -+ RADEONOutputPrivatePtr radeon_output = output->driver_private; -+ RADEONInfoPtr info = RADEONPTR(output->scrn); -+ DIG_ENCODER_CONTROL_PS_ALLOCATION disp_data; -+ AtomBiosArgRec data; -+ unsigned char *space; -+ -+ disp_data.ucAction = 1; -+ disp_data.usPixelClock = cpu_to_le16(mode->Clock / 10); -+ disp_data.ucConfig = ATOM_ENCODER_CONFIG_TRANSMITTER2; -+ if (OUTPUT_IS_DVI || (radeon_output->type == OUTPUT_HDMI)) { -+ if (radeon_output->coherent_mode) { -+ disp_data.ucConfig |= ATOM_TRANSMITTER_CONFIG_COHERENT; -+ xf86DrvMsg(output->scrn->scrnIndex, X_INFO, "DIG2: Coherent Mode enabled\n"); -+ } else -+ xf86DrvMsg(output->scrn->scrnIndex, X_INFO, "DIG2: Coherent Mode disabled\n"); -+ } -+ -+ if (mode->Clock > 165000) { -+ disp_data.ucConfig |= ATOM_ENCODER_CONFIG_LINKA_B; -+ disp_data.ucLaneNum = 8; -+ } else { -+ disp_data.ucConfig |= ATOM_ENCODER_CONFIG_LINKA; -+ disp_data.ucLaneNum = 4; -+ } -+ -+ if (OUTPUT_IS_DVI) -+ disp_data.ucEncoderMode = ATOM_ENCODER_MODE_DVI; -+ else if (radeon_output->type == OUTPUT_HDMI) -+ disp_data.ucEncoderMode = ATOM_ENCODER_MODE_HDMI; -+ else if (radeon_output->type == OUTPUT_DP) -+ disp_data.ucEncoderMode = ATOM_ENCODER_MODE_DP; -+ else if (radeon_output->type == OUTPUT_LVDS) -+ disp_data.ucEncoderMode = ATOM_ENCODER_MODE_LVDS; -+ -+ data.exec.index = GetIndexIntoMasterTable(COMMAND, DIG2EncoderControl); -+ data.exec.dataSpace = (void *)&space; -+ data.exec.pspace = &disp_data; -+ -+ if (RHDAtomBiosFunc(info->atomBIOS->scrnIndex, info->atomBIOS, ATOMBIOS_EXEC, &data) == ATOM_SUCCESS) { -+ ErrorF("Output DIG2 setup success\n"); -+ return ATOM_SUCCESS; -+ } -+ -+ ErrorF("Output DIG2 setup failed\n"); -+ return ATOM_NOT_IMPLEMENTED; -+ -+} -+ -+static int -+atombios_output_dig2_transmitter_setup(xf86OutputPtr output, DisplayModePtr mode) -+{ -+ RADEONOutputPrivatePtr radeon_output = output->driver_private; -+ RADEONInfoPtr info = RADEONPTR(output->scrn); -+ DIG_TRANSMITTER_CONTROL_PS_ALLOCATION disp_data; -+ AtomBiosArgRec data; -+ unsigned char *space; -+ -+ disp_data.ucAction = ATOM_TRANSMITTER_ACTION_ENABLE; -+ disp_data.usPixelClock = cpu_to_le16(mode->Clock / 10); -+ disp_data.ucConfig = ATOM_TRANSMITTER_CONFIG_DIG2_ENCODER | ATOM_TRANSMITTER_CONFIG_CLKSRC_PPLL; -+ -+ if (info->IsIGP && (radeon_output->TMDSType == TMDS_UNIPHY)) { -+ if (mode->Clock > 165000) { -+ disp_data.ucConfig |= (ATOM_TRANSMITTER_CONFIG_8LANE_LINK | -+ ATOM_TRANSMITTER_CONFIG_LINKA_B); -+ /* guess */ -+ if (radeon_output->igp_lane_info & 0x3) -+ disp_data.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_0_7; -+ else if (radeon_output->igp_lane_info & 0xc) -+ disp_data.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_8_15; -+ } else { -+ disp_data.ucConfig |= ATOM_TRANSMITTER_CONFIG_LINKA; -+ if (radeon_output->igp_lane_info & 0x1) -+ disp_data.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_0_3; -+ else if (radeon_output->igp_lane_info & 0x2) -+ disp_data.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_4_7; -+ else if (radeon_output->igp_lane_info & 0x4) -+ disp_data.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_8_11; -+ else if (radeon_output->igp_lane_info & 0x8) -+ disp_data.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_12_15; -+ } -+ } else { -+ if (mode->Clock > 165000) -+ disp_data.ucConfig |= (ATOM_TRANSMITTER_CONFIG_8LANE_LINK | -+ ATOM_TRANSMITTER_CONFIG_LINKA_B | -+ ATOM_TRANSMITTER_CONFIG_LANE_0_7); -+ else -+ disp_data.ucConfig |= ATOM_TRANSMITTER_CONFIG_LINKA | ATOM_TRANSMITTER_CONFIG_LANE_0_3; -+ } -+ -+ radeon_output->transmitter_config = disp_data.ucConfig; -+ -+ data.exec.index = GetIndexIntoMasterTable(COMMAND, DIG2TransmitterControl); -+ data.exec.dataSpace = (void *)&space; -+ data.exec.pspace = &disp_data; -+ -+ if (RHDAtomBiosFunc(info->atomBIOS->scrnIndex, info->atomBIOS, ATOMBIOS_EXEC, &data) == ATOM_SUCCESS) { -+ ErrorF("Output DIG2 transmitter setup success\n"); -+ return ATOM_SUCCESS; -+ } -+ -+ ErrorF("Output DIG2 transmitter setup failed\n"); -+ return ATOM_NOT_IMPLEMENTED; -+ -+} -+ -+static int - atombios_output_scaler_setup(xf86OutputPtr output, DisplayModePtr mode) - { - RADEONInfoPtr info = RADEONPTR(output->scrn); -@@ -382,6 +600,34 @@ atombios_output_scaler_setup(xf86OutputPtr output, DisplayModePtr mode) - - } - -+static void -+dfp_disable_dither(xf86OutputPtr output, int device) -+{ -+ RADEONInfoPtr info = RADEONPTR(output->scrn); -+ unsigned char *RADEONMMIO = info->MMIO; -+ -+ switch (device) { -+ case ATOM_DEVICE_DFP1_SUPPORT: -+ OUTREG(AVIVO_TMDSA_BIT_DEPTH_CONTROL, 0); /* TMDSA */ -+ break; -+ case ATOM_DEVICE_DFP2_SUPPORT: -+ if ((info->ChipFamily == CHIP_FAMILY_RS600) || -+ (info->ChipFamily == CHIP_FAMILY_RS690) || -+ (info->ChipFamily == CHIP_FAMILY_RS740)) -+ OUTREG(AVIVO_DDIA_BIT_DEPTH_CONTROL, 0); /* DDIA */ -+ else -+ OUTREG(AVIVO_DVOA_BIT_DEPTH_CONTROL, 0); /* DVO */ -+ break; -+ /*case ATOM_DEVICE_LCD1_SUPPORT:*/ /* LVDS panels need dither enabled */ -+ case ATOM_DEVICE_DFP3_SUPPORT: -+ OUTREG(AVIVO_LVTMA_BIT_DEPTH_CONTROL, 0); /* LVTMA */ -+ break; -+ default: -+ break; -+ } -+ -+} -+ - static AtomBiosResult - atombios_display_device_control(atomBiosHandlePtr atomBIOS, int device, Bool state) - { -@@ -452,40 +698,94 @@ atombios_device_dpms(xf86OutputPtr output, int device, int mode) - } - } - -+static int -+atombios_output_dig_dpms(xf86OutputPtr output, int mode, int block) -+{ -+ RADEONOutputPrivatePtr radeon_output = output->driver_private; -+ RADEONInfoPtr info = RADEONPTR(output->scrn); -+ DIG_TRANSMITTER_CONTROL_PS_ALLOCATION disp_data; -+ AtomBiosArgRec data; -+ unsigned char *space; -+ -+ switch (mode) { -+ case DPMSModeOn: -+ disp_data.ucAction = ATOM_TRANSMITTER_ACTION_ENABLE_OUTPUT; -+ break; -+ case DPMSModeStandby: -+ case DPMSModeSuspend: -+ case DPMSModeOff: -+ disp_data.ucAction = ATOM_TRANSMITTER_ACTION_DISABLE_OUTPUT; -+ break; -+ } -+ -+ disp_data.ucConfig = radeon_output->transmitter_config; -+ -+ if (block == 1) -+ data.exec.index = GetIndexIntoMasterTable(COMMAND, DIG1TransmitterControl); -+ else -+ data.exec.index = GetIndexIntoMasterTable(COMMAND, DIG2TransmitterControl); -+ data.exec.dataSpace = (void *)&space; -+ data.exec.pspace = &disp_data; -+ -+ if (RHDAtomBiosFunc(info->atomBIOS->scrnIndex, info->atomBIOS, ATOMBIOS_EXEC, &data) == ATOM_SUCCESS) { -+ ErrorF("Output DIG%d dpms success\n", block); -+ return ATOM_SUCCESS; -+ } -+ -+ ErrorF("Output DIG%d dpms failed\n", block); -+ return ATOM_NOT_IMPLEMENTED; -+ -+} -+ - void - atombios_output_dpms(xf86OutputPtr output, int mode) - { - RADEONOutputPrivatePtr radeon_output = output->driver_private; -+ RADEONInfoPtr info = RADEONPTR(output->scrn); - -- ErrorF("AGD: output dpms %d\n", mode); -- -- if (radeon_output->MonType == MT_LCD) { -- if (radeon_output->devices & ATOM_DEVICE_LCD1_SUPPORT) -- atombios_device_dpms(output, ATOM_DEVICE_LCD1_SUPPORT, mode); -- } else if (radeon_output->MonType == MT_DFP) { -- ErrorF("AGD: tmds dpms\n"); -- if (radeon_output->devices & ATOM_DEVICE_DFP1_SUPPORT) -- atombios_device_dpms(output, ATOM_DEVICE_DFP1_SUPPORT, mode); -- else if (radeon_output->devices & ATOM_DEVICE_DFP2_SUPPORT) -- atombios_device_dpms(output, ATOM_DEVICE_DFP2_SUPPORT, mode); -- else if (radeon_output->devices & ATOM_DEVICE_DFP3_SUPPORT) -- atombios_device_dpms(output, ATOM_DEVICE_DFP3_SUPPORT, mode); -- } else if (radeon_output->MonType == MT_CRT) { -- ErrorF("AGD: dac dpms\n"); -- if (radeon_output->devices & ATOM_DEVICE_CRT1_SUPPORT) -- atombios_device_dpms(output, ATOM_DEVICE_CRT1_SUPPORT, mode); -- else if (radeon_output->devices & ATOM_DEVICE_CRT2_SUPPORT) -- atombios_device_dpms(output, ATOM_DEVICE_CRT2_SUPPORT, mode); -- } else if (radeon_output->MonType == MT_CV) { -- ErrorF("AGD: cv dpms\n"); -- if (radeon_output->devices & ATOM_DEVICE_CV_SUPPORT) -- atombios_device_dpms(output, ATOM_DEVICE_CV_SUPPORT, mode); -- } else if (0 /*radeon_output->MonType == MT_STV || -- radeon_output->MonType == MT_CTV*/) { -- ErrorF("AGD: tv dpms\n"); -- if (radeon_output->devices & ATOM_DEVICE_TV1_SUPPORT) -- atombios_device_dpms(output, ATOM_DEVICE_TV1_SUPPORT, mode); -- } -+ /*ErrorF("output dpms %d\n", mode);*/ -+ -+ if (radeon_output->MonType == MT_LCD) { -+ if (radeon_output->devices & ATOM_DEVICE_LCD1_SUPPORT) { -+ if (IS_DCE3_VARIANT) -+ atombios_output_dig_dpms(output, mode, 2); -+ else -+ atombios_device_dpms(output, ATOM_DEVICE_LCD1_SUPPORT, mode); -+ } -+ } else if (radeon_output->MonType == MT_DFP) { -+ /*ErrorF("tmds dpms\n");*/ -+ if (radeon_output->devices & ATOM_DEVICE_DFP1_SUPPORT) { -+ if (IS_DCE3_VARIANT) -+ atombios_output_dig_dpms(output, mode, 1); -+ else -+ atombios_device_dpms(output, ATOM_DEVICE_DFP1_SUPPORT, mode); -+ } else if (radeon_output->devices & ATOM_DEVICE_DFP2_SUPPORT) { -+ if (IS_DCE3_VARIANT) -+ return; // fixme -+ else -+ atombios_device_dpms(output, ATOM_DEVICE_DFP2_SUPPORT, mode); -+ } else if (radeon_output->devices & ATOM_DEVICE_DFP3_SUPPORT) { -+ if (IS_DCE3_VARIANT) -+ atombios_output_dig_dpms(output, mode, 2); -+ else -+ atombios_device_dpms(output, ATOM_DEVICE_DFP3_SUPPORT, mode); -+ } -+ } else if (radeon_output->MonType == MT_CRT) { -+ /*ErrorF("AGD: dac dpms\n");*/ -+ if (radeon_output->devices & ATOM_DEVICE_CRT1_SUPPORT) -+ atombios_device_dpms(output, ATOM_DEVICE_CRT1_SUPPORT, mode); -+ else if (radeon_output->devices & ATOM_DEVICE_CRT2_SUPPORT) -+ atombios_device_dpms(output, ATOM_DEVICE_CRT2_SUPPORT, mode); -+ } else if (radeon_output->MonType == MT_CV) { -+ /*ErrorF("AGD: cv dpms\n");*/ -+ if (radeon_output->devices & ATOM_DEVICE_CV_SUPPORT) -+ atombios_device_dpms(output, ATOM_DEVICE_CV_SUPPORT, mode); -+ } else if (0 /*radeon_output->MonType == MT_STV || -+ radeon_output->MonType == MT_CTV*/) { -+ /*ErrorF("AGD: tv dpms\n");*/ -+ if (radeon_output->devices & ATOM_DEVICE_TV1_SUPPORT) -+ atombios_device_dpms(output, ATOM_DEVICE_TV1_SUPPORT, mode); -+ } - - } - -@@ -498,15 +798,13 @@ atombios_set_output_crtc_source(xf86OutputPtr output) - AtomBiosArgRec data; - unsigned char *space; - SELECT_CRTC_SOURCE_PS_ALLOCATION crtc_src_param; -+ SELECT_CRTC_SOURCE_PARAMETERS_V2 crtc_src_param2; - int index = GetIndexIntoMasterTable(COMMAND, SelectCRTC_Source); - int major, minor; - - atombios_get_command_table_version(info->atomBIOS, index, &major, &minor); - -- ErrorF("select crtc source table is %d %d\n", major, minor); -- -- crtc_src_param.ucCRTC = radeon_crtc->crtc_id; -- crtc_src_param.ucDevice = 0; -+ /*ErrorF("select crtc source table is %d %d\n", major, minor);*/ - - switch(major) { - case 1: { -@@ -514,6 +812,8 @@ atombios_set_output_crtc_source(xf86OutputPtr output) - case 0: - case 1: - default: -+ crtc_src_param.ucCRTC = radeon_crtc->crtc_id; -+ crtc_src_param.ucDevice = 0; - if (radeon_output->MonType == MT_CRT) { - if (radeon_output->devices & ATOM_DEVICE_CRT1_SUPPORT) - crtc_src_param.ucDevice = ATOM_DEVICE_CRT1_INDEX; -@@ -536,6 +836,46 @@ atombios_set_output_crtc_source(xf86OutputPtr output) - if (radeon_output->devices & ATOM_DEVICE_CV_SUPPORT) - crtc_src_param.ucDevice = ATOM_DEVICE_CV_INDEX; - } -+ data.exec.pspace = &crtc_src_param; -+ /*ErrorF("device sourced: 0x%x\n", crtc_src_param.ucDevice);*/ -+ break; -+ case 2: -+ crtc_src_param2.ucCRTC = radeon_crtc->crtc_id; -+ if (radeon_output->MonType == MT_CRT) { -+ if (radeon_output->devices & ATOM_DEVICE_CRT1_SUPPORT) -+ crtc_src_param2.ucEncoderID = ATOM_DEVICE_CRT1_INDEX; -+ else if (radeon_output->devices & ATOM_DEVICE_CRT2_SUPPORT) -+ crtc_src_param2.ucEncoderID = ATOM_DEVICE_CRT2_INDEX; -+ crtc_src_param2.ucEncodeMode = ATOM_ENCODER_MODE_CRT; -+ } else if (radeon_output->MonType == MT_DFP) { -+ if (radeon_output->devices & ATOM_DEVICE_DFP1_SUPPORT) -+ crtc_src_param2.ucEncoderID = ATOM_DEVICE_DFP1_INDEX; -+ else if (radeon_output->devices & ATOM_DEVICE_DFP2_SUPPORT) -+ crtc_src_param2.ucEncoderID = ATOM_DEVICE_DFP2_INDEX; -+ else if (radeon_output->devices & ATOM_DEVICE_DFP3_SUPPORT) -+ crtc_src_param2.ucEncoderID = ATOM_DEVICE_DFP3_INDEX; -+ if (OUTPUT_IS_DVI) -+ crtc_src_param2.ucEncodeMode = ATOM_ENCODER_MODE_DVI; -+ else if (radeon_output->type == OUTPUT_HDMI) -+ crtc_src_param2.ucEncodeMode = ATOM_ENCODER_MODE_HDMI; -+ else if (radeon_output->type == OUTPUT_DP) -+ crtc_src_param2.ucEncodeMode = ATOM_ENCODER_MODE_DP; -+ } else if (radeon_output->MonType == MT_LCD) { -+ if (radeon_output->devices & ATOM_DEVICE_LCD1_SUPPORT) -+ crtc_src_param2.ucEncoderID = ATOM_DEVICE_LCD1_INDEX; -+ crtc_src_param2.ucEncodeMode = ATOM_ENCODER_MODE_LVDS; -+ } else if (OUTPUT_IS_TV) { -+ if (radeon_output->devices & ATOM_DEVICE_TV1_SUPPORT) -+ crtc_src_param2.ucEncoderID = ATOM_DEVICE_TV1_INDEX; -+ crtc_src_param2.ucEncodeMode = ATOM_ENCODER_MODE_TV; -+ } else if (radeon_output->MonType == MT_CV) { -+ if (radeon_output->devices & ATOM_DEVICE_CV_SUPPORT) -+ crtc_src_param2.ucEncoderID = ATOM_DEVICE_CV_INDEX; -+ crtc_src_param2.ucEncodeMode = ATOM_ENCODER_MODE_CV; -+ } -+ -+ data.exec.pspace = &crtc_src_param2; -+ /*ErrorF("device sourced: 0x%x\n", crtc_src_param2.ucEncoderID);*/ - break; - } - break; -@@ -544,11 +884,8 @@ atombios_set_output_crtc_source(xf86OutputPtr output) - break; - } - -- ErrorF("device sourced: 0x%x\n", crtc_src_param.ucDevice); -- - data.exec.index = index; - data.exec.dataSpace = (void *)&space; -- data.exec.pspace = &crtc_src_param; - - if (RHDAtomBiosFunc(info->atomBIOS->scrnIndex, info->atomBIOS, ATOMBIOS_EXEC, &data) == ATOM_SUCCESS) { - ErrorF("Set CRTC %d Source success\n", radeon_crtc->crtc_id); -@@ -579,19 +916,48 @@ atombios_output_mode_set(xf86OutputPtr output, - atombios_output_dac2_setup(output, adjusted_mode); - } - } else if (radeon_output->MonType == MT_DFP) { -- if (radeon_output->devices & ATOM_DEVICE_DFP1_SUPPORT) -- atombios_output_tmds1_setup(output, adjusted_mode); -- else if (radeon_output->devices & ATOM_DEVICE_DFP2_SUPPORT) { -- if (info->IsIGP) -- atombios_ddia_setup(output, adjusted_mode); -- else -- atombios_external_tmds_setup(output, adjusted_mode); -- } else if (radeon_output->devices & ATOM_DEVICE_DFP3_SUPPORT) -- atombios_output_tmds2_setup(output, adjusted_mode); -+ if (radeon_output->devices & ATOM_DEVICE_DFP1_SUPPORT) { -+ if (IS_DCE3_VARIANT) { -+ atombios_output_dig1_setup(output, adjusted_mode); -+ atombios_output_dig1_transmitter_setup(output, adjusted_mode); -+ } else { -+ atombios_output_tmds1_setup(output, adjusted_mode); -+ dfp_disable_dither(output, ATOM_DEVICE_DFP1_SUPPORT); -+ } -+ } else if (radeon_output->devices & ATOM_DEVICE_DFP2_SUPPORT) { -+ if (IS_DCE3_VARIANT) { -+ // fix me -+ } else { -+ if ((info->ChipFamily == CHIP_FAMILY_RS600) || -+ (info->ChipFamily == CHIP_FAMILY_RS690) || -+ (info->ChipFamily == CHIP_FAMILY_RS740)) -+ atombios_output_ddia_setup(output, adjusted_mode); -+ else -+ atombios_external_tmds_setup(output, adjusted_mode); -+ dfp_disable_dither(output, ATOM_DEVICE_DFP2_SUPPORT); -+ } -+ } else if (radeon_output->devices & ATOM_DEVICE_DFP3_SUPPORT) { -+ if (IS_DCE3_VARIANT) { -+ atombios_output_dig2_setup(output, adjusted_mode); -+ atombios_output_dig2_transmitter_setup(output, adjusted_mode); -+ } else { -+ atombios_output_tmds2_setup(output, adjusted_mode); -+ dfp_disable_dither(output, ATOM_DEVICE_DFP3_SUPPORT); -+ } -+ } - } else if (radeon_output->MonType == MT_LCD) { -- if (radeon_output->devices & ATOM_DEVICE_LCD1_SUPPORT) -- atombios_output_lvds_setup(output, adjusted_mode); -- } else if (OUTPUT_IS_TV || (radeon_output->MonType == MT_CV)) { -+ if (radeon_output->devices & ATOM_DEVICE_LCD1_SUPPORT) { -+ if (IS_DCE3_VARIANT) { -+ atombios_output_dig2_setup(output, adjusted_mode); -+ atombios_output_dig2_transmitter_setup(output, adjusted_mode); -+ } else { -+ atombios_output_lvds_setup(output, adjusted_mode); -+ dfp_disable_dither(output, ATOM_DEVICE_LCD1_SUPPORT); -+ } -+ } -+ } else if ((radeon_output->MonType == MT_CTV) || -+ (radeon_output->MonType == MT_STV) || -+ (radeon_output->MonType == MT_CV)) { - if (radeon_output->DACType == DAC_PRIMARY) - atombios_output_dac1_setup(output, adjusted_mode); - else if (radeon_output->DACType == DAC_TVDAC) -@@ -605,40 +971,46 @@ static AtomBiosResult - atom_bios_dac_load_detect(atomBiosHandlePtr atomBIOS, xf86OutputPtr output) - { - RADEONOutputPrivatePtr radeon_output = output->driver_private; -+ RADEONInfoPtr info = RADEONPTR(output->scrn); - DAC_LOAD_DETECTION_PS_ALLOCATION dac_data; - AtomBiosArgRec data; - unsigned char *space; - -+ dac_data.sDacload.ucMisc = 0; -+ - if (radeon_output->devices & ATOM_DEVICE_CRT1_SUPPORT) { -- dac_data.sDacload.usDeviceID = ATOM_DEVICE_CRT1_SUPPORT; -+ dac_data.sDacload.usDeviceID = cpu_to_le16(ATOM_DEVICE_CRT1_SUPPORT); - if (radeon_output->DACType == DAC_PRIMARY) - dac_data.sDacload.ucDacType = ATOM_DAC_A; - else if (radeon_output->DACType == DAC_TVDAC) - dac_data.sDacload.ucDacType = ATOM_DAC_B; - } else if (radeon_output->devices & ATOM_DEVICE_CRT2_SUPPORT) { -- dac_data.sDacload.usDeviceID = ATOM_DEVICE_CRT2_SUPPORT; -+ dac_data.sDacload.usDeviceID = cpu_to_le16(ATOM_DEVICE_CRT2_SUPPORT); - if (radeon_output->DACType == DAC_PRIMARY) - dac_data.sDacload.ucDacType = ATOM_DAC_A; - else if (radeon_output->DACType == DAC_TVDAC) - dac_data.sDacload.ucDacType = ATOM_DAC_B; - } else if (radeon_output->devices & ATOM_DEVICE_CV_SUPPORT) { -- dac_data.sDacload.usDeviceID = ATOM_DEVICE_CV_SUPPORT; -+ dac_data.sDacload.usDeviceID = cpu_to_le16(ATOM_DEVICE_CV_SUPPORT); - if (radeon_output->DACType == DAC_PRIMARY) - dac_data.sDacload.ucDacType = ATOM_DAC_A; - else if (radeon_output->DACType == DAC_TVDAC) - dac_data.sDacload.ucDacType = ATOM_DAC_B; -+ if (IS_DCE3_VARIANT) -+ dac_data.sDacload.ucMisc = 1; - } else if (radeon_output->devices & ATOM_DEVICE_TV1_SUPPORT) { -- dac_data.sDacload.usDeviceID = ATOM_DEVICE_TV1_SUPPORT; -+ dac_data.sDacload.usDeviceID = cpu_to_le16(ATOM_DEVICE_TV1_SUPPORT); - if (radeon_output->DACType == DAC_PRIMARY) - dac_data.sDacload.ucDacType = ATOM_DAC_A; - else if (radeon_output->DACType == DAC_TVDAC) - dac_data.sDacload.ucDacType = ATOM_DAC_B; -+ if (IS_DCE3_VARIANT) -+ dac_data.sDacload.ucMisc = 1; - } else { - ErrorF("invalid output device for dac detection\n"); - return ATOM_NOT_IMPLEMENTED; - } - -- dac_data.sDacload.ucMisc = 0; - - data.exec.index = GetIndexIntoMasterTable(COMMAND, DAC_LoadDetection); - data.exec.dataSpace = (void *)&space; -@@ -679,7 +1051,7 @@ atombios_dac_detect(ScrnInfoPtr pScrn, xf86OutputPtr output) - bios_0_scratch = INREG(R600_BIOS_0_SCRATCH); - else - bios_0_scratch = INREG(RADEON_BIOS_0_SCRATCH); -- ErrorF("DAC connect %08X\n", (unsigned int)bios_0_scratch); -+ /*ErrorF("DAC connect %08X\n", (unsigned int)bios_0_scratch);*/ - - if (radeon_output->devices & ATOM_DEVICE_CRT1_SUPPORT) { - if (bios_0_scratch & ATOM_S0_CRT1_MASK) -diff --git a/src/generic_bus.h b/src/generic_bus.h -index 6197eab..a04baa1 100644 ---- a/src/generic_bus.h -+++ b/src/generic_bus.h -@@ -4,6 +4,7 @@ - /* this is meant to be used for proprietary buses where abstraction is needed - but they don't occur often enough to warrant a separate helper library */ - -+#include - - #define GB_IOCTL_GET_NAME 1 - /* third argument is size of the buffer, fourth argument is pointer -@@ -21,10 +22,10 @@ typedef struct _GENERIC_BUS_Rec{ - int scrnIndex; - DevUnion DriverPrivate; - Bool (*ioctl)(GENERIC_BUS_Ptr, long, long, char *); -- Bool (*read)(GENERIC_BUS_Ptr, CARD32, CARD32, CARD8 *); -- Bool (*write)(GENERIC_BUS_Ptr, CARD32, CARD32, CARD8 *); -- Bool (*fifo_read)(GENERIC_BUS_Ptr, CARD32, CARD32, CARD8 *); -- Bool (*fifo_write)(GENERIC_BUS_Ptr, CARD32, CARD32, CARD8 *); -+ Bool (*read)(GENERIC_BUS_Ptr, uint32_t, uint32_t, uint8_t *); -+ Bool (*write)(GENERIC_BUS_Ptr, uint32_t, uint32_t, uint8_t *); -+ Bool (*fifo_read)(GENERIC_BUS_Ptr, uint32_t, uint32_t, uint8_t *); -+ Bool (*fifo_write)(GENERIC_BUS_Ptr, uint32_t, uint32_t, uint8_t *); - - } GENERIC_BUS_Rec; - -diff --git a/src/legacy_crtc.c b/src/legacy_crtc.c -index 06ad60c..334194a 100644 ---- a/src/legacy_crtc.c -+++ b/src/legacy_crtc.c -@@ -51,6 +51,9 @@ - #include "radeon_dri.h" - #include "radeon_sarea.h" - #include "sarea.h" -+#ifdef DRM_IOCTL_MODESET_CTL -+#include -+#endif - #endif - - /* Write common registers */ -@@ -78,6 +81,14 @@ RADEONRestoreCommonRegisters(ScrnInfoPtr pScrn, - OUTREG(RADEON_BUS_CNTL, restore->bus_cntl); - OUTREG(RADEON_SURFACE_CNTL, restore->surface_cntl); - -+ if ((info->ChipFamily == CHIP_FAMILY_RS400) || -+ (info->ChipFamily == CHIP_FAMILY_RS480)) { -+ OUTREG(RS400_DISP2_REQ_CNTL1, restore->disp2_req_cntl1); -+ OUTREG(RS400_DISP2_REQ_CNTL2, restore->disp2_req_cntl2); -+ OUTREG(RS400_DMIF_MEM_CNTL1, restore->dmif_mem_cntl1); -+ OUTREG(RS400_DISP1_REQ_CNTL1, restore->disp1_req_cntl1); -+ } -+ - /* Workaround for the VT switching problem in dual-head mode. This - * problem only occurs on RV style chips, typically when a FP and - * CRT are connected. -@@ -85,7 +96,7 @@ RADEONRestoreCommonRegisters(ScrnInfoPtr pScrn, - if (pRADEONEnt->HasCRTC2 && - info->ChipFamily != CHIP_FAMILY_R200 && - !IS_R300_VARIANT) { -- CARD32 tmp; -+ uint32_t tmp; - - tmp = INREG(RADEON_DAC_CNTL2); - OUTREG(RADEON_DAC_CNTL2, tmp & ~RADEON_DAC2_DAC_CLK_SEL); -@@ -148,7 +159,7 @@ RADEONRestoreCrtc2Registers(ScrnInfoPtr pScrn, - { - RADEONInfoPtr info = RADEONPTR(pScrn); - unsigned char *RADEONMMIO = info->MMIO; -- /* CARD32 crtc2_gen_cntl;*/ -+ /* uint32_t crtc2_gen_cntl;*/ - - xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG, - "Programming CRTC2, offset: 0x%08x\n", -@@ -178,12 +189,6 @@ RADEONRestoreCrtc2Registers(ScrnInfoPtr pScrn, - OUTREG(RADEON_CRTC2_PITCH, restore->crtc2_pitch); - OUTREG(RADEON_DISP2_MERGE_CNTL, restore->disp2_merge_cntl); - -- if (info->ChipFamily == CHIP_FAMILY_RS400) { -- OUTREG(RADEON_RS480_UNK_e30, restore->rs480_unk_e30); -- OUTREG(RADEON_RS480_UNK_e34, restore->rs480_unk_e34); -- OUTREG(RADEON_RS480_UNK_e38, restore->rs480_unk_e38); -- OUTREG(RADEON_RS480_UNK_e3c, restore->rs480_unk_e3c); -- } - OUTREG(RADEON_CRTC2_GEN_CNTL, restore->crtc2_gen_cntl); - - } -@@ -238,9 +243,9 @@ RADEONPLL2WriteUpdate(ScrnInfoPtr pScrn) - ~(RADEON_P2PLL_ATOMIC_UPDATE_W)); - } - --static CARD8 --RADEONComputePLLGain(CARD16 reference_freq, CARD16 ref_div, -- CARD16 fb_div) -+static uint8_t -+RADEONComputePLLGain(uint16_t reference_freq, uint16_t ref_div, -+ uint16_t fb_div) - { - unsigned vcoFreq; - -@@ -277,7 +282,7 @@ RADEONRestorePLLRegisters(ScrnInfoPtr pScrn, - { - RADEONInfoPtr info = RADEONPTR(pScrn); - unsigned char *RADEONMMIO = info->MMIO; -- CARD8 pllGain; -+ uint8_t pllGain; - - #if defined(__powerpc__) - /* apparently restoring the pll causes a hang??? */ -@@ -316,7 +321,7 @@ RADEONRestorePLLRegisters(ScrnInfoPtr pScrn, - RADEON_PPLL_RESET - | RADEON_PPLL_ATOMIC_UPDATE_EN - | RADEON_PPLL_VGA_ATOMIC_UPDATE_EN -- | ((CARD32)pllGain << RADEON_PPLL_PVG_SHIFT), -+ | ((uint32_t)pllGain << RADEON_PPLL_PVG_SHIFT), - ~(RADEON_PPLL_RESET - | RADEON_PPLL_ATOMIC_UPDATE_EN - | RADEON_PPLL_VGA_ATOMIC_UPDATE_EN -@@ -329,7 +334,8 @@ RADEONRestorePLLRegisters(ScrnInfoPtr pScrn, - - if (IS_R300_VARIANT || - (info->ChipFamily == CHIP_FAMILY_RS300) || -- (info->ChipFamily == CHIP_FAMILY_RS400)) { -+ (info->ChipFamily == CHIP_FAMILY_RS400) || -+ (info->ChipFamily == CHIP_FAMILY_RS480)) { - if (restore->ppll_ref_div & R300_PPLL_REF_DIV_ACC_MASK) { - /* When restoring console mode, use saved PPLL_REF_DIV - * setting. -@@ -399,7 +405,7 @@ RADEONRestorePLL2Registers(ScrnInfoPtr pScrn, - RADEONSavePtr restore) - { - RADEONInfoPtr info = RADEONPTR(pScrn); -- CARD8 pllGain; -+ uint8_t pllGain; - - pllGain = RADEONComputePLLGain(info->pll.reference_freq, - restore->p2pll_ref_div & RADEON_P2PLL_REF_DIV_MASK, -@@ -414,7 +420,7 @@ RADEONRestorePLL2Registers(ScrnInfoPtr pScrn, - RADEON_P2PLL_CNTL, - RADEON_P2PLL_RESET - | RADEON_P2PLL_ATOMIC_UPDATE_EN -- | ((CARD32)pllGain << RADEON_P2PLL_PVG_SHIFT), -+ | ((uint32_t)pllGain << RADEON_P2PLL_PVG_SHIFT), - ~(RADEON_P2PLL_RESET - | RADEON_P2PLL_ATOMIC_UPDATE_EN - | RADEON_P2PLL_PVG_MASK)); -@@ -489,6 +495,14 @@ RADEONSaveCommonRegisters(ScrnInfoPtr pScrn, RADEONSavePtr save) - save->surface_cntl = INREG(RADEON_SURFACE_CNTL); - save->grph_buffer_cntl = INREG(RADEON_GRPH_BUFFER_CNTL); - save->grph2_buffer_cntl = INREG(RADEON_GRPH2_BUFFER_CNTL); -+ -+ if ((info->ChipFamily == CHIP_FAMILY_RS400) || -+ (info->ChipFamily == CHIP_FAMILY_RS480)) { -+ save->disp2_req_cntl1 = INREG(RS400_DISP2_REQ_CNTL1); -+ save->disp2_req_cntl2 = INREG(RS400_DISP2_REQ_CNTL2); -+ save->dmif_mem_cntl1 = INREG(RS400_DMIF_MEM_CNTL1); -+ save->disp1_req_cntl1 = INREG(RS400_DISP1_REQ_CNTL1); -+ } - } - - /* Read CRTC registers */ -@@ -550,13 +564,6 @@ RADEONSaveCrtc2Registers(ScrnInfoPtr pScrn, RADEONSavePtr save) - save->fp_h2_sync_strt_wid = INREG (RADEON_FP_H2_SYNC_STRT_WID); - save->fp_v2_sync_strt_wid = INREG (RADEON_FP_V2_SYNC_STRT_WID); - -- if (info->ChipFamily == CHIP_FAMILY_RS400) { -- save->rs480_unk_e30 = INREG(RADEON_RS480_UNK_e30); -- save->rs480_unk_e34 = INREG(RADEON_RS480_UNK_e34); -- save->rs480_unk_e38 = INREG(RADEON_RS480_UNK_e38); -- save->rs480_unk_e3c = INREG(RADEON_RS480_UNK_e3c); -- } -- - save->disp2_merge_cntl = INREG(RADEON_DISP2_MERGE_CNTL); - - /* track if the crtc is enabled for text restore */ -@@ -611,16 +618,35 @@ RADEONSavePLL2Registers(ScrnInfoPtr pScrn, RADEONSavePtr save) - } - - void -+radeon_crtc_modeset_ioctl(xf86CrtcPtr crtc, Bool post) -+{ -+#if defined(XF86DRI) && defined(DRM_IOCTL_MODESET_CTL) -+ RADEONInfoPtr info = RADEONPTR(crtc->scrn); -+ RADEONCrtcPrivatePtr radeon_crtc = crtc->driver_private; -+ struct drm_modeset_ctl modeset; -+ -+ if (!info->directRenderingEnabled) -+ return; -+ -+ modeset.crtc = radeon_crtc->crtc_id; -+ modeset.cmd = post ? _DRM_POST_MODESET : _DRM_PRE_MODESET; -+ -+ ioctl(info->drmFD, DRM_IOCTL_MODESET_CTL, &modeset); -+#endif -+} -+ -+void - legacy_crtc_dpms(xf86CrtcPtr crtc, int mode) - { - int mask; -- ScrnInfoPtr pScrn = crtc->scrn; - RADEONCrtcPrivatePtr radeon_crtc = crtc->driver_private; -- RADEONInfoPtr info = RADEONPTR(pScrn); -- unsigned char *RADEONMMIO = info->MMIO; -+ RADEONEntPtr pRADEONEnt = RADEONEntPriv(crtc->scrn); -+ unsigned char *RADEONMMIO = pRADEONEnt->MMIO; - - mask = radeon_crtc->crtc_id ? (RADEON_CRTC2_DISP_DIS | RADEON_CRTC2_VSYNC_DIS | RADEON_CRTC2_HSYNC_DIS | RADEON_CRTC2_DISP_REQ_EN_B) : (RADEON_CRTC_DISPLAY_DIS | RADEON_CRTC_HSYNC_DIS | RADEON_CRTC_VSYNC_DIS); - -+ if (mode == DPMSModeOff) -+ radeon_crtc_modeset_ioctl(crtc, FALSE); - - switch(mode) { - case DPMSModeOn: -@@ -657,8 +683,10 @@ legacy_crtc_dpms(xf86CrtcPtr crtc, int mode) - break; - } - -- if (mode != DPMSModeOff) -+ if (mode != DPMSModeOff) { -+ radeon_crtc_modeset_ioctl(crtc, TRUE); - radeon_crtc_load_lut(crtc); -+ } - } - - -@@ -677,6 +705,15 @@ RADEONInitCommonRegisters(RADEONSavePtr save, RADEONInfoPtr info) - save->cap0_trig_cntl = 0; - save->cap1_trig_cntl = 0; - save->bus_cntl = info->BusCntl; -+ -+ if ((info->ChipFamily == CHIP_FAMILY_RS400) || -+ (info->ChipFamily == CHIP_FAMILY_RS480)) { -+ save->disp2_req_cntl1 = info->SavedReg->disp2_req_cntl1; -+ save->disp2_req_cntl2 = info->SavedReg->disp2_req_cntl2; -+ save->dmif_mem_cntl1 = info->SavedReg->dmif_mem_cntl1; -+ save->disp1_req_cntl1 = info->SavedReg->disp1_req_cntl1; -+ } -+ - /* - * If bursts are enabled, turn on discards - * Radeon doesn't have write bursts -@@ -1125,13 +1162,6 @@ RADEONInitCrtc2Registers(xf86CrtcPtr crtc, RADEONSavePtr save, - save->fp_h2_sync_strt_wid = save->crtc2_h_sync_strt_wid; - save->fp_v2_sync_strt_wid = save->crtc2_v_sync_strt_wid; - -- if (info->ChipFamily == CHIP_FAMILY_RS400) { -- save->rs480_unk_e30 = 0x105DC1CC; /* because I'm worth it */ -- save->rs480_unk_e34 = 0x2749D000; /* AMD really should */ -- save->rs480_unk_e38 = 0x29ca71dc; /* release docs */ -- save->rs480_unk_e3c = 0x28FBC3AC; /* this is so a trade secret */ -- } -- - return TRUE; - } - -@@ -1143,10 +1173,10 @@ RADEONInitPLLRegisters(ScrnInfoPtr pScrn, RADEONSavePtr save, - int flags) - { - RADEONInfoPtr info = RADEONPTR(pScrn); -- CARD32 feedback_div = 0; -- CARD32 reference_div = 0; -- CARD32 post_divider = 0; -- CARD32 freq = 0; -+ uint32_t feedback_div = 0; -+ uint32_t reference_div = 0; -+ uint32_t post_divider = 0; -+ uint32_t freq = 0; - - struct { - int divider; -@@ -1224,10 +1254,10 @@ RADEONInitPLL2Registers(ScrnInfoPtr pScrn, RADEONSavePtr save, - int flags) - { - RADEONInfoPtr info = RADEONPTR(pScrn); -- CARD32 feedback_div = 0; -- CARD32 reference_div = 0; -- CARD32 post_divider = 0; -- CARD32 freq = 0; -+ uint32_t feedback_div = 0; -+ uint32_t reference_div = 0; -+ uint32_t post_divider = 0; -+ uint32_t freq = 0; - - struct { - int divider; -@@ -1300,22 +1330,25 @@ radeon_update_tv_routing(ScrnInfoPtr pScrn, RADEONSavePtr restore) - } - - /* Calculate display buffer watermark to prevent buffer underflow */ --static void --RADEONInitDispBandwidth2(ScrnInfoPtr pScrn, RADEONInfoPtr info, int pixel_bytes2, DisplayModePtr mode1, DisplayModePtr mode2) -+void -+RADEONInitDispBandwidthLegacy(ScrnInfoPtr pScrn, -+ DisplayModePtr mode1, int pixel_bytes1, -+ DisplayModePtr mode2, int pixel_bytes2) - { -+ RADEONInfoPtr info = RADEONPTR(pScrn); - RADEONEntPtr pRADEONEnt = RADEONEntPriv(pScrn); - unsigned char *RADEONMMIO = info->MMIO; - -- CARD32 temp, data, mem_trcd, mem_trp, mem_tras, mem_trbs=0; -+ uint32_t temp, data, mem_trcd, mem_trp, mem_tras, mem_trbs=0; - float mem_tcas; - int k1, c; -- CARD32 MemTrcdExtMemCntl[4] = {1, 2, 3, 4}; -- CARD32 MemTrpExtMemCntl[4] = {1, 2, 3, 4}; -- CARD32 MemTrasExtMemCntl[8] = {1, 2, 3, 4, 5, 6, 7, 8}; -+ uint32_t MemTrcdExtMemCntl[4] = {1, 2, 3, 4}; -+ uint32_t MemTrpExtMemCntl[4] = {1, 2, 3, 4}; -+ uint32_t MemTrasExtMemCntl[8] = {1, 2, 3, 4, 5, 6, 7, 8}; - -- CARD32 MemTrcdMemTimingCntl[8] = {1, 2, 3, 4, 5, 6, 7, 8}; -- CARD32 MemTrpMemTimingCntl[8] = {1, 2, 3, 4, 5, 6, 7, 8}; -- CARD32 MemTrasMemTimingCntl[16] = {4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19}; -+ uint32_t MemTrcdMemTimingCntl[8] = {1, 2, 3, 4, 5, 6, 7, 8}; -+ uint32_t MemTrpMemTimingCntl[8] = {1, 2, 3, 4, 5, 6, 7, 8}; -+ uint32_t MemTrasMemTimingCntl[16] = {4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19}; - - float MemTcas[8] = {0, 1, 2, 3, 0, 1.5, 2.5, 0}; - float MemTcas2[8] = {0, 1, 2, 3, 4, 5, 6, 7}; -@@ -1325,10 +1358,10 @@ RADEONInitDispBandwidth2(ScrnInfoPtr pScrn, RADEONInfoPtr info, int pixel_bytes2 - float min_mem_eff = 0.8; - float sclk_eff, sclk_delay; - float mc_latency_mclk, mc_latency_sclk, cur_latency_mclk, cur_latency_sclk; -- float disp_latency, disp_latency_overhead, disp_drain_rate, disp_drain_rate2; -+ float disp_latency, disp_latency_overhead, disp_drain_rate = 0, disp_drain_rate2; - float pix_clk, pix_clk2; /* in MHz */ - int cur_size = 16; /* in octawords */ -- int critical_point, critical_point2; -+ int critical_point = 0, critical_point2; - int stop_req, max_stop_req; - float read_return_rate, time_disp1_drop_priority; - -@@ -1338,16 +1371,16 @@ RADEONInitDispBandwidth2(ScrnInfoPtr pScrn, RADEONInfoPtr info, int pixel_bytes2 - * option. - */ - if ((info->DispPriority == 2) && IS_R300_VARIANT) { -- CARD32 mc_init_misc_lat_timer = INREG(R300_MC_INIT_MISC_LAT_TIMER); -- if (pRADEONEnt->pCrtc[1]->enabled) { -- mc_init_misc_lat_timer |= 0x1100; /* display 0 and 1 */ -- } else { -- mc_init_misc_lat_timer |= 0x0100; /* display 0 only */ -- } -+ uint32_t mc_init_misc_lat_timer = INREG(R300_MC_INIT_MISC_LAT_TIMER); -+ mc_init_misc_lat_timer &= ~(R300_MC_DISP1R_INIT_LAT_MASK << R300_MC_DISP1R_INIT_LAT_SHIFT); -+ mc_init_misc_lat_timer &= ~(R300_MC_DISP0R_INIT_LAT_MASK << R300_MC_DISP0R_INIT_LAT_SHIFT); -+ if (pRADEONEnt->pCrtc[1]->enabled) -+ mc_init_misc_lat_timer |= (1 << R300_MC_DISP1R_INIT_LAT_SHIFT); /* display 1 */ -+ if (pRADEONEnt->pCrtc[0]->enabled) -+ mc_init_misc_lat_timer |= (1 << R300_MC_DISP0R_INIT_LAT_SHIFT); /* display 0 */ - OUTREG(R300_MC_INIT_MISC_LAT_TIMER, mc_init_misc_lat_timer); - } - -- - /* R420 and RV410 family not supported yet */ - if (info->ChipFamily == CHIP_FAMILY_R420 || info->ChipFamily == CHIP_FAMILY_RV410) return; - -@@ -1356,15 +1389,17 @@ RADEONInitDispBandwidth2(ScrnInfoPtr pScrn, RADEONInfoPtr info, int pixel_bytes2 - */ - mem_bw = info->mclk * (info->RamWidth / 8) * (info->IsDDR ? 2 : 1); - -- pix_clk = mode1->Clock/1000.0; -- if (mode2) -+ pix_clk = 0; -+ pix_clk2 = 0; -+ peak_disp_bw = 0; -+ if (mode1) { -+ pix_clk = mode1->Clock/1000.0; -+ peak_disp_bw += (pix_clk * pixel_bytes1); -+ } -+ if (mode2) { - pix_clk2 = mode2->Clock/1000.0; -- else -- pix_clk2 = 0; -- -- peak_disp_bw = (pix_clk * info->CurrentLayout.pixel_bytes); -- if (pixel_bytes2) -- peak_disp_bw += (pix_clk2 * pixel_bytes2); -+ peak_disp_bw += (pix_clk2 * pixel_bytes2); -+ } - - if (peak_disp_bw >= mem_bw * min_mem_eff) { - xf86DrvMsg(pScrn->scrnIndex, X_WARNING, -@@ -1372,20 +1407,6 @@ RADEONInitDispBandwidth2(ScrnInfoPtr pScrn, RADEONInfoPtr info, int pixel_bytes2 - "If you have flickering problem, try to lower resolution, refresh rate, or color depth\n"); - } - -- /* CRTC1 -- Set GRPH_BUFFER_CNTL register using h/w defined optimal values. -- GRPH_STOP_REQ <= MIN[ 0x7C, (CRTC_H_DISP + 1) * (bit depth) / 0x10 ] -- */ -- stop_req = mode1->HDisplay * info->CurrentLayout.pixel_bytes / 16; -- -- /* setup Max GRPH_STOP_REQ default value */ -- if (IS_RV100_VARIANT) -- max_stop_req = 0x5c; -- else -- max_stop_req = 0x7c; -- if (stop_req > max_stop_req) -- stop_req = max_stop_req; -- - /* Get values from the EXT_MEM_CNTL register...converting its contents. */ - temp = INREG(RADEON_MEM_TIMING_CNTL); - if ((info->ChipFamily == CHIP_FAMILY_RV100) || info->IsIGP) { /* RV100, M6, IGPs */ -@@ -1408,9 +1429,8 @@ RADEONInitDispBandwidth2(ScrnInfoPtr pScrn, RADEONInfoPtr info, int pixel_bytes2 - } - - if (IS_R300_VARIANT) { -- - /* on the R300, Tcas is included in Trbs. -- */ -+ */ - temp = INREG(RADEON_MEM_CNTL); - data = (R300_MEM_NUM_CHANNELS_MASK & temp); - if (data == 1) { -@@ -1446,7 +1466,8 @@ RADEONInitDispBandwidth2(ScrnInfoPtr pScrn, RADEONInfoPtr info, int pixel_bytes2 - sclk_eff = info->sclk; - } - -- /* Find the memory controller latency for the display client. -+ /* -+ Find the memory controller latency for the display client. - */ - if (IS_R300_VARIANT) { - /*not enough for R350 ???*/ -@@ -1500,70 +1521,107 @@ RADEONInitDispBandwidth2(ScrnInfoPtr pScrn, RADEONInfoPtr info, int pixel_bytes2 - mc_latency_sclk = mc_latency_sclk + disp_latency_overhead + cur_latency_sclk; - disp_latency = MAX(mc_latency_mclk, mc_latency_sclk); - -- /* -- Find the drain rate of the display buffer. -- */ -- disp_drain_rate = pix_clk / (16.0/info->CurrentLayout.pixel_bytes); -- if (pixel_bytes2) -- disp_drain_rate2 = pix_clk2 / (16.0/pixel_bytes2); -+ /* setup Max GRPH_STOP_REQ default value */ -+ if (IS_RV100_VARIANT) -+ max_stop_req = 0x5c; - else -- disp_drain_rate2 = 0; -+ max_stop_req = 0x7c; - -- /* -- Find the critical point of the display buffer. -- */ -- critical_point= (CARD32)(disp_drain_rate * disp_latency + 0.5); -+ if (mode1) { -+ /* CRTC1 -+ Set GRPH_BUFFER_CNTL register using h/w defined optimal values. -+ GRPH_STOP_REQ <= MIN[ 0x7C, (CRTC_H_DISP + 1) * (bit depth) / 0x10 ] -+ */ -+ stop_req = mode1->HDisplay * pixel_bytes1 / 16; - -- /* ???? */ -- /* -- temp = (info->SavedReg.grph_buffer_cntl & RADEON_GRPH_CRITICAL_POINT_MASK) >> RADEON_GRPH_CRITICAL_POINT_SHIFT; -- if (critical_point < temp) critical_point = temp; -- */ -- if (info->DispPriority == 2) { -- critical_point = 0; -- } -+ if (stop_req > max_stop_req) -+ stop_req = max_stop_req; - -- /* -- The critical point should never be above max_stop_req-4. Setting -- GRPH_CRITICAL_CNTL = 0 will thus force high priority all the time. -- */ -- if (max_stop_req - critical_point < 4) critical_point = 0; -+ /* -+ Find the drain rate of the display buffer. -+ */ -+ disp_drain_rate = pix_clk / (16.0/pixel_bytes1); - -- if (critical_point == 0 && mode2 && info->ChipFamily == CHIP_FAMILY_R300) { -- /* some R300 cards have problem with this set to 0, when CRTC2 is enabled.*/ -- critical_point = 0x10; -- } -+ /* -+ Find the critical point of the display buffer. -+ */ -+ critical_point= (uint32_t)(disp_drain_rate * disp_latency + 0.5); - -- temp = info->SavedReg->grph_buffer_cntl; -- temp &= ~(RADEON_GRPH_STOP_REQ_MASK); -- temp |= (stop_req << RADEON_GRPH_STOP_REQ_SHIFT); -- temp &= ~(RADEON_GRPH_START_REQ_MASK); -- if ((info->ChipFamily == CHIP_FAMILY_R350) && -- (stop_req > 0x15)) { -- stop_req -= 0x10; -- } -- temp |= (stop_req << RADEON_GRPH_START_REQ_SHIFT); -+ /* ???? */ -+ /* -+ temp = (info->SavedReg.grph_buffer_cntl & RADEON_GRPH_CRITICAL_POINT_MASK) >> RADEON_GRPH_CRITICAL_POINT_SHIFT; -+ if (critical_point < temp) critical_point = temp; -+ */ -+ if (info->DispPriority == 2) { -+ critical_point = 0; -+ } - -- temp |= RADEON_GRPH_BUFFER_SIZE; -- temp &= ~(RADEON_GRPH_CRITICAL_CNTL | -- RADEON_GRPH_CRITICAL_AT_SOF | -- RADEON_GRPH_STOP_CNTL); -- /* -- Write the result into the register. -- */ -- OUTREG(RADEON_GRPH_BUFFER_CNTL, ((temp & ~RADEON_GRPH_CRITICAL_POINT_MASK) | -- (critical_point << RADEON_GRPH_CRITICAL_POINT_SHIFT))); -+ /* -+ The critical point should never be above max_stop_req-4. Setting -+ GRPH_CRITICAL_CNTL = 0 will thus force high priority all the time. -+ */ -+ if (max_stop_req - critical_point < 4) critical_point = 0; - -- xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG, -- "GRPH_BUFFER_CNTL from %x to %x\n", -- (unsigned int)info->SavedReg->grph_buffer_cntl, -- (unsigned int)INREG(RADEON_GRPH_BUFFER_CNTL)); -+ if (critical_point == 0 && mode2 && info->ChipFamily == CHIP_FAMILY_R300) { -+ /* some R300 cards have problem with this set to 0, when CRTC2 is enabled.*/ -+ critical_point = 0x10; -+ } -+ -+ temp = info->SavedReg->grph_buffer_cntl; -+ temp &= ~(RADEON_GRPH_STOP_REQ_MASK); -+ temp |= (stop_req << RADEON_GRPH_STOP_REQ_SHIFT); -+ temp &= ~(RADEON_GRPH_START_REQ_MASK); -+ if ((info->ChipFamily == CHIP_FAMILY_R350) && -+ (stop_req > 0x15)) { -+ stop_req -= 0x10; -+ } -+ temp |= (stop_req << RADEON_GRPH_START_REQ_SHIFT); -+ -+ temp |= RADEON_GRPH_BUFFER_SIZE; -+ temp &= ~(RADEON_GRPH_CRITICAL_CNTL | -+ RADEON_GRPH_CRITICAL_AT_SOF | -+ RADEON_GRPH_STOP_CNTL); -+ /* -+ Write the result into the register. -+ */ -+ OUTREG(RADEON_GRPH_BUFFER_CNTL, ((temp & ~RADEON_GRPH_CRITICAL_POINT_MASK) | -+ (critical_point << RADEON_GRPH_CRITICAL_POINT_SHIFT))); -+ -+#if 0 -+ if ((info->ChipFamily == CHIP_FAMILY_RS400) || -+ (info->ChipFamily == CHIP_FAMILY_RS480)) { -+ /* attempt to program RS400 disp regs correctly ??? */ -+ temp = info->SavedReg->disp1_req_cntl1; -+ temp &= ~(RS400_DISP1_START_REQ_LEVEL_MASK | -+ RS400_DISP1_STOP_REQ_LEVEL_MASK); -+ OUTREG(RS400_DISP1_REQ_CNTL1, (temp | -+ (critical_point << RS400_DISP1_START_REQ_LEVEL_SHIFT) | -+ (critical_point << RS400_DISP1_STOP_REQ_LEVEL_SHIFT))); -+ temp = info->SavedReg->dmif_mem_cntl1; -+ temp &= ~(RS400_DISP1_CRITICAL_POINT_START_MASK | -+ RS400_DISP1_CRITICAL_POINT_STOP_MASK); -+ OUTREG(RS400_DMIF_MEM_CNTL1, (temp | -+ (critical_point << RS400_DISP1_CRITICAL_POINT_START_SHIFT) | -+ (critical_point << RS400_DISP1_CRITICAL_POINT_STOP_SHIFT))); -+ } -+#endif -+ -+ xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG, -+ "GRPH_BUFFER_CNTL from %x to %x\n", -+ (unsigned int)info->SavedReg->grph_buffer_cntl, -+ (unsigned int)INREG(RADEON_GRPH_BUFFER_CNTL)); -+ } - - if (mode2) { - stop_req = mode2->HDisplay * pixel_bytes2 / 16; - - if (stop_req > max_stop_req) stop_req = max_stop_req; - -+ /* -+ Find the drain rate of the display buffer. -+ */ -+ disp_drain_rate2 = pix_clk2 / (16.0/pixel_bytes2); -+ - temp = info->SavedReg->grph2_buffer_cntl; - temp &= ~(RADEON_GRPH_STOP_REQ_MASK); - temp |= (stop_req << RADEON_GRPH_STOP_REQ_SHIFT); -@@ -1583,9 +1641,12 @@ RADEONInitDispBandwidth2(ScrnInfoPtr pScrn, RADEONInfoPtr info, int pixel_bytes2 - critical_point2 = 0; - else { - read_return_rate = MIN(info->sclk, info->mclk*(info->RamWidth*(info->IsDDR+1)/128)); -- time_disp1_drop_priority = critical_point / (read_return_rate - disp_drain_rate); -+ if (mode1) -+ time_disp1_drop_priority = critical_point / (read_return_rate - disp_drain_rate); -+ else -+ time_disp1_drop_priority = 0; - -- critical_point2 = (CARD32)((disp_latency + time_disp1_drop_priority + -+ critical_point2 = (uint32_t)((disp_latency + time_disp1_drop_priority + - disp_latency) * disp_drain_rate2 + 0.5); - - if (info->DispPriority == 2) { -@@ -1604,6 +1665,29 @@ RADEONInitDispBandwidth2(ScrnInfoPtr pScrn, RADEONInfoPtr info, int pixel_bytes2 - OUTREG(RADEON_GRPH2_BUFFER_CNTL, ((temp & ~RADEON_GRPH_CRITICAL_POINT_MASK) | - (critical_point2 << RADEON_GRPH_CRITICAL_POINT_SHIFT))); - -+ if ((info->ChipFamily == CHIP_FAMILY_RS400) || -+ (info->ChipFamily == CHIP_FAMILY_RS480)) { -+#if 0 -+ /* attempt to program RS400 disp2 regs correctly ??? */ -+ temp = info->SavedReg->disp2_req_cntl1; -+ temp &= ~(RS400_DISP2_START_REQ_LEVEL_MASK | -+ RS400_DISP2_STOP_REQ_LEVEL_MASK); -+ OUTREG(RS400_DISP2_REQ_CNTL1, (temp | -+ (critical_point2 << RS400_DISP1_START_REQ_LEVEL_SHIFT) | -+ (critical_point2 << RS400_DISP1_STOP_REQ_LEVEL_SHIFT))); -+ temp = info->SavedReg->disp2_req_cntl2; -+ temp &= ~(RS400_DISP2_CRITICAL_POINT_START_MASK | -+ RS400_DISP2_CRITICAL_POINT_STOP_MASK); -+ OUTREG(RS400_DISP2_REQ_CNTL2, (temp | -+ (critical_point2 << RS400_DISP2_CRITICAL_POINT_START_SHIFT) | -+ (critical_point2 << RS400_DISP2_CRITICAL_POINT_STOP_SHIFT))); -+#endif -+ OUTREG(RS400_DISP2_REQ_CNTL1, 0x105DC1CC); -+ OUTREG(RS400_DISP2_REQ_CNTL2, 0x2749D000); -+ OUTREG(RS400_DMIF_MEM_CNTL1, 0x29CA71DC); -+ OUTREG(RS400_DISP1_REQ_CNTL1, 0x28FBC3AC); -+ } -+ - xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG, - "GRPH2_BUFFER_CNTL from %x to %x\n", - (unsigned int)info->SavedReg->grph2_buffer_cntl, -@@ -1612,45 +1696,6 @@ RADEONInitDispBandwidth2(ScrnInfoPtr pScrn, RADEONInfoPtr info, int pixel_bytes2 - } - - void --RADEONInitDispBandwidth(ScrnInfoPtr pScrn) --{ -- RADEONInfoPtr info = RADEONPTR(pScrn); -- xf86CrtcConfigPtr xf86_config = XF86_CRTC_CONFIG_PTR(pScrn); -- DisplayModePtr mode1, mode2; -- int pixel_bytes2 = 0; -- -- if (info->IsPrimary || info->IsSecondary) -- mode1 = &xf86_config->crtc[0]->mode; -- else -- mode1 = info->CurrentLayout.mode; -- mode2 = NULL; -- pixel_bytes2 = info->CurrentLayout.pixel_bytes; -- -- if (xf86_config->num_crtc == 2) { -- pixel_bytes2 = 0; -- mode2 = NULL; -- -- if (xf86_config->crtc[1]->enabled && xf86_config->crtc[0]->enabled) { -- pixel_bytes2 = info->CurrentLayout.pixel_bytes; -- mode1 = &xf86_config->crtc[0]->mode; -- mode2 = &xf86_config->crtc[1]->mode; -- } else if (xf86_config->crtc[0]->enabled) { -- mode1 = &xf86_config->crtc[0]->mode; -- } else if (xf86_config->crtc[1]->enabled) { -- mode1 = &xf86_config->crtc[1]->mode; -- } else -- return; -- } else { -- if (xf86_config->crtc[0]->enabled) -- mode1 = &xf86_config->crtc[0]->mode; -- else -- return; -- } -- -- RADEONInitDispBandwidth2(pScrn, info, pixel_bytes2, mode1, mode2); --} -- --void - legacy_crtc_mode_set(xf86CrtcPtr crtc, DisplayModePtr mode, - DisplayModePtr adjusted_mode, int x, int y) - { -@@ -1658,26 +1703,15 @@ legacy_crtc_mode_set(xf86CrtcPtr crtc, DisplayModePtr mode, - xf86CrtcConfigPtr xf86_config = XF86_CRTC_CONFIG_PTR(pScrn); - RADEONCrtcPrivatePtr radeon_crtc = crtc->driver_private; - RADEONInfoPtr info = RADEONPTR(pScrn); -- Bool tilingOld = info->tilingEnabled; - int i = 0; - double dot_clock = 0; -- int pll_flags = RADEON_PLL_LEGACY; -+ int pll_flags = RADEON_PLL_LEGACY | RADEON_PLL_PREFER_LOW_REF_DIV; - Bool update_tv_routing = FALSE; -- -+ Bool tilingChanged = FALSE; - - if (info->allowColorTiling) { -- info->tilingEnabled = (adjusted_mode->Flags & (V_DBLSCAN | V_INTERLACE)) ? FALSE : TRUE; --#ifdef XF86DRI -- if (info->directRenderingEnabled && (info->tilingEnabled != tilingOld)) { -- RADEONSAREAPrivPtr pSAREAPriv; -- if (RADEONDRISetParam(pScrn, RADEON_SETPARAM_SWITCH_TILING, (info->tilingEnabled ? 1 : 0)) < 0) -- xf86DrvMsg(pScrn->scrnIndex, X_ERROR, -- "[drm] failed changing tiling status\n"); -- /* if this is called during ScreenInit() we don't have pScrn->pScreen yet */ -- pSAREAPriv = DRIGetSAREAPrivate(screenInfo.screens[pScrn->scrnIndex]); -- info->tilingEnabled = pSAREAPriv->tiling_enabled ? TRUE : FALSE; -- } --#endif -+ radeon_crtc->can_tile = (adjusted_mode->Flags & (V_DBLSCAN | V_INTERLACE)) ? FALSE : TRUE; -+ tilingChanged = RADEONSetTiling(pScrn); - } - - for (i = 0; i < xf86_config->num_output; i++) { -@@ -1775,7 +1809,7 @@ legacy_crtc_mode_set(xf86CrtcPtr crtc, DisplayModePtr mode, - if (info->DispPriority) - RADEONInitDispBandwidth(pScrn); - -- if (info->tilingEnabled != tilingOld) { -+ if (tilingChanged) { - /* need to redraw front buffer, I guess this can be considered a hack ? */ - /* if this is called during ScreenInit() we don't have pScrn->pScreen yet */ - if (pScrn->pScreen) -diff --git a/src/legacy_output.c b/src/legacy_output.c -index 0de13df..ccf59ba 100644 ---- a/src/legacy_output.c -+++ b/src/legacy_output.c -@@ -48,6 +48,8 @@ - #include "radeon_tv.h" - #include "radeon_atombios.h" - -+#include "ati_pciids_gen.h" -+ - static RADEONMonitorType radeon_detect_tv(ScrnInfoPtr pScrn); - static RADEONMonitorType radeon_detect_primary_dac(ScrnInfoPtr pScrn, Bool color); - static RADEONMonitorType radeon_detect_tv_dac(ScrnInfoPtr pScrn, Bool color); -@@ -71,7 +73,7 @@ RADEONRestoreDACRegisters(ScrnInfoPtr pScrn, - OUTREG(RADEON_DAC_CNTL2, restore->dac2_cntl); - - if ((info->ChipFamily != CHIP_FAMILY_RADEON) && -- (info->ChipFamily != CHIP_FAMILY_R200)) -+ (info->ChipFamily != CHIP_FAMILY_R200)) - OUTREG (RADEON_TV_DAC_CNTL, restore->tv_dac_cntl); - - OUTREG(RADEON_DISP_OUTPUT_CNTL, restore->disp_output_cntl); -@@ -103,6 +105,13 @@ RADEONRestoreFPRegisters(ScrnInfoPtr pScrn, RADEONSavePtr restore) - OUTREG(RADEON_TMDS_TRANSMITTER_CNTL,restore->tmds_transmitter_cntl); - OUTREG(RADEON_FP_GEN_CNTL, restore->fp_gen_cntl); - -+ if ((info->ChipFamily == CHIP_FAMILY_RS400) || -+ (info->ChipFamily == CHIP_FAMILY_RS480)) { -+ OUTREG(RS400_FP_2ND_GEN_CNTL, restore->fp_2nd_gen_cntl); -+ /*OUTREG(RS400_TMDS2_CNTL, restore->tmds2_cntl);*/ -+ OUTREG(RS400_TMDS2_TRANSMITTER_CNTL, restore->tmds2_transmitter_cntl); -+ } -+ - /* old AIW Radeon has some BIOS initialization problem - * with display buffer underflow, only occurs to DFP - */ -@@ -121,6 +130,9 @@ RADEONRestoreFP2Registers(ScrnInfoPtr pScrn, RADEONSavePtr restore) - - OUTREG(RADEON_FP2_GEN_CNTL, restore->fp2_gen_cntl); - -+ if ((info->ChipFamily == CHIP_FAMILY_RS400) || -+ (info->ChipFamily == CHIP_FAMILY_RS480)) -+ OUTREG(RS400_FP2_2_GEN_CNTL, restore->fp2_2_gen_cntl); - } - - /* Write RMX registers */ -@@ -203,10 +215,19 @@ RADEONSaveFPRegisters(ScrnInfoPtr pScrn, RADEONSavePtr save) - /* bit 22 of TMDS_PLL_CNTL is read-back inverted */ - save->tmds_pll_cntl ^= (1 << 22); - } -+ -+ if ((info->ChipFamily == CHIP_FAMILY_RS400) || -+ (info->ChipFamily == CHIP_FAMILY_RS480)) { -+ save->fp_2nd_gen_cntl = INREG(RS400_FP_2ND_GEN_CNTL); -+ save->fp2_2_gen_cntl = INREG(RS400_FP2_2_GEN_CNTL); -+ save->tmds2_cntl = INREG(RS400_TMDS2_CNTL); -+ save->tmds2_transmitter_cntl = INREG(RS400_TMDS2_TRANSMITTER_CNTL); -+ } -+ - } - - Bool --RADEONDVOReadByte(I2CDevPtr dvo, int addr, CARD8 *ch) -+RADEONDVOReadByte(I2CDevPtr dvo, int addr, uint8_t *ch) - { - if (!xf86I2CReadByte(dvo, addr, ch)) { - xf86DrvMsg(dvo->pI2CBus->scrnIndex, X_ERROR, -@@ -218,7 +239,7 @@ RADEONDVOReadByte(I2CDevPtr dvo, int addr, CARD8 *ch) - } - - Bool --RADEONDVOWriteByte(I2CDevPtr dvo, int addr, CARD8 ch) -+RADEONDVOWriteByte(I2CDevPtr dvo, int addr, uint8_t ch) - { - if (!xf86I2CWriteByte(dvo, addr, ch)) { - xf86DrvMsg(dvo->pI2CBus->scrnIndex, X_ERROR, -@@ -266,7 +287,7 @@ RADEONRestoreDVOChip(ScrnInfoPtr pScrn, xf86OutputPtr output) - - OUTREG(radeon_output->dvo_i2c.mask_clk_reg, - INREG(radeon_output->dvo_i2c.mask_clk_reg) & -- (CARD32)~(RADEON_GPIO_A_0 | RADEON_GPIO_A_1)); -+ (uint32_t)~(RADEON_GPIO_A_0 | RADEON_GPIO_A_1)); - - if (!RADEONInitExtTMDSInfoFromBIOS(output)) { - if (radeon_output->DVOChip) { -@@ -596,8 +617,8 @@ RADEONDacPowerSet(ScrnInfoPtr pScrn, Bool IsOn, Bool IsPrimaryDAC) - unsigned char *RADEONMMIO = info->MMIO; - - if (IsPrimaryDAC) { -- CARD32 dac_cntl; -- CARD32 dac_macro_cntl = 0; -+ uint32_t dac_cntl; -+ uint32_t dac_macro_cntl = 0; - dac_cntl = INREG(RADEON_DAC_CNTL); - dac_macro_cntl = INREG(RADEON_DAC_MACRO_CNTL); - if (IsOn) { -@@ -614,8 +635,8 @@ RADEONDacPowerSet(ScrnInfoPtr pScrn, Bool IsOn, Bool IsPrimaryDAC) - OUTREG(RADEON_DAC_CNTL, dac_cntl); - OUTREG(RADEON_DAC_MACRO_CNTL, dac_macro_cntl); - } else { -- CARD32 tv_dac_cntl; -- CARD32 fp2_gen_cntl; -+ uint32_t tv_dac_cntl; -+ uint32_t fp2_gen_cntl; - - switch(info->ChipFamily) - { -@@ -675,9 +696,9 @@ RADEONEnableDisplay(xf86OutputPtr output, BOOL bEnable) - unsigned long tmp; - RADEONOutputPrivatePtr radeon_output; - int tv_dac_change = 0, o; -- radeon_output = output->driver_private; - xf86CrtcConfigPtr xf86_config = XF86_CRTC_CONFIG_PTR(pScrn); - -+ radeon_output = output->driver_private; - for (o = 0; o < xf86_config->num_output; o++) { - if (output == xf86_config->output[o]) { - break; -@@ -685,7 +706,7 @@ RADEONEnableDisplay(xf86OutputPtr output, BOOL bEnable) - } - - if (bEnable) { -- ErrorF("enable montype: %d\n", radeon_output->MonType); -+ /*ErrorF("enable montype: %d\n", radeon_output->MonType);*/ - if (radeon_output->MonType == MT_CRT) { - if (radeon_output->DACType == DAC_PRIMARY) { - info->output_crt1 |= (1 << o); -@@ -716,6 +737,14 @@ RADEONEnableDisplay(xf86OutputPtr output, BOOL bEnable) - tmp |= (RADEON_FP_FPON | RADEON_FP_TMDS_EN); - OUTREG(RADEON_FP_GEN_CNTL, tmp); - save->fp_gen_cntl |= (RADEON_FP_FPON | RADEON_FP_TMDS_EN); -+ if ((info->ChipFamily == CHIP_FAMILY_RS400) || -+ (info->ChipFamily == CHIP_FAMILY_RS480)) { -+ tmp = INREG(RS400_FP_2ND_GEN_CNTL); -+ tmp |= (RS400_FP_2ND_ON | RS400_TMDS_2ND_EN); -+ OUTREG(RS400_FP_2ND_GEN_CNTL, tmp); -+ save->fp_2nd_gen_cntl |= (RS400_FP_2ND_ON | -+ RS400_TMDS_2ND_EN); -+ } - } else if (radeon_output->TMDSType == TMDS_EXT) { - info->output_dfp2 |= (1 << o); - tmp = INREG(RADEON_FP2_GEN_CNTL); -@@ -724,6 +753,15 @@ RADEONEnableDisplay(xf86OutputPtr output, BOOL bEnable) - OUTREG(RADEON_FP2_GEN_CNTL, tmp); - save->fp2_gen_cntl |= (RADEON_FP2_ON | RADEON_FP2_DVO_EN); - save->fp2_gen_cntl &= ~RADEON_FP2_BLANK_EN; -+ if ((info->ChipFamily == CHIP_FAMILY_RS400) || -+ (info->ChipFamily == CHIP_FAMILY_RS480)) { -+ tmp = INREG(RS400_FP2_2_GEN_CNTL); -+ tmp &= ~RS400_FP2_2_BLANK_EN; -+ tmp |= (RS400_FP2_2_ON | RS400_FP2_2_DVO2_EN); -+ OUTREG(RS400_FP2_2_GEN_CNTL, tmp); -+ save->fp2_2_gen_cntl |= (RS400_FP2_2_ON | RS400_FP2_2_DVO2_EN); -+ save->fp2_2_gen_cntl &= ~RS400_FP2_2_BLANK_EN; -+ } - } - } else if (radeon_output->MonType == MT_LCD) { - info->output_lcd1 |= (1 << o); -@@ -744,7 +782,7 @@ RADEONEnableDisplay(xf86OutputPtr output, BOOL bEnable) - radeon_output->tv_on = TRUE; - } - } else { -- ErrorF("disable montype: %d\n", radeon_output->MonType); -+ /*ErrorF("disable montype: %d\n", radeon_output->MonType);*/ - if (radeon_output->MonType == MT_CRT) { - if (radeon_output->DACType == DAC_PRIMARY) { - info->output_crt1 &= ~(1 << o); -@@ -780,6 +818,14 @@ RADEONEnableDisplay(xf86OutputPtr output, BOOL bEnable) - tmp &= ~(RADEON_FP_FPON | RADEON_FP_TMDS_EN); - OUTREG(RADEON_FP_GEN_CNTL, tmp); - save->fp_gen_cntl &= ~(RADEON_FP_FPON | RADEON_FP_TMDS_EN); -+ if ((info->ChipFamily == CHIP_FAMILY_RS400) || -+ (info->ChipFamily == CHIP_FAMILY_RS480)) { -+ tmp = INREG(RS400_FP_2ND_GEN_CNTL); -+ tmp &= ~(RS400_FP_2ND_ON | RS400_TMDS_2ND_EN); -+ OUTREG(RS400_FP_2ND_GEN_CNTL, tmp); -+ save->fp_2nd_gen_cntl &= ~(RS400_FP_2ND_ON | -+ RS400_TMDS_2ND_EN); -+ } - } - } else if (radeon_output->TMDSType == TMDS_EXT) { - info->output_dfp2 &= ~(1 << o); -@@ -790,6 +836,15 @@ RADEONEnableDisplay(xf86OutputPtr output, BOOL bEnable) - OUTREG(RADEON_FP2_GEN_CNTL, tmp); - save->fp2_gen_cntl &= ~(RADEON_FP2_ON | RADEON_FP2_DVO_EN); - save->fp2_gen_cntl |= RADEON_FP2_BLANK_EN; -+ if ((info->ChipFamily == CHIP_FAMILY_RS400) || -+ (info->ChipFamily == CHIP_FAMILY_RS480)) { -+ tmp = INREG(RS400_FP2_2_GEN_CNTL); -+ tmp |= RS400_FP2_2_BLANK_EN; -+ tmp &= ~(RS400_FP2_2_ON | RS400_FP2_2_DVO2_EN); -+ OUTREG(RS400_FP2_2_GEN_CNTL, tmp); -+ save->fp2_2_gen_cntl &= ~(RS400_FP2_2_ON | RS400_FP2_2_DVO2_EN); -+ save->fp2_2_gen_cntl |= RS400_FP2_2_BLANK_EN; -+ } - } - } - } else if (radeon_output->MonType == MT_LCD) { -@@ -862,11 +917,11 @@ RADEONInitFPRegisters(xf86OutputPtr output, RADEONSavePtr save, - RADEONEntPtr pRADEONEnt = RADEONEntPriv(pScrn); - RADEONOutputPrivatePtr radeon_output = output->driver_private; - int i; -- CARD32 tmp = info->SavedReg->tmds_pll_cntl & 0xfffff; -+ uint32_t tmp = info->SavedReg->tmds_pll_cntl & 0xfffff; - - for (i=0; i<4; i++) { - if (radeon_output->tmds_pll[i].freq == 0) break; -- if ((CARD32)(mode->Clock/10) < radeon_output->tmds_pll[i].freq) { -+ if ((uint32_t)(mode->Clock/10) < radeon_output->tmds_pll[i].freq) { - tmp = radeon_output->tmds_pll[i].value ; - break; - } -@@ -918,6 +973,30 @@ RADEONInitFPRegisters(xf86OutputPtr output, RADEONSavePtr save, - save->fp_gen_cntl |= RADEON_FP_SEL_CRTC2; - } - -+ if ((info->ChipFamily == CHIP_FAMILY_RS400) || -+ (info->ChipFamily == CHIP_FAMILY_RS480)) { -+ save->tmds2_transmitter_cntl = info->SavedReg->tmds2_transmitter_cntl & -+ ~(RS400_TMDS2_PLLRST); -+ save->tmds2_transmitter_cntl &= ~(RS400_TMDS2_PLLEN); -+ -+ save->fp_2nd_gen_cntl = info->SavedReg->fp_2nd_gen_cntl; -+ -+ if (pScrn->rgbBits == 8) -+ save->fp_2nd_gen_cntl |= RS400_PANEL_FORMAT_2ND; /* 24 bit format */ -+ else -+ save->fp_2nd_gen_cntl &= ~RS400_PANEL_FORMAT_2ND;/* 18 bit format */ -+ -+ save->fp_2nd_gen_cntl &= ~RS400_FP_2ND_SOURCE_SEL_MASK; -+ -+ if (IsPrimary) { -+ if (radeon_output->Flags & RADEON_USE_RMX) -+ save->fp_2nd_gen_cntl |= RS400_FP_2ND_SOURCE_SEL_RMX; -+ else -+ save->fp_2nd_gen_cntl |= RS400_FP_2ND_SOURCE_SEL_CRTC1; -+ } else -+ save->fp_2nd_gen_cntl |= RS400_FP_2ND_SOURCE_SEL_CRTC2; -+ } -+ - } - - static void -@@ -940,9 +1019,14 @@ RADEONInitFP2Registers(xf86OutputPtr output, RADEONSavePtr save, - RADEON_FP2_DVO_RATE_SEL_SDR); - - -- /* XXX: these may be oem specific */ -+ /* XXX: these are oem specific */ - if (IS_R300_VARIANT) { -- save->fp2_gen_cntl |= RADEON_FP2_PAD_FLOP_EN | R300_FP2_DVO_CLOCK_MODE_SINGLE; -+ if ((info->Chipset == PCI_CHIP_RV350_NP) && -+ (PCI_SUB_VENDOR_ID(info->PciInfo) == 0x1028) && -+ (PCI_SUB_DEVICE_ID(info->PciInfo) == 0x2001)) -+ save->fp2_gen_cntl |= R300_FP2_DVO_CLOCK_MODE_SINGLE; /* Dell Inspiron 8600 */ -+ else -+ save->fp2_gen_cntl |= RADEON_FP2_PAD_FLOP_EN | R300_FP2_DVO_CLOCK_MODE_SINGLE; - #if 0 - if (mode->Clock > 165000) - save->fp2_gen_cntl |= R300_FP2_DVO_DUAL_CHANNEL_EN; -@@ -954,6 +1038,8 @@ RADEONInitFP2Registers(xf86OutputPtr output, RADEONSavePtr save, - save->fp2_gen_cntl &= ~R200_FP2_SOURCE_SEL_MASK; - if (radeon_output->Flags & RADEON_USE_RMX) - save->fp2_gen_cntl |= R200_FP2_SOURCE_SEL_RMX; -+ else -+ save->fp2_gen_cntl |= R200_FP2_SOURCE_SEL_CRTC1; - } else { - save->fp2_gen_cntl &= ~RADEON_FP2_SRC_SEL_CRTC2; - } -@@ -966,6 +1052,28 @@ RADEONInitFP2Registers(xf86OutputPtr output, RADEONSavePtr save, - } - } - -+ if ((info->ChipFamily == CHIP_FAMILY_RS400) || -+ (info->ChipFamily == CHIP_FAMILY_RS480)) { -+ if (pScrn->rgbBits == 8) -+ save->fp2_2_gen_cntl = info->SavedReg->fp2_2_gen_cntl | -+ RS400_FP2_2_PANEL_FORMAT; /* 24 bit format, */ -+ else -+ save->fp2_2_gen_cntl = info->SavedReg->fp2_2_gen_cntl & -+ ~RS400_FP2_2_PANEL_FORMAT;/* 18 bit format, */ -+ -+ save->fp2_2_gen_cntl &= ~(RS400_FP2_2_ON | -+ RS400_FP2_2_DVO2_EN | -+ RS400_FP2_2_SOURCE_SEL_MASK); -+ -+ if (IsPrimary) { -+ if (radeon_output->Flags & RADEON_USE_RMX) -+ save->fp2_2_gen_cntl |= RS400_FP2_2_SOURCE_SEL_RMX; -+ else -+ save->fp2_2_gen_cntl |= RS400_FP2_2_SOURCE_SEL_CRTC1; -+ } else -+ save->fp2_2_gen_cntl |= RS400_FP2_2_SOURCE_SEL_CRTC2; -+ } -+ - } - - static void -@@ -1015,14 +1123,15 @@ RADEONInitRMXRegisters(xf86OutputPtr output, RADEONSavePtr save, - RADEONOutputPrivatePtr radeon_output = output->driver_private; - int xres = mode->HDisplay; - int yres = mode->VDisplay; -- float Hratio, Vratio; -+ Bool Hscale = TRUE, Vscale = TRUE; - int hsync_wid; - int vsync_wid; - int hsync_start; - - - save->fp_vert_stretch = info->SavedReg->fp_vert_stretch & -- RADEON_VERT_STRETCH_RESERVED; -+ (RADEON_VERT_STRETCH_RESERVED | -+ RADEON_VERT_AUTO_RATIO_INC); - save->fp_horz_stretch = info->SavedReg->fp_horz_stretch & - (RADEON_HORZ_FP_LOOP_STRETCH | - RADEON_HORZ_AUTO_RATIO_INC); -@@ -1069,34 +1178,41 @@ RADEONInitRMXRegisters(xf86OutputPtr output, RADEONSavePtr save, - return; - - if (radeon_output->PanelXRes == 0 || radeon_output->PanelYRes == 0) { -- Hratio = 1.0; -- Vratio = 1.0; -+ Hscale = FALSE; -+ Vscale = FALSE; - } else { - if (xres > radeon_output->PanelXRes) xres = radeon_output->PanelXRes; - if (yres > radeon_output->PanelYRes) yres = radeon_output->PanelYRes; - -- Hratio = (float)xres/(float)radeon_output->PanelXRes; -- Vratio = (float)yres/(float)radeon_output->PanelYRes; -+ if (xres == radeon_output->PanelXRes) -+ Hscale = FALSE; -+ if (yres == radeon_output->PanelYRes) -+ Vscale = FALSE; - } - -- if ((Hratio == 1.0) || (!(radeon_output->Flags & RADEON_USE_RMX)) || -+ if ((!Hscale) || (!(radeon_output->Flags & RADEON_USE_RMX)) || - (radeon_output->rmx_type == RMX_CENTER)) { - save->fp_horz_stretch |= ((xres/8-1)<<16); - } else { -- save->fp_horz_stretch |= ((((unsigned long) -- (Hratio * RADEON_HORZ_STRETCH_RATIO_MAX)) & -- RADEON_HORZ_STRETCH_RATIO_MASK) | -+ CARD32 scale, inc; -+ inc = (save->fp_horz_stretch & RADEON_HORZ_AUTO_RATIO_INC) ? 1 : 0; -+ scale = ((xres + inc) * RADEON_HORZ_STRETCH_RATIO_MAX) -+ / radeon_output->PanelXRes + 1; -+ save->fp_horz_stretch |= (((scale) & RADEON_HORZ_STRETCH_RATIO_MASK) | - RADEON_HORZ_STRETCH_BLEND | - RADEON_HORZ_STRETCH_ENABLE | - ((radeon_output->PanelXRes/8-1)<<16)); - } - -- if ((Vratio == 1.0) || (!(radeon_output->Flags & RADEON_USE_RMX)) || -+ if ((!Vscale) || (!(radeon_output->Flags & RADEON_USE_RMX)) || - (radeon_output->rmx_type == RMX_CENTER)) { - save->fp_vert_stretch |= ((yres-1)<<12); - } else { -- save->fp_vert_stretch |= ((((unsigned long)(Vratio * RADEON_VERT_STRETCH_RATIO_MAX)) & -- RADEON_VERT_STRETCH_RATIO_MASK) | -+ CARD32 scale, inc; -+ inc = (save->fp_vert_stretch & RADEON_VERT_AUTO_RATIO_INC) ? 1 : 0; -+ scale = ((yres + inc) * RADEON_VERT_STRETCH_RATIO_MAX) -+ / radeon_output->PanelYRes + 1; -+ save->fp_vert_stretch |= (((scale) & RADEON_VERT_STRETCH_RATIO_MASK) | - RADEON_VERT_STRETCH_ENABLE | - RADEON_VERT_STRETCH_BLEND | - ((radeon_output->PanelYRes-1)<<12)); -@@ -1310,7 +1426,7 @@ legacy_output_mode_set(xf86OutputPtr output, DisplayModePtr mode, - ErrorF("restore FP2\n"); - if (info->IsAtomBios) { - unsigned char *RADEONMMIO = info->MMIO; -- CARD32 fp2_gen_cntl; -+ uint32_t fp2_gen_cntl; - - atombios_external_tmds_setup(output, mode); - /* r4xx atom has hard coded crtc mappings in the atom code -@@ -1354,8 +1470,8 @@ radeon_detect_primary_dac(ScrnInfoPtr pScrn, Bool color) - { - RADEONInfoPtr info = RADEONPTR(pScrn); - unsigned char *RADEONMMIO = info->MMIO; -- CARD32 vclk_ecp_cntl, crtc_ext_cntl; -- CARD32 dac_ext_cntl, dac_cntl, dac_macro_cntl, tmp; -+ uint32_t vclk_ecp_cntl, crtc_ext_cntl; -+ uint32_t dac_ext_cntl, dac_cntl, dac_macro_cntl, tmp; - RADEONMonitorType found = MT_NONE; - - /* save the regs we need */ -@@ -1421,11 +1537,11 @@ radeon_detect_ext_dac(ScrnInfoPtr pScrn) - { - RADEONInfoPtr info = RADEONPTR(pScrn); - unsigned char *RADEONMMIO = info->MMIO; -- CARD32 gpio_monid, fp2_gen_cntl, disp_output_cntl, crtc2_gen_cntl; -- CARD32 disp_lin_trans_grph_a, disp_lin_trans_grph_b, disp_lin_trans_grph_c; -- CARD32 disp_lin_trans_grph_d, disp_lin_trans_grph_e, disp_lin_trans_grph_f; -- CARD32 tmp, crtc2_h_total_disp, crtc2_v_total_disp; -- CARD32 crtc2_h_sync_strt_wid, crtc2_v_sync_strt_wid; -+ uint32_t gpio_monid, fp2_gen_cntl, disp_output_cntl, crtc2_gen_cntl; -+ uint32_t disp_lin_trans_grph_a, disp_lin_trans_grph_b, disp_lin_trans_grph_c; -+ uint32_t disp_lin_trans_grph_d, disp_lin_trans_grph_e, disp_lin_trans_grph_f; -+ uint32_t tmp, crtc2_h_total_disp, crtc2_v_total_disp; -+ uint32_t crtc2_h_sync_strt_wid, crtc2_v_sync_strt_wid; - RADEONMonitorType found = MT_NONE; - int connected = 0; - int i = 0; -@@ -1517,8 +1633,8 @@ radeon_detect_tv_dac(ScrnInfoPtr pScrn, Bool color) - { - RADEONInfoPtr info = RADEONPTR(pScrn); - unsigned char *RADEONMMIO = info->MMIO; -- CARD32 crtc2_gen_cntl, tv_dac_cntl, dac_cntl2, dac_ext_cntl; -- CARD32 disp_hw_debug, disp_output_cntl, gpiopad_a, pixclks_cntl, tmp; -+ uint32_t crtc2_gen_cntl, tv_dac_cntl, dac_cntl2, dac_ext_cntl; -+ uint32_t disp_hw_debug, disp_output_cntl, gpiopad_a, pixclks_cntl, tmp; - RADEONMonitorType found = MT_NONE; - - /* save the regs we need */ -@@ -1619,8 +1735,8 @@ r300_detect_tv(ScrnInfoPtr pScrn) - { - RADEONInfoPtr info = RADEONPTR(pScrn); - unsigned char *RADEONMMIO = info->MMIO; -- CARD32 tmp, dac_cntl2, crtc2_gen_cntl, dac_ext_cntl, tv_dac_cntl; -- CARD32 gpiopad_a, disp_output_cntl; -+ uint32_t tmp, dac_cntl2, crtc2_gen_cntl, dac_ext_cntl, tv_dac_cntl; -+ uint32_t gpiopad_a, disp_output_cntl; - RADEONMonitorType found = MT_NONE; - - /* save the regs we need */ -@@ -1695,8 +1811,8 @@ radeon_detect_tv(ScrnInfoPtr pScrn) - { - RADEONInfoPtr info = RADEONPTR(pScrn); - unsigned char *RADEONMMIO = info->MMIO; -- CARD32 tmp, dac_cntl2, tv_master_cntl; -- CARD32 tv_dac_cntl, tv_pre_dac_mux_cntl, config_cntl; -+ uint32_t tmp, dac_cntl2, tv_master_cntl; -+ uint32_t tv_dac_cntl, tv_pre_dac_mux_cntl, config_cntl; - RADEONMonitorType found = MT_NONE; - - if (IS_R300_VARIANT) -diff --git a/src/pcidb/ati_pciids.csv b/src/pcidb/ati_pciids.csv -index 5a2191a..364f4e1 100644 ---- a/src/pcidb/ati_pciids.csv -+++ b/src/pcidb/ati_pciids.csv -@@ -1,5 +1,6 @@ - "#pciid","define","family","mobility","igp","nocrtc2","Nointtvout","singledac","name" - "0x3150","RV380_3150","RV380",1,,,,,"ATI Radeon Mobility X600 (M24) 3150 (PCIE)" -+"0x3151","RV380_3151","RV380",,,,,,"ATI FireMV 2400 (PCI)" - "0x3152","RV380_3152","RV380",1,,,,,"ATI Radeon Mobility X300 (M24) 3152 (PCIE)" - "0x3154","RV380_3154","RV380",1,,,,,"ATI FireGL M24 GL 3154 (PCIE)" - "0x3E50","RV380_3E50","RV380",,,,,,"ATI Radeon X600 (RV380) 3E50 (PCIE)" -@@ -174,21 +175,22 @@ - "0x564F","RV410_564F","RV410",1,,,,,"ATI Mobility Radeon X700 XL (M26) (PCIE)" - "0x5652","RV410_5652","RV410",1,,,,,"ATI Mobility Radeon X700 (M26) (PCIE)" - "0x5653","RV410_5653","RV410",1,,,,,"ATI Mobility Radeon X700 (M26) (PCIE)" -+"0x5657","RV410_5657","RV410",,,,,,"ATI Radeon X550XTX 5657 (PCIE)" - "0x5654","MACH64VT","MACH64",,,,,, - "0x5655","MACH64VU","MACH64",,,,,, - "0x5656","MACH64VV","MACH64",,,,,, - "0x5834","RS300_5834","RS300",,1,,,1,"ATI Radeon 9100 IGP (A5) 5834" - "0x5835","RS300_5835","RS300",1,1,,,1,"ATI Radeon Mobility 9100 IGP (U3) 5835" --"0x5954","RS480_5954","RS400",,1,,,1,"ATI Radeon XPRESS 200 5954 (PCIE)" --"0x5955","RS480_5955","RS400",1,1,,,1,"ATI Radeon XPRESS 200M 5955 (PCIE)" -+"0x5954","RS480_5954","RS480",,1,,,1,"ATI Radeon XPRESS 200 5954 (PCIE)" -+"0x5955","RS480_5955","RS480",1,1,,,1,"ATI Radeon XPRESS 200M 5955 (PCIE)" - "0x5960","RV280_5960","RV280",,,,,,"ATI Radeon 9250 5960 (AGP)" - "0x5961","RV280_5961","RV280",,,,,,"ATI Radeon 9200 5961 (AGP)" - "0x5962","RV280_5962","RV280",,,,,,"ATI Radeon 9200 5962 (AGP)" - "0x5964","RV280_5964","RV280",,,,,,"ATI Radeon 9200SE 5964 (AGP)" - "0x5965","RV280_5965","RV280",,,,,,"ATI FireMV 2200 (PCI)" - "0x5969","RN50_5969","RV100",,,1,,,"ATI ES1000 5969 (PCI)" --"0x5974","RS482_5974","RS400",,1,,,1,"ATI Radeon XPRESS 200 5974 (PCIE)" --"0x5975","RS485_5975","RS400",1,1,,,1,"ATI Radeon XPRESS 200M 5975 (PCIE)" -+"0x5974","RS482_5974","RS480",1,1,,,1,"ATI Radeon XPRESS 200 5974 (PCIE)" -+"0x5975","RS485_5975","RS480",1,1,,,1,"ATI Radeon XPRESS 200M 5975 (PCIE)" - "0x5A41","RS400_5A41","RS400",,1,,,1,"ATI Radeon XPRESS 200 5A41 (PCIE)" - "0x5A42","RS400_5A42","RS400",1,1,,,1,"ATI Radeon XPRESS 200M 5A42 (PCIE)" - "0x5A61","RC410_5A61","RS400",,1,,,1,"ATI Radeon XPRESS 200 5A61 (PCIE)" -@@ -196,7 +198,6 @@ - "0x5B60","RV370_5B60","RV380",,,,,,"ATI Radeon X300 (RV370) 5B60 (PCIE)" - "0x5B62","RV370_5B62","RV380",,,,,,"ATI Radeon X600 (RV370) 5B62 (PCIE)" - "0x5B63","RV370_5B63","RV380",,,,,,"ATI Radeon X550 (RV370) 5B63 (PCIE)" --"0x5657","RV370_5657","RV380",,,,,,"ATI Radeon X550XTX (RV370) 5657 (PCIE)" - "0x5B64","RV370_5B64","RV380",,,,,,"ATI FireGL V3100 (RV370) 5B64 (PCIE)" - "0x5B65","RV370_5B65","RV380",,,,,,"ATI FireMV 2200 PCIE (RV370) 5B65 (PCIE)" - "0x5C61","RV280_5C61","RV280",1,,,,,"ATI Radeon Mobility 9200 (M9+) 5C61 (AGP)" -@@ -282,9 +283,9 @@ - "0x71D6","RV530_71D6","RV530",1,,,,,"ATI Mobility Radeon X1700 XT" - "0x71DA","RV530_71DA","RV530",,,,,,"ATI FireGL V5200" - "0x71DE","RV530_71DE","RV530",1,,,,,"ATI Mobility Radeon X1700" --"0x7200","RV530_7200","RV530",,,,,,"ATI Radeon X2300HD" --"0x7210","RV530_7210","RV530",1,,,,,"ATI Mobility Radeon HD 2300" --"0x7211","RV530_7211","RV530",1,,,,,"ATI Mobility Radeon HD 2300" -+"0x7200","RV515_7200","RV515",,,,,,"ATI Radeon X2300HD" -+"0x7210","RV515_7210","RV515",1,,,,,"ATI Mobility Radeon HD 2300" -+"0x7211","RV515_7211","RV515",1,,,,,"ATI Mobility Radeon HD 2300" - "0x7240","R580_7240","R580",,,,,,"ATI Radeon X1950" - "0x7243","R580_7243","R580",,,,,,"ATI Radeon X1900" - "0x7244","R580_7244","R580",,,,,,"ATI Radeon X1950" -@@ -316,6 +317,9 @@ - "0x7835","RS350_7835","RS300",1,1,,,1,"ATI Radeon Mobility 9200 IGP 7835" - "0x791E","RS690_791E","RS690",,1,,,1,"ATI Radeon X1200" - "0x791F","RS690_791F","RS690",,1,,,1,"ATI Radeon X1200" -+"0x793F","RS600_793F","RS600",,1,,,1,"ATI Radeon X1200" -+"0x7941","RS600_7941","RS600",,1,,,1,"ATI Radeon X1200" -+"0x7942","RS600_7942","RS600",,1,,,1,"ATI Radeon X1200" - "0x796C","RS740_796C","RS740",,1,,,1,"ATI RS740" - "0x796D","RS740_796D","RS740",,1,,,1,"ATI RS740M" - "0x796E","RS740_796E","RS740",,1,,,1,"ATI RS740" -@@ -328,16 +332,18 @@ - "0x940A","R600_940A","R600",,,,,,"ATI FireGL V8650" - "0x940B","R600_940B","R600",,,,,,"ATI FireGL V8600" - "0x940F","R600_940F","R600",,,,,,"ATI FireGL V7600" -+"0x9440","RV770_9440","RV770",,,,,,"ATI Radeon 4800 Series" -+"0x9442","RV770_9442","RV770",,,,,,"ATI Radeon 4800 Series" - "0x94C0","RV610_94C0","RV610",,,,,,"ATI RV610" - "0x94C1","RV610_94C1","RV610",,,,,,"ATI Radeon HD 2400 XT" - "0x94C3","RV610_94C3","RV610",,,,,,"ATI Radeon HD 2400 Pro" --"0x94C4","RV610_94C4","RV610",,,,,,"ATI ATI Radeon HD 2400 PRO AGP" -+"0x94C4","RV610_94C4","RV610",,,,,,"ATI Radeon HD 2400 PRO AGP" - "0x94C5","RV610_94C5","RV610",,,,,,"ATI FireGL V4000" - "0x94C6","RV610_94C6","RV610",,,,,,"ATI RV610" - "0x94C7","RV610_94C7","RV610",,,,,,"ATI ATI Radeon HD 2350" - "0x94C8","RV610_94C8","RV610",1,,,,,"ATI Mobility Radeon HD 2400 XT" - "0x94C9","RV610_94C9","RV610",1,,,,,"ATI Mobility Radeon HD 2400" --"0x94CB","RV610_94CB","RV610",1,,,,,"ATI ATI RADEON E2400" -+"0x94CB","RV610_94CB","RV610",1,,,,,"ATI RADEON E2400" - "0x94CC","RV610_94CC","RV610",,,,,,"ATI RV610" - "0x9500","RV670_9500","RV670",,,,,,"ATI RV670" - "0x9501","RV670_9501","RV670",,,,,,"ATI Radeon HD3870" -@@ -345,15 +351,35 @@ - "0x9507","RV670_9507","RV670",,,,,,"ATI RV670" - "0x950F","RV670_950F","RV670",,,,,,"ATI Radeon HD3870 X2" - "0x9511","RV670_9511","RV670",,,,,,"ATI FireGL V7700" -+"0x9515","RV670_9515","RV670",,,,,,"ATI Radeon HD3850" - "0x9580","RV630_9580","RV630",,,,,,"ATI RV630" - "0x9581","RV630_9581","RV630",1,,,,,"ATI Mobility Radeon HD 2600" - "0x9583","RV630_9583","RV630",1,,,,,"ATI Mobility Radeon HD 2600 XT" --"0x9586","RV630_9586","RV630",,,,,,"ATI ATI Radeon HD 2600 XT AGP" --"0x9587","RV630_9587","RV630",,,,,,"ATI ATI Radeon HD 2600 Pro AGP" -+"0x9586","RV630_9586","RV630",,,,,,"ATI Radeon HD 2600 XT AGP" -+"0x9587","RV630_9587","RV630",,,,,,"ATI Radeon HD 2600 Pro AGP" - "0x9588","RV630_9588","RV630",,,,,,"ATI Radeon HD 2600 XT" - "0x9589","RV630_9589","RV630",,,,,,"ATI Radeon HD 2600 Pro" - "0x958A","RV630_958A","RV630",,,,,,"ATI Gemini RV630" --"0x958B","RV630_958B","RV630",1,,,,,"ATI Gemini ATI Mobility Radeon HD 2600 XT" -+"0x958B","RV630_958B","RV630",1,,,,,"ATI Gemini Mobility Radeon HD 2600 XT" - "0x958C","RV630_958C","RV630",,,,,,"ATI FireGL V5600" - "0x958D","RV630_958D","RV630",,,,,,"ATI FireGL V3600" --"0x958E","RV630_958E","RV630",,,,,,"ATI ATI Radeon HD 2600 LE" -+"0x958E","RV630_958E","RV630",,,,,,"ATI Radeon HD 2600 LE" -+"0x95C0","RV620_95C0","RV620",,,,,,"ATI Radeon HD 3470" -+"0x95C5","RV620_95C5","RV620",,,,,,"ATI Radeon HD 3450" -+"0x95C7","RV620_95C7","RV620",,,,,,"ATI Radeon HD 3430" -+"0x95C2","RV620_95C2","RV620",1,,,,,"ATI Mobility Radeon HD 3430" -+"0x95C4","RV620_95C4","RV620",1,,,,,"ATI Mobility Radeon HD 3400 Series" -+"0x95CD","RV620_95CD","RV620",,,,,,"ATI FireMV 2450" -+"0x95CE","RV620_95CE","RV620",,,,,,"ATI FireMV 2260" -+"0x95CF","RV620_95CF","RV620",,,,,,"ATI FireMV 2260" -+"0x9590","RV635_9590","RV635",,,,,,"ATI ATI Radeon HD 3600 Series" -+"0x9596","RV635_9596","RV635",,,,,,"ATI ATI Radeon HD 3650 AGP" -+"0x9597","RV635_9597","RV635",,,,,,"ATI ATI Radeon HD 3600 PRO" -+"0x9598","RV635_9598","RV635",,,,,,"ATI ATI Radeon HD 3600 XT" -+"0x9599","RV635_9599","RV635",,,,,,"ATI ATI Radeon HD 3600 PRO" -+"0x9591","RV635_9591","RV635",1,,,,,"ATI Mobility Radeon HD 3650" -+"0x9593","RV635_9593","RV635",1,,,,,"ATI Mobility Radeon HD 3670" -+"0x9610","RS780_9610","RS780",,1,,,1,"ATI Radeon HD 3200 Graphics" -+"0x9611","RS780_9611","RS780",,1,,,1,"ATI Radeon 3100 Graphics" -+"0x9612","RS780_9612","RS780",,1,,,1,"ATI Radeon HD 3200 Graphics" -+"0x9613","RS780_9613","RS780",,1,,,1,"ATI Radeon 3100 Graphics" -diff --git a/src/radeon.h b/src/radeon.h -index aba3c0f..8f25fdf 100644 ---- a/src/radeon.h -+++ b/src/radeon.h -@@ -98,6 +98,41 @@ - #define MIN(a,b) ((a)>(b)?(b):(a)) - #endif - -+#if HAVE_BYTESWAP_H -+#include -+#elif defined(USE_SYS_ENDIAN_H) -+#include -+#else -+#define bswap_16(value) \ -+ ((((value) & 0xff) << 8) | ((value) >> 8)) -+ -+#define bswap_32(value) \ -+ (((uint32_t)bswap_16((uint16_t)((value) & 0xffff)) << 16) | \ -+ (uint32_t)bswap_16((uint16_t)((value) >> 16))) -+ -+#define bswap_64(value) \ -+ (((uint64_t)bswap_32((uint32_t)((value) & 0xffffffff)) \ -+ << 32) | \ -+ (uint64_t)bswap_32((uint32_t)((value) >> 32))) -+#endif -+ -+#if X_BYTE_ORDER == X_BIG_ENDIAN -+#define le32_to_cpu(x) bswap_32(x) -+#define le16_to_cpu(x) bswap_16(x) -+#define cpu_to_le32(x) bswap_32(x) -+#define cpu_to_le16(x) bswap_16(x) -+#else -+#define le32_to_cpu(x) (x) -+#define le16_to_cpu(x) (x) -+#define cpu_to_le32(x) (x) -+#define cpu_to_le16(x) (x) -+#endif -+ -+/* Provide substitutes for gcc's __FUNCTION__ on other compilers */ -+#if !defined(__GNUC__) && !defined(__FUNCTION__) -+# define __FUNCTION__ __func__ /* C99 */ -+#endif -+ - #ifndef HAVE_XF86MODEBANDWIDTH - extern unsigned int xf86ModeBandwidth(DisplayModePtr mode, int depth); - #define MODE_BANDWIDTH MODE_BAD -@@ -167,7 +202,9 @@ typedef enum { - OPTION_TVDAC_LOAD_DETECT, - OPTION_FORCE_TVOUT, - OPTION_TVSTD, -- OPTION_IGNORE_LID_STATUS -+ OPTION_IGNORE_LID_STATUS, -+ OPTION_DEFAULT_TVDAC_ADJ, -+ OPTION_INT10 - } RADEONOpts; - - -@@ -198,38 +235,39 @@ typedef enum { - - typedef struct { - int revision; -- CARD16 rr1_offset; -- CARD16 rr2_offset; -- CARD16 dyn_clk_offset; -- CARD16 pll_offset; -- CARD16 mem_config_offset; -- CARD16 mem_reset_offset; -- CARD16 short_mem_offset; -- CARD16 rr3_offset; -- CARD16 rr4_offset; -+ uint16_t rr1_offset; -+ uint16_t rr2_offset; -+ uint16_t dyn_clk_offset; -+ uint16_t pll_offset; -+ uint16_t mem_config_offset; -+ uint16_t mem_reset_offset; -+ uint16_t short_mem_offset; -+ uint16_t rr3_offset; -+ uint16_t rr4_offset; - } RADEONBIOSInitTable; - - #define RADEON_PLL_USE_BIOS_DIVS (1 << 0) - #define RADEON_PLL_NO_ODD_POST_DIV (1 << 1) - #define RADEON_PLL_USE_REF_DIV (1 << 2) - #define RADEON_PLL_LEGACY (1 << 3) -+#define RADEON_PLL_PREFER_LOW_REF_DIV (1 << 4) - - typedef struct { -- CARD16 reference_freq; -- CARD16 reference_div; -- CARD32 pll_in_min; -- CARD32 pll_in_max; -- CARD32 pll_out_min; -- CARD32 pll_out_max; -- CARD16 xclk; -- -- CARD32 min_ref_div; -- CARD32 max_ref_div; -- CARD32 min_post_div; -- CARD32 max_post_div; -- CARD32 min_feedback_div; -- CARD32 max_feedback_div; -- CARD32 best_vco; -+ uint16_t reference_freq; -+ uint16_t reference_div; -+ uint32_t pll_in_min; -+ uint32_t pll_in_max; -+ uint32_t pll_out_min; -+ uint32_t pll_out_max; -+ uint16_t xclk; -+ -+ uint32_t min_ref_div; -+ uint32_t max_ref_div; -+ uint32_t min_post_div; -+ uint32_t max_post_div; -+ uint32_t min_feedback_div; -+ uint32_t max_feedback_div; -+ uint32_t best_vco; - } RADEONPLLRec, *RADEONPLLPtr; - - typedef struct { -@@ -260,20 +298,26 @@ typedef enum { - CHIP_FAMILY_RV380, /* RV370/RV380/M22/M24 */ - CHIP_FAMILY_R420, /* R420/R423/M18 */ - CHIP_FAMILY_RV410, /* RV410, M26 */ -- CHIP_FAMILY_RS400, /* xpress 200, 200m (RS400/410/480) */ -+ CHIP_FAMILY_RS400, /* xpress 200, 200m (RS400) Intel */ -+ CHIP_FAMILY_RS480, /* xpress 200, 200m (RS410/480/482/485) AMD */ - CHIP_FAMILY_RV515, /* rv515 */ - CHIP_FAMILY_R520, /* r520 */ - CHIP_FAMILY_RV530, /* rv530 */ - CHIP_FAMILY_R580, /* r580 */ - CHIP_FAMILY_RV560, /* rv560 */ - CHIP_FAMILY_RV570, /* rv570 */ -+ CHIP_FAMILY_RS600, - CHIP_FAMILY_RS690, -- CHIP_FAMILY_R600, /* r60 */ -+ CHIP_FAMILY_RS740, -+ CHIP_FAMILY_R600, /* r600 */ - CHIP_FAMILY_R630, - CHIP_FAMILY_RV610, - CHIP_FAMILY_RV630, - CHIP_FAMILY_RV670, -- CHIP_FAMILY_RS740, -+ CHIP_FAMILY_RV620, -+ CHIP_FAMILY_RV635, -+ CHIP_FAMILY_RS780, -+ CHIP_FAMILY_RV770, - CHIP_FAMILY_LAST - } RADEONChipFamily; - -@@ -292,10 +336,32 @@ typedef enum { - (info->ChipFamily == CHIP_FAMILY_RV380) || \ - (info->ChipFamily == CHIP_FAMILY_R420) || \ - (info->ChipFamily == CHIP_FAMILY_RV410) || \ -- (info->ChipFamily == CHIP_FAMILY_RS400)) -+ (info->ChipFamily == CHIP_FAMILY_RS400) || \ -+ (info->ChipFamily == CHIP_FAMILY_RS480)) - - #define IS_AVIVO_VARIANT ((info->ChipFamily >= CHIP_FAMILY_RV515)) - -+#define IS_DCE3_VARIANT ((info->ChipFamily >= CHIP_FAMILY_RV620)) -+ -+#define IS_R500_3D ((info->ChipFamily == CHIP_FAMILY_RV515) || \ -+ (info->ChipFamily == CHIP_FAMILY_R520) || \ -+ (info->ChipFamily == CHIP_FAMILY_RV530) || \ -+ (info->ChipFamily == CHIP_FAMILY_R580) || \ -+ (info->ChipFamily == CHIP_FAMILY_RV560) || \ -+ (info->ChipFamily == CHIP_FAMILY_RV570)) -+ -+#define IS_R300_3D ((info->ChipFamily == CHIP_FAMILY_R300) || \ -+ (info->ChipFamily == CHIP_FAMILY_RV350) || \ -+ (info->ChipFamily == CHIP_FAMILY_R350) || \ -+ (info->ChipFamily == CHIP_FAMILY_RV380) || \ -+ (info->ChipFamily == CHIP_FAMILY_R420) || \ -+ (info->ChipFamily == CHIP_FAMILY_RV410) || \ -+ (info->ChipFamily == CHIP_FAMILY_RS690) || \ -+ (info->ChipFamily == CHIP_FAMILY_RS600) || \ -+ (info->ChipFamily == CHIP_FAMILY_RS740) || \ -+ (info->ChipFamily == CHIP_FAMILY_RS400) || \ -+ (info->ChipFamily == CHIP_FAMILY_RS480)) -+ - /* - * Errata workarounds - */ -@@ -333,7 +399,7 @@ typedef enum { - typedef struct _atomBiosHandle *atomBiosHandlePtr; - - typedef struct { -- CARD32 pci_device_id; -+ uint32_t pci_device_id; - RADEONChipFamily chip_family; - int mobility; - int igp; -@@ -353,22 +419,22 @@ typedef struct { - unsigned long LinearAddr; /* Frame buffer physical address */ - unsigned long MMIOAddr; /* MMIO region physical address */ - unsigned long BIOSAddr; /* BIOS physical address */ -- CARD32 fbLocation; -- CARD32 gartLocation; -- CARD32 mc_fb_location; -- CARD32 mc_agp_location; -- CARD32 mc_agp_location_hi; -+ uint32_t fbLocation; -+ uint32_t gartLocation; -+ uint32_t mc_fb_location; -+ uint32_t mc_agp_location; -+ uint32_t mc_agp_location_hi; - - void *MMIO; /* Map of MMIO region */ - void *FB; /* Map of frame buffer */ -- CARD8 *VBIOS; /* Video BIOS pointer */ -+ uint8_t *VBIOS; /* Video BIOS pointer */ - - Bool IsAtomBios; /* New BIOS used in R420 etc. */ - int ROMHeaderStart; /* Start of the ROM Info Table */ - int MasterDataStart; /* Offset for Master Data Table for ATOM BIOS */ - -- CARD32 MemCntl; -- CARD32 BusCntl; -+ uint32_t MemCntl; -+ uint32_t BusCntl; - unsigned long MMIOSize; /* MMIO region physical address */ - unsigned long FbMapSize; /* Size of frame buffer, in bytes */ - unsigned long FbSecureSize; /* Size of secured fb area at end of -@@ -448,9 +514,9 @@ typedef struct { - /* Computed values for Radeon */ - int pitch; - int datatype; -- CARD32 dp_gui_master_cntl; -- CARD32 dp_gui_master_cntl_clip; -- CARD32 trans_color; -+ uint32_t dp_gui_master_cntl; -+ uint32_t dp_gui_master_cntl_clip; -+ uint32_t trans_color; - - /* Saved values for ScreenToScreenCopy */ - int xdir; -@@ -476,7 +542,7 @@ typedef struct { - #endif - /* Saved values for DashedTwoPointLine */ - int dashLen; -- CARD32 dashPattern; -+ uint32_t dashPattern; - int dash_fg; - int dash_bg; - -@@ -487,7 +553,7 @@ typedef struct { - DGAFunctionRec DGAFuncs; - - RADEONFBLayout CurrentLayout; -- CARD32 dst_pitch_offset; -+ uint32_t dst_pitch_offset; - #ifdef XF86DRI - Bool noBackBuffer; - Bool directRenderingEnabled; -@@ -502,14 +568,14 @@ typedef struct { - RADEONConfigPrivPtr pVisualConfigsPriv; - Bool (*DRICloseScreen)(int, ScreenPtr); - -- drm_handle_t fbHandle; -+ drm_handle_t fbHandle; - - drmSize registerSize; -- drm_handle_t registerHandle; -+ drm_handle_t registerHandle; - - RADEONCardType cardType; /* Current card is a PCI card */ - drmSize pciSize; -- drm_handle_t pciMemHandle; -+ drm_handle_t pciMemHandle; - unsigned char *PCI; /* Map */ - - Bool depthMoves; /* Enable depth moves -- slow! */ -@@ -522,37 +588,36 @@ typedef struct { - - int pciAperSize; - drmSize gartSize; -- drm_handle_t agpMemHandle; /* Handle from drmAgpAlloc */ -+ drm_handle_t agpMemHandle; /* Handle from drmAgpAlloc */ - unsigned long gartOffset; - unsigned char *AGP; /* Map */ - int agpMode; - -- CARD32 pciCommand; -+ uint32_t pciCommand; - - Bool CPRuns; /* CP is running */ - Bool CPInUse; /* CP has been used by X server */ - Bool CPStarted; /* CP has started */ -- int CPMode; /* CP mode that server/clients use */ - int CPFifoSize; /* Size of the CP command FIFO */ - int CPusecTimeout; /* CP timeout in usecs */ - Bool needCacheFlush; - - /* CP ring buffer data */ - unsigned long ringStart; /* Offset into GART space */ -- drm_handle_t ringHandle; /* Handle from drmAddMap */ -+ drm_handle_t ringHandle; /* Handle from drmAddMap */ - drmSize ringMapSize; /* Size of map */ - int ringSize; /* Size of ring (in MB) */ - drmAddress ring; /* Map */ - int ringSizeLog2QW; - - unsigned long ringReadOffset; /* Offset into GART space */ -- drm_handle_t ringReadPtrHandle; /* Handle from drmAddMap */ -+ drm_handle_t ringReadPtrHandle; /* Handle from drmAddMap */ - drmSize ringReadMapSize; /* Size of map */ - drmAddress ringReadPtr; /* Map */ - - /* CP vertex/indirect buffer data */ - unsigned long bufStart; /* Offset into GART space */ -- drm_handle_t bufHandle; /* Handle from drmAddMap */ -+ drm_handle_t bufHandle; /* Handle from drmAddMap */ - drmSize bufMapSize; /* Size of map */ - int bufSize; /* Size of buffers (in MB) */ - drmAddress buf; /* Map */ -@@ -561,7 +626,7 @@ typedef struct { - - /* CP GART Texture data */ - unsigned long gartTexStart; /* Offset into GART space */ -- drm_handle_t gartTexHandle; /* Handle from drmAddMap */ -+ drm_handle_t gartTexHandle; /* Handle from drmAddMap */ - drmSize gartTexMapSize; /* Size of map */ - int gartTexSize; /* Size of GART tex space (in MB) */ - drmAddress gartTex; /* Map */ -@@ -591,12 +656,12 @@ typedef struct { - int log2TexGran; - - int pciGartSize; -- CARD32 pciGartOffset; -+ uint32_t pciGartOffset; - void *pciGartBackup; - #ifdef USE_XAA -- CARD32 frontPitchOffset; -- CARD32 backPitchOffset; -- CARD32 depthPitchOffset; -+ uint32_t frontPitchOffset; -+ uint32_t backPitchOffset; -+ uint32_t depthPitchOffset; - - /* offscreen memory management */ - int backLines; -@@ -606,15 +671,15 @@ typedef struct { - #endif - - /* Saved scissor values */ -- CARD32 sc_left; -- CARD32 sc_right; -- CARD32 sc_top; -- CARD32 sc_bottom; -+ uint32_t sc_left; -+ uint32_t sc_right; -+ uint32_t sc_top; -+ uint32_t sc_bottom; - -- CARD32 re_top_left; -- CARD32 re_width_height; -+ uint32_t re_top_left; -+ uint32_t re_width_height; - -- CARD32 aux_sc_cntl; -+ uint32_t aux_sc_cntl; - - int irq; - -@@ -639,22 +704,22 @@ typedef struct { - int RageTheatreCompositePort; - int RageTheatreSVideoPort; - int tunerType; -- char* RageTheatreMicrocPath; -- char* RageTheatreMicrocType; -- Bool MM_TABLE_valid; -+ char* RageTheatreMicrocPath; -+ char* RageTheatreMicrocType; -+ Bool MM_TABLE_valid; - struct { -- CARD8 table_revision; -- CARD8 table_size; -- CARD8 tuner_type; -- CARD8 audio_chip; -- CARD8 product_id; -- CARD8 tuner_voltage_teletext_fm; -- CARD8 i2s_config; /* configuration of the sound chip */ -- CARD8 video_decoder_type; -- CARD8 video_decoder_host_config; -- CARD8 input[5]; -- } MM_TABLE; -- CARD16 video_decoder_type; -+ uint8_t table_revision; -+ uint8_t table_size; -+ uint8_t tuner_type; -+ uint8_t audio_chip; -+ uint8_t product_id; -+ uint8_t tuner_voltage_teletext_fm; -+ uint8_t i2s_config; /* configuration of the sound chip */ -+ uint8_t video_decoder_type; -+ uint8_t video_decoder_host_config; -+ uint8_t input[5]; -+ } MM_TABLE; -+ uint16_t video_decoder_type; - int overlay_scaler_buffer_width; - int ecp_div; - -@@ -686,15 +751,15 @@ typedef struct { - DisplayModePtr currentMode, savedCurrentMode; - - /* special handlings for DELL triple-head server */ -- Bool IsDellServer; -+ Bool IsDellServer; - -- Bool VGAAccess; -+ Bool VGAAccess; - -- int MaxSurfaceWidth; -- int MaxLines; -+ int MaxSurfaceWidth; -+ int MaxLines; - -- CARD32 tv_dac_adj; -- CARD32 tv_dac_enable_mask; -+ uint32_t tv_dac_adj; -+ uint32_t tv_dac_enable_mask; - - Bool want_vblank_interrupts; - RADEONBIOSConnector BiosConnector[RADEON_MAX_BIOS_CONNECTOR]; -@@ -736,6 +801,9 @@ typedef struct { - - Bool r600_shadow_fb; - void *fb_shadow; -+ -+ int num_gb_pipes; -+ Bool has_tcl; - } RADEONInfoRec, *RADEONInfoPtr; - - #define RADEONWaitForFifo(pScrn, entries) \ -@@ -745,152 +813,209 @@ do { \ - info->fifo_slots -= entries; \ - } while (0) - --extern RADEONEntPtr RADEONEntPriv(ScrnInfoPtr pScrn); --extern void RADEONWaitForFifoFunction(ScrnInfoPtr pScrn, int entries); --extern void RADEONWaitForIdleMMIO(ScrnInfoPtr pScrn); -+/* legacy_crtc.c */ -+extern void legacy_crtc_dpms(xf86CrtcPtr crtc, int mode); -+extern void legacy_crtc_mode_set(xf86CrtcPtr crtc, DisplayModePtr mode, -+ DisplayModePtr adjusted_mode, int x, int y); -+extern void RADEONRestoreCommonRegisters(ScrnInfoPtr pScrn, -+ RADEONSavePtr restore); -+extern void RADEONRestoreCrtcRegisters(ScrnInfoPtr pScrn, -+ RADEONSavePtr restore); -+extern void RADEONRestoreCrtc2Registers(ScrnInfoPtr pScrn, -+ RADEONSavePtr restore); -+extern void RADEONRestorePLLRegisters(ScrnInfoPtr pScrn, -+ RADEONSavePtr restore); -+extern void RADEONRestorePLL2Registers(ScrnInfoPtr pScrn, -+ RADEONSavePtr restore); -+extern void RADEONSaveCommonRegisters(ScrnInfoPtr pScrn, RADEONSavePtr save); -+extern void RADEONSaveCrtcRegisters(ScrnInfoPtr pScrn, RADEONSavePtr save); -+extern void RADEONSaveCrtc2Registers(ScrnInfoPtr pScrn, RADEONSavePtr save); -+extern void RADEONSavePLLRegisters(ScrnInfoPtr pScrn, RADEONSavePtr save); -+extern void RADEONSavePLL2Registers(ScrnInfoPtr pScrn, RADEONSavePtr save); -+ -+/* legacy_output.c */ -+extern RADEONMonitorType legacy_dac_detect(ScrnInfoPtr pScrn, -+ xf86OutputPtr output); -+extern void legacy_output_dpms(xf86OutputPtr output, int mode); -+extern void legacy_output_mode_set(xf86OutputPtr output, DisplayModePtr mode, -+ DisplayModePtr adjusted_mode); -+extern I2CDevPtr RADEONDVODeviceInit(I2CBusPtr b, I2CSlaveAddr addr); -+extern Bool RADEONDVOReadByte(I2CDevPtr dvo, int addr, uint8_t *ch); -+extern Bool RADEONDVOWriteByte(I2CDevPtr dvo, int addr, uint8_t ch); -+extern void RADEONRestoreDACRegisters(ScrnInfoPtr pScrn, RADEONSavePtr restore); -+extern void RADEONRestoreFPRegisters(ScrnInfoPtr pScrn, RADEONSavePtr restore); -+extern void RADEONRestoreFP2Registers(ScrnInfoPtr pScrn, RADEONSavePtr restore); -+extern void RADEONRestoreLVDSRegisters(ScrnInfoPtr pScrn, RADEONSavePtr restore); -+extern void RADEONRestoreRMXRegisters(ScrnInfoPtr pScrn, RADEONSavePtr restore); -+extern void RADEONSaveDACRegisters(ScrnInfoPtr pScrn, RADEONSavePtr save); -+extern void RADEONSaveFPRegisters(ScrnInfoPtr pScrn, RADEONSavePtr save); -+ -+/* radeon_accel.c */ -+extern Bool RADEONAccelInit(ScreenPtr pScreen); -+extern void RADEONEngineFlush(ScrnInfoPtr pScrn); -+extern void RADEONEngineInit(ScrnInfoPtr pScrn); -+extern void RADEONEngineReset(ScrnInfoPtr pScrn); -+extern void RADEONEngineRestore(ScrnInfoPtr pScrn); -+extern uint8_t *RADEONHostDataBlit(ScrnInfoPtr pScrn, unsigned int cpp, -+ unsigned int w, uint32_t dstPitchOff, -+ uint32_t *bufPitch, int x, int *y, -+ unsigned int *h, unsigned int *hpass); -+extern void RADEONHostDataBlitCopyPass(ScrnInfoPtr pScrn, -+ unsigned int bpp, -+ uint8_t *dst, uint8_t *src, -+ unsigned int hpass, -+ unsigned int dstPitch, -+ unsigned int srcPitch); -+extern void RADEONCopySwap(uint8_t *dst, uint8_t *src, unsigned int size, int swap); -+extern void RADEONHostDataParams(ScrnInfoPtr pScrn, uint8_t *dst, -+ uint32_t pitch, int cpp, -+ uint32_t *dstPitchOffset, int *x, int *y); -+extern void RADEONInit3DEngine(ScrnInfoPtr pScrn); -+extern void RADEONWaitForFifoFunction(ScrnInfoPtr pScrn, int entries); - #ifdef XF86DRI --extern int RADEONDRISetParam(ScrnInfoPtr pScrn, unsigned int param, int64_t value); --extern void RADEONWaitForIdleCP(ScrnInfoPtr pScrn); -+extern drmBufPtr RADEONCPGetBuffer(ScrnInfoPtr pScrn); -+extern void RADEONCPFlushIndirect(ScrnInfoPtr pScrn, int discard); -+extern void RADEONCPReleaseIndirect(ScrnInfoPtr pScrn); -+extern int RADEONCPStop(ScrnInfoPtr pScrn, RADEONInfoPtr info); -+# ifdef USE_XAA -+extern Bool RADEONSetupMemXAA_DRI(int scrnIndex, ScreenPtr pScreen); -+# endif - #endif - --extern void RADEONDoAdjustFrame(ScrnInfoPtr pScrn, int x, int y, -- Bool clone); -- --extern void RADEONEngineReset(ScrnInfoPtr pScrn); --extern void RADEONEngineFlush(ScrnInfoPtr pScrn); --extern void RADEONEngineRestore(ScrnInfoPtr pScrn); -- --extern unsigned RADEONINPLL(ScrnInfoPtr pScrn, int addr); --extern void RADEONOUTPLL(ScrnInfoPtr pScrn, int addr, CARD32 data); -- --extern unsigned RADEONINMC(ScrnInfoPtr pScrn, int addr); --extern void RADEONOUTMC(ScrnInfoPtr pScrn, int addr, CARD32 data); -+#ifdef USE_XAA -+/* radeon_accelfuncs.c */ -+extern void RADEONAccelInitMMIO(ScreenPtr pScreen, XAAInfoRecPtr a); -+extern Bool RADEONSetupMemXAA(int scrnIndex, ScreenPtr pScreen); -+#endif - --extern void RADEONWaitForVerticalSync(ScrnInfoPtr pScrn); --extern void RADEONWaitForVerticalSync2(ScrnInfoPtr pScrn); -+/* radeon_bios.c */ -+extern Bool RADEONGetBIOSInfo(ScrnInfoPtr pScrn, xf86Int10InfoPtr pInt10); -+extern Bool RADEONGetClockInfoFromBIOS(ScrnInfoPtr pScrn); -+extern Bool RADEONGetConnectorInfoFromBIOS(ScrnInfoPtr pScrn); -+extern Bool RADEONGetDAC2InfoFromBIOS(xf86OutputPtr output); -+extern Bool RADEONGetExtTMDSInfoFromBIOS(xf86OutputPtr output); -+extern Bool RADEONGetHardCodedEDIDFromBIOS(xf86OutputPtr output); -+extern Bool RADEONGetBIOSInitTableOffsets(ScrnInfoPtr pScrn); -+extern Bool RADEONGetLVDSInfoFromBIOS(xf86OutputPtr output); -+extern Bool RADEONGetTMDSInfoFromBIOS(xf86OutputPtr output); -+extern Bool RADEONGetTVInfoFromBIOS(xf86OutputPtr output); -+extern Bool RADEONInitExtTMDSInfoFromBIOS (xf86OutputPtr output); -+extern Bool RADEONPostCardFromBIOSTables(ScrnInfoPtr pScrn); -+ -+/* radeon_commonfuncs.c */ -+#ifdef XF86DRI -+extern void RADEONWaitForIdleCP(ScrnInfoPtr pScrn); -+#endif -+extern void RADEONWaitForIdleMMIO(ScrnInfoPtr pScrn); - --extern void RADEONChangeSurfaces(ScrnInfoPtr pScrn); -+/* radeon_crtc.c */ -+extern void radeon_crtc_dpms(xf86CrtcPtr crtc, int mode); -+extern void radeon_crtc_load_lut(xf86CrtcPtr crtc); -+extern void radeon_crtc_modeset_ioctl(xf86CrtcPtr crtc, Bool post); -+extern Bool RADEONAllocateControllers(ScrnInfoPtr pScrn, int mask); -+extern void RADEONBlank(ScrnInfoPtr pScrn); -+extern void RADEONComputePLL(RADEONPLLPtr pll, unsigned long freq, -+ uint32_t *chosen_dot_clock_freq, -+ uint32_t *chosen_feedback_div, -+ uint32_t *chosen_reference_div, -+ uint32_t *chosen_post_div, int flags); -+extern DisplayModePtr RADEONCrtcFindClosestMode(xf86CrtcPtr crtc, -+ DisplayModePtr pMode); -+extern void RADEONUnblank(ScrnInfoPtr pScrn); -+extern Bool RADEONSetTiling(ScrnInfoPtr pScrn); -+extern void RADEONInitDispBandwidth(ScrnInfoPtr pScrn); -+ -+/* radeon_cursor.c */ -+extern Bool RADEONCursorInit(ScreenPtr pScreen); -+extern void radeon_crtc_hide_cursor(xf86CrtcPtr crtc); -+extern void radeon_crtc_load_cursor_argb(xf86CrtcPtr crtc, CARD32 *image); -+extern void radeon_crtc_set_cursor_colors(xf86CrtcPtr crtc, int bg, int fg); -+extern void radeon_crtc_set_cursor_position(xf86CrtcPtr crtc, int x, int y); -+extern void radeon_crtc_show_cursor(xf86CrtcPtr crtc); -+ -+/* radeon_dga.c */ -+extern Bool RADEONDGAInit(ScreenPtr pScreen); - --extern Bool RADEONAccelInit(ScreenPtr pScreen); --#ifdef USE_EXA --extern Bool RADEONSetupMemEXA (ScreenPtr pScreen); --extern Bool RADEONDrawInitMMIO(ScreenPtr pScreen); - #ifdef XF86DRI --extern unsigned long long RADEONTexOffsetStart(PixmapPtr pPix); --extern Bool RADEONGetDatatypeBpp(int bpp, CARD32 *type); --extern Bool RADEONGetPixmapOffsetPitch(PixmapPtr pPix, -- CARD32 *pitch_offset); --extern Bool RADEONDrawInitCP(ScreenPtr pScreen); --extern void RADEONDoPrepareCopyCP(ScrnInfoPtr pScrn, -- CARD32 src_pitch_offset, -- CARD32 dst_pitch_offset, -- CARD32 datatype, int rop, -- Pixel planemask); --extern void RADEONCopyCP(PixmapPtr pDst, int srcX, int srcY, int dstX, -- int dstY, int w, int h); --#endif --#endif --#ifdef USE_XAA --extern void RADEONAccelInitMMIO(ScreenPtr pScreen, XAAInfoRecPtr a); -+/* radeon_dri.c */ -+extern void RADEONDRIAllocatePCIGARTTable(ScreenPtr pScreen); -+extern void RADEONDRICloseScreen(ScreenPtr pScreen); -+extern Bool RADEONDRIFinishScreenInit(ScreenPtr pScreen); -+extern int RADEONDRIGetPciAperTableSize(ScrnInfoPtr pScrn); -+extern Bool RADEONDRIGetVersion(ScrnInfoPtr pScrn); -+extern void RADEONDRIResume(ScreenPtr pScreen); -+extern Bool RADEONDRIScreenInit(ScreenPtr pScreen); -+extern int RADEONDRISetParam(ScrnInfoPtr pScrn, -+ unsigned int param, int64_t value); -+extern Bool RADEONDRISetVBlankInterrupt(ScrnInfoPtr pScrn, Bool on); -+extern void RADEONDRIStop(ScreenPtr pScreen); - #endif --extern void RADEONEngineInit(ScrnInfoPtr pScrn); --extern Bool RADEONCursorInit(ScreenPtr pScreen); --extern Bool RADEONDGAInit(ScreenPtr pScreen); -- --extern void RADEONInit3DEngine(ScrnInfoPtr pScrn); -- --extern int RADEONMinBits(int val); -- --extern void RADEONInitVideo(ScreenPtr pScreen); --extern void RADEONResetVideo(ScrnInfoPtr pScrn); --extern void R300CGWorkaround(ScrnInfoPtr pScrn); -- --extern void RADEONPllErrataAfterIndex(RADEONInfoPtr info); --extern void RADEONPllErrataAfterData(RADEONInfoPtr info); -- --extern Bool RADEONGetBIOSInfo(ScrnInfoPtr pScrn, xf86Int10InfoPtr pInt10); --extern Bool RADEONGetConnectorInfoFromBIOS (ScrnInfoPtr pScrn); --extern Bool RADEONGetClockInfoFromBIOS (ScrnInfoPtr pScrn); --extern Bool RADEONGetLVDSInfoFromBIOS (xf86OutputPtr output); --extern Bool RADEONGetTMDSInfoFromBIOS (xf86OutputPtr output); --extern Bool RADEONGetTVInfoFromBIOS (xf86OutputPtr output); --extern Bool RADEONGetDAC2InfoFromBIOS (xf86OutputPtr output); --extern Bool RADEONGetHardCodedEDIDFromBIOS (xf86OutputPtr output); -- --extern void RADEONRestoreMemMapRegisters(ScrnInfoPtr pScrn, -- RADEONSavePtr restore); --extern void RADEONRestoreCommonRegisters(ScrnInfoPtr pScrn, -- RADEONSavePtr restore); --extern void RADEONRestoreCrtcRegisters(ScrnInfoPtr pScrn, -- RADEONSavePtr restore); --extern void RADEONRestoreDACRegisters(ScrnInfoPtr pScrn, -- RADEONSavePtr restore); --extern void RADEONRestoreFPRegisters(ScrnInfoPtr pScrn, -- RADEONSavePtr restore); --extern void RADEONRestoreFP2Registers(ScrnInfoPtr pScrn, -- RADEONSavePtr restore); --extern void RADEONRestoreLVDSRegisters(ScrnInfoPtr pScrn, -- RADEONSavePtr restore); --extern void RADEONRestoreRMXRegisters(ScrnInfoPtr pScrn, -- RADEONSavePtr restore); --extern void RADEONRestorePLLRegisters(ScrnInfoPtr pScrn, -- RADEONSavePtr restore); --extern void RADEONRestoreCrtc2Registers(ScrnInfoPtr pScrn, -- RADEONSavePtr restore); --extern void RADEONRestorePLL2Registers(ScrnInfoPtr pScrn, -- RADEONSavePtr restore); -- --extern void RADEONInitMemMapRegisters(ScrnInfoPtr pScrn, -- RADEONSavePtr save, -- RADEONInfoPtr info); --extern void RADEONInitDispBandwidth(ScrnInfoPtr pScrn); --extern Bool RADEONI2cInit(ScrnInfoPtr pScrn); --extern Bool RADEONSetupConnectors(ScrnInfoPtr pScrn); --extern void RADEONPrintPortMap(ScrnInfoPtr pScrn); --extern void RADEONDisableDisplays(ScrnInfoPtr pScrn); --extern void RADEONGetPanelInfo(ScrnInfoPtr pScrn); --extern void RADEONUnblank(ScrnInfoPtr pScrn); --extern void RADEONUnblank(ScrnInfoPtr pScrn); --extern void RADEONBlank(ScrnInfoPtr pScrn); - --extern Bool RADEONAllocateControllers(ScrnInfoPtr pScrn, int mask); --extern Bool RADEONAllocateConnectors(ScrnInfoPtr pScrn); -+/* radeon_driver.c */ -+extern void RADEONDoAdjustFrame(ScrnInfoPtr pScrn, int x, int y, Bool clone); -+extern void RADEONChangeSurfaces(ScrnInfoPtr pScrn); -+extern RADEONEntPtr RADEONEntPriv(ScrnInfoPtr pScrn); -+extern int RADEONMinBits(int val); -+extern unsigned RADEONINMC(ScrnInfoPtr pScrn, int addr); -+extern unsigned RADEONINPLL(ScrnInfoPtr pScrn, int addr); -+extern void RADEONOUTMC(ScrnInfoPtr pScrn, int addr, uint32_t data); -+extern void RADEONOUTPLL(ScrnInfoPtr pScrn, int addr, uint32_t data); -+extern void RADEONPllErrataAfterData(RADEONInfoPtr info); -+extern void RADEONPllErrataAfterIndex(RADEONInfoPtr info); -+extern void RADEONWaitForVerticalSync(ScrnInfoPtr pScrn); -+extern void RADEONWaitForVerticalSync2(ScrnInfoPtr pScrn); -+extern void RADEONInitMemMapRegisters(ScrnInfoPtr pScrn, RADEONSavePtr save, -+ RADEONInfoPtr info); -+extern void RADEONRestoreMemMapRegisters(ScrnInfoPtr pScrn, -+ RADEONSavePtr restore); - --extern void RADEONSetPitch (ScrnInfoPtr pScrn); --extern void RADEONUpdateHVPosition(xf86OutputPtr output, DisplayModePtr mode); -+#ifdef USE_EXA -+/* radeon_exa.c */ -+extern Bool RADEONSetupMemEXA(ScreenPtr pScreen); -+ -+/* radeon_exa_funcs.c */ -+extern void RADEONCopyCP(PixmapPtr pDst, int srcX, int srcY, int dstX, -+ int dstY, int w, int h); -+extern void RADEONCopyMMIO(PixmapPtr pDst, int srcX, int srcY, int dstX, -+ int dstY, int w, int h); -+extern Bool RADEONDrawInitCP(ScreenPtr pScreen); -+extern Bool RADEONDrawInitMMIO(ScreenPtr pScreen); -+extern void RADEONDoPrepareCopyCP(ScrnInfoPtr pScrn, -+ uint32_t src_pitch_offset, -+ uint32_t dst_pitch_offset, -+ uint32_t datatype, int rop, -+ Pixel planemask); -+extern void RADEONDoPrepareCopyMMIO(ScrnInfoPtr pScrn, -+ uint32_t src_pitch_offset, -+ uint32_t dst_pitch_offset, -+ uint32_t datatype, int rop, -+ Pixel planemask); -+#endif - --extern DisplayModePtr --RADEONProbeOutputModes(xf86OutputPtr output); -- --extern Bool --RADEONDVOReadByte(I2CDevPtr dvo, int addr, CARD8 *ch); --extern Bool --RADEONDVOWriteByte(I2CDevPtr dvo, int addr, CARD8 ch); --extern Bool --RADEONGetExtTMDSInfoFromBIOS (xf86OutputPtr output); --extern Bool --RADEONInitExtTMDSInfoFromBIOS (xf86OutputPtr output); -- --extern RADEONI2CBusRec --legacy_setup_i2c_bus(int ddc_line); --extern RADEONI2CBusRec --atom_setup_i2c_bus(int ddc_line); -- --extern void --radeon_crtc_set_cursor_position (xf86CrtcPtr crtc, int x, int y); --extern void --radeon_crtc_show_cursor (xf86CrtcPtr crtc); --extern void --radeon_crtc_hide_cursor (xf86CrtcPtr crtc); --extern void --radeon_crtc_set_cursor_position (xf86CrtcPtr crtc, int x, int y); --extern void --radeon_crtc_set_cursor_colors (xf86CrtcPtr crtc, int bg, int fg); --extern void --radeon_crtc_load_cursor_argb (xf86CrtcPtr crtc, CARD32 *image); --extern void --radeon_crtc_load_lut(xf86CrtcPtr crtc); -+#if defined(XF86DRI) && defined(USE_EXA) -+/* radeon_exa.c */ -+extern Bool RADEONGetDatatypeBpp(int bpp, uint32_t *type); -+extern Bool RADEONGetPixmapOffsetPitch(PixmapPtr pPix, -+ uint32_t *pitch_offset); -+extern unsigned long long RADEONTexOffsetStart(PixmapPtr pPix); -+#endif - -+/* radeon_modes.c */ -+extern void RADEONSetPitch(ScrnInfoPtr pScrn); -+extern DisplayModePtr RADEONProbeOutputModes(xf86OutputPtr output); -+ -+/* radeon_output.c */ -+extern RADEONI2CBusRec atom_setup_i2c_bus(int ddc_line); -+extern RADEONI2CBusRec legacy_setup_i2c_bus(int ddc_line); -+extern void RADEONGetPanelInfo(ScrnInfoPtr pScrn); -+extern void RADEONInitConnector(xf86OutputPtr output); -+extern void RADEONPrintPortMap(ScrnInfoPtr pScrn); -+extern void RADEONSetOutputType(ScrnInfoPtr pScrn, -+ RADEONOutputPrivatePtr radeon_output); -+extern Bool RADEONSetupConnectors(ScrnInfoPtr pScrn); -+ -+/* radeon_tv.c */ -+extern void RADEONSaveTVRegisters(ScrnInfoPtr pScrn, RADEONSavePtr save); - extern void RADEONAdjustCrtcRegistersForTV(ScrnInfoPtr pScrn, RADEONSavePtr save, - DisplayModePtr mode, xf86OutputPtr output); - extern void RADEONAdjustPLLRegistersForTV(ScrnInfoPtr pScrn, RADEONSavePtr save, -@@ -901,47 +1026,18 @@ extern void RADEONAdjustPLL2RegistersForTV(ScrnInfoPtr pScrn, RADEONSavePtr save - DisplayModePtr mode, xf86OutputPtr output); - extern void RADEONInitTVRegisters(xf86OutputPtr output, RADEONSavePtr save, - DisplayModePtr mode, BOOL IsPrimary); -- - extern void RADEONRestoreTVRegisters(ScrnInfoPtr pScrn, RADEONSavePtr restore); -+extern void RADEONUpdateHVPosition(xf86OutputPtr output, DisplayModePtr mode); - --extern void RADEONComputePLL(RADEONPLLPtr pll, unsigned long freq, CARD32 *chosen_dot_clock_freq, -- CARD32 *chosen_feedback_div, CARD32 *chosen_reference_div, -- CARD32 *chosen_post_div, int flags); -+/* radeon_video.c */ -+extern void RADEONInitVideo(ScreenPtr pScreen); -+extern void RADEONResetVideo(ScrnInfoPtr pScrn); - - #ifdef XF86DRI --#ifdef USE_XAA --extern void RADEONAccelInitCP(ScreenPtr pScreen, XAAInfoRecPtr a); --#endif --extern Bool RADEONDRIGetVersion(ScrnInfoPtr pScrn); --extern Bool RADEONDRIScreenInit(ScreenPtr pScreen); --extern void RADEONDRICloseScreen(ScreenPtr pScreen); --extern void RADEONDRIResume(ScreenPtr pScreen); --extern Bool RADEONDRIFinishScreenInit(ScreenPtr pScreen); --extern void RADEONDRIAllocatePCIGARTTable(ScreenPtr pScreen); --extern int RADEONDRIGetPciAperTableSize(ScrnInfoPtr pScrn); --extern void RADEONDRIStop(ScreenPtr pScreen); -- --extern drmBufPtr RADEONCPGetBuffer(ScrnInfoPtr pScrn); --extern void RADEONCPFlushIndirect(ScrnInfoPtr pScrn, int discard); --extern void RADEONCPReleaseIndirect(ScrnInfoPtr pScrn); --extern int RADEONCPStop(ScrnInfoPtr pScrn, RADEONInfoPtr info); --extern Bool RADEONDRISetVBlankInterrupt(ScrnInfoPtr pScrn, Bool on); -- --extern void RADEONHostDataParams(ScrnInfoPtr pScrn, CARD8 *dst, -- CARD32 pitch, int cpp, -- CARD32 *dstPitchOffset, int *x, int *y); --extern CARD8* RADEONHostDataBlit(ScrnInfoPtr pScrn, unsigned int cpp, -- unsigned int w, CARD32 dstPitchOff, -- CARD32 *bufPitch, int x, int *y, -- unsigned int *h, unsigned int *hpass); --extern void RADEONHostDataBlitCopyPass(ScrnInfoPtr pScrn, -- unsigned int bpp, -- CARD8 *dst, CARD8 *src, -- unsigned int hpass, -- unsigned int dstPitch, -- unsigned int srcPitch); --extern void RADEONCopySwap(CARD8 *dst, CARD8 *src, unsigned int size, -- int swap); -+# ifdef USE_XAA -+/* radeon_accelfuncs.c */ -+extern void RADEONAccelInitCP(ScreenPtr pScreen, XAAInfoRecPtr a); -+# endif - - #define RADEONCP_START(pScrn, info) \ - do { \ -@@ -980,13 +1076,11 @@ do { \ - - #define RADEONCP_RESET(pScrn, info) \ - do { \ -- if (RADEONCP_USE_RING_BUFFER(info->CPMode)) { \ - int _ret = drmCommandNone(info->drmFD, DRM_RADEON_CP_RESET); \ - if (_ret) { \ - xf86DrvMsg(pScrn->scrnIndex, X_ERROR, \ - "%s: CP reset %d\n", __FUNCTION__, _ret); \ - } \ -- } \ - } while (0) - - #define RADEONCP_REFRESH(pScrn, info) \ -@@ -998,11 +1092,18 @@ do { \ - info->needCacheFlush = FALSE; \ - } \ - RADEON_WAIT_UNTIL_IDLE(); \ -- BEGIN_RING(6); \ -- OUT_RING_REG(RADEON_RE_TOP_LEFT, info->re_top_left); \ -- OUT_RING_REG(RADEON_RE_WIDTH_HEIGHT, info->re_width_height); \ -- OUT_RING_REG(RADEON_AUX_SC_CNTL, info->aux_sc_cntl); \ -- ADVANCE_RING(); \ -+ if (info->ChipFamily <= CHIP_FAMILY_RV280) { \ -+ BEGIN_RING(6); \ -+ OUT_RING_REG(RADEON_RE_TOP_LEFT, info->re_top_left); \ -+ OUT_RING_REG(RADEON_RE_WIDTH_HEIGHT, info->re_width_height); \ -+ OUT_RING_REG(RADEON_AUX_SC_CNTL, info->aux_sc_cntl); \ -+ ADVANCE_RING(); \ -+ } else { \ -+ BEGIN_RING(4); \ -+ OUT_RING_REG(R300_SC_SCISSOR0, info->re_top_left); \ -+ OUT_RING_REG(R300_SC_SCISSOR1, info->re_width_height); \ -+ ADVANCE_RING(); \ -+ } \ - info->CPInUse = TRUE; \ - } \ - } while (0) -@@ -1020,7 +1121,7 @@ do { \ - - #define RADEON_VERBOSE 0 - --#define RING_LOCALS CARD32 *__head = NULL; int __expected; int __count = 0 -+#define RING_LOCALS uint32_t *__head = NULL; int __expected; int __count = 0 - - #define BEGIN_RING(n) do { \ - if (RADEON_VERBOSE) { \ -@@ -1038,7 +1139,7 @@ do { \ - if (!info->indirectBuffer) { \ - info->indirectBuffer = RADEONCPGetBuffer(pScrn); \ - info->indirectStart = 0; \ -- } else if (info->indirectBuffer->used + (n) * (int)sizeof(CARD32) > \ -+ } else if (info->indirectBuffer->used + (n) * (int)sizeof(uint32_t) > \ - info->indirectBuffer->total) { \ - RADEONCPFlushIndirect(pScrn, 1); \ - } \ -@@ -1065,9 +1166,9 @@ do { \ - "ADVANCE_RING() start: %d used: %d count: %d\n", \ - info->indirectStart, \ - info->indirectBuffer->used, \ -- __count * (int)sizeof(CARD32)); \ -+ __count * (int)sizeof(uint32_t)); \ - } \ -- info->indirectBuffer->used += __count * (int)sizeof(CARD32); \ -+ info->indirectBuffer->used += __count * (int)sizeof(uint32_t); \ - } while (0) - - #define OUT_RING(x) do { \ -@@ -1130,15 +1231,27 @@ do { \ - #define RADEON_PURGE_CACHE() \ - do { \ - BEGIN_RING(2); \ -- OUT_RING(CP_PACKET0(RADEON_RB3D_DSTCACHE_CTLSTAT, 0)); \ -- OUT_RING(RADEON_RB3D_DC_FLUSH_ALL); \ -+ if (info->ChipFamily <= CHIP_FAMILY_RV280) { \ -+ OUT_RING(CP_PACKET0(RADEON_RB3D_DSTCACHE_CTLSTAT, 0)); \ -+ OUT_RING(RADEON_RB3D_DC_FLUSH_ALL); \ -+ } else { \ -+ OUT_RING(CP_PACKET0(R300_RB3D_DSTCACHE_CTLSTAT, 0)); \ -+ OUT_RING(R300_RB3D_DC_FLUSH_ALL); \ -+ } \ - ADVANCE_RING(); \ - } while (0) - - #define RADEON_PURGE_ZCACHE() \ - do { \ -- OUT_RING(CP_PACKET0(RADEON_RB3D_ZCACHE_CTLSTAT, 0)); \ -- OUT_RING(RADEON_RB3D_ZC_FLUSH_ALL); \ -+ BEGIN_RING(2); \ -+ if (info->ChipFamily <= CHIP_FAMILY_RV280) { \ -+ OUT_RING(CP_PACKET0(RADEON_RB3D_ZCACHE_CTLSTAT, 0)); \ -+ OUT_RING(RADEON_RB3D_ZC_FLUSH_ALL); \ -+ } else { \ -+ OUT_RING(CP_PACKET0(R300_RB3D_ZCACHE_CTLSTAT, 0)); \ -+ OUT_RING(R300_ZC_FLUSH_ALL); \ -+ } \ -+ ADVANCE_RING(); \ - } while (0) - - #endif /* XF86DRI */ -diff --git a/src/radeon_accel.c b/src/radeon_accel.c -index 8b2f167..91f463a 100644 ---- a/src/radeon_accel.c -+++ b/src/radeon_accel.c -@@ -158,17 +158,32 @@ void RADEONEngineFlush(ScrnInfoPtr pScrn) - unsigned char *RADEONMMIO = info->MMIO; - int i; - -- OUTREGP(RADEON_RB3D_DSTCACHE_CTLSTAT, -- RADEON_RB3D_DC_FLUSH_ALL, -- ~RADEON_RB3D_DC_FLUSH_ALL); -- for (i = 0; i < RADEON_TIMEOUT; i++) { -- if (!(INREG(RADEON_RB3D_DSTCACHE_CTLSTAT) & RADEON_RB3D_DC_BUSY)) -- break; -- } -- if (i == RADEON_TIMEOUT) { -- xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG, -- "DC flush timeout: %x\n", -- (unsigned int)INREG(RADEON_RB3D_DSTCACHE_CTLSTAT)); -+ if (info->ChipFamily <= CHIP_FAMILY_RV280) { -+ OUTREGP(RADEON_RB3D_DSTCACHE_CTLSTAT, -+ RADEON_RB3D_DC_FLUSH_ALL, -+ ~RADEON_RB3D_DC_FLUSH_ALL); -+ for (i = 0; i < RADEON_TIMEOUT; i++) { -+ if (!(INREG(RADEON_RB3D_DSTCACHE_CTLSTAT) & RADEON_RB3D_DC_BUSY)) -+ break; -+ } -+ if (i == RADEON_TIMEOUT) { -+ xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG, -+ "DC flush timeout: %x\n", -+ (unsigned int)INREG(RADEON_RB3D_DSTCACHE_CTLSTAT)); -+ } -+ } else { -+ OUTREGP(R300_DSTCACHE_CTLSTAT, -+ R300_RB2D_DC_FLUSH_ALL, -+ ~R300_RB2D_DC_FLUSH_ALL); -+ for (i = 0; i < RADEON_TIMEOUT; i++) { -+ if (!(INREG(R300_DSTCACHE_CTLSTAT) & R300_RB2D_DC_BUSY)) -+ break; -+ } -+ if (i == RADEON_TIMEOUT) { -+ xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG, -+ "DC flush timeout: %x\n", -+ (unsigned int)INREG(R300_DSTCACHE_CTLSTAT)); -+ } - } - } - -@@ -177,10 +192,10 @@ void RADEONEngineReset(ScrnInfoPtr pScrn) - { - RADEONInfoPtr info = RADEONPTR(pScrn); - unsigned char *RADEONMMIO = info->MMIO; -- CARD32 clock_cntl_index; -- CARD32 mclk_cntl; -- CARD32 rbbm_soft_reset; -- CARD32 host_path_cntl; -+ uint32_t clock_cntl_index; -+ uint32_t mclk_cntl; -+ uint32_t rbbm_soft_reset; -+ uint32_t host_path_cntl; - - /* The following RBBM_SOFT_RESET sequence can help un-wedge - * an R300 after the command processor got stuck. -@@ -195,7 +210,7 @@ void RADEONEngineReset(ScrnInfoPtr pScrn) - RADEON_SOFT_RESET_E2 | - RADEON_SOFT_RESET_RB)); - INREG(RADEON_RBBM_SOFT_RESET); -- OUTREG(RADEON_RBBM_SOFT_RESET, (rbbm_soft_reset & (CARD32) -+ OUTREG(RADEON_RBBM_SOFT_RESET, (rbbm_soft_reset & (uint32_t) - ~(RADEON_SOFT_RESET_CP | - RADEON_SOFT_RESET_HI | - RADEON_SOFT_RESET_SE | -@@ -217,7 +232,7 @@ void RADEONEngineReset(ScrnInfoPtr pScrn) - * ASIC-version dependent, so we force all blocks on for now - */ - if (info->HasCRTC2) { -- CARD32 tmp; -+ uint32_t tmp; - - tmp = INPLL(pScrn, RADEON_SCLK_CNTL); - OUTPLL(RADEON_SCLK_CNTL, ((tmp & ~RADEON_DYN_STOP_LAT_MASK) | -@@ -251,7 +266,7 @@ void RADEONEngineReset(ScrnInfoPtr pScrn) - rbbm_soft_reset = INREG(RADEON_RBBM_SOFT_RESET); - - if (IS_R300_VARIANT || IS_AVIVO_VARIANT) { -- CARD32 tmp; -+ uint32_t tmp; - - OUTREG(RADEON_RBBM_SOFT_RESET, (rbbm_soft_reset | - RADEON_SOFT_RESET_CP | -@@ -270,7 +285,7 @@ void RADEONEngineReset(ScrnInfoPtr pScrn) - RADEON_SOFT_RESET_E2 | - RADEON_SOFT_RESET_RB)); - INREG(RADEON_RBBM_SOFT_RESET); -- OUTREG(RADEON_RBBM_SOFT_RESET, (rbbm_soft_reset & (CARD32) -+ OUTREG(RADEON_RBBM_SOFT_RESET, (rbbm_soft_reset & (uint32_t) - ~(RADEON_SOFT_RESET_CP | - RADEON_SOFT_RESET_SE | - RADEON_SOFT_RESET_RE | -@@ -355,7 +370,78 @@ void RADEONEngineInit(ScrnInfoPtr pScrn) - info->CurrentLayout.pixel_code, - info->CurrentLayout.bitsPerPixel); - -- OUTREG(RADEON_RB3D_CNTL, 0); -+#ifdef XF86DRI -+ if (info->directRenderingEnabled && (IS_R300_3D || IS_R500_3D)) { -+ drmRadeonGetParam np; -+ int num_pipes; -+ -+ memset(&np, 0, sizeof(np)); -+ np.param = RADEON_PARAM_NUM_GB_PIPES; -+ np.value = &num_pipes; -+ -+ if (drmCommandWriteRead(info->drmFD, DRM_RADEON_GETPARAM, &np, -+ sizeof(np)) < 0) { -+ xf86DrvMsg(pScrn->scrnIndex, X_WARNING, -+ "Failed to determine num pipes from DRM, falling back to " -+ "manual look-up!\n"); -+ info->num_gb_pipes = 0; -+ } else { -+ info->num_gb_pipes = num_pipes; -+ } -+ } -+#endif -+ -+ if ((info->ChipFamily == CHIP_FAMILY_RV410) || -+ (info->ChipFamily == CHIP_FAMILY_R420) || -+ (info->ChipFamily == CHIP_FAMILY_RS600) || -+ (info->ChipFamily == CHIP_FAMILY_RS690) || -+ (info->ChipFamily == CHIP_FAMILY_RS740) || -+ (info->ChipFamily == CHIP_FAMILY_RS400) || -+ (info->ChipFamily == CHIP_FAMILY_RS480) || -+ IS_R500_3D) { -+ if (info->num_gb_pipes == 0) { -+ uint32_t gb_pipe_sel = INREG(R400_GB_PIPE_SELECT); -+ -+ info->num_gb_pipes = ((gb_pipe_sel >> 12) & 0x3) + 1; -+ if (IS_R500_3D) -+ OUTPLL(pScrn, R500_DYN_SCLK_PWMEM_PIPE, (1 | ((gb_pipe_sel >> 8) & 0xf) << 4)); -+ } -+ } else { -+ if (info->num_gb_pipes == 0) { -+ if ((info->ChipFamily == CHIP_FAMILY_R300) || -+ (info->ChipFamily == CHIP_FAMILY_R350)) { -+ /* R3xx chips */ -+ info->num_gb_pipes = 2; -+ } else { -+ /* RV3xx chips */ -+ info->num_gb_pipes = 1; -+ } -+ } -+ } -+ -+ if (IS_R300_3D || IS_R500_3D) -+ xf86DrvMsg(pScrn->scrnIndex, X_INFO, -+ "num pipes is %d\n", info->num_gb_pipes); -+ -+ if (IS_R300_3D || IS_R500_3D) { -+ uint32_t gb_tile_config = (R300_ENABLE_TILING | R300_TILE_SIZE_16 | R300_SUBPIXEL_1_16); -+ -+ switch(info->num_gb_pipes) { -+ case 2: gb_tile_config |= R300_PIPE_COUNT_R300; break; -+ case 3: gb_tile_config |= R300_PIPE_COUNT_R420_3P; break; -+ case 4: gb_tile_config |= R300_PIPE_COUNT_R420; break; -+ default: -+ case 1: gb_tile_config |= R300_PIPE_COUNT_RV350; break; -+ } -+ -+ OUTREG(R300_GB_TILE_CONFIG, gb_tile_config); -+ OUTREG(RADEON_WAIT_UNTIL, RADEON_WAIT_2D_IDLECLEAN | RADEON_WAIT_3D_IDLECLEAN); -+ OUTREG(R300_DST_PIPE_CONFIG, INREG(R300_DST_PIPE_CONFIG) | R300_PIPE_AUTO_CONFIG); -+ OUTREG(R300_RB2D_DSTCACHE_MODE, (INREG(R300_RB2D_DSTCACHE_MODE) | -+ R300_DC_AUTOFLUSH_ENABLE | -+ R300_DC_DC_DISABLE_IGNORE_PE)); -+ } else -+ OUTREG(RADEON_RB3D_CNTL, 0); - - RADEONEngineReset(pScrn); - -@@ -390,8 +476,12 @@ void RADEONEngineInit(ScrnInfoPtr pScrn) - info->sc_bottom = RADEON_DEFAULT_SC_BOTTOM_MAX; - - info->re_top_left = 0x00000000; -- info->re_width_height = ((0x7ff << RADEON_RE_WIDTH_SHIFT) | -- (0x7ff << RADEON_RE_HEIGHT_SHIFT)); -+ if (info->ChipFamily <= CHIP_FAMILY_RV280) -+ info->re_width_height = ((0x7ff << RADEON_RE_WIDTH_SHIFT) | -+ (0x7ff << RADEON_RE_HEIGHT_SHIFT)); -+ else -+ info->re_width_height = ((8191 << R300_SCISSOR_X_SHIFT) | -+ (8191 << R300_SCISSOR_Y_SHIFT)); - - info->aux_sc_cntl = 0x00000000; - #endif -@@ -617,11 +707,11 @@ void RADEONCPReleaseIndirect(ScrnInfoPtr pScrn) - * about tiling etc. - */ - void --RADEONHostDataParams(ScrnInfoPtr pScrn, CARD8 *dst, CARD32 pitch, int cpp, -- CARD32 *dstPitchOff, int *x, int *y) -+RADEONHostDataParams(ScrnInfoPtr pScrn, uint8_t *dst, uint32_t pitch, int cpp, -+ uint32_t *dstPitchOff, int *x, int *y) - { - RADEONInfoPtr info = RADEONPTR( pScrn ); -- CARD32 dstOffs = dst - (CARD8*)info->FB + info->fbLocation; -+ uint32_t dstOffs = dst - (uint8_t*)info->FB + info->fbLocation; - - *dstPitchOff = pitch << 16 | (dstOffs & ~RADEON_BUFFER_ALIGN) >> 10; - *y = ( dstOffs & RADEON_BUFFER_ALIGN ) / pitch; -@@ -632,21 +722,21 @@ RADEONHostDataParams(ScrnInfoPtr pScrn, CARD8 *dst, CARD32 pitch, int cpp, - * framebuffer. Returns the address where the data can be written to and sets - * the dstPitch and hpass variables as required. - */ --CARD8* -+uint8_t* - RADEONHostDataBlit( - ScrnInfoPtr pScrn, - unsigned int cpp, - unsigned int w, -- CARD32 dstPitchOff, -- CARD32 *bufPitch, -+ uint32_t dstPitchOff, -+ uint32_t *bufPitch, - int x, - int *y, - unsigned int *h, - unsigned int *hpass - ){ - RADEONInfoPtr info = RADEONPTR( pScrn ); -- CARD32 format, dwords; -- CARD8 *ret; -+ uint32_t format, dwords; -+ uint8_t *ret; - RING_LOCALS; - - if ( *h == 0 ) -@@ -719,7 +809,7 @@ RADEONHostDataBlit( - OUT_RING( *hpass << 16 | (*bufPitch / cpp) ); - OUT_RING( dwords ); - -- ret = ( CARD8* )&__head[__count]; -+ ret = ( uint8_t* )&__head[__count]; - - __count += dwords; - ADVANCE_RING(); -@@ -730,7 +820,7 @@ RADEONHostDataBlit( - return ret; - } - --void RADEONCopySwap(CARD8 *dst, CARD8 *src, unsigned int size, int swap) -+void RADEONCopySwap(uint8_t *dst, uint8_t *src, unsigned int size, int swap) - { - switch(swap) { - case RADEON_HOST_DATA_SWAP_HDW: -@@ -785,8 +875,8 @@ void - RADEONHostDataBlitCopyPass( - ScrnInfoPtr pScrn, - unsigned int cpp, -- CARD8 *dst, -- CARD8 *src, -+ uint8_t *dst, -+ uint8_t *src, - unsigned int hpass, - unsigned int dstPitch, - unsigned int srcPitch -@@ -956,18 +1046,6 @@ RADEONSetupMemXAA_DRI(int scrnIndex, ScreenPtr pScreen) - depthSize = ((((pScrn->virtualY + 15) & ~15) * info->depthPitch - * depthCpp + RADEON_BUFFER_ALIGN) & ~RADEON_BUFFER_ALIGN); - -- switch (info->CPMode) { -- case RADEON_DEFAULT_CP_PIO_MODE: -- xf86DrvMsg(pScrn->scrnIndex, X_INFO, "CP in PIO mode\n"); -- break; -- case RADEON_DEFAULT_CP_BM_MODE: -- xf86DrvMsg(pScrn->scrnIndex, X_INFO, "CP in BM mode\n"); -- break; -- default: -- xf86DrvMsg(pScrn->scrnIndex, X_INFO, "CP in UNKNOWN mode\n"); -- break; -- } -- - xf86DrvMsg(pScrn->scrnIndex, X_INFO, - "Using %d MB GART aperture\n", info->gartSize); - xf86DrvMsg(pScrn->scrnIndex, X_INFO, -@@ -1075,7 +1153,7 @@ RADEONSetupMemXAA_DRI(int scrnIndex, ScreenPtr pScreen) - /* Reserve space for textures */ - info->textureOffset = ((info->FbMapSize - info->textureSize + - RADEON_BUFFER_ALIGN) & -- ~(CARD32)RADEON_BUFFER_ALIGN); -+ ~(uint32_t)RADEON_BUFFER_ALIGN); - } - - /* Reserve space for the shared depth -@@ -1083,7 +1161,7 @@ RADEONSetupMemXAA_DRI(int scrnIndex, ScreenPtr pScreen) - */ - info->depthOffset = ((info->textureOffset - depthSize + - RADEON_BUFFER_ALIGN) & -- ~(CARD32)RADEON_BUFFER_ALIGN); -+ ~(uint32_t)RADEON_BUFFER_ALIGN); - - /* Reserve space for the shared back buffer */ - if (info->noBackBuffer) { -@@ -1091,7 +1169,7 @@ RADEONSetupMemXAA_DRI(int scrnIndex, ScreenPtr pScreen) - } else { - info->backOffset = ((info->depthOffset - bufferSize + - RADEON_BUFFER_ALIGN) & -- ~(CARD32)RADEON_BUFFER_ALIGN); -+ ~(uint32_t)RADEON_BUFFER_ALIGN); - } - - info->backY = info->backOffset / width_bytes; -diff --git a/src/radeon_accelfuncs.c b/src/radeon_accelfuncs.c -index e3b37c1..56793cd 100644 ---- a/src/radeon_accelfuncs.c -+++ b/src/radeon_accelfuncs.c -@@ -151,6 +151,11 @@ FUNC_NAME(RADEONSetupForSolidFill)(ScrnInfoPtr pScrn, - | RADEON_DST_Y_TOP_TO_BOTTOM)); - - FINISH_ACCEL(); -+ BEGIN_ACCEL(2); -+ OUT_ACCEL_REG(RADEON_DSTCACHE_CTLSTAT, RADEON_RB2D_DC_FLUSH_ALL); -+ OUT_ACCEL_REG(RADEON_WAIT_UNTIL, -+ RADEON_WAIT_2D_IDLECLEAN | RADEON_WAIT_DMA_GUI_IDLE); -+ FINISH_ACCEL(); - } - - /* Subsequent XAA SolidFillRect -@@ -205,6 +210,11 @@ FUNC_NAME(RADEONSetupForSolidLine)(ScrnInfoPtr pScrn, - OUT_ACCEL_REG(RADEON_DP_WRITE_MASK, planemask); - - FINISH_ACCEL(); -+ BEGIN_ACCEL(2); -+ OUT_ACCEL_REG(RADEON_DSTCACHE_CTLSTAT, RADEON_RB2D_DC_FLUSH_ALL); -+ OUT_ACCEL_REG(RADEON_WAIT_UNTIL, -+ RADEON_WAIT_2D_IDLECLEAN | RADEON_WAIT_DMA_GUI_IDLE); -+ FINISH_ACCEL(); - } - - /* Subsequent XAA solid horizontal and vertical lines */ -@@ -284,7 +294,7 @@ FUNC_NAME(RADEONSetupForDashedLine)(ScrnInfoPtr pScrn, - unsigned char *pattern) - { - RADEONInfoPtr info = RADEONPTR(pScrn); -- CARD32 pat = *(CARD32 *)(pointer)pattern; -+ uint32_t pat = *(uint32_t *)(pointer)pattern; - ACCEL_PREAMBLE(); - - /* Save for determining whether or not to draw last pixel */ -@@ -324,6 +334,11 @@ FUNC_NAME(RADEONSetupForDashedLine)(ScrnInfoPtr pScrn, - OUT_ACCEL_REG(RADEON_BRUSH_DATA0, pat); - - FINISH_ACCEL(); -+ BEGIN_ACCEL(2); -+ OUT_ACCEL_REG(RADEON_DSTCACHE_CTLSTAT, RADEON_RB2D_DC_FLUSH_ALL); -+ OUT_ACCEL_REG(RADEON_WAIT_UNTIL, -+ RADEON_WAIT_2D_IDLECLEAN | RADEON_WAIT_DMA_GUI_IDLE); -+ FINISH_ACCEL(); - } - - /* Helper function to draw last point for dashed lines */ -@@ -333,7 +348,7 @@ FUNC_NAME(RADEONDashedLastPel)(ScrnInfoPtr pScrn, - int fg) - { - RADEONInfoPtr info = RADEONPTR(pScrn); -- CARD32 dp_gui_master_cntl = info->dp_gui_master_cntl_clip; -+ uint32_t dp_gui_master_cntl = info->dp_gui_master_cntl_clip; - ACCEL_PREAMBLE(); - - dp_gui_master_cntl &= ~RADEON_GMC_BRUSH_DATATYPE_MASK; -@@ -358,6 +373,11 @@ FUNC_NAME(RADEONDashedLastPel)(ScrnInfoPtr pScrn, - OUT_ACCEL_REG(RADEON_DP_BRUSH_FRGD_CLR, info->dash_fg); - - FINISH_ACCEL(); -+ BEGIN_ACCEL(2); -+ OUT_ACCEL_REG(RADEON_DSTCACHE_CTLSTAT, RADEON_RB2D_DC_FLUSH_ALL); -+ OUT_ACCEL_REG(RADEON_WAIT_UNTIL, -+ RADEON_WAIT_2D_IDLECLEAN | RADEON_WAIT_DMA_GUI_IDLE); -+ FINISH_ACCEL(); - } - - /* Subsequent XAA dashed line */ -@@ -461,6 +481,11 @@ FUNC_NAME(RADEONSetupForScreenToScreenCopy)(ScrnInfoPtr pScrn, - (ydir >= 0 ? RADEON_DST_Y_TOP_TO_BOTTOM : 0))); - - FINISH_ACCEL(); -+ BEGIN_ACCEL(2); -+ OUT_ACCEL_REG(RADEON_DSTCACHE_CTLSTAT, RADEON_RB2D_DC_FLUSH_ALL); -+ OUT_ACCEL_REG(RADEON_WAIT_UNTIL, -+ RADEON_WAIT_2D_IDLECLEAN | RADEON_WAIT_DMA_GUI_IDLE); -+ FINISH_ACCEL(); - - info->trans_color = trans_color; - FUNC_NAME(RADEONSetTransparency)(pScrn, trans_color); -@@ -548,11 +573,16 @@ FUNC_NAME(RADEONSetupForMono8x8PatternFill)(ScrnInfoPtr pScrn, - OUT_ACCEL_REG(RADEON_BRUSH_DATA0, patternx); - OUT_ACCEL_REG(RADEON_BRUSH_DATA1, patterny); - #else -- OUT_ACCEL_REG(RADEON_BRUSH_DATA0, *(CARD32 *)(pointer)&pattern[0]); -- OUT_ACCEL_REG(RADEON_BRUSH_DATA1, *(CARD32 *)(pointer)&pattern[4]); -+ OUT_ACCEL_REG(RADEON_BRUSH_DATA0, *(uint32_t *)(pointer)&pattern[0]); -+ OUT_ACCEL_REG(RADEON_BRUSH_DATA1, *(uint32_t *)(pointer)&pattern[4]); - #endif - - FINISH_ACCEL(); -+ BEGIN_ACCEL(2); -+ OUT_ACCEL_REG(RADEON_DSTCACHE_CTLSTAT, RADEON_RB2D_DC_FLUSH_ALL); -+ OUT_ACCEL_REG(RADEON_WAIT_UNTIL, -+ RADEON_WAIT_2D_IDLECLEAN | RADEON_WAIT_DMA_GUI_IDLE); -+ FINISH_ACCEL(); - } - - /* Subsequent XAA 8x8 pattern color expansion. Because they are used in -@@ -829,10 +859,10 @@ FUNC_NAME(RADEONSubsequentScanline)(ScrnInfoPtr pScrn, - { - RADEONInfoPtr info = RADEONPTR(pScrn); - #ifdef ACCEL_MMIO -- CARD32 *p = (pointer)info->scratch_buffer[bufno]; -+ uint32_t *p = (pointer)info->scratch_buffer[bufno]; - int i; - int left = info->scanline_words; -- volatile CARD32 *d; -+ volatile uint32_t *d; - ACCEL_PREAMBLE(); - - if (info->scanline_direct) return; -@@ -1086,6 +1116,11 @@ FUNC_NAME(RADEONSetClippingRectangle)(ScrnInfoPtr pScrn, - OUT_ACCEL_REG(RADEON_SC_BOTTOM_RIGHT, tmp2); - - FINISH_ACCEL(); -+ BEGIN_ACCEL(2); -+ OUT_ACCEL_REG(RADEON_DSTCACHE_CTLSTAT, RADEON_RB2D_DC_FLUSH_ALL); -+ OUT_ACCEL_REG(RADEON_WAIT_UNTIL, -+ RADEON_WAIT_2D_IDLECLEAN | RADEON_WAIT_DMA_GUI_IDLE); -+ FINISH_ACCEL(); - - FUNC_NAME(RADEONSetTransparency)(pScrn, info->trans_color); - } -@@ -1105,6 +1140,11 @@ FUNC_NAME(RADEONDisableClipping)(ScrnInfoPtr pScrn) - RADEON_DEFAULT_SC_BOTTOM_MAX)); - - FINISH_ACCEL(); -+ BEGIN_ACCEL(2); -+ OUT_ACCEL_REG(RADEON_DSTCACHE_CTLSTAT, RADEON_RB2D_DC_FLUSH_ALL); -+ OUT_ACCEL_REG(RADEON_WAIT_UNTIL, -+ RADEON_WAIT_2D_IDLECLEAN | RADEON_WAIT_DMA_GUI_IDLE); -+ FINISH_ACCEL(); - - FUNC_NAME(RADEONSetTransparency)(pScrn, info->trans_color); - } -@@ -1302,15 +1342,16 @@ FUNC_NAME(RADEONAccelInit)(ScreenPtr pScreen, XAAInfoRecPtr a) - a->CPUToScreenTextureDstFormats = RADEONDstFormats; - - if (IS_R300_VARIANT || IS_AVIVO_VARIANT) { -- xf86DrvMsg(pScrn->scrnIndex, X_INFO, "Render acceleration " -- "unsupported on Radeon 9500/9700 and newer.\n"); -+ xf86DrvMsg(pScrn->scrnIndex, X_INFO, "XAA Render acceleration " -+ "unsupported on Radeon 9500/9700 and newer. " -+ "Please use EXA instead.\n"); - } else if ((info->ChipFamily == CHIP_FAMILY_RV250) || - (info->ChipFamily == CHIP_FAMILY_RV280) || - (info->ChipFamily == CHIP_FAMILY_RS300) || - (info->ChipFamily == CHIP_FAMILY_R200)) { - a->SetupForCPUToScreenAlphaTexture2 = - FUNC_NAME(R200SetupForCPUToScreenAlphaTexture); -- a->SubsequentCPUToScreenAlphaTexture = -+ a->SubsequentCPUToScreenAlphaTexture = - FUNC_NAME(R200SubsequentCPUToScreenTexture); - - a->SetupForCPUToScreenTexture2 = -diff --git a/src/radeon_atombios.c b/src/radeon_atombios.c -index 88c220b..d667572 100644 ---- a/src/radeon_atombios.c -+++ b/src/radeon_atombios.c -@@ -35,6 +35,8 @@ - #include "radeon_probe.h" - #include "radeon_macros.h" - -+#include "ati_pciids_gen.h" -+ - #include "xorg-server.h" - - /* only for testing now */ -@@ -228,7 +230,7 @@ CailDebug(int scrnIndex, const char *format, ...) - static int - rhdAtomAnalyzeCommonHdr(ATOM_COMMON_TABLE_HEADER *hdr) - { -- if (hdr->usStructureSize == 0xaa55) -+ if (le16_to_cpu(hdr->usStructureSize) == 0xaa55) - return FALSE; - - return TRUE; -@@ -244,24 +246,24 @@ rhdAtomAnalyzeRomHdr(unsigned char *rombase, - return FALSE; - } - xf86DrvMsg(-1,X_NONE,"\tSubsystemVendorID: 0x%4.4x SubsystemID: 0x%4.4x\n", -- hdr->usSubsystemVendorID,hdr->usSubsystemID); -- xf86DrvMsg(-1,X_NONE,"\tIOBaseAddress: 0x%4.4x\n",hdr->usIoBaseAddress); -- xf86DrvMsgVerb(-1,X_NONE,3,"\tFilename: %s\n",rombase + hdr->usConfigFilenameOffset); -+ le16_to_cpu(hdr->usSubsystemVendorID),le16_to_cpu(hdr->usSubsystemID)); -+ xf86DrvMsg(-1,X_NONE,"\tIOBaseAddress: 0x%4.4x\n",le16_to_cpu(hdr->usIoBaseAddress)); -+ xf86DrvMsgVerb(-1,X_NONE,3,"\tFilename: %s\n",rombase + le16_to_cpu(hdr->usConfigFilenameOffset)); - xf86DrvMsgVerb(-1,X_NONE,3,"\tBIOS Bootup Message: %s\n", -- rombase + hdr->usBIOS_BootupMessageOffset); -+ rombase + le16_to_cpu(hdr->usBIOS_BootupMessageOffset)); - -- *data_offset = hdr->usMasterDataTableOffset; -- *command_offset = hdr->usMasterCommandTableOffset; -+ *data_offset = le16_to_cpu(hdr->usMasterDataTableOffset); -+ *command_offset = le16_to_cpu(hdr->usMasterCommandTableOffset); - - return TRUE; - } - - static int --rhdAtomAnalyzeRomDataTable(unsigned char *base, int offset, -+rhdAtomAnalyzeRomDataTable(unsigned char *base, uint16_t offset, - void *ptr,unsigned short *size) - { - ATOM_COMMON_TABLE_HEADER *table = (ATOM_COMMON_TABLE_HEADER *) -- (base + offset); -+ (base + le16_to_cpu(offset)); - - if (!*size || !rhdAtomAnalyzeCommonHdr(table)) { - if (*size) *size -= 2; -@@ -275,8 +277,8 @@ rhdAtomAnalyzeRomDataTable(unsigned char *base, int offset, - - Bool - rhdAtomGetTableRevisionAndSize(ATOM_COMMON_TABLE_HEADER *hdr, -- CARD8 *contentRev, -- CARD8 *formatRev, -+ uint8_t *contentRev, -+ uint8_t *formatRev, - unsigned short *size) - { - if (!hdr) -@@ -284,7 +286,7 @@ rhdAtomGetTableRevisionAndSize(ATOM_COMMON_TABLE_HEADER *hdr, - - if (contentRev) *contentRev = hdr->ucTableContentRevision; - if (formatRev) *formatRev = hdr->ucTableFormatRevision; -- if (size) *size = (short)hdr->usStructureSize -+ if (size) *size = (short)le16_to_cpu(hdr->usStructureSize) - - sizeof(ATOM_COMMON_TABLE_HEADER); - return TRUE; - } -@@ -358,8 +360,8 @@ rhdAtomGetDataTable(int scrnIndex, - unsigned int BIOSImageSize) - { - unsigned int data_offset; -- unsigned int atom_romhdr_off = *(unsigned short*) -- (base + OFFSET_TO_POINTER_TO_ATOM_ROM_HEADER); -+ unsigned int atom_romhdr_off = le16_to_cpu(*(unsigned short*) -+ (base + OFFSET_TO_POINTER_TO_ATOM_ROM_HEADER)); - ATOM_ROM_HEADER *atom_rom_hdr = - (ATOM_ROM_HEADER *)(base + atom_romhdr_off); - -@@ -454,7 +456,7 @@ rhdAtomAllocateFbScratch(atomBiosHandlePtr handle, - } - if (fb_base && fb_size && size) { - /* 4k align */ -- fb_size = (fb_size & ~(CARD32)0xfff) + ((fb_size & 0xfff) ? 1 : 0); -+ fb_size = (fb_size & ~(uint32_t)0xfff) + ((fb_size & 0xfff) ? 1 : 0); - if ((fb_base + fb_size) > (start + size)) { - xf86DrvMsg(handle->scrnIndex, X_WARNING, - "%s: FW FB scratch area %i (size: %i)" -@@ -490,7 +492,7 @@ rhdAtomAllocateFbScratch(atomBiosHandlePtr handle, - } - - # ifdef ATOM_BIOS_PARSER --static Bool -+Bool - rhdAtomASICInit(atomBiosHandlePtr handle) - { - ASIC_INIT_PS_ALLOCATION asicInit; -@@ -499,11 +501,11 @@ rhdAtomASICInit(atomBiosHandlePtr handle) - RHDAtomBiosFunc(handle->scrnIndex, handle, - GET_DEFAULT_ENGINE_CLOCK, - &data); -- asicInit.sASICInitClocks.ulDefaultEngineClock = data.val / 10;/*in 10 Khz*/ -+ asicInit.sASICInitClocks.ulDefaultEngineClock = cpu_to_le32(data.val / 10);/*in 10 Khz*/ - RHDAtomBiosFunc(handle->scrnIndex, handle, - GET_DEFAULT_MEMORY_CLOCK, - &data); -- asicInit.sASICInitClocks.ulDefaultMemoryClock = data.val / 10;/*in 10 Khz*/ -+ asicInit.sASICInitClocks.ulDefaultMemoryClock = cpu_to_le32(data.val / 10);/*in 10 Khz*/ - data.exec.dataSpace = NULL; - data.exec.index = 0x0; - data.exec.pspace = &asicInit; -@@ -517,25 +519,52 @@ rhdAtomASICInit(atomBiosHandlePtr handle) - return FALSE; - } - --Bool --rhdAtomSetScaler(atomBiosHandlePtr handle, unsigned char scalerID, int setting) -+int -+atombios_dyn_clk_setup(ScrnInfoPtr pScrn, int enable) - { -- ENABLE_SCALER_PARAMETERS scaler; -+ RADEONInfoPtr info = RADEONPTR(pScrn); -+ DYNAMIC_CLOCK_GATING_PS_ALLOCATION dynclk_data; - AtomBiosArgRec data; -+ unsigned char *space; - -- scaler.ucScaler = scalerID; -- scaler.ucEnable = setting; -- data.exec.dataSpace = NULL; -- data.exec.index = 0x21; -- data.exec.pspace = &scaler; -- xf86DrvMsg(handle->scrnIndex, X_INFO, "Calling EnableScaler\n"); -- if (RHDAtomBiosFunc(handle->scrnIndex, handle, -- ATOMBIOS_EXEC, &data) == ATOM_SUCCESS) { -- xf86DrvMsg(handle->scrnIndex, X_INFO, "EnableScaler Successful\n"); -- return TRUE; -+ dynclk_data.ucEnable = enable; -+ -+ data.exec.index = GetIndexIntoMasterTable(COMMAND, DynamicClockGating); -+ data.exec.dataSpace = (void *)&space; -+ data.exec.pspace = &dynclk_data; -+ -+ if (RHDAtomBiosFunc(info->atomBIOS->scrnIndex, info->atomBIOS, ATOMBIOS_EXEC, &data) == ATOM_SUCCESS) { -+ ErrorF("Dynamic clock gating %s success\n", enable? "enable" : "disable"); -+ return ATOM_SUCCESS; - } -- xf86DrvMsg(handle->scrnIndex, X_INFO, "EableScaler Failed\n"); -- return FALSE; -+ -+ ErrorF("Dynamic clock gating %s failure\n", enable? "enable" : "disable"); -+ return ATOM_NOT_IMPLEMENTED; -+ -+} -+ -+int -+atombios_static_pwrmgt_setup(ScrnInfoPtr pScrn, int enable) -+{ -+ RADEONInfoPtr info = RADEONPTR(pScrn); -+ ENABLE_ASIC_STATIC_PWR_MGT_PS_ALLOCATION pwrmgt_data; -+ AtomBiosArgRec data; -+ unsigned char *space; -+ -+ pwrmgt_data.ucEnable = enable; -+ -+ data.exec.index = GetIndexIntoMasterTable(COMMAND, EnableASIC_StaticPwrMgt); -+ data.exec.dataSpace = (void *)&space; -+ data.exec.pspace = &pwrmgt_data; -+ -+ if (RHDAtomBiosFunc(info->atomBIOS->scrnIndex, info->atomBIOS, ATOMBIOS_EXEC, &data) == ATOM_SUCCESS) { -+ ErrorF("Static power management %s success\n", enable? "enable" : "disable"); -+ return ATOM_SUCCESS; -+ } -+ -+ ErrorF("Static power management %s failure\n", enable? "enable" : "disable"); -+ return ATOM_NOT_IMPLEMENTED; -+ - } - - # endif -@@ -546,69 +575,30 @@ rhdAtomInit(atomBiosHandlePtr unused1, AtomBiosRequestID unused2, - { - int scrnIndex = data->val; - RADEONInfoPtr info = RADEONPTR(xf86Screens[scrnIndex]); -- unsigned char *ptr; - atomDataTablesPtr atomDataPtr; - unsigned int cmd_offset; - atomBiosHandlePtr handle = NULL; - unsigned int BIOSImageSize = 0; - data->atomhandle = NULL; - -- //RHDFUNCI(scrnIndex); -- -- /*if (info->BIOSCopy) { -- xf86DrvMsg(scrnIndex,X_INFO,"Getting BIOS copy from INT10\n"); -- ptr = info->BIOSCopy; -- info->BIOSCopy = NULL; -- -- BIOSImageSize = ptr[2] * 512; -- if (BIOSImageSize > legacyBIOSMax) { -- xf86DrvMsg(scrnIndex,X_ERROR,"Invalid BIOS length field\n"); -- return ATOM_FAILED; -- } -- } else*/ { -- /*if (!xf86IsEntityPrimary(info->entityIndex)) { -- if (!(BIOSImageSize = RHDReadPCIBios(info, &ptr))) -- return ATOM_FAILED; -- } else*/ { -- int read_len; -- unsigned char tmp[32]; -- xf86DrvMsg(scrnIndex,X_INFO,"Getting BIOS copy from legacy VBIOS location\n"); -- if (xf86ReadBIOS(legacyBIOSLocation, 0, tmp, 32) < 0) { -- xf86DrvMsg(scrnIndex,X_ERROR, -- "Cannot obtain POSTed BIOS header\n"); -- return ATOM_FAILED; -- } -- BIOSImageSize = tmp[2] * 512; -- if (BIOSImageSize > legacyBIOSMax) { -- xf86DrvMsg(scrnIndex,X_ERROR,"Invalid BIOS length field\n"); -- return ATOM_FAILED; -- } -- if (!(ptr = xcalloc(1,BIOSImageSize))) { -- xf86DrvMsg(scrnIndex,X_ERROR, -- "Cannot allocate %i bytes of memory " -- "for BIOS image\n",BIOSImageSize); -- return ATOM_FAILED; -- } -- if ((read_len = xf86ReadBIOS(legacyBIOSLocation, 0, ptr, BIOSImageSize) -- < 0)) { -- xf86DrvMsg(scrnIndex,X_ERROR,"Cannot read POSTed BIOS\n"); -- goto error; -- } -- } -- } -+#ifdef XSERVER_LIBPCIACCESS -+ BIOSImageSize = info->PciInfo->rom_size > RADEON_VBIOS_SIZE ? info->PciInfo->rom_size : RADEON_VBIOS_SIZE; -+#else -+ BIOSImageSize = RADEON_VBIOS_SIZE; -+#endif - - if (!(atomDataPtr = xcalloc(1, sizeof(atomDataTables)))) { - xf86DrvMsg(scrnIndex,X_ERROR,"Cannot allocate memory for " - "ATOM BIOS data tabes\n"); - goto error; - } -- if (!rhdAtomGetDataTable(scrnIndex, ptr, atomDataPtr, &cmd_offset, BIOSImageSize)) -+ if (!rhdAtomGetDataTable(scrnIndex, info->VBIOS, atomDataPtr, &cmd_offset, BIOSImageSize)) - goto error1; - if (!(handle = xcalloc(1, sizeof(atomBiosHandleRec)))) { - xf86DrvMsg(scrnIndex,X_ERROR,"Cannot allocate memory\n"); - goto error1; - } -- handle->BIOSBase = ptr; -+ handle->BIOSBase = info->VBIOS; - handle->atomDataPtr = atomDataPtr; - handle->cmd_offset = cmd_offset; - handle->scrnIndex = scrnIndex; -@@ -619,24 +609,12 @@ rhdAtomInit(atomBiosHandlePtr unused1, AtomBiosRequestID unused2, - #endif - handle->BIOSImageSize = BIOSImageSize; - --# if ATOM_BIOS_PARSER -- /* Try to find out if BIOS has been posted (either by system or int10 */ -- if (!rhdAtomGetFbBaseAndSize(handle, NULL, NULL)) { -- /* run AsicInit */ -- if (!rhdAtomASICInit(handle)) -- xf86DrvMsg(scrnIndex, X_WARNING, -- "%s: AsicInit failed. Won't be able to obtain in VRAM " -- "FB scratch space\n",__func__); -- } --# endif -- - data->atomhandle = handle; - return ATOM_SUCCESS; - - error1: - xfree(atomDataPtr); - error: -- xfree(ptr); - return ATOM_FAILED; - } - -@@ -658,19 +636,25 @@ rhdAtomVramInfoQuery(atomBiosHandlePtr handle, AtomBiosRequestID func, - AtomBiosArgPtr data) - { - atomDataTablesPtr atomDataPtr; -- CARD32 *val = &data->val; -+ uint32_t *val = &data->val; - //RHDFUNC(handle); - - atomDataPtr = handle->atomDataPtr; - - switch (func) { - case GET_FW_FB_START: -- *val = atomDataPtr->VRAM_UsageByFirmware -- ->asFirmwareVramReserveInfo[0].ulStartAddrUsedByFirmware; -+ if (atomDataPtr->VRAM_UsageByFirmware) -+ *val = le32_to_cpu(atomDataPtr->VRAM_UsageByFirmware -+ ->asFirmwareVramReserveInfo[0].ulStartAddrUsedByFirmware); -+ else -+ return ATOM_NOT_IMPLEMENTED; - break; - case GET_FW_FB_SIZE: -- *val = atomDataPtr->VRAM_UsageByFirmware -- ->asFirmwareVramReserveInfo[0].usFirmwareUseInKb; -+ if (atomDataPtr->VRAM_UsageByFirmware) -+ *val = le16_to_cpu(atomDataPtr->VRAM_UsageByFirmware -+ ->asFirmwareVramReserveInfo[0].usFirmwareUseInKb); -+ else -+ return ATOM_NOT_IMPLEMENTED; - break; - default: - return ATOM_NOT_IMPLEMENTED; -@@ -683,7 +667,7 @@ rhdAtomTmdsInfoQuery(atomBiosHandlePtr handle, - AtomBiosRequestID func, AtomBiosArgPtr data) - { - atomDataTablesPtr atomDataPtr; -- CARD32 *val = &data->val; -+ uint32_t *val = &data->val; - int idx = *val; - - atomDataPtr = handle->atomDataPtr; -@@ -697,7 +681,7 @@ rhdAtomTmdsInfoQuery(atomBiosHandlePtr handle, - - switch (func) { - case ATOM_TMDS_FREQUENCY: -- *val = atomDataPtr->TMDS_Info->asMiscInfo[idx].usFrequency; -+ *val = le16_to_cpu(atomDataPtr->TMDS_Info->asMiscInfo[idx].usFrequency); - break; - case ATOM_TMDS_PLL_CHARGE_PUMP: - *val = atomDataPtr->TMDS_Info->asMiscInfo[idx].ucPLL_ChargePump; -@@ -732,20 +716,20 @@ rhdAtomDTDTimings(atomBiosHandlePtr handle, ATOM_DTD_FORMAT *dtd) - if (!(mode = (DisplayModePtr)xcalloc(1,sizeof(DisplayModeRec)))) - return NULL; - -- mode->CrtcHDisplay = mode->HDisplay = dtd->usHActive; -- mode->CrtcVDisplay = mode->VDisplay = dtd->usVActive; -+ mode->CrtcHDisplay = mode->HDisplay = le16_to_cpu(dtd->usHActive); -+ mode->CrtcVDisplay = mode->VDisplay = le16_to_cpu(dtd->usVActive); - mode->CrtcHBlankStart = dtd->usHActive + dtd->ucHBorder; -- mode->CrtcHBlankEnd = mode->CrtcHBlankStart + dtd->usHBlanking_Time; -+ mode->CrtcHBlankEnd = mode->CrtcHBlankStart + le16_to_cpu(dtd->usHBlanking_Time); - mode->CrtcHTotal = mode->HTotal = mode->CrtcHBlankEnd + dtd->ucHBorder; - mode->CrtcVBlankStart = dtd->usVActive + dtd->ucVBorder; -- mode->CrtcVBlankEnd = mode->CrtcVBlankStart + dtd->usVBlanking_Time; -+ mode->CrtcVBlankEnd = mode->CrtcVBlankStart + le16_to_cpu(dtd->usVBlanking_Time); - mode->CrtcVTotal = mode->VTotal = mode->CrtcVBlankEnd + dtd->ucVBorder; -- mode->CrtcHSyncStart = mode->HSyncStart = dtd->usHActive + dtd->usHSyncOffset; -- mode->CrtcHSyncEnd = mode->HSyncEnd = mode->HSyncStart + dtd->usHSyncWidth; -- mode->CrtcVSyncStart = mode->VSyncStart = dtd->usVActive + dtd->usVSyncOffset; -- mode->CrtcVSyncEnd = mode->VSyncEnd = mode->VSyncStart + dtd->usVSyncWidth; -+ mode->CrtcHSyncStart = mode->HSyncStart = dtd->usHActive + le16_to_cpu(dtd->usHSyncOffset); -+ mode->CrtcHSyncEnd = mode->HSyncEnd = mode->HSyncStart + le16_to_cpu(dtd->usHSyncWidth); -+ mode->CrtcVSyncStart = mode->VSyncStart = dtd->usVActive + le16_to_cpu(dtd->usVSyncOffset); -+ mode->CrtcVSyncEnd = mode->VSyncEnd = mode->VSyncStart + le16_to_cpu(dtd->usVSyncWidth); - -- mode->SynthClock = mode->Clock = dtd->usPixClk * 10; -+ mode->SynthClock = mode->Clock = le16_to_cpu(dtd->usPixClk) * 10; - - mode->HSync = ((float) mode->Clock) / ((float)mode->HTotal); - mode->VRefresh = (1000.0 * ((float) mode->Clock)) -@@ -778,7 +762,7 @@ rhdAtomDTDTimings(atomBiosHandlePtr handle, ATOM_DTD_FORMAT *dtd) - } - - static unsigned char* --rhdAtomLvdsDDC(atomBiosHandlePtr handle, CARD32 offset, unsigned char *record) -+rhdAtomLvdsDDC(atomBiosHandlePtr handle, uint32_t offset, unsigned char *record) - { - unsigned char *EDIDBlock; - -@@ -848,7 +832,7 @@ rhdAtomCVGetTimings(atomBiosHandlePtr handle, AtomBiosRequestID func, - AtomBiosArgPtr data) - { - atomDataTablesPtr atomDataPtr; -- CARD8 crev, frev; -+ uint8_t crev, frev; - DisplayModePtr last = NULL; - DisplayModePtr new = NULL; - DisplayModePtr first = NULL; -@@ -938,7 +922,7 @@ rhdAtomLvdsGetTimings(atomBiosHandlePtr handle, AtomBiosRequestID func, - AtomBiosArgPtr data) - { - atomDataTablesPtr atomDataPtr; -- CARD8 crev, frev; -+ uint8_t crev, frev; - unsigned long offset; - - //RHDFUNC(handle); -@@ -977,15 +961,15 @@ rhdAtomLvdsGetTimings(atomBiosHandlePtr handle, AtomBiosRequestID func, - case ATOMBIOS_GET_PANEL_EDID: - offset = (unsigned long)&atomDataPtr->LVDS_Info.base - - (unsigned long)handle->BIOSBase -- + atomDataPtr->LVDS_Info -- .LVDS_Info_v12->usExtInfoTableOffset; -+ + le16_to_cpu(atomDataPtr->LVDS_Info -+ .LVDS_Info_v12->usExtInfoTableOffset); - - data->EDIDBlock - = rhdAtomLvdsDDC(handle, offset, - (unsigned char *) - &atomDataPtr->LVDS_Info.base -- + atomDataPtr->LVDS_Info -- .LVDS_Info_v12->usExtInfoTableOffset); -+ + le16_to_cpu(atomDataPtr->LVDS_Info -+ .LVDS_Info_v12->usExtInfoTableOffset)); - if (data->EDIDBlock) - return ATOM_SUCCESS; - default: -@@ -1002,8 +986,8 @@ rhdAtomLvdsInfoQuery(atomBiosHandlePtr handle, - AtomBiosRequestID func, AtomBiosArgPtr data) - { - atomDataTablesPtr atomDataPtr; -- CARD8 crev, frev; -- CARD32 *val = &data->val; -+ uint8_t crev, frev; -+ uint32_t *val = &data->val; - - //RHDFUNC(handle); - -@@ -1019,12 +1003,12 @@ rhdAtomLvdsInfoQuery(atomBiosHandlePtr handle, - case 1: - switch (func) { - case ATOM_LVDS_SUPPORTED_REFRESH_RATE: -- *val = atomDataPtr->LVDS_Info -- .LVDS_Info->usSupportedRefreshRate; -+ *val = le16_to_cpu(atomDataPtr->LVDS_Info -+ .LVDS_Info->usSupportedRefreshRate); - break; - case ATOM_LVDS_OFF_DELAY: -- *val = atomDataPtr->LVDS_Info -- .LVDS_Info->usOffDelayInMs; -+ *val = le16_to_cpu(atomDataPtr->LVDS_Info -+ .LVDS_Info->usOffDelayInMs); - break; - case ATOM_LVDS_SEQ_DIG_ONTO_DE: - *val = atomDataPtr->LVDS_Info -@@ -1061,12 +1045,12 @@ rhdAtomLvdsInfoQuery(atomBiosHandlePtr handle, - case 2: - switch (func) { - case ATOM_LVDS_SUPPORTED_REFRESH_RATE: -- *val = atomDataPtr->LVDS_Info -- .LVDS_Info_v12->usSupportedRefreshRate; -+ *val = le16_to_cpu(atomDataPtr->LVDS_Info -+ .LVDS_Info_v12->usSupportedRefreshRate); - break; - case ATOM_LVDS_OFF_DELAY: -- *val = atomDataPtr->LVDS_Info -- .LVDS_Info_v12->usOffDelayInMs; -+ *val = le16_to_cpu(atomDataPtr->LVDS_Info -+ .LVDS_Info_v12->usOffDelayInMs); - break; - case ATOM_LVDS_SEQ_DIG_ONTO_DE: - *val = atomDataPtr->LVDS_Info -@@ -1112,8 +1096,8 @@ rhdAtomCompassionateDataQuery(atomBiosHandlePtr handle, - AtomBiosRequestID func, AtomBiosArgPtr data) - { - atomDataTablesPtr atomDataPtr; -- CARD8 crev, frev; -- CARD32 *val = &data->val; -+ uint8_t crev, frev; -+ uint32_t *val = &data->val; - - //RHDFUNC(handle); - -@@ -1169,8 +1153,8 @@ rhdAtomGPIOI2CInfoQuery(atomBiosHandlePtr handle, - AtomBiosRequestID func, AtomBiosArgPtr data) - { - atomDataTablesPtr atomDataPtr; -- CARD8 crev, frev; -- CARD32 *val = &data->val; -+ uint8_t crev, frev; -+ uint32_t *val = &data->val; - unsigned short size; - - //RHDFUNC(handle); -@@ -1194,8 +1178,8 @@ rhdAtomGPIOI2CInfoQuery(atomBiosHandlePtr handle, - return ATOM_FAILED; - } - -- *val = atomDataPtr->GPIO_I2C_Info->asGPIO_Info[*val] -- .usClkMaskRegisterIndex; -+ *val = le16_to_cpu(atomDataPtr->GPIO_I2C_Info->asGPIO_Info[*val] -+ .usClkMaskRegisterIndex); - break; - - default: -@@ -1209,8 +1193,8 @@ rhdAtomFirmwareInfoQuery(atomBiosHandlePtr handle, - AtomBiosRequestID func, AtomBiosArgPtr data) - { - atomDataTablesPtr atomDataPtr; -- CARD8 crev, frev; -- CARD32 *val = &data->val; -+ uint8_t crev, frev; -+ uint32_t *val = &data->val; - - //RHDFUNC(handle); - -@@ -1226,35 +1210,35 @@ rhdAtomFirmwareInfoQuery(atomBiosHandlePtr handle, - case 1: - switch (func) { - case GET_DEFAULT_ENGINE_CLOCK: -- *val = atomDataPtr->FirmwareInfo -- .FirmwareInfo->ulDefaultEngineClock * 10; -+ *val = le32_to_cpu(atomDataPtr->FirmwareInfo -+ .FirmwareInfo->ulDefaultEngineClock) * 10; - break; - case GET_DEFAULT_MEMORY_CLOCK: -- *val = atomDataPtr->FirmwareInfo -- .FirmwareInfo->ulDefaultMemoryClock * 10; -+ *val = le32_to_cpu(atomDataPtr->FirmwareInfo -+ .FirmwareInfo->ulDefaultMemoryClock) * 10; - break; - case GET_MAX_PIXEL_CLOCK_PLL_OUTPUT: -- *val = atomDataPtr->FirmwareInfo -- .FirmwareInfo->ulMaxPixelClockPLL_Output * 10; -+ *val = le32_to_cpu(atomDataPtr->FirmwareInfo -+ .FirmwareInfo->ulMaxPixelClockPLL_Output) * 10; - break; - case GET_MIN_PIXEL_CLOCK_PLL_OUTPUT: -- *val = atomDataPtr->FirmwareInfo -- .FirmwareInfo->usMinPixelClockPLL_Output * 10; -+ *val = le16_to_cpu(atomDataPtr->FirmwareInfo -+ .FirmwareInfo->usMinPixelClockPLL_Output) * 10; - case GET_MAX_PIXEL_CLOCK_PLL_INPUT: -- *val = atomDataPtr->FirmwareInfo -- .FirmwareInfo->usMaxPixelClockPLL_Input * 10; -+ *val = le16_to_cpu(atomDataPtr->FirmwareInfo -+ .FirmwareInfo->usMaxPixelClockPLL_Input) * 10; - break; - case GET_MIN_PIXEL_CLOCK_PLL_INPUT: -- *val = atomDataPtr->FirmwareInfo -- .FirmwareInfo->usMinPixelClockPLL_Input * 10; -+ *val = le16_to_cpu(atomDataPtr->FirmwareInfo -+ .FirmwareInfo->usMinPixelClockPLL_Input) * 10; - break; - case GET_MAX_PIXEL_CLK: -- *val = atomDataPtr->FirmwareInfo -- .FirmwareInfo->usMaxPixelClock * 10; -+ *val = le16_to_cpu(atomDataPtr->FirmwareInfo -+ .FirmwareInfo->usMaxPixelClock) * 10; - break; - case GET_REF_CLOCK: -- *val = atomDataPtr->FirmwareInfo -- .FirmwareInfo->usReferenceClock * 10; -+ *val = le16_to_cpu(atomDataPtr->FirmwareInfo -+ .FirmwareInfo->usReferenceClock) * 10; - break; - default: - return ATOM_NOT_IMPLEMENTED; -@@ -1262,36 +1246,36 @@ rhdAtomFirmwareInfoQuery(atomBiosHandlePtr handle, - case 2: - switch (func) { - case GET_DEFAULT_ENGINE_CLOCK: -- *val = atomDataPtr->FirmwareInfo -- .FirmwareInfo_V_1_2->ulDefaultEngineClock * 10; -+ *val = le32_to_cpu(atomDataPtr->FirmwareInfo -+ .FirmwareInfo_V_1_2->ulDefaultEngineClock) * 10; - break; - case GET_DEFAULT_MEMORY_CLOCK: -- *val = atomDataPtr->FirmwareInfo -- .FirmwareInfo_V_1_2->ulDefaultMemoryClock * 10; -+ *val = le32_to_cpu(atomDataPtr->FirmwareInfo -+ .FirmwareInfo_V_1_2->ulDefaultMemoryClock) * 10; - break; - case GET_MAX_PIXEL_CLOCK_PLL_OUTPUT: -- *val = atomDataPtr->FirmwareInfo -- .FirmwareInfo_V_1_2->ulMaxPixelClockPLL_Output * 10; -+ *val = le32_to_cpu(atomDataPtr->FirmwareInfo -+ .FirmwareInfo_V_1_2->ulMaxPixelClockPLL_Output) * 10; - break; - case GET_MIN_PIXEL_CLOCK_PLL_OUTPUT: -- *val = atomDataPtr->FirmwareInfo -- .FirmwareInfo_V_1_2->usMinPixelClockPLL_Output * 10; -+ *val = le16_to_cpu(atomDataPtr->FirmwareInfo -+ .FirmwareInfo_V_1_2->usMinPixelClockPLL_Output) * 10; - break; - case GET_MAX_PIXEL_CLOCK_PLL_INPUT: -- *val = atomDataPtr->FirmwareInfo -- .FirmwareInfo_V_1_2->usMaxPixelClockPLL_Input * 10; -+ *val = le16_to_cpu(atomDataPtr->FirmwareInfo -+ .FirmwareInfo_V_1_2->usMaxPixelClockPLL_Input) * 10; - break; - case GET_MIN_PIXEL_CLOCK_PLL_INPUT: -- *val = atomDataPtr->FirmwareInfo -- .FirmwareInfo_V_1_2->usMinPixelClockPLL_Input * 10; -+ *val = le16_to_cpu(atomDataPtr->FirmwareInfo -+ .FirmwareInfo_V_1_2->usMinPixelClockPLL_Input) * 10; - break; - case GET_MAX_PIXEL_CLK: -- *val = atomDataPtr->FirmwareInfo -- .FirmwareInfo_V_1_2->usMaxPixelClock * 10; -+ *val = le16_to_cpu(atomDataPtr->FirmwareInfo -+ .FirmwareInfo_V_1_2->usMaxPixelClock) * 10; - break; - case GET_REF_CLOCK: -- *val = atomDataPtr->FirmwareInfo -- .FirmwareInfo_V_1_2->usReferenceClock * 10; -+ *val = le16_to_cpu(atomDataPtr->FirmwareInfo -+ .FirmwareInfo_V_1_2->usReferenceClock) * 10; - break; - default: - return ATOM_NOT_IMPLEMENTED; -@@ -1300,36 +1284,36 @@ rhdAtomFirmwareInfoQuery(atomBiosHandlePtr handle, - case 3: - switch (func) { - case GET_DEFAULT_ENGINE_CLOCK: -- *val = atomDataPtr->FirmwareInfo -- .FirmwareInfo_V_1_3->ulDefaultEngineClock * 10; -+ *val = le32_to_cpu(atomDataPtr->FirmwareInfo -+ .FirmwareInfo_V_1_3->ulDefaultEngineClock) * 10; - break; - case GET_DEFAULT_MEMORY_CLOCK: -- *val = atomDataPtr->FirmwareInfo -- .FirmwareInfo_V_1_3->ulDefaultMemoryClock * 10; -+ *val = le32_to_cpu(atomDataPtr->FirmwareInfo -+ .FirmwareInfo_V_1_3->ulDefaultMemoryClock) * 10; - break; - case GET_MAX_PIXEL_CLOCK_PLL_OUTPUT: -- *val = atomDataPtr->FirmwareInfo -- .FirmwareInfo_V_1_3->ulMaxPixelClockPLL_Output * 10; -+ *val = le32_to_cpu(atomDataPtr->FirmwareInfo -+ .FirmwareInfo_V_1_3->ulMaxPixelClockPLL_Output) * 10; - break; - case GET_MIN_PIXEL_CLOCK_PLL_OUTPUT: -- *val = atomDataPtr->FirmwareInfo -- .FirmwareInfo_V_1_3->usMinPixelClockPLL_Output * 10; -+ *val = le16_to_cpu(atomDataPtr->FirmwareInfo -+ .FirmwareInfo_V_1_3->usMinPixelClockPLL_Output) * 10; - break; - case GET_MAX_PIXEL_CLOCK_PLL_INPUT: -- *val = atomDataPtr->FirmwareInfo -- .FirmwareInfo_V_1_3->usMaxPixelClockPLL_Input * 10; -+ *val = le16_to_cpu(atomDataPtr->FirmwareInfo -+ .FirmwareInfo_V_1_3->usMaxPixelClockPLL_Input) * 10; - break; - case GET_MIN_PIXEL_CLOCK_PLL_INPUT: -- *val = atomDataPtr->FirmwareInfo -- .FirmwareInfo_V_1_3->usMinPixelClockPLL_Input * 10; -+ *val = le16_to_cpu(atomDataPtr->FirmwareInfo -+ .FirmwareInfo_V_1_3->usMinPixelClockPLL_Input) * 10; - break; - case GET_MAX_PIXEL_CLK: -- *val = atomDataPtr->FirmwareInfo -- .FirmwareInfo_V_1_3->usMaxPixelClock * 10; -+ *val = le16_to_cpu(atomDataPtr->FirmwareInfo -+ .FirmwareInfo_V_1_3->usMaxPixelClock) * 10; - break; - case GET_REF_CLOCK: -- *val = atomDataPtr->FirmwareInfo -- .FirmwareInfo_V_1_3->usReferenceClock * 10; -+ *val = le16_to_cpu(atomDataPtr->FirmwareInfo -+ .FirmwareInfo_V_1_3->usReferenceClock) * 10; - break; - default: - return ATOM_NOT_IMPLEMENTED; -@@ -1338,36 +1322,36 @@ rhdAtomFirmwareInfoQuery(atomBiosHandlePtr handle, - case 4: - switch (func) { - case GET_DEFAULT_ENGINE_CLOCK: -- *val = atomDataPtr->FirmwareInfo -- .FirmwareInfo_V_1_4->ulDefaultEngineClock * 10; -+ *val = le32_to_cpu(atomDataPtr->FirmwareInfo -+ .FirmwareInfo_V_1_4->ulDefaultEngineClock) * 10; - break; - case GET_DEFAULT_MEMORY_CLOCK: -- *val = atomDataPtr->FirmwareInfo -- .FirmwareInfo_V_1_4->ulDefaultMemoryClock * 10; -+ *val = le32_to_cpu(atomDataPtr->FirmwareInfo -+ .FirmwareInfo_V_1_4->ulDefaultMemoryClock) * 10; - break; - case GET_MAX_PIXEL_CLOCK_PLL_INPUT: -- *val = atomDataPtr->FirmwareInfo -- .FirmwareInfo_V_1_4->usMaxPixelClockPLL_Input * 10; -+ *val = le16_to_cpu(atomDataPtr->FirmwareInfo -+ .FirmwareInfo_V_1_4->usMaxPixelClockPLL_Input) * 10; - break; - case GET_MIN_PIXEL_CLOCK_PLL_INPUT: -- *val = atomDataPtr->FirmwareInfo -- .FirmwareInfo_V_1_4->usMinPixelClockPLL_Input * 10; -+ *val = le16_to_cpu(atomDataPtr->FirmwareInfo -+ .FirmwareInfo_V_1_4->usMinPixelClockPLL_Input) * 10; - break; - case GET_MAX_PIXEL_CLOCK_PLL_OUTPUT: -- *val = atomDataPtr->FirmwareInfo -- .FirmwareInfo_V_1_4->ulMaxPixelClockPLL_Output * 10; -+ *val = le32_to_cpu(atomDataPtr->FirmwareInfo -+ .FirmwareInfo_V_1_4->ulMaxPixelClockPLL_Output) * 10; - break; - case GET_MIN_PIXEL_CLOCK_PLL_OUTPUT: -- *val = atomDataPtr->FirmwareInfo -- .FirmwareInfo_V_1_4->usMinPixelClockPLL_Output * 10; -+ *val = le16_to_cpu(atomDataPtr->FirmwareInfo -+ .FirmwareInfo_V_1_4->usMinPixelClockPLL_Output) * 10; - break; - case GET_MAX_PIXEL_CLK: -- *val = atomDataPtr->FirmwareInfo -- .FirmwareInfo_V_1_4->usMaxPixelClock * 10; -+ *val = le16_to_cpu(atomDataPtr->FirmwareInfo -+ .FirmwareInfo_V_1_4->usMaxPixelClock) * 10; - break; - case GET_REF_CLOCK: -- *val = atomDataPtr->FirmwareInfo -- .FirmwareInfo_V_1_4->usReferenceClock * 10; -+ *val = le16_to_cpu(atomDataPtr->FirmwareInfo -+ .FirmwareInfo_V_1_4->usReferenceClock) * 10; - break; - default: - return ATOM_NOT_IMPLEMENTED; -@@ -1399,7 +1383,7 @@ const int object_connector_convert[] = - CONNECTOR_NONE, - CONNECTOR_NONE, - CONNECTOR_NONE, -- CONNECTOR_NONE, -+ CONNECTOR_DISPLAY_PORT, - }; - - static void -@@ -1434,13 +1418,13 @@ rhdAtomParseI2CRecord(atomBiosHandlePtr handle, - } - - static RADEONI2CBusRec --RADEONLookupGPIOLineForDDC(ScrnInfoPtr pScrn, CARD8 id) -+RADEONLookupGPIOLineForDDC(ScrnInfoPtr pScrn, uint8_t id) - { - RADEONInfoPtr info = RADEONPTR (pScrn); - atomDataTablesPtr atomDataPtr; - ATOM_GPIO_I2C_ASSIGMENT gpio; - RADEONI2CBusRec i2c; -- CARD8 crev, frev; -+ uint8_t crev, frev; - - memset(&i2c, 0, sizeof(RADEONI2CBusRec)); - i2c.valid = FALSE; -@@ -1455,12 +1439,12 @@ RADEONLookupGPIOLineForDDC(ScrnInfoPtr pScrn, CARD8 id) - } - - gpio = atomDataPtr->GPIO_I2C_Info->asGPIO_Info[id]; -- i2c.mask_clk_reg = gpio.usClkMaskRegisterIndex * 4; -- i2c.mask_data_reg = gpio.usDataMaskRegisterIndex * 4; -- i2c.put_clk_reg = gpio.usClkEnRegisterIndex * 4; -- i2c.put_data_reg = gpio.usDataEnRegisterIndex * 4; -- i2c.get_clk_reg = gpio.usClkY_RegisterIndex * 4; -- i2c.get_data_reg = gpio.usDataY_RegisterIndex * 4; -+ i2c.mask_clk_reg = le16_to_cpu(gpio.usClkMaskRegisterIndex) * 4; -+ i2c.mask_data_reg = le16_to_cpu(gpio.usDataMaskRegisterIndex) * 4; -+ i2c.put_clk_reg = le16_to_cpu(gpio.usClkEnRegisterIndex) * 4; -+ i2c.put_data_reg = le16_to_cpu(gpio.usDataEnRegisterIndex) * 4; -+ i2c.get_clk_reg = le16_to_cpu(gpio.usClkY_RegisterIndex) * 4; -+ i2c.get_data_reg = le16_to_cpu(gpio.usDataY_RegisterIndex) * 4; - i2c.mask_clk_mask = (1 << gpio.ucClkMaskShift); - i2c.mask_data_mask = (1 << gpio.ucDataMaskShift); - i2c.put_clk_mask = (1 << gpio.ucClkEnShift); -@@ -1495,10 +1479,11 @@ Bool - RADEONGetATOMConnectorInfoFromBIOSObject (ScrnInfoPtr pScrn) - { - RADEONInfoPtr info = RADEONPTR (pScrn); -- CARD8 crev, frev; -+ uint8_t crev, frev; - unsigned short size; - atomDataTablesPtr atomDataPtr; - ATOM_CONNECTOR_OBJECT_TABLE *con_obj; -+ ATOM_INTEGRATED_SYSTEM_INFO_V2 *igp_obj = NULL; - int i, j, ddc_line = 0; - - atomDataPtr = info->atomBIOS->atomDataPtr; -@@ -1507,38 +1492,63 @@ RADEONGetATOMConnectorInfoFromBIOSObject (ScrnInfoPtr pScrn) - - if (crev < 2) - return FALSE; -- -+ - con_obj = (ATOM_CONNECTOR_OBJECT_TABLE *) - ((char *)&atomDataPtr->Object_Header->sHeader + -- atomDataPtr->Object_Header->usConnectorObjectTableOffset); -+ le16_to_cpu(atomDataPtr->Object_Header->usConnectorObjectTableOffset)); - - for (i = 0; i < con_obj->ucNumberOfObjects; i++) { - ATOM_SRC_DST_TABLE_FOR_ONE_OBJECT *SrcDstTable; - ATOM_COMMON_RECORD_HEADER *Record; -- CARD8 obj_id, num, obj_type; -+ uint8_t obj_id, num, obj_type; - int record_base; -+ uint16_t con_obj_id = le16_to_cpu(con_obj->asObjects[i].usObjectID); - -- obj_id = (con_obj->asObjects[i].usObjectID & OBJECT_ID_MASK) >> OBJECT_ID_SHIFT; -- num = (con_obj->asObjects[i].usObjectID & ENUM_ID_MASK) >> ENUM_ID_SHIFT; -- obj_type = (con_obj->asObjects[i].usObjectID & OBJECT_TYPE_MASK) >> OBJECT_TYPE_SHIFT; -+ obj_id = (con_obj_id & OBJECT_ID_MASK) >> OBJECT_ID_SHIFT; -+ num = (con_obj_id & ENUM_ID_MASK) >> ENUM_ID_SHIFT; -+ obj_type = (con_obj_id & OBJECT_TYPE_MASK) >> OBJECT_TYPE_SHIFT; - if (obj_type != GRAPH_OBJECT_TYPE_CONNECTOR) - continue; - - SrcDstTable = (ATOM_SRC_DST_TABLE_FOR_ONE_OBJECT *) - ((char *)&atomDataPtr->Object_Header->sHeader -- + con_obj->asObjects[i].usSrcDstTableOffset); -- -+ + le16_to_cpu(con_obj->asObjects[i].usSrcDstTableOffset)); -+ - ErrorF("object id %04x %02x\n", obj_id, SrcDstTable->ucNumberOfSrc); -- info->BiosConnector[i].ConnectorType = object_connector_convert[obj_id]; -- info->BiosConnector[i].valid = TRUE; -+ -+ if ((info->ChipFamily == CHIP_FAMILY_RS780) && -+ (obj_id == CONNECTOR_OBJECT_ID_PCIE_CONNECTOR)) { -+ uint32_t slot_config, ct; -+ -+ igp_obj = info->atomBIOS->atomDataPtr->IntegratedSystemInfo.IntegratedSystemInfo_v2; -+ -+ if (!igp_obj) -+ info->BiosConnector[i].ConnectorType = object_connector_convert[obj_id]; -+ else { -+ if (num == 1) -+ slot_config = igp_obj->ulDDISlot1Config; -+ else -+ slot_config = igp_obj->ulDDISlot2Config; -+ -+ ct = (slot_config >> 16) & 0xff; -+ info->BiosConnector[i].ConnectorType = object_connector_convert[ct]; -+ info->BiosConnector[i].igp_lane_info = slot_config & 0xffff; -+ } -+ } else -+ info->BiosConnector[i].ConnectorType = object_connector_convert[obj_id]; -+ -+ if (info->BiosConnector[i].ConnectorType == CONNECTOR_NONE) -+ info->BiosConnector[i].valid = FALSE; -+ else -+ info->BiosConnector[i].valid = TRUE; - info->BiosConnector[i].devices = 0; - - for (j = 0; j < SrcDstTable->ucNumberOfSrc; j++) { -- CARD8 sobj_id; -+ uint8_t sobj_id; - - sobj_id = (SrcDstTable->usSrcObjectID[j] & OBJECT_ID_MASK) >> OBJECT_ID_SHIFT; - ErrorF("src object id %04x %d\n", SrcDstTable->usSrcObjectID[j], sobj_id); -- -+ - switch(sobj_id) { - case ENCODER_OBJECT_ID_INTERNAL_LVDS: - info->BiosConnector[i].devices |= (1 << ATOM_DEVICE_LCD1_INDEX); -@@ -1548,6 +1558,13 @@ RADEONGetATOMConnectorInfoFromBIOSObject (ScrnInfoPtr pScrn) - info->BiosConnector[i].devices |= (1 << ATOM_DEVICE_DFP1_INDEX); - info->BiosConnector[i].TMDSType = TMDS_INT; - break; -+ case ENCODER_OBJECT_ID_INTERNAL_UNIPHY: -+ if (num == 1) -+ info->BiosConnector[i].devices |= (1 << ATOM_DEVICE_DFP1_INDEX); -+ else -+ info->BiosConnector[i].devices |= (1 << ATOM_DEVICE_DFP2_INDEX); -+ info->BiosConnector[i].TMDSType = TMDS_UNIPHY; -+ break; - case ENCODER_OBJECT_ID_INTERNAL_TMDS2: - case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1: - info->BiosConnector[i].devices |= (1 << ATOM_DEVICE_DFP2_INDEX); -@@ -1560,7 +1577,13 @@ RADEONGetATOMConnectorInfoFromBIOSObject (ScrnInfoPtr pScrn) - break; - case ENCODER_OBJECT_ID_INTERNAL_DAC1: - case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1: -- info->BiosConnector[i].devices |= (1 << ATOM_DEVICE_CRT1_INDEX); -+ if (info->BiosConnector[i].ConnectorType == CONNECTOR_DIN || -+ info->BiosConnector[i].ConnectorType == CONNECTOR_STV || -+ info->BiosConnector[i].ConnectorType == CONNECTOR_CTV) -+ //info->BiosConnector[i].devices |= (1 << ATOM_DEVICE_TV1_INDEX); -+ info->BiosConnector[i].valid = FALSE; -+ else -+ info->BiosConnector[i].devices |= (1 << ATOM_DEVICE_CRT1_INDEX); - info->BiosConnector[i].DACType = DAC_PRIMARY; - break; - case ENCODER_OBJECT_ID_INTERNAL_DAC2: -@@ -1568,7 +1591,8 @@ RADEONGetATOMConnectorInfoFromBIOSObject (ScrnInfoPtr pScrn) - if (info->BiosConnector[i].ConnectorType == CONNECTOR_DIN || - info->BiosConnector[i].ConnectorType == CONNECTOR_STV || - info->BiosConnector[i].ConnectorType == CONNECTOR_CTV) -- info->BiosConnector[i].devices |= (1 << ATOM_DEVICE_TV1_INDEX); -+ //info->BiosConnector[i].devices |= (1 << ATOM_DEVICE_TV1_INDEX); -+ info->BiosConnector[i].valid = FALSE; - else - info->BiosConnector[i].devices |= (1 << ATOM_DEVICE_CRT2_INDEX); - info->BiosConnector[i].DACType = DAC_TVDAC; -@@ -1578,9 +1602,9 @@ RADEONGetATOMConnectorInfoFromBIOSObject (ScrnInfoPtr pScrn) - - Record = (ATOM_COMMON_RECORD_HEADER *) - ((char *)&atomDataPtr->Object_Header->sHeader -- + con_obj->asObjects[i].usRecordOffset); -+ + le16_to_cpu(con_obj->asObjects[i].usRecordOffset)); - -- record_base = con_obj->asObjects[i].usRecordOffset; -+ record_base = le16_to_cpu(con_obj->asObjects[i].usRecordOffset); - - while (Record->ucRecordType > 0 - && Record->ucRecordType <= ATOM_MAX_OBJECT_RECORD_NUMBER ) { -@@ -1588,7 +1612,7 @@ RADEONGetATOMConnectorInfoFromBIOSObject (ScrnInfoPtr pScrn) - ErrorF("record type %d\n", Record->ucRecordType); - switch (Record->ucRecordType) { - case ATOM_I2C_RECORD_TYPE: -- rhdAtomParseI2CRecord(info->atomBIOS, -+ rhdAtomParseI2CRecord(info->atomBIOS, - (ATOM_I2C_RECORD *)Record, - &ddc_line); - info->BiosConnector[i].ddc_i2c = atom_setup_i2c_bus(ddc_line); -@@ -1687,33 +1711,58 @@ RADEONATOMGetTVTimings(ScrnInfoPtr pScrn, int index, SET_CRTC_TIMING_PARAMETERS_ - if (index > MAX_SUPPORTED_TV_TIMING) - return FALSE; - -- crtc_timing->usH_Total = tv_info->aModeTimings[index].usCRTC_H_Total; -- crtc_timing->usH_Disp = tv_info->aModeTimings[index].usCRTC_H_Disp; -- crtc_timing->usH_SyncStart = tv_info->aModeTimings[index].usCRTC_H_SyncStart; -- crtc_timing->usH_SyncWidth = tv_info->aModeTimings[index].usCRTC_H_SyncWidth; -+ crtc_timing->usH_Total = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_H_Total); -+ crtc_timing->usH_Disp = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_H_Disp); -+ crtc_timing->usH_SyncStart = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_H_SyncStart); -+ crtc_timing->usH_SyncWidth = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_H_SyncWidth); - -- crtc_timing->usV_Total = tv_info->aModeTimings[index].usCRTC_V_Total; -- crtc_timing->usV_Disp = tv_info->aModeTimings[index].usCRTC_V_Disp; -- crtc_timing->usV_SyncStart = tv_info->aModeTimings[index].usCRTC_V_SyncStart; -- crtc_timing->usV_SyncWidth = tv_info->aModeTimings[index].usCRTC_V_SyncWidth; -+ crtc_timing->usV_Total = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_V_Total); -+ crtc_timing->usV_Disp = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_V_Disp); -+ crtc_timing->usV_SyncStart = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_V_SyncStart); -+ crtc_timing->usV_SyncWidth = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_V_SyncWidth); - - crtc_timing->susModeMiscInfo = tv_info->aModeTimings[index].susModeMiscInfo; - -- crtc_timing->ucOverscanRight = tv_info->aModeTimings[index].usCRTC_OverscanRight; -- crtc_timing->ucOverscanLeft = tv_info->aModeTimings[index].usCRTC_OverscanLeft; -- crtc_timing->ucOverscanBottom = tv_info->aModeTimings[index].usCRTC_OverscanBottom; -- crtc_timing->ucOverscanTop = tv_info->aModeTimings[index].usCRTC_OverscanTop; -- *pixel_clock = tv_info->aModeTimings[index].usPixelClock * 10; -+ crtc_timing->ucOverscanRight = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_OverscanRight); -+ crtc_timing->ucOverscanLeft = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_OverscanLeft); -+ crtc_timing->ucOverscanBottom = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_OverscanBottom); -+ crtc_timing->ucOverscanTop = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_OverscanTop); -+ *pixel_clock = le16_to_cpu(tv_info->aModeTimings[index].usPixelClock) * 10; - - return TRUE; - } - -+static void RADEONApplyATOMQuirks(ScrnInfoPtr pScrn, int index) -+{ -+ RADEONInfoPtr info = RADEONPTR (pScrn); -+ -+ /* Asus M2A-VM HDMI board lists the DVI port as HDMI */ -+ if ((info->Chipset == PCI_CHIP_RS690_791E) && -+ (PCI_SUB_VENDOR_ID(info->PciInfo) == 0x1043) && -+ (PCI_SUB_DEVICE_ID(info->PciInfo) == 0x826d)) { -+ if ((info->BiosConnector[index].ConnectorType == CONNECTOR_HDMI_TYPE_A) && -+ (info->BiosConnector[index].TMDSType == TMDS_LVTMA)) { -+ info->BiosConnector[index].ConnectorType = CONNECTOR_DVI_D; -+ } -+ } -+ -+ /* Falcon NW laptop lists vga ddc line for LVDS */ -+ if ((info->Chipset == PCI_CHIP_RV410_5653) && -+ (PCI_SUB_VENDOR_ID(info->PciInfo) == 0x1462) && -+ (PCI_SUB_DEVICE_ID(info->PciInfo) == 0x0291)) { -+ if (info->BiosConnector[index].ConnectorType == CONNECTOR_LVDS) { -+ info->BiosConnector[index].ddc_i2c.valid = FALSE; -+ } -+ } -+ -+} -+ - Bool - RADEONGetATOMConnectorInfoFromBIOSConnectorTable (ScrnInfoPtr pScrn) - { - RADEONInfoPtr info = RADEONPTR (pScrn); - atomDataTablesPtr atomDataPtr; -- CARD8 crev, frev; -+ uint8_t crev, frev; - int i, j; - - atomDataPtr = info->atomBIOS->atomDataPtr; -@@ -1729,8 +1778,8 @@ RADEONGetATOMConnectorInfoFromBIOSConnectorTable (ScrnInfoPtr pScrn) - ATOM_CONNECTOR_INFO_I2C ci - = atomDataPtr->SupportedDevicesInfo.SupportedDevicesInfo->asConnInfo[i]; - -- if (!(atomDataPtr->SupportedDevicesInfo -- .SupportedDevicesInfo->usDeviceSupport & (1 << i))) { -+ if (!(le16_to_cpu(atomDataPtr->SupportedDevicesInfo -+ .SupportedDevicesInfo->usDeviceSupport) & (1 << i))) { - info->BiosConnector[i].valid = FALSE; - continue; - } -@@ -1742,16 +1791,24 @@ RADEONGetATOMConnectorInfoFromBIOSConnectorTable (ScrnInfoPtr pScrn) - continue; - } - #endif -+#if 1 -+ if (i == ATOM_DEVICE_TV1_INDEX) { -+ xf86DrvMsg(pScrn->scrnIndex, X_INFO, "Skipping TV-Out\n"); -+ info->BiosConnector[i].valid = FALSE; -+ continue; -+ } -+#endif - - info->BiosConnector[i].valid = TRUE; - info->BiosConnector[i].output_id = ci.sucI2cId.sbfAccess.bfI2C_LineMux; -- if (info->IsIGP && (i == ATOM_DEVICE_DFP2_INDEX)) -- info->BiosConnector[i].devices = (1 << ATOM_DEVICE_DFP3_INDEX); -- else if (info->IsIGP && (i == ATOM_DEVICE_DFP3_INDEX)) -- info->BiosConnector[i].devices = (1 << ATOM_DEVICE_DFP2_INDEX); -- else -- info->BiosConnector[i].devices = (1 << i); -+ info->BiosConnector[i].devices = (1 << i); - info->BiosConnector[i].ConnectorType = ci.sucConnectorInfo.sbfAccess.bfConnectorType; -+ -+ if (info->BiosConnector[i].ConnectorType == CONNECTOR_NONE) { -+ info->BiosConnector[i].valid = FALSE; -+ continue; -+ } -+ - info->BiosConnector[i].DACType = ci.sucConnectorInfo.sbfAccess.bfAssociatedDAC; - - /* don't assign a gpio for tv */ -@@ -1759,14 +1816,16 @@ RADEONGetATOMConnectorInfoFromBIOSConnectorTable (ScrnInfoPtr pScrn) - (i == ATOM_DEVICE_TV2_INDEX) || - (i == ATOM_DEVICE_CV_INDEX)) - info->BiosConnector[i].ddc_i2c.valid = FALSE; -- else if ((i == ATOM_DEVICE_DFP3_INDEX) && info->IsIGP) { -- /* DDIA port uses non-standard gpio entry */ -- if (info->BiosConnector[ATOM_DEVICE_DFP2_INDEX].valid) -+ else if ((info->ChipFamily == CHIP_FAMILY_RS600) || -+ (info->ChipFamily == CHIP_FAMILY_RS690) || -+ (info->ChipFamily == CHIP_FAMILY_RS740)) { -+ /* IGP DFP ports use non-standard gpio entries */ -+ if ((i == ATOM_DEVICE_DFP2_INDEX) || (i == ATOM_DEVICE_DFP3_INDEX)) - info->BiosConnector[i].ddc_i2c = -- RADEONLookupGPIOLineForDDC(pScrn, ci.sucI2cId.sbfAccess.bfI2C_LineMux + 2); -+ RADEONLookupGPIOLineForDDC(pScrn, ci.sucI2cId.sbfAccess.bfI2C_LineMux + 1); - else - info->BiosConnector[i].ddc_i2c = -- RADEONLookupGPIOLineForDDC(pScrn, ci.sucI2cId.sbfAccess.bfI2C_LineMux + 1); -+ RADEONLookupGPIOLineForDDC(pScrn, ci.sucI2cId.sbfAccess.bfI2C_LineMux); - } else - info->BiosConnector[i].ddc_i2c = - RADEONLookupGPIOLineForDDC(pScrn, ci.sucI2cId.sbfAccess.bfI2C_LineMux); -@@ -1774,16 +1833,15 @@ RADEONGetATOMConnectorInfoFromBIOSConnectorTable (ScrnInfoPtr pScrn) - if (i == ATOM_DEVICE_DFP1_INDEX) - info->BiosConnector[i].TMDSType = TMDS_INT; - else if (i == ATOM_DEVICE_DFP2_INDEX) { -- if (info->IsIGP) -- info->BiosConnector[i].TMDSType = TMDS_LVTMA; -- else -- info->BiosConnector[i].TMDSType = TMDS_EXT; -- } else if (i == ATOM_DEVICE_DFP3_INDEX) { -- if (info->IsIGP) -+ if ((info->ChipFamily == CHIP_FAMILY_RS600) || -+ (info->ChipFamily == CHIP_FAMILY_RS690) || -+ (info->ChipFamily == CHIP_FAMILY_RS740)) - info->BiosConnector[i].TMDSType = TMDS_DDIA; - else -- info->BiosConnector[i].TMDSType = TMDS_LVTMA; -- } else -+ info->BiosConnector[i].TMDSType = TMDS_EXT; -+ } else if (i == ATOM_DEVICE_DFP3_INDEX) -+ info->BiosConnector[i].TMDSType = TMDS_LVTMA; -+ else - info->BiosConnector[i].TMDSType = TMDS_NONE; - - /* Always set the connector type to VGA for CRT1/CRT2. if they are -@@ -1816,6 +1874,9 @@ RADEONGetATOMConnectorInfoFromBIOSConnectorTable (ScrnInfoPtr pScrn) - } else { - info->BiosConnector[i].hpd_mask = 0; - } -+ -+ RADEONApplyATOMQuirks(pScrn, i); -+ - } - - /* CRTs/DFPs may share a port */ -@@ -1859,689 +1920,6 @@ RADEONGetATOMConnectorInfoFromBIOSConnectorTable (ScrnInfoPtr pScrn) - return TRUE; - } - --#if 0 --#define RHD_CONNECTORS_MAX 4 --#define MAX_OUTPUTS_PER_CONNECTOR 2 -- --#define Limit(n,max,name) ((n >= max) ? ( \ -- xf86DrvMsg(handle->scrnIndex,X_ERROR,"%s: %s %i exceeds maximum %i\n", \ -- __func__,name,n,max), TRUE) : FALSE) -- --static const struct _rhd_connector_objs --{ -- char *name; -- RADEONConnectorTypeATOM con; --} rhd_connector_objs[] = { -- { "NONE", CONNECTOR_NONE_ATOM }, -- { "SINGLE_LINK_DVI_I", CONNECTOR_DVI_I_ATOM }, -- { "DUAL_LINK_DVI_I", CONNECTOR_DVI_I_ATOM }, -- { "SINGLE_LINK_DVI_D", CONNECTOR_DVI_D_ATOM }, -- { "DUAL_LINK_DVI_D", CONNECTOR_DVI_D_ATOM }, -- { "VGA", CONNECTOR_VGA_ATOM }, -- { "COMPOSITE", CONNECTOR_CTV_ATOM }, -- { "SVIDEO", CONNECTOR_STV_ATOM }, -- { "D_CONNECTOR", CONNECTOR_NONE_ATOM }, -- { "9PIN_DIN", CONNECTOR_NONE_ATOM }, -- { "SCART", CONNECTOR_SCART_ATOM }, -- { "HDMI_TYPE_A", CONNECTOR_HDMI_TYPE_A_ATOM }, -- { "HDMI_TYPE_B", CONNECTOR_HDMI_TYPE_B_ATOM }, -- { "HDMI_TYPE_B", CONNECTOR_HDMI_TYPE_B_ATOM }, -- { "LVDS", CONNECTOR_LVDS_ATOM }, -- { "7PIN_DIN", CONNECTOR_STV_ATOM }, -- { "PCIE_CONNECTOR", CONNECTOR_NONE_ATOM }, -- { "CROSSFIRE", CONNECTOR_NONE_ATOM }, -- { "HARDCODE_DVI", CONNECTOR_NONE_ATOM }, -- { "DISPLAYPORT", CONNECTOR_DISPLAY_PORT_ATOM } --}; --static const int n_rhd_connector_objs = sizeof (rhd_connector_objs) / sizeof(struct _rhd_connector_objs); -- --static const struct _rhd_encoders --{ -- char *name; -- RADEONOutputTypeATOM ot; --} rhd_encoders[] = { -- { "NONE", OUTPUT_NONE_ATOM }, -- { "INTERNAL_LVDS", OUTPUT_LVDS_ATOM }, -- { "INTERNAL_TMDS1", OUTPUT_TMDSA_ATOM }, -- { "INTERNAL_TMDS2", OUTPUT_TMDSB_ATOM }, -- { "INTERNAL_DAC1", OUTPUT_DACA_ATOM }, -- { "INTERNAL_DAC2", OUTPUT_DACB_ATOM }, -- { "INTERNAL_SDVOA", OUTPUT_NONE_ATOM }, -- { "INTERNAL_SDVOB", OUTPUT_NONE_ATOM }, -- { "SI170B", OUTPUT_NONE_ATOM }, -- { "CH7303", OUTPUT_NONE_ATOM }, -- { "CH7301", OUTPUT_NONE_ATOM }, -- { "INTERNAL_DVO1", OUTPUT_NONE_ATOM }, -- { "EXTERNAL_SDVOA", OUTPUT_NONE_ATOM }, -- { "EXTERNAL_SDVOB", OUTPUT_NONE_ATOM }, -- { "TITFP513", OUTPUT_NONE_ATOM }, -- { "INTERNAL_LVTM1", OUTPUT_LVTMA_ATOM }, -- { "VT1623", OUTPUT_NONE_ATOM }, -- { "HDMI_SI1930", OUTPUT_NONE_ATOM }, -- { "HDMI_INTERNAL", OUTPUT_NONE_ATOM }, -- { "INTERNAL_KLDSCP_TMDS1", OUTPUT_TMDSA_ATOM }, -- { "INTERNAL_KLSCP_DVO1", OUTPUT_NONE_ATOM }, -- { "INTERNAL_KLDSCP_DAC1", OUTPUT_DACA_ATOM }, -- { "INTERNAL_KLDSCP_DAC2", OUTPUT_DACB_ATOM }, -- { "SI178", OUTPUT_NONE_ATOM }, -- { "MVPU_FPGA", OUTPUT_NONE_ATOM }, -- { "INTERNAL_DDI", OUTPUT_NONE_ATOM }, -- { "VT1625", OUTPUT_NONE_ATOM }, -- { "HDMI_SI1932", OUTPUT_NONE_ATOM }, -- { "AN9801", OUTPUT_NONE_ATOM }, -- { "DP501", OUTPUT_NONE_ATOM }, --}; --static const int n_rhd_encoders = sizeof (rhd_encoders) / sizeof(struct _rhd_encoders); -- --static const struct _rhd_connectors --{ -- char *name; -- RADEONConnectorTypeATOM con; -- Bool dual; --} rhd_connectors[] = { -- {"NONE", CONNECTOR_NONE_ATOM, FALSE }, -- {"VGA", CONNECTOR_VGA_ATOM, FALSE }, -- {"DVI-I", CONNECTOR_DVI_I_ATOM, TRUE }, -- {"DVI-D", CONNECTOR_DVI_D_ATOM, FALSE }, -- {"DVI-A", CONNECTOR_DVI_A_ATOM, FALSE }, -- {"SVIDEO", CONNECTOR_STV_ATOM, FALSE }, -- {"COMPOSITE", CONNECTOR_CTV_ATOM, FALSE }, -- {"PANEL", CONNECTOR_LVDS_ATOM, FALSE }, -- {"DIGITAL_LINK", CONNECTOR_DIGITAL_ATOM, FALSE }, -- {"SCART", CONNECTOR_SCART_ATOM, FALSE }, -- {"HDMI Type A", CONNECTOR_HDMI_TYPE_A_ATOM, FALSE }, -- {"HDMI Type B", CONNECTOR_HDMI_TYPE_B_ATOM, FALSE }, -- {"UNKNOWN", CONNECTOR_NONE_ATOM, FALSE }, -- {"UNKNOWN", CONNECTOR_NONE_ATOM, FALSE }, -- {"DVI+DIN", CONNECTOR_NONE_ATOM, FALSE } --}; --static const int n_rhd_connectors = sizeof(rhd_connectors) / sizeof(struct _rhd_connectors); -- --static const struct _rhd_devices --{ -- char *name; -- RADEONOutputTypeATOM ot; --} rhd_devices[] = { -- {" CRT1", OUTPUT_NONE_ATOM }, -- {" LCD1", OUTPUT_LVTMA_ATOM }, -- {" TV1", OUTPUT_NONE_ATOM }, -- {" DFP1", OUTPUT_TMDSA_ATOM }, -- {" CRT2", OUTPUT_NONE_ATOM }, -- {" LCD2", OUTPUT_LVTMA_ATOM }, -- {" TV2", OUTPUT_NONE_ATOM }, -- {" DFP2", OUTPUT_LVTMA_ATOM }, -- {" CV", OUTPUT_NONE_ATOM }, -- {" DFP3", OUTPUT_LVTMA_ATOM } --}; --static const int n_rhd_devices = sizeof(rhd_devices) / sizeof(struct _rhd_devices); -- --static const rhdDDC hwddc[] = { RHD_DDC_0, RHD_DDC_1, RHD_DDC_2, RHD_DDC_3 }; --static const int n_hwddc = sizeof(hwddc) / sizeof(rhdDDC); -- --static const rhdOutputType acc_dac[] = { OUTPUT_NONE_ATOM, -- OUTPUT_DACA_ATOM, -- OUTPUT_DACB_ATOM, -- OUTPUT_DAC_EXTERNAL_ATOM }; --static const int n_acc_dac = sizeof(acc_dac) / sizeof (rhdOutputType); -- --/* -- * -- */ --static Bool --rhdAtomInterpretObjectID(atomBiosHandlePtr handle, -- CARD16 id, CARD8 *obj_type, CARD8 *obj_id, -- CARD8 *num, char **name) --{ -- *obj_id = (id & OBJECT_ID_MASK) >> OBJECT_ID_SHIFT; -- *num = (id & ENUM_ID_MASK) >> ENUM_ID_SHIFT; -- *obj_type = (id & OBJECT_TYPE_MASK) >> OBJECT_TYPE_SHIFT; -- -- *name = NULL; -- -- switch (*obj_type) { -- case GRAPH_OBJECT_TYPE_CONNECTOR: -- if (!Limit(*obj_id, n_rhd_connector_objs, "obj_id")) -- *name = rhd_connector_objs[*obj_id].name; -- break; -- case GRAPH_OBJECT_TYPE_ENCODER: -- if (!Limit(*obj_id, n_rhd_encoders, "obj_id")) -- *name = rhd_encoders[*obj_id].name; -- break; -- default: -- break; -- } -- return TRUE; --} -- --/* -- * -- */ --static void --rhdAtomDDCFromI2CRecord(atomBiosHandlePtr handle, -- ATOM_I2C_RECORD *Record, rhdDDC *DDC) --{ -- RHDDebug(handle->scrnIndex, -- " %s: I2C Record: %s[%x] EngineID: %x I2CAddr: %x\n", -- __func__, -- Record->sucI2cId.bfHW_Capable ? "HW_Line" : "GPIO_ID", -- Record->sucI2cId.bfI2C_LineMux, -- Record->sucI2cId.bfHW_EngineID, -- Record->ucI2CAddr); -- -- if (!*(unsigned char *)&(Record->sucI2cId)) -- *DDC = RHD_DDC_NONE; -- else { -- -- if (Record->ucI2CAddr != 0) -- return; -- -- if (Record->sucI2cId.bfHW_Capable) { -- -- *DDC = (rhdDDC)Record->sucI2cId.bfI2C_LineMux; -- if (*DDC >= RHD_DDC_MAX) -- *DDC = RHD_DDC_NONE; -- -- } else { -- *DDC = RHD_DDC_GPIO; -- /* add GPIO pin parsing */ -- } -- } --} -- --/* -- * -- */ --static void --rhdAtomParseGPIOLutForHPD(atomBiosHandlePtr handle, -- CARD8 pinID, rhdHPD *HPD) --{ -- atomDataTablesPtr atomDataPtr; -- ATOM_GPIO_PIN_LUT *gpio_pin_lut; -- unsigned short size; -- int i = 0; -- -- //RHDFUNC(handle); -- -- atomDataPtr = handle->atomDataPtr; -- -- *HPD = RHD_HPD_NONE; -- -- if (!rhdAtomGetTableRevisionAndSize( -- &atomDataPtr->GPIO_Pin_LUT->sHeader, NULL, NULL, &size)) { -- xf86DrvMsg(handle->scrnIndex, X_ERROR, -- "%s: No valid GPIO pin LUT in AtomBIOS\n",__func__); -- return; -- } -- gpio_pin_lut = atomDataPtr->GPIO_Pin_LUT; -- -- while (1) { -- if (gpio_pin_lut->asGPIO_Pin[i].ucGPIO_ID == pinID) { -- -- if ((sizeof(ATOM_COMMON_TABLE_HEADER) -- + (i * sizeof(ATOM_GPIO_PIN_ASSIGNMENT))) > size) -- return; -- -- RHDDebug(handle->scrnIndex, -- " %s: GPIO PinID: %i Index: %x Shift: %i\n", -- __func__, -- pinID, -- gpio_pin_lut->asGPIO_Pin[i].usGpioPin_AIndex, -- gpio_pin_lut->asGPIO_Pin[i].ucGpioPinBitShift); -- -- /* grr... map backwards: register indices -> line numbers */ -- if (gpio_pin_lut->asGPIO_Pin[i].usGpioPin_AIndex -- == (DC_GPIO_HPD_A >> 2)) { -- switch (gpio_pin_lut->asGPIO_Pin[i].ucGpioPinBitShift) { -- case 0: -- *HPD = RHD_HPD_0; -- return; -- case 8: -- *HPD = RHD_HPD_1; -- return; -- case 16: -- *HPD = RHD_HPD_2; -- return; -- } -- } -- } -- i++; -- } --} -- --/* -- * -- */ --static void --rhdAtomHPDFromRecord(atomBiosHandlePtr handle, -- ATOM_HPD_INT_RECORD *Record, rhdHPD *HPD) --{ -- RHDDebug(handle->scrnIndex, -- " %s: HPD Record: GPIO ID: %x Plugged_PinState: %x\n", -- __func__, -- Record->ucHPDIntGPIOID, -- Record->ucPluggged_PinState); -- rhdAtomParseGPIOLutForHPD(handle, Record->ucHPDIntGPIOID, HPD); --} -- --/* -- * -- */ --static char * --rhdAtomDeviceTagsFromRecord(atomBiosHandlePtr handle, -- ATOM_CONNECTOR_DEVICE_TAG_RECORD *Record) --{ -- int i, j, k; -- char *devices; -- -- //RHDFUNC(handle); -- -- RHDDebug(handle->scrnIndex," NumberOfDevice: %i\n", -- Record->ucNumberOfDevice); -- -- if (!Record->ucNumberOfDevice) return NULL; -- -- devices = (char *)xcalloc(Record->ucNumberOfDevice * 4 + 1,1); -- -- for (i = 0; i < Record->ucNumberOfDevice; i++) { -- k = 0; -- j = Record->asDeviceTag[i].usDeviceID; -- -- while (!(j & 0x1)) { j >>= 1; k++; }; -- -- if (!Limit(k,n_rhd_devices,"usDeviceID")) -- strcat(devices, rhd_devices[k].name); -- } -- -- RHDDebug(handle->scrnIndex," Devices:%s\n",devices); -- -- return devices; --} -- --/* -- * -- */ --static AtomBiosResult --rhdAtomConnectorInfoFromObjectHeader(atomBiosHandlePtr handle, -- rhdConnectorInfoPtr *ptr) --{ -- atomDataTablesPtr atomDataPtr; -- CARD8 crev, frev; -- ATOM_CONNECTOR_OBJECT_TABLE *con_obj; -- rhdConnectorInfoPtr cp; -- unsigned long object_header_end; -- int ncon = 0; -- int i,j; -- unsigned short object_header_size; -- -- //RHDFUNC(handle); -- -- atomDataPtr = handle->atomDataPtr; -- -- if (!rhdAtomGetTableRevisionAndSize( -- &atomDataPtr->Object_Header->sHeader, -- &crev,&frev,&object_header_size)) { -- return ATOM_NOT_IMPLEMENTED; -- } -- -- if (crev < 2) /* don't bother with anything below rev 2 */ -- return ATOM_NOT_IMPLEMENTED; -- -- if (!(cp = (rhdConnectorInfoPtr)xcalloc(sizeof(struct rhdConnectorInfo), -- RHD_CONNECTORS_MAX))) -- return ATOM_FAILED; -- -- object_header_end = -- atomDataPtr->Object_Header->usConnectorObjectTableOffset -- + object_header_size; -- -- RHDDebug(handle->scrnIndex,"ObjectTable - size: %u, BIOS - size: %u " -- "TableOffset: %u object_header_end: %u\n", -- object_header_size, handle->BIOSImageSize, -- atomDataPtr->Object_Header->usConnectorObjectTableOffset, -- object_header_end); -- -- if ((object_header_size > handle->BIOSImageSize) -- || (atomDataPtr->Object_Header->usConnectorObjectTableOffset -- > handle->BIOSImageSize) -- || object_header_end > handle->BIOSImageSize) { -- xf86DrvMsg(handle->scrnIndex, X_ERROR, -- "%s: Object table information is bogus\n",__func__); -- return ATOM_FAILED; -- } -- -- if (((unsigned long)&atomDataPtr->Object_Header->sHeader -- + object_header_end) > ((unsigned long)handle->BIOSBase -- + handle->BIOSImageSize)) { -- xf86DrvMsg(handle->scrnIndex, X_ERROR, -- "%s: Object table extends beyond BIOS Image\n",__func__); -- return ATOM_FAILED; -- } -- -- con_obj = (ATOM_CONNECTOR_OBJECT_TABLE *) -- ((char *)&atomDataPtr->Object_Header->sHeader + -- atomDataPtr->Object_Header->usConnectorObjectTableOffset); -- -- for (i = 0; i < con_obj->ucNumberOfObjects; i++) { -- ATOM_SRC_DST_TABLE_FOR_ONE_OBJECT *SrcDstTable; -- ATOM_COMMON_RECORD_HEADER *Record; -- int record_base; -- CARD8 obj_type, obj_id, num; -- char *name; -- int nout = 0; -- -- rhdAtomInterpretObjectID(handle, con_obj->asObjects[i].usObjectID, -- &obj_type, &obj_id, &num, &name); -- -- RHDDebug(handle->scrnIndex, "Object: ID: %x name: %s type: %x id: %x\n", -- con_obj->asObjects[i].usObjectID, name ? name : "", -- obj_type, obj_id); -- -- -- if (obj_type != GRAPH_OBJECT_TYPE_CONNECTOR) -- continue; -- -- SrcDstTable = (ATOM_SRC_DST_TABLE_FOR_ONE_OBJECT *) -- ((char *)&atomDataPtr->Object_Header->sHeader -- + con_obj->asObjects[i].usSrcDstTableOffset); -- -- if (con_obj->asObjects[i].usSrcDstTableOffset -- + (SrcDstTable->ucNumberOfSrc -- * sizeof(ATOM_SRC_DST_TABLE_FOR_ONE_OBJECT)) -- > handle->BIOSImageSize) { -- xf86DrvMsg(handle->scrnIndex, X_ERROR, "%s: SrcDstTable[%i] extends " -- "beyond Object_Header table\n",__func__,i); -- continue; -- } -- -- cp[ncon].Type = rhd_connector_objs[obj_id].con; -- cp[ncon].Name = RhdAppendString(cp[ncon].Name,name); -- -- for (j = 0; j < SrcDstTable->ucNumberOfSrc; j++) { -- CARD8 stype, sobj_id, snum; -- char *sname; -- -- rhdAtomInterpretObjectID(handle, SrcDstTable->usSrcObjectID[j], -- &stype, &sobj_id, &snum, &sname); -- -- RHDDebug(handle->scrnIndex, " * SrcObject: ID: %x name: %s\n", -- SrcDstTable->usSrcObjectID[j], sname); -- -- cp[ncon].Output[nout] = rhd_encoders[sobj_id].ot; -- if (++nout >= MAX_OUTPUTS_PER_CONNECTOR) -- break; -- } -- -- Record = (ATOM_COMMON_RECORD_HEADER *) -- ((char *)&atomDataPtr->Object_Header->sHeader -- + con_obj->asObjects[i].usRecordOffset); -- -- record_base = con_obj->asObjects[i].usRecordOffset; -- -- while (Record->ucRecordType > 0 -- && Record->ucRecordType <= ATOM_MAX_OBJECT_RECORD_NUMBER ) { -- char *taglist; -- -- if ((record_base += Record->ucRecordSize) -- > object_header_size) { -- xf86DrvMsg(handle->scrnIndex, X_ERROR, -- "%s: Object Records extend beyond Object Table\n", -- __func__); -- break; -- } -- -- RHDDebug(handle->scrnIndex, " - Record Type: %x\n", -- Record->ucRecordType); -- -- switch (Record->ucRecordType) { -- -- case ATOM_I2C_RECORD_TYPE: -- rhdAtomDDCFromI2CRecord(handle, -- (ATOM_I2C_RECORD *)Record, -- &cp[ncon].DDC); -- break; -- -- case ATOM_HPD_INT_RECORD_TYPE: -- rhdAtomHPDFromRecord(handle, -- (ATOM_HPD_INT_RECORD *)Record, -- &cp[ncon].HPD); -- break; -- -- case ATOM_CONNECTOR_DEVICE_TAG_RECORD_TYPE: -- taglist = rhdAtomDeviceTagsFromRecord(handle, -- (ATOM_CONNECTOR_DEVICE_TAG_RECORD *)Record); -- if (taglist) { -- cp[ncon].Name = RhdAppendString(cp[ncon].Name,taglist); -- xfree(taglist); -- } -- break; -- -- default: -- break; -- } -- -- Record = (ATOM_COMMON_RECORD_HEADER*) -- ((char *)Record + Record->ucRecordSize); -- -- } -- -- if ((++ncon) == RHD_CONNECTORS_MAX) -- break; -- } -- *ptr = cp; -- -- RhdPrintConnectorInfo(handle->scrnIndex, cp); -- -- return ATOM_SUCCESS; --} -- --/* -- * -- */ --static AtomBiosResult --rhdAtomConnectorInfoFromSupportedDevices(atomBiosHandlePtr handle, -- rhdConnectorInfoPtr *ptr) --{ -- atomDataTablesPtr atomDataPtr; -- CARD8 crev, frev; -- rhdConnectorInfoPtr cp; -- struct { -- rhdOutputType ot; -- rhdConnectorType con; -- rhdDDC ddc; -- rhdHPD hpd; -- Bool dual; -- char *name; -- char *outputName; -- } devices[ATOM_MAX_SUPPORTED_DEVICE]; -- int ncon = 0; -- int n; -- -- //RHDFUNC(handle); -- -- atomDataPtr = handle->atomDataPtr; -- -- if (!rhdAtomGetTableRevisionAndSize( -- &(atomDataPtr->SupportedDevicesInfo.SupportedDevicesInfo->sHeader), -- &crev,&frev,NULL)) { -- return ATOM_NOT_IMPLEMENTED; -- } -- -- if (!(cp = (rhdConnectorInfoPtr)xcalloc(RHD_CONNECTORS_MAX, -- sizeof(struct rhdConnectorInfo)))) -- return ATOM_FAILED; -- -- for (n = 0; n < ATOM_MAX_SUPPORTED_DEVICE; n++) { -- ATOM_CONNECTOR_INFO_I2C ci -- = atomDataPtr->SupportedDevicesInfo.SupportedDevicesInfo->asConnInfo[n]; -- -- devices[n].ot = OUTPUT_NONE_ATOM; -- -- if (!(atomDataPtr->SupportedDevicesInfo -- .SupportedDevicesInfo->usDeviceSupport & (1 << n))) -- continue; -- -- if (Limit(ci.sucConnectorInfo.sbfAccess.bfConnectorType, -- n_rhd_connectors, "bfConnectorType")) -- continue; -- -- devices[n].con -- = rhd_connectors[ci.sucConnectorInfo.sbfAccess.bfConnectorType].con; -- if (devices[n].con == RHD_CONNECTOR_NONE) -- continue; -- -- devices[n].dual -- = rhd_connectors[ci.sucConnectorInfo.sbfAccess.bfConnectorType].dual; -- devices[n].name -- = rhd_connectors[ci.sucConnectorInfo.sbfAccess.bfConnectorType].name; -- -- RHDDebug(handle->scrnIndex,"AtomBIOS Connector[%i]: %s Device:%s ",n, -- rhd_connectors[ci.sucConnectorInfo -- .sbfAccess.bfConnectorType].name, -- rhd_devices[n].name); -- -- devices[n].outputName = rhd_devices[n].name; -- -- if (!Limit(ci.sucConnectorInfo.sbfAccess.bfAssociatedDAC, -- n_acc_dac, "bfAssociatedDAC")) { -- if ((devices[n].ot -- = acc_dac[ci.sucConnectorInfo.sbfAccess.bfAssociatedDAC]) -- == OUTPUT_NONE_ATOM) { -- devices[n].ot = rhd_devices[n].ot; -- } -- } else -- devices[n].ot = OUTPUT_NONE_ATOM; -- -- RHDDebugCont("Output: %x ",devices[n].ot); -- -- if (ci.sucI2cId.sbfAccess.bfHW_Capable) { -- -- RHDDebugCont("HW DDC %i ", -- ci.sucI2cId.sbfAccess.bfI2C_LineMux); -- -- if (Limit(ci.sucI2cId.sbfAccess.bfI2C_LineMux, -- n_hwddc, "bfI2C_LineMux")) -- devices[n].ddc = RHD_DDC_NONE; -- else -- devices[n].ddc = hwddc[ci.sucI2cId.sbfAccess.bfI2C_LineMux]; -- -- } else if (ci.sucI2cId.sbfAccess.bfI2C_LineMux) { -- -- RHDDebugCont("GPIO DDC "); -- devices[n].ddc = RHD_DDC_GPIO; -- -- /* add support for GPIO line */ -- } else { -- -- RHDDebugCont("NO DDC "); -- devices[n].ddc = RHD_DDC_NONE; -- -- } -- -- if (crev > 1) { -- ATOM_CONNECTOR_INC_SRC_BITMAP isb -- = atomDataPtr->SupportedDevicesInfo -- .SupportedDevicesInfo_HD->asIntSrcInfo[n]; -- -- switch (isb.ucIntSrcBitmap) { -- case 0x4: -- RHDDebugCont("HPD 0\n"); -- devices[n].hpd = RHD_HPD_0; -- break; -- case 0xa: -- RHDDebugCont("HPD 1\n"); -- devices[n].hpd = RHD_HPD_1; -- break; -- default: -- RHDDebugCont("NO HPD\n"); -- devices[n].hpd = RHD_HPD_NONE; -- break; -- } -- } else { -- RHDDebugCont("NO HPD\n"); -- devices[n].hpd = RHD_HPD_NONE; -- } -- } -- /* sort devices for connectors */ -- for (n = 0; n < ATOM_MAX_SUPPORTED_DEVICE; n++) { -- int i; -- -- if (devices[n].ot == OUTPUT_NONE_ATOM) -- continue; -- if (devices[n].con == CONNECTOR_NONE_ATOM) -- continue; -- -- cp[ncon].DDC = devices[n].ddc; -- cp[ncon].HPD = devices[n].hpd; -- cp[ncon].Output[0] = devices[n].ot; -- cp[ncon].Output[1] = OUTPUT_NONE_ATOM; -- cp[ncon].Type = devices[n].con; -- cp[ncon].Name = xf86strdup(devices[n].name); -- cp[ncon].Name = RhdAppendString(cp[ncon].Name, devices[n].outputName); -- -- if (devices[n].dual) { -- if (devices[n].ddc == RHD_DDC_NONE) -- xf86DrvMsg(handle->scrnIndex, X_ERROR, -- "No DDC channel for device %s found." -- " Cannot find matching device.\n",devices[n].name); -- else { -- for (i = n + 1; i < ATOM_MAX_SUPPORTED_DEVICE; i++) { -- -- if (!devices[i].dual) -- continue; -- -- if (devices[n].ddc != devices[i].ddc) -- continue; -- -- if (((devices[n].ot == OUTPUT_DACA_ATOM -- || devices[n].ot == OUTPUT_DACB_ATOM) -- && (devices[i].ot == OUTPUT_LVTMA_ATOM -- || devices[i].ot == OUTPUT_TMDSA_ATOM)) -- || ((devices[i].ot == OUTPUT_DACA_ATOM -- || devices[i].ot == OUTPUT_DACB_ATOM) -- && (devices[n].ot == OUTPUT_LVTMA_ATOM -- || devices[n].ot == OUTPUT_TMDSA_ATOM))) { -- -- cp[ncon].Output[1] = devices[i].ot; -- -- if (cp[ncon].HPD == RHD_HPD_NONE) -- cp[ncon].HPD = devices[i].hpd; -- -- cp[ncon].Name = RhdAppendString(cp[ncon].Name, -- devices[i].outputName); -- devices[i].ot = OUTPUT_NONE_ATOM; /* zero the device */ -- } -- } -- } -- } -- -- if ((++ncon) == RHD_CONNECTORS_MAX) -- break; -- } -- *ptr = cp; -- -- RhdPrintConnectorInfo(handle->scrnIndex, cp); -- -- return ATOM_SUCCESS; --} -- --/* -- * -- */ --static AtomBiosResult --rhdAtomConnectorInfo(atomBiosHandlePtr handle, -- AtomBiosRequestID unused, AtomBiosArgPtr data) --{ -- data->connectorInfo = NULL; -- -- if (rhdAtomConnectorInfoFromObjectHeader(handle,&data->connectorInfo) -- == ATOM_SUCCESS) -- return ATOM_SUCCESS; -- else -- return rhdAtomConnectorInfoFromSupportedDevices(handle, -- &data->connectorInfo); --} --#endif -- - # ifdef ATOM_BIOS_PARSER - static AtomBiosResult - rhdAtomExec (atomBiosHandlePtr handle, -@@ -2566,9 +1944,9 @@ rhdAtomExec (atomBiosHandlePtr handle, - __func__); - return ATOM_FAILED; - } -- *dataSpace = (CARD8*)info->FB + handle->fbBase; -+ *dataSpace = (uint8_t*)info->FB + handle->fbBase; - } else -- *dataSpace = (CARD8*)handle->scratchBase; -+ *dataSpace = (uint8_t*)handle->scratchBase; - } - ret = ParseTableWrapper(pspace, idx, handle, - handle->BIOSBase, -@@ -2653,9 +2031,12 @@ RHDAtomBiosFunc(int scrnIndex, atomBiosHandlePtr handle, - VOID* - CailAllocateMemory(VOID *CAIL,UINT16 size) - { -+ void *ret; - CAILFUNC(CAIL); - -- return malloc(size); -+ ret = malloc(size); -+ memset(ret, 0, size); -+ return ret; - } - - VOID -@@ -2673,20 +2054,20 @@ CailDelayMicroSeconds(VOID *CAIL, UINT32 delay) - - usleep(delay); - -- DEBUGP(xf86DrvMsg(((atomBiosHandlePtr)CAIL)->scrnIndex,X_INFO,"Delay %i usec\n",delay)); -+ /*DEBUGP(xf86DrvMsg(((atomBiosHandlePtr)CAIL)->scrnIndex,X_INFO,"Delay %i usec\n",delay));*/ - } - - UINT32 - CailReadATIRegister(VOID* CAIL, UINT32 idx) - { - ScrnInfoPtr pScrn = xf86Screens[((atomBiosHandlePtr)CAIL)->scrnIndex]; -- RADEONInfoPtr info = RADEONPTR(pScrn); -- unsigned char *RADEONMMIO = info->MMIO; -+ RADEONEntPtr pRADEONEnt = RADEONEntPriv(pScrn); -+ unsigned char *RADEONMMIO = pRADEONEnt->MMIO; - UINT32 ret; - CAILFUNC(CAIL); - - ret = INREG(idx << 2); -- DEBUGP(ErrorF("%s(%x) = %x\n",__func__,idx << 2,ret)); -+ /*DEBUGP(ErrorF("%s(%x) = %x\n",__func__,idx << 2,ret));*/ - return ret; - } - -@@ -2694,12 +2075,12 @@ VOID - CailWriteATIRegister(VOID *CAIL, UINT32 idx, UINT32 data) - { - ScrnInfoPtr pScrn = xf86Screens[((atomBiosHandlePtr)CAIL)->scrnIndex]; -- RADEONInfoPtr info = RADEONPTR(pScrn); -- unsigned char *RADEONMMIO = info->MMIO; -+ RADEONEntPtr pRADEONEnt = RADEONEntPriv(pScrn); -+ unsigned char *RADEONMMIO = pRADEONEnt->MMIO; - CAILFUNC(CAIL); - - OUTREG(idx << 2,data); -- DEBUGP(ErrorF("%s(%x,%x)\n",__func__,idx << 2,data)); -+ /*DEBUGP(ErrorF("%s(%x,%x)\n",__func__,idx << 2,data));*/ - } - - UINT32 -@@ -2712,12 +2093,12 @@ CailReadFBData(VOID* CAIL, UINT32 idx) - CAILFUNC(CAIL); - - if (((atomBiosHandlePtr)CAIL)->fbBase) { -- CARD8 *FBBase = (CARD8*)info->FB; -- ret = *((CARD32*)(FBBase + (((atomBiosHandlePtr)CAIL)->fbBase) + idx)); -- DEBUGP(ErrorF("%s(%x) = %x\n",__func__,idx,ret)); -+ uint8_t *FBBase = (uint8_t*)info->FB; -+ ret = *((uint32_t*)(FBBase + (((atomBiosHandlePtr)CAIL)->fbBase) + idx)); -+ /*DEBUGP(ErrorF("%s(%x) = %x\n",__func__,idx,ret));*/ - } else if (((atomBiosHandlePtr)CAIL)->scratchBase) { -- ret = *(CARD32*)((CARD8*)(((atomBiosHandlePtr)CAIL)->scratchBase) + idx); -- DEBUGP(ErrorF("%s(%x) = %x\n",__func__,idx,ret)); -+ ret = *(uint32_t*)((uint8_t*)(((atomBiosHandlePtr)CAIL)->scratchBase) + idx); -+ /*DEBUGP(ErrorF("%s(%x) = %x\n",__func__,idx,ret));*/ - } else { - xf86DrvMsg(((atomBiosHandlePtr)CAIL)->scrnIndex,X_ERROR, - "%s: no fbbase set\n",__func__); -@@ -2731,13 +2112,13 @@ CailWriteFBData(VOID *CAIL, UINT32 idx, UINT32 data) - { - CAILFUNC(CAIL); - -- DEBUGP(ErrorF("%s(%x,%x)\n",__func__,idx,data)); -+ /*DEBUGP(ErrorF("%s(%x,%x)\n",__func__,idx,data));*/ - if (((atomBiosHandlePtr)CAIL)->fbBase) { -- CARD8 *FBBase = (CARD8*) -+ uint8_t *FBBase = (uint8_t*) - RADEONPTR(xf86Screens[((atomBiosHandlePtr)CAIL)->scrnIndex])->FB; -- *((CARD32*)(FBBase + (((atomBiosHandlePtr)CAIL)->fbBase) + idx)) = data; -+ *((uint32_t*)(FBBase + (((atomBiosHandlePtr)CAIL)->fbBase) + idx)) = data; - } else if (((atomBiosHandlePtr)CAIL)->scratchBase) { -- *(CARD32*)((CARD8*)(((atomBiosHandlePtr)CAIL)->scratchBase) + idx) = data; -+ *(uint32_t*)((uint8_t*)(((atomBiosHandlePtr)CAIL)->scratchBase) + idx) = data; - } else - xf86DrvMsg(((atomBiosHandlePtr)CAIL)->scrnIndex,X_ERROR, - "%s: no fbbase set\n",__func__); -@@ -2752,7 +2133,7 @@ CailReadMC(VOID *CAIL, ULONG Address) - CAILFUNC(CAIL); - - ret = INMC(pScrn, Address); -- DEBUGP(ErrorF("%s(%x) = %x\n",__func__,Address,ret)); -+ /*DEBUGP(ErrorF("%s(%x) = %x\n",__func__,Address,ret));*/ - return ret; - } - -@@ -2762,7 +2143,7 @@ CailWriteMC(VOID *CAIL, ULONG Address, ULONG data) - ScrnInfoPtr pScrn = xf86Screens[((atomBiosHandlePtr)CAIL)->scrnIndex]; - - CAILFUNC(CAIL); -- DEBUGP(ErrorF("%s(%x,%x)\n",__func__,Address,data)); -+ /*DEBUGP(ErrorF("%s(%x,%x)\n",__func__,Address,data));*/ - OUTMC(pScrn, Address, data); - } - -@@ -2793,13 +2174,13 @@ CailReadPCIConfigData(VOID*CAIL, VOID* ret, UINT32 idx,UINT16 size) - - switch (size) { - case 8: -- *(CARD8*)ret = pciReadByte(tag,idx << 2); -+ *(uint8_t*)ret = pciReadByte(tag,idx << 2); - break; - case 16: -- *(CARD16*)ret = pciReadWord(tag,idx << 2); -+ *(uint16_t*)ret = pciReadWord(tag,idx << 2); - break; - case 32: -- *(CARD32*)ret = pciReadLong(tag,idx << 2); -+ *(uint32_t*)ret = pciReadLong(tag,idx << 2); - break; - default: - xf86DrvMsg(((atomBiosHandlePtr)CAIL)->scrnIndex, -@@ -2808,7 +2189,7 @@ CailReadPCIConfigData(VOID*CAIL, VOID* ret, UINT32 idx,UINT16 size) - return; - break; - } -- DEBUGP(ErrorF("%s(%x) = %x\n",__func__,idx,*(unsigned int*)ret)); -+ /*DEBUGP(ErrorF("%s(%x) = %x\n",__func__,idx,*(unsigned int*)ret));*/ - - } - -@@ -2818,16 +2199,16 @@ CailWritePCIConfigData(VOID*CAIL,VOID*src,UINT32 idx,UINT16 size) - PCITAG tag = ((atomBiosHandlePtr)CAIL)->PciTag; - - CAILFUNC(CAIL); -- DEBUGP(ErrorF("%s(%x,%x)\n",__func__,idx,(*(unsigned int*)src))); -+ /*DEBUGP(ErrorF("%s(%x,%x)\n",__func__,idx,(*(unsigned int*)src)));*/ - switch (size) { - case 8: -- pciWriteByte(tag,idx << 2,*(CARD8*)src); -+ pciWriteByte(tag,idx << 2,*(uint8_t*)src); - break; - case 16: -- pciWriteWord(tag,idx << 2,*(CARD16*)src); -+ pciWriteWord(tag,idx << 2,*(uint16_t*)src); - break; - case 32: -- pciWriteLong(tag,idx << 2,*(CARD32*)src); -+ pciWriteLong(tag,idx << 2,*(uint32_t*)src); - break; - default: - xf86DrvMsg(((atomBiosHandlePtr)CAIL)->scrnIndex,X_ERROR, -@@ -2846,7 +2227,7 @@ CailReadPLL(VOID *CAIL, ULONG Address) - CAILFUNC(CAIL); - - ret = RADEONINPLL(pScrn, Address); -- DEBUGP(ErrorF("%s(%x) = %x\n",__func__,Address,ret)); -+ /*DEBUGP(ErrorF("%s(%x) = %x\n",__func__,Address,ret));*/ - return ret; - } - -@@ -2856,7 +2237,7 @@ CailWritePLL(VOID *CAIL, ULONG Address,ULONG Data) - ScrnInfoPtr pScrn = xf86Screens[((atomBiosHandlePtr)CAIL)->scrnIndex]; - CAILFUNC(CAIL); - -- DEBUGP(ErrorF("%s(%x,%x)\n",__func__,Address,Data)); -+ /*DEBUGP(ErrorF("%s(%x,%x)\n",__func__,Address,Data));*/ - RADEONOUTPLL(pScrn, Address, Data); - } - -@@ -2874,6 +2255,7 @@ atombios_get_command_table_version(atomBiosHandlePtr atomBIOS, int index, int *m - - offset = *(((unsigned short *)table_start) + index); - -+ offset = le16_to_cpu(offset); - table_hdr = (ATOM_COMMON_ROM_COMMAND_TABLE_HEADER *)(atomBIOS->BIOSBase + offset); - - *major = table_hdr->CommonHeader.ucTableFormatRevision; -@@ -2881,4 +2263,15 @@ atombios_get_command_table_version(atomBiosHandlePtr atomBIOS, int index, int *m - } - - -+UINT16 ATOM_BSWAP16(UINT16 x) -+{ -+ return bswap_16(x); -+} -+ -+UINT32 ATOM_BSWAP32(UINT32 x) -+{ -+ return bswap_32(x); -+} -+ -+ - #endif /* ATOM_BIOS */ -diff --git a/src/radeon_atombios.h b/src/radeon_atombios.h -index 9cb279e..fe7044d 100644 ---- a/src/radeon_atombios.h -+++ b/src/radeon_atombios.h -@@ -98,7 +98,7 @@ typedef struct AtomFb { - - typedef union AtomBiosArg - { -- CARD32 val; -+ uint32_t val; - struct rhdConnectorInfo *connectorInfo; - unsigned char* EDIDBlock; - atomBiosHandlePtr atomhandle; -@@ -116,6 +116,12 @@ RADEONGetATOMConnectorInfoFromBIOSObject (ScrnInfoPtr pScrn); - extern Bool - RADEONGetATOMConnectorInfoFromBIOSConnectorTable (ScrnInfoPtr pScrn); - -+extern int -+atombios_dyn_clk_setup(ScrnInfoPtr pScrn, int enable); -+ -+extern int -+atombios_static_pwrmgt_setup(ScrnInfoPtr pScrn, int enable); -+ - extern Bool - RADEONGetATOMTVInfo(xf86OutputPtr output); - -@@ -125,6 +131,9 @@ atombios_external_tmds_setup(xf86OutputPtr output, DisplayModePtr mode); - extern void - atombios_get_command_table_version(atomBiosHandlePtr atomBIOS, int index, int *major, int *minor); - -+Bool -+rhdAtomASICInit(atomBiosHandlePtr handle); -+ - # include "xf86int10.h" - # ifdef ATOM_BIOS_PARSER - # define INT8 INT8 -@@ -236,7 +245,7 @@ typedef struct _atomBiosHandle { - atomDataTablesPtr atomDataPtr; - unsigned int cmd_offset; - pointer *scratchBase; -- CARD32 fbBase; -+ uint32_t fbBase; - #if XSERVER_LIBPCIACCESS - struct pci_device *device; - #else -diff --git a/src/radeon_atomwrapper.c b/src/radeon_atomwrapper.c -index 259366c..bed1471 100644 ---- a/src/radeon_atomwrapper.c -+++ b/src/radeon_atomwrapper.c -@@ -27,10 +27,11 @@ - # include "config.h" - #endif - --//#include "radeon_atomwrapper.h" -+#include "radeon_atomwrapper.h" - - #define INT32 INT32 - #include "CD_Common_Types.h" -+#include "atombios.h" - #include "CD_Definitions.h" - - -diff --git a/src/radeon_bios.c b/src/radeon_bios.c -index 8e6bd8d..adedeb3 100644 ---- a/src/radeon_bios.c -+++ b/src/radeon_bios.c -@@ -65,17 +65,219 @@ typedef enum - CONNECTOR_UNSUPPORTED_LEGACY - } RADEONLegacyConnectorType; - -+static Bool -+radeon_read_bios(ScrnInfoPtr pScrn) -+{ -+ RADEONInfoPtr info = RADEONPTR(pScrn); -+ -+#ifdef XSERVER_LIBPCIACCESS -+ if (pci_device_read_rom(info->PciInfo, info->VBIOS)) { -+ xf86DrvMsg(pScrn->scrnIndex, X_WARNING, -+ "Failed to read PCI ROM!\n"); -+ return FALSE; -+ } -+#else -+ xf86ReadPciBIOS(0, info->PciTag, 0, info->VBIOS, RADEON_VBIOS_SIZE); -+ if (info->VBIOS[0] != 0x55 || info->VBIOS[1] != 0xaa) { -+ xf86DrvMsg(pScrn->scrnIndex, X_WARNING, -+ "Video BIOS not detected in PCI space!\n"); -+ if (xf86IsEntityPrimary(info->pEnt->index)) { -+ xf86DrvMsg(pScrn->scrnIndex, X_WARNING, -+ "Attempting to read Video BIOS from " -+ "legacy ISA space!\n"); -+ info->BIOSAddr = 0x000c0000; -+ xf86ReadDomainMemory(info->PciTag, info->BIOSAddr, -+ RADEON_VBIOS_SIZE, info->VBIOS); -+ } -+ } -+#endif -+ if (info->VBIOS[0] != 0x55 || info->VBIOS[1] != 0xaa) -+ return FALSE; -+ else -+ return TRUE; -+} -+ -+static Bool -+radeon_read_unposted_bios(ScrnInfoPtr pScrn) -+{ -+ RADEONInfoPtr info = RADEONPTR(pScrn); -+ RADEONEntPtr pRADEONEnt = RADEONEntPriv(pScrn); -+ unsigned char *RADEONMMIO = info->MMIO; -+ Bool ret; -+ -+ xf86DrvMsg(pScrn->scrnIndex, X_INFO, "Attempting to read un-POSTed bios\n"); -+ -+ if (info->ChipFamily >= CHIP_FAMILY_R600) { -+ uint32_t viph_control = INREG(RADEON_VIPH_CONTROL); -+ uint32_t bus_cntl = INREG(RADEON_BUS_CNTL); -+ uint32_t d1vga_control = INREG(AVIVO_D1VGA_CONTROL); -+ uint32_t d2vga_control = INREG(AVIVO_D2VGA_CONTROL); -+ uint32_t vga_render_control = INREG(AVIVO_VGA_RENDER_CONTROL); -+ uint32_t rom_cntl = INREG(R600_ROM_CNTL); -+ uint32_t general_pwrmgt = INREG(R600_GENERAL_PWRMGT); -+ uint32_t low_vid_lower_gpio_cntl = INREG(R600_LOW_VID_LOWER_GPIO_CNTL); -+ uint32_t medium_vid_lower_gpio_cntl = INREG(R600_MEDIUM_VID_LOWER_GPIO_CNTL); -+ uint32_t high_vid_lower_gpio_cntl = INREG(R600_HIGH_VID_LOWER_GPIO_CNTL); -+ uint32_t ctxsw_vid_lower_gpio_cntl = INREG(R600_CTXSW_VID_LOWER_GPIO_CNTL); -+ uint32_t lower_gpio_enable = INREG(R600_LOWER_GPIO_ENABLE); -+ -+ /* disable VIP */ -+ OUTREG(RADEON_VIPH_CONTROL, (viph_control & ~RADEON_VIPH_EN)); -+ -+ /* enable the rom */ -+ OUTREG(RADEON_BUS_CNTL, (bus_cntl & ~RADEON_BUS_BIOS_DIS_ROM)); -+ -+ /* Disable VGA mode */ -+ OUTREG(AVIVO_D1VGA_CONTROL, (d1vga_control & ~(AVIVO_DVGA_CONTROL_MODE_ENABLE | -+ AVIVO_DVGA_CONTROL_TIMING_SELECT))); -+ OUTREG(AVIVO_D2VGA_CONTROL, (d2vga_control & ~(AVIVO_DVGA_CONTROL_MODE_ENABLE | -+ AVIVO_DVGA_CONTROL_TIMING_SELECT))); -+ OUTREG(AVIVO_VGA_RENDER_CONTROL, (vga_render_control & ~AVIVO_VGA_VSTATUS_CNTL_MASK)); -+ -+ OUTREG(R600_ROM_CNTL, ((rom_cntl & ~R600_SCK_PRESCALE_CRYSTAL_CLK_MASK) | -+ (1 << R600_SCK_PRESCALE_CRYSTAL_CLK_SHIFT) | -+ R600_SCK_OVERWRITE)); -+ -+ OUTREG(R600_GENERAL_PWRMGT, (general_pwrmgt & ~R600_OPEN_DRAIN_PADS)); -+ -+ OUTREG(R600_LOW_VID_LOWER_GPIO_CNTL, (low_vid_lower_gpio_cntl & ~0x400)); -+ -+ OUTREG(R600_MEDIUM_VID_LOWER_GPIO_CNTL, (medium_vid_lower_gpio_cntl & ~0x400)); -+ -+ OUTREG(R600_HIGH_VID_LOWER_GPIO_CNTL, (high_vid_lower_gpio_cntl & ~0x400)); -+ -+ OUTREG(R600_CTXSW_VID_LOWER_GPIO_CNTL, (ctxsw_vid_lower_gpio_cntl & ~0x400)); -+ -+ OUTREG(R600_LOWER_GPIO_ENABLE, (lower_gpio_enable | 0x400)); -+ -+ ret = radeon_read_bios(pScrn); -+ -+ /* restore regs */ -+ OUTREG(RADEON_VIPH_CONTROL, viph_control); -+ OUTREG(RADEON_BUS_CNTL, bus_cntl); -+ OUTREG(AVIVO_D1VGA_CONTROL, d1vga_control); -+ OUTREG(AVIVO_D2VGA_CONTROL, d2vga_control); -+ OUTREG(AVIVO_VGA_RENDER_CONTROL, vga_render_control); -+ OUTREG(R600_ROM_CNTL, rom_cntl); -+ OUTREG(R600_GENERAL_PWRMGT, general_pwrmgt); -+ OUTREG(R600_LOW_VID_LOWER_GPIO_CNTL, low_vid_lower_gpio_cntl); -+ OUTREG(R600_MEDIUM_VID_LOWER_GPIO_CNTL, medium_vid_lower_gpio_cntl); -+ OUTREG(R600_HIGH_VID_LOWER_GPIO_CNTL, high_vid_lower_gpio_cntl); -+ OUTREG(R600_CTXSW_VID_LOWER_GPIO_CNTL, ctxsw_vid_lower_gpio_cntl); -+ OUTREG(R600_LOWER_GPIO_ENABLE, lower_gpio_enable); -+ -+ } else if (info->ChipFamily >= CHIP_FAMILY_RV515) { -+ uint32_t seprom_cntl1 = INREG(RADEON_SEPROM_CNTL1); -+ uint32_t viph_control = INREG(RADEON_VIPH_CONTROL); -+ uint32_t bus_cntl = INREG(RADEON_BUS_CNTL); -+ uint32_t d1vga_control = INREG(AVIVO_D1VGA_CONTROL); -+ uint32_t d2vga_control = INREG(AVIVO_D2VGA_CONTROL); -+ uint32_t vga_render_control = INREG(AVIVO_VGA_RENDER_CONTROL); -+ uint32_t gpiopad_a = INREG(RADEON_GPIOPAD_A); -+ uint32_t gpiopad_en = INREG(RADEON_GPIOPAD_EN); -+ uint32_t gpiopad_mask = INREG(RADEON_GPIOPAD_MASK); -+ -+ OUTREG(RADEON_SEPROM_CNTL1, ((seprom_cntl1 & ~RADEON_SCK_PRESCALE_MASK) | -+ (0xc << RADEON_SCK_PRESCALE_SHIFT))); -+ -+ OUTREG(RADEON_GPIOPAD_A, 0); -+ OUTREG(RADEON_GPIOPAD_EN, 0); -+ OUTREG(RADEON_GPIOPAD_MASK, 0); -+ -+ /* disable VIP */ -+ OUTREG(RADEON_VIPH_CONTROL, (viph_control & ~RADEON_VIPH_EN)); -+ -+ /* enable the rom */ -+ OUTREG(RADEON_BUS_CNTL, (bus_cntl & ~RADEON_BUS_BIOS_DIS_ROM)); -+ -+ /* Disable VGA mode */ -+ OUTREG(AVIVO_D1VGA_CONTROL, (d1vga_control & ~(AVIVO_DVGA_CONTROL_MODE_ENABLE | -+ AVIVO_DVGA_CONTROL_TIMING_SELECT))); -+ OUTREG(AVIVO_D2VGA_CONTROL, (d2vga_control & ~(AVIVO_DVGA_CONTROL_MODE_ENABLE | -+ AVIVO_DVGA_CONTROL_TIMING_SELECT))); -+ OUTREG(AVIVO_VGA_RENDER_CONTROL, (vga_render_control & ~AVIVO_VGA_VSTATUS_CNTL_MASK)); -+ -+ ret = radeon_read_bios(pScrn); -+ -+ /* restore regs */ -+ OUTREG(RADEON_SEPROM_CNTL1, seprom_cntl1); -+ OUTREG(RADEON_VIPH_CONTROL, viph_control); -+ OUTREG(RADEON_BUS_CNTL, bus_cntl); -+ OUTREG(AVIVO_D1VGA_CONTROL, d1vga_control); -+ OUTREG(AVIVO_D2VGA_CONTROL, d2vga_control); -+ OUTREG(AVIVO_VGA_RENDER_CONTROL, vga_render_control); -+ OUTREG(RADEON_GPIOPAD_A, gpiopad_a); -+ OUTREG(RADEON_GPIOPAD_EN, gpiopad_en); -+ OUTREG(RADEON_GPIOPAD_MASK, gpiopad_mask); -+ -+ } else { -+ uint32_t seprom_cntl1 = INREG(RADEON_SEPROM_CNTL1); -+ uint32_t viph_control = INREG(RADEON_VIPH_CONTROL); -+ uint32_t bus_cntl = INREG(RADEON_BUS_CNTL); -+ uint32_t crtc_gen_cntl = INREG(RADEON_CRTC_GEN_CNTL); -+ uint32_t crtc2_gen_cntl = 0; -+ uint32_t crtc_ext_cntl = INREG(RADEON_CRTC_EXT_CNTL); -+ uint32_t fp2_gen_cntl = 0; -+ -+ if (PCI_DEV_DEVICE_ID(info->PciInfo) == PCI_CHIP_RV100_QY) -+ fp2_gen_cntl = INREG(RADEON_FP2_GEN_CNTL); -+ -+ if (pRADEONEnt->HasCRTC2) -+ crtc2_gen_cntl = INREG(RADEON_CRTC2_GEN_CNTL); -+ -+ OUTREG(RADEON_SEPROM_CNTL1, ((seprom_cntl1 & ~RADEON_SCK_PRESCALE_MASK) | -+ (0xc << RADEON_SCK_PRESCALE_SHIFT))); -+ -+ /* disable VIP */ -+ OUTREG(RADEON_VIPH_CONTROL, (viph_control & ~RADEON_VIPH_EN)); -+ -+ /* enable the rom */ -+ OUTREG(RADEON_BUS_CNTL, (bus_cntl & ~RADEON_BUS_BIOS_DIS_ROM)); -+ -+ /* Turn off mem requests and CRTC for both controllers */ -+ OUTREG(RADEON_CRTC_GEN_CNTL, ((crtc_gen_cntl & ~RADEON_CRTC_EN) | -+ (RADEON_CRTC_DISP_REQ_EN_B | -+ RADEON_CRTC_EXT_DISP_EN))); -+ if (pRADEONEnt->HasCRTC2) -+ OUTREG(RADEON_CRTC2_GEN_CNTL, ((crtc2_gen_cntl & ~RADEON_CRTC2_EN) | -+ RADEON_CRTC2_DISP_REQ_EN_B)); -+ -+ /* Turn off CRTC */ -+ OUTREG(RADEON_CRTC_EXT_CNTL, ((crtc_ext_cntl & ~RADEON_CRTC_CRT_ON) | -+ (RADEON_CRTC_SYNC_TRISTAT | -+ RADEON_CRTC_DISPLAY_DIS))); -+ -+ if (PCI_DEV_DEVICE_ID(info->PciInfo) == PCI_CHIP_RV100_QY) -+ OUTREG(RADEON_FP2_GEN_CNTL, (fp2_gen_cntl & ~RADEON_FP2_ON)); -+ -+ ret = radeon_read_bios(pScrn); -+ -+ /* restore regs */ -+ OUTREG(RADEON_SEPROM_CNTL1, seprom_cntl1); -+ OUTREG(RADEON_VIPH_CONTROL, viph_control); -+ OUTREG(RADEON_BUS_CNTL, bus_cntl); -+ OUTREG(RADEON_CRTC_GEN_CNTL, crtc_gen_cntl); -+ if (pRADEONEnt->HasCRTC2) -+ OUTREG(RADEON_CRTC2_GEN_CNTL, crtc2_gen_cntl); -+ OUTREG(RADEON_CRTC_EXT_CNTL, crtc_ext_cntl); -+ if (PCI_DEV_DEVICE_ID(info->PciInfo) == PCI_CHIP_RV100_QY) -+ OUTREG(RADEON_FP2_GEN_CNTL, fp2_gen_cntl); -+ } -+ return ret; -+} - - /* Read the Video BIOS block and the FP registers (if applicable). */ --Bool RADEONGetBIOSInfo(ScrnInfoPtr pScrn, xf86Int10InfoPtr pInt10) -+Bool -+RADEONGetBIOSInfo(ScrnInfoPtr pScrn, xf86Int10InfoPtr pInt10) - { - RADEONInfoPtr info = RADEONPTR(pScrn); - int tmp; - unsigned short dptr; -+ Bool unposted = FALSE; - - #ifdef XSERVER_LIBPCIACCESS -- //info->VBIOS = xalloc(info->PciInfo->rom_size); -- info->VBIOS = xalloc(RADEON_VBIOS_SIZE); -+ int size = info->PciInfo->rom_size > RADEON_VBIOS_SIZE ? info->PciInfo->rom_size : RADEON_VBIOS_SIZE; -+ info->VBIOS = xalloc(size); - #else - info->VBIOS = xalloc(RADEON_VBIOS_SIZE); - #endif -@@ -88,25 +290,9 @@ Bool RADEONGetBIOSInfo(ScrnInfoPtr pScrn, xf86Int10InfoPtr pInt10) - info->BIOSAddr = pInt10->BIOSseg << 4; - (void)memcpy(info->VBIOS, xf86int10Addr(pInt10, info->BIOSAddr), - RADEON_VBIOS_SIZE); -- } else { --#ifdef XSERVER_LIBPCIACCESS -- if (pci_device_read_rom(info->PciInfo, info->VBIOS)) { -- xf86DrvMsg(pScrn->scrnIndex, X_WARNING, -- "Failed to read PCI ROM!\n"); -- } --#else -- xf86ReadPciBIOS(0, info->PciTag, 0, info->VBIOS, RADEON_VBIOS_SIZE); -- if (info->VBIOS[0] != 0x55 || info->VBIOS[1] != 0xaa) { -- xf86DrvMsg(pScrn->scrnIndex, X_WARNING, -- "Video BIOS not detected in PCI space!\n"); -- xf86DrvMsg(pScrn->scrnIndex, X_WARNING, -- "Attempting to read Video BIOS from " -- "legacy ISA space!\n"); -- info->BIOSAddr = 0x000c0000; -- xf86ReadDomainMemory(info->PciTag, info->BIOSAddr, -- RADEON_VBIOS_SIZE, info->VBIOS); -- } --#endif -+ } else if (!radeon_read_bios(pScrn)) { -+ (void)radeon_read_unposted_bios(pScrn); -+ unposted = TRUE; - } - } - -@@ -142,7 +328,7 @@ Bool RADEONGetBIOSInfo(ScrnInfoPtr pScrn, xf86Int10InfoPtr pInt10) - info->VBIOS = NULL; - return FALSE; - } -- -+ - tmp = info->ROMHeaderStart + 4; - if ((RADEON_BIOS8(tmp) == 'A' && - RADEON_BIOS8(tmp+1) == 'T' && -@@ -160,44 +346,76 @@ Bool RADEONGetBIOSInfo(ScrnInfoPtr pScrn, xf86Int10InfoPtr pInt10) - info->IsAtomBios ? "ATOM":"Legacy"); - - if (info->IsAtomBios) { --#if 1 -- AtomBiosArgRec atomBiosArg; -+ AtomBiosArgRec atomBiosArg; - -- if (RHDAtomBiosFunc(pScrn->scrnIndex, NULL, ATOMBIOS_INIT, &atomBiosArg) -- == ATOM_SUCCESS) { -- info->atomBIOS = atomBiosArg.atomhandle; -- } -+ if (RHDAtomBiosFunc(pScrn->scrnIndex, NULL, ATOMBIOS_INIT, &atomBiosArg) -+ == ATOM_SUCCESS) { -+ info->atomBIOS = atomBiosArg.atomhandle; -+ } - -- atomBiosArg.fb.start = info->FbFreeStart; -- atomBiosArg.fb.size = info->FbFreeSize; -- if (RHDAtomBiosFunc(pScrn->scrnIndex, info->atomBIOS, ATOMBIOS_ALLOCATE_FB_SCRATCH, -+ atomBiosArg.fb.start = info->FbFreeStart; -+ atomBiosArg.fb.size = info->FbFreeSize; -+ if (RHDAtomBiosFunc(pScrn->scrnIndex, info->atomBIOS, ATOMBIOS_ALLOCATE_FB_SCRATCH, - &atomBiosArg) == ATOM_SUCCESS) { - - info->FbFreeStart = atomBiosArg.fb.start; - info->FbFreeSize = atomBiosArg.fb.size; -- } -- -- RHDAtomBiosFunc(pScrn->scrnIndex, info->atomBIOS, GET_DEFAULT_ENGINE_CLOCK, -- &atomBiosArg); -- RHDAtomBiosFunc(pScrn->scrnIndex, info->atomBIOS, GET_DEFAULT_MEMORY_CLOCK, -- &atomBiosArg); -- RHDAtomBiosFunc(pScrn->scrnIndex, info->atomBIOS, -- GET_MAX_PIXEL_CLOCK_PLL_OUTPUT, &atomBiosArg); -- RHDAtomBiosFunc(pScrn->scrnIndex, info->atomBIOS, -- GET_MIN_PIXEL_CLOCK_PLL_OUTPUT, &atomBiosArg); -- RHDAtomBiosFunc(pScrn->scrnIndex, info->atomBIOS, -- GET_MAX_PIXEL_CLOCK_PLL_INPUT, &atomBiosArg); -- RHDAtomBiosFunc(pScrn->scrnIndex, info->atomBIOS, -+ } -+ -+ RHDAtomBiosFunc(pScrn->scrnIndex, info->atomBIOS, GET_DEFAULT_ENGINE_CLOCK, -+ &atomBiosArg); -+ RHDAtomBiosFunc(pScrn->scrnIndex, info->atomBIOS, GET_DEFAULT_MEMORY_CLOCK, -+ &atomBiosArg); -+ RHDAtomBiosFunc(pScrn->scrnIndex, info->atomBIOS, -+ GET_MAX_PIXEL_CLOCK_PLL_OUTPUT, &atomBiosArg); -+ RHDAtomBiosFunc(pScrn->scrnIndex, info->atomBIOS, -+ GET_MIN_PIXEL_CLOCK_PLL_OUTPUT, &atomBiosArg); -+ RHDAtomBiosFunc(pScrn->scrnIndex, info->atomBIOS, -+ GET_MAX_PIXEL_CLOCK_PLL_INPUT, &atomBiosArg); -+ RHDAtomBiosFunc(pScrn->scrnIndex, info->atomBIOS, - GET_MIN_PIXEL_CLOCK_PLL_INPUT, &atomBiosArg); -- RHDAtomBiosFunc(pScrn->scrnIndex, info->atomBIOS, -+ RHDAtomBiosFunc(pScrn->scrnIndex, info->atomBIOS, - GET_MAX_PIXEL_CLK, &atomBiosArg); -- RHDAtomBiosFunc(pScrn->scrnIndex, info->atomBIOS, -- GET_REF_CLOCK, &atomBiosArg); -+ RHDAtomBiosFunc(pScrn->scrnIndex, info->atomBIOS, -+ GET_REF_CLOCK, &atomBiosArg); - --#endif - info->MasterDataStart = RADEON_BIOS16 (info->ROMHeaderStart + 32); - } - -+ /* We are a bit too quick at using this "unposted" to re-post the -+ * card. This causes some problems with VT switch on some machines, -+ * so let's work around this for now by only POSTing if none of the -+ * CRTCs are enabled -+ */ -+ if (unposted && info->VBIOS) { -+ unsigned char *RADEONMMIO = info->MMIO; -+ uint32_t reg; -+ -+ if (IS_AVIVO_VARIANT) { -+ reg = INREG(AVIVO_D1CRTC_CONTROL) | INREG(AVIVO_D2CRTC_CONTROL); -+ if (reg & AVIVO_CRTC_EN) -+ unposted = FALSE; -+ } else { -+ reg = INREG(RADEON_CRTC_GEN_CNTL) | INREG(RADEON_CRTC2_GEN_CNTL); -+ if (reg & RADEON_CRTC_EN) -+ unposted = FALSE; -+ } -+ } -+ -+ if (unposted && info->VBIOS) { -+ if (info->IsAtomBios) { -+ if (!rhdAtomASICInit(info->atomBIOS)) -+ xf86DrvMsg(pScrn->scrnIndex, X_WARNING, -+ "%s: AsicInit failed.\n",__func__); -+ } else { -+#if 0 -+ xf86DrvMsg(pScrn->scrnIndex, X_INFO, "Attempting to POST via legacy BIOS tables\n"); -+ RADEONGetBIOSInitTableOffsets(pScrn); -+ RADEONPostCardFromBIOSTables(pScrn); -+#endif -+ } -+ } -+ - return TRUE; - } - -@@ -216,6 +434,65 @@ static Bool RADEONGetATOMConnectorInfoFromBIOS (ScrnInfoPtr pScrn) - return FALSE; - } - -+static void RADEONApplyLegacyQuirks(ScrnInfoPtr pScrn, int index) -+{ -+ RADEONInfoPtr info = RADEONPTR (pScrn); -+ -+ /* on XPRESS chips, CRT2_DDC and MONID_DCC both use the -+ * MONID gpio, but use different pins. -+ * CRT2_DDC uses the standard pinout, MONID_DDC uses -+ * something else. -+ */ -+ if ((info->ChipFamily == CHIP_FAMILY_RS400 || -+ info->ChipFamily == CHIP_FAMILY_RS480) && -+ info->BiosConnector[index].ConnectorType == CONNECTOR_VGA && -+ info->BiosConnector[index].ddc_i2c.mask_clk_reg == RADEON_GPIO_CRT2_DDC) { -+ info->BiosConnector[index].ddc_i2c = legacy_setup_i2c_bus(RADEON_GPIO_MONID); -+ } -+ -+ /* XPRESS desktop chips seem to have a proprietary connector listed for -+ * DVI-D, try and do the right thing here. -+ */ -+ if ((!info->IsMobility) && -+ (info->BiosConnector[index].ConnectorType == CONNECTOR_LVDS)) { -+ xf86DrvMsg(pScrn->scrnIndex, X_WARNING, -+ "Proprietary connector found, assuming DVI-D\n"); -+ info->BiosConnector[index].DACType = DAC_NONE; -+ info->BiosConnector[index].TMDSType = TMDS_EXT; -+ info->BiosConnector[index].ConnectorType = CONNECTOR_DVI_D; -+ } -+ -+ /* Certain IBM chipset RN50s have a BIOS reporting two VGAs, -+ one with VGA DDC and one with CRT2 DDC. - kill the CRT2 DDC one */ -+ if (info->Chipset == PCI_CHIP_RN50_515E && -+ PCI_SUB_VENDOR_ID(info->PciInfo) == 0x1014) { -+ if (info->BiosConnector[index].ConnectorType == CONNECTOR_VGA && -+ info->BiosConnector[index].ddc_i2c.mask_clk_reg == RADEON_GPIO_CRT2_DDC) { -+ info->BiosConnector[index].valid = FALSE; -+ } -+ } -+ -+ /* Some RV100 cards with 2 VGA ports show up with DVI+VGA */ -+ if (info->Chipset == PCI_CHIP_RV100_QY && -+ PCI_SUB_VENDOR_ID(info->PciInfo) == 0x1002 && -+ PCI_SUB_DEVICE_ID(info->PciInfo) == 0x013a) { -+ if (info->BiosConnector[index].ConnectorType == CONNECTOR_DVI_I) { -+ info->BiosConnector[index].ConnectorType = CONNECTOR_VGA; -+ } -+ } -+ -+ /* X300 card with extra non-existent DVI port */ -+ if (info->Chipset == PCI_CHIP_RV370_5B60 && -+ PCI_SUB_VENDOR_ID(info->PciInfo) == 0x17af && -+ PCI_SUB_DEVICE_ID(info->PciInfo) == 0x201e && -+ index == 2) { -+ if (info->BiosConnector[index].ConnectorType == CONNECTOR_DVI_I) { -+ info->BiosConnector[index].valid = FALSE; -+ } -+ } -+ -+} -+ - static Bool RADEONGetLegacyConnectorInfoFromBIOS (ScrnInfoPtr pScrn) - { - RADEONInfoPtr info = RADEONPTR (pScrn); -@@ -289,7 +566,9 @@ static Bool RADEONGetLegacyConnectorInfoFromBIOS (ScrnInfoPtr pScrn) - info->BiosConnector[i].DACType = DAC_PRIMARY; - - /* For RS300/RS350/RS400 chips, there is no primary DAC. Force VGA port to use TVDAC*/ -- if (info->IsIGP) -+ if ((info->ChipFamily == CHIP_FAMILY_RS300) || -+ (info->ChipFamily == CHIP_FAMILY_RS400) || -+ (info->ChipFamily == CHIP_FAMILY_RS480)) - info->BiosConnector[i].DACType = DAC_TVDAC; - - if ((tmp >> 4) & 0x1) -@@ -297,28 +576,8 @@ static Bool RADEONGetLegacyConnectorInfoFromBIOS (ScrnInfoPtr pScrn) - else - info->BiosConnector[i].TMDSType = TMDS_INT; - -- /* most XPRESS chips seem to specify DDC_CRT2 for their -- * VGA DDC port, however DDC never seems to work on that -- * port. Some have reported success on DDC_MONID, so -- * lets see what happens with that. -- */ -- if (info->ChipFamily == CHIP_FAMILY_RS400 && -- info->BiosConnector[i].ConnectorType == CONNECTOR_VGA && -- info->BiosConnector[i].ddc_i2c.mask_clk_reg == RADEON_GPIO_CRT2_DDC) { -- info->BiosConnector[i].ddc_i2c = legacy_setup_i2c_bus(RADEON_GPIO_MONID); -- } -+ RADEONApplyLegacyQuirks(pScrn, i); - -- /* XPRESS desktop chips seem to have a proprietary connector listed for -- * DVI-D, try and do the right thing here. -- */ -- if ((!info->IsMobility) && -- (info->BiosConnector[i].ConnectorType == CONNECTOR_LVDS)) { -- xf86DrvMsg(pScrn->scrnIndex, X_WARNING, -- "Proprietary connector found, assuming DVI-D\n"); -- info->BiosConnector[i].DACType = DAC_NONE; -- info->BiosConnector[i].TMDSType = TMDS_EXT; -- info->BiosConnector[i].ConnectorType = CONNECTOR_DVI_D; -- } - } - } else { - xf86DrvMsg(pScrn->scrnIndex, X_WARNING, "No Connector Info Table found!\n"); -@@ -541,7 +800,7 @@ Bool RADEONGetClockInfoFromBIOS (ScrnInfoPtr pScrn) - { - RADEONInfoPtr info = RADEONPTR (pScrn); - RADEONPLLPtr pll = &info->pll; -- CARD16 pll_info_block; -+ uint16_t pll_info_block; - - if (!info->VBIOS) { - return FALSE; -@@ -620,6 +879,9 @@ Bool RADEONGetDAC2InfoFromBIOS (xf86OutputPtr output) - - if (!info->VBIOS) return FALSE; - -+ if (xf86ReturnOptValBool(info->Options, OPTION_DEFAULT_TVDAC_ADJ, FALSE)) -+ return FALSE; -+ - if (info->IsAtomBios) { - /* not implemented yet */ - return FALSE; -@@ -628,7 +890,21 @@ Bool RADEONGetDAC2InfoFromBIOS (xf86OutputPtr output) - offset = RADEON_BIOS16(info->ROMHeaderStart + 0x32); - if (offset) { - rev = RADEON_BIOS8(offset + 0x3); -- if (rev > 1) { -+ if (rev > 4) { -+ bg = RADEON_BIOS8(offset + 0xc) & 0xf; -+ dac = RADEON_BIOS8(offset + 0xd) & 0xf; -+ radeon_output->ps2_tvdac_adj = (bg << 16) | (dac << 20); -+ -+ bg = RADEON_BIOS8(offset + 0xe) & 0xf; -+ dac = RADEON_BIOS8(offset + 0xf) & 0xf; -+ radeon_output->pal_tvdac_adj = (bg << 16) | (dac << 20); -+ -+ bg = RADEON_BIOS8(offset + 0x10) & 0xf; -+ dac = RADEON_BIOS8(offset + 0x11) & 0xf; -+ radeon_output->ntsc_tvdac_adj = (bg << 16) | (dac << 20); -+ -+ return TRUE; -+ } else if (rev > 1) { - bg = RADEON_BIOS8(offset + 0xc) & 0xf; - dac = (RADEON_BIOS8(offset + 0xc) >> 4) & 0xf; - radeon_output->ps2_tvdac_adj = (bg << 16) | (dac << 20); -@@ -656,6 +932,14 @@ Bool RADEONGetDAC2InfoFromBIOS (xf86OutputPtr output) - radeon_output->ntsc_tvdac_adj = radeon_output->ps2_tvdac_adj; - - return TRUE; -+ } else { -+ bg = RADEON_BIOS8(offset + 0x4) & 0xf; -+ dac = RADEON_BIOS8(offset + 0x5) & 0xf; -+ radeon_output->ps2_tvdac_adj = (bg << 16) | (dac << 20); -+ radeon_output->pal_tvdac_adj = radeon_output->ps2_tvdac_adj; -+ radeon_output->ntsc_tvdac_adj = radeon_output->ps2_tvdac_adj; -+ -+ return TRUE; - } - } - } -@@ -793,16 +1077,16 @@ Bool RADEONGetHardCodedEDIDFromBIOS (xf86OutputPtr output) - - memcpy(EDID, (char*)(info->VBIOS + tmp), 256); - -- radeon_output->DotClock = (*(CARD16*)(EDID+54)) * 10; -- radeon_output->PanelXRes = (*(CARD8*)(EDID+56)) + ((*(CARD8*)(EDID+58))>>4)*256; -- radeon_output->HBlank = (*(CARD8*)(EDID+57)) + ((*(CARD8*)(EDID+58)) & 0xf)*256; -- radeon_output->HOverPlus = (*(CARD8*)(EDID+62)) + ((*(CARD8*)(EDID+65)>>6)*256); -- radeon_output->HSyncWidth = (*(CARD8*)(EDID+63)) + (((*(CARD8*)(EDID+65)>>4) & 3)*256); -- radeon_output->PanelYRes = (*(CARD8*)(EDID+59)) + ((*(CARD8*)(EDID+61))>>4)*256; -- radeon_output->VBlank = ((*(CARD8*)(EDID+60)) + ((*(CARD8*)(EDID+61)) & 0xf)*256); -- radeon_output->VOverPlus = (((*(CARD8*)(EDID+64))>>4) + (((*(CARD8*)(EDID+65)>>2) & 3)*16)); -- radeon_output->VSyncWidth = (((*(CARD8*)(EDID+64)) & 0xf) + ((*(CARD8*)(EDID+65)) & 3)*256); -- radeon_output->Flags = V_NHSYNC | V_NVSYNC; /**(CARD8*)(EDID+71);*/ -+ radeon_output->DotClock = (*(uint16_t*)(EDID+54)) * 10; -+ radeon_output->PanelXRes = (*(uint8_t*)(EDID+56)) + ((*(uint8_t*)(EDID+58))>>4)*256; -+ radeon_output->HBlank = (*(uint8_t*)(EDID+57)) + ((*(uint8_t*)(EDID+58)) & 0xf)*256; -+ radeon_output->HOverPlus = (*(uint8_t*)(EDID+62)) + ((*(uint8_t*)(EDID+65)>>6)*256); -+ radeon_output->HSyncWidth = (*(uint8_t*)(EDID+63)) + (((*(uint8_t*)(EDID+65)>>4) & 3)*256); -+ radeon_output->PanelYRes = (*(uint8_t*)(EDID+59)) + ((*(uint8_t*)(EDID+61))>>4)*256; -+ radeon_output->VBlank = ((*(uint8_t*)(EDID+60)) + ((*(uint8_t*)(EDID+61)) & 0xf)*256); -+ radeon_output->VOverPlus = (((*(uint8_t*)(EDID+64))>>4) + (((*(uint8_t*)(EDID+65)>>2) & 3)*16)); -+ radeon_output->VSyncWidth = (((*(uint8_t*)(EDID+64)) & 0xf) + ((*(uint8_t*)(EDID+65)) & 3)*256); -+ radeon_output->Flags = V_NHSYNC | V_NVSYNC; /**(uint8_t*)(EDID+71);*/ - xf86DrvMsg(pScrn->scrnIndex, X_INFO, "Hardcoded EDID data will be used for TMDS panel\n"); - } - return TRUE; -@@ -813,7 +1097,7 @@ Bool RADEONGetTMDSInfoFromBIOS (xf86OutputPtr output) - ScrnInfoPtr pScrn = output->scrn; - RADEONInfoPtr info = RADEONPTR(pScrn); - RADEONOutputPrivatePtr radeon_output = output->driver_private; -- CARD32 tmp, maxfreq; -+ uint32_t tmp, maxfreq; - int i, n; - - if (!info->VBIOS) return FALSE; -@@ -934,7 +1218,7 @@ Bool RADEONInitExtTMDSInfoFromBIOS (xf86OutputPtr output) - unsigned char *RADEONMMIO = info->MMIO; - RADEONOutputPrivatePtr radeon_output = output->driver_private; - int offset, index, id; -- CARD32 val, reg, andmask, ormask; -+ uint32_t val, reg, andmask, ormask; - - if (!info->VBIOS) return FALSE; - -@@ -1044,11 +1328,11 @@ Bool RADEONInitExtTMDSInfoFromBIOS (xf86OutputPtr output) - #define RADEON_PLL_WAIT_DLL_READY_MASK 4 - #define RADEON_PLL_WAIT_CHK_SET_CLK_PWRMGT_CNTL24 5 - --static CARD16 --RADEONValidateBIOSOffset(ScrnInfoPtr pScrn, CARD16 offset) -+static uint16_t -+RADEONValidateBIOSOffset(ScrnInfoPtr pScrn, uint16_t offset) - { - RADEONInfoPtr info = RADEONPTR (pScrn); -- CARD8 revision = RADEON_BIOS8(offset - 1); -+ uint8_t revision = RADEON_BIOS8(offset - 1); - - if (revision > 0x10) { - xf86DrvMsg(pScrn->scrnIndex, X_WARNING, -@@ -1069,7 +1353,7 @@ Bool - RADEONGetBIOSInitTableOffsets(ScrnInfoPtr pScrn) - { - RADEONInfoPtr info = RADEONPTR (pScrn); -- CARD8 val; -+ uint8_t val; - - if (!info->VBIOS) { - return FALSE; -@@ -1163,14 +1447,14 @@ RADEONGetBIOSInitTableOffsets(ScrnInfoPtr pScrn) - } - - static void --RADEONRestoreBIOSRegBlock(ScrnInfoPtr pScrn, CARD16 table_offset) -+RADEONRestoreBIOSRegBlock(ScrnInfoPtr pScrn, uint16_t table_offset) - { - RADEONInfoPtr info = RADEONPTR (pScrn); - unsigned char *RADEONMMIO = info->MMIO; -- CARD16 offset = table_offset; -- CARD16 value, flag, index, count; -- CARD32 andmask, ormask, val, channel_complete_mask; -- CARD8 command; -+ uint16_t offset = table_offset; -+ uint16_t value, flag, index, count; -+ uint32_t andmask, ormask, val, channel_complete_mask; -+ uint8_t command; - - if (offset == 0) - return; -@@ -1271,14 +1555,14 @@ RADEONRestoreBIOSRegBlock(ScrnInfoPtr pScrn, CARD16 table_offset) - } - - static void --RADEONRestoreBIOSMemBlock(ScrnInfoPtr pScrn, CARD16 table_offset) -+RADEONRestoreBIOSMemBlock(ScrnInfoPtr pScrn, uint16_t table_offset) - { - RADEONInfoPtr info = RADEONPTR (pScrn); - unsigned char *RADEONMMIO = info->MMIO; -- CARD16 offset = table_offset; -- CARD16 count; -- CARD32 ormask, val, channel_complete_mask; -- CARD8 index; -+ uint16_t offset = table_offset; -+ uint16_t count; -+ uint32_t ormask, val, channel_complete_mask; -+ uint8_t index; - - if (offset == 0) - return; -@@ -1315,7 +1599,7 @@ RADEONRestoreBIOSMemBlock(ScrnInfoPtr pScrn, CARD16 table_offset) - val = (val & RADEON_SDRAM_MODE_MASK) | ormask; - OUTREG(RADEON_MM_DATA, val); - -- ormask = (CARD32)index << 24; -+ ormask = (uint32_t)index << 24; - - ErrorF("INDEX RADEON_MEM_SDRAM_MODE_REG %x %x\n", - RADEON_B3MEM_RESET_MASK, (unsigned)ormask); -@@ -1330,13 +1614,13 @@ RADEONRestoreBIOSMemBlock(ScrnInfoPtr pScrn, CARD16 table_offset) - } - - static void --RADEONRestoreBIOSPllBlock(ScrnInfoPtr pScrn, CARD16 table_offset) -+RADEONRestoreBIOSPllBlock(ScrnInfoPtr pScrn, uint16_t table_offset) - { - RADEONInfoPtr info = RADEONPTR (pScrn); -- CARD16 offset = table_offset; -- CARD8 index, shift; -- CARD32 andmask, ormask, val, clk_pwrmgt_cntl; -- CARD16 count; -+ uint16_t offset = table_offset; -+ uint8_t index, shift; -+ uint32_t andmask, ormask, val, clk_pwrmgt_cntl; -+ uint16_t count; - - if (offset == 0) - return; -@@ -1398,11 +1682,11 @@ RADEONRestoreBIOSPllBlock(ScrnInfoPtr pScrn, CARD16 table_offset) - offset++; - - andmask = -- (((CARD32)RADEON_BIOS8(offset)) << shift) | -- ~((CARD32)0xff << shift); -+ (((uint32_t)RADEON_BIOS8(offset)) << shift) | -+ ~((uint32_t)0xff << shift); - offset++; - -- ormask = ((CARD32)RADEON_BIOS8(offset)) << shift; -+ ormask = ((uint32_t)RADEON_BIOS8(offset)) << shift; - offset++; - - ErrorF("PLL_MASK_BYTE 0x%x 0x%x 0x%x 0x%x\n", -diff --git a/src/radeon_chipinfo_gen.h b/src/radeon_chipinfo_gen.h -index 420f5d8..0d7d085 100644 ---- a/src/radeon_chipinfo_gen.h -+++ b/src/radeon_chipinfo_gen.h -@@ -1,6 +1,7 @@ - /* This file is autogenerated please do not edit */ - RADEONCardInfo RADEONCards[] = { - { 0x3150, CHIP_FAMILY_RV380, 1, 0, 0, 0, 0 }, -+ { 0x3151, CHIP_FAMILY_RV380, 0, 0, 0, 0, 0 }, - { 0x3152, CHIP_FAMILY_RV380, 1, 0, 0, 0, 0 }, - { 0x3154, CHIP_FAMILY_RV380, 1, 0, 0, 0, 0 }, - { 0x3E50, CHIP_FAMILY_RV380, 0, 0, 0, 0, 0 }, -@@ -96,18 +97,19 @@ RADEONCardInfo RADEONCards[] = { - { 0x564F, CHIP_FAMILY_RV410, 1, 0, 0, 0, 0 }, - { 0x5652, CHIP_FAMILY_RV410, 1, 0, 0, 0, 0 }, - { 0x5653, CHIP_FAMILY_RV410, 1, 0, 0, 0, 0 }, -+ { 0x5657, CHIP_FAMILY_RV410, 0, 0, 0, 0, 0 }, - { 0x5834, CHIP_FAMILY_RS300, 0, 1, 0, 0, 1 }, - { 0x5835, CHIP_FAMILY_RS300, 1, 1, 0, 0, 1 }, -- { 0x5954, CHIP_FAMILY_RS400, 0, 1, 0, 0, 1 }, -- { 0x5955, CHIP_FAMILY_RS400, 1, 1, 0, 0, 1 }, -+ { 0x5954, CHIP_FAMILY_RS480, 0, 1, 0, 0, 1 }, -+ { 0x5955, CHIP_FAMILY_RS480, 1, 1, 0, 0, 1 }, - { 0x5960, CHIP_FAMILY_RV280, 0, 0, 0, 0, 0 }, - { 0x5961, CHIP_FAMILY_RV280, 0, 0, 0, 0, 0 }, - { 0x5962, CHIP_FAMILY_RV280, 0, 0, 0, 0, 0 }, - { 0x5964, CHIP_FAMILY_RV280, 0, 0, 0, 0, 0 }, - { 0x5965, CHIP_FAMILY_RV280, 0, 0, 0, 0, 0 }, - { 0x5969, CHIP_FAMILY_RV100, 0, 0, 1, 0, 0 }, -- { 0x5974, CHIP_FAMILY_RS400, 0, 1, 0, 0, 1 }, -- { 0x5975, CHIP_FAMILY_RS400, 1, 1, 0, 0, 1 }, -+ { 0x5974, CHIP_FAMILY_RS480, 1, 1, 0, 0, 1 }, -+ { 0x5975, CHIP_FAMILY_RS480, 1, 1, 0, 0, 1 }, - { 0x5A41, CHIP_FAMILY_RS400, 0, 1, 0, 0, 1 }, - { 0x5A42, CHIP_FAMILY_RS400, 1, 1, 0, 0, 1 }, - { 0x5A61, CHIP_FAMILY_RS400, 0, 1, 0, 0, 1 }, -@@ -115,7 +117,6 @@ RADEONCardInfo RADEONCards[] = { - { 0x5B60, CHIP_FAMILY_RV380, 0, 0, 0, 0, 0 }, - { 0x5B62, CHIP_FAMILY_RV380, 0, 0, 0, 0, 0 }, - { 0x5B63, CHIP_FAMILY_RV380, 0, 0, 0, 0, 0 }, -- { 0x5657, CHIP_FAMILY_RV380, 0, 0, 0, 0, 0 }, - { 0x5B64, CHIP_FAMILY_RV380, 0, 0, 0, 0, 0 }, - { 0x5B65, CHIP_FAMILY_RV380, 0, 0, 0, 0, 0 }, - { 0x5C61, CHIP_FAMILY_RV280, 1, 0, 0, 0, 0 }, -@@ -201,9 +202,9 @@ RADEONCardInfo RADEONCards[] = { - { 0x71D6, CHIP_FAMILY_RV530, 1, 0, 0, 0, 0 }, - { 0x71DA, CHIP_FAMILY_RV530, 0, 0, 0, 0, 0 }, - { 0x71DE, CHIP_FAMILY_RV530, 1, 0, 0, 0, 0 }, -- { 0x7200, CHIP_FAMILY_RV530, 0, 0, 0, 0, 0 }, -- { 0x7210, CHIP_FAMILY_RV530, 1, 0, 0, 0, 0 }, -- { 0x7211, CHIP_FAMILY_RV530, 1, 0, 0, 0, 0 }, -+ { 0x7200, CHIP_FAMILY_RV515, 0, 0, 0, 0, 0 }, -+ { 0x7210, CHIP_FAMILY_RV515, 1, 0, 0, 0, 0 }, -+ { 0x7211, CHIP_FAMILY_RV515, 1, 0, 0, 0, 0 }, - { 0x7240, CHIP_FAMILY_R580, 0, 0, 0, 0, 0 }, - { 0x7243, CHIP_FAMILY_R580, 0, 0, 0, 0, 0 }, - { 0x7244, CHIP_FAMILY_R580, 0, 0, 0, 0, 0 }, -@@ -235,6 +236,9 @@ RADEONCardInfo RADEONCards[] = { - { 0x7835, CHIP_FAMILY_RS300, 1, 1, 0, 0, 1 }, - { 0x791E, CHIP_FAMILY_RS690, 0, 1, 0, 0, 1 }, - { 0x791F, CHIP_FAMILY_RS690, 0, 1, 0, 0, 1 }, -+ { 0x793F, CHIP_FAMILY_RS600, 0, 1, 0, 0, 1 }, -+ { 0x7941, CHIP_FAMILY_RS600, 0, 1, 0, 0, 1 }, -+ { 0x7942, CHIP_FAMILY_RS600, 0, 1, 0, 0, 1 }, - { 0x796C, CHIP_FAMILY_RS740, 0, 1, 0, 0, 1 }, - { 0x796D, CHIP_FAMILY_RS740, 0, 1, 0, 0, 1 }, - { 0x796E, CHIP_FAMILY_RS740, 0, 1, 0, 0, 1 }, -@@ -247,6 +251,8 @@ RADEONCardInfo RADEONCards[] = { - { 0x940A, CHIP_FAMILY_R600, 0, 0, 0, 0, 0 }, - { 0x940B, CHIP_FAMILY_R600, 0, 0, 0, 0, 0 }, - { 0x940F, CHIP_FAMILY_R600, 0, 0, 0, 0, 0 }, -+ { 0x9440, CHIP_FAMILY_RV770, 0, 0, 0, 0, 0 }, -+ { 0x9442, CHIP_FAMILY_RV770, 0, 0, 0, 0, 0 }, - { 0x94C0, CHIP_FAMILY_RV610, 0, 0, 0, 0, 0 }, - { 0x94C1, CHIP_FAMILY_RV610, 0, 0, 0, 0, 0 }, - { 0x94C3, CHIP_FAMILY_RV610, 0, 0, 0, 0, 0 }, -@@ -264,6 +270,7 @@ RADEONCardInfo RADEONCards[] = { - { 0x9507, CHIP_FAMILY_RV670, 0, 0, 0, 0, 0 }, - { 0x950F, CHIP_FAMILY_RV670, 0, 0, 0, 0, 0 }, - { 0x9511, CHIP_FAMILY_RV670, 0, 0, 0, 0, 0 }, -+ { 0x9515, CHIP_FAMILY_RV670, 0, 0, 0, 0, 0 }, - { 0x9580, CHIP_FAMILY_RV630, 0, 0, 0, 0, 0 }, - { 0x9581, CHIP_FAMILY_RV630, 1, 0, 0, 0, 0 }, - { 0x9583, CHIP_FAMILY_RV630, 1, 0, 0, 0, 0 }, -@@ -276,4 +283,23 @@ RADEONCardInfo RADEONCards[] = { - { 0x958C, CHIP_FAMILY_RV630, 0, 0, 0, 0, 0 }, - { 0x958D, CHIP_FAMILY_RV630, 0, 0, 0, 0, 0 }, - { 0x958E, CHIP_FAMILY_RV630, 0, 0, 0, 0, 0 }, -+ { 0x95C0, CHIP_FAMILY_RV620, 0, 0, 0, 0, 0 }, -+ { 0x95C5, CHIP_FAMILY_RV620, 0, 0, 0, 0, 0 }, -+ { 0x95C7, CHIP_FAMILY_RV620, 0, 0, 0, 0, 0 }, -+ { 0x95C2, CHIP_FAMILY_RV620, 1, 0, 0, 0, 0 }, -+ { 0x95C4, CHIP_FAMILY_RV620, 1, 0, 0, 0, 0 }, -+ { 0x95CD, CHIP_FAMILY_RV620, 0, 0, 0, 0, 0 }, -+ { 0x95CE, CHIP_FAMILY_RV620, 0, 0, 0, 0, 0 }, -+ { 0x95CF, CHIP_FAMILY_RV620, 0, 0, 0, 0, 0 }, -+ { 0x9590, CHIP_FAMILY_RV635, 0, 0, 0, 0, 0 }, -+ { 0x9596, CHIP_FAMILY_RV635, 0, 0, 0, 0, 0 }, -+ { 0x9597, CHIP_FAMILY_RV635, 0, 0, 0, 0, 0 }, -+ { 0x9598, CHIP_FAMILY_RV635, 0, 0, 0, 0, 0 }, -+ { 0x9599, CHIP_FAMILY_RV635, 0, 0, 0, 0, 0 }, -+ { 0x9591, CHIP_FAMILY_RV635, 1, 0, 0, 0, 0 }, -+ { 0x9593, CHIP_FAMILY_RV635, 1, 0, 0, 0, 0 }, -+ { 0x9610, CHIP_FAMILY_RS780, 0, 1, 0, 0, 1 }, -+ { 0x9611, CHIP_FAMILY_RS780, 0, 1, 0, 0, 1 }, -+ { 0x9612, CHIP_FAMILY_RS780, 0, 1, 0, 0, 1 }, -+ { 0x9613, CHIP_FAMILY_RS780, 0, 1, 0, 0, 1 }, - }; -diff --git a/src/radeon_chipset_gen.h b/src/radeon_chipset_gen.h -index e6890be..96b60e9 100644 ---- a/src/radeon_chipset_gen.h -+++ b/src/radeon_chipset_gen.h -@@ -1,6 +1,7 @@ - /* This file is autogenerated please do not edit */ - static SymTabRec RADEONChipsets[] = { - { PCI_CHIP_RV380_3150, "ATI Radeon Mobility X600 (M24) 3150 (PCIE)" }, -+ { PCI_CHIP_RV380_3151, "ATI FireMV 2400 (PCI)" }, - { PCI_CHIP_RV380_3152, "ATI Radeon Mobility X300 (M24) 3152 (PCIE)" }, - { PCI_CHIP_RV380_3154, "ATI FireGL M24 GL 3154 (PCIE)" }, - { PCI_CHIP_RV380_3E50, "ATI Radeon X600 (RV380) 3E50 (PCIE)" }, -@@ -96,6 +97,7 @@ static SymTabRec RADEONChipsets[] = { - { PCI_CHIP_RV410_564F, "ATI Mobility Radeon X700 XL (M26) (PCIE)" }, - { PCI_CHIP_RV410_5652, "ATI Mobility Radeon X700 (M26) (PCIE)" }, - { PCI_CHIP_RV410_5653, "ATI Mobility Radeon X700 (M26) (PCIE)" }, -+ { PCI_CHIP_RV410_5657, "ATI Radeon X550XTX 5657 (PCIE)" }, - { PCI_CHIP_RS300_5834, "ATI Radeon 9100 IGP (A5) 5834" }, - { PCI_CHIP_RS300_5835, "ATI Radeon Mobility 9100 IGP (U3) 5835" }, - { PCI_CHIP_RS480_5954, "ATI Radeon XPRESS 200 5954 (PCIE)" }, -@@ -115,7 +117,6 @@ static SymTabRec RADEONChipsets[] = { - { PCI_CHIP_RV370_5B60, "ATI Radeon X300 (RV370) 5B60 (PCIE)" }, - { PCI_CHIP_RV370_5B62, "ATI Radeon X600 (RV370) 5B62 (PCIE)" }, - { PCI_CHIP_RV370_5B63, "ATI Radeon X550 (RV370) 5B63 (PCIE)" }, -- { PCI_CHIP_RV370_5657, "ATI Radeon X550XTX (RV370) 5657 (PCIE)" }, - { PCI_CHIP_RV370_5B64, "ATI FireGL V3100 (RV370) 5B64 (PCIE)" }, - { PCI_CHIP_RV370_5B65, "ATI FireMV 2200 PCIE (RV370) 5B65 (PCIE)" }, - { PCI_CHIP_RV280_5C61, "ATI Radeon Mobility 9200 (M9+) 5C61 (AGP)" }, -@@ -201,9 +202,9 @@ static SymTabRec RADEONChipsets[] = { - { PCI_CHIP_RV530_71D6, "ATI Mobility Radeon X1700 XT" }, - { PCI_CHIP_RV530_71DA, "ATI FireGL V5200" }, - { PCI_CHIP_RV530_71DE, "ATI Mobility Radeon X1700" }, -- { PCI_CHIP_RV530_7200, "ATI Radeon X2300HD" }, -- { PCI_CHIP_RV530_7210, "ATI Mobility Radeon HD 2300" }, -- { PCI_CHIP_RV530_7211, "ATI Mobility Radeon HD 2300" }, -+ { PCI_CHIP_RV515_7200, "ATI Radeon X2300HD" }, -+ { PCI_CHIP_RV515_7210, "ATI Mobility Radeon HD 2300" }, -+ { PCI_CHIP_RV515_7211, "ATI Mobility Radeon HD 2300" }, - { PCI_CHIP_R580_7240, "ATI Radeon X1950" }, - { PCI_CHIP_R580_7243, "ATI Radeon X1900" }, - { PCI_CHIP_R580_7244, "ATI Radeon X1950" }, -@@ -235,6 +236,9 @@ static SymTabRec RADEONChipsets[] = { - { PCI_CHIP_RS350_7835, "ATI Radeon Mobility 9200 IGP 7835" }, - { PCI_CHIP_RS690_791E, "ATI Radeon X1200" }, - { PCI_CHIP_RS690_791F, "ATI Radeon X1200" }, -+ { PCI_CHIP_RS600_793F, "ATI Radeon X1200" }, -+ { PCI_CHIP_RS600_7941, "ATI Radeon X1200" }, -+ { PCI_CHIP_RS600_7942, "ATI Radeon X1200" }, - { PCI_CHIP_RS740_796C, "ATI RS740" }, - { PCI_CHIP_RS740_796D, "ATI RS740M" }, - { PCI_CHIP_RS740_796E, "ATI RS740" }, -@@ -247,16 +251,18 @@ static SymTabRec RADEONChipsets[] = { - { PCI_CHIP_R600_940A, "ATI FireGL V8650" }, - { PCI_CHIP_R600_940B, "ATI FireGL V8600" }, - { PCI_CHIP_R600_940F, "ATI FireGL V7600" }, -+ { PCI_CHIP_RV770_9440, "ATI Radeon 4800 Series" }, -+ { PCI_CHIP_RV770_9442, "ATI Radeon 4800 Series" }, - { PCI_CHIP_RV610_94C0, "ATI RV610" }, - { PCI_CHIP_RV610_94C1, "ATI Radeon HD 2400 XT" }, - { PCI_CHIP_RV610_94C3, "ATI Radeon HD 2400 Pro" }, -- { PCI_CHIP_RV610_94C4, "ATI ATI Radeon HD 2400 PRO AGP" }, -+ { PCI_CHIP_RV610_94C4, "ATI Radeon HD 2400 PRO AGP" }, - { PCI_CHIP_RV610_94C5, "ATI FireGL V4000" }, - { PCI_CHIP_RV610_94C6, "ATI RV610" }, - { PCI_CHIP_RV610_94C7, "ATI ATI Radeon HD 2350" }, - { PCI_CHIP_RV610_94C8, "ATI Mobility Radeon HD 2400 XT" }, - { PCI_CHIP_RV610_94C9, "ATI Mobility Radeon HD 2400" }, -- { PCI_CHIP_RV610_94CB, "ATI ATI RADEON E2400" }, -+ { PCI_CHIP_RV610_94CB, "ATI RADEON E2400" }, - { PCI_CHIP_RV610_94CC, "ATI RV610" }, - { PCI_CHIP_RV670_9500, "ATI RV670" }, - { PCI_CHIP_RV670_9501, "ATI Radeon HD3870" }, -@@ -264,17 +270,37 @@ static SymTabRec RADEONChipsets[] = { - { PCI_CHIP_RV670_9507, "ATI RV670" }, - { PCI_CHIP_RV670_950F, "ATI Radeon HD3870 X2" }, - { PCI_CHIP_RV670_9511, "ATI FireGL V7700" }, -+ { PCI_CHIP_RV670_9515, "ATI Radeon HD3850" }, - { PCI_CHIP_RV630_9580, "ATI RV630" }, - { PCI_CHIP_RV630_9581, "ATI Mobility Radeon HD 2600" }, - { PCI_CHIP_RV630_9583, "ATI Mobility Radeon HD 2600 XT" }, -- { PCI_CHIP_RV630_9586, "ATI ATI Radeon HD 2600 XT AGP" }, -- { PCI_CHIP_RV630_9587, "ATI ATI Radeon HD 2600 Pro AGP" }, -+ { PCI_CHIP_RV630_9586, "ATI Radeon HD 2600 XT AGP" }, -+ { PCI_CHIP_RV630_9587, "ATI Radeon HD 2600 Pro AGP" }, - { PCI_CHIP_RV630_9588, "ATI Radeon HD 2600 XT" }, - { PCI_CHIP_RV630_9589, "ATI Radeon HD 2600 Pro" }, - { PCI_CHIP_RV630_958A, "ATI Gemini RV630" }, -- { PCI_CHIP_RV630_958B, "ATI Gemini ATI Mobility Radeon HD 2600 XT" }, -+ { PCI_CHIP_RV630_958B, "ATI Gemini Mobility Radeon HD 2600 XT" }, - { PCI_CHIP_RV630_958C, "ATI FireGL V5600" }, - { PCI_CHIP_RV630_958D, "ATI FireGL V3600" }, -- { PCI_CHIP_RV630_958E, "ATI ATI Radeon HD 2600 LE" }, -+ { PCI_CHIP_RV630_958E, "ATI Radeon HD 2600 LE" }, -+ { PCI_CHIP_RV620_95C0, "ATI Radeon HD 3470" }, -+ { PCI_CHIP_RV620_95C5, "ATI Radeon HD 3450" }, -+ { PCI_CHIP_RV620_95C7, "ATI Radeon HD 3430" }, -+ { PCI_CHIP_RV620_95C2, "ATI Mobility Radeon HD 3430" }, -+ { PCI_CHIP_RV620_95C4, "ATI Mobility Radeon HD 3400 Series" }, -+ { PCI_CHIP_RV620_95CD, "ATI FireMV 2450" }, -+ { PCI_CHIP_RV620_95CE, "ATI FireMV 2260" }, -+ { PCI_CHIP_RV620_95CF, "ATI FireMV 2260" }, -+ { PCI_CHIP_RV635_9590, "ATI ATI Radeon HD 3600 Series" }, -+ { PCI_CHIP_RV635_9596, "ATI ATI Radeon HD 3650 AGP" }, -+ { PCI_CHIP_RV635_9597, "ATI ATI Radeon HD 3600 PRO" }, -+ { PCI_CHIP_RV635_9598, "ATI ATI Radeon HD 3600 XT" }, -+ { PCI_CHIP_RV635_9599, "ATI ATI Radeon HD 3600 PRO" }, -+ { PCI_CHIP_RV635_9591, "ATI Mobility Radeon HD 3650" }, -+ { PCI_CHIP_RV635_9593, "ATI Mobility Radeon HD 3670" }, -+ { PCI_CHIP_RS780_9610, "ATI Radeon HD 3200 Graphics" }, -+ { PCI_CHIP_RS780_9611, "ATI Radeon 3100 Graphics" }, -+ { PCI_CHIP_RS780_9612, "ATI Radeon HD 3200 Graphics" }, -+ { PCI_CHIP_RS780_9613, "ATI Radeon 3100 Graphics" }, - { -1, NULL } - }; -diff --git a/src/radeon_common.h b/src/radeon_common.h -index 467addf..193c1f9 100644 ---- a/src/radeon_common.h -+++ b/src/radeon_common.h -@@ -422,6 +422,8 @@ typedef union { - #define RADEON_PARAM_SCRATCH_OFFSET 11 - #define RADEON_PARAM_CARD_TYPE 12 - #define RADEON_PARAM_VBLANK_CRTC 13 /* VBLANK CRTC */ -+#define RADEON_PARAM_FB_LOCATION 14 /* FB location */ -+#define RADEON_PARAM_NUM_GB_PIPES 15 - - typedef struct drm_radeon_getparam { - int param; -diff --git a/src/radeon_commonfuncs.c b/src/radeon_commonfuncs.c -index 0250aef..d0c5229 100644 ---- a/src/radeon_commonfuncs.c -+++ b/src/radeon_commonfuncs.c -@@ -55,53 +55,49 @@ - static void FUNC_NAME(RADEONInit3DEngine)(ScrnInfoPtr pScrn) - { - RADEONInfoPtr info = RADEONPTR(pScrn); -- CARD32 gb_tile_config; -+ uint32_t gb_tile_config, su_reg_dest, vap_cntl; - ACCEL_PREAMBLE(); - - info->texW[0] = info->texH[0] = info->texW[1] = info->texH[1] = 1; - -- if (IS_R300_VARIANT || IS_AVIVO_VARIANT || info->ChipFamily == CHIP_FAMILY_RS690) { -+ if (IS_R300_3D || IS_R500_3D) { - - BEGIN_ACCEL(3); - OUT_ACCEL_REG(R300_RB3D_DSTCACHE_CTLSTAT, R300_DC_FLUSH_3D | R300_DC_FREE_3D); - OUT_ACCEL_REG(R300_RB3D_ZCACHE_CTLSTAT, R300_ZC_FLUSH | R300_ZC_FREE); -- OUT_ACCEL_REG(R300_WAIT_UNTIL, R300_WAIT_2D_IDLECLEAN | R300_WAIT_3D_IDLECLEAN); -+ OUT_ACCEL_REG(RADEON_WAIT_UNTIL, RADEON_WAIT_2D_IDLECLEAN | RADEON_WAIT_3D_IDLECLEAN); - FINISH_ACCEL(); - - gb_tile_config = (R300_ENABLE_TILING | R300_TILE_SIZE_16 | R300_SUBPIXEL_1_16); - -- if ((info->Chipset == PCI_CHIP_RV410_5E4C) || -- (info->Chipset == PCI_CHIP_RV410_5E4F)) { -- /* RV410 SE chips */ -- gb_tile_config |= R300_PIPE_COUNT_RV350; -- } else if ((info->ChipFamily == CHIP_FAMILY_RV350) || -- (info->ChipFamily == CHIP_FAMILY_RV380) || -- (info->ChipFamily == CHIP_FAMILY_RS400)) { -- /* RV3xx, RS4xx chips */ -- gb_tile_config |= R300_PIPE_COUNT_RV350; -- } else if ((info->ChipFamily == CHIP_FAMILY_R300) || -- (info->ChipFamily == CHIP_FAMILY_R350)) { -- /* R3xx chips */ -- gb_tile_config |= R300_PIPE_COUNT_R300; -- } else if ((info->ChipFamily == CHIP_FAMILY_RV410) || -- (info->ChipFamily == CHIP_FAMILY_RS690)) { -- /* RV4xx, RS6xx chips */ -- gb_tile_config |= R300_PIPE_COUNT_R420_3P; -- } else { -- /* R4xx, R5xx chips */ -- gb_tile_config |= R300_PIPE_COUNT_R420; -+ switch(info->num_gb_pipes) { -+ case 2: gb_tile_config |= R300_PIPE_COUNT_R300; break; -+ case 3: gb_tile_config |= R300_PIPE_COUNT_R420_3P; break; -+ case 4: gb_tile_config |= R300_PIPE_COUNT_R420; break; -+ default: -+ case 1: gb_tile_config |= R300_PIPE_COUNT_RV350; break; - } - -- BEGIN_ACCEL(3); -+ BEGIN_ACCEL(5); - OUT_ACCEL_REG(R300_GB_TILE_CONFIG, gb_tile_config); -+ OUT_ACCEL_REG(RADEON_WAIT_UNTIL, RADEON_WAIT_2D_IDLECLEAN | RADEON_WAIT_3D_IDLECLEAN); -+ OUT_ACCEL_REG(R300_DST_PIPE_CONFIG, R300_PIPE_AUTO_CONFIG); - OUT_ACCEL_REG(R300_GB_SELECT, 0); - OUT_ACCEL_REG(R300_GB_ENABLE, 0); - FINISH_ACCEL(); - -+ if (IS_R500_3D) { -+ su_reg_dest = ((1 << info->num_gb_pipes) - 1); -+ BEGIN_ACCEL(2); -+ OUT_ACCEL_REG(R500_SU_REG_DEST, su_reg_dest); -+ OUT_ACCEL_REG(R500_VAP_INDEX_OFFSET, 0); -+ FINISH_ACCEL(); -+ } -+ - BEGIN_ACCEL(3); - OUT_ACCEL_REG(R300_RB3D_DSTCACHE_CTLSTAT, R300_DC_FLUSH_3D | R300_DC_FREE_3D); - OUT_ACCEL_REG(R300_RB3D_ZCACHE_CTLSTAT, R300_ZC_FLUSH | R300_ZC_FREE); -- OUT_ACCEL_REG(R300_WAIT_UNTIL, R300_WAIT_2D_IDLECLEAN | R300_WAIT_3D_IDLECLEAN); -+ OUT_ACCEL_REG(RADEON_WAIT_UNTIL, RADEON_WAIT_2D_IDLECLEAN | RADEON_WAIT_3D_IDLECLEAN); - FINISH_ACCEL(); - - BEGIN_ACCEL(5); -@@ -125,7 +121,8 @@ static void FUNC_NAME(RADEONInit3DEngine)(ScrnInfoPtr pScrn) - (8 << R300_MSBD1_SHIFT))); - FINISH_ACCEL(); - -- BEGIN_ACCEL(4); -+ BEGIN_ACCEL(5); -+ OUT_ACCEL_REG(R300_GA_ENHANCE, R300_GA_DEADLOCK_CNTL | R300_GA_FASTSYNC_CNTL); - OUT_ACCEL_REG(R300_GA_POLY_MODE, R300_FRONT_PTYPE_TRIANGE | R300_BACK_PTYPE_TRIANGE); - OUT_ACCEL_REG(R300_GA_ROUND_MODE, (R300_GEOMETRY_ROUND_NEAREST | - R300_COLOR_ROUND_NEAREST)); -@@ -148,7 +145,400 @@ static void FUNC_NAME(RADEONInit3DEngine)(ScrnInfoPtr pScrn) - OUT_ACCEL_REG(R300_SU_DEPTH_OFFSET, 0); - FINISH_ACCEL(); - -- BEGIN_ACCEL(5); -+ /* setup the VAP */ -+ if (info->has_tcl) -+ vap_cntl = ((5 << R300_PVS_NUM_SLOTS_SHIFT) | -+ (5 << R300_PVS_NUM_CNTLRS_SHIFT) | -+ (9 << R300_VF_MAX_VTX_NUM_SHIFT)); -+ else -+ vap_cntl = ((10 << R300_PVS_NUM_SLOTS_SHIFT) | -+ (5 << R300_PVS_NUM_CNTLRS_SHIFT) | -+ (5 << R300_VF_MAX_VTX_NUM_SHIFT)); -+ -+ if (info->ChipFamily == CHIP_FAMILY_RV515) -+ vap_cntl |= (2 << R300_PVS_NUM_FPUS_SHIFT); -+ else if ((info->ChipFamily == CHIP_FAMILY_RV530) || -+ (info->ChipFamily == CHIP_FAMILY_RV560) || -+ (info->ChipFamily == CHIP_FAMILY_RV570)) -+ vap_cntl |= (5 << R300_PVS_NUM_FPUS_SHIFT); -+ else if ((info->ChipFamily == CHIP_FAMILY_RV410) || -+ (info->ChipFamily == CHIP_FAMILY_R420)) -+ vap_cntl |= (6 << R300_PVS_NUM_FPUS_SHIFT); -+ else if ((info->ChipFamily == CHIP_FAMILY_R520) || -+ (info->ChipFamily == CHIP_FAMILY_R580)) -+ vap_cntl |= (8 << R300_PVS_NUM_FPUS_SHIFT); -+ else -+ vap_cntl |= (4 << R300_PVS_NUM_FPUS_SHIFT); -+ -+ if (info->has_tcl) -+ BEGIN_ACCEL(15); -+ else -+ BEGIN_ACCEL(9); -+ OUT_ACCEL_REG(R300_VAP_VTX_STATE_CNTL, 0); -+ OUT_ACCEL_REG(R300_VAP_PVS_STATE_FLUSH_REG, 0); -+ -+ if (info->has_tcl) -+ OUT_ACCEL_REG(R300_VAP_CNTL_STATUS, 0); -+ else -+ OUT_ACCEL_REG(R300_VAP_CNTL_STATUS, R300_PVS_BYPASS); -+ OUT_ACCEL_REG(R300_VAP_CNTL, vap_cntl); -+ OUT_ACCEL_REG(R300_VAP_PVS_STATE_FLUSH_REG, 0); -+ OUT_ACCEL_REG(R300_VAP_VTE_CNTL, R300_VTX_XY_FMT | R300_VTX_Z_FMT); -+ OUT_ACCEL_REG(R300_VAP_PSC_SGN_NORM_CNTL, 0); -+ -+ OUT_ACCEL_REG(R300_VAP_PROG_STREAM_CNTL_EXT_0, -+ ((R300_SWIZZLE_SELECT_X << R300_SWIZZLE_SELECT_X_0_SHIFT) | -+ (R300_SWIZZLE_SELECT_Y << R300_SWIZZLE_SELECT_Y_0_SHIFT) | -+ (R300_SWIZZLE_SELECT_Z << R300_SWIZZLE_SELECT_Z_0_SHIFT) | -+ (R300_SWIZZLE_SELECT_W << R300_SWIZZLE_SELECT_W_0_SHIFT) | -+ ((R300_WRITE_ENA_X | R300_WRITE_ENA_Y | R300_WRITE_ENA_Z | R300_WRITE_ENA_W) -+ << R300_WRITE_ENA_0_SHIFT) | -+ (R300_SWIZZLE_SELECT_X << R300_SWIZZLE_SELECT_X_1_SHIFT) | -+ (R300_SWIZZLE_SELECT_Y << R300_SWIZZLE_SELECT_Y_1_SHIFT) | -+ (R300_SWIZZLE_SELECT_Z << R300_SWIZZLE_SELECT_Z_1_SHIFT) | -+ (R300_SWIZZLE_SELECT_W << R300_SWIZZLE_SELECT_W_1_SHIFT) | -+ ((R300_WRITE_ENA_X | R300_WRITE_ENA_Y | R300_WRITE_ENA_Z | R300_WRITE_ENA_W) -+ << R300_WRITE_ENA_1_SHIFT))); -+ OUT_ACCEL_REG(R300_VAP_PROG_STREAM_CNTL_EXT_1, -+ ((R300_SWIZZLE_SELECT_X << R300_SWIZZLE_SELECT_X_2_SHIFT) | -+ (R300_SWIZZLE_SELECT_Y << R300_SWIZZLE_SELECT_Y_2_SHIFT) | -+ (R300_SWIZZLE_SELECT_Z << R300_SWIZZLE_SELECT_Z_2_SHIFT) | -+ (R300_SWIZZLE_SELECT_W << R300_SWIZZLE_SELECT_W_2_SHIFT) | -+ ((R300_WRITE_ENA_X | R300_WRITE_ENA_Y | R300_WRITE_ENA_Z | R300_WRITE_ENA_W) -+ << R300_WRITE_ENA_2_SHIFT))); -+ -+ if (info->has_tcl) { -+ OUT_ACCEL_REG(R300_VAP_PVS_FLOW_CNTL_OPC, 0); -+ OUT_ACCEL_REG(R300_VAP_GB_VERT_CLIP_ADJ, 0x3f800000); -+ OUT_ACCEL_REG(R300_VAP_GB_VERT_DISC_ADJ, 0x3f800000); -+ OUT_ACCEL_REG(R300_VAP_GB_HORZ_CLIP_ADJ, 0x3f800000); -+ OUT_ACCEL_REG(R300_VAP_GB_HORZ_DISC_ADJ, 0x3f800000); -+ OUT_ACCEL_REG(R300_VAP_CLIP_CNTL, R300_CLIP_DISABLE); -+ } -+ FINISH_ACCEL(); -+ -+ /* pre-load the vertex shaders */ -+ if (info->has_tcl) { -+ /* exa mask shader program */ -+ BEGIN_ACCEL(13); -+ OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_INDX_REG, 0); -+ /* PVS inst 0 */ -+ OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_DATA_REG, -+ (R300_PVS_DST_OPCODE(R300_VE_ADD) | -+ R300_PVS_DST_REG_TYPE(R300_PVS_DST_REG_OUT) | -+ R300_PVS_DST_OFFSET(0) | -+ R300_PVS_DST_WE_X | R300_PVS_DST_WE_Y | -+ R300_PVS_DST_WE_Z | R300_PVS_DST_WE_W)); -+ OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_DATA_REG, -+ (R300_PVS_SRC_REG_TYPE(R300_PVS_SRC_REG_INPUT) | -+ R300_PVS_SRC_OFFSET(0) | -+ R300_PVS_SRC_SWIZZLE_X(R300_PVS_SRC_SELECT_X) | -+ R300_PVS_SRC_SWIZZLE_Y(R300_PVS_SRC_SELECT_Y) | -+ R300_PVS_SRC_SWIZZLE_Z(R300_PVS_SRC_SELECT_Z) | -+ R300_PVS_SRC_SWIZZLE_W(R300_PVS_SRC_SELECT_W))); -+ OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_DATA_REG, -+ (R300_PVS_SRC_REG_TYPE(R300_PVS_SRC_REG_INPUT) | -+ R300_PVS_SRC_OFFSET(0) | -+ R300_PVS_SRC_SWIZZLE_X(R300_PVS_SRC_SELECT_FORCE_0) | -+ R300_PVS_SRC_SWIZZLE_Y(R300_PVS_SRC_SELECT_FORCE_0) | -+ R300_PVS_SRC_SWIZZLE_Z(R300_PVS_SRC_SELECT_FORCE_0) | -+ R300_PVS_SRC_SWIZZLE_W(R300_PVS_SRC_SELECT_FORCE_0))); -+ OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_DATA_REG, -+ (R300_PVS_SRC_REG_TYPE(R300_PVS_SRC_REG_INPUT) | -+ R300_PVS_SRC_OFFSET(0) | -+ R300_PVS_SRC_SWIZZLE_X(R300_PVS_SRC_SELECT_FORCE_0) | -+ R300_PVS_SRC_SWIZZLE_Y(R300_PVS_SRC_SELECT_FORCE_0) | -+ R300_PVS_SRC_SWIZZLE_Z(R300_PVS_SRC_SELECT_FORCE_0) | -+ R300_PVS_SRC_SWIZZLE_W(R300_PVS_SRC_SELECT_FORCE_0))); -+ -+ /* PVS inst 1 */ -+ OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_DATA_REG, -+ (R300_PVS_DST_OPCODE(R300_VE_ADD) | -+ R300_PVS_DST_REG_TYPE(R300_PVS_DST_REG_OUT) | -+ R300_PVS_DST_OFFSET(1) | -+ R300_PVS_DST_WE_X | R300_PVS_DST_WE_Y | -+ R300_PVS_DST_WE_Z | R300_PVS_DST_WE_W)); -+ OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_DATA_REG, -+ (R300_PVS_SRC_REG_TYPE(R300_PVS_SRC_REG_INPUT) | -+ R300_PVS_SRC_OFFSET(6) | -+ R300_PVS_SRC_SWIZZLE_X(R300_PVS_SRC_SELECT_X) | -+ R300_PVS_SRC_SWIZZLE_Y(R300_PVS_SRC_SELECT_Y) | -+ R300_PVS_SRC_SWIZZLE_Z(R300_PVS_SRC_SELECT_Z) | -+ R300_PVS_SRC_SWIZZLE_W(R300_PVS_SRC_SELECT_W))); -+ OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_DATA_REG, -+ (R300_PVS_SRC_REG_TYPE(R300_PVS_SRC_REG_INPUT) | -+ R300_PVS_SRC_OFFSET(6) | -+ R300_PVS_SRC_SWIZZLE_X(R300_PVS_SRC_SELECT_FORCE_0) | -+ R300_PVS_SRC_SWIZZLE_Y(R300_PVS_SRC_SELECT_FORCE_0) | -+ R300_PVS_SRC_SWIZZLE_Z(R300_PVS_SRC_SELECT_FORCE_0) | -+ R300_PVS_SRC_SWIZZLE_W(R300_PVS_SRC_SELECT_FORCE_0))); -+ OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_DATA_REG, -+ (R300_PVS_SRC_REG_TYPE(R300_PVS_SRC_REG_INPUT) | -+ R300_PVS_SRC_OFFSET(6) | -+ R300_PVS_SRC_SWIZZLE_X(R300_PVS_SRC_SELECT_FORCE_0) | -+ R300_PVS_SRC_SWIZZLE_Y(R300_PVS_SRC_SELECT_FORCE_0) | -+ R300_PVS_SRC_SWIZZLE_Z(R300_PVS_SRC_SELECT_FORCE_0) | -+ R300_PVS_SRC_SWIZZLE_W(R300_PVS_SRC_SELECT_FORCE_0))); -+ -+ /* PVS inst 2 */ -+ OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_DATA_REG, -+ (R300_PVS_DST_OPCODE(R300_VE_ADD) | -+ R300_PVS_DST_REG_TYPE(R300_PVS_DST_REG_OUT) | -+ R300_PVS_DST_OFFSET(2) | -+ R300_PVS_DST_WE_X | R300_PVS_DST_WE_Y | -+ R300_PVS_DST_WE_Z | R300_PVS_DST_WE_W)); -+ OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_DATA_REG, -+ (R300_PVS_SRC_REG_TYPE(R300_PVS_SRC_REG_INPUT) | -+ R300_PVS_SRC_OFFSET(7) | -+ R300_PVS_SRC_SWIZZLE_X(R300_PVS_SRC_SELECT_X) | -+ R300_PVS_SRC_SWIZZLE_Y(R300_PVS_SRC_SELECT_Y) | -+ R300_PVS_SRC_SWIZZLE_Z(R300_PVS_SRC_SELECT_Z) | -+ R300_PVS_SRC_SWIZZLE_W(R300_PVS_SRC_SELECT_W))); -+ OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_DATA_REG, -+ (R300_PVS_SRC_REG_TYPE(R300_PVS_SRC_REG_INPUT) | -+ R300_PVS_SRC_OFFSET(7) | -+ R300_PVS_SRC_SWIZZLE_X(R300_PVS_SRC_SELECT_FORCE_0) | -+ R300_PVS_SRC_SWIZZLE_Y(R300_PVS_SRC_SELECT_FORCE_0) | -+ R300_PVS_SRC_SWIZZLE_Z(R300_PVS_SRC_SELECT_FORCE_0) | -+ R300_PVS_SRC_SWIZZLE_W(R300_PVS_SRC_SELECT_FORCE_0))); -+ OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_DATA_REG, -+ (R300_PVS_SRC_REG_TYPE(R300_PVS_SRC_REG_INPUT) | -+ R300_PVS_SRC_OFFSET(7) | -+ R300_PVS_SRC_SWIZZLE_X(R300_PVS_SRC_SELECT_FORCE_0) | -+ R300_PVS_SRC_SWIZZLE_Y(R300_PVS_SRC_SELECT_FORCE_0) | -+ R300_PVS_SRC_SWIZZLE_Z(R300_PVS_SRC_SELECT_FORCE_0) | -+ R300_PVS_SRC_SWIZZLE_W(R300_PVS_SRC_SELECT_FORCE_0))); -+ FINISH_ACCEL(); -+ -+ BEGIN_ACCEL(9); -+ /* exa no mask instruction */ -+ OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_INDX_REG, 3); -+ /* PVS inst 0 */ -+ OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_DATA_REG, -+ (R300_PVS_DST_OPCODE(R300_VE_ADD) | -+ R300_PVS_DST_REG_TYPE(R300_PVS_DST_REG_OUT) | -+ R300_PVS_DST_OFFSET(0) | -+ R300_PVS_DST_WE_X | R300_PVS_DST_WE_Y | -+ R300_PVS_DST_WE_Z | R300_PVS_DST_WE_W)); -+ OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_DATA_REG, -+ (R300_PVS_SRC_REG_TYPE(R300_PVS_SRC_REG_INPUT) | -+ R300_PVS_SRC_OFFSET(0) | -+ R300_PVS_SRC_SWIZZLE_X(R300_PVS_SRC_SELECT_X) | -+ R300_PVS_SRC_SWIZZLE_Y(R300_PVS_SRC_SELECT_Y) | -+ R300_PVS_SRC_SWIZZLE_Z(R300_PVS_SRC_SELECT_Z) | -+ R300_PVS_SRC_SWIZZLE_W(R300_PVS_SRC_SELECT_W))); -+ OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_DATA_REG, -+ (R300_PVS_SRC_REG_TYPE(R300_PVS_SRC_REG_INPUT) | -+ R300_PVS_SRC_OFFSET(0) | -+ R300_PVS_SRC_SWIZZLE_X(R300_PVS_SRC_SELECT_FORCE_0) | -+ R300_PVS_SRC_SWIZZLE_Y(R300_PVS_SRC_SELECT_FORCE_0) | -+ R300_PVS_SRC_SWIZZLE_Z(R300_PVS_SRC_SELECT_FORCE_0) | -+ R300_PVS_SRC_SWIZZLE_W(R300_PVS_SRC_SELECT_FORCE_0))); -+ OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_DATA_REG, -+ (R300_PVS_SRC_REG_TYPE(R300_PVS_SRC_REG_INPUT) | -+ R300_PVS_SRC_OFFSET(0) | -+ R300_PVS_SRC_SWIZZLE_X(R300_PVS_SRC_SELECT_FORCE_0) | -+ R300_PVS_SRC_SWIZZLE_Y(R300_PVS_SRC_SELECT_FORCE_0) | -+ R300_PVS_SRC_SWIZZLE_Z(R300_PVS_SRC_SELECT_FORCE_0) | -+ R300_PVS_SRC_SWIZZLE_W(R300_PVS_SRC_SELECT_FORCE_0))); -+ -+ /* PVS inst 1 */ -+ OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_DATA_REG, -+ (R300_PVS_DST_OPCODE(R300_VE_ADD) | -+ R300_PVS_DST_REG_TYPE(R300_PVS_DST_REG_OUT) | -+ R300_PVS_DST_OFFSET(1) | -+ R300_PVS_DST_WE_X | R300_PVS_DST_WE_Y | -+ R300_PVS_DST_WE_Z | R300_PVS_DST_WE_W)); -+ OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_DATA_REG, -+ (R300_PVS_SRC_REG_TYPE(R300_PVS_SRC_REG_INPUT) | -+ R300_PVS_SRC_OFFSET(6) | -+ R300_PVS_SRC_SWIZZLE_X(R300_PVS_SRC_SELECT_X) | -+ R300_PVS_SRC_SWIZZLE_Y(R300_PVS_SRC_SELECT_Y) | -+ R300_PVS_SRC_SWIZZLE_Z(R300_PVS_SRC_SELECT_Z) | -+ R300_PVS_SRC_SWIZZLE_W(R300_PVS_SRC_SELECT_W))); -+ OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_DATA_REG, -+ (R300_PVS_SRC_REG_TYPE(R300_PVS_SRC_REG_INPUT) | -+ R300_PVS_SRC_OFFSET(6) | -+ R300_PVS_SRC_SWIZZLE_X(R300_PVS_SRC_SELECT_FORCE_0) | -+ R300_PVS_SRC_SWIZZLE_Y(R300_PVS_SRC_SELECT_FORCE_0) | -+ R300_PVS_SRC_SWIZZLE_Z(R300_PVS_SRC_SELECT_FORCE_0) | -+ R300_PVS_SRC_SWIZZLE_W(R300_PVS_SRC_SELECT_FORCE_0))); -+ OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_DATA_REG, -+ (R300_PVS_SRC_REG_TYPE(R300_PVS_SRC_REG_INPUT) | -+ R300_PVS_SRC_OFFSET(6) | -+ R300_PVS_SRC_SWIZZLE_X(R300_PVS_SRC_SELECT_FORCE_0) | -+ R300_PVS_SRC_SWIZZLE_Y(R300_PVS_SRC_SELECT_FORCE_0) | -+ R300_PVS_SRC_SWIZZLE_Z(R300_PVS_SRC_SELECT_FORCE_0) | -+ R300_PVS_SRC_SWIZZLE_W(R300_PVS_SRC_SELECT_FORCE_0))); -+ FINISH_ACCEL(); -+ -+ /* Xv shader program */ -+ BEGIN_ACCEL(9); -+ OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_INDX_REG, 5); -+ -+ OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_DATA_REG, -+ (R300_PVS_DST_OPCODE(R300_VE_ADD) | -+ R300_PVS_DST_REG_TYPE(R300_PVS_DST_REG_OUT) | -+ R300_PVS_DST_OFFSET(0) | -+ R300_PVS_DST_WE_X | R300_PVS_DST_WE_Y | -+ R300_PVS_DST_WE_Z | R300_PVS_DST_WE_W)); -+ OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_DATA_REG, -+ (R300_PVS_SRC_REG_TYPE(R300_PVS_SRC_REG_INPUT) | -+ R300_PVS_SRC_OFFSET(0) | -+ R300_PVS_SRC_SWIZZLE_X(R300_PVS_SRC_SELECT_X) | -+ R300_PVS_SRC_SWIZZLE_Y(R300_PVS_SRC_SELECT_Y) | -+ R300_PVS_SRC_SWIZZLE_Z(R300_PVS_SRC_SELECT_Z) | -+ R300_PVS_SRC_SWIZZLE_W(R300_PVS_SRC_SELECT_W))); -+ OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_DATA_REG, -+ (R300_PVS_SRC_REG_TYPE(R300_PVS_SRC_REG_INPUT) | -+ R300_PVS_SRC_OFFSET(0) | -+ R300_PVS_SRC_SWIZZLE_X(R300_PVS_SRC_SELECT_FORCE_0) | -+ R300_PVS_SRC_SWIZZLE_Y(R300_PVS_SRC_SELECT_FORCE_0) | -+ R300_PVS_SRC_SWIZZLE_Z(R300_PVS_SRC_SELECT_FORCE_0) | -+ R300_PVS_SRC_SWIZZLE_W(R300_PVS_SRC_SELECT_FORCE_0))); -+ OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_DATA_REG, -+ (R300_PVS_SRC_REG_TYPE(R300_PVS_SRC_REG_INPUT) | -+ R300_PVS_SRC_OFFSET(0) | -+ R300_PVS_SRC_SWIZZLE_X(R300_PVS_SRC_SELECT_FORCE_0) | -+ R300_PVS_SRC_SWIZZLE_Y(R300_PVS_SRC_SELECT_FORCE_0) | -+ R300_PVS_SRC_SWIZZLE_Z(R300_PVS_SRC_SELECT_FORCE_0) | -+ R300_PVS_SRC_SWIZZLE_W(R300_PVS_SRC_SELECT_FORCE_0))); -+ -+ OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_DATA_REG, -+ (R300_PVS_DST_OPCODE(R300_VE_ADD) | -+ R300_PVS_DST_REG_TYPE(R300_PVS_DST_REG_OUT) | -+ R300_PVS_DST_OFFSET(1) | -+ R300_PVS_DST_WE_X | R300_PVS_DST_WE_Y | -+ R300_PVS_DST_WE_Z | R300_PVS_DST_WE_W)); -+ OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_DATA_REG, -+ (R300_PVS_SRC_REG_TYPE(R300_PVS_SRC_REG_INPUT) | -+ R300_PVS_SRC_OFFSET(6) | -+ R300_PVS_SRC_SWIZZLE_X(R300_PVS_SRC_SELECT_X) | -+ R300_PVS_SRC_SWIZZLE_Y(R300_PVS_SRC_SELECT_Y) | -+ R300_PVS_SRC_SWIZZLE_Z(R300_PVS_SRC_SELECT_Z) | -+ R300_PVS_SRC_SWIZZLE_W(R300_PVS_SRC_SELECT_W))); -+ OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_DATA_REG, -+ (R300_PVS_SRC_REG_TYPE(R300_PVS_SRC_REG_INPUT) | -+ R300_PVS_SRC_OFFSET(6) | -+ R300_PVS_SRC_SWIZZLE_X(R300_PVS_SRC_SELECT_FORCE_0) | -+ R300_PVS_SRC_SWIZZLE_Y(R300_PVS_SRC_SELECT_FORCE_0) | -+ R300_PVS_SRC_SWIZZLE_Z(R300_PVS_SRC_SELECT_FORCE_0) | -+ R300_PVS_SRC_SWIZZLE_W(R300_PVS_SRC_SELECT_FORCE_0))); -+ OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_DATA_REG, -+ (R300_PVS_SRC_REG_TYPE(R300_PVS_SRC_REG_INPUT) | -+ R300_PVS_SRC_OFFSET(6) | -+ R300_PVS_SRC_SWIZZLE_X(R300_PVS_SRC_SELECT_FORCE_0) | -+ R300_PVS_SRC_SWIZZLE_Y(R300_PVS_SRC_SELECT_FORCE_0) | -+ R300_PVS_SRC_SWIZZLE_Z(R300_PVS_SRC_SELECT_FORCE_0) | -+ R300_PVS_SRC_SWIZZLE_W(R300_PVS_SRC_SELECT_FORCE_0))); -+ FINISH_ACCEL(); -+ } -+ -+ /* pre-load the RS instructions */ -+ BEGIN_ACCEL(4); -+ if (IS_R300_3D) { -+ /* rasterizer source table -+ * R300_RS_TEX_PTR is the offset into the input RS stream -+ * 0,1 are tex0 -+ * 2,3 are tex1 -+ */ -+ OUT_ACCEL_REG(R300_RS_IP_0, -+ (R300_RS_TEX_PTR(0) | -+ R300_RS_SEL_S(R300_RS_SEL_C0) | -+ R300_RS_SEL_T(R300_RS_SEL_C1) | -+ R300_RS_SEL_R(R300_RS_SEL_K0) | -+ R300_RS_SEL_Q(R300_RS_SEL_K1))); -+ OUT_ACCEL_REG(R300_RS_IP_1, -+ (R300_RS_TEX_PTR(2) | -+ R300_RS_SEL_S(R300_RS_SEL_C0) | -+ R300_RS_SEL_T(R300_RS_SEL_C1) | -+ R300_RS_SEL_R(R300_RS_SEL_K0) | -+ R300_RS_SEL_Q(R300_RS_SEL_K1))); -+ /* src tex */ -+ /* R300_INST_TEX_ID - select the RS source table entry -+ * R300_INST_TEX_ADDR - the FS temp register for the texture data -+ */ -+ OUT_ACCEL_REG(R300_RS_INST_0, (R300_INST_TEX_ID(0) | -+ R300_RS_INST_TEX_CN_WRITE | -+ R300_INST_TEX_ADDR(0))); -+ /* mask tex */ -+ OUT_ACCEL_REG(R300_RS_INST_1, (R300_INST_TEX_ID(1) | -+ R300_RS_INST_TEX_CN_WRITE | -+ R300_INST_TEX_ADDR(1))); -+ -+ } else { -+ /* rasterizer source table -+ * R300_RS_TEX_PTR is the offset into the input RS stream -+ * 0,1 are tex0 -+ * 2,3 are tex1 -+ */ -+ OUT_ACCEL_REG(R500_RS_IP_0, ((0 << R500_RS_IP_TEX_PTR_S_SHIFT) | -+ (1 << R500_RS_IP_TEX_PTR_T_SHIFT) | -+ (R500_RS_IP_PTR_K0 << R500_RS_IP_TEX_PTR_R_SHIFT) | -+ (R500_RS_IP_PTR_K1 << R500_RS_IP_TEX_PTR_Q_SHIFT))); -+ -+ OUT_ACCEL_REG(R500_RS_IP_1, ((2 << R500_RS_IP_TEX_PTR_S_SHIFT) | -+ (3 << R500_RS_IP_TEX_PTR_T_SHIFT) | -+ (R500_RS_IP_PTR_K0 << R500_RS_IP_TEX_PTR_R_SHIFT) | -+ (R500_RS_IP_PTR_K1 << R500_RS_IP_TEX_PTR_Q_SHIFT))); -+ /* src tex */ -+ /* R500_RS_INST_TEX_ID_SHIFT - select the RS source table entry -+ * R500_RS_INST_TEX_ADDR_SHIFT - the FS temp register for the texture data -+ */ -+ OUT_ACCEL_REG(R500_RS_INST_0, ((0 << R500_RS_INST_TEX_ID_SHIFT) | -+ R500_RS_INST_TEX_CN_WRITE | -+ (0 << R500_RS_INST_TEX_ADDR_SHIFT))); -+ /* mask tex */ -+ OUT_ACCEL_REG(R500_RS_INST_1, ((1 << R500_RS_INST_TEX_ID_SHIFT) | -+ R500_RS_INST_TEX_CN_WRITE | -+ (1 << R500_RS_INST_TEX_ADDR_SHIFT))); -+ } -+ FINISH_ACCEL(); -+ -+ /* pre-load FS tex instructions */ -+ if (IS_R300_3D) { -+ BEGIN_ACCEL(2); -+ /* tex inst for src texture */ -+ OUT_ACCEL_REG(R300_US_TEX_INST_0, -+ (R300_TEX_SRC_ADDR(0) | -+ R300_TEX_DST_ADDR(0) | -+ R300_TEX_ID(0) | -+ R300_TEX_INST(R300_TEX_INST_LD))); -+ -+ /* tex inst for mask texture */ -+ OUT_ACCEL_REG(R300_US_TEX_INST_1, -+ (R300_TEX_SRC_ADDR(1) | -+ R300_TEX_DST_ADDR(1) | -+ R300_TEX_ID(1) | -+ R300_TEX_INST(R300_TEX_INST_LD))); -+ FINISH_ACCEL(); -+ } -+ -+ if (IS_R300_3D) { -+ BEGIN_ACCEL(9); -+ OUT_ACCEL_REG(R300_US_CONFIG, (0 << R300_NLEVEL_SHIFT) | R300_FIRST_TEX); -+ OUT_ACCEL_REG(R300_US_PIXSIZE, 1); /* highest temp used */ -+ OUT_ACCEL_REG(R300_US_CODE_ADDR_0, -+ (R300_ALU_START(0) | -+ R300_ALU_SIZE(0) | -+ R300_TEX_START(0) | -+ R300_TEX_SIZE(0))); -+ OUT_ACCEL_REG(R300_US_CODE_ADDR_1, -+ (R300_ALU_START(0) | -+ R300_ALU_SIZE(0) | -+ R300_TEX_START(0) | -+ R300_TEX_SIZE(0))); -+ OUT_ACCEL_REG(R300_US_CODE_ADDR_2, -+ (R300_ALU_START(0) | -+ R300_ALU_SIZE(0) | -+ R300_TEX_START(0) | -+ R300_TEX_SIZE(0))); -+ } else { -+ BEGIN_ACCEL(7); -+ OUT_ACCEL_REG(R300_US_CONFIG, R500_ZERO_TIMES_ANYTHING_EQUALS_ZERO); -+ OUT_ACCEL_REG(R300_US_PIXSIZE, 1); /* highest temp used */ -+ OUT_ACCEL_REG(R500_US_FC_CTRL, 0); -+ } - OUT_ACCEL_REG(R300_US_W_FMT, 0); - OUT_ACCEL_REG(R300_US_OUT_FMT_1, (R300_OUT_FMT_UNUSED | - R300_OUT_FMT_C0_SEL_BLUE | -@@ -165,11 +555,6 @@ static void FUNC_NAME(RADEONInit3DEngine)(ScrnInfoPtr pScrn) - R300_OUT_FMT_C1_SEL_GREEN | - R300_OUT_FMT_C2_SEL_RED | - R300_OUT_FMT_C3_SEL_ALPHA)); -- OUT_ACCEL_REG(R300_US_OUT_FMT_0, (R300_OUT_FMT_C4_10 | -- R300_OUT_FMT_C0_SEL_BLUE | -- R300_OUT_FMT_C1_SEL_GREEN | -- R300_OUT_FMT_C2_SEL_RED | -- R300_OUT_FMT_C3_SEL_ALPHA)); - FINISH_ACCEL(); - - -@@ -179,7 +564,8 @@ static void FUNC_NAME(RADEONInit3DEngine)(ScrnInfoPtr pScrn) - OUT_ACCEL_REG(R300_FG_ALPHA_FUNC, 0); - FINISH_ACCEL(); - -- BEGIN_ACCEL(12); -+ BEGIN_ACCEL(13); -+ OUT_ACCEL_REG(R300_RB3D_ABLENDCNTL, 0); - OUT_ACCEL_REG(R300_RB3D_ZSTENCILCNTL, 0); - OUT_ACCEL_REG(R300_RB3D_ZCACHE_CTLSTAT, R300_ZC_FLUSH | R300_ZC_FREE); - OUT_ACCEL_REG(R300_RB3D_BW_CNTL, 0); -@@ -205,12 +591,12 @@ static void FUNC_NAME(RADEONInit3DEngine)(ScrnInfoPtr pScrn) - OUT_ACCEL_REG(R300_SC_SCISSOR1, ((8191 << R300_SCISSOR_X_SHIFT) | - (8191 << R300_SCISSOR_Y_SHIFT))); - -- if (IS_R300_VARIANT || (info->ChipFamily == CHIP_FAMILY_RS690)) { -+ if (IS_R300_3D) { - /* clip has offset 1440 */ - OUT_ACCEL_REG(R300_SC_CLIP_0_A, ((1088 << R300_CLIP_X_SHIFT) | - (1088 << R300_CLIP_Y_SHIFT))); -- OUT_ACCEL_REG(R300_SC_CLIP_0_B, (((1080 + 2048) << R300_CLIP_X_SHIFT) | -- ((1080 + 2048) << R300_CLIP_Y_SHIFT))); -+ OUT_ACCEL_REG(R300_SC_CLIP_0_B, (((1080 + 2920) << R300_CLIP_X_SHIFT) | -+ ((1080 + 2920) << R300_CLIP_Y_SHIFT))); - } else { - OUT_ACCEL_REG(R300_SC_CLIP_0_A, ((0 << R300_CLIP_X_SHIFT) | - (0 << R300_CLIP_Y_SHIFT))); -@@ -239,6 +625,19 @@ static void FUNC_NAME(RADEONInit3DEngine)(ScrnInfoPtr pScrn) - OUT_ACCEL_REG(R200_SE_VAP_CNTL, R200_VAP_FORCE_W_TO_ONE | - R200_VAP_VF_MAX_VTX_NUM); - FINISH_ACCEL(); -+ -+ BEGIN_ACCEL(5); -+ OUT_ACCEL_REG(RADEON_RE_TOP_LEFT, 0); -+ OUT_ACCEL_REG(RADEON_RE_WIDTH_HEIGHT, 0x07ff07ff); -+ OUT_ACCEL_REG(RADEON_AUX_SC_CNTL, 0); -+ OUT_ACCEL_REG(RADEON_RB3D_PLANEMASK, 0xffffffff); -+ OUT_ACCEL_REG(RADEON_SE_CNTL, (RADEON_DIFFUSE_SHADE_GOURAUD | -+ RADEON_BFACE_SOLID | -+ RADEON_FFACE_SOLID | -+ RADEON_VTX_PIX_CENTER_OGL | -+ RADEON_ROUND_MODE_ROUND | -+ RADEON_ROUND_PREC_4TH_PIX)); -+ FINISH_ACCEL(); - } else { - BEGIN_ACCEL(2); - if ((info->ChipFamily == CHIP_FAMILY_RADEON) || -@@ -252,20 +651,21 @@ static void FUNC_NAME(RADEONInit3DEngine)(ScrnInfoPtr pScrn) - RADEON_VTX_ST1_NONPARAMETRIC | - RADEON_TEX1_W_ROUTING_USE_W0); - FINISH_ACCEL(); -+ -+ BEGIN_ACCEL(5); -+ OUT_ACCEL_REG(RADEON_RE_TOP_LEFT, 0); -+ OUT_ACCEL_REG(RADEON_RE_WIDTH_HEIGHT, 0x07ff07ff); -+ OUT_ACCEL_REG(RADEON_AUX_SC_CNTL, 0); -+ OUT_ACCEL_REG(RADEON_RB3D_PLANEMASK, 0xffffffff); -+ OUT_ACCEL_REG(RADEON_SE_CNTL, (RADEON_DIFFUSE_SHADE_GOURAUD | -+ RADEON_BFACE_SOLID | -+ RADEON_FFACE_SOLID | -+ RADEON_VTX_PIX_CENTER_OGL | -+ RADEON_ROUND_MODE_ROUND | -+ RADEON_ROUND_PREC_4TH_PIX)); -+ FINISH_ACCEL(); - } - -- BEGIN_ACCEL(5); -- OUT_ACCEL_REG(RADEON_RE_TOP_LEFT, 0); -- OUT_ACCEL_REG(RADEON_RE_WIDTH_HEIGHT, 0x07ff07ff); -- OUT_ACCEL_REG(RADEON_AUX_SC_CNTL, 0); -- OUT_ACCEL_REG(RADEON_RB3D_PLANEMASK, 0xffffffff); -- OUT_ACCEL_REG(RADEON_SE_CNTL, (RADEON_DIFFUSE_SHADE_GOURAUD | -- RADEON_BFACE_SOLID | -- RADEON_FFACE_SOLID | -- RADEON_VTX_PIX_CENTER_OGL | -- RADEON_ROUND_MODE_ROUND | -- RADEON_ROUND_PREC_4TH_PIX)); -- FINISH_ACCEL(); - } - - -diff --git a/src/radeon_crtc.c b/src/radeon_crtc.c -index 3524b75..1316669 100644 ---- a/src/radeon_crtc.c -+++ b/src/radeon_crtc.c -@@ -57,14 +57,17 @@ extern void atombios_crtc_mode_set(xf86CrtcPtr crtc, - DisplayModePtr mode, - DisplayModePtr adjusted_mode, - int x, int y); --extern void legacy_crtc_mode_set(xf86CrtcPtr crtc, -- DisplayModePtr mode, -- DisplayModePtr adjusted_mode, -- int x, int y); - extern void atombios_crtc_dpms(xf86CrtcPtr crtc, int mode); --extern void legacy_crtc_dpms(xf86CrtcPtr crtc, int mode); -+extern void -+RADEONInitDispBandwidthLegacy(ScrnInfoPtr pScrn, -+ DisplayModePtr mode1, int pixel_bytes1, -+ DisplayModePtr mode2, int pixel_bytes2); -+extern void -+RADEONInitDispBandwidthAVIVO(ScrnInfoPtr pScrn, -+ DisplayModePtr mode1, int pixel_bytes1, -+ DisplayModePtr mode2, int pixel_bytes2); - --static void -+void - radeon_crtc_dpms(xf86CrtcPtr crtc, int mode) - { - RADEONInfoPtr info = RADEONPTR(crtc->scrn); -@@ -72,6 +75,9 @@ radeon_crtc_dpms(xf86CrtcPtr crtc, int mode) - RADEONCrtcPrivatePtr radeon_crtc = crtc->driver_private; - xf86CrtcPtr crtc0 = pRADEONEnt->pCrtc[0]; - -+ if ((mode == DPMSModeOn) && radeon_crtc->enabled) -+ return; -+ - if (IS_AVIVO_VARIANT) { - atombios_crtc_dpms(crtc, mode); - } else { -@@ -91,6 +97,11 @@ radeon_crtc_dpms(xf86CrtcPtr crtc, int mode) - legacy_crtc_dpms(crtc0, mode); - } - } -+ -+ if (mode == DPMSModeOn) -+ radeon_crtc->enabled = TRUE; -+ else -+ radeon_crtc->enabled = FALSE; - } - - static Bool -@@ -103,10 +114,13 @@ radeon_crtc_mode_fixup(xf86CrtcPtr crtc, DisplayModePtr mode, - static void - radeon_crtc_mode_prepare(xf86CrtcPtr crtc) - { -- radeon_crtc_dpms(crtc, DPMSModeOff); -+ RADEONCrtcPrivatePtr radeon_crtc = crtc->driver_private; -+ -+ if (radeon_crtc->enabled) -+ crtc->funcs->hide_cursor(crtc); - } - --static CARD32 RADEONDiv(CARD64 n, CARD32 d) -+static uint32_t RADEONDiv(CARD64 n, uint32_t d) - { - return (n + (d / 2)) / d; - } -@@ -114,22 +128,22 @@ static CARD32 RADEONDiv(CARD64 n, CARD32 d) - void - RADEONComputePLL(RADEONPLLPtr pll, - unsigned long freq, -- CARD32 *chosen_dot_clock_freq, -- CARD32 *chosen_feedback_div, -- CARD32 *chosen_reference_div, -- CARD32 *chosen_post_div, -+ uint32_t *chosen_dot_clock_freq, -+ uint32_t *chosen_feedback_div, -+ uint32_t *chosen_reference_div, -+ uint32_t *chosen_post_div, - int flags) - { -- CARD32 min_ref_div = pll->min_ref_div; -- CARD32 max_ref_div = pll->max_ref_div; -- CARD32 best_vco = pll->best_vco; -- CARD32 best_post_div = 1; -- CARD32 best_ref_div = 1; -- CARD32 best_feedback_div = 1; -- CARD32 best_freq = 1; -- CARD32 best_error = 0xffffffff; -- CARD32 best_vco_diff = 1; -- CARD32 post_div; -+ uint32_t min_ref_div = pll->min_ref_div; -+ uint32_t max_ref_div = pll->max_ref_div; -+ uint32_t best_vco = pll->best_vco; -+ uint32_t best_post_div = 1; -+ uint32_t best_ref_div = 1; -+ uint32_t best_feedback_div = 1; -+ uint32_t best_freq = -1; -+ uint32_t best_error = 0xffffffff; -+ uint32_t best_vco_diff = 1; -+ uint32_t post_div; - - freq = freq * 1000; - -@@ -137,10 +151,20 @@ RADEONComputePLL(RADEONPLLPtr pll, - - if (flags & RADEON_PLL_USE_REF_DIV) - min_ref_div = max_ref_div = pll->reference_div; -+ else { -+ while (min_ref_div < max_ref_div-1) { -+ uint32_t mid=(min_ref_div+max_ref_div)/2; -+ uint32_t pll_in = pll->reference_freq / mid; -+ if (pll_in < pll->pll_in_min) -+ max_ref_div = mid; -+ else if (pll_in > pll->pll_in_max) -+ min_ref_div = mid; -+ else break; -+ } -+ } - - for (post_div = pll->min_post_div; post_div <= pll->max_post_div; ++post_div) { -- CARD32 ref_div; -- CARD32 vco = (freq / 10000) * post_div; -+ uint32_t ref_div; - - if ((flags & RADEON_PLL_NO_ODD_POST_DIV) && (post_div & 1)) - continue; -@@ -155,43 +179,71 @@ RADEONComputePLL(RADEONPLLPtr pll, - continue; - } - -- if (vco < pll->pll_out_min || vco > pll->pll_out_max) -- continue; -- - for (ref_div = min_ref_div; ref_div <= max_ref_div; ++ref_div) { -- CARD32 feedback_div, current_freq, error, vco_diff; -- CARD32 pll_in = pll->reference_freq / ref_div; -+ uint32_t feedback_div, current_freq, error, vco_diff; -+ uint32_t pll_in = pll->reference_freq / ref_div; -+ uint32_t min_feed_div = pll->min_feedback_div; -+ uint32_t max_feed_div = pll->max_feedback_div+1; - - if (pll_in < pll->pll_in_min || pll_in > pll->pll_in_max) - continue; - -- feedback_div = RADEONDiv((CARD64)freq * ref_div * post_div, -- pll->reference_freq * 10000); -+ while (min_feed_div < max_feed_div) { -+ uint32_t vco; - -- if (feedback_div < pll->min_feedback_div || feedback_div > pll->max_feedback_div) -- continue; -+ feedback_div = (min_feed_div+max_feed_div)/2; - -- current_freq = RADEONDiv((CARD64)pll->reference_freq * 10000 * feedback_div, -- ref_div * post_div); -- -- error = abs(current_freq - freq); -- vco_diff = abs(vco - best_vco); -- -- if ((best_vco == 0 && error < best_error) || -- (ref_div == pll->reference_div) || -- (best_vco != 0 && -- (error < best_error - 100 || -- (abs(error - best_error) < 100 && vco_diff < best_vco_diff )))) { -- best_post_div = post_div; -- best_ref_div = ref_div; -- best_feedback_div = feedback_div; -- best_freq = current_freq; -- best_error = error; -- best_vco_diff = vco_diff; -+ vco = RADEONDiv((CARD64)pll->reference_freq * feedback_div, -+ ref_div); -+ -+ if (vco < pll->pll_out_min) { -+ min_feed_div = feedback_div+1; -+ continue; -+ } else if(vco > pll->pll_out_max) { -+ max_feed_div = feedback_div; -+ continue; -+ } -+ -+ current_freq = RADEONDiv((CARD64)pll->reference_freq * 10000 * feedback_div, -+ ref_div * post_div); -+ -+ error = abs(current_freq - freq); -+ vco_diff = abs(vco - best_vco); -+ -+ if ((best_vco == 0 && error < best_error) || -+ (best_vco != 0 && -+ (error < best_error - 100 || -+ (abs(error - best_error) < 100 && vco_diff < best_vco_diff )))) { -+ best_post_div = post_div; -+ best_ref_div = ref_div; -+ best_feedback_div = feedback_div; -+ best_freq = current_freq; -+ best_error = error; -+ best_vco_diff = vco_diff; -+ } else if (current_freq == freq) { -+ if (best_freq == -1) { -+ best_post_div = post_div; -+ best_ref_div = ref_div; -+ best_feedback_div = feedback_div; -+ best_freq = current_freq; -+ best_error = error; -+ best_vco_diff = vco_diff; -+ } else if ((flags & RADEON_PLL_PREFER_LOW_REF_DIV) && (ref_div < best_ref_div)) { -+ best_post_div = post_div; -+ best_ref_div = ref_div; -+ best_feedback_div = feedback_div; -+ best_freq = current_freq; -+ best_error = error; -+ best_vco_diff = vco_diff; -+ } -+ } -+ -+ if (current_freq < freq) -+ min_feed_div = feedback_div+1; -+ else -+ max_feed_div = feedback_div; - } - } -- if (best_freq == freq) -- break; - } - - ErrorF("best_freq: %u\n", (unsigned int)best_freq); -@@ -199,6 +251,8 @@ RADEONComputePLL(RADEONPLLPtr pll, - ErrorF("best_ref_div: %u\n", (unsigned int)best_ref_div); - ErrorF("best_post_div: %u\n", (unsigned int)best_post_div); - -+ if (best_freq == -1) -+ FatalError("Couldn't find valid PLL dividers\n"); - *chosen_dot_clock_freq = best_freq / 10000; - *chosen_feedback_div = best_feedback_div; - *chosen_reference_div = best_ref_div; -@@ -223,21 +277,8 @@ radeon_crtc_mode_set(xf86CrtcPtr crtc, DisplayModePtr mode, - static void - radeon_crtc_mode_commit(xf86CrtcPtr crtc) - { -- RADEONInfoPtr info = RADEONPTR(crtc->scrn); -- RADEONEntPtr pRADEONEnt = RADEONEntPriv(crtc->scrn); -- RADEONCrtcPrivatePtr radeon_crtc = crtc->driver_private; -- -- if (info->ChipFamily >= CHIP_FAMILY_R600) { -- xf86CrtcPtr other; -- if (radeon_crtc->crtc_id == 1) -- other = pRADEONEnt->pCrtc[0]; -- else -- other = pRADEONEnt->pCrtc[1]; -- if (other->enabled) -- radeon_crtc_dpms(other, DPMSModeOn); -- } -- -- radeon_crtc_dpms(crtc, DPMSModeOn); -+ if (crtc->scrn->pScreen != NULL) -+ xf86_reload_cursors(crtc->scrn->pScreen); - } - - void -@@ -275,12 +316,16 @@ radeon_crtc_load_lut(xf86CrtcPtr crtc) - OUTPAL(i, radeon_crtc->lut_r[i], radeon_crtc->lut_g[i], radeon_crtc->lut_b[i]); - } - -+ if (IS_AVIVO_VARIANT) { -+ OUTREG(AVIVO_D1GRPH_LUT_SEL + radeon_crtc->crtc_offset, radeon_crtc->crtc_id); -+ } -+ - } - - - static void --radeon_crtc_gamma_set(xf86CrtcPtr crtc, CARD16 *red, CARD16 *green, -- CARD16 *blue, int size) -+radeon_crtc_gamma_set(xf86CrtcPtr crtc, uint16_t *red, uint16_t *green, -+ uint16_t *blue, int size) - { - RADEONCrtcPrivatePtr radeon_crtc = crtc->driver_private; - ScrnInfoPtr pScrn = crtc->scrn; -@@ -530,14 +575,52 @@ static const xf86CrtcFuncsRec radeon_crtc_funcs = { - .destroy = NULL, /* XXX */ - }; - -+void -+RADEONInitDispBandwidth(ScrnInfoPtr pScrn) -+{ -+ RADEONInfoPtr info = RADEONPTR(pScrn); -+ xf86CrtcConfigPtr xf86_config = XF86_CRTC_CONFIG_PTR(pScrn); -+ DisplayModePtr mode1 = NULL, mode2 = NULL; -+ int pixel_bytes1 = info->CurrentLayout.pixel_bytes; -+ int pixel_bytes2 = info->CurrentLayout.pixel_bytes; -+ -+ if (xf86_config->num_crtc == 2) { -+ if (xf86_config->crtc[1]->enabled && -+ xf86_config->crtc[0]->enabled) { -+ mode1 = &xf86_config->crtc[0]->mode; -+ mode2 = &xf86_config->crtc[1]->mode; -+ } else if (xf86_config->crtc[0]->enabled) { -+ mode1 = &xf86_config->crtc[0]->mode; -+ } else if (xf86_config->crtc[1]->enabled) { -+ mode2 = &xf86_config->crtc[1]->mode; -+ } else -+ return; -+ } else { -+ if (info->IsPrimary) -+ mode1 = &xf86_config->crtc[0]->mode; -+ else if (info->IsSecondary) -+ mode2 = &xf86_config->crtc[0]->mode; -+ else if (xf86_config->crtc[0]->enabled) -+ mode1 = &xf86_config->crtc[0]->mode; -+ else -+ return; -+ } -+ -+ if (IS_AVIVO_VARIANT) -+ RADEONInitDispBandwidthAVIVO(pScrn, mode1, pixel_bytes1, mode2, pixel_bytes2); -+ else -+ RADEONInitDispBandwidthLegacy(pScrn, mode1, pixel_bytes1, mode2, pixel_bytes2); -+} -+ - Bool RADEONAllocateControllers(ScrnInfoPtr pScrn, int mask) - { - RADEONEntPtr pRADEONEnt = RADEONEntPriv(pScrn); -+ RADEONInfoPtr info = RADEONPTR(pScrn); - - if (mask & 1) { - if (pRADEONEnt->Controller[0]) - return TRUE; -- -+ - pRADEONEnt->pCrtc[0] = xf86CrtcCreate(pScrn, &radeon_crtc_funcs); - if (!pRADEONEnt->pCrtc[0]) - return FALSE; -@@ -549,16 +632,20 @@ Bool RADEONAllocateControllers(ScrnInfoPtr pScrn, int mask) - pRADEONEnt->pCrtc[0]->driver_private = pRADEONEnt->Controller[0]; - pRADEONEnt->Controller[0]->crtc_id = 0; - pRADEONEnt->Controller[0]->crtc_offset = 0; -+ if (info->allowColorTiling) -+ pRADEONEnt->Controller[0]->can_tile = 1; -+ else -+ pRADEONEnt->Controller[0]->can_tile = 0; - } - - if (mask & 2) { - if (!pRADEONEnt->HasCRTC2) - return TRUE; -- -+ - pRADEONEnt->pCrtc[1] = xf86CrtcCreate(pScrn, &radeon_crtc_funcs); - if (!pRADEONEnt->pCrtc[1]) - return FALSE; -- -+ - pRADEONEnt->Controller[1] = xnfcalloc(sizeof(RADEONCrtcPrivateRec), 1); - if (!pRADEONEnt->Controller[1]) - { -@@ -569,6 +656,10 @@ Bool RADEONAllocateControllers(ScrnInfoPtr pScrn, int mask) - pRADEONEnt->pCrtc[1]->driver_private = pRADEONEnt->Controller[1]; - pRADEONEnt->Controller[1]->crtc_id = 1; - pRADEONEnt->Controller[1]->crtc_offset = AVIVO_D2CRTC_H_TOTAL - AVIVO_D1CRTC_H_TOTAL; -+ if (info->allowColorTiling) -+ pRADEONEnt->Controller[1]->can_tile = 1; -+ else -+ pRADEONEnt->Controller[1]->can_tile = 0; - } - - return TRUE; -@@ -719,3 +810,41 @@ RADEONUnblank(ScrnInfoPtr pScrn) - } - } - -+Bool -+RADEONSetTiling(ScrnInfoPtr pScrn) -+{ -+ xf86CrtcConfigPtr xf86_config = XF86_CRTC_CONFIG_PTR(pScrn); -+ RADEONInfoPtr info = RADEONPTR(pScrn); -+ RADEONCrtcPrivatePtr radeon_crtc; -+ xf86CrtcPtr crtc; -+ int c; -+ int can_tile = 1; -+ Bool changed = FALSE; -+ -+ for (c = 0; c < xf86_config->num_crtc; c++) { -+ crtc = xf86_config->crtc[c]; -+ radeon_crtc = crtc->driver_private; -+ -+ if (crtc->enabled) { -+ if (!radeon_crtc->can_tile) -+ can_tile = 0; -+ } -+ } -+ -+ if (info->tilingEnabled != can_tile) -+ changed = TRUE; -+ -+#ifdef XF86DRI -+ if (info->directRenderingEnabled && (info->tilingEnabled != can_tile)) { -+ RADEONSAREAPrivPtr pSAREAPriv; -+ if (RADEONDRISetParam(pScrn, RADEON_SETPARAM_SWITCH_TILING, (can_tile ? 1 : 0)) < 0) -+ xf86DrvMsg(pScrn->scrnIndex, X_ERROR, -+ "[drm] failed changing tiling status\n"); -+ /* if this is called during ScreenInit() we don't have pScrn->pScreen yet */ -+ pSAREAPriv = DRIGetSAREAPrivate(screenInfo.screens[pScrn->scrnIndex]); -+ info->tilingEnabled = pSAREAPriv->tiling_enabled ? TRUE : FALSE; -+ } -+#endif -+ -+ return changed; -+} -diff --git a/src/radeon_cursor.c b/src/radeon_cursor.c -index 0f7e668..13c2b9c 100644 ---- a/src/radeon_cursor.c -+++ b/src/radeon_cursor.c -@@ -92,6 +92,7 @@ - static void - avivo_setup_cursor(xf86CrtcPtr crtc, Bool enable) - { -+ ScrnInfoPtr pScrn = crtc->scrn; - RADEONCrtcPrivatePtr radeon_crtc = crtc->driver_private; - RADEONInfoPtr info = RADEONPTR(crtc->scrn); - unsigned char *RADEONMMIO = info->MMIO; -@@ -100,7 +101,7 @@ avivo_setup_cursor(xf86CrtcPtr crtc, Bool enable) - - if (enable) { - OUTREG(AVIVO_D1CUR_SURFACE_ADDRESS + radeon_crtc->crtc_offset, -- info->fbLocation + radeon_crtc->cursor_offset); -+ info->fbLocation + radeon_crtc->cursor_offset + pScrn->fbOffset); - OUTREG(AVIVO_D1CUR_SIZE + radeon_crtc->crtc_offset, - ((CURSOR_WIDTH - 1) << 16) | (CURSOR_HEIGHT - 1)); - OUTREG(AVIVO_D1CUR_CONTROL + radeon_crtc->crtc_offset, -@@ -108,6 +109,24 @@ avivo_setup_cursor(xf86CrtcPtr crtc, Bool enable) - } - } - -+static void -+avivo_lock_cursor(xf86CrtcPtr crtc, Bool lock) -+{ -+ RADEONCrtcPrivatePtr radeon_crtc = crtc->driver_private; -+ RADEONInfoPtr info = RADEONPTR(crtc->scrn); -+ unsigned char *RADEONMMIO = info->MMIO; -+ uint32_t tmp; -+ -+ tmp = INREG(AVIVO_D1CUR_UPDATE + radeon_crtc->crtc_offset); -+ -+ if (lock) -+ tmp |= AVIVO_D1CURSOR_UPDATE_LOCK; -+ else -+ tmp &= ~AVIVO_D1CURSOR_UPDATE_LOCK; -+ -+ OUTREG(AVIVO_D1CUR_UPDATE + radeon_crtc->crtc_offset, tmp); -+} -+ - void - radeon_crtc_show_cursor (xf86CrtcPtr crtc) - { -@@ -118,10 +137,12 @@ radeon_crtc_show_cursor (xf86CrtcPtr crtc) - unsigned char *RADEONMMIO = info->MMIO; - - if (IS_AVIVO_VARIANT) { -+ avivo_lock_cursor(crtc, TRUE); - OUTREG(AVIVO_D1CUR_CONTROL + radeon_crtc->crtc_offset, - INREG(AVIVO_D1CUR_CONTROL + radeon_crtc->crtc_offset) - | AVIVO_D1CURSOR_EN); - avivo_setup_cursor(crtc, TRUE); -+ avivo_lock_cursor(crtc, FALSE); - } else { - switch (crtc_id) { - case 0: -@@ -149,10 +170,12 @@ radeon_crtc_hide_cursor (xf86CrtcPtr crtc) - unsigned char *RADEONMMIO = info->MMIO; - - if (IS_AVIVO_VARIANT) { -+ avivo_lock_cursor(crtc, TRUE); - OUTREG(AVIVO_D1CUR_CONTROL+ radeon_crtc->crtc_offset, - INREG(AVIVO_D1CUR_CONTROL + radeon_crtc->crtc_offset) - & ~(AVIVO_D1CURSOR_EN)); - avivo_setup_cursor(crtc, FALSE); -+ avivo_lock_cursor(crtc, FALSE); - } else { - switch(crtc_id) { - case 0: -@@ -186,19 +209,23 @@ radeon_crtc_set_cursor_position (xf86CrtcPtr crtc, int x, int y) - if (xorigin >= CURSOR_WIDTH) xorigin = CURSOR_WIDTH - 1; - if (yorigin >= CURSOR_HEIGHT) yorigin = CURSOR_HEIGHT - 1; - -- if (mode->Flags & V_INTERLACE) -- y /= 2; -- else if (mode->Flags & V_DBLSCAN) -- y *= 2; -- - if (IS_AVIVO_VARIANT) { - /* avivo cursor spans the full fb width */ -- x += crtc->x; -- y += crtc->y; -+ if (crtc->rotatedData == NULL) { -+ x += crtc->x; -+ y += crtc->y; -+ } -+ avivo_lock_cursor(crtc, TRUE); - OUTREG(AVIVO_D1CUR_POSITION + radeon_crtc->crtc_offset, ((xorigin ? 0 : x) << 16) - | (yorigin ? 0 : y)); - OUTREG(AVIVO_D1CUR_HOT_SPOT + radeon_crtc->crtc_offset, (xorigin << 16) | yorigin); -+ avivo_lock_cursor(crtc, FALSE); - } else { -+ if (mode->Flags & V_INTERLACE) -+ y /= 2; -+ else if (mode->Flags & V_DBLSCAN) -+ y *= 2; -+ - if (crtc_id == 0) { - OUTREG(RADEON_CUR_HORZ_VERT_OFF, (RADEON_CUR_LOCK - | (xorigin << 16) -@@ -230,8 +257,8 @@ radeon_crtc_set_cursor_colors (xf86CrtcPtr crtc, int bg, int fg) - { - ScrnInfoPtr pScrn = crtc->scrn; - RADEONCrtcPrivatePtr radeon_crtc = crtc->driver_private; -- RADEONInfoPtr info = RADEONPTR(pScrn); -- CARD32 *pixels = (CARD32 *)(pointer)(info->FB + radeon_crtc->cursor_offset + pScrn->fbOffset); -+ RADEONInfoPtr info = RADEONPTR(pScrn); -+ uint32_t *pixels = (uint32_t *)(pointer)(info->FB + radeon_crtc->cursor_offset); - int pixel, i; - CURSOR_SWAPPING_DECL_MMIO - -@@ -272,9 +299,9 @@ radeon_crtc_load_cursor_argb (xf86CrtcPtr crtc, CARD32 *image) - { - ScrnInfoPtr pScrn = crtc->scrn; - RADEONCrtcPrivatePtr radeon_crtc = crtc->driver_private; -- RADEONInfoPtr info = RADEONPTR(pScrn); -+ RADEONInfoPtr info = RADEONPTR(pScrn); - CURSOR_SWAPPING_DECL_MMIO -- CARD32 *d = (CARD32 *)(pointer)(info->FB + radeon_crtc->cursor_offset + pScrn->fbOffset); -+ uint32_t *d = (uint32_t *)(pointer)(info->FB + radeon_crtc->cursor_offset); - - RADEONCTRACE(("RADEONLoadCursorARGB\n")); - -@@ -300,13 +327,13 @@ Bool RADEONCursorInit(ScreenPtr pScreen) - int width_bytes; - int height; - int size_bytes; -- CARD32 cursor_offset = 0; -+ uint32_t cursor_offset = 0; - int c; - -- size_bytes = CURSOR_WIDTH * 4 * CURSOR_HEIGHT; -- width = pScrn->displayWidth; -- width_bytes = width * (pScrn->bitsPerPixel / 8); -- height = ((size_bytes * xf86_config->num_crtc) + width_bytes - 1) / width_bytes; -+ size_bytes = CURSOR_WIDTH * 4 * CURSOR_HEIGHT; -+ width = pScrn->displayWidth; -+ width_bytes = width * (pScrn->bitsPerPixel / 8); -+ height = ((size_bytes * xf86_config->num_crtc) + width_bytes - 1) / width_bytes; - - #ifdef USE_XAA - if (!info->useEXA) { -@@ -346,14 +373,6 @@ Bool RADEONCursorInit(ScreenPtr pScreen) - - return xf86_cursors_init (pScreen, CURSOR_WIDTH, CURSOR_HEIGHT, - (HARDWARE_CURSOR_TRUECOLOR_AT_8BPP | --#if X_BYTE_ORDER == X_BIG_ENDIAN -- /* this is a lie -- -- * HARDWARE_CURSOR_BIT_ORDER_MSBFIRST -- * actually inverts the bit order, so -- * this switches to LSBFIRST -- */ -- HARDWARE_CURSOR_BIT_ORDER_MSBFIRST | --#endif - HARDWARE_CURSOR_AND_SOURCE_WITH_MASK | - HARDWARE_CURSOR_SOURCE_MASK_INTERLEAVE_1 | - HARDWARE_CURSOR_ARGB)); -diff --git a/src/radeon_dga.c b/src/radeon_dga.c -index ab5d278..d623fe4 100644 ---- a/src/radeon_dga.c -+++ b/src/radeon_dga.c -@@ -374,7 +374,7 @@ static void RADEON_FillRect(ScrnInfoPtr pScrn, - /* XXX */ - if (info->useEXA) { - /* -- info->exa.accel.PrepareSolid(pScrn, color, GXcopy, (CARD32)(~0)); -+ info->exa.accel.PrepareSolid(pScrn, color, GXcopy, (uint32_t)(~0)); - info->exa.accel.Solid(pScrn, x, y, x+w, y+h); - info->exa.accel.DoneSolid(); - */ -@@ -383,7 +383,7 @@ static void RADEON_FillRect(ScrnInfoPtr pScrn, - #endif /* USE_EXA */ - #ifdef USE_XAA - if (!info->useEXA) { -- (*info->accel->SetupForSolidFill)(pScrn, color, GXcopy, (CARD32)(~0)); -+ (*info->accel->SetupForSolidFill)(pScrn, color, GXcopy, (uint32_t)(~0)); - (*info->accel->SubsequentSolidFillRect)(pScrn, x, y, w, h); - if (pScrn->bitsPerPixel == info->CurrentLayout.bitsPerPixel) - RADEON_MARK_SYNC(info, pScrn); -@@ -404,7 +404,7 @@ static void RADEON_BlitRect(ScrnInfoPtr pScrn, - /* XXX */ - if (info->useEXA) { - /* -- info->exa.accel.PrepareCopy(pScrn, color, GXcopy, (CARD32)(~0)); -+ info->exa.accel.PrepareCopy(pScrn, color, GXcopy, (uint32_t)(~0)); - info->exa.accel.Copy(pScrn, srcx, srcy, dstx, dsty, w, h); - info->exa.accel.DoneCopy(); - */ -@@ -414,7 +414,7 @@ static void RADEON_BlitRect(ScrnInfoPtr pScrn, - #ifdef USE_XAA - if (!info->useEXA) { - (*info->accel->SetupForScreenToScreenCopy)(pScrn, xdir, ydir, -- GXcopy, (CARD32)(~0), -1); -+ GXcopy, (uint32_t)(~0), -1); - (*info->accel->SubsequentScreenToScreenCopy)(pScrn, srcx, srcy, - dstx, dsty, w, h); - if (pScrn->bitsPerPixel == info->CurrentLayout.bitsPerPixel) -@@ -433,7 +433,7 @@ static void RADEON_BlitTransRect(ScrnInfoPtr pScrn, - - info->XAAForceTransBlit = TRUE; - (*info->accel->SetupForScreenToScreenCopy)(pScrn, xdir, ydir, -- GXcopy, (CARD32)(~0), color); -+ GXcopy, (uint32_t)(~0), color); - - info->XAAForceTransBlit = FALSE; - -diff --git a/src/radeon_dri.c b/src/radeon_dri.c -index ac8d03c..a192811 100644 ---- a/src/radeon_dri.c -+++ b/src/radeon_dri.c -@@ -451,17 +451,17 @@ static void RADEONDRISwapContext(ScreenPtr pScreen, DRISyncType syncType, - - /* 16-bit depth buffer functions */ - #define WRITE_DEPTH16(_x, _y, d) \ -- *(CARD16 *)(pointer)(buf + 2*(_x + _y*info->frontPitch)) = (d) -+ *(uint16_t *)(pointer)(buf + 2*(_x + _y*info->frontPitch)) = (d) - - #define READ_DEPTH16(d, _x, _y) \ -- (d) = *(CARD16 *)(pointer)(buf + 2*(_x + _y*info->frontPitch)) -+ (d) = *(uint16_t *)(pointer)(buf + 2*(_x + _y*info->frontPitch)) - - /* 32-bit depth buffer (stencil and depth simultaneously) functions */ - #define WRITE_DEPTHSTENCIL32(_x, _y, d) \ -- *(CARD32 *)(pointer)(buf + 4*(_x + _y*info->frontPitch)) = (d) -+ *(uint32_t *)(pointer)(buf + 4*(_x + _y*info->frontPitch)) = (d) - - #define READ_DEPTHSTENCIL32(d, _x, _y) \ -- (d) = *(CARD32 *)(pointer)(buf + 4*(_x + _y*info->frontPitch)) -+ (d) = *(uint32_t *)(pointer)(buf + 4*(_x + _y*info->frontPitch)) - - /* Screen to screen copy of data in the depth buffer */ - static void RADEONScreenToScreenCopyDepth(ScrnInfoPtr pScrn, -@@ -646,7 +646,7 @@ static void RADEONDRIMoveBuffers(WindowPtr pParent, DDXPointRec ptOldOrg, - info->dst_pitch_offset |= RADEON_DST_TILE_MACRO; - - (*info->accel->SetupForScreenToScreenCopy)(pScrn, xdir, ydir, GXcopy, -- (CARD32)(-1), -1); -+ (uint32_t)(-1), -1); - - for (; nbox-- ; pbox++) { - int xa = pbox->x1; -@@ -724,7 +724,7 @@ static Bool RADEONSetAgpMode(RADEONInfoPtr info, ScreenPtr pScreen) - unsigned int device = drmAgpDeviceId(info->drmFD); - /* ignore agp 3.0 mode bit from the chip as it's buggy on some cards with - pcie-agp rialto bridge chip - use the one from bridge which must match */ -- CARD32 agp_status = (INREG(RADEON_AGP_STATUS) | RADEON_AGPv3_MODE) & mode; -+ uint32_t agp_status = (INREG(RADEON_AGP_STATUS) | RADEON_AGPv3_MODE) & mode; - Bool is_v3 = (agp_status & RADEON_AGPv3_MODE); - unsigned int defaultMode; - MessageType from; -@@ -820,11 +820,24 @@ static Bool RADEONSetAgpMode(RADEONInfoPtr info, ScreenPtr pScreen) - } - - /* Initialize Radeon's AGP registers */ --static void RADEONSetAgpBase(RADEONInfoPtr info) -+static void RADEONSetAgpBase(RADEONInfoPtr info, ScreenPtr pScreen) - { -+ ScrnInfoPtr pScrn = xf86Screens[pScreen->myNum]; - unsigned char *RADEONMMIO = info->MMIO; - -- OUTREG(RADEON_AGP_BASE, drmAgpBase(info->drmFD)); -+ /* drm already does this, so we can probably remove this. -+ * agp_base_2 ? -+ */ -+ if (info->ChipFamily == CHIP_FAMILY_RV515) -+ OUTMC(pScrn, RV515_MC_AGP_BASE, drmAgpBase(info->drmFD)); -+ else if ((info->ChipFamily >= CHIP_FAMILY_R520) && -+ (info->ChipFamily <= CHIP_FAMILY_RV570)) -+ OUTMC(pScrn, R520_MC_AGP_BASE, drmAgpBase(info->drmFD)); -+ else if ((info->ChipFamily == CHIP_FAMILY_RS690) || -+ (info->ChipFamily == CHIP_FAMILY_RS740)) -+ OUTMC(pScrn, RS690_MC_AGP_BASE, drmAgpBase(info->drmFD)); -+ else if (info->ChipFamily < CHIP_FAMILY_RV515) -+ OUTREG(RADEON_AGP_BASE, drmAgpBase(info->drmFD)); - } - - /* Initialize the AGP state. Request memory for use in AGP space, and -@@ -940,7 +953,7 @@ static Bool RADEONDRIAgpInit(RADEONInfoPtr info, ScreenPtr pScreen) - "[agp] GART Texture map mapped at 0x%08lx\n", - (unsigned long)info->gartTex); - -- RADEONSetAgpBase(info); -+ RADEONSetAgpBase(info, pScreen); - - return TRUE; - } -@@ -1090,7 +1103,7 @@ static int RADEONDRIKernelInit(RADEONInfoPtr info, ScreenPtr pScreen) - - drmInfo.sarea_priv_offset = sizeof(XF86DRISAREARec); - drmInfo.is_pci = (info->cardType!=CARD_AGP); -- drmInfo.cp_mode = info->CPMode; -+ drmInfo.cp_mode = RADEON_CSQ_PRIBM_INDBM; - drmInfo.gart_size = info->gartSize*1024*1024; - drmInfo.ring_size = info->ringSize*1024*1024; - drmInfo.usec_timeout = info->CPusecTimeout; -@@ -1198,6 +1211,12 @@ static void RADEONDRIIrqInit(RADEONInfoPtr info, ScreenPtr pScreen) - } else { - unsigned char *RADEONMMIO = info->MMIO; - info->ModeReg->gen_int_cntl = INREG( RADEON_GEN_INT_CNTL ); -+ -+ /* Let the DRM know it can safely disable the vblank interrupts */ -+ radeon_crtc_modeset_ioctl(XF86_CRTC_CONFIG_PTR(pScrn)->crtc[0], -+ FALSE); -+ radeon_crtc_modeset_ioctl(XF86_CRTC_CONFIG_PTR(pScrn)->crtc[0], -+ TRUE); - } - } - -@@ -1440,10 +1459,9 @@ Bool RADEONDRIScreenInit(ScreenPtr pScreen) - PCI_DEV_DEV(info->PciInfo), - PCI_DEV_FUNC(info->PciInfo)); - } -- pDRIInfo->ddxDriverMajorVersion = info->allowColorTiling ? -- RADEON_VERSION_MAJOR_TILED : RADEON_VERSION_MAJOR; -- pDRIInfo->ddxDriverMinorVersion = RADEON_VERSION_MINOR; -- pDRIInfo->ddxDriverPatchVersion = RADEON_VERSION_PATCH; -+ pDRIInfo->ddxDriverMajorVersion = info->allowColorTiling ? 5 : 4; -+ pDRIInfo->ddxDriverMinorVersion = 3; -+ pDRIInfo->ddxDriverPatchVersion = 0; - pDRIInfo->frameBufferPhysicalAddress = (void *)info->LinearAddr + info->frontOffset; - pDRIInfo->frameBufferSize = info->FbMapSize - info->FbSecureSize; - pDRIInfo->frameBufferStride = (pScrn->displayWidth * -@@ -1722,7 +1740,7 @@ void RADEONDRIResume(ScreenPtr pScreen) - if (!RADEONSetAgpMode(info, pScreen)) - return; - -- RADEONSetAgpBase(info); -+ RADEONSetAgpBase(info, pScreen); - } - - _ret = drmCommandNone(info->drmFD, DRM_RADEON_CP_RESUME); -@@ -1903,7 +1921,7 @@ static void RADEONDRIRefreshArea(ScrnInfoPtr pScrn, RegionPtr pReg) - - #ifdef USE_EXA - if (info->useEXA) { -- CARD32 src_pitch_offset, dst_pitch_offset, datatype; -+ uint32_t src_pitch_offset, dst_pitch_offset, datatype; - - RADEONGetPixmapOffsetPitch(pPix, &src_pitch_offset); - dst_pitch_offset = src_pitch_offset + (info->backOffset >> 10); -@@ -1924,7 +1942,7 @@ static void RADEONDRIRefreshArea(ScrnInfoPtr pScrn, RegionPtr pReg) - info->dst_pitch_offset |= RADEON_DST_TILE_MACRO; - (*info->accel->SetupForScreenToScreenCopy)(pScrn, - 1, 1, GXcopy, -- (CARD32)(-1), -1); -+ (uint32_t)(-1), -1); - } - #endif - -diff --git a/src/radeon_dri.h b/src/radeon_dri.h -index 3b54626..6e3ad62 100644 ---- a/src/radeon_dri.h -+++ b/src/radeon_dri.h -@@ -39,23 +39,18 @@ - #include "xf86drm.h" - - /* DRI Driver defaults */ --#define RADEON_DEFAULT_CP_PIO_MODE RADEON_CSQ_PRIPIO_INDPIO --#define RADEON_DEFAULT_CP_BM_MODE RADEON_CSQ_PRIBM_INDBM - #define RADEON_DEFAULT_GART_SIZE 8 /* MB (must be 2^n and > 4MB) */ -+#define R300_DEFAULT_GART_SIZE 32 /* MB (for R300 and above) */ - #define RADEON_DEFAULT_RING_SIZE 1 /* MB (must be page aligned) */ - #define RADEON_DEFAULT_BUFFER_SIZE 2 /* MB (must be page aligned) */ - #define RADEON_DEFAULT_GART_TEX_SIZE 1 /* MB (must be page aligned) */ - --#define RADEON_DEFAULT_CP_TIMEOUT 10000 /* usecs */ -+#define RADEON_DEFAULT_CP_TIMEOUT 100000 /* usecs */ - - #define RADEON_DEFAULT_PCI_APER_SIZE 32 /* in MB */ - - #define RADEON_CARD_TYPE_RADEON 1 - --#define RADEONCP_USE_RING_BUFFER(m) \ -- (((m) == RADEON_CSQ_PRIBM_INDDIS) || \ -- ((m) == RADEON_CSQ_PRIBM_INDBM)) -- - typedef struct { - /* DRI screen private data */ - int deviceID; /* PCI device ID */ -diff --git a/src/radeon_driver.c b/src/radeon_driver.c -index 5cf8d51..010f1b9 100644 ---- a/src/radeon_driver.c -+++ b/src/radeon_driver.c -@@ -126,35 +126,6 @@ static void RADEONSaveMemMapRegisters(ScrnInfoPtr pScrn, RADEONSavePtr save); - static void RADEONAdjustMemMapRegisters(ScrnInfoPtr pScrn, RADEONSavePtr save); - #endif - --extern DisplayModePtr --RADEONCrtcFindClosestMode(xf86CrtcPtr crtc, DisplayModePtr pMode); -- --extern void --RADEONSaveCommonRegisters(ScrnInfoPtr pScrn, RADEONSavePtr save); --extern void --RADEONSaveCrtcRegisters(ScrnInfoPtr pScrn, RADEONSavePtr save); --extern void --RADEONSaveCrtc2Registers(ScrnInfoPtr pScrn, RADEONSavePtr save); --extern void --RADEONSavePLLRegisters(ScrnInfoPtr pScrn, RADEONSavePtr save); --extern void --RADEONSavePLL2Registers(ScrnInfoPtr pScrn, RADEONSavePtr save); --extern void --RADEONSaveFPRegisters(ScrnInfoPtr pScrn, RADEONSavePtr save); --extern void --RADEONSaveDACRegisters(ScrnInfoPtr pScrn, RADEONSavePtr save); --extern void --RADEONSaveTVRegisters(ScrnInfoPtr pScrn, RADEONSavePtr save); -- --#ifdef USE_XAA --#ifdef XF86DRI --extern Bool --RADEONSetupMemXAA_DRI(int scrnIndex, ScreenPtr pScreen); --#endif /* XF86DRI */ --extern Bool --RADEONSetupMemXAA(int scrnIndex, ScreenPtr pScreen); --#endif /* USE_XAA */ -- - static const OptionInfoRec RADEONOptions[] = { - { OPTION_NOACCEL, "NoAccel", OPTV_BOOLEAN, {0}, FALSE }, - { OPTION_SW_CURSOR, "SWcursor", OPTV_BOOLEAN, {0}, FALSE }, -@@ -219,24 +190,24 @@ static const OptionInfoRec RADEONOptions[] = { - { OPTION_FORCE_TVOUT, "ForceTVOut", OPTV_BOOLEAN, {0}, FALSE }, - { OPTION_TVSTD, "TVStandard", OPTV_STRING, {0}, FALSE }, - { OPTION_IGNORE_LID_STATUS, "IgnoreLidStatus", OPTV_BOOLEAN, {0}, FALSE }, -+ { OPTION_DEFAULT_TVDAC_ADJ, "DefaultTVDACAdj", OPTV_BOOLEAN, {0}, FALSE }, -+ { OPTION_INT10, "Int10", OPTV_BOOLEAN, {0}, FALSE }, - { -1, NULL, OPTV_NONE, {0}, FALSE } - }; - - const OptionInfoRec *RADEONOptionsWeak(void) { return RADEONOptions; } - -+extern _X_EXPORT int gRADEONEntityIndex; -+ - static int getRADEONEntityIndex(void) - { -- int *radeon_entity_index = LoaderSymbol("gRADEONEntityIndex"); -- if (!radeon_entity_index) -- return -1; -- else -- return *radeon_entity_index; -+ return gRADEONEntityIndex; - } - - struct RADEONInt10Save { -- CARD32 MEM_CNTL; -- CARD32 MEMSIZE; -- CARD32 MPP_TB_CONFIG; -+ uint32_t MEM_CNTL; -+ uint32_t MEMSIZE; -+ uint32_t MPP_TB_CONFIG; - }; - - static Bool RADEONMapMMIO(ScrnInfoPtr pScrn); -@@ -253,8 +224,7 @@ radeonShadowWindow(ScreenPtr screen, CARD32 row, CARD32 offset, int mode, - stride = (pScrn->displayWidth * pScrn->bitsPerPixel) / 8; - *size = stride; - -- return ((CARD8 *)info->FB + pScrn->fbOffset + -- row * stride + offset); -+ return ((uint8_t *)info->FB + row * stride + offset); - } - static Bool - RADEONCreateScreenResources (ScreenPtr pScreen) -@@ -292,8 +262,8 @@ RADEONPreInt10Save(ScrnInfoPtr pScrn, void **pPtr) - { - RADEONInfoPtr info = RADEONPTR(pScrn); - unsigned char *RADEONMMIO = info->MMIO; -- CARD32 CardTmp; -- static struct RADEONInt10Save SaveStruct = { 0, 0, 0 }; -+ uint32_t CardTmp; -+ static struct RADEONInt10Save SaveStruct = { 0, 0, 0 }; - - if (!IS_AVIVO_VARIANT) { - /* Save the values and zap MEM_CNTL */ -@@ -319,7 +289,7 @@ RADEONPostInt10Check(ScrnInfoPtr pScrn, void *ptr) - RADEONInfoPtr info = RADEONPTR(pScrn); - unsigned char *RADEONMMIO = info->MMIO; - struct RADEONInt10Save *pSave = ptr; -- CARD32 CardTmp; -+ uint32_t CardTmp; - - /* If we don't have a valid (non-zero) saved MEM_CNTL, get out now */ - if (!pSave || !pSave->MEM_CNTL) -@@ -387,6 +357,12 @@ static void RADEONFreeRec(ScrnInfoPtr pScrn) - static Bool RADEONMapMMIO(ScrnInfoPtr pScrn) - { - RADEONInfoPtr info = RADEONPTR(pScrn); -+ RADEONEntPtr pRADEONEnt = RADEONEntPriv(pScrn); -+ -+ if (pRADEONEnt->MMIO) { -+ info->MMIO = pRADEONEnt->MMIO; -+ return TRUE; -+ } - - #ifndef XSERVER_LIBPCIACCESS - -@@ -397,7 +373,6 @@ static Bool RADEONMapMMIO(ScrnInfoPtr pScrn) - info->MMIOSize); - - if (!info->MMIO) return FALSE; -- - #else - - void** result = (void**)&info->MMIO; -@@ -416,6 +391,7 @@ static Bool RADEONMapMMIO(ScrnInfoPtr pScrn) - - #endif - -+ pRADEONEnt->MMIO = info->MMIO; - return TRUE; - } - -@@ -425,6 +401,13 @@ static Bool RADEONMapMMIO(ScrnInfoPtr pScrn) - static Bool RADEONUnmapMMIO(ScrnInfoPtr pScrn) - { - RADEONInfoPtr info = RADEONPTR(pScrn); -+ RADEONEntPtr pRADEONEnt = RADEONEntPriv(pScrn); -+ -+ if (info->IsPrimary || info->IsSecondary) { -+ /* never unmap on zaphod */ -+ info->MMIO = NULL; -+ return TRUE; -+ } - - #ifndef XSERVER_LIBPCIACCESS - xf86UnMapVidMem(pScrn->scrnIndex, info->MMIO, info->MMIOSize); -@@ -432,6 +415,7 @@ static Bool RADEONUnmapMMIO(ScrnInfoPtr pScrn) - pci_device_unmap_range(info->PciInfo, info->MMIO, info->MMIOSize); - #endif - -+ pRADEONEnt->MMIO = NULL; - info->MMIO = NULL; - return TRUE; - } -@@ -439,6 +423,9 @@ static Bool RADEONUnmapMMIO(ScrnInfoPtr pScrn) - /* Memory map the frame buffer. Used by RADEONMapMem, below. */ - static Bool RADEONMapFB(ScrnInfoPtr pScrn) - { -+#ifdef XSERVER_LIBPCIACCESS -+ int err; -+#endif - RADEONInfoPtr info = RADEONPTR(pScrn); - - xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG, -@@ -456,7 +443,7 @@ static Bool RADEONMapFB(ScrnInfoPtr pScrn) - - #else - -- int err = pci_device_map_range(info->PciInfo, -+ err = pci_device_map_range(info->PciInfo, - info->LinearAddr, - info->FbMapSize, - PCI_DEV_MAP_FLAG_WRITABLE | -@@ -540,7 +527,7 @@ void RADEONPllErrataAfterData(RADEONInfoPtr info) - * may not be correct. - */ - if (info->ChipErrata & CHIP_ERRATA_R300_CG) { -- CARD32 save, tmp; -+ uint32_t save, tmp; - - save = INREG(RADEON_CLOCK_CNTL_INDEX); - tmp = save & ~(0x3f | RADEON_PLL_WR_EN); -@@ -555,7 +542,7 @@ unsigned RADEONINPLL(ScrnInfoPtr pScrn, int addr) - { - RADEONInfoPtr info = RADEONPTR(pScrn); - unsigned char *RADEONMMIO = info->MMIO; -- CARD32 data; -+ uint32_t data; - - OUTREG8(RADEON_CLOCK_CNTL_INDEX, addr & 0x3f); - RADEONPllErrataAfterIndex(info); -@@ -566,7 +553,7 @@ unsigned RADEONINPLL(ScrnInfoPtr pScrn, int addr) - } - - /* Write PLL information */ --void RADEONOUTPLL(ScrnInfoPtr pScrn, int addr, CARD32 data) -+void RADEONOUTPLL(ScrnInfoPtr pScrn, int addr, uint32_t data) - { - RADEONInfoPtr info = RADEONPTR(pScrn); - unsigned char *RADEONMMIO = info->MMIO; -@@ -583,12 +570,15 @@ unsigned RADEONINMC(ScrnInfoPtr pScrn, int addr) - { - RADEONInfoPtr info = RADEONPTR(pScrn); - unsigned char *RADEONMMIO = info->MMIO; -- CARD32 data; -- -- if (info->ChipFamily == CHIP_FAMILY_RS690) -- { -- OUTREG(RS690_MC_INDEX, (addr & RS690_MC_INDEX_MASK)); -- data = INREG(RS690_MC_DATA); -+ uint32_t data; -+ -+ if ((info->ChipFamily == CHIP_FAMILY_RS690) || -+ (info->ChipFamily == CHIP_FAMILY_RS740)) { -+ OUTREG(RS690_MC_INDEX, (addr & RS690_MC_INDEX_MASK)); -+ data = INREG(RS690_MC_DATA); -+ } else if (info->ChipFamily == CHIP_FAMILY_RS600) { -+ OUTREG(RS600_MC_INDEX, (addr & RS600_MC_INDEX_MASK)); -+ data = INREG(RS600_MC_DATA); - } else if (IS_AVIVO_VARIANT) { - OUTREG(AVIVO_MC_INDEX, (addr & 0xff) | 0x7f0000); - (void)INREG(AVIVO_MC_INDEX); -@@ -609,17 +599,22 @@ unsigned RADEONINMC(ScrnInfoPtr pScrn, int addr) - } - - /* Write MC information */ --void RADEONOUTMC(ScrnInfoPtr pScrn, int addr, CARD32 data) -+void RADEONOUTMC(ScrnInfoPtr pScrn, int addr, uint32_t data) - { - RADEONInfoPtr info = RADEONPTR(pScrn); - unsigned char *RADEONMMIO = info->MMIO; - -- if (info->ChipFamily == CHIP_FAMILY_RS690) -- { -- OUTREG(RS690_MC_INDEX, ((addr & RS690_MC_INDEX_MASK) | -- RS690_MC_INDEX_WR_EN)); -- OUTREG(RS690_MC_DATA, data); -- OUTREG(RS690_MC_INDEX, RS690_MC_INDEX_WR_ACK); -+ if ((info->ChipFamily == CHIP_FAMILY_RS690) || -+ (info->ChipFamily == CHIP_FAMILY_RS740)) { -+ OUTREG(RS690_MC_INDEX, ((addr & RS690_MC_INDEX_MASK) | -+ RS690_MC_INDEX_WR_EN)); -+ OUTREG(RS690_MC_DATA, data); -+ OUTREG(RS690_MC_INDEX, RS690_MC_INDEX_WR_ACK); -+ } else if (info->ChipFamily == CHIP_FAMILY_RS600) { -+ OUTREG(RS600_MC_INDEX, ((addr & RS600_MC_INDEX_MASK) | -+ RS600_MC_INDEX_WR_EN)); -+ OUTREG(RS600_MC_DATA, data); -+ OUTREG(RS600_MC_INDEX, RS600_MC_INDEX_WR_ACK); - } else if (IS_AVIVO_VARIANT) { - OUTREG(AVIVO_MC_INDEX, (addr & 0xff) | 0xff0000); - (void)INREG(AVIVO_MC_INDEX); -@@ -636,7 +631,7 @@ void RADEONOUTMC(ScrnInfoPtr pScrn, int addr, CARD32 data) - } - } - --Bool avivo_get_mc_idle(ScrnInfoPtr pScrn) -+static Bool avivo_get_mc_idle(ScrnInfoPtr pScrn) - { - RADEONInfoPtr info = RADEONPTR(pScrn); - -@@ -648,7 +643,13 @@ Bool avivo_get_mc_idle(ScrnInfoPtr pScrn) - return TRUE; - else - return FALSE; -- } else if (info->ChipFamily == CHIP_FAMILY_RS690) { -+ } else if (info->ChipFamily == CHIP_FAMILY_RS600) { -+ if (INMC(pScrn, RS600_MC_STATUS) & RS600_MC_STATUS_IDLE) -+ return TRUE; -+ else -+ return FALSE; -+ } else if ((info->ChipFamily == CHIP_FAMILY_RS690) || -+ (info->ChipFamily == CHIP_FAMILY_RS740)) { - if (INMC(pScrn, RS690_MC_STATUS) & RS690_MC_STATUS_IDLE) - return TRUE; - else -@@ -663,12 +664,19 @@ Bool avivo_get_mc_idle(ScrnInfoPtr pScrn) - - #define LOC_FB 0x1 - #define LOC_AGP 0x2 --void radeon_write_mc_fb_agp_location(ScrnInfoPtr pScrn, int mask, CARD32 fb_loc, CARD32 agp_loc, CARD32 agp_loc_hi) -+static void radeon_write_mc_fb_agp_location(ScrnInfoPtr pScrn, int mask, uint32_t fb_loc, uint32_t agp_loc, uint32_t agp_loc_hi) - { - RADEONInfoPtr info = RADEONPTR(pScrn); - unsigned char *RADEONMMIO = info->MMIO; - -- if (info->ChipFamily >= CHIP_FAMILY_R600) { -+ if (info->ChipFamily >= CHIP_FAMILY_RV770) { -+ if (mask & LOC_FB) -+ OUTREG(R700_MC_VM_FB_LOCATION, fb_loc); -+ if (mask & LOC_AGP) { -+ OUTREG(R600_MC_VM_AGP_BOT, agp_loc); -+ OUTREG(R600_MC_VM_AGP_TOP, agp_loc_hi); -+ } -+ } else if (info->ChipFamily >= CHIP_FAMILY_R600) { - if (mask & LOC_FB) - OUTREG(R600_MC_VM_FB_LOCATION, fb_loc); - if (mask & LOC_AGP) { -@@ -681,12 +689,18 @@ void radeon_write_mc_fb_agp_location(ScrnInfoPtr pScrn, int mask, CARD32 fb_loc, - if (mask & LOC_AGP) - OUTMC(pScrn, RV515_MC_AGP_LOCATION, agp_loc); - (void)INMC(pScrn, RV515_MC_AGP_LOCATION); -- } else if (info->ChipFamily == CHIP_FAMILY_RS690) { -+ } else if (info->ChipFamily == CHIP_FAMILY_RS600) { -+ if (mask & LOC_FB) -+ OUTMC(pScrn, RS600_MC_FB_LOCATION, fb_loc); -+ /* if (mask & LOC_AGP) -+ OUTMC(pScrn, RS600_MC_AGP_LOCATION, agp_loc);*/ -+ } else if ((info->ChipFamily == CHIP_FAMILY_RS690) || -+ (info->ChipFamily == CHIP_FAMILY_RS740)) { - if (mask & LOC_FB) - OUTMC(pScrn, RS690_MC_FB_LOCATION, fb_loc); - if (mask & LOC_AGP) - OUTMC(pScrn, RS690_MC_AGP_LOCATION, agp_loc); -- } else if (info->ChipFamily >= CHIP_FAMILY_R520) { -+ } else if (info->ChipFamily >= CHIP_FAMILY_R520) { - if (mask & LOC_FB) - OUTMC(pScrn, R520_MC_FB_LOCATION, fb_loc); - if (mask & LOC_AGP) -@@ -700,12 +714,19 @@ void radeon_write_mc_fb_agp_location(ScrnInfoPtr pScrn, int mask, CARD32 fb_loc, - } - } - --void radeon_read_mc_fb_agp_location(ScrnInfoPtr pScrn, int mask, CARD32 *fb_loc, CARD32 *agp_loc, CARD32 *agp_loc_hi) -+static void radeon_read_mc_fb_agp_location(ScrnInfoPtr pScrn, int mask, uint32_t *fb_loc, uint32_t *agp_loc, uint32_t *agp_loc_hi) - { - RADEONInfoPtr info = RADEONPTR(pScrn); - unsigned char *RADEONMMIO = info->MMIO; - -- if (info->ChipFamily >= CHIP_FAMILY_R600) { -+ if (info->ChipFamily >= CHIP_FAMILY_RV770) { -+ if (mask & LOC_FB) -+ *fb_loc = INREG(R700_MC_VM_FB_LOCATION); -+ if (mask & LOC_AGP) { -+ *agp_loc = INREG(R600_MC_VM_AGP_BOT); -+ *agp_loc_hi = INREG(R600_MC_VM_AGP_TOP); -+ } -+ } else if (info->ChipFamily >= CHIP_FAMILY_R600) { - if (mask & LOC_FB) - *fb_loc = INREG(R600_MC_VM_FB_LOCATION); - if (mask & LOC_AGP) { -@@ -719,7 +740,15 @@ void radeon_read_mc_fb_agp_location(ScrnInfoPtr pScrn, int mask, CARD32 *fb_loc, - *agp_loc = INMC(pScrn, RV515_MC_AGP_LOCATION); - *agp_loc_hi = 0; - } -- } else if (info->ChipFamily == CHIP_FAMILY_RS690) { -+ } else if (info->ChipFamily == CHIP_FAMILY_RS600) { -+ if (mask & LOC_FB) -+ *fb_loc = INMC(pScrn, RS600_MC_FB_LOCATION); -+ if (mask & LOC_AGP) { -+ *agp_loc = 0;//INMC(pScrn, RS600_MC_AGP_LOCATION); -+ *agp_loc_hi = 0; -+ } -+ } else if ((info->ChipFamily == CHIP_FAMILY_RS690) || -+ (info->ChipFamily == CHIP_FAMILY_RS740)) { - if (mask & LOC_FB) - *fb_loc = INMC(pScrn, RS690_MC_FB_LOCATION); - if (mask & LOC_AGP) { -@@ -758,7 +787,7 @@ void RADEONWaitForVerticalSync(ScrnInfoPtr pScrn) - { - RADEONInfoPtr info = RADEONPTR(pScrn); - unsigned char *RADEONMMIO = info->MMIO; -- CARD32 crtc_gen_cntl; -+ uint32_t crtc_gen_cntl; - struct timeval timeout; - - crtc_gen_cntl = INREG(RADEON_CRTC_GEN_CNTL); -@@ -781,7 +810,7 @@ void RADEONWaitForVerticalSync2(ScrnInfoPtr pScrn) - { - RADEONInfoPtr info = RADEONPTR(pScrn); - unsigned char *RADEONMMIO = info->MMIO; -- CARD32 crtc2_gen_cntl; -+ uint32_t crtc2_gen_cntl; - struct timeval timeout; - - crtc2_gen_cntl = INREG(RADEON_CRTC2_GEN_CNTL); -@@ -938,12 +967,12 @@ static Bool RADEONProbePLLParameters(ScrnInfoPtr pScrn) - xtal = 2700; - } else { - if (prev_xtal == 0) { -- prev_xtal = xtal; -- tries = 0; -- goto again; -+ prev_xtal = xtal; -+ tries = 0; -+ goto again; - } else if (prev_xtal != xtal) { -- prev_xtal = 0; -- goto again; -+ prev_xtal = 0; -+ goto again; - } - } - -@@ -952,16 +981,18 @@ static Bool RADEONProbePLLParameters(ScrnInfoPtr pScrn) - - /* Some sanity check based on the BIOS code .... */ - if (ref_div < 2) { -- CARD32 tmp; -+ uint32_t tmp; - tmp = INPLL(pScrn, RADEON_PPLL_REF_DIV); -- if (IS_R300_VARIANT || (info->ChipFamily == CHIP_FAMILY_RS300) -- || (info->ChipFamily == CHIP_FAMILY_RS400)) -- ref_div = (tmp & R300_PPLL_REF_DIV_ACC_MASK) >> -- R300_PPLL_REF_DIV_ACC_SHIFT; -+ if (IS_R300_VARIANT -+ || (info->ChipFamily == CHIP_FAMILY_RS300) -+ || (info->ChipFamily == CHIP_FAMILY_RS400) -+ || (info->ChipFamily == CHIP_FAMILY_RS480)) -+ ref_div = (tmp & R300_PPLL_REF_DIV_ACC_MASK) >> -+ R300_PPLL_REF_DIV_ACC_SHIFT; - else -- ref_div = tmp & RADEON_PPLL_REF_DIV_MASK; -+ ref_div = tmp & RADEON_PPLL_REF_DIV_MASK; - if (ref_div < 2) -- ref_div = 12; -+ ref_div = 12; - } - - /* Calculate "base" xclk straight from MPLL, though that isn't -@@ -1031,11 +1062,12 @@ static void RADEONGetClockInfo(ScrnInfoPtr pScrn) - We'll probably need a new routine to calculate the best ref_div from BIOS - provided min_input_pll and max_input_pll - */ -- CARD32 tmp; -+ uint32_t tmp; - tmp = INPLL(pScrn, RADEON_PPLL_REF_DIV); - if (IS_R300_VARIANT || - (info->ChipFamily == CHIP_FAMILY_RS300) || -- (info->ChipFamily == CHIP_FAMILY_RS400)) { -+ (info->ChipFamily == CHIP_FAMILY_RS400) || -+ (info->ChipFamily == CHIP_FAMILY_RS480)) { - pll->reference_div = (tmp & R300_PPLL_REF_DIV_ACC_MASK) >> R300_PPLL_REF_DIV_ACC_SHIFT; - } else { - pll->reference_div = tmp & RADEON_PPLL_REF_DIV_MASK; -@@ -1226,8 +1258,8 @@ static void RADEONInitMemoryMap(ScrnInfoPtr pScrn) - { - RADEONInfoPtr info = RADEONPTR(pScrn); - unsigned char *RADEONMMIO = info->MMIO; -- CARD32 mem_size; -- CARD32 aper_size; -+ uint32_t mem_size; -+ uint32_t aper_size; - - radeon_read_mc_fb_agp_location(pScrn, LOC_FB | LOC_AGP, &info->mc_fb_location, - &info->mc_agp_location, &info->mc_agp_location_hi); -@@ -1259,7 +1291,9 @@ static void RADEONInitMemoryMap(ScrnInfoPtr pScrn) - } - #endif - -- if (info->ChipFamily != CHIP_FAMILY_RS690) { -+ if ((info->ChipFamily != CHIP_FAMILY_RS600) && -+ (info->ChipFamily != CHIP_FAMILY_RS690) && -+ (info->ChipFamily != CHIP_FAMILY_RS740)) { - if (info->IsIGP) - info->mc_fb_location = INREG(RADEON_NB_TOM); - else -@@ -1271,7 +1305,7 @@ static void RADEONInitMemoryMap(ScrnInfoPtr pScrn) - else - #endif - { -- CARD32 aper0_base; -+ uint32_t aper0_base; - - if (info->ChipFamily >= CHIP_FAMILY_R600) { - aper0_base = INREG(R600_CONFIG_F0_BASE); -@@ -1338,17 +1372,64 @@ static void RADEONGetVRamType(ScrnInfoPtr pScrn) - RADEONInfoPtr info = RADEONPTR(pScrn); - RADEONEntPtr pRADEONEnt = RADEONEntPriv(pScrn); - unsigned char *RADEONMMIO = info->MMIO; -- CARD32 tmp; -- -- if (info->IsIGP || (info->ChipFamily >= CHIP_FAMILY_R300) || -- (INREG(RADEON_MEM_SDRAM_MODE_REG) & (1<<30))) -+ uint32_t tmp; -+ -+ if (info->IsIGP || (info->ChipFamily >= CHIP_FAMILY_R300)) -+ info->IsDDR = TRUE; -+ else if (INREG(RADEON_MEM_SDRAM_MODE_REG) & RADEON_MEM_CFG_TYPE_DDR) - info->IsDDR = TRUE; - else - info->IsDDR = FALSE; - -- tmp = INREG(RADEON_MEM_CNTL); -- if (IS_R300_VARIANT) { -- tmp &= R300_MEM_NUM_CHANNELS_MASK; -+ if ((info->ChipFamily >= CHIP_FAMILY_R600) && -+ (info->ChipFamily <= CHIP_FAMILY_RV635)) { -+ int chansize; -+ /* r6xx */ -+ tmp = INREG(R600_RAMCFG); -+ if (tmp & R600_CHANSIZE_OVERRIDE) -+ chansize = 16; -+ else if (tmp & R600_CHANSIZE) -+ chansize = 64; -+ else -+ chansize = 32; -+ if (info->ChipFamily == CHIP_FAMILY_R600) -+ info->RamWidth = 8 * chansize; -+ else if (info->ChipFamily == CHIP_FAMILY_RV670) -+ info->RamWidth = 4 * chansize; -+ else if ((info->ChipFamily == CHIP_FAMILY_RV610) || -+ (info->ChipFamily == CHIP_FAMILY_RV620)) -+ info->RamWidth = chansize; -+ else if ((info->ChipFamily == CHIP_FAMILY_RV630) || -+ (info->ChipFamily == CHIP_FAMILY_RV635)) -+ info->RamWidth = 2 * chansize; -+ } else if (info->ChipFamily == CHIP_FAMILY_RV515) { -+ /* rv515/rv550 */ -+ tmp = INMC(pScrn, RV515_MC_CNTL); -+ tmp &= RV515_MEM_NUM_CHANNELS_MASK; -+ switch (tmp) { -+ case 0: info->RamWidth = 64; break; -+ case 1: info->RamWidth = 128; break; -+ default: info->RamWidth = 128; break; -+ } -+ } else if ((info->ChipFamily >= CHIP_FAMILY_R520) && -+ (info->ChipFamily <= CHIP_FAMILY_RV570)){ -+ /* r520/rv530/rv560/rv570/r580 */ -+ tmp = INMC(pScrn, R520_MC_CNTL0); -+ switch ((tmp & R520_MEM_NUM_CHANNELS_MASK) >> R520_MEM_NUM_CHANNELS_SHIFT) { -+ case 0: info->RamWidth = 32; break; -+ case 1: info->RamWidth = 64; break; -+ case 2: info->RamWidth = 128; break; -+ case 3: info->RamWidth = 256; break; -+ default: info->RamWidth = 64; break; -+ } -+ if (tmp & R520_MC_CHANNEL_SIZE) { -+ info->RamWidth *= 2; -+ } -+ } else if ((info->ChipFamily >= CHIP_FAMILY_R300) && -+ (info->ChipFamily <= CHIP_FAMILY_RV410)) { -+ /* r3xx, r4xx */ -+ tmp = INREG(RADEON_MEM_CNTL); -+ tmp &= R300_MEM_NUM_CHANNELS_MASK; - switch (tmp) { - case 0: info->RamWidth = 64; break; - case 1: info->RamWidth = 128; break; -@@ -1358,15 +1439,25 @@ static void RADEONGetVRamType(ScrnInfoPtr pScrn) - } else if ((info->ChipFamily == CHIP_FAMILY_RV100) || - (info->ChipFamily == CHIP_FAMILY_RS100) || - (info->ChipFamily == CHIP_FAMILY_RS200)){ -- if (tmp & RV100_HALF_MODE) info->RamWidth = 32; -- else info->RamWidth = 64; -- if (!pRADEONEnt->HasCRTC2) { -- info->RamWidth /= 4; -- info->IsDDR = TRUE; -- } -+ tmp = INREG(RADEON_MEM_CNTL); -+ if (tmp & RV100_HALF_MODE) -+ info->RamWidth = 32; -+ else -+ info->RamWidth = 64; -+ -+ if (!pRADEONEnt->HasCRTC2) { -+ info->RamWidth /= 4; -+ info->IsDDR = TRUE; -+ } -+ } else if (info->ChipFamily <= CHIP_FAMILY_RV280) { -+ tmp = INREG(RADEON_MEM_CNTL); -+ if (tmp & RADEON_MEM_NUM_CHANNELS_MASK) -+ info->RamWidth = 128; -+ else -+ info->RamWidth = 64; - } else { -- if (tmp & RADEON_MEM_NUM_CHANNELS_MASK) info->RamWidth = 128; -- else info->RamWidth = 64; -+ /* newer IGPs */ -+ info->RamWidth = 128; - } - - /* This may not be correct, as some cards can have half of channel disabled -@@ -1379,11 +1470,11 @@ static void RADEONGetVRamType(ScrnInfoPtr pScrn) - * accessible to the CPU can vary. This function is our best shot at figuring - * it out. Returns a value in KB. - */ --static CARD32 RADEONGetAccessibleVRAM(ScrnInfoPtr pScrn) -+static uint32_t RADEONGetAccessibleVRAM(ScrnInfoPtr pScrn) - { - RADEONInfoPtr info = RADEONPTR(pScrn); - unsigned char *RADEONMMIO = info->MMIO; -- CARD32 aper_size; -+ uint32_t aper_size; - unsigned char byte; - - if (info->ChipFamily >= CHIP_FAMILY_R600) -@@ -1456,25 +1547,22 @@ static Bool RADEONPreInitVRAM(ScrnInfoPtr pScrn) - GDevPtr dev = pEnt->device; - unsigned char *RADEONMMIO = info->MMIO; - MessageType from = X_PROBED; -- CARD32 accessible, bar_size; -+ uint32_t accessible, bar_size; - -- if (info->ChipFamily == CHIP_FAMILY_RS690) { -- pScrn->videoRam = INREG(RADEON_CONFIG_MEMSIZE); -- } else if (info->IsIGP) { -- CARD32 tom = INREG(RADEON_NB_TOM); -+ if ((!IS_AVIVO_VARIANT) && info->IsIGP) { -+ uint32_t tom = INREG(RADEON_NB_TOM); - - pScrn->videoRam = (((tom >> 16) - - (tom & 0xffff) + 1) << 6); - - OUTREG(RADEON_CONFIG_MEMSIZE, pScrn->videoRam * 1024); - } else { -- - if (info->ChipFamily >= CHIP_FAMILY_R600) - pScrn->videoRam = INREG(R600_CONFIG_MEMSIZE) / 1024; - else { - /* Read VRAM size from card */ - pScrn->videoRam = INREG(RADEON_CONFIG_MEMSIZE) / 1024; -- -+ - /* Some production boards of m6 will return 0 if it's 8 MB */ - if (pScrn->videoRam == 0) { - pScrn->videoRam = 8192; -@@ -1614,7 +1702,7 @@ static Bool RADEONPreInitChipType(ScrnInfoPtr pScrn) - break; - } - } -- -+ - switch (info->Chipset) { - case PCI_CHIP_RN50_515E: /* RN50 is based on the RV100 but 3D isn't guaranteed to work. YMMV. */ - case PCI_CHIP_RN50_5969: -@@ -1636,6 +1724,13 @@ static Bool RADEONPreInitChipType(ScrnInfoPtr pScrn) - xf86DrvMsg(pScrn->scrnIndex, X_INFO, "DELL server detected, force to special setup\n"); - } - break; -+ case PCI_CHIP_RS482_5974: -+ /* RH BZ 444586 - non mobility version -+ * Dell appear to have the Vostro 1100 with a mobility part with the same pci-id */ -+ if ((PCI_SUB_VENDOR_ID(info->PciInfo) == 0x1462) && -+ (PCI_SUB_DEVICE_ID(info->PciInfo) == 0x7141)) { -+ info->IsMobility = FALSE; -+ } - default: - break; - } -@@ -1811,6 +1906,21 @@ static Bool RADEONPreInitChipType(ScrnInfoPtr pScrn) - if (!xf86LoadSubModule(pScrn, "shadow")) - return FALSE; - } -+ -+ -+ if ((info->ChipFamily == CHIP_FAMILY_RS100) || -+ (info->ChipFamily == CHIP_FAMILY_RS200) || -+ (info->ChipFamily == CHIP_FAMILY_RS300) || -+ (info->ChipFamily == CHIP_FAMILY_RS400) || -+ (info->ChipFamily == CHIP_FAMILY_RS480) || -+ (info->ChipFamily == CHIP_FAMILY_RS600) || -+ (info->ChipFamily == CHIP_FAMILY_RS690) || -+ (info->ChipFamily == CHIP_FAMILY_RS740)) -+ info->has_tcl = FALSE; -+ else { -+ info->has_tcl = TRUE; -+ } -+ - return TRUE; - } - -@@ -1936,10 +2046,31 @@ static Bool RADEONPreInitAccel(ScrnInfoPtr pScrn) - - static Bool RADEONPreInitInt10(ScrnInfoPtr pScrn, xf86Int10InfoPtr *ppInt10) - { --#if !defined(__powerpc__) && !defined(__sparc__) -+#if (!defined(__powerpc__) && !defined(__sparc__)) || \ -+ (defined(XSERVER_LIBPCIACCESS) && HAVE_PCI_DEVICE_ENABLE) - RADEONInfoPtr info = RADEONPTR(pScrn); -+#endif -+#if !defined(__powerpc__) && !defined(__sparc__) - unsigned char *RADEONMMIO = info->MMIO; -- CARD32 fp2_gen_ctl_save = 0; -+ uint32_t fp2_gen_ctl_save = 0; -+#endif -+ -+#ifdef XSERVER_LIBPCIACCESS -+#if HAVE_PCI_DEVICE_ENABLE -+ pci_device_enable(info->PciInfo); -+#endif -+#endif -+ -+#if !defined(__powerpc__) && !defined(__sparc__) -+ /* don't need int10 on atom cards. -+ * in theory all radeons, but the older stuff -+ * isn't 100% yet -+ * secondary atom cards tend to hang when initializing int10, -+ * however, on some stom cards, you can't read the bios without -+ * intitializing int10. -+ */ -+ if (!xf86ReturnOptValBool(info->Options, OPTION_INT10, TRUE)) -+ return TRUE; - - if (xf86LoadSubModule(pScrn, "int10")) { - /* The VGA BIOS on the RV100/QY cannot be read when the digital output -@@ -1952,13 +2083,15 @@ static Bool RADEONPreInitInt10(ScrnInfoPtr pScrn, xf86Int10InfoPtr *ppInt10) - OUTREG(RADEON_FP2_GEN_CNTL, fp2_gen_ctl_save & ~RADEON_FP2_ON); - } - } -- -+ - xf86DrvMsg(pScrn->scrnIndex,X_INFO,"initializing int10\n"); - *ppInt10 = xf86InitInt10(info->pEnt->index); - -- if (fp2_gen_ctl_save & RADEON_FP2_ON) { -- xf86DrvMsg(pScrn->scrnIndex, X_INFO, "re-enabling digital out\n"); -- OUTREG(RADEON_FP2_GEN_CNTL, fp2_gen_ctl_save); -+ if (PCI_DEV_DEVICE_ID(info->PciInfo) == PCI_CHIP_RV100_QY) { -+ if (fp2_gen_ctl_save & RADEON_FP2_ON) { -+ xf86DrvMsg(pScrn->scrnIndex, X_INFO, "re-enabling digital out\n"); -+ OUTREG(RADEON_FP2_GEN_CNTL, fp2_gen_ctl_save); -+ } - } - } - #endif -@@ -1993,18 +2126,16 @@ static Bool RADEONPreInitDRI(ScrnInfoPtr pScrn) - - if (info->Chipset == PCI_CHIP_RN50_515E || - info->Chipset == PCI_CHIP_RN50_5969 || -- info->Chipset == PCI_CHIP_RC410_5A61 || -- info->Chipset == PCI_CHIP_RC410_5A62 || -- info->Chipset == PCI_CHIP_RS485_5975 || -+ info->ChipFamily == CHIP_FAMILY_RS600 || - info->ChipFamily >= CHIP_FAMILY_R600) { -- if (xf86ReturnOptValBool(info->Options, OPTION_DRI, FALSE)) { -+ if (xf86ReturnOptValBool(info->Options, OPTION_DRI, FALSE)) { - xf86DrvMsg(pScrn->scrnIndex, X_WARNING, -- "Direct rendering for RN50/RC410/RS485/R600 forced on -- " -+ "Direct rendering for RN50/RS600/R600 forced on -- " - "This is NOT officially supported at the hardware level " - "and may cause instability or lockups\n"); -- } else { -+ } else { - xf86DrvMsg(pScrn->scrnIndex, X_INFO, -- "Direct rendering not officially supported on RN50/RC410/R600\n"); -+ "Direct rendering not officially supported on RN50/RS600/R600\n"); - return FALSE; - } - } -@@ -2053,14 +2184,11 @@ static Bool RADEONPreInitDRI(ScrnInfoPtr pScrn) - "Direct rendering experimental on RS400/Xpress 200 enabled\n"); - } - -- if (xf86ReturnOptValBool(info->Options, OPTION_CP_PIO, FALSE)) { -- xf86DrvMsg(pScrn->scrnIndex, X_CONFIG, "Forcing CP into PIO mode\n"); -- info->CPMode = RADEON_DEFAULT_CP_PIO_MODE; -- } else { -- info->CPMode = RADEON_DEFAULT_CP_BM_MODE; -- } -+ if (info->ChipFamily >= CHIP_FAMILY_R300) -+ info->gartSize = R300_DEFAULT_GART_SIZE; -+ else -+ info->gartSize = RADEON_DEFAULT_GART_SIZE; - -- info->gartSize = RADEON_DEFAULT_GART_SIZE; - info->ringSize = RADEON_DEFAULT_RING_SIZE; - info->bufSize = RADEON_DEFAULT_BUFFER_SIZE; - info->gartTexSize = RADEON_DEFAULT_GART_TEX_SIZE; -@@ -2163,7 +2291,14 @@ static Bool RADEONPreInitDRI(ScrnInfoPtr pScrn) - } else { - from = xf86GetOptValBool(info->Options, OPTION_PAGE_FLIP, - &info->allowPageFlip) ? X_CONFIG : X_DEFAULT; -- reason = ""; -+ -+ if (IS_AVIVO_VARIANT) { -+ info->allowPageFlip = 0; -+ reason = " on r5xx and newer chips.\n"; -+ } else { -+ reason = ""; -+ } -+ - } - #else - from = X_DEFAULT; -@@ -2221,7 +2356,7 @@ static void RADEONPreInitColorTiling(ScrnInfoPtr pScrn) - info->pKernelDRMVersion->version_minor, - info->pKernelDRMVersion->version_patchlevel); - info->allowColorTiling = FALSE; -- return; -+ return; - } - #endif /* XF86DRI */ - -@@ -2236,9 +2371,9 @@ static void RADEONPreInitColorTiling(ScrnInfoPtr pScrn) - static Bool RADEONPreInitXv(ScrnInfoPtr pScrn) - { - RADEONInfoPtr info = RADEONPTR(pScrn); -- CARD16 mm_table; -- CARD16 bios_header; -- CARD16 pll_info_block; -+ uint16_t mm_table; -+ uint16_t bios_header; -+ uint16_t pll_info_block; - #ifdef XvExtension - char* microc_path = NULL; - char* microc_type = NULL; -@@ -2366,7 +2501,7 @@ static Bool RADEONPreInitXv(ScrnInfoPtr pScrn) - } - - bios_header=info->VBIOS[0x48]; -- bios_header+=(((int)info->VBIOS[0x49]+0)<<8); -+ bios_header+=(((int)info->VBIOS[0x49]+0)<<8); - - mm_table=info->VBIOS[bios_header+0x38]; - if(mm_table==0) -@@ -2420,13 +2555,17 @@ static Bool RADEONPreInitXv(ScrnInfoPtr pScrn) - return TRUE; - } - --static void RADEONPreInitBIOS(ScrnInfoPtr pScrn, xf86Int10InfoPtr pInt10) -+static Bool -+RADEONPreInitBIOS(ScrnInfoPtr pScrn, xf86Int10InfoPtr pInt10) - { -- RADEONGetBIOSInfo(pScrn, pInt10); --#if 0 -- RADEONGetBIOSInitTableOffsets(pScrn); -- RADEONPostCardFromBIOSTables(pScrn); --#endif -+ RADEONInfoPtr info = RADEONPTR(pScrn); -+ -+ if (!RADEONGetBIOSInfo(pScrn, pInt10)) { -+ /* Avivo chips require bios for atom */ -+ if (IS_AVIVO_VARIANT) -+ return FALSE; -+ } -+ return TRUE; - } - - static void RADEONFixZaphodOutputs(ScrnInfoPtr pScrn) -@@ -2636,8 +2775,7 @@ Bool RADEONPreInit(ScrnInfoPtr pScrn, int flags) - if (xf86RegisterResources(info->pEnt->index, 0, ResExclusive)) - goto fail; - -- if (xf86SetOperatingState(resVga, info->pEnt->index, ResUnusedOpr)) -- goto fail; -+ xf86SetOperatingState(resVga, info->pEnt->index, ResUnusedOpr); - - pScrn->racMemFlags = RAC_FB | RAC_COLORMAP | RAC_VIEWPORT | RAC_CURSOR; - pScrn->monitor = pScrn->confScreen->monitor; -@@ -2689,7 +2827,7 @@ Bool RADEONPreInit(ScrnInfoPtr pScrn, int flags) - if (!RADEONPreInitWeight(pScrn)) - goto fail; - -- info->DispPriority = 1; -+ info->DispPriority = 1; - if ((s = xf86GetOptValString(info->Options, OPTION_DISP_PRIORITY))) { - if (strcmp(s, "AUTO") == 0) { - info->DispPriority = 1; -@@ -2698,19 +2836,20 @@ Bool RADEONPreInit(ScrnInfoPtr pScrn, int flags) - } else if (strcmp(s, "HIGH") == 0) { - info->DispPriority = 2; - } else -- info->DispPriority = 1; -+ info->DispPriority = 1; - } - -+ if (!RADEONPreInitChipType(pScrn)) -+ goto fail; -+ - if (!RADEONPreInitInt10(pScrn, &pInt10)) - goto fail; - - RADEONPostInt10Check(pScrn, int10_save); - -- if (!RADEONPreInitChipType(pScrn)) -+ if (!RADEONPreInitBIOS(pScrn, pInt10)) - goto fail; - -- RADEONPreInitBIOS(pScrn, pInt10); -- - #ifdef XF86DRI - /* PreInit DRI first of all since we need that for getting a proper - * memory map -@@ -2739,17 +2878,22 @@ Bool RADEONPreInit(ScrnInfoPtr pScrn, int flags) - if (crtc_max_Y > 8192) - crtc_max_Y = 8192; - } else { -+ /* -+ * note that these aren't really the CRTC limits, they're just -+ * heuristics until we have a better memory manager. -+ */ - if (pScrn->videoRam <= 16384) { - crtc_max_X = 1600; - crtc_max_Y = 1200; -+ } else if (IS_R300_VARIANT) { -+ crtc_max_X = 2560; -+ crtc_max_Y = 1200; -+ } else if (IS_AVIVO_VARIANT) { -+ crtc_max_X = 2560; -+ crtc_max_Y = 1600; - } else { -- if (IS_R300_VARIANT || IS_AVIVO_VARIANT) { -- crtc_max_X = 2560; -- crtc_max_Y = 1200; -- } else { -- crtc_max_X = 2048; -- crtc_max_Y = 1200; -- } -+ crtc_max_X = 2048; -+ crtc_max_Y = 1200; - } - } - xf86DrvMsg(pScrn->scrnIndex, X_INFO, "Max desktop size set to %dx%d\n", -@@ -2793,14 +2937,16 @@ Bool RADEONPreInit(ScrnInfoPtr pScrn, int flags) - - if (!RADEONPreInitAccel(pScrn)) goto fail; - -- if (!RADEONPreInitXv(pScrn)) goto fail; -+ if (!IS_AVIVO_VARIANT) { -+ if (!RADEONPreInitXv(pScrn)) goto fail; -+ } - - if (!xf86RandR12PreInit (pScrn)) - { - xf86DrvMsg(pScrn->scrnIndex, X_ERROR, "RandR initialization failure\n"); - goto fail; -- } -- -+ } -+ - if (pScrn->modes == NULL) { - xf86DrvMsg(pScrn->scrnIndex, X_ERROR, "No modes.\n"); - goto fail; -@@ -2858,7 +3004,7 @@ static void RADEONLoadPalette(ScrnInfoPtr pScrn, int numColors, - xf86CrtcConfigPtr xf86_config = XF86_CRTC_CONFIG_PTR(pScrn); - int i; - int index, j; -- CARD16 lut_r[256], lut_g[256], lut_b[256]; -+ uint16_t lut_r[256], lut_g[256], lut_b[256]; - int c; - - #ifdef XF86DRI -@@ -3001,7 +3147,8 @@ RADEONInitBIOSRegisters(ScrnInfoPtr pScrn) - /* let the bios control the backlight */ - save->bios_2_scratch &= ~ATOM_S2_VRI_BRIGHT_ENABLE; - /* tell the bios not to handle mode switching */ -- save->bios_6_scratch |= ATOM_S6_ACC_BLOCK_DISPLAY_SWITCH; -+ save->bios_6_scratch |= (ATOM_S6_ACC_BLOCK_DISPLAY_SWITCH | -+ ATOM_S6_ACC_MODE); - - if (info->ChipFamily >= CHIP_FAMILY_R600) { - OUTREG(R600_BIOS_2_SCRATCH, save->bios_2_scratch); -@@ -3014,7 +3161,8 @@ RADEONInitBIOSRegisters(ScrnInfoPtr pScrn) - /* let the bios control the backlight */ - save->bios_0_scratch &= ~RADEON_DRIVER_BRIGHTNESS_EN; - /* tell the bios not to handle mode switching */ -- save->bios_6_scratch |= RADEON_DISPLAY_SWITCHING_DIS; -+ save->bios_6_scratch |= (RADEON_DISPLAY_SWITCHING_DIS | -+ RADEON_ACC_MODE_CHANGE); - /* tell the bios a driver is loaded */ - save->bios_7_scratch |= RADEON_DRV_LOADED; - -@@ -3032,9 +3180,7 @@ Bool RADEONScreenInit(int scrnIndex, ScreenPtr pScreen, - { - ScrnInfoPtr pScrn = xf86Screens[pScreen->myNum]; - RADEONInfoPtr info = RADEONPTR(pScrn); -- xf86CrtcConfigPtr xf86_config = XF86_CRTC_CONFIG_PTR(pScrn); - int hasDRI = 0; -- int i; - #ifdef RENDER - int subPixelOrder = SubPixelUnknown; - char* s; -@@ -3080,11 +3226,16 @@ Bool RADEONScreenInit(int scrnIndex, ScreenPtr pScreen, - RADEONBlank(pScrn); - - if (info->IsMobility && !IS_AVIVO_VARIANT) { -- if (xf86ReturnOptValBool(info->Options, OPTION_DYNAMIC_CLOCKS, FALSE)) { -+ if (xf86ReturnOptValBool(info->Options, OPTION_DYNAMIC_CLOCKS, FALSE)) { - RADEONSetDynamicClock(pScrn, 1); -- } else { -+ } else { - RADEONSetDynamicClock(pScrn, 0); -- } -+ } -+ } else if (IS_AVIVO_VARIANT) { -+ if (xf86ReturnOptValBool(info->Options, OPTION_DYNAMIC_CLOCKS, FALSE)) { -+ atombios_static_pwrmgt_setup(pScrn, 1); -+ atombios_dyn_clk_setup(pScrn, 1); -+ } - } - - if (IS_R300_VARIANT || IS_RV100_VARIANT) -@@ -3139,12 +3290,14 @@ Bool RADEONScreenInit(int scrnIndex, ScreenPtr pScreen, - RADEONInitMemoryMap(pScrn); - - /* empty the surfaces */ -- unsigned char *RADEONMMIO = info->MMIO; -- unsigned int j; -- for (j = 0; j < 8; j++) { -- OUTREG(RADEON_SURFACE0_INFO + 16 * j, 0); -- OUTREG(RADEON_SURFACE0_LOWER_BOUND + 16 * j, 0); -- OUTREG(RADEON_SURFACE0_UPPER_BOUND + 16 * j, 0); -+ { -+ unsigned char *RADEONMMIO = info->MMIO; -+ unsigned int j; -+ for (j = 0; j < 8; j++) { -+ OUTREG(RADEON_SURFACE0_INFO + 16 * j, 0); -+ OUTREG(RADEON_SURFACE0_LOWER_BOUND + 16 * j, 0); -+ OUTREG(RADEON_SURFACE0_UPPER_BOUND + 16 * j, 0); -+ } - } - - #ifdef XF86DRI -@@ -3164,9 +3317,11 @@ Bool RADEONScreenInit(int scrnIndex, ScreenPtr pScreen, - #endif - - /* Initial setup of surfaces */ -- xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG, -- "Setting up initial surfaces\n"); -- RADEONChangeSurfaces(pScrn); -+ if (info->ChipFamily < CHIP_FAMILY_R600) { -+ xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG, -+ "Setting up initial surfaces\n"); -+ RADEONChangeSurfaces(pScrn); -+ } - - /* Memory manager setup */ - -@@ -3340,28 +3495,8 @@ Bool RADEONScreenInit(int scrnIndex, ScreenPtr pScreen, - /* xf86CrtcRotate() accesses pScrn->pScreen */ - pScrn->pScreen = pScreen; - --#if 1 -- for (i = 0; i < xf86_config->num_crtc; i++) { -- xf86CrtcPtr crtc = xf86_config->crtc[i]; -- -- /* Mark that we'll need to re-set the mode for sure */ -- memset(&crtc->mode, 0, sizeof(crtc->mode)); -- if (!crtc->desiredMode.CrtcHDisplay) { -- crtc->desiredMode = *RADEONCrtcFindClosestMode (crtc, pScrn->currentMode); -- crtc->desiredRotation = RR_Rotate_0; -- crtc->desiredX = 0; -- crtc->desiredY = 0; -- } -- -- if (!xf86CrtcSetMode (crtc, &crtc->desiredMode, crtc->desiredRotation, crtc->desiredX, crtc->desiredY)) -- return FALSE; -- -- } --#else -- /* seems to do the wrong thing on some cards??? */ - if (!xf86SetDesiredModes (pScrn)) - return FALSE; --#endif - - RADEONSaveScreen(pScreen, SCREEN_SAVER_ON); - -@@ -3417,10 +3552,12 @@ Bool RADEONScreenInit(int scrnIndex, ScreenPtr pScreen, - #endif - - /* Make sure surfaces are allright since DRI setup may have changed them */ -- xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG, -- "Setting up final surfaces\n"); -+ if (info->ChipFamily < CHIP_FAMILY_R600) { -+ xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG, -+ "Setting up final surfaces\n"); - -- RADEONChangeSurfaces(pScrn); -+ RADEONChangeSurfaces(pScrn); -+ } - - - /* Enable aceleration */ -@@ -3544,7 +3681,7 @@ void RADEONRestoreMemMapRegisters(ScrnInfoPtr pScrn, - RADEONEntPtr pRADEONEnt = RADEONEntPriv(pScrn); - unsigned char *RADEONMMIO = info->MMIO; - int timeout; -- CARD32 mc_fb_loc, mc_agp_loc, mc_agp_loc_hi; -+ uint32_t mc_fb_loc, mc_agp_loc, mc_agp_loc_hi; - - radeon_read_mc_fb_agp_location(pScrn, LOC_FB | LOC_AGP, &mc_fb_loc, - &mc_agp_loc, &mc_agp_loc_hi); -@@ -3564,7 +3701,7 @@ void RADEONRestoreMemMapRegisters(ScrnInfoPtr pScrn, - - if (mc_fb_loc != restore->mc_fb_location || - mc_agp_loc != restore->mc_agp_location) { -- CARD32 tmp; -+ uint32_t tmp; - - RADEONWaitForIdleMMIO(pScrn); - -@@ -3620,8 +3757,8 @@ void RADEONRestoreMemMapRegisters(ScrnInfoPtr pScrn, - */ - if (mc_fb_loc != restore->mc_fb_location || - mc_agp_loc != restore->mc_agp_location) { -- CARD32 crtc_ext_cntl, crtc_gen_cntl, crtc2_gen_cntl=0, ov0_scale_cntl; -- CARD32 old_mc_status, status_idle; -+ uint32_t crtc_ext_cntl, crtc_gen_cntl, crtc2_gen_cntl=0, ov0_scale_cntl; -+ uint32_t old_mc_status, status_idle; - - xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG, - " Map Changed ! Applying ...\n"); -@@ -3759,16 +3896,16 @@ void RADEONRestoreMemMapRegisters(ScrnInfoPtr pScrn, - static void RADEONAdjustMemMapRegisters(ScrnInfoPtr pScrn, RADEONSavePtr save) - { - RADEONInfoPtr info = RADEONPTR(pScrn); -- CARD32 fb, agp, agp_hi; -- int changed; -+ uint32_t fb, agp, agp_hi; -+ int changed = 0; - - if (info->IsSecondary) - return; - - radeon_read_mc_fb_agp_location(pScrn, LOC_FB | LOC_AGP, &fb, &agp, &agp_hi); -- -- if (fb != info->mc_fb_location || agp != info->mc_agp_location || -- agp_hi || info->mc_agp_location_hi) -+ -+ if (fb != save->mc_fb_location || agp != save->mc_agp_location || -+ agp_hi != save->mc_agp_location_hi) - changed = 1; - - if (changed) { -@@ -3997,7 +4134,8 @@ void RADEONChangeSurfaces(ScrnInfoPtr pScrn) - } - - /* Update surface images */ -- RADEONSaveSurfaces(pScrn, info->ModeReg); -+ if (info->ChipFamily < CHIP_FAMILY_R600) -+ RADEONSaveSurfaces(pScrn, info->ModeReg); - } - - /* Read memory map */ -@@ -4039,12 +4177,13 @@ static void RADEONSavePalette(ScrnInfoPtr pScrn, RADEONSavePtr save) - } - #endif - --void -+static void - avivo_save(ScrnInfoPtr pScrn, RADEONSavePtr save) - { - RADEONInfoPtr info = RADEONPTR(pScrn); - unsigned char *RADEONMMIO = info->MMIO; - struct avivo_state *state = &save->avivo; -+ int i, j; - - // state->vga_memory_base = INREG(AVIVO_VGA_MEMORY_BASE); - // state->vga_fb_start = INREG(AVIVO_VGA_FB_START); -@@ -4053,6 +4192,7 @@ avivo_save(ScrnInfoPtr pScrn, RADEONSavePtr save) - - state->crtc_master_en = INREG(AVIVO_DC_CRTC_MASTER_EN); - state->crtc_tv_control = INREG(AVIVO_DC_CRTC_TV_CONTROL); -+ state->dc_lb_memory_split = INREG(AVIVO_DC_LB_MEMORY_SPLIT); - - state->pll1.ref_div_src = INREG(AVIVO_EXT1_PPLL_REF_DIV_SRC); - state->pll1.ref_div = INREG(AVIVO_EXT1_PPLL_REF_DIV); -@@ -4108,10 +4248,10 @@ avivo_save(ScrnInfoPtr pScrn, RADEONSavePtr save) - state->grph1.x_end = INREG(AVIVO_D1GRPH_X_END); - state->grph1.y_end = INREG(AVIVO_D1GRPH_Y_END); - -+ state->grph1.desktop_height = INREG(AVIVO_D1MODE_DESKTOP_HEIGHT); - state->grph1.viewport_start = INREG(AVIVO_D1MODE_VIEWPORT_START); - state->grph1.viewport_size = INREG(AVIVO_D1MODE_VIEWPORT_SIZE); -- state->grph1.scl_enable = INREG(AVIVO_D1SCL_SCALER_ENABLE); -- state->grph1.scl_tap_control = INREG(AVIVO_D1SCL_SCALER_TAP_CONTROL); -+ state->grph1.mode_data_format = INREG(AVIVO_D1MODE_DATA_FORMAT); - - state->crtc2.pll_source = INREG(AVIVO_PCLK_CRTC2_CNTL); - -@@ -4149,68 +4289,278 @@ avivo_save(ScrnInfoPtr pScrn, RADEONSavePtr save) - state->grph2.x_end = INREG(AVIVO_D2GRPH_X_END); - state->grph2.y_end = INREG(AVIVO_D2GRPH_Y_END); - -+ state->grph2.desktop_height = INREG(AVIVO_D2MODE_DESKTOP_HEIGHT); - state->grph2.viewport_start = INREG(AVIVO_D2MODE_VIEWPORT_START); - state->grph2.viewport_size = INREG(AVIVO_D2MODE_VIEWPORT_SIZE); -- state->grph2.scl_enable = INREG(AVIVO_D2SCL_SCALER_ENABLE); -- state->grph2.scl_tap_control = INREG(AVIVO_D2SCL_SCALER_TAP_CONTROL); -- -- state->daca.enable = INREG(AVIVO_DACA_ENABLE); -- state->daca.source_select = INREG(AVIVO_DACA_SOURCE_SELECT); -- state->daca.force_output_cntl = INREG(AVIVO_DACA_FORCE_OUTPUT_CNTL); -- state->daca.powerdown = INREG(AVIVO_DACA_POWERDOWN); -- -- state->dacb.enable = INREG(AVIVO_DACB_ENABLE); -- state->dacb.source_select = INREG(AVIVO_DACB_SOURCE_SELECT); -- state->dacb.force_output_cntl = INREG(AVIVO_DACB_FORCE_OUTPUT_CNTL); -- state->dacb.powerdown = INREG(AVIVO_DACB_POWERDOWN); -- -- state->tmds1.cntl = INREG(AVIVO_TMDSA_CNTL); -- state->tmds1.source_select = INREG(AVIVO_TMDSA_SOURCE_SELECT); -- state->tmds1.bit_depth_cntl = INREG(AVIVO_TMDSA_BIT_DEPTH_CONTROL); -- state->tmds1.data_sync = INREG(AVIVO_TMDSA_DATA_SYNCHRONIZATION); -- state->tmds1.transmitter_enable = INREG(AVIVO_TMDSA_TRANSMITTER_ENABLE); -- state->tmds1.transmitter_cntl = INREG(AVIVO_TMDSA_TRANSMITTER_CONTROL); -- -- state->tmds2.cntl = INREG(AVIVO_LVTMA_CNTL); -- state->tmds2.source_select = INREG(AVIVO_LVTMA_SOURCE_SELECT); -- state->tmds2.bit_depth_cntl = INREG(AVIVO_LVTMA_BIT_DEPTH_CONTROL); -- state->tmds2.data_sync = INREG(AVIVO_LVTMA_DATA_SYNCHRONIZATION); -+ state->grph2.mode_data_format = INREG(AVIVO_D2MODE_DATA_FORMAT); -+ -+ if (IS_DCE3_VARIANT) { -+ /* save DVOA regs */ -+ state->dvoa[0] = INREG(0x7080); -+ state->dvoa[1] = INREG(0x7084); -+ state->dvoa[2] = INREG(0x708c); -+ state->dvoa[3] = INREG(0x7090); -+ state->dvoa[4] = INREG(0x7094); -+ state->dvoa[5] = INREG(0x70ac); -+ state->dvoa[6] = INREG(0x70b0); -+ -+ j = 0; -+ /* save DAC regs */ -+ for (i = 0x7000; i <= 0x7040; i += 4) { -+ state->daca[j] = INREG(i); -+ state->dacb[j] = INREG(i + 0x100); -+ j++; -+ } -+ for (i = 0x7058; i <= 0x7060; i += 4) { -+ state->daca[j] = INREG(i); -+ state->dacb[j] = INREG(i + 0x100); -+ j++; -+ } -+ for (i = 0x7068; i <= 0x706c; i += 4) { -+ state->daca[j] = INREG(i); -+ state->dacb[j] = INREG(i + 0x100); -+ j++; -+ } -+ for (i = 0x7ef0; i <= 0x7ef8; i += 4) { -+ state->daca[j] = INREG(i); -+ state->dacb[j] = INREG(i + 0x100); -+ j++; -+ } -+ state->daca[j] = INREG(0x7050); -+ state->dacb[j] = INREG(0x7050 + 0x100); -+ -+ j = 0; -+ /* save FMT regs */ -+ for (i = 0x6700; i <= 0x6744; i += 4) { -+ state->fmt1[j] = INREG(i); -+ state->fmt2[j] = INREG(i + 0x800); -+ j++; -+ } - -- if (info->ChipFamily >= CHIP_FAMILY_R600) { -- state->tmds2.transmitter_enable = INREG(R600_LVTMA_TRANSMITTER_ENABLE); -- state->tmds2.transmitter_cntl = INREG(R600_LVTMA_TRANSMITTER_CONTROL); -- state->lvtma_pwrseq_cntl = INREG(R600_LVTMA_PWRSEQ_CNTL); -- state->lvtma_pwrseq_state = INREG(R600_LVTMA_PWRSEQ_STATE); -+ j = 0; -+ /* save DIG regs */ -+ for (i = 0x75a0; i <= 0x75e0; i += 4) { -+ state->dig1[j] = INREG(i); -+ state->dig2[j] = INREG(i + 0x400); -+ j++; -+ } -+ for (i = 0x75e8; i <= 0x75ec; i += 4) { -+ state->dig1[j] = INREG(i); -+ state->dig2[j] = INREG(i + 0x400); -+ j++; -+ } -+ -+ j = 0; -+ /* save HDMI regs */ -+ for (i = 0x7400; i <= 0x741c; i += 4) { -+ state->hdmi1[j] = INREG(i); -+ state->hdmi2[j] = INREG(i + 0x400); -+ j++; -+ } -+ for (i = 0x7430; i <= 0x74ec; i += 4) { -+ state->hdmi1[j] = INREG(i); -+ state->hdmi2[j] = INREG(i + 0x400); -+ j++; -+ } -+ state->hdmi1[j] = INREG(0x7428); -+ state->hdmi2[j] = INREG(0x7828); -+ -+ j = 0; -+ /* save AUX regs */ -+ for (i = 0x7780; i <= 0x77b4; i += 4) { -+ state->aux_cntl1[j] = INREG(i); -+ state->aux_cntl2[j] = INREG(i + 0x040); -+ state->aux_cntl3[j] = INREG(i + 0x400); -+ state->aux_cntl4[j] = INREG(i + 0x440); -+ j++; -+ } -+ -+ j = 0; -+ /* save UNIPHY regs */ -+ for (i = 0x7ec0; i <= 0x7edc; i += 4) { -+ state->uniphy1[j] = INREG(i); -+ state->uniphy2[j] = INREG(i + 0x100); -+ j++; -+ } -+ j = 0; -+ /* save PHY,LINK regs */ -+ for (i = 0x7f20; i <= 0x7f34; i += 4) { -+ state->phy[j] = INREG(i); -+ j++; -+ } -+ for (i = 0x7f9c; i <= 0x7fa4; i += 4) { -+ state->phy[j] = INREG(i); -+ j++; -+ } -+ state->phy[j] = INREG(0x7f40); -+ -+ j = 0; -+ /* save LVTMA regs */ -+ for (i = 0x7f00; i <= 0x7f1c; i += 4) { -+ state->lvtma[j] = INREG(i); -+ j++; -+ } -+ for (i = 0x7f80; i <= 0x7f98; i += 4) { -+ state->lvtma[j] = INREG(i); -+ j++; -+ } - } else { -- state->tmds2.transmitter_enable = INREG(R500_LVTMA_TRANSMITTER_ENABLE); -- state->tmds2.transmitter_cntl = INREG(R500_LVTMA_TRANSMITTER_CONTROL); -- state->lvtma_pwrseq_cntl = INREG(R500_LVTMA_PWRSEQ_CNTL); -- state->lvtma_pwrseq_state = INREG(R500_LVTMA_PWRSEQ_STATE); -+ j = 0; -+ /* save DVOA regs */ -+ for (i = 0x7980; i <= 0x79bc; i += 4) { -+ state->dvoa[j] = INREG(i); -+ j++; -+ } -+ -+ j = 0; -+ /* save DAC regs */ -+ for (i = 0x7800; i <= 0x782c; i += 4) { -+ state->daca[j] = INREG(i); -+ state->dacb[j] = INREG(i + 0x200); -+ j++; -+ } -+ for (i = 0x7834; i <= 0x7840; i += 4) { -+ state->daca[j] = INREG(i); -+ state->dacb[j] = INREG(i + 0x200); -+ j++; -+ } -+ for (i = 0x7850; i <= 0x7868; i += 4) { -+ state->daca[j] = INREG(i); -+ state->dacb[j] = INREG(i + 0x200); -+ j++; -+ } -+ -+ j = 0; -+ /* save TMDSA regs */ -+ for (i = 0x7880; i <= 0x78e0; i += 4) { -+ state->tmdsa[j] = INREG(i); -+ j++; -+ } -+ for (i = 0x7904; i <= 0x7918; i += 4) { -+ state->tmdsa[j] = INREG(i); -+ j++; -+ } -+ -+ j = 0; -+ /* save LVTMA regs */ -+ for (i = 0x7a80; i <= 0x7b18; i += 4) { -+ state->lvtma[j] = INREG(i); -+ j++; -+ } -+ -+ if ((info->ChipFamily == CHIP_FAMILY_RS600) || -+ (info->ChipFamily == CHIP_FAMILY_RS690) || -+ (info->ChipFamily == CHIP_FAMILY_RS740)) { -+ j = 0; -+ /* save DDIA regs */ -+ for (i = 0x7200; i <= 0x7290; i += 4) { -+ state->ddia[j] = INREG(i); -+ j++; -+ } -+ } - } - -+ /* scalers */ -+ j = 0; -+ for (i = 0x6578; i <= 0x65e4; i += 4) { -+ state->d1scl[j] = INREG(i); -+ state->d2scl[j] = INREG(i + 0x800); -+ j++; -+ } -+ for (i = 0x6600; i <= 0x662c; i += 4) { -+ state->d1scl[j] = INREG(i); -+ state->d2scl[j] = INREG(i + 0x800); -+ j++; -+ } -+ j = 0; -+ for (i = 0x66e8; i <= 0x66fc; i += 4) { -+ state->dxscl[j] = INREG(i); -+ j++; -+ } -+ state->dxscl[6] = INREG(0x6e30); -+ state->dxscl[7] = INREG(0x6e34); -+ - if (state->crtc1.control & AVIVO_CRTC_EN) - info->crtc_on = TRUE; -- -+ - if (state->crtc2.control & AVIVO_CRTC_EN) - info->crtc2_on = TRUE; - - } - --void -+static void - avivo_restore(ScrnInfoPtr pScrn, RADEONSavePtr restore) - { - RADEONInfoPtr info = RADEONPTR(pScrn); - unsigned char *RADEONMMIO = info->MMIO; - struct avivo_state *state = &restore->avivo; -+ int i, j; -+ -+ xf86DrvMsg(pScrn->scrnIndex, X_INFO, "avivo_restore !\n"); -+ -+ /* Disable VGA control for now.. maybe needs to be changed */ -+ OUTREG(AVIVO_D1VGA_CONTROL, 0); -+ OUTREG(AVIVO_D2VGA_CONTROL, 0); -+ -+ /* Disable CRTCs */ -+ OUTREG(AVIVO_D1CRTC_CONTROL, -+ (INREG(AVIVO_D1CRTC_CONTROL) & ~0x300) | 0x01000000); -+ OUTREG(AVIVO_D2CRTC_CONTROL, -+ (INREG(AVIVO_D2CRTC_CONTROL) & ~0x300) | 0x01000000); -+ OUTREG(AVIVO_D1CRTC_CONTROL, -+ INREG(AVIVO_D1CRTC_CONTROL) & ~0x1); -+ OUTREG(AVIVO_D2CRTC_CONTROL, -+ INREG(AVIVO_D2CRTC_CONTROL) & ~0x1); -+ OUTREG(AVIVO_D1CRTC_CONTROL, -+ INREG(AVIVO_D1CRTC_CONTROL) | 0x100); -+ OUTREG(AVIVO_D2CRTC_CONTROL, -+ INREG(AVIVO_D2CRTC_CONTROL) | 0x100); -+ -+ /* Lock graph registers */ -+ OUTREG(AVIVO_D1GRPH_UPDATE, AVIVO_D1GRPH_UPDATE_LOCK); -+ OUTREG(AVIVO_D1GRPH_PRIMARY_SURFACE_ADDRESS, state->grph1.prim_surf_addr); -+ OUTREG(AVIVO_D1GRPH_SECONDARY_SURFACE_ADDRESS, state->grph1.sec_surf_addr); -+ OUTREG(AVIVO_D1GRPH_CONTROL, state->grph1.control); -+ OUTREG(AVIVO_D1GRPH_SURFACE_OFFSET_X, state->grph1.x_offset); -+ OUTREG(AVIVO_D1GRPH_SURFACE_OFFSET_Y, state->grph1.y_offset); -+ OUTREG(AVIVO_D1GRPH_X_START, state->grph1.x_start); -+ OUTREG(AVIVO_D1GRPH_Y_START, state->grph1.y_start); -+ OUTREG(AVIVO_D1GRPH_X_END, state->grph1.x_end); -+ OUTREG(AVIVO_D1GRPH_Y_END, state->grph1.y_end); -+ OUTREG(AVIVO_D1GRPH_PITCH, state->grph1.pitch); -+ OUTREG(AVIVO_D1GRPH_ENABLE, state->grph1.enable); -+ OUTREG(AVIVO_D1GRPH_UPDATE, 0); - -- // OUTMC(pScrn, AVIVO_MC_MEMORY_MAP, state->mc_memory_map); -- // OUTREG(AVIVO_VGA_MEMORY_BASE, state->vga_memory_base); -- // OUTREG(AVIVO_VGA_FB_START, state->vga_fb_start); -+ OUTREG(AVIVO_D2GRPH_UPDATE, AVIVO_D1GRPH_UPDATE_LOCK); -+ OUTREG(AVIVO_D2GRPH_PRIMARY_SURFACE_ADDRESS, state->grph2.prim_surf_addr); -+ OUTREG(AVIVO_D2GRPH_SECONDARY_SURFACE_ADDRESS, state->grph2.sec_surf_addr); -+ OUTREG(AVIVO_D2GRPH_CONTROL, state->grph2.control); -+ OUTREG(AVIVO_D2GRPH_SURFACE_OFFSET_X, state->grph2.x_offset); -+ OUTREG(AVIVO_D2GRPH_SURFACE_OFFSET_Y, state->grph2.y_offset); -+ OUTREG(AVIVO_D2GRPH_X_START, state->grph2.x_start); -+ OUTREG(AVIVO_D2GRPH_Y_START, state->grph2.y_start); -+ OUTREG(AVIVO_D2GRPH_X_END, state->grph2.x_end); -+ OUTREG(AVIVO_D2GRPH_Y_END, state->grph2.y_end); -+ OUTREG(AVIVO_D2GRPH_PITCH, state->grph2.pitch); -+ OUTREG(AVIVO_D2GRPH_ENABLE, state->grph2.enable); -+ OUTREG(AVIVO_D2GRPH_UPDATE, 0); - -+ /* Whack some mode regs too */ -+ OUTREG(AVIVO_D1SCL_UPDATE, AVIVO_D1SCL_UPDATE_LOCK); -+ OUTREG(AVIVO_D1MODE_DESKTOP_HEIGHT, state->grph1.desktop_height); -+ OUTREG(AVIVO_D1MODE_VIEWPORT_START, state->grph1.viewport_start); -+ OUTREG(AVIVO_D1MODE_VIEWPORT_SIZE, state->grph1.viewport_size); -+ OUTREG(AVIVO_D1MODE_DATA_FORMAT, state->grph1.mode_data_format); -+ OUTREG(AVIVO_D1SCL_UPDATE, 0); - -- OUTREG(AVIVO_DC_CRTC_MASTER_EN, state->crtc_master_en); -- OUTREG(AVIVO_DC_CRTC_TV_CONTROL, state->crtc_tv_control); -+ OUTREG(AVIVO_D2SCL_UPDATE, AVIVO_D1SCL_UPDATE_LOCK); -+ OUTREG(AVIVO_D2MODE_DESKTOP_HEIGHT, state->grph2.desktop_height); -+ OUTREG(AVIVO_D2MODE_VIEWPORT_START, state->grph2.viewport_start); -+ OUTREG(AVIVO_D2MODE_VIEWPORT_SIZE, state->grph2.viewport_size); -+ OUTREG(AVIVO_D2MODE_DATA_FORMAT, state->grph2.mode_data_format); -+ OUTREG(AVIVO_D2SCL_UPDATE, 0); - -+ /* Set the PLL */ - OUTREG(AVIVO_EXT1_PPLL_REF_DIV_SRC, state->pll1.ref_div_src); - OUTREG(AVIVO_EXT1_PPLL_REF_DIV, state->pll1.ref_div); - OUTREG(AVIVO_EXT1_PPLL_FB_DIV, state->pll1.fb_div); -@@ -4230,7 +4580,9 @@ avivo_restore(ScrnInfoPtr pScrn, RADEONSavePtr restore) - OUTREG(AVIVO_P2PLL_INT_SS_CNTL, state->pll2.int_ss_cntl); - - OUTREG(AVIVO_PCLK_CRTC1_CNTL, state->crtc1.pll_source); -+ OUTREG(AVIVO_PCLK_CRTC2_CNTL, state->crtc2.pll_source); - -+ /* Set the CRTC */ - OUTREG(AVIVO_D1CRTC_H_TOTAL, state->crtc1.h_total); - OUTREG(AVIVO_D1CRTC_H_BLANK_START_END, state->crtc1.h_blank_start_end); - OUTREG(AVIVO_D1CRTC_H_SYNC_A, state->crtc1.h_sync_a); -@@ -4245,31 +4597,12 @@ avivo_restore(ScrnInfoPtr pScrn, RADEONSavePtr restore) - OUTREG(AVIVO_D1CRTC_V_SYNC_B, state->crtc1.v_sync_b); - OUTREG(AVIVO_D1CRTC_V_SYNC_B_CNTL, state->crtc1.v_sync_b_cntl); - -- OUTREG(AVIVO_D1CRTC_CONTROL, state->crtc1.control); -- OUTREG(AVIVO_D1CRTC_BLANK_CONTROL, state->crtc1.blank_control); - OUTREG(AVIVO_D1CRTC_INTERLACE_CONTROL, state->crtc1.interlace_control); - OUTREG(AVIVO_D1CRTC_STEREO_CONTROL, state->crtc1.stereo_control); - - OUTREG(AVIVO_D1CUR_CONTROL, state->crtc1.cursor_control); - -- OUTREG(AVIVO_D1GRPH_ENABLE, state->grph1.enable); -- OUTREG(AVIVO_D1GRPH_CONTROL, state->grph1.control); -- OUTREG(AVIVO_D1GRPH_PRIMARY_SURFACE_ADDRESS, state->grph1.prim_surf_addr); -- OUTREG(AVIVO_D1GRPH_SECONDARY_SURFACE_ADDRESS, state->grph1.sec_surf_addr); -- OUTREG(AVIVO_D1GRPH_PITCH, state->grph1.pitch); -- OUTREG(AVIVO_D1GRPH_SURFACE_OFFSET_X, state->grph1.x_offset); -- OUTREG(AVIVO_D1GRPH_SURFACE_OFFSET_Y, state->grph1.y_offset); -- OUTREG(AVIVO_D1GRPH_X_START, state->grph1.x_start); -- OUTREG(AVIVO_D1GRPH_Y_START, state->grph1.y_start); -- OUTREG(AVIVO_D1GRPH_X_END, state->grph1.x_end); -- OUTREG(AVIVO_D1GRPH_Y_END, state->grph1.y_end); -- -- OUTREG(AVIVO_D1MODE_VIEWPORT_START, state->grph1.viewport_start); -- OUTREG(AVIVO_D1MODE_VIEWPORT_SIZE, state->grph1.viewport_size); -- OUTREG(AVIVO_D1SCL_SCALER_ENABLE, state->grph1.scl_enable); -- OUTREG(AVIVO_D1SCL_SCALER_TAP_CONTROL, state->grph1.scl_tap_control); -- -- OUTREG(AVIVO_PCLK_CRTC2_CNTL, state->crtc2.pll_source); -+ /* XXX Fix scaler */ - - OUTREG(AVIVO_D2CRTC_H_TOTAL, state->crtc2.h_total); - OUTREG(AVIVO_D2CRTC_H_BLANK_START_END, state->crtc2.h_blank_start_end); -@@ -4285,70 +4618,226 @@ avivo_restore(ScrnInfoPtr pScrn, RADEONSavePtr restore) - OUTREG(AVIVO_D2CRTC_V_SYNC_B, state->crtc2.v_sync_b); - OUTREG(AVIVO_D2CRTC_V_SYNC_B_CNTL, state->crtc2.v_sync_b_cntl); - -- OUTREG(AVIVO_D2CRTC_CONTROL, state->crtc2.control); -- OUTREG(AVIVO_D2CRTC_BLANK_CONTROL, state->crtc2.blank_control); - OUTREG(AVIVO_D2CRTC_INTERLACE_CONTROL, state->crtc2.interlace_control); - OUTREG(AVIVO_D2CRTC_STEREO_CONTROL, state->crtc2.stereo_control); - - OUTREG(AVIVO_D2CUR_CONTROL, state->crtc2.cursor_control); - -- OUTREG(AVIVO_D2GRPH_ENABLE, state->grph2.enable); -- OUTREG(AVIVO_D2GRPH_CONTROL, state->grph2.control); -- OUTREG(AVIVO_D2GRPH_PRIMARY_SURFACE_ADDRESS, state->grph2.prim_surf_addr); -- OUTREG(AVIVO_D2GRPH_SECONDARY_SURFACE_ADDRESS, state->grph2.sec_surf_addr); -- OUTREG(AVIVO_D2GRPH_PITCH, state->grph2.pitch); -- OUTREG(AVIVO_D2GRPH_SURFACE_OFFSET_X, state->grph2.x_offset); -- OUTREG(AVIVO_D2GRPH_SURFACE_OFFSET_Y, state->grph2.y_offset); -- OUTREG(AVIVO_D2GRPH_X_START, state->grph2.x_start); -- OUTREG(AVIVO_D2GRPH_Y_START, state->grph2.y_start); -- OUTREG(AVIVO_D2GRPH_X_END, state->grph2.x_end); -- OUTREG(AVIVO_D2GRPH_Y_END, state->grph2.y_end); -+ if (IS_DCE3_VARIANT) { -+ /* DVOA regs */ -+ OUTREG(0x7080, state->dvoa[0]); -+ OUTREG(0x7084, state->dvoa[1]); -+ OUTREG(0x708c, state->dvoa[2]); -+ OUTREG(0x7090, state->dvoa[3]); -+ OUTREG(0x7094, state->dvoa[4]); -+ OUTREG(0x70ac, state->dvoa[5]); -+ OUTREG(0x70b0, state->dvoa[6]); -+ -+ j = 0; -+ /* DAC regs */ -+ for (i = 0x7000; i <= 0x7040; i += 4) { -+ OUTREG(i, state->daca[j]); -+ OUTREG((i + 0x100), state->dacb[j]); -+ j++; -+ } -+ for (i = 0x7058; i <= 0x7060; i += 4) { -+ OUTREG(i, state->daca[j]); -+ OUTREG((i + 0x100), state->dacb[j]); -+ j++; -+ } -+ for (i = 0x7068; i <= 0x706c; i += 4) { -+ OUTREG(i, state->daca[j]); -+ OUTREG((i + 0x100), state->dacb[j]); -+ j++; -+ } -+ for (i = 0x7ef0; i <= 0x7ef8; i += 4) { -+ OUTREG(i, state->daca[j]); -+ OUTREG((i + 0x100), state->dacb[j]); -+ j++; -+ } -+ OUTREG(0x7050, state->daca[j]); -+ OUTREG((0x7050 + 0x100), state->dacb[j]); -+ -+ j = 0; -+ /* FMT regs */ -+ for (i = 0x6700; i <= 0x6744; i += 4) { -+ OUTREG(i, state->fmt1[j]); -+ OUTREG((i + 0x800), state->fmt2[j]); -+ j++; -+ } - -- OUTREG(AVIVO_D2MODE_VIEWPORT_START, state->grph2.viewport_start); -- OUTREG(AVIVO_D2MODE_VIEWPORT_SIZE, state->grph2.viewport_size); -- OUTREG(AVIVO_D2SCL_SCALER_ENABLE, state->grph2.scl_enable); -- OUTREG(AVIVO_D2SCL_SCALER_TAP_CONTROL, state->grph2.scl_tap_control); -- -- OUTREG(AVIVO_DACA_ENABLE, state->daca.enable); -- OUTREG(AVIVO_DACA_SOURCE_SELECT, state->daca.source_select); -- OUTREG(AVIVO_DACA_FORCE_OUTPUT_CNTL, state->daca.force_output_cntl); -- OUTREG(AVIVO_DACA_POWERDOWN, state->daca.powerdown); -- -- OUTREG(AVIVO_TMDSA_CNTL, state->tmds1.cntl); -- OUTREG(AVIVO_TMDSA_BIT_DEPTH_CONTROL, state->tmds1.bit_depth_cntl); -- OUTREG(AVIVO_TMDSA_DATA_SYNCHRONIZATION, state->tmds1.data_sync); -- OUTREG(AVIVO_TMDSA_TRANSMITTER_ENABLE, state->tmds1.transmitter_enable); -- OUTREG(AVIVO_TMDSA_TRANSMITTER_CONTROL, state->tmds1.transmitter_cntl); -- OUTREG(AVIVO_TMDSA_SOURCE_SELECT, state->tmds1.source_select); -- -- OUTREG(AVIVO_DACB_ENABLE, state->dacb.enable); -- OUTREG(AVIVO_DACB_SOURCE_SELECT, state->dacb.source_select); -- OUTREG(AVIVO_DACB_FORCE_OUTPUT_CNTL, state->dacb.force_output_cntl); -- OUTREG(AVIVO_DACB_POWERDOWN, state->dacb.powerdown); -- -- OUTREG(AVIVO_LVTMA_CNTL, state->tmds2.cntl); -- OUTREG(AVIVO_LVTMA_BIT_DEPTH_CONTROL, state->tmds2.bit_depth_cntl); -- OUTREG(AVIVO_LVTMA_DATA_SYNCHRONIZATION, state->tmds2.data_sync); -- OUTREG(AVIVO_LVTMA_SOURCE_SELECT, state->tmds2.source_select); -+ j = 0; -+ /* DIG regs */ -+ for (i = 0x75a0; i <= 0x75e0; i += 4) { -+ OUTREG(i, state->dig1[j]); -+ OUTREG((i + 0x400), state->dig2[j]); -+ j++; -+ } -+ for (i = 0x75e8; i <= 0x75ec; i += 4) { -+ OUTREG(i, state->dig1[j]); -+ OUTREG((i + 0x400), state->dig2[j]); -+ j++; -+ } - -- if (info->ChipFamily >= CHIP_FAMILY_R600) { -- OUTREG(R600_LVTMA_TRANSMITTER_ENABLE, state->tmds2.transmitter_enable); -- OUTREG(R600_LVTMA_TRANSMITTER_CONTROL, state->tmds2.transmitter_cntl); -- OUTREG(R600_LVTMA_PWRSEQ_CNTL, state->lvtma_pwrseq_cntl); -- OUTREG(R600_LVTMA_PWRSEQ_STATE, state->lvtma_pwrseq_state); -+ j = 0; -+ /* HDMI regs */ -+ for (i = 0x7400; i <= 0x741c; i += 4) { -+ OUTREG(i, state->hdmi1[j]); -+ OUTREG((i + 0x400), state->hdmi2[j]); -+ j++; -+ } -+ for (i = 0x7430; i <= 0x74ec; i += 4) { -+ OUTREG(i, state->hdmi1[j]); -+ OUTREG((i + 0x400), state->hdmi2[j]); -+ j++; -+ } -+ OUTREG(0x7428, state->hdmi1[j]); -+ OUTREG((0x7428 + 0x400), state->hdmi2[j]); -+ -+ j = 0; -+ /* save AUX regs */ -+ for (i = 0x7780; i <= 0x77b4; i += 4) { -+ OUTREG(i, state->aux_cntl1[j]); -+ OUTREG((i + 0x040), state->aux_cntl2[j]); -+ OUTREG((i + 0x400), state->aux_cntl3[j]); -+ OUTREG((i + 0x440), state->aux_cntl4[j]); -+ j++; -+ } -+ -+ j = 0; -+ /* save UNIPHY regs */ -+ for (i = 0x7ec0; i <= 0x7edc; i += 4) { -+ OUTREG(i, state->uniphy1[j]); -+ OUTREG((i + 0x100), state->uniphy2[j]); -+ j++; -+ } -+ j = 0; -+ /* save PHY,LINK regs */ -+ for (i = 0x7f20; i <= 0x7f34; i += 4) { -+ OUTREG(i, state->phy[j]); -+ j++; -+ } -+ for (i = 0x7f9c; i <= 0x7fa4; i += 4) { -+ OUTREG(i, state->phy[j]); -+ j++; -+ } -+ state->phy[j] = INREG(0x7f40); -+ -+ j = 0; -+ /* save LVTMA regs */ -+ for (i = 0x7f00; i <= 0x7f1c; i += 4) { -+ OUTREG(i, state->lvtma[j]); -+ j++; -+ } -+ for (i = 0x7f80; i <= 0x7f98; i += 4) { -+ OUTREG(i, state->lvtma[j]); -+ j++; -+ } - } else { -- OUTREG(R500_LVTMA_TRANSMITTER_ENABLE, state->tmds2.transmitter_enable); -- OUTREG(R500_LVTMA_TRANSMITTER_CONTROL, state->tmds2.transmitter_cntl); -- OUTREG(R500_LVTMA_PWRSEQ_CNTL, state->lvtma_pwrseq_cntl); -- OUTREG(R500_LVTMA_PWRSEQ_STATE, state->lvtma_pwrseq_state); -+ j = 0; -+ /* DVOA regs */ -+ for (i = 0x7980; i <= 0x79bc; i += 4) { -+ OUTREG(i, state->dvoa[j]); -+ j++; -+ } -+ -+ j = 0; -+ /* DAC regs */ /* -- MIGHT NEED ORDERING FIX & DELAYS -- */ -+ for (i = 0x7800; i <= 0x782c; i += 4) { -+ OUTREG(i, state->daca[j]); -+ OUTREG((i + 0x200), state->dacb[j]); -+ j++; -+ } -+ for (i = 0x7834; i <= 0x7840; i += 4) { -+ OUTREG(i, state->daca[j]); -+ OUTREG((i + 0x200), state->dacb[j]); -+ j++; -+ } -+ for (i = 0x7850; i <= 0x7868; i += 4) { -+ OUTREG(i, state->daca[j]); -+ OUTREG((i + 0x200), state->dacb[j]); -+ j++; -+ } -+ -+ j = 0; -+ /* TMDSA regs */ -+ for (i = 0x7880; i <= 0x78e0; i += 4) { -+ OUTREG(i, state->tmdsa[j]); -+ j++; -+ } -+ for (i = 0x7904; i <= 0x7918; i += 4) { -+ OUTREG(i, state->tmdsa[j]); -+ j++; -+ } -+ -+ j = 0; -+ /* LVTMA regs */ -+ for (i = 0x7a80; i <= 0x7b18; i += 4) { -+ OUTREG(i, state->lvtma[j]); -+ j++; -+ } -+ -+ /* DDIA regs */ -+ if ((info->ChipFamily == CHIP_FAMILY_RS600) || -+ (info->ChipFamily == CHIP_FAMILY_RS690) || -+ (info->ChipFamily == CHIP_FAMILY_RS740)) { -+ j = 0; -+ for (i = 0x7200; i <= 0x7290; i += 4) { -+ OUTREG(i, state->ddia[j]); -+ j++; -+ } -+ } -+ } -+ -+ /* scalers */ -+ j = 0; -+ for (i = 0x6578; i <= 0x65e4; i += 4) { -+ OUTREG(i, state->d1scl[j]); -+ OUTREG((i + 0x800), state->d2scl[j]); -+ j++; -+ } -+ for (i = 0x6600; i <= 0x662c; i += 4) { -+ OUTREG(i, state->d1scl[j]); -+ OUTREG((i + 0x800), state->d2scl[j]); -+ j++; -+ } -+ j = 0; -+ for (i = 0x66e8; i <= 0x66fc; i += 4) { -+ OUTREG(i, state->dxscl[j]); -+ j++; - } -+ OUTREG(0x6e30, state->dxscl[6]); -+ OUTREG(0x6e34, state->dxscl[7]); - -+ /* Enable CRTCs */ -+ if (state->crtc1.control & 1) { -+ OUTREG(AVIVO_D1CRTC_CONTROL, 0x01000101); -+ INREG(AVIVO_D1CRTC_CONTROL); -+ OUTREG(AVIVO_D1CRTC_CONTROL, 0x00010101); -+ } -+ if (state->crtc2.control & 1) { -+ OUTREG(AVIVO_D2CRTC_CONTROL, 0x01000101); -+ INREG(AVIVO_D2CRTC_CONTROL); -+ OUTREG(AVIVO_D2CRTC_CONTROL, 0x00010101); -+ } -+ -+ /* Where should that go ? */ -+ OUTREG(AVIVO_DC_CRTC_TV_CONTROL, state->crtc_tv_control); -+ OUTREG(AVIVO_DC_LB_MEMORY_SPLIT, state->dc_lb_memory_split); -+ -+ /* Need fixing too ? */ -+ OUTREG(AVIVO_D1CRTC_BLANK_CONTROL, state->crtc1.blank_control); -+ OUTREG(AVIVO_D2CRTC_BLANK_CONTROL, state->crtc2.blank_control); -+ -+ /* Dbl check */ - OUTREG(AVIVO_D1VGA_CONTROL, state->vga1_cntl); - OUTREG(AVIVO_D2VGA_CONTROL, state->vga2_cntl); -+ -+ /* Should only enable outputs here */ - } - --void avivo_restore_vga_regs(ScrnInfoPtr pScrn, RADEONSavePtr restore) --{ -+static void avivo_restore_vga_regs(ScrnInfoPtr pScrn, RADEONSavePtr restore) -+{ - RADEONInfoPtr info = RADEONPTR(pScrn); - unsigned char *RADEONMMIO = info->MMIO; - struct avivo_state *state = &restore->avivo; -@@ -4434,6 +4923,9 @@ static void RADEONSave(ScrnInfoPtr pScrn) - * setup in the card at all !! - */ - vgaHWSave(pScrn, &hwp->SavedReg, VGA_SR_MODE); /* Save mode only */ -+# elif defined(__linux__) -+ /* Save only mode * & fonts */ -+ vgaHWSave(pScrn, &hwp->SavedReg, VGA_SR_MODE | VGA_SR_FONTS ); - # else - /* Save mode * & fonts & cmap */ - vgaHWSave(pScrn, &hwp->SavedReg, VGA_SR_ALL); -@@ -4466,12 +4958,13 @@ static void RADEONSave(ScrnInfoPtr pScrn) - } - - RADEONSaveBIOSRegisters(pScrn, save); -- RADEONSaveSurfaces(pScrn, save); -+ if (info->ChipFamily < CHIP_FAMILY_R600) -+ RADEONSaveSurfaces(pScrn, save); - - } - - /* Restore the original (text) mode */ --void RADEONRestore(ScrnInfoPtr pScrn) -+static void RADEONRestore(ScrnInfoPtr pScrn) - { - RADEONInfoPtr info = RADEONPTR(pScrn); - RADEONEntPtr pRADEONEnt = RADEONEntPriv(pScrn); -@@ -4522,9 +5015,9 @@ void RADEONRestore(ScrnInfoPtr pScrn) - } - - RADEONRestoreBIOSRegisters(pScrn, restore); -- RADEONRestoreSurfaces(pScrn, restore); - } - -+ - #if 1 - /* Temp fix to "solve" VT switch problems. When switching VTs on - * some systems, the console can either hang or the fonts can be -@@ -4534,6 +5027,9 @@ void RADEONRestore(ScrnInfoPtr pScrn) - usleep(100000); - #endif - -+ if (info->ChipFamily < CHIP_FAMILY_R600) -+ RADEONRestoreSurfaces(pScrn, restore); -+ - /* need to make sure we don't enable a crtc by accident or we may get a hang */ - if (pRADEONEnt->HasCRTC2 && !info->IsSecondary) { - if (info->crtc2_on && xf86_config->num_crtc > 1) { -@@ -4555,7 +5051,9 @@ void RADEONRestore(ScrnInfoPtr pScrn) - * write VGA fonts, will find a better solution in the future - */ - vgaHWRestore(pScrn, &hwp->SavedReg, VGA_SR_MODE ); --# else -+# elif defined(__linux__) -+ vgaHWRestore(pScrn, &hwp->SavedReg, VGA_SR_MODE | VGA_SR_FONTS ); -+# else - vgaHWRestore(pScrn, &hwp->SavedReg, VGA_SR_ALL ); - # endif - vgaHWLock(hwp); -@@ -4567,7 +5065,9 @@ void RADEONRestore(ScrnInfoPtr pScrn) - */ - if (IS_AVIVO_VARIANT) - avivo_restore_vga_regs(pScrn, restore); -- RADEONRestoreDACRegisters(pScrn, restore); -+ -+ if (!IS_AVIVO_VARIANT) -+ RADEONRestoreDACRegisters(pScrn, restore); - - #if 0 - RADEONWaitForVerticalSync(pScrn); -@@ -4885,63 +5385,73 @@ Bool RADEONEnterVT(int scrnIndex, int flags) - ScrnInfoPtr pScrn = xf86Screens[scrnIndex]; - RADEONInfoPtr info = RADEONPTR(pScrn); - unsigned char *RADEONMMIO = info->MMIO; -- xf86CrtcConfigPtr xf86_config = XF86_CRTC_CONFIG_PTR(pScrn); -+ uint32_t mem_size; -+ xf86CrtcConfigPtr config = XF86_CRTC_CONFIG_PTR(pScrn); - int i; - - xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG, - "RADEONEnterVT\n"); - -- if ((INREG(RADEON_CONFIG_MEMSIZE)) == 0) { /* Softboot V_BIOS */ -- xf86Int10InfoPtr pInt; -- xf86DrvMsg(pScrn->scrnIndex, X_WARNING, -- "zero MEMSIZE, probably at D3cold. Re-POSTing via int10.\n"); -- pInt = xf86InitInt10 (info->pEnt->index); -- if (pInt) { -- pInt->num = 0xe6; -- xf86ExecX86int10 (pInt); -- xf86FreeInt10 (pInt); -- } -+ if (info->ChipFamily >= CHIP_FAMILY_R600) -+ mem_size = INREG(R600_CONFIG_MEMSIZE); -+ else -+ mem_size = INREG(RADEON_CONFIG_MEMSIZE); -+ -+ if (mem_size == 0) { /* Softboot V_BIOS */ -+ if (info->IsAtomBios) { -+ rhdAtomASICInit(info->atomBIOS); -+ } else { -+ xf86Int10InfoPtr pInt; -+ xf86DrvMsg(pScrn->scrnIndex, X_WARNING, -+ "zero MEMSIZE, probably at D3cold. Re-POSTing via int10.\n"); -+ pInt = xf86InitInt10 (info->pEnt->index); -+ if (pInt) { -+ pInt->num = 0xe6; -+ xf86ExecX86int10 (pInt); -+ xf86FreeInt10 (pInt); -+ } else { -+ RADEONGetBIOSInitTableOffsets(pScrn); -+ RADEONPostCardFromBIOSTables(pScrn); -+ } -+ } - } - - /* Makes sure the engine is idle before doing anything */ - RADEONWaitForIdleMMIO(pScrn); - - if (info->IsMobility && !IS_AVIVO_VARIANT) { -- if (xf86ReturnOptValBool(info->Options, OPTION_DYNAMIC_CLOCKS, FALSE)) { -+ if (xf86ReturnOptValBool(info->Options, OPTION_DYNAMIC_CLOCKS, FALSE)) { - RADEONSetDynamicClock(pScrn, 1); -- } else { -+ } else { - RADEONSetDynamicClock(pScrn, 0); -- } -+ } -+ } else if (IS_AVIVO_VARIANT) { -+ if (xf86ReturnOptValBool(info->Options, OPTION_DYNAMIC_CLOCKS, FALSE)) { -+ atombios_static_pwrmgt_setup(pScrn, 1); -+ atombios_dyn_clk_setup(pScrn, 1); -+ } - } - - if (IS_R300_VARIANT || IS_RV100_VARIANT) - RADEONForceSomeClocks(pScrn); - -- pScrn->vtSema = TRUE; -- for (i = 0; i < xf86_config->num_crtc; i++) { -- xf86CrtcPtr crtc = xf86_config->crtc[i]; -- /* Mark that we'll need to re-set the mode for sure */ -- memset(&crtc->mode, 0, sizeof(crtc->mode)); -- if (!crtc->desiredMode.CrtcHDisplay) { -- crtc->desiredMode = *RADEONCrtcFindClosestMode (crtc, pScrn->currentMode); -- crtc->desiredRotation = RR_Rotate_0; -- crtc->desiredX = 0; -- crtc->desiredY = 0; -- } -+ for (i = 0; i < config->num_crtc; i++) -+ radeon_crtc_modeset_ioctl(config->crtc[i], TRUE); - -- if (!xf86CrtcSetMode (crtc, &crtc->desiredMode, crtc->desiredRotation, -- crtc->desiredX, crtc->desiredY)) -- return FALSE; -+ pScrn->vtSema = TRUE; - -- } -+ if (!xf86SetDesiredModes(pScrn)) -+ return FALSE; - -- RADEONRestoreSurfaces(pScrn, info->ModeReg); -+ if (info->ChipFamily < CHIP_FAMILY_R600) -+ RADEONRestoreSurfaces(pScrn, info->ModeReg); - #ifdef XF86DRI - if (info->directRenderingEnabled) { -- if (info->cardType == CARD_PCIE && info->pKernelDRMVersion->version_minor >= 19 && info->FbSecureSize) -- { -- /* we need to backup the PCIE GART TABLE from fb memory */ -- memcpy(info->FB + info->pciGartOffset, info->pciGartBackup, info->pciGartSize); -+ if (info->cardType == CARD_PCIE && -+ info->pKernelDRMVersion->version_minor >= 19 && -+ info->FbSecureSize) { -+ /* we need to backup the PCIE GART TABLE from fb memory */ -+ memcpy(info->FB + info->pciGartOffset, info->pciGartBackup, info->pciGartSize); - } - - /* get the DRI back into shape after resume */ -@@ -4966,8 +5476,6 @@ Bool RADEONEnterVT(int scrnIndex, int flags) - } - #endif - -- // pScrn->AdjustFrame(scrnIndex, pScrn->frameX0, pScrn->frameY0, 0); -- - return TRUE; - } - -@@ -4978,6 +5486,8 @@ void RADEONLeaveVT(int scrnIndex, int flags) - { - ScrnInfoPtr pScrn = xf86Screens[scrnIndex]; - RADEONInfoPtr info = RADEONPTR(pScrn); -+ xf86CrtcConfigPtr config = XF86_CRTC_CONFIG_PTR(pScrn); -+ int i; - - xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG, - "RADEONLeaveVT\n"); -@@ -4988,8 +5498,9 @@ void RADEONLeaveVT(int scrnIndex, int flags) - DRILock(pScrn->pScreen, 0); - RADEONCP_STOP(pScrn, info); - -- if (info->cardType == CARD_PCIE && info->pKernelDRMVersion->version_minor >= 19 && info->FbSecureSize) -- { -+ if (info->cardType == CARD_PCIE && -+ info->pKernelDRMVersion->version_minor >= 19 && -+ info->FbSecureSize) { - /* we need to backup the PCIE GART TABLE from fb memory */ - memcpy(info->pciGartBackup, (info->FB + info->pciGartOffset), info->pciGartSize); - } -@@ -4999,7 +5510,9 @@ void RADEONLeaveVT(int scrnIndex, int flags) - RADEONSAREAPrivPtr pSAREAPriv = - (RADEONSAREAPrivPtr)DRIGetSAREAPrivate(pScrn->pScreen); - drmTextureRegionPtr list = pSAREAPriv->texList[0]; -- int age = ++pSAREAPriv->texAge[0], i = 0; -+ int age = ++pSAREAPriv->texAge[0]; -+ -+ i = 0; - - do { - list[i].age = age; -@@ -5009,8 +5522,28 @@ void RADEONLeaveVT(int scrnIndex, int flags) - } - #endif - -+#ifndef HAVE_FREE_SHADOW -+ for (i = 0; i < config->num_crtc; i++) { -+ xf86CrtcPtr crtc = config->crtc[i]; -+ -+ if (crtc->rotatedPixmap || crtc->rotatedData) { -+ crtc->funcs->shadow_destroy(crtc, crtc->rotatedPixmap, -+ crtc->rotatedData); -+ crtc->rotatedPixmap = NULL; -+ crtc->rotatedData = NULL; -+ } -+ } -+#else -+ xf86RotateFreeShadow(pScrn); -+#endif -+ -+ xf86_hide_cursors (pScrn); -+ - RADEONRestore(pScrn); - -+ for (i = 0; i < config->num_crtc; i++) -+ radeon_crtc_modeset_ioctl(config->crtc[i], FALSE); -+ - xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG, - "Ok, leaving now...\n"); - } -@@ -5121,7 +5654,7 @@ void RADEONFreeScreen(int scrnIndex, int flags) - static void RADEONForceSomeClocks(ScrnInfoPtr pScrn) - { - /* It appears from r300 and rv100 may need some clocks forced-on */ -- CARD32 tmp; -+ uint32_t tmp; - - tmp = INPLL(pScrn, RADEON_SCLK_CNTL); - tmp |= RADEON_SCLK_FORCE_CP | RADEON_SCLK_FORCE_VIP; -@@ -5133,7 +5666,7 @@ static void RADEONSetDynamicClock(ScrnInfoPtr pScrn, int mode) - RADEONInfoPtr info = RADEONPTR(pScrn); - RADEONEntPtr pRADEONEnt = RADEONEntPriv(pScrn); - unsigned char *RADEONMMIO = info->MMIO; -- CARD32 tmp; -+ uint32_t tmp; - switch(mode) { - case 0: /* Turn everything OFF (ForceON to everything)*/ - if ( !pRADEONEnt->HasCRTC2 ) { -diff --git a/src/radeon_exa.c b/src/radeon_exa.c -index 4da4841..02fd4fc 100644 ---- a/src/radeon_exa.c -+++ b/src/radeon_exa.c -@@ -99,17 +99,24 @@ static __inline__ int - RADEONLog2(int val) - { - int bits; -- -+#if (defined __i386__ || defined __x86_64__) && (defined __GNUC__) -+ __asm volatile("bsrl %1, %0" -+ : "=r" (bits) -+ : "c" (val) -+ ); -+ return bits; -+#else - for (bits = 0; val != 0; val >>= 1, ++bits) - ; - return bits - 1; -+#endif - } - --static __inline__ CARD32 F_TO_DW(float val) -+static __inline__ uint32_t F_TO_DW(float val) - { - union { - float f; -- CARD32 l; -+ uint32_t l; - } tmp; - tmp.f = val; - return tmp.l; -@@ -118,7 +125,7 @@ static __inline__ CARD32 F_TO_DW(float val) - /* Assumes that depth 15 and 16 can be used as depth 16, which is okay since we - * require src and dest datatypes to be equal. - */ --Bool RADEONGetDatatypeBpp(int bpp, CARD32 *type) -+Bool RADEONGetDatatypeBpp(int bpp, uint32_t *type) - { - switch (bpp) { - case 8: -@@ -152,7 +159,7 @@ static Bool RADEONPixmapIsColortiled(PixmapPtr pPix) - return FALSE; - } - --static Bool RADEONGetOffsetPitch(PixmapPtr pPix, int bpp, CARD32 *pitch_offset, -+static Bool RADEONGetOffsetPitch(PixmapPtr pPix, int bpp, uint32_t *pitch_offset, - unsigned int offset, unsigned int pitch) - { - RINFO_FROM_SCREEN(pPix->drawable.pScreen); -@@ -172,17 +179,17 @@ static Bool RADEONGetOffsetPitch(PixmapPtr pPix, int bpp, CARD32 *pitch_offset, - return TRUE; - } - --Bool RADEONGetPixmapOffsetPitch(PixmapPtr pPix, CARD32 *pitch_offset) -+Bool RADEONGetPixmapOffsetPitch(PixmapPtr pPix, uint32_t *pitch_offset) - { - RINFO_FROM_SCREEN(pPix->drawable.pScreen); -- CARD32 pitch, offset; -+ uint32_t pitch, offset; - int bpp; - - bpp = pPix->drawable.bitsPerPixel; - if (bpp == 24) - bpp = 8; - -- offset = exaGetPixmapOffset(pPix) + info->fbLocation; -+ offset = exaGetPixmapOffset(pPix) + info->fbLocation + pScrn->fbOffset; - pitch = exaGetPixmapPitch(pPix); - - return RADEONGetOffsetPitch(pPix, bpp, pitch_offset, offset, pitch); -@@ -196,9 +203,9 @@ static Bool RADEONPrepareAccess(PixmapPtr pPix, int index) - { - RINFO_FROM_SCREEN(pPix->drawable.pScreen); - unsigned char *RADEONMMIO = info->MMIO; -- CARD32 offset = exaGetPixmapOffset(pPix); -+ uint32_t offset = exaGetPixmapOffset(pPix); - int bpp, soff; -- CARD32 size, flags; -+ uint32_t size, flags; - - /* Front buffer is always set with proper swappers */ - if (offset == 0) -@@ -262,7 +269,7 @@ static void RADEONFinishAccess(PixmapPtr pPix, int index) - { - RINFO_FROM_SCREEN(pPix->drawable.pScreen); - unsigned char *RADEONMMIO = info->MMIO; -- CARD32 offset = exaGetPixmapOffset(pPix); -+ uint32_t offset = exaGetPixmapOffset(pPix); - int soff; - - /* Front buffer is always set with proper swappers */ -@@ -293,7 +300,7 @@ static void RADEONFinishAccess(PixmapPtr pPix, int index) - - #define RADEON_SWITCH_TO_2D() \ - do { \ -- CARD32 wait_until = 0; \ -+ uint32_t wait_until = 0; \ - BEGIN_ACCEL(1); \ - switch (info->engineMode) { \ - case EXA_ENGINEMODE_UNKNOWN: \ -@@ -310,13 +317,13 @@ do { \ - - #define RADEON_SWITCH_TO_3D() \ - do { \ -- CARD32 wait_until = 0; \ -+ uint32_t wait_until = 0; \ - BEGIN_ACCEL(1); \ - switch (info->engineMode) { \ - case EXA_ENGINEMODE_UNKNOWN: \ - wait_until |= RADEON_WAIT_HOST_IDLECLEAN | RADEON_WAIT_3D_IDLECLEAN; \ - case EXA_ENGINEMODE_2D: \ -- wait_until |= RADEON_WAIT_2D_IDLECLEAN; \ -+ wait_until |= RADEON_WAIT_2D_IDLECLEAN | RADEON_WAIT_DMA_GUI_IDLE; \ - case EXA_ENGINEMODE_3D: \ - break; \ - } \ -@@ -395,7 +402,7 @@ Bool RADEONSetupMemEXA (ScreenPtr pScreen) - else - screen_size = pScrn->virtualY * byteStride; - -- info->exa->memoryBase = info->FB + pScrn->fbOffset; -+ info->exa->memoryBase = info->FB; - info->exa->memorySize = info->FbMapSize - info->FbSecureSize; - info->exa->offScreenBase = screen_size; - -@@ -406,14 +413,16 @@ Bool RADEONSetupMemEXA (ScreenPtr pScreen) - /* Reserve static area for hardware cursor */ - if (!xf86ReturnOptValBool(info->Options, OPTION_SW_CURSOR, FALSE)) { - int cursor_size = 64 * 4 * 64; -+ int align = IS_AVIVO_VARIANT ? 4096 : 256; - int c; - - for (c = 0; c < xf86_config->num_crtc; c++) { - xf86CrtcPtr crtc = xf86_config->crtc[c]; - RADEONCrtcPrivatePtr radeon_crtc = crtc->driver_private; - -- radeon_crtc->cursor_offset = info->exa->offScreenBase; -- info->exa->offScreenBase += cursor_size; -+ radeon_crtc->cursor_offset = -+ RADEON_ALIGN(info->exa->offScreenBase, align); -+ info->exa->offScreenBase = radeon_crtc->cursor_offset + cursor_size; - - xf86DrvMsg(pScrn->scrnIndex, X_INFO, - "Will use %d kb for hardware cursor %d at offset 0x%08x\n", -diff --git a/src/radeon_exa_funcs.c b/src/radeon_exa_funcs.c -index 10221c0..56de23e 100644 ---- a/src/radeon_exa_funcs.c -+++ b/src/radeon_exa_funcs.c -@@ -88,7 +88,7 @@ static Bool - FUNC_NAME(RADEONPrepareSolid)(PixmapPtr pPix, int alu, Pixel pm, Pixel fg) - { - RINFO_FROM_SCREEN(pPix->drawable.pScreen); -- CARD32 datatype, dst_pitch_offset; -+ uint32_t datatype, dst_pitch_offset; - ACCEL_PREAMBLE(); - - TRACE; -@@ -124,7 +124,6 @@ FUNC_NAME(RADEONPrepareSolid)(PixmapPtr pPix, int alu, Pixel pm, Pixel fg) - static void - FUNC_NAME(RADEONSolid)(PixmapPtr pPix, int x1, int y1, int x2, int y2) - { -- - RINFO_FROM_SCREEN(pPix->drawable.pScreen); - ACCEL_PREAMBLE(); - -@@ -139,12 +138,21 @@ FUNC_NAME(RADEONSolid)(PixmapPtr pPix, int x1, int y1, int x2, int y2) - static void - FUNC_NAME(RADEONDoneSolid)(PixmapPtr pPix) - { -+ RINFO_FROM_SCREEN(pPix->drawable.pScreen); -+ ACCEL_PREAMBLE(); -+ - TRACE; -+ -+ BEGIN_ACCEL(2); -+ OUT_ACCEL_REG(RADEON_DSTCACHE_CTLSTAT, RADEON_RB2D_DC_FLUSH_ALL); -+ OUT_ACCEL_REG(RADEON_WAIT_UNTIL, -+ RADEON_WAIT_2D_IDLECLEAN | RADEON_WAIT_DMA_GUI_IDLE); -+ FINISH_ACCEL(); - } - - void --FUNC_NAME(RADEONDoPrepareCopy)(ScrnInfoPtr pScrn, CARD32 src_pitch_offset, -- CARD32 dst_pitch_offset, CARD32 datatype, int rop, -+FUNC_NAME(RADEONDoPrepareCopy)(ScrnInfoPtr pScrn, uint32_t src_pitch_offset, -+ uint32_t dst_pitch_offset, uint32_t datatype, int rop, - Pixel planemask) - { - RADEONInfoPtr info = RADEONPTR(pScrn); -@@ -178,7 +186,7 @@ FUNC_NAME(RADEONPrepareCopy)(PixmapPtr pSrc, PixmapPtr pDst, - Pixel planemask) - { - RINFO_FROM_SCREEN(pDst->drawable.pScreen); -- CARD32 datatype, src_pitch_offset, dst_pitch_offset; -+ uint32_t datatype, src_pitch_offset, dst_pitch_offset; - - TRACE; - -@@ -206,7 +214,6 @@ FUNC_NAME(RADEONCopy)(PixmapPtr pDst, - int dstX, int dstY, - int w, int h) - { -- - RINFO_FROM_SCREEN(pDst->drawable.pScreen); - ACCEL_PREAMBLE(); - -@@ -233,7 +240,16 @@ FUNC_NAME(RADEONCopy)(PixmapPtr pDst, - static void - FUNC_NAME(RADEONDoneCopy)(PixmapPtr pDst) - { -+ RINFO_FROM_SCREEN(pDst->drawable.pScreen); -+ ACCEL_PREAMBLE(); -+ - TRACE; -+ -+ BEGIN_ACCEL(2); -+ OUT_ACCEL_REG(RADEON_DSTCACHE_CTLSTAT, RADEON_RB2D_DC_FLUSH_ALL); -+ OUT_ACCEL_REG(RADEON_WAIT_UNTIL, -+ RADEON_WAIT_2D_IDLECLEAN | RADEON_WAIT_DMA_GUI_IDLE); -+ FINISH_ACCEL(); - } - - static Bool -@@ -241,12 +257,12 @@ FUNC_NAME(RADEONUploadToScreen)(PixmapPtr pDst, int x, int y, int w, int h, - char *src, int src_pitch) - { - RINFO_FROM_SCREEN(pDst->drawable.pScreen); -- CARD8 *dst = info->FB + exaGetPixmapOffset(pDst); -+ uint8_t *dst = info->FB + exaGetPixmapOffset(pDst); - unsigned int dst_pitch = exaGetPixmapPitch(pDst); - unsigned int bpp = pDst->drawable.bitsPerPixel; - #ifdef ACCEL_CP - unsigned int hpass; -- CARD32 buf_pitch, dst_pitch_off; -+ uint32_t buf_pitch, dst_pitch_off; - #endif - #if X_BYTE_ORDER == X_BIG_ENDIAN - unsigned char *RADEONMMIO = info->MMIO; -@@ -263,7 +279,7 @@ FUNC_NAME(RADEONUploadToScreen)(PixmapPtr pDst, int x, int y, int w, int h, - #ifdef ACCEL_CP - if (info->directRenderingEnabled && - RADEONGetPixmapOffsetPitch(pDst, &dst_pitch_off)) { -- CARD8 *buf; -+ uint8_t *buf; - int cpp = bpp / 8; - ACCEL_PREAMBLE(); - -@@ -271,7 +287,7 @@ FUNC_NAME(RADEONUploadToScreen)(PixmapPtr pDst, int x, int y, int w, int h, - while ((buf = RADEONHostDataBlit(pScrn, - cpp, w, dst_pitch_off, &buf_pitch, - x, &y, (unsigned int*)&h, &hpass)) != 0) { -- RADEONHostDataBlitCopyPass(pScrn, cpp, buf, (CARD8 *)src, -+ RADEONHostDataBlitCopyPass(pScrn, cpp, buf, (uint8_t *)src, - hpass, buf_pitch, src_pitch); - src += hpass * src_pitch; - } -@@ -319,8 +335,8 @@ FUNC_NAME(RADEONUploadToScreen)(PixmapPtr pDst, int x, int y, int w, int h, - #ifdef ACCEL_CP - /* Emit blit with arbitrary source and destination offsets and pitches */ - static void --RADEONBlitChunk(ScrnInfoPtr pScrn, CARD32 datatype, CARD32 src_pitch_offset, -- CARD32 dst_pitch_offset, int srcX, int srcY, int dstX, int dstY, -+RADEONBlitChunk(ScrnInfoPtr pScrn, uint32_t datatype, uint32_t src_pitch_offset, -+ uint32_t dst_pitch_offset, int srcX, int srcY, int dstX, int dstY, - int w, int h) - { - RADEONInfoPtr info = RADEONPTR(pScrn); -@@ -343,6 +359,11 @@ RADEONBlitChunk(ScrnInfoPtr pScrn, CARD32 datatype, CARD32 src_pitch_offset, - OUT_ACCEL_REG(RADEON_DST_Y_X, (dstY << 16) | dstX); - OUT_ACCEL_REG(RADEON_DST_HEIGHT_WIDTH, (h << 16) | w); - FINISH_ACCEL(); -+ BEGIN_ACCEL(2); -+ OUT_ACCEL_REG(RADEON_DSTCACHE_CTLSTAT, RADEON_RB2D_DC_FLUSH_ALL); -+ OUT_ACCEL_REG(RADEON_WAIT_UNTIL, -+ RADEON_WAIT_2D_IDLECLEAN | RADEON_WAIT_DMA_GUI_IDLE); -+ FINISH_ACCEL(); - } - #endif - -@@ -357,11 +378,11 @@ FUNC_NAME(RADEONDownloadFromScreen)(PixmapPtr pSrc, int x, int y, int w, int h, - ~(RADEON_NONSURF_AP0_SWP_32BPP | RADEON_NONSURF_AP1_SWP_32BPP | - RADEON_NONSURF_AP0_SWP_16BPP | RADEON_NONSURF_AP1_SWP_16BPP); - #endif -- CARD8 *src = info->FB + exaGetPixmapOffset(pSrc); -+ uint8_t *src = info->FB + exaGetPixmapOffset(pSrc); - int src_pitch = exaGetPixmapPitch(pSrc); - int bpp = pSrc->drawable.bitsPerPixel; - #ifdef ACCEL_CP -- CARD32 datatype, src_pitch_offset, scratch_pitch = (w * bpp/8 + 63) & ~63, scratch_off = 0; -+ uint32_t datatype, src_pitch_offset, scratch_pitch = (w * bpp/8 + 63) & ~63, scratch_off = 0; - drmBufPtr scratch; - #endif - -@@ -379,7 +400,7 @@ FUNC_NAME(RADEONDownloadFromScreen)(PixmapPtr pSrc, int x, int y, int w, int h, - { - int swap = RADEON_HOST_DATA_SWAP_NONE, wpass = w * bpp / 8; - int hpass = min(h, scratch->total/2 / scratch_pitch); -- CARD32 scratch_pitch_offset = scratch_pitch << 16 -+ uint32_t scratch_pitch_offset = scratch_pitch << 16 - | (info->gartLocation + info->bufStart - + scratch->idx * scratch->total) >> 10; - drmRadeonIndirect indirect; -@@ -406,7 +427,7 @@ FUNC_NAME(RADEONDownloadFromScreen)(PixmapPtr pSrc, int x, int y, int w, int h, - while (h) { - int oldhpass = hpass, i = 0; - -- src = (CARD8*)scratch->address + scratch_off; -+ src = (uint8_t*)scratch->address + scratch_off; - - y += oldhpass; - h -= oldhpass; -@@ -439,10 +460,10 @@ FUNC_NAME(RADEONDownloadFromScreen)(PixmapPtr pSrc, int x, int y, int w, int h, - - /* Copy out data from previous blit */ - if (wpass == scratch_pitch && wpass == dst_pitch) { -- RADEONCopySwap((CARD8*)dst, src, wpass * oldhpass, swap); -+ RADEONCopySwap((uint8_t*)dst, src, wpass * oldhpass, swap); - dst += dst_pitch * oldhpass; - } else while (oldhpass--) { -- RADEONCopySwap((CARD8*)dst, src, wpass, swap); -+ RADEONCopySwap((uint8_t*)dst, src, wpass, swap); - src += scratch_pitch; - dst += dst_pitch; - } -@@ -533,21 +554,27 @@ Bool FUNC_NAME(RADEONDrawInit)(ScreenPtr pScreen) - - #ifdef RENDER - if (info->RenderAccel) { -- if ((info->ChipFamily >= CHIP_FAMILY_R600) || -- (info->ChipFamily == CHIP_FAMILY_RS400)) -+ if (info->ChipFamily >= CHIP_FAMILY_R600) - xf86DrvMsg(pScrn->scrnIndex, X_INFO, "Render acceleration " -- "unsupported on XPRESS, R500 and newer cards.\n"); -- else if (IS_R300_VARIANT || (IS_AVIVO_VARIANT && info->ChipFamily <= CHIP_FAMILY_RS690)) { -+ "unsupported on R600 and newer cards.\n"); -+ else if (IS_R300_3D || IS_R500_3D) { -+ if ((info->ChipFamily < CHIP_FAMILY_RS400) -+#ifdef XF86DRI -+ || (info->directRenderingEnabled) -+#endif -+ ) { - xf86DrvMsg(pScrn->scrnIndex, X_INFO, "Render acceleration " -- "enabled for R300 type cards.\n"); -+ "enabled for R300/R400/R500 type cards.\n"); - info->exa->CheckComposite = R300CheckComposite; - info->exa->PrepareComposite = - FUNC_NAME(R300PrepareComposite); - info->exa->Composite = FUNC_NAME(RadeonComposite); -- info->exa->DoneComposite = RadeonDoneComposite; -- } else if ((info->ChipFamily == CHIP_FAMILY_RV250) || -- (info->ChipFamily == CHIP_FAMILY_RV280) || -- (info->ChipFamily == CHIP_FAMILY_RS300) || -+ info->exa->DoneComposite = FUNC_NAME(RadeonDoneComposite); -+ } else -+ xf86DrvMsg(pScrn->scrnIndex, X_INFO, "EXA Composite requires CP on R5xx/IGP\n"); -+ } else if ((info->ChipFamily == CHIP_FAMILY_RV250) || -+ (info->ChipFamily == CHIP_FAMILY_RV280) || -+ (info->ChipFamily == CHIP_FAMILY_RS300) || - (info->ChipFamily == CHIP_FAMILY_R200)) { - xf86DrvMsg(pScrn->scrnIndex, X_INFO, "Render acceleration " - "enabled for R200 type cards.\n"); -@@ -555,7 +582,7 @@ Bool FUNC_NAME(RADEONDrawInit)(ScreenPtr pScreen) - info->exa->PrepareComposite = - FUNC_NAME(R200PrepareComposite); - info->exa->Composite = FUNC_NAME(RadeonComposite); -- info->exa->DoneComposite = RadeonDoneComposite; -+ info->exa->DoneComposite = FUNC_NAME(RadeonDoneComposite); - } else { - xf86DrvMsg(pScrn->scrnIndex, X_INFO, "Render acceleration " - "enabled for R100 type cards.\n"); -@@ -563,7 +590,7 @@ Bool FUNC_NAME(RADEONDrawInit)(ScreenPtr pScreen) - info->exa->PrepareComposite = - FUNC_NAME(R100PrepareComposite); - info->exa->Composite = FUNC_NAME(RadeonComposite); -- info->exa->DoneComposite = RadeonDoneComposite; -+ info->exa->DoneComposite = FUNC_NAME(RadeonDoneComposite); - } - } - #endif -@@ -572,11 +599,11 @@ Bool FUNC_NAME(RADEONDrawInit)(ScreenPtr pScreen) - xf86DrvMsg(pScrn->scrnIndex, X_INFO, "Setting EXA maxPitchBytes\n"); - - info->exa->maxPitchBytes = 16320; -- info->exa->maxX = info->exa->Composite ? 2048 : 8192; -+ info->exa->maxX = 8192; - #else -- info->exa->maxX = info->exa->Composite ? 2048 : 16320 / 4; -+ info->exa->maxX = 16320 / 4; - #endif -- info->exa->maxY = info->exa->Composite ? 2048 : 8192; -+ info->exa->maxY = 8192; - - RADEONEngineInit(pScrn); - -diff --git a/src/radeon_exa_render.c b/src/radeon_exa_render.c -index 9bbccb5..5d28d80 100644 ---- a/src/radeon_exa_render.c -+++ b/src/radeon_exa_render.c -@@ -26,6 +26,7 @@ - * Eric Anholt - * Zack Rusin - * Benjamin Herrenschmidt -+ * Alex Deucher - * - */ - -@@ -57,11 +58,18 @@ - #ifdef ONLY_ONCE - static Bool is_transform[2]; - static PictTransform *transform[2]; -+static Bool has_mask; -+/* Whether we are tiling horizontally and vertically */ -+static Bool need_src_tile_x; -+static Bool need_src_tile_y; -+/* Size of tiles ... set to 65536x65536 if not tiling in that direction */ -+static Bool src_tile_width; -+static Bool src_tile_height; - - struct blendinfo { - Bool dst_alpha; - Bool src_alpha; -- CARD32 blend_cntl; -+ uint32_t blend_cntl; - }; - - static struct blendinfo RadeonBlendOp[] = { -@@ -95,7 +103,7 @@ static struct blendinfo RadeonBlendOp[] = { - - struct formatinfo { - int fmt; -- CARD32 card_fmt; -+ uint32_t card_fmt; - }; - - /* Note on texture formats: -@@ -134,7 +142,7 @@ static struct formatinfo R300TexFormats[] = { - - /* Common Radeon setup code */ - --static Bool RADEONGetDestFormat(PicturePtr pDstPicture, CARD32 *dst_format) -+static Bool RADEONGetDestFormat(PicturePtr pDstPicture, uint32_t *dst_format) - { - switch (pDstPicture->format) { - case PICT_a8r8g8b8: -@@ -159,7 +167,7 @@ static Bool RADEONGetDestFormat(PicturePtr pDstPicture, CARD32 *dst_format) - return TRUE; - } - --static Bool R300GetDestFormat(PicturePtr pDstPicture, CARD32 *dst_format) -+static Bool R300GetDestFormat(PicturePtr pDstPicture, uint32_t *dst_format) - { - switch (pDstPicture->format) { - case PICT_a8r8g8b8: -@@ -177,16 +185,15 @@ static Bool R300GetDestFormat(PicturePtr pDstPicture, CARD32 *dst_format) - *dst_format = R300_COLORFORMAT_I8; - break; - default: -- ErrorF("Unsupported dest format 0x%x\n", -- (int)pDstPicture->format); -- return FALSE; -+ RADEON_FALLBACK(("Unsupported dest format 0x%x\n", -+ (int)pDstPicture->format)); - } - return TRUE; - } - --static CARD32 RADEONGetBlendCntl(int op, PicturePtr pMask, CARD32 dst_format) -+static uint32_t RADEONGetBlendCntl(int op, PicturePtr pMask, uint32_t dst_format) - { -- CARD32 sblend, dblend; -+ uint32_t sblend, dblend; - - sblend = RadeonBlendOp[op].blend_cntl & RADEON_SRC_BLEND_MASK; - dblend = RadeonBlendOp[op].blend_cntl & RADEON_DST_BLEND_MASK; -@@ -218,9 +225,98 @@ static CARD32 RADEONGetBlendCntl(int op, PicturePtr pMask, CARD32 dst_format) - - union intfloat { - float f; -- CARD32 i; -+ uint32_t i; - }; - -+/* Check if we need a software-fallback because of a repeating -+ * non-power-of-two texture. -+ * -+ * canTile: whether we can emulate a repeat by drawing in tiles: -+ * possible for the source, but not for the mask. (Actually -+ * we could do tiling for the mask too, but dealing with the -+ * combination of a tiled mask and a tiled source would be -+ * a lot of complexity, so we handle only the most common -+ * case of a repeating mask.) -+ */ -+static Bool RADEONCheckTexturePOT(PicturePtr pPict, Bool canTile) -+{ -+ int w = pPict->pDrawable->width; -+ int h = pPict->pDrawable->height; -+ -+ if (pPict->repeat && ((w & (w - 1)) != 0 || (h & (h - 1)) != 0) && -+ !(!pPict->transform && canTile)) -+ RADEON_FALLBACK(("NPOT repeating %s unsupported (%dx%d), transform=%d\n", -+ canTile ? "source" : "mask", w, h, pPict->transform != 0)); -+ -+ return TRUE; -+} -+ -+/* Determine if the pitch of the pixmap meets the criteria for being -+ * used as a repeating texture: no padding or only a single line texture. -+ */ -+static Bool RADEONPitchMatches(PixmapPtr pPix) -+{ -+ int w = pPix->drawable.width; -+ int h = pPix->drawable.height; -+ uint32_t txpitch = exaGetPixmapPitch(pPix); -+ -+ if (h > 1 && ((w * pPix->drawable.bitsPerPixel / 8 + 31) & ~31) != txpitch) -+ return FALSE; -+ -+ return TRUE; -+} -+ -+/* We can't turn on repeats normally for a non-power-of-two dimension, -+ * but if the source isn't transformed, we can get the same effect -+ * by drawing the image in multiple tiles. (A common case that it's -+ * important to get right is drawing a strip of a NPOTxPOT texture -+ * repeating in the POT direction. With tiling, this ends up as a -+ * a single tile on R300 and newer, which is perfect.) -+ * -+ * canTile1d: On R300 and newer, we can repeat a texture that is NPOT in -+ * one direction and POT in the other in the POT direction; on -+ * older chips we can only repeat at all if the texture is POT in -+ * both directions. -+ * -+ * needMatchingPitch: On R100/R200, we can only repeat horizontally if -+ * there is no padding in the texture. Textures with small POT widths -+ * (1,2,4,8) thus can't be tiled. -+ */ -+static Bool RADEONSetupSourceTile(PicturePtr pPict, -+ PixmapPtr pPix, -+ Bool canTile1d, -+ Bool needMatchingPitch) -+{ -+ need_src_tile_x = need_src_tile_y = FALSE; -+ src_tile_width = src_tile_height = 65536; /* "infinite" */ -+ -+ if (pPict->repeat) { -+ Bool badPitch = needMatchingPitch && !RADEONPitchMatches(pPix); -+ -+ int w = pPict->pDrawable->width; -+ int h = pPict->pDrawable->height; -+ -+ if (pPict->transform) { -+ if (badPitch) -+ RADEON_FALLBACK(("Width %d and pitch %u not compatible for repeat\n", -+ w, (unsigned)exaGetPixmapPitch(pPix))); -+ } else { -+ need_src_tile_x = (w & (w - 1)) != 0 || badPitch; -+ need_src_tile_y = (h & (h - 1)) != 0; -+ -+ if (!canTile1d) -+ need_src_tile_x = need_src_tile_y = need_src_tile_x || need_src_tile_y; -+ } -+ -+ if (need_src_tile_x) -+ src_tile_width = w; -+ if (need_src_tile_y) -+ src_tile_height = h; -+ } -+ -+ return TRUE; -+} -+ - /* R100-specific code */ - - static Bool R100CheckCompositeTexture(PicturePtr pPict, int unit) -@@ -240,8 +336,8 @@ static Bool R100CheckCompositeTexture(PicturePtr pPict, int unit) - RADEON_FALLBACK(("Unsupported picture format 0x%x\n", - (int)pPict->format)); - -- if (pPict->repeat && ((w & (w - 1)) != 0 || (h & (h - 1)) != 0)) -- RADEON_FALLBACK(("NPOT repeat unsupported (%dx%d)\n", w, h)); -+ if (!RADEONCheckTexturePOT(pPict, unit == 0)) -+ return FALSE; - - if (pPict->filter != PictFilterNearest && - pPict->filter != PictFilterBilinear) -@@ -258,14 +354,15 @@ static Bool FUNC_NAME(R100TextureSetup)(PicturePtr pPict, PixmapPtr pPix, - int unit) - { - RINFO_FROM_SCREEN(pPix->drawable.pScreen); -- CARD32 txfilter, txformat, txoffset, txpitch; -+ uint32_t txfilter, txformat, txoffset, txpitch; - int w = pPict->pDrawable->width; - int h = pPict->pDrawable->height; -+ Bool repeat = pPict->repeat && !(unit == 0 && (need_src_tile_x || need_src_tile_y)); - int i; - ACCEL_PREAMBLE(); - - txpitch = exaGetPixmapPitch(pPix); -- txoffset = exaGetPixmapOffset(pPix) + info->fbLocation; -+ txoffset = exaGetPixmapOffset(pPix) + info->fbLocation + pScrn->fbOffset; - - if ((txoffset & 0x1f) != 0) - RADEON_FALLBACK(("Bad texture offset 0x%x\n", (int)txoffset)); -@@ -281,9 +378,8 @@ static Bool FUNC_NAME(R100TextureSetup)(PicturePtr pPict, PixmapPtr pPix, - if (RADEONPixmapIsColortiled(pPix)) - txoffset |= RADEON_TXO_MACRO_TILE; - -- if (pPict->repeat) { -- if ((h != 1) && -- (((w * pPix->drawable.bitsPerPixel / 8 + 31) & ~31) != txpitch)) -+ if (repeat) { -+ if (!RADEONPitchMatches(pPix)) - RADEON_FALLBACK(("Width %d and pitch %u not compatible for repeat\n", - w, (unsigned)txpitch)); - -@@ -307,6 +403,9 @@ static Bool FUNC_NAME(R100TextureSetup)(PicturePtr pPict, PixmapPtr pPix, - RADEON_FALLBACK(("Bad filter 0x%x\n", pPict->filter)); - } - -+ if (repeat) -+ txfilter |= RADEON_CLAMP_S_WRAP | RADEON_CLAMP_T_WRAP; -+ - BEGIN_ACCEL(5); - if (unit == 0) { - OUT_ACCEL_REG(RADEON_PP_TXFILTER_0, txfilter); -@@ -338,41 +437,76 @@ static Bool FUNC_NAME(R100TextureSetup)(PicturePtr pPict, PixmapPtr pPix, - } - - #ifdef ONLY_ONCE -+ -+static PixmapPtr -+RADEONGetDrawablePixmap(DrawablePtr pDrawable) -+{ -+ if (pDrawable->type == DRAWABLE_WINDOW) -+ return pDrawable->pScreen->GetWindowPixmap((WindowPtr)pDrawable); -+ else -+ return (PixmapPtr)pDrawable; -+} -+ - static Bool R100CheckComposite(int op, PicturePtr pSrcPicture, - PicturePtr pMaskPicture, PicturePtr pDstPicture) - { -- CARD32 tmp1; -+ PixmapPtr pSrcPixmap, pDstPixmap; -+ uint32_t tmp1; - - /* Check for unsupported compositing operations. */ - if (op >= sizeof(RadeonBlendOp) / sizeof(RadeonBlendOp[0])) - RADEON_FALLBACK(("Unsupported Composite op 0x%x\n", op)); - -- if (pMaskPicture != NULL && pMaskPicture->componentAlpha) { -- /* Check if it's component alpha that relies on a source alpha and on -- * the source value. We can only get one of those into the single -- * source value that we get to blend with. -- */ -- if (RadeonBlendOp[op].src_alpha && -- (RadeonBlendOp[op].blend_cntl & RADEON_SRC_BLEND_MASK) != -- RADEON_SRC_BLEND_GL_ZERO) -- { -- RADEON_FALLBACK(("Component alpha not supported with source " -- "alpha and source value blending.\n")); -- } -+ if (!pSrcPicture->pDrawable) -+ return FALSE; -+ -+ pSrcPixmap = RADEONGetDrawablePixmap(pSrcPicture->pDrawable); -+ -+ if (pSrcPixmap->drawable.width >= 2048 || -+ pSrcPixmap->drawable.height >= 2048) { -+ RADEON_FALLBACK(("Source w/h too large (%d,%d).\n", -+ pSrcPixmap->drawable.width, -+ pSrcPixmap->drawable.height)); - } - -- if (pDstPicture->pDrawable->width >= (1 << 11) || -- pDstPicture->pDrawable->height >= (1 << 11)) -- { -+ pDstPixmap = RADEONGetDrawablePixmap(pDstPicture->pDrawable); -+ -+ if (pDstPixmap->drawable.width >= 2048 || -+ pDstPixmap->drawable.height >= 2048) { - RADEON_FALLBACK(("Dest w/h too large (%d,%d).\n", -- pDstPicture->pDrawable->width, -- pDstPicture->pDrawable->height)); -+ pDstPixmap->drawable.width, -+ pDstPixmap->drawable.height)); -+ } -+ -+ if (pMaskPicture) { -+ PixmapPtr pMaskPixmap = RADEONGetDrawablePixmap(pMaskPicture->pDrawable); -+ -+ if (pMaskPixmap->drawable.width >= 2048 || -+ pMaskPixmap->drawable.height >= 2048) { -+ RADEON_FALLBACK(("Mask w/h too large (%d,%d).\n", -+ pMaskPixmap->drawable.width, -+ pMaskPixmap->drawable.height)); -+ } -+ -+ if (pMaskPicture->componentAlpha) { -+ /* Check if it's component alpha that relies on a source alpha and -+ * on the source value. We can only get one of those into the -+ * single source value that we get to blend with. -+ */ -+ if (RadeonBlendOp[op].src_alpha && -+ (RadeonBlendOp[op].blend_cntl & RADEON_SRC_BLEND_MASK) != -+ RADEON_SRC_BLEND_GL_ZERO) { -+ RADEON_FALLBACK(("Component alpha not supported with source " -+ "alpha and source value blending.\n")); -+ } -+ } -+ -+ if (!R100CheckCompositeTexture(pMaskPicture, 1)) -+ return FALSE; - } - - if (!R100CheckCompositeTexture(pSrcPicture, 0)) - return FALSE; -- if (pMaskPicture != NULL && !R100CheckCompositeTexture(pMaskPicture, 1)) -- return FALSE; - - if (!RADEONGetDestFormat(pDstPicture, &tmp1)) - return FALSE; -@@ -390,8 +524,8 @@ static Bool FUNC_NAME(R100PrepareComposite)(int op, - PixmapPtr pDst) - { - RINFO_FROM_SCREEN(pDst->drawable.pScreen); -- CARD32 dst_format, dst_offset, dst_pitch, colorpitch; -- CARD32 pp_cntl, blendcntl, cblend, ablend; -+ uint32_t dst_format, dst_offset, dst_pitch, colorpitch; -+ uint32_t pp_cntl, blendcntl, cblend, ablend; - int pixel_shift; - ACCEL_PREAMBLE(); - -@@ -400,22 +534,32 @@ static Bool FUNC_NAME(R100PrepareComposite)(int op, - if (!info->XInited3D) - RADEONInit3DEngine(pScrn); - -- RADEONGetDestFormat(pDstPicture, &dst_format); -+ if (!RADEONGetDestFormat(pDstPicture, &dst_format)) -+ return FALSE; -+ -+ if (pMask) -+ has_mask = TRUE; -+ else -+ has_mask = FALSE; -+ - pixel_shift = pDst->drawable.bitsPerPixel >> 4; - -- dst_offset = exaGetPixmapOffset(pDst) + info->fbLocation; -+ dst_offset = exaGetPixmapOffset(pDst) + info->fbLocation + pScrn->fbOffset; - dst_pitch = exaGetPixmapPitch(pDst); - colorpitch = dst_pitch >> pixel_shift; - if (RADEONPixmapIsColortiled(pDst)) - colorpitch |= RADEON_COLOR_TILE_ENABLE; - -- dst_offset = exaGetPixmapOffset(pDst) + info->fbLocation; -+ dst_offset = exaGetPixmapOffset(pDst) + info->fbLocation + pScrn->fbOffset; - dst_pitch = exaGetPixmapPitch(pDst); - if ((dst_offset & 0x0f) != 0) - RADEON_FALLBACK(("Bad destination offset 0x%x\n", (int)dst_offset)); - if (((dst_pitch >> pixel_shift) & 0x7) != 0) - RADEON_FALLBACK(("Bad destination pitch 0x%x\n", (int)dst_pitch)); - -+ if (!RADEONSetupSourceTile(pSrcPicture, pSrc, FALSE, TRUE)) -+ return FALSE; -+ - if (!FUNC_NAME(R100TextureSetup)(pSrcPicture, pSrc, 0)) - return FALSE; - pp_cntl = RADEON_TEX_0_ENABLE | RADEON_TEX_BLEND_0_ENABLE; -@@ -471,9 +615,13 @@ static Bool FUNC_NAME(R100PrepareComposite)(int op, - - OUT_ACCEL_REG(RADEON_PP_TXCBLEND_0, cblend); - OUT_ACCEL_REG(RADEON_PP_TXABLEND_0, ablend); -- OUT_ACCEL_REG(RADEON_SE_VTX_FMT, RADEON_SE_VTX_FMT_XY | -- RADEON_SE_VTX_FMT_ST0 | -- RADEON_SE_VTX_FMT_ST1); -+ if (pMask) -+ OUT_ACCEL_REG(RADEON_SE_VTX_FMT, (RADEON_SE_VTX_FMT_XY | -+ RADEON_SE_VTX_FMT_ST0 | -+ RADEON_SE_VTX_FMT_ST1)); -+ else -+ OUT_ACCEL_REG(RADEON_SE_VTX_FMT, (RADEON_SE_VTX_FMT_XY | -+ RADEON_SE_VTX_FMT_ST0)); - /* Op operator. */ - blendcntl = RADEONGetBlendCntl(op, pMaskPicture, pDstPicture->format); - -@@ -503,8 +651,8 @@ static Bool R200CheckCompositeTexture(PicturePtr pPict, int unit) - RADEON_FALLBACK(("Unsupported picture format 0x%x\n", - (int)pPict->format)); - -- if (pPict->repeat && ((w & (w - 1)) != 0 || (h & (h - 1)) != 0)) -- RADEON_FALLBACK(("NPOT repeat unsupported (%dx%d)\n", w, h)); -+ if (!RADEONCheckTexturePOT(pPict, unit == 0)) -+ return FALSE; - - if (pPict->filter != PictFilterNearest && - pPict->filter != PictFilterBilinear) -@@ -519,20 +667,21 @@ static Bool FUNC_NAME(R200TextureSetup)(PicturePtr pPict, PixmapPtr pPix, - int unit) - { - RINFO_FROM_SCREEN(pPix->drawable.pScreen); -- CARD32 txfilter, txformat, txoffset, txpitch; -+ uint32_t txfilter, txformat, txoffset, txpitch; - int w = pPict->pDrawable->width; - int h = pPict->pDrawable->height; -+ Bool repeat = pPict->repeat && !(unit == 0 && (need_src_tile_x || need_src_tile_y)); - int i; - ACCEL_PREAMBLE(); - - txpitch = exaGetPixmapPitch(pPix); -- txoffset = exaGetPixmapOffset(pPix) + info->fbLocation; -+ txoffset = exaGetPixmapOffset(pPix) + info->fbLocation + pScrn->fbOffset; - - if ((txoffset & 0x1f) != 0) - RADEON_FALLBACK(("Bad texture offset 0x%x\n", (int)txoffset)); - if ((txpitch & 0x1f) != 0) - RADEON_FALLBACK(("Bad texture pitch 0x%x\n", (int)txpitch)); -- -+ - for (i = 0; i < sizeof(R200TexFormats) / sizeof(R200TexFormats[0]); i++) - { - if (R200TexFormats[i].fmt == pPict->format) -@@ -542,9 +691,8 @@ static Bool FUNC_NAME(R200TextureSetup)(PicturePtr pPict, PixmapPtr pPix, - if (RADEONPixmapIsColortiled(pPix)) - txoffset |= R200_TXO_MACRO_TILE; - -- if (pPict->repeat) { -- if ((h != 1) && -- (((w * pPix->drawable.bitsPerPixel / 8 + 31) & ~31) != txpitch)) -+ if (repeat) { -+ if (!RADEONPitchMatches(pPix)) - RADEON_FALLBACK(("Width %d and pitch %u not compatible for repeat\n", - w, (unsigned)txpitch)); - -@@ -570,6 +718,9 @@ static Bool FUNC_NAME(R200TextureSetup)(PicturePtr pPict, PixmapPtr pPix, - RADEON_FALLBACK(("Bad filter 0x%x\n", pPict->filter)); - } - -+ if (repeat) -+ txfilter |= R200_CLAMP_S_WRAP | R200_CLAMP_T_WRAP; -+ - BEGIN_ACCEL(6); - if (unit == 0) { - OUT_ACCEL_REG(R200_PP_TXFILTER_0, txfilter); -@@ -604,32 +755,61 @@ static Bool FUNC_NAME(R200TextureSetup)(PicturePtr pPict, PixmapPtr pPix, - static Bool R200CheckComposite(int op, PicturePtr pSrcPicture, PicturePtr pMaskPicture, - PicturePtr pDstPicture) - { -- CARD32 tmp1; -+ PixmapPtr pSrcPixmap, pDstPixmap; -+ uint32_t tmp1; - - TRACE; - -- /* Check for unsupported compositing operations. */ -- if (op >= sizeof(RadeonBlendOp) / sizeof(RadeonBlendOp[0])) -- RADEON_FALLBACK(("Unsupported Composite op 0x%x\n", op)); -+ if (!pSrcPicture->pDrawable) -+ return FALSE; - -- if (pMaskPicture != NULL && pMaskPicture->componentAlpha) { -- /* Check if it's component alpha that relies on a source alpha and on -- * the source value. We can only get one of those into the single -- * source value that we get to blend with. -- */ -- if (RadeonBlendOp[op].src_alpha && -- (RadeonBlendOp[op].blend_cntl & RADEON_SRC_BLEND_MASK) != -- RADEON_SRC_BLEND_GL_ZERO) -- { -- RADEON_FALLBACK(("Component alpha not supported with source " -- "alpha and source value blending.\n")); -+ pSrcPixmap = RADEONGetDrawablePixmap(pSrcPicture->pDrawable); -+ -+ if (pSrcPixmap->drawable.width >= 2048 || -+ pSrcPixmap->drawable.height >= 2048) { -+ RADEON_FALLBACK(("Source w/h too large (%d,%d).\n", -+ pSrcPixmap->drawable.width, -+ pSrcPixmap->drawable.height)); -+ } -+ -+ pDstPixmap = RADEONGetDrawablePixmap(pDstPicture->pDrawable); -+ -+ if (pDstPixmap->drawable.width >= 2048 || -+ pDstPixmap->drawable.height >= 2048) { -+ RADEON_FALLBACK(("Dest w/h too large (%d,%d).\n", -+ pDstPixmap->drawable.width, -+ pDstPixmap->drawable.height)); -+ } -+ -+ if (pMaskPicture) { -+ PixmapPtr pMaskPixmap = RADEONGetDrawablePixmap(pMaskPicture->pDrawable); -+ -+ if (pMaskPixmap->drawable.width >= 2048 || -+ pMaskPixmap->drawable.height >= 2048) { -+ RADEON_FALLBACK(("Mask w/h too large (%d,%d).\n", -+ pMaskPixmap->drawable.width, -+ pMaskPixmap->drawable.height)); - } -+ -+ if (pMaskPicture->componentAlpha) { -+ /* Check if it's component alpha that relies on a source alpha and -+ * on the source value. We can only get one of those into the -+ * single source value that we get to blend with. -+ */ -+ if (RadeonBlendOp[op].src_alpha && -+ (RadeonBlendOp[op].blend_cntl & RADEON_SRC_BLEND_MASK) != -+ RADEON_SRC_BLEND_GL_ZERO) { -+ RADEON_FALLBACK(("Component alpha not supported with source " -+ "alpha and source value blending.\n")); -+ } -+ } -+ -+ if (!R200CheckCompositeTexture(pMaskPicture, 1)) -+ return FALSE; - } - - if (!R200CheckCompositeTexture(pSrcPicture, 0)) - return FALSE; -- if (pMaskPicture != NULL && !R200CheckCompositeTexture(pMaskPicture, 1)) -- return FALSE; - - if (!RADEONGetDestFormat(pDstPicture, &tmp1)) - return FALSE; -@@ -643,8 +823,8 @@ static Bool FUNC_NAME(R200PrepareComposite)(int op, PicturePtr pSrcPicture, - PixmapPtr pSrc, PixmapPtr pMask, PixmapPtr pDst) - { - RINFO_FROM_SCREEN(pDst->drawable.pScreen); -- CARD32 dst_format, dst_offset, dst_pitch; -- CARD32 pp_cntl, blendcntl, cblend, ablend, colorpitch; -+ uint32_t dst_format, dst_offset, dst_pitch; -+ uint32_t pp_cntl, blendcntl, cblend, ablend, colorpitch; - int pixel_shift; - ACCEL_PREAMBLE(); - -@@ -653,10 +833,17 @@ static Bool FUNC_NAME(R200PrepareComposite)(int op, PicturePtr pSrcPicture, - if (!info->XInited3D) - RADEONInit3DEngine(pScrn); - -- RADEONGetDestFormat(pDstPicture, &dst_format); -+ if (!RADEONGetDestFormat(pDstPicture, &dst_format)) -+ return FALSE; -+ -+ if (pMask) -+ has_mask = TRUE; -+ else -+ has_mask = FALSE; -+ - pixel_shift = pDst->drawable.bitsPerPixel >> 4; - -- dst_offset = exaGetPixmapOffset(pDst) + info->fbLocation; -+ dst_offset = exaGetPixmapOffset(pDst) + info->fbLocation + pScrn->fbOffset; - dst_pitch = exaGetPixmapPitch(pDst); - colorpitch = dst_pitch >> pixel_shift; - if (RADEONPixmapIsColortiled(pDst)) -@@ -667,6 +854,9 @@ static Bool FUNC_NAME(R200PrepareComposite)(int op, PicturePtr pSrcPicture, - if (((dst_pitch >> pixel_shift) & 0x7) != 0) - RADEON_FALLBACK(("Bad destination pitch 0x%x\n", (int)dst_pitch)); - -+ if (!RADEONSetupSourceTile(pSrcPicture, pSrc, FALSE, TRUE)) -+ return FALSE; -+ - if (!FUNC_NAME(R200TextureSetup)(pSrcPicture, pSrc, 0)) - return FALSE; - pp_cntl = RADEON_TEX_0_ENABLE | RADEON_TEX_BLEND_0_ENABLE; -@@ -688,9 +878,13 @@ static Bool FUNC_NAME(R200PrepareComposite)(int op, PicturePtr pSrcPicture, - OUT_ACCEL_REG(RADEON_RB3D_COLOROFFSET, dst_offset); - - OUT_ACCEL_REG(R200_SE_VTX_FMT_0, R200_VTX_XY); -- OUT_ACCEL_REG(R200_SE_VTX_FMT_1, -- (2 << R200_VTX_TEX0_COMP_CNT_SHIFT) | -- (2 << R200_VTX_TEX1_COMP_CNT_SHIFT)); -+ if (pMask) -+ OUT_ACCEL_REG(R200_SE_VTX_FMT_1, -+ (2 << R200_VTX_TEX0_COMP_CNT_SHIFT) | -+ (2 << R200_VTX_TEX1_COMP_CNT_SHIFT)); -+ else -+ OUT_ACCEL_REG(R200_SE_VTX_FMT_1, -+ (2 << R200_VTX_TEX0_COMP_CNT_SHIFT)); - - OUT_ACCEL_REG(RADEON_RB3D_COLORPITCH, colorpitch); - -@@ -744,13 +938,26 @@ static Bool FUNC_NAME(R200PrepareComposite)(int op, PicturePtr pSrcPicture, - - #ifdef ONLY_ONCE - --static Bool R300CheckCompositeTexture(PicturePtr pPict, int unit) -+static Bool R300CheckCompositeTexture(PicturePtr pPict, -+ PicturePtr pDstPict, -+ int op, -+ int unit, -+ Bool is_r500) - { - int w = pPict->pDrawable->width; - int h = pPict->pDrawable->height; - int i; -+ int max_tex_w, max_tex_h; - -- if ((w > 0x7ff) || (h > 0x7ff)) -+ if (is_r500) { -+ max_tex_w = 4096; -+ max_tex_h = 4096; -+ } else { -+ max_tex_w = 2048; -+ max_tex_h = 2048; -+ } -+ -+ if ((w > max_tex_w) || (h > max_tex_h)) - RADEON_FALLBACK(("Picture w/h too large (%dx%d)\n", w, h)); - - for (i = 0; i < sizeof(R300TexFormats) / sizeof(R300TexFormats[0]); i++) -@@ -762,13 +969,26 @@ static Bool R300CheckCompositeTexture(PicturePtr pPict, int unit) - RADEON_FALLBACK(("Unsupported picture format 0x%x\n", - (int)pPict->format)); - -- if (pPict->repeat && ((w & (w - 1)) != 0 || (h & (h - 1)) != 0)) -- RADEON_FALLBACK(("NPOT repeat unsupported (%dx%d)\n", w, h)); -+ if (!RADEONCheckTexturePOT(pPict, unit == 0)) -+ return FALSE; - - if (pPict->filter != PictFilterNearest && - pPict->filter != PictFilterBilinear) - RADEON_FALLBACK(("Unsupported filter 0x%x\n", pPict->filter)); - -+ /* for REPEAT_NONE, Render semantics are that sampling outside the source -+ * picture results in alpha=0 pixels. We can implement this with a border color -+ * *if* our source texture has an alpha channel, otherwise we need to fall -+ * back. If we're not transformed then we hope that upper layers have clipped -+ * rendering to the bounds of the source drawable, in which case it doesn't -+ * matter. I have not, however, verified that the X server always does such -+ * clipping. -+ */ -+ if (pPict->transform != 0 && !pPict->repeat && PICT_FORMAT_A(pPict->format) == 0) { -+ if (!(((op == PictOpSrc) || (op == PictOpClear)) && (PICT_FORMAT_A(pDstPict->format) == 0))) -+ RADEON_FALLBACK(("REPEAT_NONE unsupported for transformed xRGB source\n")); -+ } -+ - return TRUE; - } - -@@ -778,7 +998,7 @@ static Bool FUNC_NAME(R300TextureSetup)(PicturePtr pPict, PixmapPtr pPix, - int unit) - { - RINFO_FROM_SCREEN(pPix->drawable.pScreen); -- CARD32 txfilter, txformat0, txformat1, txoffset, txpitch; -+ uint32_t txfilter, txformat0, txformat1, txoffset, txpitch; - int w = pPict->pDrawable->width; - int h = pPict->pDrawable->height; - int i, pixel_shift; -@@ -787,13 +1007,14 @@ static Bool FUNC_NAME(R300TextureSetup)(PicturePtr pPict, PixmapPtr pPix, - TRACE; - - txpitch = exaGetPixmapPitch(pPix); -- txoffset = exaGetPixmapOffset(pPix) + info->fbLocation; -+ txoffset = exaGetPixmapOffset(pPix) + info->fbLocation + pScrn->fbOffset; - - if ((txoffset & 0x1f) != 0) - RADEON_FALLBACK(("Bad texture offset 0x%x\n", (int)txoffset)); - if ((txpitch & 0x1f) != 0) - RADEON_FALLBACK(("Bad texture pitch 0x%x\n", (int)txpitch)); - -+ /* TXPITCH = pixels (texels) per line - 1 */ - pixel_shift = pPix->drawable.bitsPerPixel >> 4; - txpitch >>= pixel_shift; - txpitch -= 1; -@@ -809,24 +1030,35 @@ static Bool FUNC_NAME(R300TextureSetup)(PicturePtr pPict, PixmapPtr pPix, - - txformat1 = R300TexFormats[i].card_fmt; - -- txformat0 = (((w - 1) << R300_TXWIDTH_SHIFT) | -- ((h - 1) << R300_TXHEIGHT_SHIFT)); -+ txformat0 = ((((w - 1) & 0x7ff) << R300_TXWIDTH_SHIFT) | -+ (((h - 1) & 0x7ff) << R300_TXHEIGHT_SHIFT)); - -- if (pPict->repeat) { -- ErrorF("repeat\n"); -- if ((h != 1) && -- (((w * pPix->drawable.bitsPerPixel / 8 + 31) & ~31) != txpitch)) -- RADEON_FALLBACK(("Width %d and pitch %u not compatible for repeat\n", -- w, (unsigned)txpitch)); -- } else -- txformat0 |= R300_TXPITCH_EN; -+ if (IS_R500_3D && ((w - 1) & 0x800)) -+ txpitch |= R500_TXWIDTH_11; - -+ if (IS_R500_3D && ((h - 1) & 0x800)) -+ txpitch |= R500_TXHEIGHT_11; -+ -+ /* Use TXPITCH instead of TXWIDTH for address computations: we could -+ * omit this if there is no padding, but there is no apparent advantage -+ * in doing so. -+ */ -+ txformat0 |= R300_TXPITCH_EN; - - info->texW[unit] = w; - info->texH[unit] = h; - -- txfilter = (R300_TX_CLAMP_S(R300_TX_CLAMP_CLAMP_LAST) | -- R300_TX_CLAMP_T(R300_TX_CLAMP_CLAMP_LAST)); -+ if (pPict->repeat && !(unit == 0 && need_src_tile_x)) -+ txfilter = R300_TX_CLAMP_S(R300_TX_CLAMP_WRAP); -+ else -+ txfilter = R300_TX_CLAMP_S(R300_TX_CLAMP_CLAMP_GL); -+ -+ if (pPict->repeat && !(unit == 0 && need_src_tile_y)) -+ txfilter |= R300_TX_CLAMP_T(R300_TX_CLAMP_WRAP); -+ else -+ txfilter |= R300_TX_CLAMP_T(R300_TX_CLAMP_CLAMP_GL); -+ -+ txfilter |= (unit << R300_TX_ID_SHIFT); - - switch (pPict->filter) { - case PictFilterNearest: -@@ -839,13 +1071,15 @@ static Bool FUNC_NAME(R300TextureSetup)(PicturePtr pPict, PixmapPtr pPix, - RADEON_FALLBACK(("Bad filter 0x%x\n", pPict->filter)); - } - -- BEGIN_ACCEL(6); -+ BEGIN_ACCEL(pPict->repeat ? 6 : 7); - OUT_ACCEL_REG(R300_TX_FILTER0_0 + (unit * 4), txfilter); -- OUT_ACCEL_REG(R300_TX_FILTER1_0 + (unit * 4), 0x0); -+ OUT_ACCEL_REG(R300_TX_FILTER1_0 + (unit * 4), 0); - OUT_ACCEL_REG(R300_TX_FORMAT0_0 + (unit * 4), txformat0); - OUT_ACCEL_REG(R300_TX_FORMAT1_0 + (unit * 4), txformat1); - OUT_ACCEL_REG(R300_TX_FORMAT2_0 + (unit * 4), txpitch); - OUT_ACCEL_REG(R300_TX_OFFSET_0 + (unit * 4), txoffset); -+ if (!pPict->repeat) -+ OUT_ACCEL_REG(R300_TX_BORDER_COLOR_0 + (unit * 4), 0); - FINISH_ACCEL(); - - if (pPict->transform != 0) { -@@ -863,12 +1097,12 @@ static Bool FUNC_NAME(R300TextureSetup)(PicturePtr pPict, PixmapPtr pPix, - static Bool R300CheckComposite(int op, PicturePtr pSrcPicture, PicturePtr pMaskPicture, - PicturePtr pDstPicture) - { -- CARD32 tmp1; -+ uint32_t tmp1; - ScreenPtr pScreen = pDstPicture->pDrawable->pScreen; - PixmapPtr pSrcPixmap, pDstPixmap; - ScrnInfoPtr pScrn = xf86Screens[pScreen->myNum]; -- xf86CrtcConfigPtr xf86_config = XF86_CRTC_CONFIG_PTR(pScrn); -- int i; -+ RADEONInfoPtr info = RADEONPTR(pScrn); -+ int max_tex_w, max_tex_h, max_dst_w, max_dst_h; - - TRACE; - -@@ -876,51 +1110,64 @@ static Bool R300CheckComposite(int op, PicturePtr pSrcPicture, PicturePtr pMaskP - if (op >= sizeof(RadeonBlendOp) / sizeof(RadeonBlendOp[0])) - RADEON_FALLBACK(("Unsupported Composite op 0x%x\n", op)); - --#if 1 -- /* Throw out cases that aren't going to be our rotation first */ -- if (pMaskPicture != NULL || op != PictOpSrc || pSrcPicture->pDrawable == NULL) -- RADEON_FALLBACK(("Junk driver\n")); -+ pSrcPixmap = RADEONGetDrawablePixmap(pSrcPicture->pDrawable); - -- if (pSrcPicture->pDrawable->type != DRAWABLE_WINDOW || -- pDstPicture->pDrawable->type != DRAWABLE_PIXMAP) { -- RADEON_FALLBACK(("bad drawable\n")); -+ if (IS_R500_3D) { -+ max_tex_w = 4096; -+ max_tex_h = 4096; -+ max_dst_w = 4096; -+ max_dst_h = 4096; -+ } else { -+ max_tex_w = 2048; -+ max_tex_h = 2048; -+ max_dst_w = 2560; -+ max_dst_h = 2560; - } - -- pSrcPixmap = (*pScreen->GetWindowPixmap) ((WindowPtr) pSrcPicture->pDrawable); -- pDstPixmap = (PixmapPtr)pDstPicture->pDrawable; -+ if (pSrcPixmap->drawable.width >= max_tex_w || -+ pSrcPixmap->drawable.height >= max_tex_h) { -+ RADEON_FALLBACK(("Source w/h too large (%d,%d).\n", -+ pSrcPixmap->drawable.width, -+ pSrcPixmap->drawable.height)); -+ } - -- /* Check if the dest is one of our shadow pixmaps */ -- for (i = 0; i < xf86_config->num_crtc; i++) { -- xf86CrtcPtr crtc = xf86_config->crtc[i]; -+ pDstPixmap = RADEONGetDrawablePixmap(pDstPicture->pDrawable); - -- if (crtc->rotatedPixmap == pDstPixmap) -- break; -+ if (pDstPixmap->drawable.width >= max_dst_w || -+ pDstPixmap->drawable.height >= max_dst_h) { -+ RADEON_FALLBACK(("Dest w/h too large (%d,%d).\n", -+ pDstPixmap->drawable.width, -+ pDstPixmap->drawable.height)); - } -- if (i == xf86_config->num_crtc) -- RADEON_FALLBACK(("no rotated pixmap\n")); - -- if (pSrcPixmap != pScreen->GetScreenPixmap(pScreen)) -- RADEON_FALLBACK(("src not screen\n")); --#endif -+ if (pMaskPicture) { -+ PixmapPtr pMaskPixmap = RADEONGetDrawablePixmap(pMaskPicture->pDrawable); - -+ if (pMaskPixmap->drawable.width >= max_tex_w || -+ pMaskPixmap->drawable.height >= max_tex_h) { -+ RADEON_FALLBACK(("Mask w/h too large (%d,%d).\n", -+ pMaskPixmap->drawable.width, -+ pMaskPixmap->drawable.height)); -+ } - -- if (pMaskPicture != NULL && pMaskPicture->componentAlpha) { -- /* Check if it's component alpha that relies on a source alpha and on -- * the source value. We can only get one of those into the single -- * source value that we get to blend with. -- */ -- if (RadeonBlendOp[op].src_alpha && -- (RadeonBlendOp[op].blend_cntl & RADEON_SRC_BLEND_MASK) != -- RADEON_SRC_BLEND_GL_ZERO) -- { -- RADEON_FALLBACK(("Component alpha not supported with source " -- "alpha and source value blending.\n")); -+ if (pMaskPicture->componentAlpha) { -+ /* Check if it's component alpha that relies on a source alpha and -+ * on the source value. We can only get one of those into the -+ * single source value that we get to blend with. -+ */ -+ if (RadeonBlendOp[op].src_alpha && -+ (RadeonBlendOp[op].blend_cntl & RADEON_SRC_BLEND_MASK) != -+ RADEON_SRC_BLEND_GL_ZERO) { -+ RADEON_FALLBACK(("Component alpha not supported with source " -+ "alpha and source value blending.\n")); -+ } - } -+ -+ if (!R300CheckCompositeTexture(pMaskPicture, pDstPicture, op, 1, IS_R500_3D)) -+ return FALSE; - } - -- if (!R300CheckCompositeTexture(pSrcPicture, 0)) -- return FALSE; -- if (pMaskPicture != NULL && !R300CheckCompositeTexture(pMaskPicture, 1)) -+ if (!R300CheckCompositeTexture(pSrcPicture, pDstPicture, op, 0, IS_R500_3D)) - return FALSE; - - if (!R300GetDestFormat(pDstPicture, &tmp1)) -@@ -936,11 +1183,10 @@ static Bool FUNC_NAME(R300PrepareComposite)(int op, PicturePtr pSrcPicture, - PixmapPtr pSrc, PixmapPtr pMask, PixmapPtr pDst) - { - RINFO_FROM_SCREEN(pDst->drawable.pScreen); -- CARD32 dst_format, dst_offset, dst_pitch; -- CARD32 txenable, colorpitch; -- CARD32 blendcntl; -+ uint32_t dst_format, dst_offset, dst_pitch; -+ uint32_t txenable, colorpitch; -+ uint32_t blendcntl; - int pixel_shift; -- int has_tcl = (info->ChipFamily != CHIP_FAMILY_RS690 && info->ChipFamily != CHIP_FAMILY_RS400); - ACCEL_PREAMBLE(); - - TRACE; -@@ -948,10 +1194,17 @@ static Bool FUNC_NAME(R300PrepareComposite)(int op, PicturePtr pSrcPicture, - if (!info->XInited3D) - RADEONInit3DEngine(pScrn); - -- R300GetDestFormat(pDstPicture, &dst_format); -+ if (!R300GetDestFormat(pDstPicture, &dst_format)) -+ return FALSE; -+ -+ if (pMask) -+ has_mask = TRUE; -+ else -+ has_mask = FALSE; -+ - pixel_shift = pDst->drawable.bitsPerPixel >> 4; - -- dst_offset = exaGetPixmapOffset(pDst) + info->fbLocation; -+ dst_offset = exaGetPixmapOffset(pDst) + info->fbLocation + pScrn->fbOffset; - dst_pitch = exaGetPixmapPitch(pDst); - colorpitch = dst_pitch >> pixel_shift; - -@@ -965,6 +1218,9 @@ static Bool FUNC_NAME(R300PrepareComposite)(int op, PicturePtr pSrcPicture, - if (((dst_pitch >> pixel_shift) & 0x7) != 0) - RADEON_FALLBACK(("Bad destination pitch 0x%x\n", (int)dst_pitch)); - -+ if (!RADEONSetupSourceTile(pSrcPicture, pSrc, TRUE, FALSE)) -+ return FALSE; -+ - if (!FUNC_NAME(R300TextureSetup)(pSrcPicture, pSrc, 0)) - return FALSE; - txenable = R300_TEX_0_ENABLE; -@@ -980,28 +1236,32 @@ static Bool FUNC_NAME(R300PrepareComposite)(int op, PicturePtr pSrcPicture, - RADEON_SWITCH_TO_3D(); - - /* setup the VAP */ -- -- if (has_tcl) { -- BEGIN_ACCEL(28); -- OUT_ACCEL_REG(R300_VAP_CNTL_STATUS, 0); -- OUT_ACCEL_REG(R300_VAP_PVS_STATE_FLUSH_REG, 0); -- OUT_ACCEL_REG(R300_VAP_CNTL, ((6 << R300_PVS_NUM_SLOTS_SHIFT) | -- (5 << R300_PVS_NUM_CNTLRS_SHIFT) | -- (4 << R300_PVS_NUM_FPUS_SHIFT) | -- (12 << R300_VF_MAX_VTX_NUM_SHIFT))); -+ if (info->has_tcl) { -+ if (pMask) -+ BEGIN_ACCEL(8); -+ else -+ BEGIN_ACCEL(7); - } else { -- BEGIN_ACCEL(10); -- OUT_ACCEL_REG(R300_VAP_CNTL_STATUS, R300_PVS_BYPASS); -- OUT_ACCEL_REG(R300_VAP_CNTL, ((10 << R300_PVS_NUM_SLOTS_SHIFT) | -- (5 << R300_PVS_NUM_CNTLRS_SHIFT) | -- (4 << R300_PVS_NUM_FPUS_SHIFT) | -- (5 << R300_VF_MAX_VTX_NUM_SHIFT))); -+ if (pMask) -+ BEGIN_ACCEL(6); -+ else -+ BEGIN_ACCEL(5); - } - -- OUT_ACCEL_REG(R300_VAP_VTE_CNTL, R300_VTX_XY_FMT | R300_VTX_Z_FMT); -- OUT_ACCEL_REG(R300_VAP_PSC_SGN_NORM_CNTL, 0); -- -- if (has_tcl) { -+ /* These registers define the number, type, and location of data submitted -+ * to the PVS unit of GA input (when PVS is disabled) -+ * DST_VEC_LOC is the slot in the PVS input vector memory when PVS/TCL is -+ * enabled. This memory provides the imputs to the vertex shader program -+ * and ordering is not important. When PVS/TCL is disabled, this field maps -+ * directly to the GA input memory and the order is signifigant. In -+ * PVS_BYPASS mode the order is as follows: -+ * Position -+ * Point Size -+ * Color 0-3 -+ * Textures 0-7 -+ * Fog -+ */ -+ if (pMask) { - OUT_ACCEL_REG(R300_VAP_PROG_STREAM_CNTL_0, - ((R300_DATA_TYPE_FLOAT_2 << R300_DATA_TYPE_0_SHIFT) | - (0 << R300_SKIP_DWORDS_0_SHIFT) | -@@ -1009,35 +1269,15 @@ static Bool FUNC_NAME(R300PrepareComposite)(int op, PicturePtr pSrcPicture, - R300_SIGNED_0 | - (R300_DATA_TYPE_FLOAT_2 << R300_DATA_TYPE_1_SHIFT) | - (0 << R300_SKIP_DWORDS_1_SHIFT) | -- (10 << R300_DST_VEC_LOC_1_SHIFT) | -+ (6 << R300_DST_VEC_LOC_1_SHIFT) | - R300_SIGNED_1)); - OUT_ACCEL_REG(R300_VAP_PROG_STREAM_CNTL_1, - ((R300_DATA_TYPE_FLOAT_2 << R300_DATA_TYPE_2_SHIFT) | - (0 << R300_SKIP_DWORDS_2_SHIFT) | -- (11 << R300_DST_VEC_LOC_2_SHIFT) | -+ (7 << R300_DST_VEC_LOC_2_SHIFT) | - R300_LAST_VEC_2 | - R300_SIGNED_2)); -- OUT_ACCEL_REG(R300_VAP_PROG_STREAM_CNTL_EXT_0, -- ((R300_SWIZZLE_SELECT_X << R300_SWIZZLE_SELECT_X_0_SHIFT) | -- (R300_SWIZZLE_SELECT_Y << R300_SWIZZLE_SELECT_Y_0_SHIFT) | -- (R300_SWIZZLE_SELECT_Z << R300_SWIZZLE_SELECT_Z_0_SHIFT) | -- (R300_SWIZZLE_SELECT_W << R300_SWIZZLE_SELECT_W_0_SHIFT) | -- ((R300_WRITE_ENA_X | R300_WRITE_ENA_Y | R300_WRITE_ENA_Z | R300_WRITE_ENA_W) -- << R300_WRITE_ENA_0_SHIFT) | -- (R300_SWIZZLE_SELECT_X << R300_SWIZZLE_SELECT_X_1_SHIFT) | -- (R300_SWIZZLE_SELECT_Y << R300_SWIZZLE_SELECT_Y_1_SHIFT) | -- (R300_SWIZZLE_SELECT_Z << R300_SWIZZLE_SELECT_Z_1_SHIFT) | -- (R300_SWIZZLE_SELECT_W << R300_SWIZZLE_SELECT_W_1_SHIFT) | -- ((R300_WRITE_ENA_X | R300_WRITE_ENA_Y | R300_WRITE_ENA_Z | R300_WRITE_ENA_W) -- << R300_WRITE_ENA_1_SHIFT))); -- OUT_ACCEL_REG(R300_VAP_PROG_STREAM_CNTL_EXT_1, -- ((R300_SWIZZLE_SELECT_X << R300_SWIZZLE_SELECT_X_2_SHIFT) | -- (R300_SWIZZLE_SELECT_Y << R300_SWIZZLE_SELECT_Y_2_SHIFT) | -- (R300_SWIZZLE_SELECT_Z << R300_SWIZZLE_SELECT_Z_2_SHIFT) | -- (R300_SWIZZLE_SELECT_W << R300_SWIZZLE_SELECT_W_2_SHIFT) | -- ((R300_WRITE_ENA_X | R300_WRITE_ENA_Y | R300_WRITE_ENA_Z | R300_WRITE_ENA_W) -- << R300_WRITE_ENA_2_SHIFT))); -- } else { -+ } else - OUT_ACCEL_REG(R300_VAP_PROG_STREAM_CNTL_0, - ((R300_DATA_TYPE_FLOAT_2 << R300_DATA_TYPE_0_SHIFT) | - (0 << R300_SKIP_DWORDS_0_SHIFT) | -@@ -1046,223 +1286,569 @@ static Bool FUNC_NAME(R300PrepareComposite)(int op, PicturePtr pSrcPicture, - (R300_DATA_TYPE_FLOAT_2 << R300_DATA_TYPE_1_SHIFT) | - (0 << R300_SKIP_DWORDS_1_SHIFT) | - (6 << R300_DST_VEC_LOC_1_SHIFT) | -+ R300_LAST_VEC_1 | - R300_SIGNED_1)); -- OUT_ACCEL_REG(R300_VAP_PROG_STREAM_CNTL_1, -- ((R300_DATA_TYPE_FLOAT_2 << R300_DATA_TYPE_2_SHIFT) | -- (0 << R300_SKIP_DWORDS_2_SHIFT) | -- (7 << R300_DST_VEC_LOC_2_SHIFT) | -- R300_LAST_VEC_2 | -- R300_SIGNED_2)); -- OUT_ACCEL_REG(R300_VAP_PROG_STREAM_CNTL_EXT_0, -- ((R300_SWIZZLE_SELECT_X << R300_SWIZZLE_SELECT_X_0_SHIFT) | -- (R300_SWIZZLE_SELECT_Y << R300_SWIZZLE_SELECT_Y_0_SHIFT) | -- (R300_SWIZZLE_SELECT_FP_ZERO << R300_SWIZZLE_SELECT_Z_0_SHIFT) | -- (R300_SWIZZLE_SELECT_FP_ONE << R300_SWIZZLE_SELECT_W_0_SHIFT) | -- ((R300_WRITE_ENA_X | R300_WRITE_ENA_Y) -- << R300_WRITE_ENA_0_SHIFT) | -- (R300_SWIZZLE_SELECT_X << R300_SWIZZLE_SELECT_X_1_SHIFT) | -- (R300_SWIZZLE_SELECT_Y << R300_SWIZZLE_SELECT_Y_1_SHIFT) | -- (R300_SWIZZLE_SELECT_FP_ZERO << R300_SWIZZLE_SELECT_Z_1_SHIFT) | -- (R300_SWIZZLE_SELECT_FP_ONE << R300_SWIZZLE_SELECT_W_1_SHIFT) | -- ((R300_WRITE_ENA_X | R300_WRITE_ENA_Y) -- << R300_WRITE_ENA_1_SHIFT))); -- OUT_ACCEL_REG(R300_VAP_PROG_STREAM_CNTL_EXT_1, -- ((R300_SWIZZLE_SELECT_X << R300_SWIZZLE_SELECT_X_2_SHIFT) | -- (R300_SWIZZLE_SELECT_Y << R300_SWIZZLE_SELECT_Y_2_SHIFT) | -- (R300_SWIZZLE_SELECT_FP_ZERO << R300_SWIZZLE_SELECT_Z_2_SHIFT) | -- (R300_SWIZZLE_SELECT_FP_ONE << R300_SWIZZLE_SELECT_W_2_SHIFT) | -- ((R300_WRITE_ENA_X | R300_WRITE_ENA_Y) -- << R300_WRITE_ENA_2_SHIFT))); -- } - -- /* setup the vertex shader */ -- if (has_tcl) { -- OUT_ACCEL_REG(R300_VAP_PVS_CODE_CNTL_0, -- ((0 << R300_PVS_FIRST_INST_SHIFT) | -- (1 << R300_PVS_XYZW_VALID_INST_SHIFT) | -- (1 << R300_PVS_LAST_INST_SHIFT))); -- OUT_ACCEL_REG(R300_VAP_PVS_CODE_CNTL_1, -- (1 << R300_PVS_LAST_VTX_SRC_INST_SHIFT)); -- OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_INDX_REG, 0); -- OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_DATA_REG,0x00f00203); -- OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_DATA_REG,0x00d10001); -- OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_DATA_REG,0x01248001); -- OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_DATA_REG,0x01248001); -- OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_DATA_REG,0x00f02203); -- OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_DATA_REG,0x00d10141); -- OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_DATA_REG,0x01248141); -- OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_DATA_REG,0x01248141); -- -- OUT_ACCEL_REG(R300_VAP_PVS_FLOW_CNTL_OPC, 0); -- -- OUT_ACCEL_REG(R300_VAP_GB_VERT_CLIP_ADJ, 0x3f800000); -- OUT_ACCEL_REG(R300_VAP_GB_VERT_DISC_ADJ, 0x3f800000); -- OUT_ACCEL_REG(R300_VAP_GB_HORZ_CLIP_ADJ, 0x3f800000); -- OUT_ACCEL_REG(R300_VAP_GB_HORZ_DISC_ADJ, 0x3f800000); -- OUT_ACCEL_REG(R300_VAP_CLIP_CNTL, R300_CLIP_DISABLE); -+ /* load the vertex shader -+ * We pre-load vertex programs in RADEONInit3DEngine(): -+ * - exa no mask -+ * - exa mask -+ * - Xv -+ * Here we select the offset of the vertex program we want to use -+ */ -+ if (info->has_tcl) { -+ if (pMask) { -+ OUT_ACCEL_REG(R300_VAP_PVS_CODE_CNTL_0, -+ ((0 << R300_PVS_FIRST_INST_SHIFT) | -+ (2 << R300_PVS_XYZW_VALID_INST_SHIFT) | -+ (2 << R300_PVS_LAST_INST_SHIFT))); -+ OUT_ACCEL_REG(R300_VAP_PVS_CODE_CNTL_1, -+ (2 << R300_PVS_LAST_VTX_SRC_INST_SHIFT)); -+ } else { -+ OUT_ACCEL_REG(R300_VAP_PVS_CODE_CNTL_0, -+ ((3 << R300_PVS_FIRST_INST_SHIFT) | -+ (4 << R300_PVS_XYZW_VALID_INST_SHIFT) | -+ (4 << R300_PVS_LAST_INST_SHIFT))); -+ OUT_ACCEL_REG(R300_VAP_PVS_CODE_CNTL_1, -+ (4 << R300_PVS_LAST_VTX_SRC_INST_SHIFT)); -+ } - } -+ -+ /* Position and one or two sets of 2 texture coordinates */ - OUT_ACCEL_REG(R300_VAP_OUT_VTX_FMT_0, R300_VTX_POS_PRESENT); -- OUT_ACCEL_REG(R300_VAP_OUT_VTX_FMT_1, -- ((2 << R300_TEX_0_COMP_CNT_SHIFT) | -- (2 << R300_TEX_1_COMP_CNT_SHIFT))); -+ if (pMask) -+ OUT_ACCEL_REG(R300_VAP_OUT_VTX_FMT_1, -+ ((2 << R300_TEX_0_COMP_CNT_SHIFT) | -+ (2 << R300_TEX_1_COMP_CNT_SHIFT))); -+ else -+ OUT_ACCEL_REG(R300_VAP_OUT_VTX_FMT_1, -+ (2 << R300_TEX_0_COMP_CNT_SHIFT)); - -+ OUT_ACCEL_REG(R300_TX_INVALTAGS, 0x0); -+ OUT_ACCEL_REG(R300_TX_ENABLE, txenable); - FINISH_ACCEL(); - - /* setup pixel shader */ -- if (IS_R300_VARIANT || info->ChipFamily == CHIP_FAMILY_RS690) { -- BEGIN_ACCEL(16); -- OUT_ACCEL_REG(R300_RS_COUNT, -- ((2 << R300_RS_COUNT_IT_COUNT_SHIFT) | -- R300_RS_COUNT_HIRES_EN)); -- OUT_ACCEL_REG(R300_RS_IP_0, -- (R300_RS_TEX_PTR(0) | -- R300_RS_COL_PTR(0) | -- R300_RS_COL_FMT(R300_RS_COL_FMT_RGBA) | -- R300_RS_SEL_S(R300_RS_SEL_C0) | -- R300_RS_SEL_T(R300_RS_SEL_C1) | -- R300_RS_SEL_R(R300_RS_SEL_K0) | -- R300_RS_SEL_Q(R300_RS_SEL_K1))); -- OUT_ACCEL_REG(R300_RS_INST_COUNT, R300_TX_OFFSET_RS(6)); -- OUT_ACCEL_REG(R300_RS_INST_0, R300_RS_INST_TEX_CN_WRITE); -- OUT_ACCEL_REG(R300_US_CONFIG, (0 << R300_NLEVEL_SHIFT) | R300_FIRST_TEX); -- OUT_ACCEL_REG(R300_US_PIXSIZE, 0); -- OUT_ACCEL_REG(R300_US_CODE_OFFSET, -- (R300_ALU_CODE_OFFSET(0) | -- R300_ALU_CODE_SIZE(1) | -- R300_TEX_CODE_OFFSET(0) | -- R300_TEX_CODE_SIZE(1))); -- OUT_ACCEL_REG(R300_US_CODE_ADDR_0, 0); -- OUT_ACCEL_REG(R300_US_CODE_ADDR_1, 0); -- OUT_ACCEL_REG(R300_US_CODE_ADDR_2, 0); -- OUT_ACCEL_REG(R300_US_CODE_ADDR_3, 0x400000); -- OUT_ACCEL_REG(R300_US_TEX_INST_0, 0x8000); -- OUT_ACCEL_REG(R300_US_ALU_RGB_ADDR_0, 0x1f800000); -- OUT_ACCEL_REG(R300_US_ALU_RGB_INST_0, 0x50a80); -- OUT_ACCEL_REG(R300_US_ALU_ALPHA_ADDR_0, 0x1800000); -- OUT_ACCEL_REG(R300_US_ALU_ALPHA_INST_0, 0x00040889); -- FINISH_ACCEL(); -- } else { -- BEGIN_ACCEL(23); -- OUT_ACCEL_REG(R300_RS_COUNT, -- ((2 << R300_RS_COUNT_IT_COUNT_SHIFT) | -- R300_RS_COUNT_HIRES_EN)); -- OUT_ACCEL_REG(R500_RS_IP_0, (0 << R500_RS_IP_TEX_PTR_S_SHIFT) | (1 << R500_RS_IP_TEX_PTR_T_SHIFT) | -- (R500_RS_IP_PTR_K0 << R500_RS_IP_TEX_PTR_R_SHIFT) | (R500_RS_IP_PTR_K1 << R500_RS_IP_TEX_PTR_Q_SHIFT)); -- -- OUT_ACCEL_REG(R300_RS_INST_COUNT, 0); -- OUT_ACCEL_REG(R500_RS_INST_0, R500_RS_INST_TEX_CN_WRITE); -- OUT_ACCEL_REG(R300_US_CONFIG, R500_ZERO_TIMES_ANYTHING_EQUALS_ZERO); -- OUT_ACCEL_REG(R300_US_PIXSIZE, 0); -- OUT_ACCEL_REG(R500_US_FC_CTRL, 0); -- OUT_ACCEL_REG(R500_US_CODE_ADDR, R500_US_CODE_START_ADDR(0) | R500_US_CODE_END_ADDR(1)); -- OUT_ACCEL_REG(R500_US_CODE_RANGE, R500_US_CODE_RANGE_ADDR(0) | R500_US_CODE_RANGE_SIZE(1)); -- OUT_ACCEL_REG(R500_US_CODE_OFFSET, 0); -- OUT_ACCEL_REG(R500_GA_US_VECTOR_INDEX, 0); -- // 7807 -- OUT_ACCEL_REG(R500_GA_US_VECTOR_DATA, R500_INST_TYPE_TEX | R500_INST_TEX_SEM_WAIT | -- R500_INST_RGB_WMASK_R | R500_INST_RGB_WMASK_G | R500_INST_RGB_WMASK_B | R500_INST_ALPHA_WMASK); -- -- OUT_ACCEL_REG(R500_GA_US_VECTOR_DATA, R500_TEX_ID(0) | R500_TEX_INST_LD | R500_TEX_SEM_ACQUIRE | -- R500_TEX_IGNORE_UNCOVERED); -- -- OUT_ACCEL_REG(R500_GA_US_VECTOR_DATA, R500_TEX_SRC_ADDR(0) | R500_TEX_SRC_S_SWIZ_R | R500_TEX_SRC_T_SWIZ_G | -- R500_TEX_DST_ADDR(0) | R500_TEX_DST_R_SWIZ_R | R500_TEX_DST_G_SWIZ_G | R500_TEX_DST_B_SWIZ_B | -- R500_TEX_DST_A_SWIZ_A); -- OUT_ACCEL_REG(R500_GA_US_VECTOR_DATA, 0x00000000); // TEX_ADDR_DXDY -- OUT_ACCEL_REG(R500_GA_US_VECTOR_DATA, 0x00000000); // mbz -- OUT_ACCEL_REG(R500_GA_US_VECTOR_DATA, 0x00000000); // mbz -- -- // 0x78105 -- OUT_ACCEL_REG(R500_GA_US_VECTOR_DATA, R500_INST_TYPE_OUT | R500_INST_TEX_SEM_WAIT | R500_INST_LAST | -- R500_INST_RGB_OMASK_R | R500_INST_RGB_OMASK_G | R500_INST_RGB_OMASK_B | R500_INST_ALPHA_OMASK); -- -- OUT_ACCEL_REG(R500_GA_US_VECTOR_DATA, R500_RGB_ADDR0(0) | R500_RGB_ADDR1(0) | R500_RGB_ADDR1_CONST | -- R500_RGB_ADDR2(0) | R500_RGB_ADDR2_CONST | R500_RGB_SRCP_OP_1_MINUS_2RGB0); //0x10040000 -- OUT_ACCEL_REG(R500_GA_US_VECTOR_DATA, R500_ALPHA_ADDR0(0) | R500_ALPHA_ADDR1(0) | R500_ALPHA_ADDR1_CONST | -- R500_ALPHA_ADDR2(0) | R500_ALPHA_ADDR2_CONST | R500_ALPHA_SRCP_OP_1_MINUS_2A0); //0x10040000 -- -- OUT_ACCEL_REG(R500_GA_US_VECTOR_DATA, -- R500_ALU_RGB_SEL_A_SRC0 | -- R500_ALU_RGB_R_SWIZ_A_R | R500_ALU_RGB_G_SWIZ_A_G | R500_ALU_RGB_B_SWIZ_A_B | -- R500_ALU_RGB_SEL_B_SRC0 | -- R500_ALU_RGB_R_SWIZ_B_1 | R500_ALU_RGB_B_SWIZ_B_1 | R500_ALU_RGB_G_SWIZ_B_1);//0x00db0220 -- -- OUT_ACCEL_REG(R500_GA_US_VECTOR_DATA, R500_ALPHA_OP_MAD | -- R500_ALPHA_SWIZ_A_A | R500_ALPHA_SWIZ_B_1);//0x00c0c000) -- -- OUT_ACCEL_REG(R500_GA_US_VECTOR_DATA, R500_ALU_RGBA_OP_MAD | -- R500_ALU_RGBA_R_SWIZ_0 | R500_ALU_RGBA_G_SWIZ_0 | R500_ALU_RGBA_B_SWIZ_0 | -- R500_ALU_RGBA_A_SWIZ_0);//0x20490000 -- FINISH_ACCEL(); -- } -+ if (IS_R300_3D) { -+ uint32_t output_fmt; -+ int src_color, src_alpha; -+ int mask_color, mask_alpha; - -- BEGIN_ACCEL(6); -- OUT_ACCEL_REG(R300_TX_INVALTAGS, 0x0); -- OUT_ACCEL_REG(R300_TX_ENABLE, txenable); -+ if (PICT_FORMAT_RGB(pSrcPicture->format) == 0) -+ src_color = R300_ALU_RGB_0_0; -+ else -+ src_color = R300_ALU_RGB_SRC0_RGB; - -- OUT_ACCEL_REG(R300_RB3D_COLOROFFSET0, dst_offset); -- OUT_ACCEL_REG(R300_RB3D_COLORPITCH0, colorpitch); -+ if (PICT_FORMAT_A(pSrcPicture->format) == 0) -+ src_alpha = R300_ALU_ALPHA_1_0; -+ else -+ src_alpha = R300_ALU_ALPHA_SRC0_A; -+ -+ if (pMask && pMaskPicture->componentAlpha) { -+ if (RadeonBlendOp[op].src_alpha) { -+ if (PICT_FORMAT_A(pSrcPicture->format) == 0) { -+ src_color = R300_ALU_RGB_1_0; -+ src_alpha = R300_ALU_ALPHA_1_0; -+ } else { -+ src_color = R300_ALU_RGB_SRC0_AAA; -+ src_alpha = R300_ALU_ALPHA_SRC0_A; -+ } -+ -+ mask_color = R300_ALU_RGB_SRC1_RGB; -+ -+ if (PICT_FORMAT_A(pMaskPicture->format) == 0) -+ mask_alpha = R300_ALU_ALPHA_1_0; -+ else -+ mask_alpha = R300_ALU_ALPHA_SRC1_A; -+ -+ } else { -+ src_color = R300_ALU_RGB_SRC0_RGB; -+ -+ if (PICT_FORMAT_A(pSrcPicture->format) == 0) -+ src_alpha = R300_ALU_ALPHA_1_0; -+ else -+ src_alpha = R300_ALU_ALPHA_SRC0_A; -+ -+ mask_color = R300_ALU_RGB_SRC1_RGB; -+ -+ if (PICT_FORMAT_A(pMaskPicture->format) == 0) -+ mask_alpha = R300_ALU_ALPHA_1_0; -+ else -+ mask_alpha = R300_ALU_ALPHA_SRC1_A; -+ -+ } -+ } else if (pMask) { -+ if (PICT_FORMAT_A(pMaskPicture->format) == 0) -+ mask_color = R300_ALU_RGB_1_0; -+ else -+ mask_color = R300_ALU_RGB_SRC1_AAA; -+ -+ if (PICT_FORMAT_A(pMaskPicture->format) == 0) -+ mask_alpha = R300_ALU_ALPHA_1_0; -+ else -+ mask_alpha = R300_ALU_ALPHA_SRC1_A; -+ } else { -+ mask_color = R300_ALU_RGB_1_0; -+ mask_alpha = R300_ALU_ALPHA_1_0; -+ } - -- blendcntl = RADEONGetBlendCntl(op, pMaskPicture, pDstPicture->format); -- OUT_ACCEL_REG(R300_RB3D_BLENDCNTL, blendcntl); -- OUT_ACCEL_REG(R300_RB3D_ABLENDCNTL, 0); -+ /* shader output swizzling */ -+ switch (pDstPicture->format) { -+ case PICT_a8r8g8b8: -+ case PICT_x8r8g8b8: -+ default: -+ output_fmt = (R300_OUT_FMT_C4_8 | -+ R300_OUT_FMT_C0_SEL_BLUE | -+ R300_OUT_FMT_C1_SEL_GREEN | -+ R300_OUT_FMT_C2_SEL_RED | -+ R300_OUT_FMT_C3_SEL_ALPHA); -+ break; -+ case PICT_a8b8g8r8: -+ case PICT_x8b8g8r8: -+ output_fmt = (R300_OUT_FMT_C4_8 | -+ R300_OUT_FMT_C0_SEL_RED | -+ R300_OUT_FMT_C1_SEL_GREEN | -+ R300_OUT_FMT_C2_SEL_BLUE | -+ R300_OUT_FMT_C3_SEL_ALPHA); -+ break; -+ case PICT_a8: -+ output_fmt = (R300_OUT_FMT_C4_8 | -+ R300_OUT_FMT_C0_SEL_ALPHA); -+ break; -+ } - --#if 0 -- /* IN operator: Multiply src by mask components or mask alpha. -- * BLEND_CTL_ADD is A * B + C. -- * If a picture is a8, we have to explicitly zero its color values. -- * If the destination is a8, we have to route the alpha to red, I think. -- * If we're doing component alpha where the source for blending is going to -- * be the source alpha (and there's no source value used), we have to zero -- * the source's color values. -- */ -- cblend = R200_TXC_OP_MADD | R200_TXC_ARG_C_ZERO; -- ablend = R200_TXA_OP_MADD | R200_TXA_ARG_C_ZERO; - -- if (pDstPicture->format == PICT_a8 || -- (pMask && pMaskPicture->componentAlpha && RadeonBlendOp[op].src_alpha)) -- { -- cblend |= R200_TXC_ARG_A_R0_ALPHA; -- } else if (pSrcPicture->format == PICT_a8) -- cblend |= R200_TXC_ARG_A_ZERO; -- else -- cblend |= R200_TXC_ARG_A_R0_COLOR; -- ablend |= R200_TXA_ARG_A_R0_ALPHA; -+ /* setup the rasterizer, load FS */ -+ BEGIN_ACCEL(9); -+ if (pMask) { -+ /* 4 components: 2 for tex0, 2 for tex1 */ -+ OUT_ACCEL_REG(R300_RS_COUNT, -+ ((4 << R300_RS_COUNT_IT_COUNT_SHIFT) | -+ R300_RS_COUNT_HIRES_EN)); -+ -+ /* R300_INST_COUNT_RS - highest RS instruction used */ -+ OUT_ACCEL_REG(R300_RS_INST_COUNT, R300_INST_COUNT_RS(1) | R300_TX_OFFSET_RS(6)); -+ -+ OUT_ACCEL_REG(R300_US_CODE_OFFSET, (R300_ALU_CODE_OFFSET(0) | -+ R300_ALU_CODE_SIZE(0) | -+ R300_TEX_CODE_OFFSET(0) | -+ R300_TEX_CODE_SIZE(1))); -+ -+ OUT_ACCEL_REG(R300_US_CODE_ADDR_3, -+ (R300_ALU_START(0) | -+ R300_ALU_SIZE(0) | -+ R300_TEX_START(0) | -+ R300_TEX_SIZE(1) | -+ R300_RGBA_OUT)); -+ } else { -+ /* 2 components: 2 for tex0 */ -+ OUT_ACCEL_REG(R300_RS_COUNT, -+ ((2 << R300_RS_COUNT_IT_COUNT_SHIFT) | -+ R300_RS_COUNT_HIRES_EN)); -+ -+ OUT_ACCEL_REG(R300_RS_INST_COUNT, R300_INST_COUNT_RS(0) | R300_TX_OFFSET_RS(6)); -+ -+ OUT_ACCEL_REG(R300_US_CODE_OFFSET, (R300_ALU_CODE_OFFSET(0) | -+ R300_ALU_CODE_SIZE(0) | -+ R300_TEX_CODE_OFFSET(0) | -+ R300_TEX_CODE_SIZE(0))); -+ -+ OUT_ACCEL_REG(R300_US_CODE_ADDR_3, -+ (R300_ALU_START(0) | -+ R300_ALU_SIZE(0) | -+ R300_TEX_START(0) | -+ R300_TEX_SIZE(0) | -+ R300_RGBA_OUT)); -+ } - -- if (pMask) { -- if (pMaskPicture->componentAlpha && -- pDstPicture->format != PICT_a8) -- cblend |= R200_TXC_ARG_B_R1_COLOR; -- else -- cblend |= R200_TXC_ARG_B_R1_ALPHA; -- ablend |= R200_TXA_ARG_B_R1_ALPHA; -+ /* shader output swizzling */ -+ OUT_ACCEL_REG(R300_US_OUT_FMT_0, output_fmt); -+ -+ /* tex inst for src texture is pre-loaded in RADEONInit3DEngine() */ -+ /* tex inst for mask texture is pre-loaded in RADEONInit3DEngine() */ -+ -+ /* RGB inst -+ * temp addresses for texture inputs -+ * ALU_RGB_ADDR0 is src tex (temp 0) -+ * ALU_RGB_ADDR1 is mask tex (temp 1) -+ * R300_ALU_RGB_OMASK - output components to write -+ * R300_ALU_RGB_TARGET_A - render target -+ */ -+ OUT_ACCEL_REG(R300_US_ALU_RGB_ADDR_0, -+ (R300_ALU_RGB_ADDR0(0) | -+ R300_ALU_RGB_ADDR1(1) | -+ R300_ALU_RGB_ADDR2(0) | -+ R300_ALU_RGB_ADDRD(0) | -+ R300_ALU_RGB_OMASK((R300_ALU_RGB_MASK_R | -+ R300_ALU_RGB_MASK_G | -+ R300_ALU_RGB_MASK_B)) | -+ R300_ALU_RGB_TARGET_A)); -+ /* RGB inst -+ * ALU operation -+ */ -+ OUT_ACCEL_REG(R300_US_ALU_RGB_INST_0, -+ (R300_ALU_RGB_SEL_A(src_color) | -+ R300_ALU_RGB_MOD_A(R300_ALU_RGB_MOD_NOP) | -+ R300_ALU_RGB_SEL_B(mask_color) | -+ R300_ALU_RGB_MOD_B(R300_ALU_RGB_MOD_NOP) | -+ R300_ALU_RGB_SEL_C(R300_ALU_RGB_0_0) | -+ R300_ALU_RGB_MOD_C(R300_ALU_RGB_MOD_NOP) | -+ R300_ALU_RGB_OP(R300_ALU_RGB_OP_MAD) | -+ R300_ALU_RGB_OMOD(R300_ALU_RGB_OMOD_NONE) | -+ R300_ALU_RGB_CLAMP)); -+ /* Alpha inst -+ * temp addresses for texture inputs -+ * ALU_ALPHA_ADDR0 is src tex (0) -+ * ALU_ALPHA_ADDR1 is mask tex (1) -+ * R300_ALU_ALPHA_OMASK - output components to write -+ * R300_ALU_ALPHA_TARGET_A - render target -+ */ -+ OUT_ACCEL_REG(R300_US_ALU_ALPHA_ADDR_0, -+ (R300_ALU_ALPHA_ADDR0(0) | -+ R300_ALU_ALPHA_ADDR1(1) | -+ R300_ALU_ALPHA_ADDR2(0) | -+ R300_ALU_ALPHA_ADDRD(0) | -+ R300_ALU_ALPHA_OMASK(R300_ALU_ALPHA_MASK_A) | -+ R300_ALU_ALPHA_TARGET_A | -+ R300_ALU_ALPHA_OMASK_W(R300_ALU_ALPHA_MASK_NONE))); -+ /* Alpha inst -+ * ALU operation -+ */ -+ OUT_ACCEL_REG(R300_US_ALU_ALPHA_INST_0, -+ (R300_ALU_ALPHA_SEL_A(src_alpha) | -+ R300_ALU_ALPHA_MOD_A(R300_ALU_ALPHA_MOD_NOP) | -+ R300_ALU_ALPHA_SEL_B(mask_alpha) | -+ R300_ALU_ALPHA_MOD_B(R300_ALU_ALPHA_MOD_NOP) | -+ R300_ALU_ALPHA_SEL_C(R300_ALU_ALPHA_0_0) | -+ R300_ALU_ALPHA_MOD_C(R300_ALU_ALPHA_MOD_NOP) | -+ R300_ALU_ALPHA_OP(R300_ALU_ALPHA_OP_MAD) | -+ R300_ALU_ALPHA_OMOD(R300_ALU_ALPHA_OMOD_NONE) | -+ R300_ALU_ALPHA_CLAMP)); -+ FINISH_ACCEL(); - } else { -- cblend |= R200_TXC_ARG_B_ZERO | R200_TXC_COMP_ARG_B; -- ablend |= R200_TXA_ARG_B_ZERO | R200_TXA_COMP_ARG_B; -+ uint32_t output_fmt; -+ uint32_t src_color, src_alpha; -+ uint32_t mask_color, mask_alpha; -+ -+ if (PICT_FORMAT_RGB(pSrcPicture->format) == 0) -+ src_color = (R500_ALU_RGB_R_SWIZ_A_0 | -+ R500_ALU_RGB_G_SWIZ_A_0 | -+ R500_ALU_RGB_B_SWIZ_A_0); -+ else -+ src_color = (R500_ALU_RGB_R_SWIZ_A_R | -+ R500_ALU_RGB_G_SWIZ_A_G | -+ R500_ALU_RGB_B_SWIZ_A_B); -+ -+ if (PICT_FORMAT_A(pSrcPicture->format) == 0) -+ src_alpha = R500_ALPHA_SWIZ_A_1; -+ else -+ src_alpha = R500_ALPHA_SWIZ_A_A; -+ -+ if (pMask && pMaskPicture->componentAlpha) { -+ if (RadeonBlendOp[op].src_alpha) { -+ if (PICT_FORMAT_A(pSrcPicture->format) == 0) { -+ src_color = (R500_ALU_RGB_R_SWIZ_A_1 | -+ R500_ALU_RGB_G_SWIZ_A_1 | -+ R500_ALU_RGB_B_SWIZ_A_1); -+ src_alpha = R500_ALPHA_SWIZ_A_1; -+ } else { -+ src_color = (R500_ALU_RGB_R_SWIZ_A_A | -+ R500_ALU_RGB_G_SWIZ_A_A | -+ R500_ALU_RGB_B_SWIZ_A_A); -+ src_alpha = R500_ALPHA_SWIZ_A_A; -+ } -+ -+ mask_color = (R500_ALU_RGB_R_SWIZ_B_R | -+ R500_ALU_RGB_G_SWIZ_B_G | -+ R500_ALU_RGB_B_SWIZ_B_B); -+ -+ if (PICT_FORMAT_A(pMaskPicture->format) == 0) -+ mask_alpha = R500_ALPHA_SWIZ_B_1; -+ else -+ mask_alpha = R500_ALPHA_SWIZ_B_A; -+ -+ } else { -+ src_color = (R500_ALU_RGB_R_SWIZ_A_R | -+ R500_ALU_RGB_G_SWIZ_A_G | -+ R500_ALU_RGB_B_SWIZ_A_B); -+ -+ if (PICT_FORMAT_A(pSrcPicture->format) == 0) -+ src_alpha = R500_ALPHA_SWIZ_A_1; -+ else -+ src_alpha = R500_ALPHA_SWIZ_A_A; -+ -+ mask_color = (R500_ALU_RGB_R_SWIZ_B_R | -+ R500_ALU_RGB_G_SWIZ_B_G | -+ R500_ALU_RGB_B_SWIZ_B_B); -+ -+ if (PICT_FORMAT_A(pMaskPicture->format) == 0) -+ mask_alpha = R500_ALPHA_SWIZ_B_1; -+ else -+ mask_alpha = R500_ALPHA_SWIZ_B_A; -+ -+ } -+ } else if (pMask) { -+ if (PICT_FORMAT_A(pMaskPicture->format) == 0) -+ mask_color = (R500_ALU_RGB_R_SWIZ_B_1 | -+ R500_ALU_RGB_G_SWIZ_B_1 | -+ R500_ALU_RGB_B_SWIZ_B_1); -+ else -+ mask_color = (R500_ALU_RGB_R_SWIZ_B_A | -+ R500_ALU_RGB_G_SWIZ_B_A | -+ R500_ALU_RGB_B_SWIZ_B_A); -+ -+ if (PICT_FORMAT_A(pMaskPicture->format) == 0) -+ mask_alpha = R500_ALPHA_SWIZ_B_1; -+ else -+ mask_alpha = R500_ALPHA_SWIZ_B_A; -+ } else { -+ mask_color = (R500_ALU_RGB_R_SWIZ_B_1 | -+ R500_ALU_RGB_G_SWIZ_B_1 | -+ R500_ALU_RGB_B_SWIZ_B_1); -+ mask_alpha = R500_ALPHA_SWIZ_B_1; -+ } -+ -+ /* shader output swizzling */ -+ switch (pDstPicture->format) { -+ case PICT_a8r8g8b8: -+ case PICT_x8r8g8b8: -+ default: -+ output_fmt = (R300_OUT_FMT_C4_8 | -+ R300_OUT_FMT_C0_SEL_BLUE | -+ R300_OUT_FMT_C1_SEL_GREEN | -+ R300_OUT_FMT_C2_SEL_RED | -+ R300_OUT_FMT_C3_SEL_ALPHA); -+ break; -+ case PICT_a8b8g8r8: -+ case PICT_x8b8g8r8: -+ output_fmt = (R300_OUT_FMT_C4_8 | -+ R300_OUT_FMT_C0_SEL_RED | -+ R300_OUT_FMT_C1_SEL_GREEN | -+ R300_OUT_FMT_C2_SEL_BLUE | -+ R300_OUT_FMT_C3_SEL_ALPHA); -+ break; -+ case PICT_a8: -+ output_fmt = (R300_OUT_FMT_C4_8 | -+ R300_OUT_FMT_C0_SEL_ALPHA); -+ break; -+ } -+ -+ BEGIN_ACCEL(6); -+ if (pMask) { -+ /* 4 components: 2 for tex0, 2 for tex1 */ -+ OUT_ACCEL_REG(R300_RS_COUNT, -+ ((4 << R300_RS_COUNT_IT_COUNT_SHIFT) | -+ R300_RS_COUNT_HIRES_EN)); -+ -+ /* 2 RS instructions: 1 for tex0 (src), 1 for tex1 (mask) */ -+ OUT_ACCEL_REG(R300_RS_INST_COUNT, R300_INST_COUNT_RS(1) | R300_TX_OFFSET_RS(6)); -+ -+ OUT_ACCEL_REG(R500_US_CODE_ADDR, (R500_US_CODE_START_ADDR(0) | -+ R500_US_CODE_END_ADDR(2))); -+ OUT_ACCEL_REG(R500_US_CODE_RANGE, (R500_US_CODE_RANGE_ADDR(0) | -+ R500_US_CODE_RANGE_SIZE(2))); -+ OUT_ACCEL_REG(R500_US_CODE_OFFSET, 0); -+ } else { -+ OUT_ACCEL_REG(R300_RS_COUNT, -+ ((2 << R300_RS_COUNT_IT_COUNT_SHIFT) | -+ R300_RS_COUNT_HIRES_EN)); -+ -+ OUT_ACCEL_REG(R300_RS_INST_COUNT, R300_INST_COUNT_RS(0) | R300_TX_OFFSET_RS(6)); -+ -+ OUT_ACCEL_REG(R500_US_CODE_ADDR, (R500_US_CODE_START_ADDR(0) | -+ R500_US_CODE_END_ADDR(1))); -+ OUT_ACCEL_REG(R500_US_CODE_RANGE, (R500_US_CODE_RANGE_ADDR(0) | -+ R500_US_CODE_RANGE_SIZE(1))); -+ OUT_ACCEL_REG(R500_US_CODE_OFFSET, 0); -+ } -+ -+ OUT_ACCEL_REG(R300_US_OUT_FMT_0, output_fmt); -+ FINISH_ACCEL(); -+ -+ if (pMask) { -+ BEGIN_ACCEL(19); -+ OUT_ACCEL_REG(R500_GA_US_VECTOR_INDEX, 0); -+ /* tex inst for src texture */ -+ OUT_ACCEL_REG(R500_GA_US_VECTOR_DATA, (R500_INST_TYPE_TEX | -+ R500_INST_RGB_WMASK_R | -+ R500_INST_RGB_WMASK_G | -+ R500_INST_RGB_WMASK_B | -+ R500_INST_ALPHA_WMASK | -+ R500_INST_RGB_CLAMP | -+ R500_INST_ALPHA_CLAMP)); -+ -+ OUT_ACCEL_REG(R500_GA_US_VECTOR_DATA, (R500_TEX_ID(0) | -+ R500_TEX_INST_LD | -+ R500_TEX_IGNORE_UNCOVERED)); -+ -+ OUT_ACCEL_REG(R500_GA_US_VECTOR_DATA, (R500_TEX_SRC_ADDR(0) | -+ R500_TEX_SRC_S_SWIZ_R | -+ R500_TEX_SRC_T_SWIZ_G | -+ R500_TEX_DST_ADDR(0) | -+ R500_TEX_DST_R_SWIZ_R | -+ R500_TEX_DST_G_SWIZ_G | -+ R500_TEX_DST_B_SWIZ_B | -+ R500_TEX_DST_A_SWIZ_A)); -+ OUT_ACCEL_REG(R500_GA_US_VECTOR_DATA, (R500_DX_ADDR(0) | -+ R500_DX_S_SWIZ_R | -+ R500_DX_T_SWIZ_R | -+ R500_DX_R_SWIZ_R | -+ R500_DX_Q_SWIZ_R | -+ R500_DY_ADDR(0) | -+ R500_DY_S_SWIZ_R | -+ R500_DY_T_SWIZ_R | -+ R500_DY_R_SWIZ_R | -+ R500_DY_Q_SWIZ_R)); -+ OUT_ACCEL_REG(R500_GA_US_VECTOR_DATA, 0x00000000); -+ OUT_ACCEL_REG(R500_GA_US_VECTOR_DATA, 0x00000000); -+ -+ /* tex inst for mask texture */ -+ OUT_ACCEL_REG(R500_GA_US_VECTOR_DATA, (R500_INST_TYPE_TEX | -+ R500_INST_TEX_SEM_WAIT | -+ R500_INST_RGB_WMASK_R | -+ R500_INST_RGB_WMASK_G | -+ R500_INST_RGB_WMASK_B | -+ R500_INST_ALPHA_WMASK | -+ R500_INST_RGB_CLAMP | -+ R500_INST_ALPHA_CLAMP)); -+ -+ OUT_ACCEL_REG(R500_GA_US_VECTOR_DATA, (R500_TEX_ID(1) | -+ R500_TEX_INST_LD | -+ R500_TEX_SEM_ACQUIRE | -+ R500_TEX_IGNORE_UNCOVERED)); -+ -+ OUT_ACCEL_REG(R500_GA_US_VECTOR_DATA, (R500_TEX_SRC_ADDR(1) | -+ R500_TEX_SRC_S_SWIZ_R | -+ R500_TEX_SRC_T_SWIZ_G | -+ R500_TEX_DST_ADDR(1) | -+ R500_TEX_DST_R_SWIZ_R | -+ R500_TEX_DST_G_SWIZ_G | -+ R500_TEX_DST_B_SWIZ_B | -+ R500_TEX_DST_A_SWIZ_A)); -+ OUT_ACCEL_REG(R500_GA_US_VECTOR_DATA, (R500_DX_ADDR(1) | -+ R500_DX_S_SWIZ_R | -+ R500_DX_T_SWIZ_R | -+ R500_DX_R_SWIZ_R | -+ R500_DX_Q_SWIZ_R | -+ R500_DY_ADDR(1) | -+ R500_DY_S_SWIZ_R | -+ R500_DY_T_SWIZ_R | -+ R500_DY_R_SWIZ_R | -+ R500_DY_Q_SWIZ_R)); -+ OUT_ACCEL_REG(R500_GA_US_VECTOR_DATA, 0x00000000); -+ OUT_ACCEL_REG(R500_GA_US_VECTOR_DATA, 0x00000000); -+ } else { -+ BEGIN_ACCEL(13); -+ OUT_ACCEL_REG(R500_GA_US_VECTOR_INDEX, 0); -+ /* tex inst for src texture */ -+ OUT_ACCEL_REG(R500_GA_US_VECTOR_DATA, (R500_INST_TYPE_TEX | -+ R500_INST_TEX_SEM_WAIT | -+ R500_INST_RGB_WMASK_R | -+ R500_INST_RGB_WMASK_G | -+ R500_INST_RGB_WMASK_B | -+ R500_INST_ALPHA_WMASK | -+ R500_INST_RGB_CLAMP | -+ R500_INST_ALPHA_CLAMP)); -+ -+ OUT_ACCEL_REG(R500_GA_US_VECTOR_DATA, (R500_TEX_ID(0) | -+ R500_TEX_INST_LD | -+ R500_TEX_SEM_ACQUIRE | -+ R500_TEX_IGNORE_UNCOVERED)); -+ -+ OUT_ACCEL_REG(R500_GA_US_VECTOR_DATA, (R500_TEX_SRC_ADDR(0) | -+ R500_TEX_SRC_S_SWIZ_R | -+ R500_TEX_SRC_T_SWIZ_G | -+ R500_TEX_DST_ADDR(0) | -+ R500_TEX_DST_R_SWIZ_R | -+ R500_TEX_DST_G_SWIZ_G | -+ R500_TEX_DST_B_SWIZ_B | -+ R500_TEX_DST_A_SWIZ_A)); -+ OUT_ACCEL_REG(R500_GA_US_VECTOR_DATA, (R500_DX_ADDR(0) | -+ R500_DX_S_SWIZ_R | -+ R500_DX_T_SWIZ_R | -+ R500_DX_R_SWIZ_R | -+ R500_DX_Q_SWIZ_R | -+ R500_DY_ADDR(0) | -+ R500_DY_S_SWIZ_R | -+ R500_DY_T_SWIZ_R | -+ R500_DY_R_SWIZ_R | -+ R500_DY_Q_SWIZ_R)); -+ OUT_ACCEL_REG(R500_GA_US_VECTOR_DATA, 0x00000000); -+ OUT_ACCEL_REG(R500_GA_US_VECTOR_DATA, 0x00000000); -+ } -+ -+ /* ALU inst */ -+ /* *_OMASK* - output component write mask */ -+ OUT_ACCEL_REG(R500_GA_US_VECTOR_DATA, (R500_INST_TYPE_OUT | -+ R500_INST_TEX_SEM_WAIT | -+ R500_INST_LAST | -+ R500_INST_RGB_OMASK_R | -+ R500_INST_RGB_OMASK_G | -+ R500_INST_RGB_OMASK_B | -+ R500_INST_ALPHA_OMASK | -+ R500_INST_RGB_CLAMP | -+ R500_INST_ALPHA_CLAMP)); -+ /* ALU inst -+ * temp addresses for texture inputs -+ * RGB_ADDR0 is src tex (temp 0) -+ * RGB_ADDR1 is mask tex (temp 1) -+ */ -+ OUT_ACCEL_REG(R500_GA_US_VECTOR_DATA, (R500_RGB_ADDR0(0) | -+ R500_RGB_ADDR1(1) | -+ R500_RGB_ADDR2(0))); -+ /* ALU inst -+ * temp addresses for texture inputs -+ * ALPHA_ADDR0 is src tex (temp 0) -+ * ALPHA_ADDR1 is mask tex (temp 1) -+ */ -+ OUT_ACCEL_REG(R500_GA_US_VECTOR_DATA, (R500_ALPHA_ADDR0(0) | -+ R500_ALPHA_ADDR1(1) | -+ R500_ALPHA_ADDR2(0))); -+ -+ /* R500_ALU_RGB_TARGET - RGB render target */ -+ OUT_ACCEL_REG(R500_GA_US_VECTOR_DATA, (R500_ALU_RGB_SEL_A_SRC0 | -+ src_color | -+ R500_ALU_RGB_SEL_B_SRC1 | -+ mask_color | -+ R500_ALU_RGB_TARGET(0))); -+ -+ /* R500_ALPHA_RGB_TARGET - alpha render target */ -+ OUT_ACCEL_REG(R500_GA_US_VECTOR_DATA, (R500_ALPHA_OP_MAD | -+ R500_ALPHA_ADDRD(0) | -+ R500_ALPHA_SEL_A_SRC0 | -+ src_alpha | -+ R500_ALPHA_SEL_B_SRC1 | -+ mask_alpha | -+ R500_ALPHA_TARGET(0))); -+ -+ OUT_ACCEL_REG(R500_GA_US_VECTOR_DATA, (R500_ALU_RGBA_OP_MAD | -+ R500_ALU_RGBA_ADDRD(0) | -+ R500_ALU_RGBA_R_SWIZ_0 | -+ R500_ALU_RGBA_G_SWIZ_0 | -+ R500_ALU_RGBA_B_SWIZ_0 | -+ R500_ALU_RGBA_A_SWIZ_0)); -+ FINISH_ACCEL(); - } - -- OUT_ACCEL_REG(R200_PP_TXCBLEND_0, cblend); -- OUT_ACCEL_REG(R200_PP_TXCBLEND2_0, -- R200_TXC_CLAMP_0_1 | R200_TXC_OUTPUT_REG_R0); -- OUT_ACCEL_REG(R200_PP_TXABLEND_0, ablend); -- OUT_ACCEL_REG(R200_PP_TXABLEND2_0, -- R200_TXA_CLAMP_0_1 | R200_TXA_OUTPUT_REG_R0); -+ BEGIN_ACCEL(3); -+ -+ OUT_ACCEL_REG(R300_RB3D_COLOROFFSET0, dst_offset); -+ OUT_ACCEL_REG(R300_RB3D_COLORPITCH0, colorpitch); - -- /* Op operator. */ - blendcntl = RADEONGetBlendCntl(op, pMaskPicture, pDstPicture->format); -- OUT_ACCEL_REG(RADEON_RB3D_BLENDCNTL, blendcntl); --#endif -+ OUT_ACCEL_REG(R300_RB3D_BLENDCNTL, blendcntl | R300_ALPHA_BLEND_ENABLE | R300_READ_ENABLE); - - FINISH_ACCEL(); - - return TRUE; - } - --#define VTX_COUNT 6 -+#define VTX_COUNT_MASK 6 -+#define VTX_COUNT 4 - - #ifdef ACCEL_CP - --#define VTX_OUT(_dstX, _dstY, _srcX, _srcY, _maskX, _maskY) \ -+#define VTX_OUT_MASK(_dstX, _dstY, _srcX, _srcY, _maskX, _maskY) \ - do { \ - OUT_RING_F(_dstX); \ - OUT_RING_F(_dstY); \ -@@ -1272,9 +1858,17 @@ do { \ - OUT_RING_F(_maskY); \ - } while (0) - -+#define VTX_OUT(_dstX, _dstY, _srcX, _srcY) \ -+do { \ -+ OUT_RING_F(_dstX); \ -+ OUT_RING_F(_dstY); \ -+ OUT_RING_F(_srcX); \ -+ OUT_RING_F(_srcY); \ -+} while (0) -+ - #else /* ACCEL_CP */ - --#define VTX_OUT(_dstX, _dstY, _srcX, _srcY, _maskX, _maskY) \ -+#define VTX_OUT_MASK(_dstX, _dstY, _srcX, _srcY, _maskX, _maskY) \ - do { \ - OUT_ACCEL_REG_F(RADEON_SE_PORT_DATA0, _dstX); \ - OUT_ACCEL_REG_F(RADEON_SE_PORT_DATA0, _dstY); \ -@@ -1284,6 +1878,14 @@ do { \ - OUT_ACCEL_REG_F(RADEON_SE_PORT_DATA0, _maskY); \ - } while (0) - -+#define VTX_OUT(_dstX, _dstY, _srcX, _srcY) \ -+do { \ -+ OUT_ACCEL_REG_F(RADEON_SE_PORT_DATA0, _dstX); \ -+ OUT_ACCEL_REG_F(RADEON_SE_PORT_DATA0, _dstY); \ -+ OUT_ACCEL_REG_F(RADEON_SE_PORT_DATA0, _srcX); \ -+ OUT_ACCEL_REG_F(RADEON_SE_PORT_DATA0, _srcY); \ -+} while (0) -+ - #endif /* !ACCEL_CP */ - - #ifdef ONLY_ONCE -@@ -1299,11 +1901,11 @@ static inline void transformPoint(PictTransform *transform, xPointFixed *point) - } - #endif - --static void FUNC_NAME(RadeonComposite)(PixmapPtr pDst, -- int srcX, int srcY, -- int maskX, int maskY, -- int dstX, int dstY, -- int w, int h) -+static void FUNC_NAME(RadeonCompositeTile)(PixmapPtr pDst, -+ int srcX, int srcY, -+ int maskX, int maskY, -+ int dstX, int dstY, -+ int w, int h) - { - RINFO_FROM_SCREEN(pDst->drawable.pScreen); - int vtx_count; -@@ -1347,9 +1949,12 @@ static void FUNC_NAME(RadeonComposite)(PixmapPtr pDst, - transformPoint(transform[1], &maskBottomRight); - } - -- vtx_count = VTX_COUNT; -+ if (has_mask) -+ vtx_count = VTX_COUNT_MASK; -+ else -+ vtx_count = VTX_COUNT; - -- if (IS_R300_VARIANT || IS_AVIVO_VARIANT) { -+ if (IS_R300_3D || IS_R500_3D) { - BEGIN_ACCEL(1); - OUT_ACCEL_REG(R300_VAP_VTX_SIZE, vtx_count); - FINISH_ACCEL(); -@@ -1357,66 +1962,86 @@ static void FUNC_NAME(RadeonComposite)(PixmapPtr pDst, - - #ifdef ACCEL_CP - if (info->ChipFamily < CHIP_FAMILY_R200) { -- BEGIN_RING(4 * vtx_count + 3); -+ BEGIN_RING(3 * vtx_count + 3); - OUT_RING(CP_PACKET3(RADEON_CP_PACKET3_3D_DRAW_IMMD, -- 4 * vtx_count + 1)); -- OUT_RING(RADEON_CP_VC_FRMT_XY | -- RADEON_CP_VC_FRMT_ST0 | -- RADEON_CP_VC_FRMT_ST1); -- OUT_RING(RADEON_CP_VC_CNTL_PRIM_TYPE_TRI_FAN | -+ 3 * vtx_count + 1)); -+ if (has_mask) -+ OUT_RING(RADEON_CP_VC_FRMT_XY | -+ RADEON_CP_VC_FRMT_ST0 | -+ RADEON_CP_VC_FRMT_ST1); -+ else -+ OUT_RING(RADEON_CP_VC_FRMT_XY | -+ RADEON_CP_VC_FRMT_ST0); -+ OUT_RING(RADEON_CP_VC_CNTL_PRIM_TYPE_RECT_LIST | - RADEON_CP_VC_CNTL_PRIM_WALK_RING | - RADEON_CP_VC_CNTL_MAOS_ENABLE | - RADEON_CP_VC_CNTL_VTX_FMT_RADEON_MODE | -- (4 << RADEON_CP_VC_CNTL_NUM_SHIFT)); -+ (3 << RADEON_CP_VC_CNTL_NUM_SHIFT)); - } else { -- if (IS_R300_VARIANT || IS_AVIVO_VARIANT) -- BEGIN_RING(4 * vtx_count + 6); -+ if (IS_R300_3D || IS_R500_3D) -+ BEGIN_RING(4 * vtx_count + 4); - else - BEGIN_RING(4 * vtx_count + 2); - - OUT_RING(CP_PACKET3(R200_CP_PACKET3_3D_DRAW_IMMD_2, - 4 * vtx_count)); -- OUT_RING(RADEON_CP_VC_CNTL_PRIM_TYPE_TRI_FAN | -+ OUT_RING(RADEON_CP_VC_CNTL_PRIM_TYPE_QUAD_LIST | - RADEON_CP_VC_CNTL_PRIM_WALK_RING | - (4 << RADEON_CP_VC_CNTL_NUM_SHIFT)); - } - - #else /* ACCEL_CP */ -- if (IS_R300_VARIANT || IS_AVIVO_VARIANT) -- BEGIN_ACCEL(3 + vtx_count * 4); -+ if (IS_R300_3D || IS_R500_3D) -+ BEGIN_ACCEL(2 + vtx_count * 4); -+ else if (info->ChipFamily < CHIP_FAMILY_R200) -+ BEGIN_ACCEL(1 + vtx_count * 3); - else - BEGIN_ACCEL(1 + vtx_count * 4); - - if (info->ChipFamily < CHIP_FAMILY_R200) { -- OUT_ACCEL_REG(RADEON_SE_VF_CNTL, (RADEON_VF_PRIM_TYPE_TRIANGLE_FAN | -+ OUT_ACCEL_REG(RADEON_SE_VF_CNTL, (RADEON_VF_PRIM_TYPE_RECTANGLE_LIST | - RADEON_VF_PRIM_WALK_DATA | - RADEON_VF_RADEON_MODE | -- 4 << RADEON_VF_NUM_VERTICES_SHIFT)); -+ (3 << RADEON_VF_NUM_VERTICES_SHIFT))); - } else { - OUT_ACCEL_REG(RADEON_SE_VF_CNTL, (RADEON_VF_PRIM_TYPE_QUAD_LIST | - RADEON_VF_PRIM_WALK_DATA | -- 4 << RADEON_VF_NUM_VERTICES_SHIFT)); -+ (4 << RADEON_VF_NUM_VERTICES_SHIFT))); - } - #endif - -- VTX_OUT((float)dstX, (float)dstY, -- xFixedToFloat(srcTopLeft.x) / info->texW[0], xFixedToFloat(srcTopLeft.y) / info->texH[0], -- xFixedToFloat(maskTopLeft.x) / info->texW[1], xFixedToFloat(maskTopLeft.y) / info->texH[1]); -- VTX_OUT((float)dstX, (float)(dstY + h), -- xFixedToFloat(srcBottomLeft.x) / info->texW[0], xFixedToFloat(srcBottomLeft.y) / info->texH[0], -- xFixedToFloat(maskBottomLeft.x) / info->texW[1], xFixedToFloat(maskBottomLeft.y) / info->texH[1]); -- VTX_OUT((float)(dstX + w), (float)(dstY + h), -- xFixedToFloat(srcBottomRight.x) / info->texW[0], xFixedToFloat(srcBottomRight.y) / info->texH[0], -- xFixedToFloat(maskBottomRight.x) / info->texW[1], xFixedToFloat(maskBottomRight.y) / info->texH[1]); -- VTX_OUT((float)(dstX + w), (float)dstY, -- xFixedToFloat(srcTopRight.x) / info->texW[0], xFixedToFloat(srcTopRight.y) / info->texH[0], -- xFixedToFloat(maskTopRight.x) / info->texW[1], xFixedToFloat(maskTopRight.y) / info->texH[1]); -- -- if (IS_R300_VARIANT || IS_AVIVO_VARIANT) { -- OUT_ACCEL_REG(R300_RB3D_DSTCACHE_CTLSTAT, R300_DC_FLUSH_3D | R300_DC_FREE_3D); -- OUT_ACCEL_REG(RADEON_WAIT_UNTIL, RADEON_WAIT_3D_IDLECLEAN); -+ if (has_mask) { -+ if (info->ChipFamily >= CHIP_FAMILY_R200) { -+ VTX_OUT_MASK((float)dstX, (float)dstY, -+ xFixedToFloat(srcTopLeft.x) / info->texW[0], xFixedToFloat(srcTopLeft.y) / info->texH[0], -+ xFixedToFloat(maskTopLeft.x) / info->texW[1], xFixedToFloat(maskTopLeft.y) / info->texH[1]); -+ } -+ VTX_OUT_MASK((float)dstX, (float)(dstY + h), -+ xFixedToFloat(srcBottomLeft.x) / info->texW[0], xFixedToFloat(srcBottomLeft.y) / info->texH[0], -+ xFixedToFloat(maskBottomLeft.x) / info->texW[1], xFixedToFloat(maskBottomLeft.y) / info->texH[1]); -+ VTX_OUT_MASK((float)(dstX + w), (float)(dstY + h), -+ xFixedToFloat(srcBottomRight.x) / info->texW[0], xFixedToFloat(srcBottomRight.y) / info->texH[0], -+ xFixedToFloat(maskBottomRight.x) / info->texW[1], xFixedToFloat(maskBottomRight.y) / info->texH[1]); -+ VTX_OUT_MASK((float)(dstX + w), (float)dstY, -+ xFixedToFloat(srcTopRight.x) / info->texW[0], xFixedToFloat(srcTopRight.y) / info->texH[0], -+ xFixedToFloat(maskTopRight.x) / info->texW[1], xFixedToFloat(maskTopRight.y) / info->texH[1]); -+ } else { -+ if (info->ChipFamily >= CHIP_FAMILY_R200) { -+ VTX_OUT((float)dstX, (float)dstY, -+ xFixedToFloat(srcTopLeft.x) / info->texW[0], xFixedToFloat(srcTopLeft.y) / info->texH[0]); -+ } -+ VTX_OUT((float)dstX, (float)(dstY + h), -+ xFixedToFloat(srcBottomLeft.x) / info->texW[0], xFixedToFloat(srcBottomLeft.y) / info->texH[0]); -+ VTX_OUT((float)(dstX + w), (float)(dstY + h), -+ xFixedToFloat(srcBottomRight.x) / info->texW[0], xFixedToFloat(srcBottomRight.y) / info->texH[0]); -+ VTX_OUT((float)(dstX + w), (float)dstY, -+ xFixedToFloat(srcTopRight.x) / info->texW[0], xFixedToFloat(srcTopRight.y) / info->texH[0]); - } - -+ if (IS_R300_3D || IS_R500_3D) -+ /* flushing is pipelined, free/finish is not */ -+ OUT_ACCEL_REG(R300_RB3D_DSTCACHE_CTLSTAT, R300_DC_FLUSH_3D); -+ - #ifdef ACCEL_CP - ADVANCE_RING(); - #else -@@ -1426,14 +2051,85 @@ static void FUNC_NAME(RadeonComposite)(PixmapPtr pDst, - LEAVE_DRAW(0); - } - #undef VTX_OUT -+#undef VTX_OUT_MASK - --#ifdef ONLY_ONCE --static void RadeonDoneComposite(PixmapPtr pDst) -+static void FUNC_NAME(RadeonComposite)(PixmapPtr pDst, -+ int srcX, int srcY, -+ int maskX, int maskY, -+ int dstX, int dstY, -+ int width, int height) - { -+ int tileSrcY, tileMaskY, tileDstY; -+ int remainingHeight; -+ -+ if (!need_src_tile_x && !need_src_tile_y) { -+ FUNC_NAME(RadeonCompositeTile)(pDst, -+ srcX, srcY, -+ maskX, maskY, -+ dstX, dstY, -+ width, height); -+ return; -+ } -+ -+ /* Tiling logic borrowed from exaFillRegionTiled */ -+ -+ modulus(srcY, src_tile_height, tileSrcY); -+ tileMaskY = maskY; -+ tileDstY = dstY; -+ -+ remainingHeight = height; -+ while (remainingHeight > 0) { -+ int remainingWidth = width; -+ int tileSrcX, tileMaskX, tileDstX; -+ int h = src_tile_height - tileSrcY; -+ -+ if (h > remainingHeight) -+ h = remainingHeight; -+ remainingHeight -= h; -+ -+ modulus(srcX, src_tile_width, tileSrcX); -+ tileMaskX = maskX; -+ tileDstX = dstX; -+ -+ while (remainingWidth > 0) { -+ int w = src_tile_width - tileSrcX; -+ if (w > remainingWidth) -+ w = remainingWidth; -+ remainingWidth -= w; -+ -+ FUNC_NAME(RadeonCompositeTile)(pDst, -+ tileSrcX, tileSrcY, -+ tileMaskX, tileMaskY, -+ tileDstX, tileDstY, -+ w, h); -+ -+ tileSrcX = 0; -+ tileMaskX += w; -+ tileDstX += w; -+ } -+ tileSrcY = 0; -+ tileMaskY += h; -+ tileDstY += h; -+ } -+} -+ -+static void FUNC_NAME(RadeonDoneComposite)(PixmapPtr pDst) -+{ -+ RINFO_FROM_SCREEN(pDst->drawable.pScreen); -+ ACCEL_PREAMBLE(); -+ - ENTER_DRAW(0); -+ -+ if (IS_R300_3D || IS_R500_3D) { -+ BEGIN_ACCEL(2); -+ OUT_ACCEL_REG(R300_RB3D_DSTCACHE_CTLSTAT, R300_RB3D_DC_FLUSH_ALL); -+ } else -+ BEGIN_ACCEL(1); -+ OUT_ACCEL_REG(RADEON_WAIT_UNTIL, RADEON_WAIT_3D_IDLECLEAN); -+ FINISH_ACCEL(); -+ - LEAVE_DRAW(0); - } --#endif /* ONLY_ONCE */ - - #undef ONLY_ONCE - #undef FUNC_NAME -diff --git a/src/radeon_macros.h b/src/radeon_macros.h -index 7f532a8..f19bc3e 100644 ---- a/src/radeon_macros.h -+++ b/src/radeon_macros.h -@@ -67,12 +67,12 @@ - #define OUTREG16(addr, val) MMIO_OUT16(RADEONMMIO, addr, val) - #define OUTREG(addr, val) MMIO_OUT32(RADEONMMIO, addr, val) - --#define ADDRREG(addr) ((volatile CARD32 *)(pointer)(RADEONMMIO + (addr))) -+#define ADDRREG(addr) ((volatile uint32_t *)(pointer)(RADEONMMIO + (addr))) - - - #define OUTREGP(addr, val, mask) \ - do { \ -- CARD32 tmp = INREG(addr); \ -+ uint32_t tmp = INREG(addr); \ - tmp &= (mask); \ - tmp |= ((val) & ~(mask)); \ - OUTREG(addr, tmp); \ -@@ -84,7 +84,7 @@ do { \ - - #define OUTPLLP(pScrn, addr, val, mask) \ - do { \ -- CARD32 tmp_ = INPLL(pScrn, addr); \ -+ uint32_t tmp_ = INPLL(pScrn, addr); \ - tmp_ &= (mask); \ - tmp_ |= ((val) & ~(mask)); \ - OUTPLL(pScrn, addr, tmp_); \ -@@ -108,7 +108,7 @@ do { \ - } \ - } while (0) - --#define OUTPAL_NEXT_CARD32(v) \ -+#define OUTPAL_NEXT_uint32_t(v) \ - do { \ - OUTREG(RADEON_PALETTE_DATA, (v & 0x00ffffff)); \ - } while (0) -@@ -148,7 +148,7 @@ do { \ - } else { \ - if (!idx) { \ - OUTREG(RADEON_DAC_CNTL2, INREG(RADEON_DAC_CNTL2) & \ -- (CARD32)~RADEON_DAC2_PALETTE_ACC_CTL); \ -+ (uint32_t)~RADEON_DAC2_PALETTE_ACC_CTL); \ - } else { \ - OUTREG(RADEON_DAC_CNTL2, INREG(RADEON_DAC_CNTL2) | \ - RADEON_DAC2_PALETTE_ACC_CTL); \ -diff --git a/src/radeon_mm_i2c.c b/src/radeon_mm_i2c.c -index 0524fa9..bb45407 100644 ---- a/src/radeon_mm_i2c.c -+++ b/src/radeon_mm_i2c.c -@@ -64,9 +64,9 @@ static void RADEON_TDA9885_Init(RADEONPortPrivPtr pPriv); - * I2C_NACK - an NACK was received from the slave * - * I2C_HALT - a timeout condition has occured * - ****************************************************************************/ --static CARD8 RADEON_I2C_WaitForAck (ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv) -+static uint8_t RADEON_I2C_WaitForAck (ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv) - { -- CARD8 retval = 0; -+ uint8_t retval = 0; - RADEONInfoPtr info = RADEONPTR(pScrn); - unsigned char *RADEONMMIO = info->MMIO; - long counter = 0; -@@ -103,7 +103,7 @@ static void RADEON_I2C_Halt (ScrnInfoPtr pScrn) - { - RADEONInfoPtr info = RADEONPTR(pScrn); - unsigned char *RADEONMMIO = info->MMIO; -- CARD8 reg; -+ uint8_t reg; - - /* reset status flags */ - RADEONWaitForIdleMMIO(pScrn); -@@ -124,8 +124,8 @@ static Bool RADEONI2CWriteRead(I2CDevPtr d, I2CByte *WriteBuffer, int nWrite, - I2CByte *ReadBuffer, int nRead) - { - int loop, status; -- CARD32 i2c_cntl_0, i2c_cntl_1; -- CARD8 reg; -+ uint32_t i2c_cntl_0, i2c_cntl_1; -+ uint8_t reg; - RADEONPortPrivPtr pPriv = (RADEONPortPrivPtr)(d->pI2CBus->DriverPrivate.ptr); - ScrnInfoPtr pScrn = xf86Screens[d->pI2CBus->scrnIndex]; - RADEONInfoPtr info = RADEONPTR(pScrn); -@@ -141,7 +141,7 @@ static Bool RADEONI2CWriteRead(I2CDevPtr d, I2CByte *WriteBuffer, int nWrite, - OUTREG(RADEON_I2C_CNTL_0, RADEON_I2C_DONE | RADEON_I2C_NACK | RADEON_I2C_HALT | RADEON_I2C_SOFT_RST); - - /* Write the address into the buffer first */ -- OUTREG(RADEON_I2C_DATA, (CARD32) (d->SlaveAddr) & ~(1)); -+ OUTREG(RADEON_I2C_DATA, (uint32_t) (d->SlaveAddr) & ~(1)); - - /* Write Value into the buffer */ - for (loop = 0; loop < nWrite; loop++) -@@ -172,7 +172,7 @@ static Bool RADEONI2CWriteRead(I2CDevPtr d, I2CByte *WriteBuffer, int nWrite, - OUTREG(RADEON_I2C_CNTL_0, RADEON_I2C_DONE | RADEON_I2C_NACK | RADEON_I2C_HALT | RADEON_I2C_SOFT_RST); - - /* Write the address into the buffer first */ -- OUTREG(RADEON_I2C_DATA, (CARD32) (d->SlaveAddr) | (1)); -+ OUTREG(RADEON_I2C_DATA, (uint32_t) (d->SlaveAddr) | (1)); - - i2c_cntl_1 = (pPriv->radeon_i2c_timing << 24) | RADEON_I2C_EN | RADEON_I2C_SEL | - nRead | 0x100; -@@ -209,8 +209,8 @@ static Bool R200_I2CWriteRead(I2CDevPtr d, I2CByte *WriteBuffer, int nWrite, - I2CByte *ReadBuffer, int nRead) - { - int loop, status; -- CARD32 i2c_cntl_0, i2c_cntl_1; -- CARD8 reg; -+ uint32_t i2c_cntl_0, i2c_cntl_1; -+ uint8_t reg; - RADEONPortPrivPtr pPriv = (RADEONPortPrivPtr)(d->pI2CBus->DriverPrivate.ptr); - ScrnInfoPtr pScrn = xf86Screens[d->pI2CBus->scrnIndex]; - RADEONInfoPtr info = RADEONPTR(pScrn); -@@ -226,7 +226,7 @@ static Bool R200_I2CWriteRead(I2CDevPtr d, I2CByte *WriteBuffer, int nWrite, - OUTREG(RADEON_I2C_CNTL_0, RADEON_I2C_DONE | RADEON_I2C_NACK | RADEON_I2C_HALT | RADEON_I2C_SOFT_RST); - - /* Write the address into the buffer first */ -- OUTREG(RADEON_I2C_DATA, (CARD32) (d->SlaveAddr) & ~(1)); -+ OUTREG(RADEON_I2C_DATA, (uint32_t) (d->SlaveAddr) & ~(1)); - - /* Write Value into the buffer */ - for (loop = 0; loop < nWrite; loop++) -@@ -257,7 +257,7 @@ static Bool R200_I2CWriteRead(I2CDevPtr d, I2CByte *WriteBuffer, int nWrite, - OUTREG(RADEON_I2C_CNTL_0, RADEON_I2C_DONE | RADEON_I2C_NACK | RADEON_I2C_HALT | RADEON_I2C_SOFT_RST); - - /* Write the address into the buffer first */ -- OUTREG(RADEON_I2C_DATA, (CARD32) (d->SlaveAddr) | (1)); -+ OUTREG(RADEON_I2C_DATA, (uint32_t) (d->SlaveAddr) | (1)); - - i2c_cntl_1 = (pPriv->radeon_i2c_timing << 24) | RADEON_I2C_EN | RADEON_I2C_SEL | - nRead | 0x010; -diff --git a/src/radeon_output.c b/src/radeon_output.c -index 62cc5d4..a835c0c 100644 ---- a/src/radeon_output.c -+++ b/src/radeon_output.c -@@ -74,12 +74,13 @@ const RADEONMonitorType MonTypeID[10] = { - MT_DP - }; - --const char *TMDSTypeName[5] = { -+const char *TMDSTypeName[6] = { - "None", - "Internal", - "External", - "LVTMA", -- "DDIA" -+ "DDIA", -+ "UNIPHY" - }; - - const char *DACTypeName[4] = { -@@ -143,9 +144,10 @@ static const RADEONTMDSPll default_tmds_pll[CHIP_FAMILY_LAST][4] = - {{0xffffffff, 0xb01cb}, {0, 0}, {0, 0}, {0, 0}}, /*CHIP_FAMILY_R420*/ - {{0xffffffff, 0xb01cb}, {0, 0}, {0, 0}, {0, 0}}, /*CHIP_FAMILY_RV410*/ /* FIXME: just values from r420 used... */ - {{15000, 0xb0155}, {0xffffffff, 0xb01cb}, {0, 0}, {0, 0}}, /*CHIP_FAMILY_RS400*/ /* FIXME: just values from rv380 used... */ -+ {{15000, 0xb0155}, {0xffffffff, 0xb01cb}, {0, 0}, {0, 0}}, /*CHIP_FAMILY_RS480*/ /* FIXME: just values from rv380 used... */ - }; - --static const CARD32 default_tvdac_adj [CHIP_FAMILY_LAST] = -+static const uint32_t default_tvdac_adj [CHIP_FAMILY_LAST] = - { - 0x00000000, /* unknown */ - 0x00000000, /* legacy */ -@@ -165,10 +167,10 @@ static const CARD32 default_tvdac_adj [CHIP_FAMILY_LAST] = - 0x01080000, /* r420 */ - 0x01080000, /* rv410 */ /* FIXME: just values from r420 used... */ - 0x00780000, /* rs400 */ /* FIXME: just values from rv380 used... */ -+ 0x00780000, /* rs480 */ /* FIXME: just values from rv380 used... */ - }; - - --static RADEONMonitorType RADEONPortCheckNonDDC(ScrnInfoPtr pScrn, xf86OutputPtr output); - static void RADEONUpdatePanelSize(xf86OutputPtr output); - static void RADEONGetTMDSInfoFromTable(xf86OutputPtr output); - #define AVIVO_I2C_DISABLE 0 -@@ -178,15 +180,11 @@ static Bool AVIVOI2CDoLock(xf86OutputPtr output, int lock_state); - extern void atombios_output_mode_set(xf86OutputPtr output, - DisplayModePtr mode, - DisplayModePtr adjusted_mode); --extern void legacy_output_mode_set(xf86OutputPtr output, -- DisplayModePtr mode, -- DisplayModePtr adjusted_mode); - extern void atombios_output_dpms(xf86OutputPtr output, int mode); --extern void legacy_output_dpms(xf86OutputPtr output, int mode); - extern RADEONMonitorType atombios_dac_detect(ScrnInfoPtr pScrn, xf86OutputPtr output); --extern RADEONMonitorType legacy_dac_detect(ScrnInfoPtr pScrn, xf86OutputPtr output); - extern int atombios_external_tmds_setup(xf86OutputPtr output, DisplayModePtr mode); --extern I2CDevPtr RADEONDVODeviceInit(I2CBusPtr b, I2CSlaveAddr addr); -+extern AtomBiosResult -+atombios_lock_crtc(atomBiosHandlePtr atomBIOS, int crtc, int lock); - static void - radeon_bios_output_dpms(xf86OutputPtr output, int mode); - static void -@@ -217,122 +215,99 @@ void RADEONPrintPortMap(ScrnInfoPtr pScrn) - - } - --static RADEONMonitorType --avivo_display_ddc_connected(ScrnInfoPtr pScrn, xf86OutputPtr output) -+static xf86MonPtr -+radeon_do_ddc(xf86OutputPtr output) - { -- RADEONInfoPtr info = RADEONPTR(pScrn); -- RADEONMonitorType MonType = MT_NONE; -- xf86MonPtr MonInfo = NULL; -- RADEONOutputPrivatePtr radeon_output = output->driver_private; -- -- if (radeon_output->pI2CBus) { -- AVIVOI2CDoLock(output, AVIVO_I2C_ENABLE); -- MonInfo = xf86OutputGetEDID(output, radeon_output->pI2CBus); -- AVIVOI2CDoLock(output, AVIVO_I2C_DISABLE); -- } -- if (MonInfo) { -- if (!xf86ReturnOptValBool(info->Options, OPTION_IGNORE_EDID, FALSE)) -- xf86OutputSetEDID(output, MonInfo); -- if (radeon_output->type == OUTPUT_LVDS) -- MonType = MT_LCD; -- else if (radeon_output->type == OUTPUT_DVI_D) -- MonType = MT_DFP; -- else if (radeon_output->type == OUTPUT_HDMI) -- MonType = MT_DFP; -- else if (radeon_output->type == OUTPUT_DVI_I && (MonInfo->rawData[0x14] & 0x80)) /* if it's digital and DVI */ -- MonType = MT_DFP; -- else -- MonType = MT_CRT; -- } else MonType = MT_NONE; -- -- xf86DrvMsg(pScrn->scrnIndex, X_INFO, -- "Output: %s, Detected Monitor Type: %d\n", output->name, MonType); -- -- return MonType; --} -- --static RADEONMonitorType --RADEONDisplayDDCConnected(ScrnInfoPtr pScrn, xf86OutputPtr output) --{ -- RADEONInfoPtr info = RADEONPTR(pScrn); -+ RADEONInfoPtr info = RADEONPTR(output->scrn); - unsigned char *RADEONMMIO = info->MMIO; -- CARD32 DDCReg; -- RADEONMonitorType MonType = MT_NONE; -+ uint32_t DDCReg; - xf86MonPtr MonInfo = NULL; - RADEONOutputPrivatePtr radeon_output = output->driver_private; - int i, j; - -- if (!radeon_output->ddc_i2c.valid) -- return MT_NONE; -+ if (radeon_output->pI2CBus) { -+ DDCReg = radeon_output->ddc_i2c.mask_clk_reg; - -- DDCReg = radeon_output->ddc_i2c.mask_clk_reg; -+ if (IS_AVIVO_VARIANT) { -+ AVIVOI2CDoLock(output, AVIVO_I2C_ENABLE); -+ MonInfo = xf86OutputGetEDID(output, radeon_output->pI2CBus); -+ AVIVOI2CDoLock(output, AVIVO_I2C_DISABLE); -+ } else if ((DDCReg == RADEON_LCD_GPIO_MASK) || (DDCReg == RADEON_MDGPIO_EN_REG)) { -+ MonInfo = xf86OutputGetEDID(output, radeon_output->pI2CBus); -+ } else { -+ OUTREG(DDCReg, INREG(DDCReg) & -+ (uint32_t)~(RADEON_GPIO_A_0 | RADEON_GPIO_A_1)); - -- /* Read and output monitor info using DDC2 over I2C bus */ -- if (radeon_output->pI2CBus && info->ddc2 && (DDCReg != RADEON_LCD_GPIO_MASK) && (DDCReg != RADEON_MDGPIO_EN_REG)) { -- OUTREG(DDCReg, INREG(DDCReg) & -- (CARD32)~(RADEON_GPIO_A_0 | RADEON_GPIO_A_1)); -+ /* For some old monitors (like Compaq Presario FP500), we need -+ * following process to initialize/stop DDC -+ */ -+ OUTREG(DDCReg, INREG(DDCReg) & ~(RADEON_GPIO_EN_1)); -+ for (j = 0; j < 3; j++) { -+ OUTREG(DDCReg, -+ INREG(DDCReg) & ~(RADEON_GPIO_EN_0)); -+ usleep(13000); -+ -+ OUTREG(DDCReg, -+ INREG(DDCReg) & ~(RADEON_GPIO_EN_1)); -+ for (i = 0; i < 10; i++) { -+ usleep(15000); -+ if (INREG(DDCReg) & RADEON_GPIO_Y_1) -+ break; -+ } -+ if (i == 10) continue; - -- /* For some old monitors (like Compaq Presario FP500), we need -- * following process to initialize/stop DDC -- */ -- OUTREG(DDCReg, INREG(DDCReg) & ~(RADEON_GPIO_EN_1)); -- for (j = 0; j < 3; j++) { -- OUTREG(DDCReg, -- INREG(DDCReg) & ~(RADEON_GPIO_EN_0)); -- usleep(13000); -- -- OUTREG(DDCReg, -- INREG(DDCReg) & ~(RADEON_GPIO_EN_1)); -- for (i = 0; i < 10; i++) { - usleep(15000); -- if (INREG(DDCReg) & RADEON_GPIO_Y_1) -- break; -- } -- if (i == 10) continue; - -- usleep(15000); -+ OUTREG(DDCReg, INREG(DDCReg) | RADEON_GPIO_EN_0); -+ usleep(15000); - -- OUTREG(DDCReg, INREG(DDCReg) | RADEON_GPIO_EN_0); -- usleep(15000); -+ OUTREG(DDCReg, INREG(DDCReg) | RADEON_GPIO_EN_1); -+ usleep(15000); -+ OUTREG(DDCReg, -+ INREG(DDCReg) & ~(RADEON_GPIO_EN_0)); -+ usleep(15000); - -- OUTREG(DDCReg, INREG(DDCReg) | RADEON_GPIO_EN_1); -- usleep(15000); -- OUTREG(DDCReg, -- INREG(DDCReg) & ~(RADEON_GPIO_EN_0)); -- usleep(15000); -+ MonInfo = xf86OutputGetEDID(output, radeon_output->pI2CBus); - -- MonInfo = xf86DoEDID_DDC2(pScrn->scrnIndex, radeon_output->pI2CBus); -+ OUTREG(DDCReg, INREG(DDCReg) | RADEON_GPIO_EN_1); -+ OUTREG(DDCReg, INREG(DDCReg) | RADEON_GPIO_EN_0); -+ usleep(15000); -+ OUTREG(DDCReg, -+ INREG(DDCReg) & ~(RADEON_GPIO_EN_1)); -+ for (i = 0; i < 5; i++) { -+ usleep(15000); -+ if (INREG(DDCReg) & RADEON_GPIO_Y_1) -+ break; -+ } -+ usleep(15000); -+ OUTREG(DDCReg, -+ INREG(DDCReg) & ~(RADEON_GPIO_EN_0)); -+ usleep(15000); - -- OUTREG(DDCReg, INREG(DDCReg) | RADEON_GPIO_EN_1); -- OUTREG(DDCReg, INREG(DDCReg) | RADEON_GPIO_EN_0); -- usleep(15000); -- OUTREG(DDCReg, -- INREG(DDCReg) & ~(RADEON_GPIO_EN_1)); -- for (i = 0; i < 5; i++) { -+ OUTREG(DDCReg, INREG(DDCReg) | RADEON_GPIO_EN_1); -+ OUTREG(DDCReg, INREG(DDCReg) | RADEON_GPIO_EN_0); - usleep(15000); -- if (INREG(DDCReg) & RADEON_GPIO_Y_1) -- break; -+ if (MonInfo) break; - } -- usleep(15000); -- OUTREG(DDCReg, -- INREG(DDCReg) & ~(RADEON_GPIO_EN_0)); -- usleep(15000); -- -- OUTREG(DDCReg, INREG(DDCReg) | RADEON_GPIO_EN_1); -- OUTREG(DDCReg, INREG(DDCReg) | RADEON_GPIO_EN_0); -- usleep(15000); -- if (MonInfo) break; -- } -- } else if (radeon_output->pI2CBus && info->ddc2 && ((DDCReg == RADEON_LCD_GPIO_MASK) || (DDCReg == RADEON_MDGPIO_EN_REG))) { -- MonInfo = xf86DoEDID_DDC2(pScrn->scrnIndex, radeon_output->pI2CBus); -- } else { -- xf86DrvMsg(pScrn->scrnIndex, X_WARNING, "DDC2/I2C is not properly initialized\n"); -- MonType = MT_NONE; -+ OUTREG(DDCReg, INREG(DDCReg) & -+ ~(RADEON_GPIO_EN_0 | RADEON_GPIO_EN_1)); -+ } - } - -- OUTREG(DDCReg, INREG(DDCReg) & -- ~(RADEON_GPIO_EN_0 | RADEON_GPIO_EN_1)); -+ return MonInfo; -+} -+ -+static RADEONMonitorType -+radeon_ddc_connected(xf86OutputPtr output) -+{ -+ ScrnInfoPtr pScrn = output->scrn; -+ RADEONInfoPtr info = RADEONPTR(pScrn); -+ RADEONMonitorType MonType = MT_NONE; -+ xf86MonPtr MonInfo = NULL; -+ RADEONOutputPrivatePtr radeon_output = output->driver_private; - -+ if (radeon_output->pI2CBus) -+ MonInfo = radeon_do_ddc(output); - if (MonInfo) { - if (!xf86ReturnOptValBool(info->Options, OPTION_IGNORE_EDID, FALSE)) - xf86OutputSetEDID(output, MonInfo); -@@ -342,67 +317,21 @@ RADEONDisplayDDCConnected(ScrnInfoPtr pScrn, xf86OutputPtr output) - MonType = MT_DFP; - else if (radeon_output->type == OUTPUT_HDMI) - MonType = MT_DFP; -+ else if (radeon_output->type == OUTPUT_DP) -+ MonType = MT_DFP; - else if (radeon_output->type == OUTPUT_DVI_I && (MonInfo->rawData[0x14] & 0x80)) /* if it's digital and DVI */ - MonType = MT_DFP; - else - MonType = MT_CRT; -- } else MonType = MT_NONE; -- -+ } else -+ MonType = MT_NONE; -+ - xf86DrvMsg(pScrn->scrnIndex, X_INFO, - "Output: %s, Detected Monitor Type: %d\n", output->name, MonType); - - return MonType; - } - -- --/* Primary Head (DVI or Laptop Int. panel)*/ --/* A ddc capable display connected on DVI port */ --/* Secondary Head (mostly VGA, can be DVI on some OEM boards)*/ --void RADEONConnectorFindMonitor(ScrnInfoPtr pScrn, xf86OutputPtr output) --{ -- RADEONInfoPtr info = RADEONPTR(pScrn); -- RADEONOutputPrivatePtr radeon_output = output->driver_private; -- -- if (radeon_output->MonType == MT_UNKNOWN) { -- if (IS_AVIVO_VARIANT) { -- radeon_output->MonType = avivo_display_ddc_connected(pScrn, output); -- if (!radeon_output->MonType) { -- if (radeon_output->type == OUTPUT_LVDS) -- radeon_output->MonType = MT_LCD; -- else -- radeon_output->MonType = atombios_dac_detect(pScrn, output); -- } -- } else { -- radeon_output->MonType = RADEONDisplayDDCConnected(pScrn, output); -- if (!radeon_output->MonType) { -- if (radeon_output->type == OUTPUT_LVDS || OUTPUT_IS_DVI) -- radeon_output->MonType = RADEONPortCheckNonDDC(pScrn, output); -- if (!radeon_output->MonType) { -- if (info->IsAtomBios) -- radeon_output->MonType = atombios_dac_detect(pScrn, output); -- else -- radeon_output->MonType = legacy_dac_detect(pScrn, output); -- } -- } -- } -- } -- -- /* update panel info for RMX */ -- if (radeon_output->MonType == MT_LCD || radeon_output->MonType == MT_DFP) -- RADEONUpdatePanelSize(output); -- -- /* panel is probably busted or not connected */ -- if ((radeon_output->MonType == MT_LCD) && -- ((radeon_output->PanelXRes == 0) || (radeon_output->PanelYRes == 0))) -- radeon_output->MonType = MT_NONE; -- -- if (output->MonInfo) { -- xf86DrvMsg(pScrn->scrnIndex, X_INFO, "EDID data from the display on output: %s ----------------------\n", -- output->name); -- xf86PrintEDID( output->MonInfo ); -- } --} -- - #ifndef __powerpc__ - - static RADEONMonitorType -@@ -449,42 +378,58 @@ RADEONDetectLidStatus(ScrnInfoPtr pScrn) - - #endif /* __powerpc__ */ - --static RADEONMonitorType RADEONPortCheckNonDDC(ScrnInfoPtr pScrn, xf86OutputPtr output) -+static void -+RADEONConnectorFindMonitor(xf86OutputPtr output) - { -- RADEONInfoPtr info = RADEONPTR(output->scrn); -+ ScrnInfoPtr pScrn = output->scrn; -+ RADEONInfoPtr info = RADEONPTR(pScrn); - RADEONOutputPrivatePtr radeon_output = output->driver_private; -- RADEONMonitorType MonType = MT_NONE; - -- if (radeon_output->type == OUTPUT_LVDS) { -- if (xf86ReturnOptValBool(info->Options, OPTION_IGNORE_LID_STATUS, TRUE)) -- MonType = MT_LCD; -- else -+ if (radeon_output->MonType == MT_UNKNOWN) { -+ radeon_output->MonType = radeon_ddc_connected(output); -+ if (!radeon_output->MonType) { -+ if (radeon_output->type == OUTPUT_LVDS) { -+ if (xf86ReturnOptValBool(info->Options, OPTION_IGNORE_LID_STATUS, TRUE)) -+ radeon_output->MonType = MT_LCD; -+ else - #if defined(__powerpc__) -- MonType = MT_LCD; -+ radeon_output->MonType = MT_LCD; - #else -- MonType = RADEONDetectLidStatus(pScrn); -+ radeon_output->MonType = RADEONDetectLidStatus(pScrn); - #endif -- } /*else if (radeon_output->type == OUTPUT_DVI) { -- if (radeon_output->TMDSType == TMDS_INT) { -- if (INREG(RADEON_FP_GEN_CNTL) & RADEON_FP_DETECT_SENSE) -- MonType = MT_DFP; -- } else if (radeon_output->TMDSType == TMDS_EXT) { -- if (INREG(RADEON_FP2_GEN_CNTL) & RADEON_FP2_DETECT_SENSE) -- MonType = MT_DFP; -+ } else { -+ if (info->IsAtomBios) -+ radeon_output->MonType = atombios_dac_detect(pScrn, output); -+ else -+ radeon_output->MonType = legacy_dac_detect(pScrn, output); -+ } - } -- }*/ -+ } - -- xf86DrvMsg(pScrn->scrnIndex, X_INFO, -- "Detected non-DDC Monitor Type: %d\n", MonType); -+ /* update panel info for RMX */ -+ if (radeon_output->MonType == MT_LCD || radeon_output->MonType == MT_DFP) -+ RADEONUpdatePanelSize(output); - -- return MonType; -+ /* panel is probably busted or not connected */ -+ if ((radeon_output->MonType == MT_LCD) && -+ ((radeon_output->PanelXRes == 0) || (radeon_output->PanelYRes == 0))) -+ radeon_output->MonType = MT_NONE; - -+ if (output->MonInfo) { -+ xf86DrvMsg(pScrn->scrnIndex, X_INFO, "EDID data from the display on output: %s ----------------------\n", -+ output->name); -+ xf86PrintEDID( output->MonInfo ); -+ } - } - - static void - radeon_dpms(xf86OutputPtr output, int mode) - { - RADEONInfoPtr info = RADEONPTR(output->scrn); -+ RADEONOutputPrivatePtr radeon_output = output->driver_private; -+ -+ if ((mode == DPMSModeOn) && radeon_output->enabled) -+ return; - - if (IS_AVIVO_VARIANT) { - atombios_output_dpms(output, mode); -@@ -493,6 +438,11 @@ radeon_dpms(xf86OutputPtr output, int mode) - } - radeon_bios_output_dpms(output, mode); - -+ if (mode == DPMSModeOn) -+ radeon_output->enabled = TRUE; -+ else -+ radeon_output->enabled = FALSE; -+ - } - - static void -@@ -589,7 +539,7 @@ radeon_mode_fixup(xf86OutputPtr output, DisplayModePtr mode, - if (IS_AVIVO_VARIANT) { - /* set to the panel's native mode */ - adjusted_mode->HDisplay = radeon_output->PanelXRes; -- adjusted_mode->HDisplay = radeon_output->PanelYRes; -+ adjusted_mode->VDisplay = radeon_output->PanelYRes; - adjusted_mode->HTotal = radeon_output->PanelXRes + radeon_output->HBlank; - adjusted_mode->HSyncStart = radeon_output->PanelXRes + radeon_output->HOverPlus; - adjusted_mode->HSyncEnd = adjusted_mode->HSyncStart + radeon_output->HSyncWidth; -@@ -632,14 +582,43 @@ radeon_mode_fixup(xf86OutputPtr output, DisplayModePtr mode, - } - } - -+ if (IS_AVIVO_VARIANT) { -+ /* hw bug */ -+ if ((mode->Flags & V_INTERLACE) -+ && (mode->CrtcVSyncStart < (mode->CrtcVDisplay + 2))) -+ adjusted_mode->CrtcVSyncStart = adjusted_mode->CrtcVDisplay + 2; -+ } -+ - return TRUE; - } - - static void - radeon_mode_prepare(xf86OutputPtr output) - { -+ RADEONInfoPtr info = RADEONPTR(output->scrn); -+ xf86CrtcConfigPtr config = XF86_CRTC_CONFIG_PTR (output->scrn); -+ int o; -+ -+ for (o = 0; o < config->num_output; o++) { -+ xf86OutputPtr loop_output = config->output[o]; -+ if (loop_output == output) -+ continue; -+ else if (loop_output->crtc) { -+ xf86CrtcPtr other_crtc = loop_output->crtc; -+ RADEONCrtcPrivatePtr other_radeon_crtc = other_crtc->driver_private; -+ if (other_crtc->enabled) { -+ radeon_crtc_dpms(other_crtc, DPMSModeOff); -+ if (IS_AVIVO_VARIANT) -+ atombios_lock_crtc(info->atomBIOS, other_radeon_crtc->crtc_id, 1); -+ radeon_dpms(loop_output, DPMSModeOff); -+ } -+ } -+ } -+ - radeon_bios_output_lock(output, TRUE); - radeon_dpms(output, DPMSModeOff); -+ radeon_crtc_dpms(output->crtc, DPMSModeOff); -+ - } - - static void -@@ -659,7 +638,28 @@ radeon_mode_set(xf86OutputPtr output, DisplayModePtr mode, - static void - radeon_mode_commit(xf86OutputPtr output) - { -+ RADEONInfoPtr info = RADEONPTR(output->scrn); -+ xf86CrtcConfigPtr config = XF86_CRTC_CONFIG_PTR (output->scrn); -+ int o; -+ -+ for (o = 0; o < config->num_output; o++) { -+ xf86OutputPtr loop_output = config->output[o]; -+ if (loop_output == output) -+ continue; -+ else if (loop_output->crtc) { -+ xf86CrtcPtr other_crtc = loop_output->crtc; -+ RADEONCrtcPrivatePtr other_radeon_crtc = other_crtc->driver_private; -+ if (other_crtc->enabled) { -+ radeon_crtc_dpms(other_crtc, DPMSModeOn); -+ if (IS_AVIVO_VARIANT) -+ atombios_lock_crtc(info->atomBIOS, other_radeon_crtc->crtc_id, 0); -+ radeon_dpms(loop_output, DPMSModeOn); -+ } -+ } -+ } -+ - radeon_dpms(output, DPMSModeOn); -+ radeon_crtc_dpms(output->crtc, DPMSModeOn); - radeon_bios_output_lock(output, FALSE); - } - -@@ -673,15 +673,15 @@ radeon_bios_output_lock(xf86OutputPtr output, Bool lock) - - if (info->IsAtomBios) { - if (lock) { -- save->bios_6_scratch |= (ATOM_S6_CRITICAL_STATE | ATOM_S6_ACC_MODE); -+ save->bios_6_scratch |= ATOM_S6_CRITICAL_STATE; - } else { -- save->bios_6_scratch &= ~(ATOM_S6_CRITICAL_STATE | ATOM_S6_ACC_MODE); -+ save->bios_6_scratch &= ~ATOM_S6_CRITICAL_STATE; - } - } else { - if (lock) { -- save->bios_6_scratch |= (RADEON_DRIVER_CRITICAL | RADEON_ACC_MODE_CHANGE); -+ save->bios_6_scratch |= RADEON_DRIVER_CRITICAL; - } else { -- save->bios_6_scratch &= ~(RADEON_DRIVER_CRITICAL | RADEON_ACC_MODE_CHANGE); -+ save->bios_6_scratch &= ~RADEON_DRIVER_CRITICAL; - } - } - if (info->ChipFamily >= CHIP_FAMILY_R600) -@@ -1032,7 +1032,7 @@ radeon_detect(xf86OutputPtr output) - - radeon_output->MonType = MT_UNKNOWN; - radeon_bios_output_connected(output, FALSE); -- RADEONConnectorFindMonitor(pScrn, output); -+ RADEONConnectorFindMonitor(output); - - /* nothing connected, light up some defaults so the server comes up */ - if (radeon_output->MonType == MT_NONE && -@@ -1101,24 +1101,6 @@ radeon_detect(xf86OutputPtr output) - break; - } - --#if 0 -- if (!connected) { -- /* default to unknown for flaky chips/connectors -- * so we can get something on the screen -- */ -- if ((radeon_output->type == OUTPUT_VGA || radeon_output->type == OUTPUT_DVI_I) && -- (radeon_output->DACType == DAC_TVDAC) && -- (info->ChipFamily == CHIP_FAMILY_RS400)) { -- radeon_output->MonType = MT_CRT; -- return XF86OutputStatusUnknown; -- } else if ((info->ChipFamily == CHIP_FAMILY_RS400) && -- radeon_output->type == OUTPUT_DVI_D) { -- radeon_output->MonType = MT_DFP; /* MT_LCD ??? */ -- return XF86OutputStatusUnknown; -- } -- } --#endif -- - if (connected) - return XF86OutputStatusConnected; - else -@@ -1149,7 +1131,7 @@ radeon_set_backlight_level(xf86OutputPtr output, int level) - ScrnInfoPtr pScrn = output->scrn; - RADEONInfoPtr info = RADEONPTR(pScrn); - unsigned char * RADEONMMIO = info->MMIO; -- CARD32 lvds_gen_cntl; -+ uint32_t lvds_gen_cntl; - - lvds_gen_cntl = INREG(RADEON_LVDS_GEN_CNTL); - lvds_gen_cntl |= RADEON_LVDS_BL_MOD_EN; -@@ -1168,6 +1150,7 @@ static Atom tmds_pll_atom; - static Atom rmx_atom; - static Atom monitor_type_atom; - static Atom load_detection_atom; -+static Atom coherent_mode_atom; - static Atom tv_hsize_atom; - static Atom tv_hpos_atom; - static Atom tv_vpos_atom; -@@ -1235,6 +1218,30 @@ radeon_create_resources(xf86OutputPtr output) - } - } - -+ if (IS_DCE3_VARIANT && -+ (OUTPUT_IS_DVI || (radeon_output->type == OUTPUT_HDMI))) { -+ coherent_mode_atom = MAKE_ATOM("coherent_mode"); -+ -+ range[0] = 0; /* off */ -+ range[1] = 1; /* on */ -+ err = RRConfigureOutputProperty(output->randr_output, coherent_mode_atom, -+ FALSE, TRUE, FALSE, 2, range); -+ if (err != 0) { -+ xf86DrvMsg(pScrn->scrnIndex, X_ERROR, -+ "RRConfigureOutputProperty error, %d\n", err); -+ } -+ -+ data = 1; /* use coherent mode by default */ -+ -+ err = RRChangeOutputProperty(output->randr_output, coherent_mode_atom, -+ XA_INTEGER, 32, PropModeReplace, 1, &data, -+ FALSE, TRUE); -+ if (err != 0) { -+ xf86DrvMsg(pScrn->scrnIndex, X_ERROR, -+ "RRChangeOutputProperty error, %d\n", err); -+ } -+ } -+ - if (OUTPUT_IS_DVI && radeon_output->TMDSType == TMDS_INT) { - tmds_pll_atom = MAKE_ATOM("tmds_pll"); - -@@ -1413,6 +1420,26 @@ radeon_create_resources(xf86OutputPtr output) - } - - static Bool -+radeon_set_mode_for_property(xf86OutputPtr output) -+{ -+ ScrnInfoPtr pScrn = output->scrn; -+ -+ if (output->crtc) { -+ xf86CrtcPtr crtc = output->crtc; -+ -+ if (crtc->enabled) { -+ if (!xf86CrtcSetMode(crtc, &crtc->desiredMode, crtc->desiredRotation, -+ crtc->desiredX, crtc->desiredY)) { -+ xf86DrvMsg(pScrn->scrnIndex, X_ERROR, -+ "Failed to set mode after propery change!\n"); -+ return FALSE; -+ } -+ } -+ } -+ return TRUE; -+} -+ -+static Bool - radeon_set_property(xf86OutputPtr output, Atom property, - RRPropertyValuePtr value) - { -@@ -1451,22 +1478,47 @@ radeon_set_property(xf86OutputPtr output, Atom property, - - radeon_output->load_detection = val; - -+ } else if (property == coherent_mode_atom) { -+ Bool coherent_mode = radeon_output->coherent_mode; -+ -+ if (value->type != XA_INTEGER || -+ value->format != 32 || -+ value->size != 1) { -+ return FALSE; -+ } -+ -+ val = *(INT32 *)value->data; -+ if (val < 0 || val > 1) -+ return FALSE; -+ -+ radeon_output->coherent_mode = val; -+ if (!radeon_set_mode_for_property(output)) { -+ radeon_output->coherent_mode = coherent_mode; -+ (void)radeon_set_mode_for_property(output); -+ return FALSE; -+ } -+ - } else if (property == rmx_atom) { - const char *s; -+ RADEONRMXType rmx = radeon_output->rmx_type; -+ - if (value->type != XA_STRING || value->format != 8) - return FALSE; - s = (char*)value->data; - if (value->size == strlen("full") && !strncmp("full", s, strlen("full"))) { - radeon_output->rmx_type = RMX_FULL; -- return TRUE; - } else if (value->size == strlen("center") && !strncmp("center", s, strlen("center"))) { - radeon_output->rmx_type = RMX_CENTER; -- return TRUE; - } else if (value->size == strlen("off") && !strncmp("off", s, strlen("off"))) { - radeon_output->rmx_type = RMX_OFF; -- return TRUE; -+ } else -+ return FALSE; -+ -+ if (!radeon_set_mode_for_property(output)) { -+ radeon_output->rmx_type = rmx; -+ (void)radeon_set_mode_for_property(output); -+ return FALSE; - } -- return FALSE; - } else if (property == tmds_pll_atom) { - const char *s; - if (value->type != XA_STRING || value->format != 8) -@@ -1475,12 +1527,12 @@ radeon_set_property(xf86OutputPtr output, Atom property, - if (value->size == strlen("bios") && !strncmp("bios", s, strlen("bios"))) { - if (!RADEONGetTMDSInfoFromBIOS(output)) - RADEONGetTMDSInfoFromTable(output); -- return TRUE; - } else if (value->size == strlen("driver") && !strncmp("driver", s, strlen("driver"))) { - RADEONGetTMDSInfoFromTable(output); -- return TRUE; -- } -- return FALSE; -+ } else -+ return FALSE; -+ -+ return radeon_set_mode_for_property(output); - } else if (property == monitor_type_atom) { - const char *s; - if (value->type != XA_STRING || value->format != 8) -@@ -1495,8 +1547,8 @@ radeon_set_property(xf86OutputPtr output, Atom property, - } else if (value->size == strlen("digital") && !strncmp("digital", s, strlen("digital"))) { - radeon_output->DVIType = DVI_DIGITAL; - return TRUE; -- } -- return FALSE; -+ } else -+ return FALSE; - } else if (property == tv_hsize_atom) { - if (value->type != XA_INTEGER || - value->format != 32 || -@@ -1511,7 +1563,7 @@ radeon_set_property(xf86OutputPtr output, Atom property, - radeon_output->hSize = val; - if (radeon_output->tv_on && !IS_AVIVO_VARIANT) - RADEONUpdateHVPosition(output, &output->crtc->mode); -- return TRUE; -+ - } else if (property == tv_hpos_atom) { - if (value->type != XA_INTEGER || - value->format != 32 || -@@ -1526,7 +1578,7 @@ radeon_set_property(xf86OutputPtr output, Atom property, - radeon_output->hPos = val; - if (radeon_output->tv_on && !IS_AVIVO_VARIANT) - RADEONUpdateHVPosition(output, &output->crtc->mode); -- return TRUE; -+ - } else if (property == tv_vpos_atom) { - if (value->type != XA_INTEGER || - value->format != 32 || -@@ -1541,38 +1593,38 @@ radeon_set_property(xf86OutputPtr output, Atom property, - radeon_output->vPos = val; - if (radeon_output->tv_on && !IS_AVIVO_VARIANT) - RADEONUpdateHVPosition(output, &output->crtc->mode); -- return TRUE; -+ - } else if (property == tv_std_atom) { - const char *s; -+ TVStd std = radeon_output->tvStd; -+ - if (value->type != XA_STRING || value->format != 8) - return FALSE; - s = (char*)value->data; - if (value->size == strlen("ntsc") && !strncmp("ntsc", s, strlen("ntsc"))) { - radeon_output->tvStd = TV_STD_NTSC; -- return TRUE; - } else if (value->size == strlen("pal") && !strncmp("pal", s, strlen("pal"))) { - radeon_output->tvStd = TV_STD_PAL; -- return TRUE; - } else if (value->size == strlen("pal-m") && !strncmp("pal-m", s, strlen("pal-m"))) { - radeon_output->tvStd = TV_STD_PAL_M; -- return TRUE; - } else if (value->size == strlen("pal-60") && !strncmp("pal-60", s, strlen("pal-60"))) { - radeon_output->tvStd = TV_STD_PAL_60; -- return TRUE; - } else if (value->size == strlen("ntsc-j") && !strncmp("ntsc-j", s, strlen("ntsc-j"))) { - radeon_output->tvStd = TV_STD_NTSC_J; -- return TRUE; - } else if (value->size == strlen("scart-pal") && !strncmp("scart-pal", s, strlen("scart-pal"))) { - radeon_output->tvStd = TV_STD_SCART_PAL; -- return TRUE; - } else if (value->size == strlen("pal-cn") && !strncmp("pal-cn", s, strlen("pal-cn"))) { - radeon_output->tvStd = TV_STD_PAL_CN; -- return TRUE; - } else if (value->size == strlen("secam") && !strncmp("secam", s, strlen("secam"))) { - radeon_output->tvStd = TV_STD_SECAM; -- return TRUE; -+ } else -+ return FALSE; -+ -+ if (!radeon_set_mode_for_property(output)) { -+ radeon_output->tvStd = std; -+ (void)radeon_set_mode_for_property(output); -+ return FALSE; - } -- return FALSE; - } - - return TRUE; -@@ -1622,6 +1674,8 @@ void RADEONSetOutputType(ScrnInfoPtr pScrn, RADEONOutputPrivatePtr radeon_output - case CONNECTOR_HDMI_TYPE_A: - case CONNECTOR_HDMI_TYPE_B: - output = OUTPUT_HDMI; break; -+ case CONNECTOR_DISPLAY_PORT: -+ output = OUTPUT_DP; break; - case CONNECTOR_DIGITAL: - case CONNECTOR_NONE: - case CONNECTOR_UNSUPPORTED: -@@ -1653,7 +1707,7 @@ Bool AVIVOI2CDoLock(xf86OutputPtr output, int lock_state) - RADEONOutputPrivatePtr radeon_output = output->driver_private; - RADEONI2CBusPtr pRADEONI2CBus = radeon_output->pI2CBus->DriverPrivate.ptr; - unsigned char *RADEONMMIO = info->MMIO; -- CARD32 temp; -+ uint32_t temp; - - temp = INREG(pRADEONI2CBus->mask_clk_reg); - if (lock_state == AVIVO_I2C_ENABLE) -@@ -1698,13 +1752,13 @@ static void RADEONI2CPutBits(I2CBusPtr b, int Clock, int data) - unsigned char *RADEONMMIO = info->MMIO; - RADEONI2CBusPtr pRADEONI2CBus = b->DriverPrivate.ptr; - -- val = INREG(pRADEONI2CBus->put_clk_reg) & (CARD32)~(pRADEONI2CBus->put_clk_mask); -+ val = INREG(pRADEONI2CBus->put_clk_reg) & (uint32_t)~(pRADEONI2CBus->put_clk_mask); - val |= (Clock ? 0:pRADEONI2CBus->put_clk_mask); - OUTREG(pRADEONI2CBus->put_clk_reg, val); - /* read back to improve reliability on some cards. */ - val = INREG(pRADEONI2CBus->put_clk_reg); - -- val = INREG(pRADEONI2CBus->put_data_reg) & (CARD32)~(pRADEONI2CBus->put_data_mask); -+ val = INREG(pRADEONI2CBus->put_data_reg) & (uint32_t)~(pRADEONI2CBus->put_data_mask); - val |= (data ? 0:pRADEONI2CBus->put_data_mask); - OUTREG(pRADEONI2CBus->put_data_reg, val); - /* read back to improve reliability on some cards. */ -@@ -1821,8 +1875,8 @@ RADEONGetPanelInfoFromReg (xf86OutputPtr output) - RADEONInfoPtr info = RADEONPTR(pScrn); - RADEONOutputPrivatePtr radeon_output = output->driver_private; - unsigned char *RADEONMMIO = info->MMIO; -- CARD32 fp_vert_stretch = INREG(RADEON_FP_VERT_STRETCH); -- CARD32 fp_horz_stretch = INREG(RADEON_FP_HORZ_STRETCH); -+ uint32_t fp_vert_stretch = INREG(RADEON_FP_VERT_STRETCH); -+ uint32_t fp_horz_stretch = INREG(RADEON_FP_HORZ_STRETCH); - - radeon_output->PanelPwrDly = 200; - if (fp_vert_stretch & RADEON_VERT_STRETCH_ENABLE) { -@@ -1845,7 +1899,7 @@ RADEONGetPanelInfoFromReg (xf86OutputPtr output) - - // move this to crtc function - if (xf86ReturnOptValBool(info->Options, OPTION_LVDS_PROBE_PLL, TRUE)) { -- CARD32 ppll_div_sel, ppll_val; -+ uint32_t ppll_div_sel, ppll_val; - - ppll_div_sel = INREG8(RADEON_CLOCK_CNTL_INDEX + 1) & 0x3; - RADEONPllErrataAfterIndex(info); -@@ -2067,9 +2121,8 @@ RADEONGetTMDSInfo(xf86OutputPtr output) - radeon_output->tmds_pll[i].freq = 0; - } - -- if (RADEONGetTMDSInfoFromBIOS(output)) return; -- -- RADEONGetTMDSInfoFromTable(output); -+ if (!RADEONGetTMDSInfoFromBIOS(output)) -+ RADEONGetTMDSInfoFromTable(output); - - } - -@@ -2139,16 +2192,17 @@ void RADEONInitConnector(xf86OutputPtr output) - RADEONInfoPtr info = RADEONPTR(pScrn); - RADEONOutputPrivatePtr radeon_output = output->driver_private; - -- if (radeon_output->DACType == DAC_PRIMARY) -+ if (info->IsAtomBios && -+ ((radeon_output->DACType == DAC_PRIMARY) || -+ (radeon_output->DACType == DAC_TVDAC))) -+ radeon_output->load_detection = 1; -+ else if (radeon_output->DACType == DAC_PRIMARY) - radeon_output->load_detection = 1; /* primary dac, only drives vga */ -- /*else if (radeon_output->DACType == DAC_TVDAC && -- info->tvdac_use_count < 2) -- radeon_output->load_detection = 1;*/ /* only one output with tvdac */ - else if ((radeon_output->DACType == DAC_TVDAC) && - (xf86ReturnOptValBool(info->Options, OPTION_TVDAC_LOAD_DETECT, FALSE))) - radeon_output->load_detection = 1; /* shared tvdac between vga/dvi/tv */ - else -- radeon_output->load_detection = 0; /* shared tvdac between vga/dvi/tv */ -+ radeon_output->load_detection = 0; - - if (radeon_output->type == OUTPUT_LVDS) { - radeon_output->rmx_type = RMX_FULL; -@@ -2179,16 +2233,17 @@ void RADEONInitConnector(xf86OutputPtr output) - RADEONGetTMDSInfo(output); - } - -- if (OUTPUT_IS_TV) { -+ if (OUTPUT_IS_TV) - RADEONGetTVInfo(output); -- RADEONGetTVDacAdjInfo(output); -- } - - if (radeon_output->DACType == DAC_TVDAC) { - radeon_output->tv_on = FALSE; - RADEONGetTVDacAdjInfo(output); - } - -+ if (OUTPUT_IS_DVI || (radeon_output->type == OUTPUT_HDMI)) -+ radeon_output->coherent_mode = TRUE; -+ - if (radeon_output->ddc_i2c.valid) - RADEONI2CInit(output, &radeon_output->pI2CBus, output->name, FALSE); - -@@ -2263,7 +2318,7 @@ static Bool RADEONSetupAppleConnectors(ScrnInfoPtr pScrn) - info->BiosConnector[0].ddc_i2c = legacy_setup_i2c_bus(RADEON_GPIO_DVI_DDC); - info->BiosConnector[0].DACType = DAC_NONE; - info->BiosConnector[0].TMDSType = TMDS_NONE; -- info->BiosConnector[0].ConnectorType = CONNECTOR_VGA; -+ info->BiosConnector[0].ConnectorType = CONNECTOR_LVDS; - info->BiosConnector[0].valid = TRUE; - - info->BiosConnector[1].ddc_i2c = legacy_setup_i2c_bus(RADEON_GPIO_VGA_DDC); -@@ -2393,7 +2448,8 @@ static void RADEONSetupGenericConnectors(ScrnInfoPtr pScrn) - info->BiosConnector[0].valid = TRUE; - - /* IGP only has TVDAC */ -- if (info->ChipFamily == CHIP_FAMILY_RS400) -+ if ((info->ChipFamily == CHIP_FAMILY_RS400) || -+ (info->ChipFamily == CHIP_FAMILY_RS480)) - info->BiosConnector[1].ddc_i2c = legacy_setup_i2c_bus(RADEON_GPIO_CRT2_DDC); - else - info->BiosConnector[1].ddc_i2c = legacy_setup_i2c_bus(RADEON_GPIO_VGA_DDC); -@@ -2421,7 +2477,8 @@ static void RADEONSetupGenericConnectors(ScrnInfoPtr pScrn) - } else { - /* Below is the most common setting, but may not be true */ - if (info->IsIGP) { -- if (info->ChipFamily == CHIP_FAMILY_RS400) -+ if ((info->ChipFamily == CHIP_FAMILY_RS400) || -+ (info->ChipFamily == CHIP_FAMILY_RS480)) - info->BiosConnector[0].ddc_i2c = legacy_setup_i2c_bus(RADEON_GPIO_CRT2_DDC); - else - info->BiosConnector[0].ddc_i2c = legacy_setup_i2c_bus(RADEON_GPIO_VGA_DDC); -@@ -2595,10 +2652,47 @@ static RADEONMacModel RADEONDetectMacModel(ScrnInfoPtr pScrn) - - #endif /* __powerpc__ */ - -+static int -+radeon_output_clones (ScrnInfoPtr pScrn, xf86OutputPtr output) -+{ -+ RADEONOutputPrivatePtr radeon_output = output->driver_private; -+ RADEONInfoPtr info = RADEONPTR(pScrn); -+ xf86CrtcConfigPtr config = XF86_CRTC_CONFIG_PTR (pScrn); -+ int o; -+ int index_mask = 0; -+ -+ if (IS_DCE3_VARIANT) -+ return index_mask; -+ -+ /* LVDS is too wacky */ -+ if (radeon_output->type == OUTPUT_LVDS) -+ return index_mask; -+ -+ for (o = 0; o < config->num_output; o++) { -+ xf86OutputPtr clone = config->output[o]; -+ RADEONOutputPrivatePtr radeon_clone = clone->driver_private; -+ if (output == clone) /* don't clone yourself */ -+ continue; -+ else if (radeon_clone->type == OUTPUT_LVDS) /* LVDS */ -+ continue; -+ else if ((radeon_output->DACType != DAC_NONE) && -+ (radeon_output->DACType == radeon_clone->DACType)) /* shared dac */ -+ continue; -+ else if ((radeon_output->TMDSType != TMDS_NONE) && -+ (radeon_output->TMDSType == radeon_clone->TMDSType)) /* shared tmds */ -+ continue; -+ else -+ index_mask |= (1 << o); -+ } -+ -+ return index_mask; -+} -+ - /* - * initialise the static data sos we don't have to re-do at randr change */ - Bool RADEONSetupConnectors(ScrnInfoPtr pScrn) - { -+ xf86CrtcConfigPtr xf86_config = XF86_CRTC_CONFIG_PTR(pScrn); - RADEONInfoPtr info = RADEONPTR(pScrn); - RADEONEntPtr pRADEONEnt = RADEONEntPriv(pScrn); - xf86OutputPtr output; -@@ -2729,11 +2823,12 @@ Bool RADEONSetupConnectors(ScrnInfoPtr pScrn) - - for (i = 0 ; i < RADEON_MAX_BIOS_CONNECTOR; i++) { - if (info->BiosConnector[i].valid) { -+ RADEONOutputPrivatePtr radeon_output; - - if (info->BiosConnector[i].ConnectorType == CONNECTOR_NONE) - continue; - -- RADEONOutputPrivatePtr radeon_output = xnfcalloc(sizeof(RADEONOutputPrivateRec), 1); -+ radeon_output = xnfcalloc(sizeof(RADEONOutputPrivateRec), 1); - if (!radeon_output) { - return FALSE; - } -@@ -2742,6 +2837,7 @@ Bool RADEONSetupConnectors(ScrnInfoPtr pScrn) - radeon_output->devices = info->BiosConnector[i].devices; - radeon_output->output_id = info->BiosConnector[i].output_id; - radeon_output->ddc_i2c = info->BiosConnector[i].ddc_i2c; -+ radeon_output->igp_lane_info = info->BiosConnector[i].igp_lane_info; - - if (radeon_output->ConnectorType == CONNECTOR_DVI_D) - radeon_output->DACType = DAC_NONE; -@@ -2798,6 +2894,12 @@ Bool RADEONSetupConnectors(ScrnInfoPtr pScrn) - } - } - -+ for (i = 0; i < xf86_config->num_output; i++) { -+ xf86OutputPtr output = xf86_config->output[i]; -+ -+ output->possible_clones = radeon_output_clones(pScrn, output); -+ } -+ - return TRUE; - } - -diff --git a/src/radeon_pci_chipset_gen.h b/src/radeon_pci_chipset_gen.h -index ab6b62a..f24deb5 100644 ---- a/src/radeon_pci_chipset_gen.h -+++ b/src/radeon_pci_chipset_gen.h -@@ -1,6 +1,7 @@ - /* This file is autogenerated please do not edit */ - PciChipsets RADEONPciChipsets[] = { - { PCI_CHIP_RV380_3150, PCI_CHIP_RV380_3150, RES_SHARED_VGA }, -+ { PCI_CHIP_RV380_3151, PCI_CHIP_RV380_3151, RES_SHARED_VGA }, - { PCI_CHIP_RV380_3152, PCI_CHIP_RV380_3152, RES_SHARED_VGA }, - { PCI_CHIP_RV380_3154, PCI_CHIP_RV380_3154, RES_SHARED_VGA }, - { PCI_CHIP_RV380_3E50, PCI_CHIP_RV380_3E50, RES_SHARED_VGA }, -@@ -96,6 +97,7 @@ PciChipsets RADEONPciChipsets[] = { - { PCI_CHIP_RV410_564F, PCI_CHIP_RV410_564F, RES_SHARED_VGA }, - { PCI_CHIP_RV410_5652, PCI_CHIP_RV410_5652, RES_SHARED_VGA }, - { PCI_CHIP_RV410_5653, PCI_CHIP_RV410_5653, RES_SHARED_VGA }, -+ { PCI_CHIP_RV410_5657, PCI_CHIP_RV410_5657, RES_SHARED_VGA }, - { PCI_CHIP_RS300_5834, PCI_CHIP_RS300_5834, RES_SHARED_VGA }, - { PCI_CHIP_RS300_5835, PCI_CHIP_RS300_5835, RES_SHARED_VGA }, - { PCI_CHIP_RS480_5954, PCI_CHIP_RS480_5954, RES_SHARED_VGA }, -@@ -115,7 +117,6 @@ PciChipsets RADEONPciChipsets[] = { - { PCI_CHIP_RV370_5B60, PCI_CHIP_RV370_5B60, RES_SHARED_VGA }, - { PCI_CHIP_RV370_5B62, PCI_CHIP_RV370_5B62, RES_SHARED_VGA }, - { PCI_CHIP_RV370_5B63, PCI_CHIP_RV370_5B63, RES_SHARED_VGA }, -- { PCI_CHIP_RV370_5657, PCI_CHIP_RV370_5657, RES_SHARED_VGA }, - { PCI_CHIP_RV370_5B64, PCI_CHIP_RV370_5B64, RES_SHARED_VGA }, - { PCI_CHIP_RV370_5B65, PCI_CHIP_RV370_5B65, RES_SHARED_VGA }, - { PCI_CHIP_RV280_5C61, PCI_CHIP_RV280_5C61, RES_SHARED_VGA }, -@@ -201,9 +202,9 @@ PciChipsets RADEONPciChipsets[] = { - { PCI_CHIP_RV530_71D6, PCI_CHIP_RV530_71D6, RES_SHARED_VGA }, - { PCI_CHIP_RV530_71DA, PCI_CHIP_RV530_71DA, RES_SHARED_VGA }, - { PCI_CHIP_RV530_71DE, PCI_CHIP_RV530_71DE, RES_SHARED_VGA }, -- { PCI_CHIP_RV530_7200, PCI_CHIP_RV530_7200, RES_SHARED_VGA }, -- { PCI_CHIP_RV530_7210, PCI_CHIP_RV530_7210, RES_SHARED_VGA }, -- { PCI_CHIP_RV530_7211, PCI_CHIP_RV530_7211, RES_SHARED_VGA }, -+ { PCI_CHIP_RV515_7200, PCI_CHIP_RV515_7200, RES_SHARED_VGA }, -+ { PCI_CHIP_RV515_7210, PCI_CHIP_RV515_7210, RES_SHARED_VGA }, -+ { PCI_CHIP_RV515_7211, PCI_CHIP_RV515_7211, RES_SHARED_VGA }, - { PCI_CHIP_R580_7240, PCI_CHIP_R580_7240, RES_SHARED_VGA }, - { PCI_CHIP_R580_7243, PCI_CHIP_R580_7243, RES_SHARED_VGA }, - { PCI_CHIP_R580_7244, PCI_CHIP_R580_7244, RES_SHARED_VGA }, -@@ -235,6 +236,9 @@ PciChipsets RADEONPciChipsets[] = { - { PCI_CHIP_RS350_7835, PCI_CHIP_RS350_7835, RES_SHARED_VGA }, - { PCI_CHIP_RS690_791E, PCI_CHIP_RS690_791E, RES_SHARED_VGA }, - { PCI_CHIP_RS690_791F, PCI_CHIP_RS690_791F, RES_SHARED_VGA }, -+ { PCI_CHIP_RS600_793F, PCI_CHIP_RS600_793F, RES_SHARED_VGA }, -+ { PCI_CHIP_RS600_7941, PCI_CHIP_RS600_7941, RES_SHARED_VGA }, -+ { PCI_CHIP_RS600_7942, PCI_CHIP_RS600_7942, RES_SHARED_VGA }, - { PCI_CHIP_RS740_796C, PCI_CHIP_RS740_796C, RES_SHARED_VGA }, - { PCI_CHIP_RS740_796D, PCI_CHIP_RS740_796D, RES_SHARED_VGA }, - { PCI_CHIP_RS740_796E, PCI_CHIP_RS740_796E, RES_SHARED_VGA }, -@@ -247,6 +251,8 @@ PciChipsets RADEONPciChipsets[] = { - { PCI_CHIP_R600_940A, PCI_CHIP_R600_940A, RES_SHARED_VGA }, - { PCI_CHIP_R600_940B, PCI_CHIP_R600_940B, RES_SHARED_VGA }, - { PCI_CHIP_R600_940F, PCI_CHIP_R600_940F, RES_SHARED_VGA }, -+ { PCI_CHIP_RV770_9440, PCI_CHIP_RV770_9440, RES_SHARED_VGA }, -+ { PCI_CHIP_RV770_9442, PCI_CHIP_RV770_9442, RES_SHARED_VGA }, - { PCI_CHIP_RV610_94C0, PCI_CHIP_RV610_94C0, RES_SHARED_VGA }, - { PCI_CHIP_RV610_94C1, PCI_CHIP_RV610_94C1, RES_SHARED_VGA }, - { PCI_CHIP_RV610_94C3, PCI_CHIP_RV610_94C3, RES_SHARED_VGA }, -@@ -264,6 +270,7 @@ PciChipsets RADEONPciChipsets[] = { - { PCI_CHIP_RV670_9507, PCI_CHIP_RV670_9507, RES_SHARED_VGA }, - { PCI_CHIP_RV670_950F, PCI_CHIP_RV670_950F, RES_SHARED_VGA }, - { PCI_CHIP_RV670_9511, PCI_CHIP_RV670_9511, RES_SHARED_VGA }, -+ { PCI_CHIP_RV670_9515, PCI_CHIP_RV670_9515, RES_SHARED_VGA }, - { PCI_CHIP_RV630_9580, PCI_CHIP_RV630_9580, RES_SHARED_VGA }, - { PCI_CHIP_RV630_9581, PCI_CHIP_RV630_9581, RES_SHARED_VGA }, - { PCI_CHIP_RV630_9583, PCI_CHIP_RV630_9583, RES_SHARED_VGA }, -@@ -276,5 +283,24 @@ PciChipsets RADEONPciChipsets[] = { - { PCI_CHIP_RV630_958C, PCI_CHIP_RV630_958C, RES_SHARED_VGA }, - { PCI_CHIP_RV630_958D, PCI_CHIP_RV630_958D, RES_SHARED_VGA }, - { PCI_CHIP_RV630_958E, PCI_CHIP_RV630_958E, RES_SHARED_VGA }, -+ { PCI_CHIP_RV620_95C0, PCI_CHIP_RV620_95C0, RES_SHARED_VGA }, -+ { PCI_CHIP_RV620_95C5, PCI_CHIP_RV620_95C5, RES_SHARED_VGA }, -+ { PCI_CHIP_RV620_95C7, PCI_CHIP_RV620_95C7, RES_SHARED_VGA }, -+ { PCI_CHIP_RV620_95C2, PCI_CHIP_RV620_95C2, RES_SHARED_VGA }, -+ { PCI_CHIP_RV620_95C4, PCI_CHIP_RV620_95C4, RES_SHARED_VGA }, -+ { PCI_CHIP_RV620_95CD, PCI_CHIP_RV620_95CD, RES_SHARED_VGA }, -+ { PCI_CHIP_RV620_95CE, PCI_CHIP_RV620_95CE, RES_SHARED_VGA }, -+ { PCI_CHIP_RV620_95CF, PCI_CHIP_RV620_95CF, RES_SHARED_VGA }, -+ { PCI_CHIP_RV635_9590, PCI_CHIP_RV635_9590, RES_SHARED_VGA }, -+ { PCI_CHIP_RV635_9596, PCI_CHIP_RV635_9596, RES_SHARED_VGA }, -+ { PCI_CHIP_RV635_9597, PCI_CHIP_RV635_9597, RES_SHARED_VGA }, -+ { PCI_CHIP_RV635_9598, PCI_CHIP_RV635_9598, RES_SHARED_VGA }, -+ { PCI_CHIP_RV635_9599, PCI_CHIP_RV635_9599, RES_SHARED_VGA }, -+ { PCI_CHIP_RV635_9591, PCI_CHIP_RV635_9591, RES_SHARED_VGA }, -+ { PCI_CHIP_RV635_9593, PCI_CHIP_RV635_9593, RES_SHARED_VGA }, -+ { PCI_CHIP_RS780_9610, PCI_CHIP_RS780_9610, RES_SHARED_VGA }, -+ { PCI_CHIP_RS780_9611, PCI_CHIP_RS780_9611, RES_SHARED_VGA }, -+ { PCI_CHIP_RS780_9612, PCI_CHIP_RS780_9612, RES_SHARED_VGA }, -+ { PCI_CHIP_RS780_9613, PCI_CHIP_RS780_9613, RES_SHARED_VGA }, - { -1, -1, RES_UNDEFINED } - }; -diff --git a/src/radeon_pci_device_match_gen.h b/src/radeon_pci_device_match_gen.h -index 04393da..aa19d6a 100644 ---- a/src/radeon_pci_device_match_gen.h -+++ b/src/radeon_pci_device_match_gen.h -@@ -1,6 +1,7 @@ - /* This file is autogenerated please do not edit */ - static const struct pci_id_match radeon_device_match[] = { - ATI_DEVICE_MATCH( PCI_CHIP_RV380_3150, 0 ), -+ ATI_DEVICE_MATCH( PCI_CHIP_RV380_3151, 0 ), - ATI_DEVICE_MATCH( PCI_CHIP_RV380_3152, 0 ), - ATI_DEVICE_MATCH( PCI_CHIP_RV380_3154, 0 ), - ATI_DEVICE_MATCH( PCI_CHIP_RV380_3E50, 0 ), -@@ -96,6 +97,7 @@ static const struct pci_id_match radeon_device_match[] = { - ATI_DEVICE_MATCH( PCI_CHIP_RV410_564F, 0 ), - ATI_DEVICE_MATCH( PCI_CHIP_RV410_5652, 0 ), - ATI_DEVICE_MATCH( PCI_CHIP_RV410_5653, 0 ), -+ ATI_DEVICE_MATCH( PCI_CHIP_RV410_5657, 0 ), - ATI_DEVICE_MATCH( PCI_CHIP_RS300_5834, 0 ), - ATI_DEVICE_MATCH( PCI_CHIP_RS300_5835, 0 ), - ATI_DEVICE_MATCH( PCI_CHIP_RS480_5954, 0 ), -@@ -115,7 +117,6 @@ static const struct pci_id_match radeon_device_match[] = { - ATI_DEVICE_MATCH( PCI_CHIP_RV370_5B60, 0 ), - ATI_DEVICE_MATCH( PCI_CHIP_RV370_5B62, 0 ), - ATI_DEVICE_MATCH( PCI_CHIP_RV370_5B63, 0 ), -- ATI_DEVICE_MATCH( PCI_CHIP_RV370_5657, 0 ), - ATI_DEVICE_MATCH( PCI_CHIP_RV370_5B64, 0 ), - ATI_DEVICE_MATCH( PCI_CHIP_RV370_5B65, 0 ), - ATI_DEVICE_MATCH( PCI_CHIP_RV280_5C61, 0 ), -@@ -201,9 +202,9 @@ static const struct pci_id_match radeon_device_match[] = { - ATI_DEVICE_MATCH( PCI_CHIP_RV530_71D6, 0 ), - ATI_DEVICE_MATCH( PCI_CHIP_RV530_71DA, 0 ), - ATI_DEVICE_MATCH( PCI_CHIP_RV530_71DE, 0 ), -- ATI_DEVICE_MATCH( PCI_CHIP_RV530_7200, 0 ), -- ATI_DEVICE_MATCH( PCI_CHIP_RV530_7210, 0 ), -- ATI_DEVICE_MATCH( PCI_CHIP_RV530_7211, 0 ), -+ ATI_DEVICE_MATCH( PCI_CHIP_RV515_7200, 0 ), -+ ATI_DEVICE_MATCH( PCI_CHIP_RV515_7210, 0 ), -+ ATI_DEVICE_MATCH( PCI_CHIP_RV515_7211, 0 ), - ATI_DEVICE_MATCH( PCI_CHIP_R580_7240, 0 ), - ATI_DEVICE_MATCH( PCI_CHIP_R580_7243, 0 ), - ATI_DEVICE_MATCH( PCI_CHIP_R580_7244, 0 ), -@@ -235,6 +236,9 @@ static const struct pci_id_match radeon_device_match[] = { - ATI_DEVICE_MATCH( PCI_CHIP_RS350_7835, 0 ), - ATI_DEVICE_MATCH( PCI_CHIP_RS690_791E, 0 ), - ATI_DEVICE_MATCH( PCI_CHIP_RS690_791F, 0 ), -+ ATI_DEVICE_MATCH( PCI_CHIP_RS600_793F, 0 ), -+ ATI_DEVICE_MATCH( PCI_CHIP_RS600_7941, 0 ), -+ ATI_DEVICE_MATCH( PCI_CHIP_RS600_7942, 0 ), - ATI_DEVICE_MATCH( PCI_CHIP_RS740_796C, 0 ), - ATI_DEVICE_MATCH( PCI_CHIP_RS740_796D, 0 ), - ATI_DEVICE_MATCH( PCI_CHIP_RS740_796E, 0 ), -@@ -247,6 +251,8 @@ static const struct pci_id_match radeon_device_match[] = { - ATI_DEVICE_MATCH( PCI_CHIP_R600_940A, 0 ), - ATI_DEVICE_MATCH( PCI_CHIP_R600_940B, 0 ), - ATI_DEVICE_MATCH( PCI_CHIP_R600_940F, 0 ), -+ ATI_DEVICE_MATCH( PCI_CHIP_RV770_9440, 0 ), -+ ATI_DEVICE_MATCH( PCI_CHIP_RV770_9442, 0 ), - ATI_DEVICE_MATCH( PCI_CHIP_RV610_94C0, 0 ), - ATI_DEVICE_MATCH( PCI_CHIP_RV610_94C1, 0 ), - ATI_DEVICE_MATCH( PCI_CHIP_RV610_94C3, 0 ), -@@ -264,6 +270,7 @@ static const struct pci_id_match radeon_device_match[] = { - ATI_DEVICE_MATCH( PCI_CHIP_RV670_9507, 0 ), - ATI_DEVICE_MATCH( PCI_CHIP_RV670_950F, 0 ), - ATI_DEVICE_MATCH( PCI_CHIP_RV670_9511, 0 ), -+ ATI_DEVICE_MATCH( PCI_CHIP_RV670_9515, 0 ), - ATI_DEVICE_MATCH( PCI_CHIP_RV630_9580, 0 ), - ATI_DEVICE_MATCH( PCI_CHIP_RV630_9581, 0 ), - ATI_DEVICE_MATCH( PCI_CHIP_RV630_9583, 0 ), -@@ -276,5 +283,24 @@ static const struct pci_id_match radeon_device_match[] = { - ATI_DEVICE_MATCH( PCI_CHIP_RV630_958C, 0 ), - ATI_DEVICE_MATCH( PCI_CHIP_RV630_958D, 0 ), - ATI_DEVICE_MATCH( PCI_CHIP_RV630_958E, 0 ), -+ ATI_DEVICE_MATCH( PCI_CHIP_RV620_95C0, 0 ), -+ ATI_DEVICE_MATCH( PCI_CHIP_RV620_95C5, 0 ), -+ ATI_DEVICE_MATCH( PCI_CHIP_RV620_95C7, 0 ), -+ ATI_DEVICE_MATCH( PCI_CHIP_RV620_95C2, 0 ), -+ ATI_DEVICE_MATCH( PCI_CHIP_RV620_95C4, 0 ), -+ ATI_DEVICE_MATCH( PCI_CHIP_RV620_95CD, 0 ), -+ ATI_DEVICE_MATCH( PCI_CHIP_RV620_95CE, 0 ), -+ ATI_DEVICE_MATCH( PCI_CHIP_RV620_95CF, 0 ), -+ ATI_DEVICE_MATCH( PCI_CHIP_RV635_9590, 0 ), -+ ATI_DEVICE_MATCH( PCI_CHIP_RV635_9596, 0 ), -+ ATI_DEVICE_MATCH( PCI_CHIP_RV635_9597, 0 ), -+ ATI_DEVICE_MATCH( PCI_CHIP_RV635_9598, 0 ), -+ ATI_DEVICE_MATCH( PCI_CHIP_RV635_9599, 0 ), -+ ATI_DEVICE_MATCH( PCI_CHIP_RV635_9591, 0 ), -+ ATI_DEVICE_MATCH( PCI_CHIP_RV635_9593, 0 ), -+ ATI_DEVICE_MATCH( PCI_CHIP_RS780_9610, 0 ), -+ ATI_DEVICE_MATCH( PCI_CHIP_RS780_9611, 0 ), -+ ATI_DEVICE_MATCH( PCI_CHIP_RS780_9612, 0 ), -+ ATI_DEVICE_MATCH( PCI_CHIP_RS780_9613, 0 ), - { 0, 0, 0 } - }; -diff --git a/src/radeon_probe.c b/src/radeon_probe.c -index 4ec7485..5d2eb43 100644 ---- a/src/radeon_probe.c -+++ b/src/radeon_probe.c -@@ -60,7 +60,7 @@ - static Bool RADEONProbe(DriverPtr drv, int flags); - #endif - --int gRADEONEntityIndex = -1; -+_X_EXPORT int gRADEONEntityIndex = -1; - - /* Return the options for supported chipset 'n'; NULL otherwise */ - static const OptionInfoRec * -diff --git a/src/radeon_probe.h b/src/radeon_probe.h -index 9c1bdc5..944ab9f 100644 ---- a/src/radeon_probe.h -+++ b/src/radeon_probe.h -@@ -104,7 +104,8 @@ typedef enum - TMDS_INT = 1, - TMDS_EXT = 2, - TMDS_LVTMA = 3, -- TMDS_DDIA = 4 -+ TMDS_DDIA = 4, -+ TMDS_UNIPHY = 5 - } RADEONTmdsType; - - typedef enum -@@ -122,8 +123,8 @@ typedef enum - } RADEONRMXType; - - typedef struct { -- CARD32 freq; -- CARD32 value; -+ uint32_t freq; -+ uint32_t value; - }RADEONTMDSPll; - - typedef enum -@@ -163,18 +164,18 @@ typedef enum - typedef struct - { - Bool valid; -- CARD32 mask_clk_reg; -- CARD32 mask_data_reg; -- CARD32 put_clk_reg; -- CARD32 put_data_reg; -- CARD32 get_clk_reg; -- CARD32 get_data_reg; -- CARD32 mask_clk_mask; -- CARD32 mask_data_mask; -- CARD32 put_clk_mask; -- CARD32 put_data_mask; -- CARD32 get_clk_mask; -- CARD32 get_data_mask; -+ uint32_t mask_clk_reg; -+ uint32_t mask_data_reg; -+ uint32_t put_clk_reg; -+ uint32_t put_data_reg; -+ uint32_t get_clk_reg; -+ uint32_t get_data_reg; -+ uint32_t mask_clk_mask; -+ uint32_t mask_data_mask; -+ uint32_t put_clk_mask; -+ uint32_t put_data_mask; -+ uint32_t get_clk_mask; -+ uint32_t get_data_mask; - } RADEONI2CBusRec, *RADEONI2CBusPtr; - - typedef struct _RADEONCrtcPrivateRec { -@@ -186,17 +187,13 @@ typedef struct _RADEONCrtcPrivateRec { - #endif - int crtc_id; - int binding; -- CARD32 cursor_offset; -+ uint32_t cursor_offset; - /* Lookup table values to be set when the CRTC is enabled */ -- CARD8 lut_r[256], lut_g[256], lut_b[256]; -+ uint8_t lut_r[256], lut_g[256], lut_b[256]; - - uint32_t crtc_offset; -- int h_total, h_blank, h_sync_wid, h_sync_pol; -- int v_total, v_blank, v_sync_wid, v_sync_pol; -- int fb_format, fb_length; -- int fb_pitch, fb_width, fb_height; -- INT16 cursor_x; -- INT16 cursor_y; -+ int can_tile; -+ Bool enabled; - } RADEONCrtcPrivateRec, *RADEONCrtcPrivatePtr; - - typedef struct { -@@ -208,13 +205,14 @@ typedef struct { - int devices; - int hpd_mask; - RADEONI2CBusRec ddc_i2c; -+ int igp_lane_info; - } RADEONBIOSConnector; - - typedef struct _RADEONOutputPrivateRec { - int num; - RADEONOutputType type; - void *dev_priv; -- CARD32 ddc_line; -+ uint32_t ddc_line; - RADEONDacType DACType; - RADEONDviType DVIType; - RADEONTmdsType TMDSType; -@@ -224,9 +222,9 @@ typedef struct _RADEONOutputPrivateRec { - int DDCReg; - I2CBusPtr pI2CBus; - RADEONI2CBusRec ddc_i2c; -- CARD32 ps2_tvdac_adj; -- CARD32 pal_tvdac_adj; -- CARD32 ntsc_tvdac_adj; -+ uint32_t ps2_tvdac_adj; -+ uint32_t pal_tvdac_adj; -+ uint32_t ntsc_tvdac_adj; - /* panel stuff */ - int PanelXRes; - int PanelYRes; -@@ -256,95 +254,81 @@ typedef struct _RADEONOutputPrivateRec { - int SupportedTVStds; - Bool tv_on; - int load_detection; -+ /* dig block */ -+ int transmitter_config; -+ Bool coherent_mode; -+ int igp_lane_info; - - char *name; - int output_id; - int devices; -+ Bool enabled; - } RADEONOutputPrivateRec, *RADEONOutputPrivatePtr; - - struct avivo_pll_state { -- CARD32 ref_div_src; -- CARD32 ref_div; -- CARD32 fb_div; -- CARD32 post_div_src; -- CARD32 post_div; -- CARD32 ext_ppll_cntl; -- CARD32 pll_cntl; -- CARD32 int_ss_cntl; -+ uint32_t ref_div_src; -+ uint32_t ref_div; -+ uint32_t fb_div; -+ uint32_t post_div_src; -+ uint32_t post_div; -+ uint32_t ext_ppll_cntl; -+ uint32_t pll_cntl; -+ uint32_t int_ss_cntl; - }; - -- - struct avivo_crtc_state { -- CARD32 pll_source; -- CARD32 h_total; -- CARD32 h_blank_start_end; -- CARD32 h_sync_a; -- CARD32 h_sync_a_cntl; -- CARD32 h_sync_b; -- CARD32 h_sync_b_cntl; -- CARD32 v_total; -- CARD32 v_blank_start_end; -- CARD32 v_sync_a; -- CARD32 v_sync_a_cntl; -- CARD32 v_sync_b; -- CARD32 v_sync_b_cntl; -- CARD32 control; -- CARD32 blank_control; -- CARD32 interlace_control; -- CARD32 stereo_control; -- CARD32 cursor_control; -+ uint32_t pll_source; -+ uint32_t h_total; -+ uint32_t h_blank_start_end; -+ uint32_t h_sync_a; -+ uint32_t h_sync_a_cntl; -+ uint32_t h_sync_b; -+ uint32_t h_sync_b_cntl; -+ uint32_t v_total; -+ uint32_t v_blank_start_end; -+ uint32_t v_sync_a; -+ uint32_t v_sync_a_cntl; -+ uint32_t v_sync_b; -+ uint32_t v_sync_b_cntl; -+ uint32_t control; -+ uint32_t blank_control; -+ uint32_t interlace_control; -+ uint32_t stereo_control; -+ uint32_t cursor_control; - }; - - struct avivo_grph_state { -- CARD32 enable; -- CARD32 control; -- CARD32 prim_surf_addr; -- CARD32 sec_surf_addr; -- CARD32 pitch; -- CARD32 x_offset; -- CARD32 y_offset; -- CARD32 x_start; -- CARD32 y_start; -- CARD32 x_end; -- CARD32 y_end; -- -- CARD32 viewport_start; -- CARD32 viewport_size; -- CARD32 scl_enable; -- CARD32 scl_tap_control; --}; -- --struct avivo_dac_state { -- CARD32 enable; -- CARD32 source_select; -- CARD32 force_output_cntl; -- CARD32 powerdown; --}; -- --struct avivo_dig_state { -- CARD32 cntl; -- CARD32 bit_depth_cntl; -- CARD32 data_sync; -- CARD32 transmitter_enable; -- CARD32 transmitter_cntl; -- CARD32 source_select; -+ uint32_t enable; -+ uint32_t control; -+ uint32_t prim_surf_addr; -+ uint32_t sec_surf_addr; -+ uint32_t pitch; -+ uint32_t x_offset; -+ uint32_t y_offset; -+ uint32_t x_start; -+ uint32_t y_start; -+ uint32_t x_end; -+ uint32_t y_end; -+ -+ uint32_t desktop_height; -+ uint32_t viewport_start; -+ uint32_t viewport_size; -+ uint32_t mode_data_format; - }; - - struct avivo_state - { -- CARD32 hdp_fb_location; -- CARD32 mc_memory_map; -- CARD32 vga_memory_base; -- CARD32 vga_fb_start; -+ uint32_t hdp_fb_location; -+ uint32_t mc_memory_map; -+ uint32_t vga_memory_base; -+ uint32_t vga_fb_start; - -- CARD32 vga1_cntl; -- CARD32 vga2_cntl; -+ uint32_t vga1_cntl; -+ uint32_t vga2_cntl; - -- CARD32 crtc_master_en; -- CARD32 crtc_tv_control; -- -- CARD32 lvtma_pwrseq_cntl; -- CARD32 lvtma_pwrseq_state; -+ uint32_t crtc_master_en; -+ uint32_t crtc_tv_control; -+ uint32_t dc_lb_memory_split; - - struct avivo_pll_state pll1; - struct avivo_pll_state pll2; -@@ -355,11 +339,41 @@ struct avivo_state - struct avivo_grph_state grph1; - struct avivo_grph_state grph2; - -- struct avivo_dac_state daca; -- struct avivo_dac_state dacb; -- -- struct avivo_dig_state tmds1; -- struct avivo_dig_state tmds2; -+ /* DDIA block on RS6xx chips */ -+ uint32_t ddia[37]; -+ -+ /* scalers */ -+ uint32_t d1scl[40]; -+ uint32_t d2scl[40]; -+ uint32_t dxscl[6+2]; -+ -+ /* dac regs */ -+ uint32_t daca[26]; -+ uint32_t dacb[26]; -+ -+ /* tmdsa */ -+ uint32_t tmdsa[31]; -+ -+ /* lvtma */ -+ uint32_t lvtma[39]; -+ -+ /* dvoa */ -+ uint32_t dvoa[16]; -+ -+ /* DCE3 chips */ -+ uint32_t fmt1[18]; -+ uint32_t fmt2[18]; -+ uint32_t dig1[19]; -+ uint32_t dig2[19]; -+ uint32_t hdmi1[57]; -+ uint32_t hdmi2[57]; -+ uint32_t aux_cntl1[14]; -+ uint32_t aux_cntl2[14]; -+ uint32_t aux_cntl3[14]; -+ uint32_t aux_cntl4[14]; -+ uint32_t phy[10]; -+ uint32_t uniphy1[8]; -+ uint32_t uniphy2[8]; - - }; - -@@ -373,100 +387,100 @@ typedef struct { - struct avivo_state avivo; - - /* Common registers */ -- CARD32 ovr_clr; -- CARD32 ovr_wid_left_right; -- CARD32 ovr_wid_top_bottom; -- CARD32 ov0_scale_cntl; -- CARD32 mpp_tb_config; -- CARD32 mpp_gp_config; -- CARD32 subpic_cntl; -- CARD32 viph_control; -- CARD32 i2c_cntl_1; -- CARD32 gen_int_cntl; -- CARD32 cap0_trig_cntl; -- CARD32 cap1_trig_cntl; -- CARD32 bus_cntl; -- -- CARD32 bios_0_scratch; -- CARD32 bios_1_scratch; -- CARD32 bios_2_scratch; -- CARD32 bios_3_scratch; -- CARD32 bios_4_scratch; -- CARD32 bios_5_scratch; -- CARD32 bios_6_scratch; -- CARD32 bios_7_scratch; -- -- CARD32 surface_cntl; -- CARD32 surfaces[8][3]; -- CARD32 mc_agp_location; -- CARD32 mc_agp_location_hi; -- CARD32 mc_fb_location; -- CARD32 display_base_addr; -- CARD32 display2_base_addr; -- CARD32 ov0_base_addr; -+ uint32_t ovr_clr; -+ uint32_t ovr_wid_left_right; -+ uint32_t ovr_wid_top_bottom; -+ uint32_t ov0_scale_cntl; -+ uint32_t mpp_tb_config; -+ uint32_t mpp_gp_config; -+ uint32_t subpic_cntl; -+ uint32_t viph_control; -+ uint32_t i2c_cntl_1; -+ uint32_t gen_int_cntl; -+ uint32_t cap0_trig_cntl; -+ uint32_t cap1_trig_cntl; -+ uint32_t bus_cntl; -+ -+ uint32_t bios_0_scratch; -+ uint32_t bios_1_scratch; -+ uint32_t bios_2_scratch; -+ uint32_t bios_3_scratch; -+ uint32_t bios_4_scratch; -+ uint32_t bios_5_scratch; -+ uint32_t bios_6_scratch; -+ uint32_t bios_7_scratch; -+ -+ uint32_t surface_cntl; -+ uint32_t surfaces[8][3]; -+ uint32_t mc_agp_location; -+ uint32_t mc_agp_location_hi; -+ uint32_t mc_fb_location; -+ uint32_t display_base_addr; -+ uint32_t display2_base_addr; -+ uint32_t ov0_base_addr; - - /* Other registers to save for VT switches */ -- CARD32 dp_datatype; -- CARD32 rbbm_soft_reset; -- CARD32 clock_cntl_index; -- CARD32 amcgpio_en_reg; -- CARD32 amcgpio_mask; -+ uint32_t dp_datatype; -+ uint32_t rbbm_soft_reset; -+ uint32_t clock_cntl_index; -+ uint32_t amcgpio_en_reg; -+ uint32_t amcgpio_mask; - - /* CRTC registers */ -- CARD32 crtc_gen_cntl; -- CARD32 crtc_ext_cntl; -- CARD32 dac_cntl; -- CARD32 crtc_h_total_disp; -- CARD32 crtc_h_sync_strt_wid; -- CARD32 crtc_v_total_disp; -- CARD32 crtc_v_sync_strt_wid; -- CARD32 crtc_offset; -- CARD32 crtc_offset_cntl; -- CARD32 crtc_pitch; -- CARD32 disp_merge_cntl; -- CARD32 grph_buffer_cntl; -- CARD32 crtc_more_cntl; -- CARD32 crtc_tile_x0_y0; -+ uint32_t crtc_gen_cntl; -+ uint32_t crtc_ext_cntl; -+ uint32_t dac_cntl; -+ uint32_t crtc_h_total_disp; -+ uint32_t crtc_h_sync_strt_wid; -+ uint32_t crtc_v_total_disp; -+ uint32_t crtc_v_sync_strt_wid; -+ uint32_t crtc_offset; -+ uint32_t crtc_offset_cntl; -+ uint32_t crtc_pitch; -+ uint32_t disp_merge_cntl; -+ uint32_t grph_buffer_cntl; -+ uint32_t crtc_more_cntl; -+ uint32_t crtc_tile_x0_y0; - - /* CRTC2 registers */ -- CARD32 crtc2_gen_cntl; -- CARD32 dac_macro_cntl; -- CARD32 dac2_cntl; -- CARD32 disp_output_cntl; -- CARD32 disp_tv_out_cntl; -- CARD32 disp_hw_debug; -- CARD32 disp2_merge_cntl; -- CARD32 grph2_buffer_cntl; -- CARD32 crtc2_h_total_disp; -- CARD32 crtc2_h_sync_strt_wid; -- CARD32 crtc2_v_total_disp; -- CARD32 crtc2_v_sync_strt_wid; -- CARD32 crtc2_offset; -- CARD32 crtc2_offset_cntl; -- CARD32 crtc2_pitch; -- CARD32 crtc2_tile_x0_y0; -+ uint32_t crtc2_gen_cntl; -+ uint32_t dac_macro_cntl; -+ uint32_t dac2_cntl; -+ uint32_t disp_output_cntl; -+ uint32_t disp_tv_out_cntl; -+ uint32_t disp_hw_debug; -+ uint32_t disp2_merge_cntl; -+ uint32_t grph2_buffer_cntl; -+ uint32_t crtc2_h_total_disp; -+ uint32_t crtc2_h_sync_strt_wid; -+ uint32_t crtc2_v_total_disp; -+ uint32_t crtc2_v_sync_strt_wid; -+ uint32_t crtc2_offset; -+ uint32_t crtc2_offset_cntl; -+ uint32_t crtc2_pitch; -+ uint32_t crtc2_tile_x0_y0; - - /* Flat panel registers */ -- CARD32 fp_crtc_h_total_disp; -- CARD32 fp_crtc_v_total_disp; -- CARD32 fp_gen_cntl; -- CARD32 fp2_gen_cntl; -- CARD32 fp_h_sync_strt_wid; -- CARD32 fp_h2_sync_strt_wid; -- CARD32 fp_horz_stretch; -- CARD32 fp_horz_vert_active; -- CARD32 fp_panel_cntl; -- CARD32 fp_v_sync_strt_wid; -- CARD32 fp_v2_sync_strt_wid; -- CARD32 fp_vert_stretch; -- CARD32 lvds_gen_cntl; -- CARD32 lvds_pll_cntl; -- CARD32 tmds_pll_cntl; -- CARD32 tmds_transmitter_cntl; -+ uint32_t fp_crtc_h_total_disp; -+ uint32_t fp_crtc_v_total_disp; -+ uint32_t fp_gen_cntl; -+ uint32_t fp2_gen_cntl; -+ uint32_t fp_h_sync_strt_wid; -+ uint32_t fp_h2_sync_strt_wid; -+ uint32_t fp_horz_stretch; -+ uint32_t fp_horz_vert_active; -+ uint32_t fp_panel_cntl; -+ uint32_t fp_v_sync_strt_wid; -+ uint32_t fp_v2_sync_strt_wid; -+ uint32_t fp_vert_stretch; -+ uint32_t lvds_gen_cntl; -+ uint32_t lvds_pll_cntl; -+ uint32_t tmds_pll_cntl; -+ uint32_t tmds_transmitter_cntl; - - /* Computed values for PLL */ -- CARD32 dot_clock_freq; -- CARD32 pll_output_freq; -+ uint32_t dot_clock_freq; -+ uint32_t pll_output_freq; - int feedback_div; - int reference_div; - int post_div; -@@ -474,75 +488,81 @@ typedef struct { - /* PLL registers */ - unsigned ppll_ref_div; - unsigned ppll_div_3; -- CARD32 htotal_cntl; -- CARD32 vclk_ecp_cntl; -+ uint32_t htotal_cntl; -+ uint32_t vclk_ecp_cntl; - - /* Computed values for PLL2 */ -- CARD32 dot_clock_freq_2; -- CARD32 pll_output_freq_2; -+ uint32_t dot_clock_freq_2; -+ uint32_t pll_output_freq_2; - int feedback_div_2; - int reference_div_2; - int post_div_2; - - /* PLL2 registers */ -- CARD32 p2pll_ref_div; -- CARD32 p2pll_div_0; -- CARD32 htotal_cntl2; -- CARD32 pixclks_cntl; -+ uint32_t p2pll_ref_div; -+ uint32_t p2pll_div_0; -+ uint32_t htotal_cntl2; -+ uint32_t pixclks_cntl; - - /* Pallet */ - Bool palette_valid; -- CARD32 palette[256]; -- CARD32 palette2[256]; -+ uint32_t palette[256]; -+ uint32_t palette2[256]; -+ -+ uint32_t disp2_req_cntl1; -+ uint32_t disp2_req_cntl2; -+ uint32_t dmif_mem_cntl1; -+ uint32_t disp1_req_cntl1; -+ -+ uint32_t fp_2nd_gen_cntl; -+ uint32_t fp2_2_gen_cntl; -+ uint32_t tmds2_cntl; -+ uint32_t tmds2_transmitter_cntl; - -- CARD32 rs480_unk_e30; -- CARD32 rs480_unk_e34; -- CARD32 rs480_unk_e38; -- CARD32 rs480_unk_e3c; - - /* TV out registers */ -- CARD32 tv_master_cntl; -- CARD32 tv_htotal; -- CARD32 tv_hsize; -- CARD32 tv_hdisp; -- CARD32 tv_hstart; -- CARD32 tv_vtotal; -- CARD32 tv_vdisp; -- CARD32 tv_timing_cntl; -- CARD32 tv_vscaler_cntl1; -- CARD32 tv_vscaler_cntl2; -- CARD32 tv_sync_size; -- CARD32 tv_vrestart; -- CARD32 tv_hrestart; -- CARD32 tv_frestart; -- CARD32 tv_ftotal; -- CARD32 tv_clock_sel_cntl; -- CARD32 tv_clkout_cntl; -- CARD32 tv_data_delay_a; -- CARD32 tv_data_delay_b; -- CARD32 tv_dac_cntl; -- CARD32 tv_pll_cntl; -- CARD32 tv_pll_cntl1; -- CARD32 tv_pll_fine_cntl; -- CARD32 tv_modulator_cntl1; -- CARD32 tv_modulator_cntl2; -- CARD32 tv_frame_lock_cntl; -- CARD32 tv_pre_dac_mux_cntl; -- CARD32 tv_rgb_cntl; -- CARD32 tv_y_saw_tooth_cntl; -- CARD32 tv_y_rise_cntl; -- CARD32 tv_y_fall_cntl; -- CARD32 tv_uv_adr; -- CARD32 tv_upsamp_and_gain_cntl; -- CARD32 tv_gain_limit_settings; -- CARD32 tv_linear_gain_settings; -- CARD32 tv_crc_cntl; -- CARD32 tv_sync_cntl; -- CARD32 gpiopad_a; -- CARD32 pll_test_cntl; -- -- CARD16 h_code_timing[MAX_H_CODE_TIMING_LEN]; -- CARD16 v_code_timing[MAX_V_CODE_TIMING_LEN]; -+ uint32_t tv_master_cntl; -+ uint32_t tv_htotal; -+ uint32_t tv_hsize; -+ uint32_t tv_hdisp; -+ uint32_t tv_hstart; -+ uint32_t tv_vtotal; -+ uint32_t tv_vdisp; -+ uint32_t tv_timing_cntl; -+ uint32_t tv_vscaler_cntl1; -+ uint32_t tv_vscaler_cntl2; -+ uint32_t tv_sync_size; -+ uint32_t tv_vrestart; -+ uint32_t tv_hrestart; -+ uint32_t tv_frestart; -+ uint32_t tv_ftotal; -+ uint32_t tv_clock_sel_cntl; -+ uint32_t tv_clkout_cntl; -+ uint32_t tv_data_delay_a; -+ uint32_t tv_data_delay_b; -+ uint32_t tv_dac_cntl; -+ uint32_t tv_pll_cntl; -+ uint32_t tv_pll_cntl1; -+ uint32_t tv_pll_fine_cntl; -+ uint32_t tv_modulator_cntl1; -+ uint32_t tv_modulator_cntl2; -+ uint32_t tv_frame_lock_cntl; -+ uint32_t tv_pre_dac_mux_cntl; -+ uint32_t tv_rgb_cntl; -+ uint32_t tv_y_saw_tooth_cntl; -+ uint32_t tv_y_rise_cntl; -+ uint32_t tv_y_fall_cntl; -+ uint32_t tv_uv_adr; -+ uint32_t tv_upsamp_and_gain_cntl; -+ uint32_t tv_gain_limit_settings; -+ uint32_t tv_linear_gain_settings; -+ uint32_t tv_crc_cntl; -+ uint32_t tv_sync_cntl; -+ uint32_t gpiopad_a; -+ uint32_t pll_test_cntl; -+ -+ uint16_t h_code_timing[MAX_H_CODE_TIMING_LEN]; -+ uint16_t v_code_timing[MAX_V_CODE_TIMING_LEN]; - - } RADEONSaveRec, *RADEONSavePtr; - -@@ -571,6 +591,7 @@ typedef struct - RADEONSaveRec ModeReg; /* Current mode */ - RADEONSaveRec SavedReg; /* Original (text) mode */ - -+ void *MMIO; /* Map of MMIO region */ - } RADEONEntRec, *RADEONEntPtr; - - /* radeon_probe.c */ -diff --git a/src/radeon_reg.h b/src/radeon_reg.h -index 046c52b..1d35236 100644 ---- a/src/radeon_reg.h -+++ b/src/radeon_reg.h -@@ -265,6 +265,7 @@ - #define RADEON_BRUSH_Y_X 0x1474 - #define RADEON_BUS_CNTL 0x0030 - # define RADEON_BUS_MASTER_DIS (1 << 6) -+# define RADEON_BUS_BIOS_DIS_ROM (1 << 12) - # define RADEON_BUS_RD_DISCARD_EN (1 << 24) - # define RADEON_BUS_RD_ABORT_EN (1 << 25) - # define RADEON_BUS_MSTR_DISCONNECT_EN (1 << 28) -@@ -886,7 +887,35 @@ - # define RADEON_VERT_STRETCH_LINEREP (0 << 26) - # define RADEON_VERT_STRETCH_BLEND (1 << 26) - # define RADEON_VERT_AUTO_RATIO_EN (1 << 27) --# define RADEON_VERT_STRETCH_RESERVED 0xf1000000 -+# define RADEON_VERT_AUTO_RATIO_INC (1 << 31) -+# define RADEON_VERT_STRETCH_RESERVED 0x71000000 -+#define RS400_FP_2ND_GEN_CNTL 0x0384 -+# define RS400_FP_2ND_ON (1 << 0) -+# define RS400_FP_2ND_BLANK_EN (1 << 1) -+# define RS400_TMDS_2ND_EN (1 << 2) -+# define RS400_PANEL_FORMAT_2ND (1 << 3) -+# define RS400_FP_2ND_EN_TMDS (1 << 7) -+# define RS400_FP_2ND_DETECT_SENSE (1 << 8) -+# define RS400_FP_2ND_SOURCE_SEL_MASK (3 << 10) -+# define RS400_FP_2ND_SOURCE_SEL_CRTC1 (0 << 10) -+# define RS400_FP_2ND_SOURCE_SEL_CRTC2 (1 << 10) -+# define RS400_FP_2ND_SOURCE_SEL_RMX (2 << 10) -+# define RS400_FP_2ND_DETECT_EN (1 << 12) -+# define RS400_HPD_2ND_SEL (1 << 13) -+#define RS400_FP2_2_GEN_CNTL 0x0388 -+# define RS400_FP2_2_BLANK_EN (1 << 1) -+# define RS400_FP2_2_ON (1 << 2) -+# define RS400_FP2_2_PANEL_FORMAT (1 << 3) -+# define RS400_FP2_2_DETECT_SENSE (1 << 8) -+# define RS400_FP2_2_SOURCE_SEL_MASK (3 << 10) -+# define RS400_FP2_2_SOURCE_SEL_CRTC1 (0 << 10) -+# define RS400_FP2_2_SOURCE_SEL_CRTC2 (1 << 10) -+# define RS400_FP2_2_SOURCE_SEL_RMX (2 << 10) -+# define RS400_FP2_2_DVO2_EN (1 << 25) -+#define RS400_TMDS2_CNTL 0x0394 -+#define RS400_TMDS2_TRANSMITTER_CNTL 0x03a4 -+# define RS400_TMDS2_PLLEN (1 << 0) -+# define RS400_TMDS2_PLLRST (1 << 1) - - #define RADEON_GEN_INT_CNTL 0x0040 - #define RADEON_GEN_INT_STATUS 0x0044 -@@ -1003,6 +1032,10 @@ - #define RADEON_OV0_BASE_ADDR 0x43c - #define RADEON_NB_TOM 0x15c - #define R300_MC_INIT_MISC_LAT_TIMER 0x180 -+# define R300_MC_DISP0R_INIT_LAT_SHIFT 8 -+# define R300_MC_DISP0R_INIT_LAT_MASK 0xf -+# define R300_MC_DISP1R_INIT_LAT_SHIFT 12 -+# define R300_MC_DISP1R_INIT_LAT_MASK 0xf - #define RADEON_MCLK_CNTL 0x0012 /* PLL */ - # define RADEON_FORCEON_MCLKA (1 << 16) - # define RADEON_FORCEON_MCLKB (1 << 17) -@@ -1018,10 +1051,12 @@ - # define RADEON_MC_MCLK_DYN_ENABLE (1 << 14) - # define RADEON_IO_MCLK_DYN_ENABLE (1 << 15) - #define RADEON_LCD_GPIO_MASK 0x01a0 -+#define RADEON_GPIOPAD_EN 0x01a0 - #define RADEON_LCD_GPIO_Y_REG 0x01a4 - #define RADEON_MDGPIO_A_REG 0x01ac - #define RADEON_MDGPIO_EN_REG 0x01b0 - #define RADEON_MDGPIO_MASK 0x0198 -+#define RADEON_GPIOPAD_MASK 0x0198 - #define RADEON_GPIOPAD_A 0x019c - #define RADEON_MDGPIO_Y_REG 0x01b4 - #define RADEON_MEM_ADDR_CONFIG 0x0148 -@@ -1038,6 +1073,7 @@ - #define RADEON_MEM_SDRAM_MODE_REG 0x0158 - # define RADEON_SDRAM_MODE_MASK 0xffff0000 - # define RADEON_B3MEM_RESET_MASK 0x6fffffff -+# define RADEON_MEM_CFG_TYPE_DDR (1 << 30) - #define RADEON_MEM_STR_CNTL 0x0150 - # define RADEON_MEM_PWRUP_COMPL_A (1 << 0) - # define RADEON_MEM_PWRUP_COMPL_B (1 << 1) -@@ -1056,6 +1092,9 @@ - #define RADEON_MPLL_CNTL 0x000e /* PLL */ - #define RADEON_MPP_TB_CONFIG 0x01c0 /* ? */ - #define RADEON_MPP_GP_CONFIG 0x01c8 /* ? */ -+#define RADEON_SEPROM_CNTL1 0x01c0 -+# define RADEON_SCK_PRESCALE_SHIFT 24 -+# define RADEON_SCK_PRESCALE_MASK (0xff << 24) - #define R300_MC_IND_INDEX 0x01f8 - # define R300_MC_IND_ADDR_MASK 0x3f - # define R300_MC_IND_WR_EN (1 << 8) -@@ -1423,6 +1462,7 @@ - # define RADEON_RB2D_DC_FLUSH_ALL 0xf - # define RADEON_RB2D_DC_BUSY (1 << 31) - #define RADEON_RB2D_DSTCACHE_MODE 0x3428 -+#define RADEON_DSTCACHE_CTLSTAT 0x1714 - - #define RADEON_RB3D_ZCACHE_MODE 0x3250 - #define RADEON_RB3D_ZCACHE_CTLSTAT 0x3254 -@@ -1620,6 +1660,7 @@ - # define RADEON_VIP_BUSY 0 - # define RADEON_VIP_IDLE 1 - # define RADEON_VIP_RESET 2 -+# define RADEON_VIPH_EN (1 << 21) - #define RADEON_VIPH_DV_LAT 0x0c44 - #define RADEON_VIPH_BM_CHUNK 0x0c48 - #define RADEON_VIPH_DV_INT 0x0c4c -@@ -1634,9 +1675,25 @@ - - #define RADEON_WAIT_UNTIL 0x1720 - # define RADEON_WAIT_CRTC_PFLIP (1 << 0) -+# define RADEON_WAIT_RE_CRTC_VLINE (1 << 1) -+# define RADEON_WAIT_FE_CRTC_VLINE (1 << 2) -+# define RADEON_WAIT_CRTC_VLINE (1 << 3) -+# define RADEON_WAIT_DMA_VID_IDLE (1 << 8) -+# define RADEON_WAIT_DMA_GUI_IDLE (1 << 9) -+# define RADEON_WAIT_CMDFIFO (1 << 10) /* wait for CMDFIFO_ENTRIES */ -+# define RADEON_WAIT_OV0_FLIP (1 << 11) -+# define RADEON_WAIT_AGP_FLUSH (1 << 13) -+# define RADEON_WAIT_2D_IDLE (1 << 14) -+# define RADEON_WAIT_3D_IDLE (1 << 15) - # define RADEON_WAIT_2D_IDLECLEAN (1 << 16) - # define RADEON_WAIT_3D_IDLECLEAN (1 << 17) - # define RADEON_WAIT_HOST_IDLECLEAN (1 << 18) -+# define RADEON_CMDFIFO_ENTRIES_SHIFT 10 -+# define RADEON_CMDFIFO_ENTRIES_MASK 0x7f -+# define RADEON_WAIT_VAP_IDLE (1 << 28) -+# define RADEON_WAIT_BOTH_CRTC_PFLIP (1 << 30) -+# define RADEON_ENG_DISPLAY_SELECT_CRTC0 (0 << 31) -+# define RADEON_ENG_DISPLAY_SELECT_CRTC1 (1 << 31) - - #define RADEON_X_MPLL_REF_FB_DIV 0x000a /* PLL */ - #define RADEON_XCLK_CNTL 0x000d /* PLL */ -@@ -3132,6 +3189,7 @@ - #define RADEON_CP_VC_CNTL_PRIM_TYPE_RECT_LIST 0x00000008 - #define RADEON_CP_VC_CNTL_PRIM_TYPE_3VRT_POINT_LIST 0x00000009 - #define RADEON_CP_VC_CNTL_PRIM_TYPE_3VRT_LINE_LIST 0x0000000a -+#define RADEON_CP_VC_CNTL_PRIM_TYPE_QUAD_LIST 0x0000000d - #define RADEON_CP_VC_CNTL_PRIM_WALK_IND 0x00000010 - #define RADEON_CP_VC_CNTL_PRIM_WALK_LIST 0x00000020 - #define RADEON_CP_VC_CNTL_PRIM_WALK_RING 0x00000030 -@@ -3328,10 +3386,32 @@ - # define RADEON_TVPLL_TEST_DIS (1 << 31) - # define RADEON_TVCLK_SRC_SEL_TVPLL (1 << 30) - --#define RADEON_RS480_UNK_e30 0xe30 --#define RADEON_RS480_UNK_e34 0xe34 --#define RADEON_RS480_UNK_e38 0xe38 --#define RADEON_RS480_UNK_e3c 0xe3c -+#define RS400_DISP2_REQ_CNTL1 0xe30 -+# define RS400_DISP2_START_REQ_LEVEL_SHIFT 0 -+# define RS400_DISP2_START_REQ_LEVEL_MASK 0x3ff -+# define RS400_DISP2_STOP_REQ_LEVEL_SHIFT 12 -+# define RS400_DISP2_STOP_REQ_LEVEL_MASK 0x3ff -+# define RS400_DISP2_ALLOW_FID_LEVEL_SHIFT 22 -+# define RS400_DISP2_ALLOW_FID_LEVEL_MASK 0x3ff -+#define RS400_DISP2_REQ_CNTL2 0xe34 -+# define RS400_DISP2_CRITICAL_POINT_START_SHIFT 12 -+# define RS400_DISP2_CRITICAL_POINT_START_MASK 0x3ff -+# define RS400_DISP2_CRITICAL_POINT_STOP_SHIFT 22 -+# define RS400_DISP2_CRITICAL_POINT_STOP_MASK 0x3ff -+#define RS400_DMIF_MEM_CNTL1 0xe38 -+# define RS400_DISP2_START_ADR_SHIFT 0 -+# define RS400_DISP2_START_ADR_MASK 0x3ff -+# define RS400_DISP1_CRITICAL_POINT_START_SHIFT 12 -+# define RS400_DISP1_CRITICAL_POINT_START_MASK 0x3ff -+# define RS400_DISP1_CRITICAL_POINT_STOP_SHIFT 22 -+# define RS400_DISP1_CRITICAL_POINT_STOP_MASK 0x3ff -+#define RS400_DISP1_REQ_CNTL1 0xe3c -+# define RS400_DISP1_START_REQ_LEVEL_SHIFT 0 -+# define RS400_DISP1_START_REQ_LEVEL_MASK 0x3ff -+# define RS400_DISP1_STOP_REQ_LEVEL_SHIFT 12 -+# define RS400_DISP1_STOP_REQ_LEVEL_MASK 0x3ff -+# define RS400_DISP1_ALLOW_FID_LEVEL_SHIFT 22 -+# define RS400_DISP1_ALLOW_FID_LEVEL_MASK 0x3ff - - #define RS690_MC_INDEX 0x78 - # define RS690_MC_INDEX_MASK 0x1ff -@@ -3342,23 +3422,52 @@ - #define RS690_MC_FB_LOCATION 0x100 - #define RS690_MC_AGP_LOCATION 0x101 - #define RS690_MC_AGP_BASE 0x102 -+#define RS690_MC_AGP_BASE_2 0x103 -+#define RS690_MC_INIT_MISC_LAT_TIMER 0x104 - #define RS690_MC_STATUS 0x90 --#define RS690_MC_STATUS_IDLE (1 << 0) -- --#define AVIVO_MC_INDEX 0x0070 --#define R520_MC_STATUS 0x00 --#define R520_MC_STATUS_IDLE (1<<1) --#define RV515_MC_STATUS 0x08 --#define RV515_MC_STATUS_IDLE (1<<4) --#define AVIVO_MC_DATA 0x0074 -- --#define RV515_MC_FB_LOCATION 0x1 --#define RV515_MC_AGP_LOCATION 0x2 --#define R520_MC_FB_LOCATION 0x4 --#define R520_MC_AGP_LOCATION 0x5 -+#define RS690_MC_STATUS_IDLE (1 << 0) -+ -+#define RS600_MC_INDEX 0x78 -+# define RS600_MC_INDEX_MASK 0xff -+# define RS600_MC_INDEX_WR_EN (1 << 8) -+# define RS600_MC_INDEX_WR_ACK 0xff -+#define RS600_MC_DATA 0x7c -+ -+#define RS600_MC_FB_LOCATION 0xA -+#define RS600_MC_STATUS 0x0 -+#define RS600_MC_STATUS_IDLE (1 << 0) -+ -+#define AVIVO_MC_INDEX 0x0070 -+#define R520_MC_STATUS 0x00 -+# define R520_MC_STATUS_IDLE (1 << 1) -+#define RV515_MC_STATUS 0x08 -+# define RV515_MC_STATUS_IDLE (1 << 4) -+#define RV515_MC_INIT_MISC_LAT_TIMER 0x09 -+#define AVIVO_MC_DATA 0x0074 -+ -+#define RV515_MC_FB_LOCATION 0x1 -+#define RV515_MC_AGP_LOCATION 0x2 -+#define RV515_MC_AGP_BASE 0x3 -+#define RV515_MC_AGP_BASE_2 0x4 -+#define RV515_MC_CNTL 0x5 -+# define RV515_MEM_NUM_CHANNELS_MASK 0x3 -+#define R520_MC_FB_LOCATION 0x4 -+#define R520_MC_AGP_LOCATION 0x5 -+#define R520_MC_AGP_BASE 0x6 -+#define R520_MC_AGP_BASE_2 0x7 -+#define R520_MC_CNTL0 0x8 -+# define R520_MEM_NUM_CHANNELS_MASK (0x3 << 24) -+# define R520_MEM_NUM_CHANNELS_SHIFT 24 -+# define R520_MC_CHANNEL_SIZE (1 << 23) -+ -+#define R600_RAMCFG 0x2408 -+# define R600_CHANSIZE (1 << 7) -+# define R600_CHANSIZE_OVERRIDE (1 << 10) - - #define AVIVO_HDP_FB_LOCATION 0x134 - -+#define AVIVO_VGA_RENDER_CONTROL 0x0300 -+# define AVIVO_VGA_VSTATUS_CNTL_MASK (3 << 16) - #define AVIVO_D1VGA_CONTROL 0x0330 - # define AVIVO_DVGA_CONTROL_MODE_ENABLE (1<<0) - # define AVIVO_DVGA_CONTROL_TIMING_SELECT (1<<8) -@@ -3475,6 +3584,8 @@ - #define AVIVO_D1CUR_SIZE 0x6410 - #define AVIVO_D1CUR_POSITION 0x6414 - #define AVIVO_D1CUR_HOT_SPOT 0x6418 -+#define AVIVO_D1CUR_UPDATE 0x6424 -+# define AVIVO_D1CURSOR_UPDATE_LOCK (1 << 16) - - #define AVIVO_DC_LUT_RW_SELECT 0x6480 - #define AVIVO_DC_LUT_RW_MODE 0x6484 -@@ -3494,8 +3605,20 @@ - #define AVIVO_DC_LUTA_WHITE_OFFSET_GREEN 0x64d4 - #define AVIVO_DC_LUTA_WHITE_OFFSET_RED 0x64d8 - -- --#define AVIVO_D1MODE_DESKTOP_HEIGHT 0x652C -+#define AVIVO_DC_LB_MEMORY_SPLIT 0x6520 -+# define AVIVO_DC_LB_MEMORY_SPLIT_MASK 0x3 -+# define AVIVO_DC_LB_MEMORY_SPLIT_SHIFT 0 -+# define AVIVO_DC_LB_MEMORY_SPLIT_D1HALF_D2HALF 0 -+# define AVIVO_DC_LB_MEMORY_SPLIT_D1_3Q_D2_1Q 1 -+# define AVIVO_DC_LB_MEMORY_SPLIT_D1_ONLY 2 -+# define AVIVO_DC_LB_MEMORY_SPLIT_D1_1Q_D2_3Q 3 -+# define AVIVO_DC_LB_MEMORY_SPLIT_SHIFT_MODE (1 << 2) -+# define AVIVO_DC_LB_DISP1_END_ADR_SHIFT 4 -+# define AVIVO_DC_LB_DISP1_END_ADR_MASK 0x7ff -+ -+#define AVIVO_D1MODE_DATA_FORMAT 0x6528 -+# define AVIVO_D1MODE_INTERLEAVE_EN (1 << 0) -+#define AVIVO_D1MODE_DESKTOP_HEIGHT 0x652c - #define AVIVO_D1MODE_VIEWPORT_START 0x6580 - #define AVIVO_D1MODE_VIEWPORT_SIZE 0x6584 - #define AVIVO_D1MODE_EXT_OVERSCAN_LEFT_RIGHT 0x6588 -@@ -3547,6 +3670,8 @@ - #define AVIVO_D2CUR_SIZE 0x6c10 - #define AVIVO_D2CUR_POSITION 0x6c14 - -+#define AVIVO_D2MODE_DATA_FORMAT 0x6d28 -+#define AVIVO_D2MODE_DESKTOP_HEIGHT 0x6d2c - #define AVIVO_D2MODE_VIEWPORT_START 0x6d80 - #define AVIVO_D2MODE_VIEWPORT_SIZE 0x6d84 - #define AVIVO_D2MODE_EXT_OVERSCAN_LEFT_RIGHT 0x6d88 -@@ -3554,6 +3679,9 @@ - - #define AVIVO_D2SCL_SCALER_ENABLE 0x6d90 - #define AVIVO_D2SCL_SCALER_TAP_CONTROL 0x6d94 -+#define AVIVO_D2SCL_UPDATE 0x6dcc -+ -+#define AVIVO_DDIA_BIT_DEPTH_CONTROL 0x7214 - - #define AVIVO_DACA_ENABLE 0x7800 - # define AVIVO_DAC_ENABLE (1 << 0) -@@ -3745,6 +3873,8 @@ - # define AVIVO_LVDS_BACKLIGHT_LEVEL_MASK 0x0000ff00 - # define AVIVO_LVDS_BACKLIGHT_LEVEL_SHIFT 8 - -+#define AVIVO_DVOA_BIT_DEPTH_CONTROL 0x7988 -+ - #define AVIVO_GPIO_0 0x7e30 - #define AVIVO_GPIO_1 0x7e40 - #define AVIVO_GPIO_2 0x7e50 -@@ -3793,6 +3923,15 @@ - # define AVIVO_I2C_EN (1 << 0) - # define AVIVO_I2C_RESET (1 << 8) - -+#define R600_GENERAL_PWRMGT 0x618 -+# define R600_OPEN_DRAIN_PADS (1 << 11) -+ -+#define R600_LOWER_GPIO_ENABLE 0x710 -+#define R600_CTXSW_VID_LOWER_GPIO_CNTL 0x718 -+#define R600_HIGH_VID_LOWER_GPIO_CNTL 0x71c -+#define R600_MEDIUM_VID_LOWER_GPIO_CNTL 0x720 -+#define R600_LOW_VID_LOWER_GPIO_CNTL 0x724 -+ - #define R600_MC_VM_FB_LOCATION 0x2180 - #define R600_MC_VM_AGP_TOP 0x2184 - #define R600_MC_VM_AGP_BOT 0x2188 -@@ -3801,6 +3940,8 @@ - #define R600_MC_VM_SYSTEM_APERTURE_HIGH_ADDR 0x2194 - #define R600_MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR 0x2198 - -+#define R700_MC_VM_FB_LOCATION 0x2024 -+ - #define R600_HDP_NONSURFACE_BASE 0x2c04 - - #define R600_BUS_CNTL 0x5420 -@@ -3809,6 +3950,11 @@ - #define R600_CONFIG_F0_BASE 0x542C - #define R600_CONFIG_APER_SIZE 0x5430 - -+#define R600_ROM_CNTL 0x1600 -+# define R600_SCK_OVERWRITE (1 << 1) -+# define R600_SCK_PRESCALE_CRYSTAL_CLK_SHIFT 28 -+# define R600_SCK_PRESCALE_CRYSTAL_CLK_MASK (0xf << 28) -+ - #define R600_BIOS_0_SCRATCH 0x1724 - #define R600_BIOS_1_SCRATCH 0x1728 - #define R600_BIOS_2_SCRATCH 0x172c -@@ -3832,6 +3978,7 @@ - #define R300_GB_SELECT 0x401c - #define R300_GB_ENABLE 0x4008 - #define R300_GB_AA_CONFIG 0x4020 -+#define R400_GB_PIPE_SELECT 0x402c - #define R300_GB_MSPOS0 0x4010 - # define R300_MS_X0_SHIFT 0 - # define R300_MS_Y0_SHIFT 4 -@@ -3850,6 +3997,10 @@ - # define R300_MS_Y5_SHIFT 20 - # define R300_MSBD1_SHIFT 24 - -+#define R300_GA_ENHANCE 0x4274 -+# define R300_GA_DEADLOCK_CNTL (1 << 0) -+# define R300_GA_FASTSYNC_CNTL (1 << 1) -+ - #define R300_GA_POLY_MODE 0x4288 - # define R300_FRONT_PTYPE_POINT (0 << 4) - # define R300_FRONT_PTYPE_LINE (1 << 4) -@@ -3889,6 +4040,8 @@ - # define R300_ALPHA3_SHADING_GOURAUD (2 << 14) - #define R300_GA_OFFSET 0x4290 - -+#define R500_SU_REG_DEST 0x42c8 -+ - #define R300_VAP_CNTL_STATUS 0x2140 - # define R300_PVS_BYPASS (1 << 8) - #define R300_VAP_PVS_STATE_FLUSH_REG 0x2284 -@@ -3899,6 +4052,7 @@ - # define R300_VF_MAX_VTX_NUM_SHIFT 18 - # define R300_GL_CLIP_SPACE_DEF (0 << 22) - # define R300_DX_CLIP_SPACE_DEF (1 << 22) -+# define R500_TCL_STATE_OPTIMIZATION (1 << 23) - #define R300_VAP_VTE_CNTL 0x20B0 - # define R300_VPORT_X_SCALE_ENA (1 << 0) - # define R300_VPORT_X_OFFSET_ENA (1 << 1) -@@ -3909,6 +4063,7 @@ - # define R300_VTX_XY_FMT (1 << 8) - # define R300_VTX_Z_FMT (1 << 9) - # define R300_VTX_W0_FMT (1 << 10) -+#define R300_VAP_VTX_STATE_CNTL 0x2180 - #define R300_VAP_PSC_SGN_NORM_CNTL 0x21DC - #define R300_VAP_PROG_STREAM_CNTL_0 0x2150 - # define R300_DATA_TYPE_0_SHIFT 0 -@@ -3986,6 +4141,123 @@ - # define R300_PVS_LAST_VTX_SRC_INST_SHIFT 0 - #define R300_VAP_PVS_VECTOR_INDX_REG 0x2200 - #define R300_VAP_PVS_VECTOR_DATA_REG 0x2204 -+/* PVS instructions */ -+/* Opcode and dst instruction */ -+#define R300_PVS_DST_OPCODE(x) (x << 0) -+/* Vector ops */ -+# define R300_VECTOR_NO_OP 0 -+# define R300_VE_DOT_PRODUCT 1 -+# define R300_VE_MULTIPLY 2 -+# define R300_VE_ADD 3 -+# define R300_VE_MULTIPLY_ADD 4 -+# define R300_VE_DISTANCE_VECTOR 5 -+# define R300_VE_FRACTION 6 -+# define R300_VE_MAXIMUM 7 -+# define R300_VE_MINIMUM 8 -+# define R300_VE_SET_GREATER_THAN_EQUAL 9 -+# define R300_VE_SET_LESS_THAN 10 -+# define R300_VE_MULTIPLYX2_ADD 11 -+# define R300_VE_MULTIPLY_CLAMP 12 -+# define R300_VE_FLT2FIX_DX 13 -+# define R300_VE_FLT2FIX_DX_RND 14 -+/* R500 additions */ -+# define R500_VE_PRED_SET_EQ_PUSH 15 -+# define R500_VE_PRED_SET_GT_PUSH 16 -+# define R500_VE_PRED_SET_GTE_PUSH 17 -+# define R500_VE_PRED_SET_NEQ_PUSH 18 -+# define R500_VE_COND_WRITE_EQ 19 -+# define R500_VE_COND_WRITE_GT 20 -+# define R500_VE_COND_WRITE_GTE 21 -+# define R500_VE_COND_WRITE_NEQ 22 -+# define R500_VE_COND_MUX_EQ 23 -+# define R500_VE_COND_MUX_GT 24 -+# define R500_VE_COND_MUX_GTE 25 -+# define R500_VE_SET_GREATER_THAN 26 -+# define R500_VE_SET_EQUAL 27 -+# define R500_VE_SET_NOT_EQUAL 28 -+/* Math ops */ -+# define R300_MATH_NO_OP 0 -+# define R300_ME_EXP_BASE2_DX 1 -+# define R300_ME_LOG_BASE2_DX 2 -+# define R300_ME_EXP_BASEE_FF 3 -+# define R300_ME_LIGHT_COEFF_DX 4 -+# define R300_ME_POWER_FUNC_FF 5 -+# define R300_ME_RECIP_DX 6 -+# define R300_ME_RECIP_FF 7 -+# define R300_ME_RECIP_SQRT_DX 8 -+# define R300_ME_RECIP_SQRT_FF 9 -+# define R300_ME_MULTIPLY 10 -+# define R300_ME_EXP_BASE2_FULL_DX 11 -+# define R300_ME_LOG_BASE2_FULL_DX 12 -+# define R300_ME_POWER_FUNC_FF_CLAMP_B 13 -+# define R300_ME_POWER_FUNC_FF_CLAMP_B1 14 -+# define R300_ME_POWER_FUNC_FF_CLAMP_01 15 -+# define R300_ME_SIN 16 -+# define R300_ME_COS 17 -+/* R500 additions */ -+# define R500_ME_LOG_BASE2_IEEE 18 -+# define R500_ME_RECIP_IEEE 19 -+# define R500_ME_RECIP_SQRT_IEEE 20 -+# define R500_ME_PRED_SET_EQ 21 -+# define R500_ME_PRED_SET_GT 22 -+# define R500_ME_PRED_SET_GTE 23 -+# define R500_ME_PRED_SET_NEQ 24 -+# define R500_ME_PRED_SET_CLR 25 -+# define R500_ME_PRED_SET_INV 26 -+# define R500_ME_PRED_SET_POP 27 -+# define R500_ME_PRED_SET_RESTORE 28 -+/* macro */ -+# define R300_PVS_MACRO_OP_2CLK_MADD 0 -+# define R300_PVS_MACRO_OP_2CLK_M2X_ADD 1 -+#define R300_PVS_DST_MATH_INST (1 << 6) -+#define R300_PVS_DST_MACRO_INST (1 << 7) -+#define R300_PVS_DST_REG_TYPE(x) (x << 8) -+# define R300_PVS_DST_REG_TEMPORARY 0 -+# define R300_PVS_DST_REG_A0 1 -+# define R300_PVS_DST_REG_OUT 2 -+# define R500_PVS_DST_REG_OUT_REPL_X 3 -+# define R300_PVS_DST_REG_ALT_TEMPORARY 4 -+# define R300_PVS_DST_REG_INPUT 5 -+#define R300_PVS_DST_ADDR_MODE_1 (1 << 12) -+#define R300_PVS_DST_OFFSET(x) (x << 13) -+#define R300_PVS_DST_WE_X (1 << 20) -+#define R300_PVS_DST_WE_Y (1 << 21) -+#define R300_PVS_DST_WE_Z (1 << 22) -+#define R300_PVS_DST_WE_W (1 << 23) -+#define R300_PVS_DST_VE_SAT (1 << 24) -+#define R300_PVS_DST_ME_SAT (1 << 25) -+#define R300_PVS_DST_PRED_ENABLE (1 << 26) -+#define R300_PVS_DST_PRED_SENSE (1 << 27) -+#define R300_PVS_DST_DUAL_MATH_OP (1 << 28) -+#define R300_PVS_DST_ADDR_SEL(x) (x << 29) -+#define R300_PVS_DST_ADDR_MODE_0 (1 << 31) -+/* src operand instruction */ -+#define R300_PVS_SRC_REG_TYPE(x) (x << 0) -+# define R300_PVS_SRC_REG_TEMPORARY 0 -+# define R300_PVS_SRC_REG_INPUT 1 -+# define R300_PVS_SRC_REG_CONSTANT 2 -+# define R300_PVS_SRC_REG_ALT_TEMPORARY 3 -+#define R300_SPARE_0 (1 << 2) -+#define R300_PVS_SRC_ABS_XYZW (1 << 3) -+#define R300_PVS_SRC_ADDR_MODE_0 (1 << 4) -+#define R300_PVS_SRC_OFFSET(x) (x << 5) -+#define R300_PVS_SRC_SWIZZLE_X(x) (x << 13) -+#define R300_PVS_SRC_SWIZZLE_Y(x) (x << 16) -+#define R300_PVS_SRC_SWIZZLE_Z(x) (x << 19) -+#define R300_PVS_SRC_SWIZZLE_W(x) (x << 22) -+# define R300_PVS_SRC_SELECT_X 0 -+# define R300_PVS_SRC_SELECT_Y 1 -+# define R300_PVS_SRC_SELECT_Z 2 -+# define R300_PVS_SRC_SELECT_W 3 -+# define R300_PVS_SRC_SELECT_FORCE_0 4 -+# define R300_PVS_SRC_SELECT_FORCE_1 5 -+#define R300_PVS_SRC_NEG_X (1 << 25) -+#define R300_PVS_SRC_NEG_Y (1 << 26) -+#define R300_PVS_SRC_NEG_Z (1 << 27) -+#define R300_PVS_SRC_NEG_W (1 << 28) -+#define R300_PVS_SRC_ADDR_SEL(x) (x << 29) -+#define R300_PVS_SRC_ADDR_MODE_1 (1 << 31) -+ - #define R300_VAP_PVS_FLOW_CNTL_OPC 0x22DC - #define R300_VAP_OUT_VTX_FMT_0 0x2090 - # define R300_VTX_POS_PRESENT (1 << 0) -@@ -4019,6 +4291,9 @@ - # define R300_CLIP_DISABLE (1 << 16) - # define R300_UCP_CULL_ONLY_ENA (1 << 17) - # define R300_BOUNDARY_EDGE_FLAG_ENA (1 << 18) -+#define R300_VAP_PVS_STATE_FLUSH_REG 0x2284 -+ -+#define R500_VAP_INDEX_OFFSET 0x208c - - #define R300_SU_TEX_WRAP 0x42a0 - #define R300_SU_POLY_OFFSET_ENABLE 0x42b4 -@@ -4036,6 +4311,7 @@ - # define R300_RS_COUNT_HIRES_EN (1 << 18) - - #define R300_RS_IP_0 0x4310 -+#define R300_RS_IP_1 0x4314 - # define R300_RS_TEX_PTR(x) (x << 0) - # define R300_RS_COL_PTR(x) (x << 6) - # define R300_RS_COL_FMT(x) (x << 9) -@@ -4063,7 +4339,10 @@ - # define R300_RS_W_EN (1 << 4) - # define R300_TX_OFFSET_RS(x) (x << 5) - #define R300_RS_INST_0 0x4330 -+#define R300_RS_INST_1 0x4334 -+# define R300_INST_TEX_ID(x) (x << 0) - # define R300_RS_INST_TEX_CN_WRITE (1 << 3) -+# define R300_INST_TEX_ADDR(x) (x << 6) - - #define R300_TX_INVALTAGS 0x4100 - #define R300_TX_FILTER0_0 0x4400 -@@ -4082,6 +4361,7 @@ - # define R300_TX_MIN_FILTER_NEAREST (1 << 11) - # define R300_TX_MAG_FILTER_LINEAR (2 << 9) - # define R300_TX_MIN_FILTER_LINEAR (2 << 11) -+# define R300_TX_ID_SHIFT 28 - #define R300_TX_FILTER1_0 0x4440 - #define R300_TX_FORMAT0_0 0x4480 - # define R300_TXWIDTH_SHIFT 0 -@@ -4164,11 +4444,16 @@ - # define R300_TX_FORMAT_SWAP_YUV (1 << 24) - - #define R300_TX_FORMAT2_0 0x4500 -+# define R500_TXWIDTH_11 (1 << 15) -+# define R500_TXHEIGHT_11 (1 << 16) -+ - #define R300_TX_OFFSET_0 0x4540 - # define R300_ENDIAN_SWAP_16_BIT (1 << 0) - # define R300_ENDIAN_SWAP_32_BIT (2 << 0) - # define R300_ENDIAN_SWAP_HALF_DWORD (3 << 0) --# define R300_MACRO_TILE (1 << 2); -+# define R300_MACRO_TILE (1 << 2) -+ -+#define R300_TX_BORDER_COLOR_0 0x45c0 - - #define R300_TX_ENABLE 0x4104 - # define R300_TEX_0_ENABLE (1 << 0) -@@ -4189,7 +4474,7 @@ - # define R300_OUT_FMT_C2_16_MPEG (7 << 0) - # define R300_OUT_FMT_C2_4 (8 << 0) - # define R300_OUT_FMT_C_3_3_2 (9 << 0) --# define R300_OUT_FMT_C_6_5_6 (10 << 0) -+# define R300_OUT_FMT_C_5_6_5 (10 << 0) - # define R300_OUT_FMT_C_11_11_10 (11 << 0) - # define R300_OUT_FMT_C_10_11_11 (12 << 0) - # define R300_OUT_FMT_C_2_10_10_10 (13 << 0) -@@ -4227,28 +4512,223 @@ - # define R300_TEX_CODE_OFFSET(x) (x << 13) - # define R300_TEX_CODE_SIZE(x) (x << 18) - #define R300_US_CODE_ADDR_0 0x4610 -+# define R300_ALU_START(x) (x << 0) -+# define R300_ALU_SIZE(x) (x << 6) -+# define R300_TEX_START(x) (x << 12) -+# define R300_TEX_SIZE(x) (x << 17) -+# define R300_RGBA_OUT (1 << 22) -+# define R300_W_OUT (1 << 23) - #define R300_US_CODE_ADDR_1 0x4614 - #define R300_US_CODE_ADDR_2 0x4618 - #define R300_US_CODE_ADDR_3 0x461c - #define R300_US_TEX_INST_0 0x4620 -+#define R300_US_TEX_INST_1 0x4624 -+#define R300_US_TEX_INST_2 0x4628 -+# define R300_TEX_SRC_ADDR(x) (x << 0) -+# define R300_TEX_DST_ADDR(x) (x << 6) -+# define R300_TEX_ID(x) (x << 11) -+# define R300_TEX_INST(x) (x << 15) -+# define R300_TEX_INST_NOP 0 -+# define R300_TEX_INST_LD 1 -+# define R300_TEX_INST_TEXKILL 2 -+# define R300_TEX_INST_PROJ 3 -+# define R300_TEX_INST_LODBIAS 4 - #define R300_US_ALU_RGB_ADDR_0 0x46c0 -+#define R300_US_ALU_RGB_ADDR_1 0x46c4 -+#define R300_US_ALU_RGB_ADDR_2 0x46c8 -+/* for ADDR0-2, values 0-31 specify a location in the pixel stack, -+ values 32-63 specify a constant */ -+# define R300_ALU_RGB_ADDR0(x) (x << 0) -+# define R300_ALU_RGB_ADDR1(x) (x << 6) -+# define R300_ALU_RGB_ADDR2(x) (x << 12) -+/* ADDRD - where on the pixel stack the result of this instruction -+ will be written */ -+# define R300_ALU_RGB_ADDRD(x) (x << 18) -+# define R300_ALU_RGB_WMASK(x) (x << 23) -+# define R300_ALU_RGB_OMASK(x) (x << 26) -+# define R300_ALU_RGB_MASK_NONE 0 -+# define R300_ALU_RGB_MASK_R 1 -+# define R300_ALU_RGB_MASK_G 2 -+# define R300_ALU_RGB_MASK_B 4 -+# define R300_ALU_RGB_TARGET_A (0 << 29) -+# define R300_ALU_RGB_TARGET_B (1 << 29) -+# define R300_ALU_RGB_TARGET_C (2 << 29) -+# define R300_ALU_RGB_TARGET_D (3 << 29) - #define R300_US_ALU_RGB_INST_0 0x48c0 -+#define R300_US_ALU_RGB_INST_1 0x48c4 -+#define R300_US_ALU_RGB_INST_2 0x48c8 -+# define R300_ALU_RGB_SEL_A(x) (x << 0) -+# define R300_ALU_RGB_SRC0_RGB 0 -+# define R300_ALU_RGB_SRC0_RRR 1 -+# define R300_ALU_RGB_SRC0_GGG 2 -+# define R300_ALU_RGB_SRC0_BBB 3 -+# define R300_ALU_RGB_SRC1_RGB 4 -+# define R300_ALU_RGB_SRC1_RRR 5 -+# define R300_ALU_RGB_SRC1_GGG 6 -+# define R300_ALU_RGB_SRC1_BBB 7 -+# define R300_ALU_RGB_SRC2_RGB 8 -+# define R300_ALU_RGB_SRC2_RRR 9 -+# define R300_ALU_RGB_SRC2_GGG 10 -+# define R300_ALU_RGB_SRC2_BBB 11 -+# define R300_ALU_RGB_SRC0_AAA 12 -+# define R300_ALU_RGB_SRC1_AAA 13 -+# define R300_ALU_RGB_SRC2_AAA 14 -+# define R300_ALU_RGB_SRCP_RGB 15 -+# define R300_ALU_RGB_SRCP_RRR 16 -+# define R300_ALU_RGB_SRCP_GGG 17 -+# define R300_ALU_RGB_SRCP_BBB 18 -+# define R300_ALU_RGB_SRCP_AAA 19 -+# define R300_ALU_RGB_0_0 20 -+# define R300_ALU_RGB_1_0 21 -+# define R300_ALU_RGB_0_5 22 -+# define R300_ALU_RGB_SRC0_GBR 23 -+# define R300_ALU_RGB_SRC1_GBR 24 -+# define R300_ALU_RGB_SRC2_GBR 25 -+# define R300_ALU_RGB_SRC0_BRG 26 -+# define R300_ALU_RGB_SRC1_BRG 27 -+# define R300_ALU_RGB_SRC2_BRG 28 -+# define R300_ALU_RGB_SRC0_ABG 29 -+# define R300_ALU_RGB_SRC1_ABG 30 -+# define R300_ALU_RGB_SRC2_ABG 31 -+# define R300_ALU_RGB_MOD_A(x) (x << 5) -+# define R300_ALU_RGB_MOD_NOP 0 -+# define R300_ALU_RGB_MOD_NEG 1 -+# define R300_ALU_RGB_MOD_ABS 2 -+# define R300_ALU_RGB_MOD_NAB 3 -+# define R300_ALU_RGB_SEL_B(x) (x << 7) -+# define R300_ALU_RGB_MOD_B(x) (x << 12) -+# define R300_ALU_RGB_SEL_C(x) (x << 14) -+# define R300_ALU_RGB_MOD_C(x) (x << 19) -+# define R300_ALU_RGB_SRCP_OP(x) (x << 21) -+# define R300_ALU_RGB_SRCP_OP_1_MINUS_2RGB0 0 -+# define R300_ALU_RGB_SRCP_OP_RGB1_MINUS_RGB0 1 -+# define R300_ALU_RGB_SRCP_OP_RGB1_PLUS_RGB0 2 -+# define R300_ALU_RGB_SRCP_OP_1_MINUS_RGB0 3 -+# define R300_ALU_RGB_OP(x) (x << 23) -+# define R300_ALU_RGB_OP_MAD 0 -+# define R300_ALU_RGB_OP_DP3 1 -+# define R300_ALU_RGB_OP_DP4 2 -+# define R300_ALU_RGB_OP_D2A 3 -+# define R300_ALU_RGB_OP_MIN 4 -+# define R300_ALU_RGB_OP_MAX 5 -+# define R300_ALU_RGB_OP_CND 7 -+# define R300_ALU_RGB_OP_CMP 8 -+# define R300_ALU_RGB_OP_FRC 9 -+# define R300_ALU_RGB_OP_SOP 10 -+# define R300_ALU_RGB_OMOD(x) (x << 27) -+# define R300_ALU_RGB_OMOD_NONE 0 -+# define R300_ALU_RGB_OMOD_MUL_2 1 -+# define R300_ALU_RGB_OMOD_MUL_4 2 -+# define R300_ALU_RGB_OMOD_MUL_8 3 -+# define R300_ALU_RGB_OMOD_DIV_2 4 -+# define R300_ALU_RGB_OMOD_DIV_4 5 -+# define R300_ALU_RGB_OMOD_DIV_8 6 -+# define R300_ALU_RGB_CLAMP (1 << 30) -+# define R300_ALU_RGB_INSERT_NOP (1 << 31) - #define R300_US_ALU_ALPHA_ADDR_0 0x47c0 -+#define R300_US_ALU_ALPHA_ADDR_1 0x47c4 -+#define R300_US_ALU_ALPHA_ADDR_2 0x47c8 -+/* for ADDR0-2, values 0-31 specify a location in the pixel stack, -+ values 32-63 specify a constant */ -+# define R300_ALU_ALPHA_ADDR0(x) (x << 0) -+# define R300_ALU_ALPHA_ADDR1(x) (x << 6) -+# define R300_ALU_ALPHA_ADDR2(x) (x << 12) -+/* ADDRD - where on the pixel stack the result of this instruction -+ will be written */ -+# define R300_ALU_ALPHA_ADDRD(x) (x << 18) -+# define R300_ALU_ALPHA_WMASK(x) (x << 23) -+# define R300_ALU_ALPHA_OMASK(x) (x << 24) -+# define R300_ALU_ALPHA_OMASK_W(x) (x << 27) -+# define R300_ALU_ALPHA_MASK_NONE 0 -+# define R300_ALU_ALPHA_MASK_A 1 -+# define R300_ALU_ALPHA_TARGET_A (0 << 25) -+# define R300_ALU_ALPHA_TARGET_B (1 << 25) -+# define R300_ALU_ALPHA_TARGET_C (2 << 25) -+# define R300_ALU_ALPHA_TARGET_D (3 << 25) - #define R300_US_ALU_ALPHA_INST_0 0x49c0 -+#define R300_US_ALU_ALPHA_INST_1 0x49c4 -+#define R300_US_ALU_ALPHA_INST_2 0x49c8 -+# define R300_ALU_ALPHA_SEL_A(x) (x << 0) -+# define R300_ALU_ALPHA_SRC0_R 0 -+# define R300_ALU_ALPHA_SRC0_G 1 -+# define R300_ALU_ALPHA_SRC0_B 2 -+# define R300_ALU_ALPHA_SRC1_R 3 -+# define R300_ALU_ALPHA_SRC1_G 4 -+# define R300_ALU_ALPHA_SRC1_B 5 -+# define R300_ALU_ALPHA_SRC2_R 6 -+# define R300_ALU_ALPHA_SRC2_G 7 -+# define R300_ALU_ALPHA_SRC2_B 8 -+# define R300_ALU_ALPHA_SRC0_A 9 -+# define R300_ALU_ALPHA_SRC1_A 10 -+# define R300_ALU_ALPHA_SRC2_A 11 -+# define R300_ALU_ALPHA_SRCP_R 12 -+# define R300_ALU_ALPHA_SRCP_G 13 -+# define R300_ALU_ALPHA_SRCP_B 14 -+# define R300_ALU_ALPHA_SRCP_A 15 -+# define R300_ALU_ALPHA_0_0 16 -+# define R300_ALU_ALPHA_1_0 17 -+# define R300_ALU_ALPHA_0_5 18 -+# define R300_ALU_ALPHA_MOD_A(x) (x << 5) -+# define R300_ALU_ALPHA_MOD_NOP 0 -+# define R300_ALU_ALPHA_MOD_NEG 1 -+# define R300_ALU_ALPHA_MOD_ABS 2 -+# define R300_ALU_ALPHA_MOD_NAB 3 -+# define R300_ALU_ALPHA_SEL_B(x) (x << 7) -+# define R300_ALU_ALPHA_MOD_B(x) (x << 12) -+# define R300_ALU_ALPHA_SEL_C(x) (x << 14) -+# define R300_ALU_ALPHA_MOD_C(x) (x << 19) -+# define R300_ALU_ALPHA_SRCP_OP(x) (x << 21) -+# define R300_ALU_ALPHA_SRCP_OP_1_MINUS_2RGB0 0 -+# define R300_ALU_ALPHA_SRCP_OP_RGB1_MINUS_RGB0 1 -+# define R300_ALU_ALPHA_SRCP_OP_RGB1_PLUS_RGB0 2 -+# define R300_ALU_ALPHA_SRCP_OP_1_MINUS_RGB0 3 -+# define R300_ALU_ALPHA_OP(x) (x << 23) -+# define R300_ALU_ALPHA_OP_MAD 0 -+# define R300_ALU_ALPHA_OP_DP 1 -+# define R300_ALU_ALPHA_OP_MIN 2 -+# define R300_ALU_ALPHA_OP_MAX 3 -+# define R300_ALU_ALPHA_OP_CND 5 -+# define R300_ALU_ALPHA_OP_CMP 6 -+# define R300_ALU_ALPHA_OP_FRC 7 -+# define R300_ALU_ALPHA_OP_EX2 8 -+# define R300_ALU_ALPHA_OP_LN2 9 -+# define R300_ALU_ALPHA_OP_RCP 10 -+# define R300_ALU_ALPHA_OP_RSQ 11 -+# define R300_ALU_ALPHA_OMOD(x) (x << 27) -+# define R300_ALU_ALPHA_OMOD_NONE 0 -+# define R300_ALU_ALPHA_OMOD_MUL_2 1 -+# define R300_ALU_ALPHA_OMOD_MUL_4 2 -+# define R300_ALU_ALPHA_OMOD_MUL_8 3 -+# define R300_ALU_ALPHA_OMOD_DIV_2 4 -+# define R300_ALU_ALPHA_OMOD_DIV_4 5 -+# define R300_ALU_ALPHA_OMOD_DIV_8 6 -+# define R300_ALU_ALPHA_CLAMP (1 << 30) - - #define R300_FG_DEPTH_SRC 0x4bd8 - #define R300_FG_FOG_BLEND 0x4bc0 - #define R300_FG_ALPHA_FUNC 0x4bd4 - -+#define R300_DST_PIPE_CONFIG 0x170c -+# define R300_PIPE_AUTO_CONFIG (1 << 31) -+#define R300_RB2D_DSTCACHE_MODE 0x3428 -+#define R300_RB2D_DSTCACHE_MODE 0x3428 -+# define R300_DC_AUTOFLUSH_ENABLE (1 << 8) -+# define R300_DC_DC_DISABLE_IGNORE_PE (1 << 17) -+#define R300_RB2D_DSTCACHE_CTLSTAT 0x342c /* use DSTCACHE_CTLSTAT instead */ -+#define R300_DSTCACHE_CTLSTAT 0x1714 -+# define R300_DC_FLUSH_2D (1 << 0) -+# define R300_DC_FREE_2D (1 << 2) -+# define R300_RB2D_DC_FLUSH_ALL (R300_DC_FLUSH_2D | R300_DC_FREE_2D) -+# define R300_RB2D_DC_BUSY (1 << 31) - #define R300_RB3D_DSTCACHE_CTLSTAT 0x4e4c - # define R300_DC_FLUSH_3D (2 << 0) - # define R300_DC_FREE_3D (2 << 2) -+# define R300_RB3D_DC_FLUSH_ALL (R300_DC_FLUSH_3D | R300_DC_FREE_3D) -+# define R300_DC_FINISH_3D (1 << 4) - #define R300_RB3D_ZCACHE_CTLSTAT 0x4f18 - # define R300_ZC_FLUSH (1 << 0) - # define R300_ZC_FREE (1 << 1) --#define R300_WAIT_UNTIL 0x1720 --# define R300_WAIT_2D_IDLECLEAN (1 << 16) --# define R300_WAIT_3D_IDLECLEAN (1 << 17) -+# define R300_ZC_FLUSH_ALL 0x3 - #define R300_RB3D_ZSTENCILCNTL 0x4f04 - #define R300_RB3D_ZCACHE_CTLSTAT 0x4f18 - #define R300_RB3D_BW_CNTL 0x4f1c -@@ -4256,6 +4736,9 @@ - #define R300_RB3D_ZTOP 0x4f14 - #define R300_RB3D_ROPCNTL 0x4e18 - #define R300_RB3D_BLENDCNTL 0x4e04 -+# define R300_ALPHA_BLEND_ENABLE (1 << 0) -+# define R300_SEPARATE_ALPHA_ENABLE (1 << 1) -+# define R300_READ_ENABLE (1 << 2) - #define R300_RB3D_ABLENDCNTL 0x4e08 - #define R300_RB3D_DSTCACHE_CTLSTAT 0x4e4c - #define R300_RB3D_COLOROFFSET0 0x4e28 -@@ -4387,7 +4870,7 @@ - # define R500_ALPHA_SRCP_OP_1_MINUS_2A0 (0 << 30) - # define R500_ALPHA_SRCP_OP_A1_MINUS_A0 (1 << 30) - # define R500_ALPHA_SRCP_OP_A1_PLUS_A0 (2 << 30) --# define R500_ALPHA_SRCP_OP_1_PLUS_A0 (3 << 30) -+# define R500_ALPHA_SRCP_OP_1_MINUS_A0 (3 << 30) - #define R500_US_ALU_RGBA_INST_0 0xb000 - # define R500_ALU_RGBA_OP_MAD (0 << 0) - # define R500_ALU_RGBA_OP_DP3 (1 << 0) -@@ -4540,7 +5023,7 @@ - # define R500_RGB_SRCP_OP_1_MINUS_2RGB0 (0 << 30) - # define R500_RGB_SRCP_OP_RGB1_MINUS_RGB0 (1 << 30) - # define R500_RGB_SRCP_OP_RGB1_PLUS_RGB0 (2 << 30) --# define R500_RGB_SRCP_OP_1_PLUS_RGB0 (3 << 30) -+# define R500_RGB_SRCP_OP_1_MINUS_RGB0 (3 << 30) - #define R500_US_CMN_INST_0 0xb800 - # define R500_INST_TYPE_ALU (0 << 0) - # define R500_INST_TYPE_OUT (1 << 0) -@@ -4779,17 +5262,18 @@ - #define R500_GA_US_VECTOR_DATA 0x4254 - - #define R500_RS_INST_0 0x4320 --#define R500_RS_INST_TEX_ID_SHIFT 0 --#define R500_RS_INST_TEX_CN_WRITE (1 << 4) --#define R500_RS_INST_TEX_ADDR_SHIFT 5 --#define R500_RS_INST_COL_ID_SHIFT 12 --#define R500_RS_INST_COL_CN_NO_WRITE (0 << 16) --#define R500_RS_INST_COL_CN_WRITE (1 << 16) --#define R500_RS_INST_COL_CN_WRITE_FBUFFER (2 << 16) --#define R500_RS_INST_COL_CN_WRITE_BACKFACE (3 << 16) --#define R500_RS_INST_COL_COL_ADDR_SHIFT 18 --#define R500_RS_INST_TEX_ADJ (1 << 25) --#define R500_RS_INST_W_CN (1 << 26) -+#define R500_RS_INST_1 0x4324 -+# define R500_RS_INST_TEX_ID_SHIFT 0 -+# define R500_RS_INST_TEX_CN_WRITE (1 << 4) -+# define R500_RS_INST_TEX_ADDR_SHIFT 5 -+# define R500_RS_INST_COL_ID_SHIFT 12 -+# define R500_RS_INST_COL_CN_NO_WRITE (0 << 16) -+# define R500_RS_INST_COL_CN_WRITE (1 << 16) -+# define R500_RS_INST_COL_CN_WRITE_FBUFFER (2 << 16) -+# define R500_RS_INST_COL_CN_WRITE_BACKFACE (3 << 16) -+# define R500_RS_INST_COL_COL_ADDR_SHIFT 18 -+# define R500_RS_INST_TEX_ADJ (1 << 25) -+# define R500_RS_INST_W_CN (1 << 26) - - #define R500_US_FC_CTRL 0x4624 - #define R500_US_CODE_ADDR 0x4630 -@@ -4797,16 +5281,18 @@ - #define R500_US_CODE_OFFSET 0x4638 - - #define R500_RS_IP_0 0x4074 --#define R500_RS_IP_PTR_K0 62 --#define R500_RS_IP_PTR_K1 63 --#define R500_RS_IP_TEX_PTR_S_SHIFT 0 --#define R500_RS_IP_TEX_PTR_T_SHIFT 6 --#define R500_RS_IP_TEX_PTR_R_SHIFT 12 --#define R500_RS_IP_TEX_PTR_Q_SHIFT 18 --#define R500_RS_IP_COL_PTR_SHIFT 24 --#define R500_RS_IP_COL_FMT_SHIFT 27 --#define R500_RS_IP_COL_FMT_RGBA (0<<27) --#define R500_RS_IP_OFFSET_EN (1 << 31) -- -+#define R500_RS_IP_1 0x4078 -+# define R500_RS_IP_PTR_K0 62 -+# define R500_RS_IP_PTR_K1 63 -+# define R500_RS_IP_TEX_PTR_S_SHIFT 0 -+# define R500_RS_IP_TEX_PTR_T_SHIFT 6 -+# define R500_RS_IP_TEX_PTR_R_SHIFT 12 -+# define R500_RS_IP_TEX_PTR_Q_SHIFT 18 -+# define R500_RS_IP_COL_PTR_SHIFT 24 -+# define R500_RS_IP_COL_FMT_SHIFT 27 -+# define R500_RS_IP_COL_FMT_RGBA (0 << 27) -+# define R500_RS_IP_OFFSET_EN (1 << 31) -+ -+#define R500_DYN_SCLK_PWMEM_PIPE 0x000d /* PLL */ - - #endif -diff --git a/src/radeon_render.c b/src/radeon_render.c -index a80d136..dbd5b79 100644 ---- a/src/radeon_render.c -+++ b/src/radeon_render.c -@@ -46,7 +46,7 @@ - struct blendinfo { - Bool dst_alpha; - Bool src_alpha; -- CARD32 blend_cntl; -+ uint32_t blend_cntl; - }; - - /* The first part of blend_cntl corresponds to Fa from the render "protocol" -@@ -166,8 +166,8 @@ static CARD32 RADEONDstFormats[] = { - 0 - }; - --static CARD32 --RadeonGetTextureFormat(CARD32 format) -+static uint32_t -+RadeonGetTextureFormat(uint32_t format) - { - switch (format) { - case PICT_a8r8g8b8: -@@ -187,8 +187,8 @@ RadeonGetTextureFormat(CARD32 format) - } - } - --static CARD32 --RadeonGetColorFormat(CARD32 format) -+static uint32_t -+RadeonGetColorFormat(uint32_t format) - { - switch (format) { - case PICT_a8r8g8b8: -@@ -207,10 +207,10 @@ RadeonGetColorFormat(CARD32 format) - /* Returns a RADEON_RB3D_BLENDCNTL value, or 0 if the operation is not - * supported - */ --static CARD32 --RadeonGetBlendCntl(CARD8 op, CARD32 dstFormat) -+static uint32_t -+RadeonGetBlendCntl(uint8_t op, uint32_t dstFormat) - { -- CARD32 blend_cntl; -+ uint32_t blend_cntl; - - if (op >= RadeonOpMax || RadeonBlendOp[op].blend_cntl == 0) - return 0; -@@ -218,7 +218,7 @@ RadeonGetBlendCntl(CARD8 op, CARD32 dstFormat) - blend_cntl = RadeonBlendOp[op].blend_cntl; - - if (RadeonBlendOp[op].dst_alpha && !PICT_FORMAT_A(dstFormat)) { -- CARD32 srcblend = blend_cntl & RADEON_SRC_BLEND_MASK; -+ uint32_t srcblend = blend_cntl & RADEON_SRC_BLEND_MASK; - - /* If there's no destination alpha channel, we need to wire the blending - * to treat the alpha channel as always 1. -@@ -235,11 +235,11 @@ RadeonGetBlendCntl(CARD8 op, CARD32 dstFormat) - return blend_cntl; - } - --static __inline__ CARD32 F_TO_DW(float val) -+static __inline__ uint32_t F_TO_DW(float val) - { - union { - float f; -- CARD32 l; -+ uint32_t l; - } tmp; - tmp.f = val; - return tmp.l; -@@ -250,10 +250,17 @@ static __inline__ int - ATILog2(int val) - { - int bits; -- -+#if (defined __i386__ || defined __x86_64__) && (defined __GNUC__) -+ __asm volatile("bsrl %1, %0" -+ : "=r" (bits) -+ : "c" (val) -+ ); -+ return bits; -+#else - for (bits = 0; val != 0; val >>= 1, ++bits) - ; - return bits - 1; -+#endif - } - - static void -@@ -317,7 +324,7 @@ static Bool RADEONSetupRenderByteswap(ScrnInfoPtr pScrn, int tex_bytepp) - { - RADEONInfoPtr info = RADEONPTR(pScrn); - unsigned char *RADEONMMIO = info->MMIO; -- CARD32 swapper = info->ModeReg->surface_cntl; -+ uint32_t swapper = info->ModeReg->surface_cntl; - - swapper &= ~(RADEON_NONSURF_AP0_SWP_16BPP | RADEON_NONSURF_AP1_SWP_16BPP | - RADEON_NONSURF_AP0_SWP_32BPP | RADEON_NONSURF_AP1_SWP_32BPP); -@@ -373,22 +380,22 @@ static void RADEONRestoreByteswap(RADEONInfoPtr info) - - static Bool FUNC_NAME(R100SetupTexture)( - ScrnInfoPtr pScrn, -- CARD32 format, -- CARD8 *src, -+ uint32_t format, -+ uint8_t *src, - int src_pitch, - unsigned int width, - unsigned int height, - int flags) - { - RADEONInfoPtr info = RADEONPTR(pScrn); -- CARD8 *dst; -- CARD32 tex_size = 0, txformat; -+ uint8_t *dst; -+ uint32_t tex_size = 0, txformat; - int dst_pitch, offset, size, tex_bytepp; - #ifdef ACCEL_CP -- CARD32 buf_pitch, dst_pitch_off; -+ uint32_t buf_pitch, dst_pitch_off; - int x, y; - unsigned int hpass; -- CARD8 *tmp_dst; -+ uint8_t *tmp_dst; - #endif - ACCEL_PREAMBLE(); - -@@ -429,7 +436,7 @@ static Bool FUNC_NAME(R100SetupTexture)( - } - - offset = info->RenderTex->offset * pScrn->bitsPerPixel / 8; -- dst = (CARD8*)(info->FB + offset); -+ dst = (uint8_t*)(info->FB + offset); - - /* Upload texture to card. */ - -@@ -500,7 +507,7 @@ FUNC_NAME(R100SetupForCPUToScreenAlphaTexture) ( - ) - { - RADEONInfoPtr info = RADEONPTR(pScrn); -- CARD32 colorformat, srccolor, blend_cntl; -+ uint32_t colorformat, srccolor, blend_cntl; - ACCEL_PREAMBLE(); - - blend_cntl = RadeonGetBlendCntl(op, dstFormat); -@@ -551,7 +558,7 @@ FUNC_NAME(R100SetupForCPUToScreenTexture) ( - ) - { - RADEONInfoPtr info = RADEONPTR(pScrn); -- CARD32 colorformat, blend_cntl; -+ uint32_t colorformat, blend_cntl; - ACCEL_PREAMBLE(); - - blend_cntl = RadeonGetBlendCntl(op, dstFormat); -@@ -598,7 +605,7 @@ FUNC_NAME(R100SubsequentCPUToScreenTexture) ( - { - RADEONInfoPtr info = RADEONPTR(pScrn); - int byteshift; -- CARD32 fboffset; -+ uint32_t fboffset; - float l, t, r, b, fl, fr, ft, fb; - - ACCEL_PREAMBLE(); -@@ -710,22 +717,22 @@ FUNC_NAME(R100SubsequentCPUToScreenTexture) ( - - static Bool FUNC_NAME(R200SetupTexture)( - ScrnInfoPtr pScrn, -- CARD32 format, -- CARD8 *src, -+ uint32_t format, -+ uint8_t *src, - int src_pitch, - unsigned int width, - unsigned int height, - int flags) - { - RADEONInfoPtr info = RADEONPTR(pScrn); -- CARD8 *dst; -- CARD32 tex_size = 0, txformat; -+ uint8_t *dst; -+ uint32_t tex_size = 0, txformat; - int dst_pitch, offset, size, tex_bytepp; - #ifdef ACCEL_CP -- CARD32 buf_pitch, dst_pitch_off; -+ uint32_t buf_pitch, dst_pitch_off; - int x, y; - unsigned int hpass; -- CARD8 *tmp_dst; -+ uint8_t *tmp_dst; - #endif - ACCEL_PREAMBLE(); - -@@ -769,7 +776,7 @@ static Bool FUNC_NAME(R200SetupTexture)( - info->texH[0] = height; - - offset = info->RenderTex->offset * pScrn->bitsPerPixel / 8; -- dst = (CARD8*)(info->FB + offset); -+ dst = (uint8_t*)(info->FB + offset); - - /* Upload texture to card. */ - -@@ -841,7 +848,7 @@ FUNC_NAME(R200SetupForCPUToScreenAlphaTexture) ( - ) - { - RADEONInfoPtr info = RADEONPTR(pScrn); -- CARD32 colorformat, srccolor, blend_cntl; -+ uint32_t colorformat, srccolor, blend_cntl; - ACCEL_PREAMBLE(); - - blend_cntl = RadeonGetBlendCntl(op, dstFormat); -@@ -893,7 +900,7 @@ FUNC_NAME(R200SetupForCPUToScreenTexture) ( - ) - { - RADEONInfoPtr info = RADEONPTR(pScrn); -- CARD32 colorformat, blend_cntl; -+ uint32_t colorformat, blend_cntl; - ACCEL_PREAMBLE(); - - blend_cntl = RadeonGetBlendCntl(op, dstFormat); -@@ -941,7 +948,7 @@ FUNC_NAME(R200SubsequentCPUToScreenTexture) ( - { - RADEONInfoPtr info = RADEONPTR(pScrn); - int byteshift; -- CARD32 fboffset; -+ uint32_t fboffset; - float l, t, r, b, fl, fr, ft, fb; - ACCEL_PREAMBLE(); - -diff --git a/src/radeon_textured_video.c b/src/radeon_textured_video.c -index 329a834..cfa349d 100644 ---- a/src/radeon_textured_video.c -+++ b/src/radeon_textured_video.c -@@ -46,6 +46,9 @@ - #define IMAGE_MAX_WIDTH 2048 - #define IMAGE_MAX_HEIGHT 2048 - -+#define IMAGE_MAX_WIDTH_R500 4096 -+#define IMAGE_MAX_HEIGHT_R500 4096 -+ - static Bool - RADEONTilingEnabled(ScrnInfoPtr pScrn, PixmapPtr pPix) - { -@@ -60,18 +63,18 @@ RADEONTilingEnabled(ScrnInfoPtr pScrn, PixmapPtr pPix) - } else - #endif - { -- if (info->tilingEnabled) -+ if (info->tilingEnabled && ((pPix->devPrivate.ptr - info->FB) == 0)) - return TRUE; - else - return FALSE; - } - } - --static __inline__ CARD32 F_TO_DW(float val) -+static __inline__ uint32_t F_TO_DW(float val) - { - union { - float f; -- CARD32 l; -+ uint32_t l; - } tmp; - tmp.f = val; - return tmp.l; -@@ -223,8 +226,8 @@ RADEONPutImageTextured(ScrnInfoPtr pScrn, - left = (x1 >> 16) & ~1; - npixels = ((((x2 + 0xffff) >> 16) + 1) & ~1) - left; - -- pPriv->src_offset = pPriv->video_offset + info->fbLocation; -- pPriv->src_addr = (CARD8 *)(info->FB + pPriv->video_offset + (top * dstPitch)); -+ pPriv->src_offset = pPriv->video_offset + info->fbLocation + pScrn->fbOffset; -+ pPriv->src_addr = (uint8_t *)(info->FB + pPriv->video_offset + (top * dstPitch)); - pPriv->src_pitch = dstPitch; - pPriv->size = size; - pPriv->pDraw = pDraw; -@@ -300,6 +303,16 @@ static XF86VideoEncodingRec DummyEncoding[1] = - } - }; - -+static XF86VideoEncodingRec DummyEncodingR500[1] = -+{ -+ { -+ 0, -+ "XV_IMAGE", -+ IMAGE_MAX_WIDTH_R500, IMAGE_MAX_HEIGHT_R500, -+ {1, 1} -+ } -+}; -+ - #define NUM_FORMATS 3 - - static XF86VideoFormatRec Formats[NUM_FORMATS] = -@@ -326,6 +339,8 @@ static XF86ImageRec Images[NUM_IMAGES] = - XF86VideoAdaptorPtr - RADEONSetupImageTexturedVideo(ScreenPtr pScreen) - { -+ ScrnInfoPtr pScrn = xf86Screens[pScreen->myNum]; -+ RADEONInfoPtr info = RADEONPTR(pScrn); - RADEONPortPrivPtr pPortPriv; - XF86VideoAdaptorPtr adapt; - int i; -@@ -340,7 +355,10 @@ RADEONSetupImageTexturedVideo(ScreenPtr pScreen) - adapt->flags = 0; - adapt->name = "Radeon Textured Video"; - adapt->nEncodings = 1; -- adapt->pEncodings = DummyEncoding; -+ if (IS_R500_3D) -+ adapt->pEncodings = DummyEncodingR500; -+ else -+ adapt->pEncodings = DummyEncoding; - adapt->nFormats = NUM_FORMATS; - adapt->pFormats = Formats; - adapt->nPorts = num_texture_ports; -diff --git a/src/radeon_textured_videofuncs.c b/src/radeon_textured_videofuncs.c -index e0f3bba..d39f74d 100644 ---- a/src/radeon_textured_videofuncs.c -+++ b/src/radeon_textured_videofuncs.c -@@ -74,22 +74,21 @@ FUNC_NAME(RADEONDisplayTexturedVideo)(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv - { - RADEONInfoPtr info = RADEONPTR(pScrn); - PixmapPtr pPixmap = pPriv->pPixmap; -- CARD32 txformat; -- CARD32 txfilter, txformat0, txformat1, txoffset, txpitch; -- CARD32 dst_offset, dst_pitch, dst_format; -- CARD32 txenable, colorpitch; -- CARD32 blendcntl; -+ uint32_t txformat; -+ uint32_t txfilter, txformat0, txformat1, txoffset, txpitch; -+ uint32_t dst_offset, dst_pitch, dst_format; -+ uint32_t txenable, colorpitch; -+ uint32_t blendcntl; - int dstxoff, dstyoff, pixel_shift; -- VIDEO_PREAMBLE(); -- - BoxPtr pBox = REGION_RECTS(&pPriv->clip); - int nBox = REGION_NUM_RECTS(&pPriv->clip); -+ VIDEO_PREAMBLE(); - - pixel_shift = pPixmap->drawable.bitsPerPixel >> 4; - - #ifdef USE_EXA - if (info->useEXA) { -- dst_offset = exaGetPixmapOffset(pPixmap) + info->fbLocation; -+ dst_offset = exaGetPixmapOffset(pPixmap) + info->fbLocation + pScrn->fbOffset; - dst_pitch = exaGetPixmapPitch(pPixmap); - } else - #endif -@@ -107,28 +106,25 @@ FUNC_NAME(RADEONDisplayTexturedVideo)(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv - dstyoff = 0; - #endif - --#if 0 -- ErrorF("dst_offset: 0x%x\n", dst_offset); -- ErrorF("dst_pitch: 0x%x\n", dst_pitch); -- ErrorF("dstxoff: 0x%x\n", dstxoff); -- ErrorF("dstyoff: 0x%x\n", dstyoff); -- ErrorF("src_offset: 0x%x\n", pPriv->src_offset); -- ErrorF("src_pitch: 0x%x\n", pPriv->src_pitch); --#endif -- - if (!info->XInited3D) - RADEONInit3DEngine(pScrn); - - /* we can probably improve this */ - BEGIN_VIDEO(2); -- OUT_VIDEO_REG(RADEON_RB3D_DSTCACHE_CTLSTAT, RADEON_RB3D_DC_FLUSH); -+ if (IS_R300_3D || IS_R500_3D) -+ OUT_VIDEO_REG(R300_RB3D_DSTCACHE_CTLSTAT, R300_DC_FLUSH_3D); -+ else -+ OUT_VIDEO_REG(RADEON_RB3D_DSTCACHE_CTLSTAT, RADEON_RB3D_DC_FLUSH); - /* We must wait for 3d to idle, in case source was just written as a dest. */ - OUT_VIDEO_REG(RADEON_WAIT_UNTIL, -- RADEON_WAIT_HOST_IDLECLEAN | RADEON_WAIT_2D_IDLECLEAN | RADEON_WAIT_3D_IDLECLEAN); -+ RADEON_WAIT_HOST_IDLECLEAN | -+ RADEON_WAIT_2D_IDLECLEAN | -+ RADEON_WAIT_3D_IDLECLEAN | -+ RADEON_WAIT_DMA_GUI_IDLE); - FINISH_VIDEO(); - -- if (IS_R300_VARIANT || IS_AVIVO_VARIANT) { -- int has_tcl = (info->ChipFamily != CHIP_FAMILY_RS690 && info->ChipFamily != CHIP_FAMILY_RS400); -+ if (IS_R300_3D || IS_R500_3D) { -+ uint32_t output_fmt; - - switch (pPixmap->drawable.bitsPerPixel) { - case 16: -@@ -144,6 +140,12 @@ FUNC_NAME(RADEONDisplayTexturedVideo)(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv - return; - } - -+ output_fmt = (R300_OUT_FMT_C4_8 | -+ R300_OUT_FMT_C0_SEL_BLUE | -+ R300_OUT_FMT_C1_SEL_GREEN | -+ R300_OUT_FMT_C2_SEL_RED | -+ R300_OUT_FMT_C3_SEL_ALPHA); -+ - colorpitch = dst_pitch >> pixel_shift; - colorpitch |= dst_format; - -@@ -157,8 +159,8 @@ FUNC_NAME(RADEONDisplayTexturedVideo)(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv - - txformat1 |= R300_TX_FORMAT_YUV_TO_RGB_CLAMP; - -- txformat0 = (((pPriv->w - 1) << R300_TXWIDTH_SHIFT) | -- ((pPriv->h - 1) << R300_TXHEIGHT_SHIFT)); -+ txformat0 = ((((pPriv->w - 1) & 0x7ff) << R300_TXWIDTH_SHIFT) | -+ (((pPriv->h - 1) & 0x7ff) << R300_TXHEIGHT_SHIFT)); - - txformat0 |= R300_TXPITCH_EN; - -@@ -173,6 +175,12 @@ FUNC_NAME(RADEONDisplayTexturedVideo)(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv - txpitch = pPriv->src_pitch / 2; - txpitch -= 1; - -+ if (IS_R500_3D && ((pPriv->w - 1) & 0x800)) -+ txpitch |= R500_TXWIDTH_11; -+ -+ if (IS_R500_3D && ((pPriv->h - 1) & 0x800)) -+ txpitch |= R500_TXHEIGHT_11; -+ - txoffset = pPriv->src_offset; - - BEGIN_VIDEO(6); -@@ -187,173 +195,220 @@ FUNC_NAME(RADEONDisplayTexturedVideo)(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv - txenable = R300_TEX_0_ENABLE; - - /* setup the VAP */ -- if (has_tcl) { -- BEGIN_VIDEO(26); -- OUT_VIDEO_REG(R300_VAP_CNTL_STATUS, 0); -- OUT_VIDEO_REG(R300_VAP_PVS_STATE_FLUSH_REG, 0); -- OUT_VIDEO_REG(R300_VAP_CNTL, ((6 << R300_PVS_NUM_SLOTS_SHIFT) | -- (5 << R300_PVS_NUM_CNTLRS_SHIFT) | -- (4 << R300_PVS_NUM_FPUS_SHIFT) | -- (12 << R300_VF_MAX_VTX_NUM_SHIFT))); -- } else { -- BEGIN_VIDEO(8); -- OUT_VIDEO_REG(R300_VAP_CNTL_STATUS, R300_PVS_BYPASS); -- OUT_VIDEO_REG(R300_VAP_CNTL, ((10 << R300_PVS_NUM_SLOTS_SHIFT) | -- (5 << R300_PVS_NUM_CNTLRS_SHIFT) | -- (4 << R300_PVS_NUM_FPUS_SHIFT) | -- (5 << R300_VF_MAX_VTX_NUM_SHIFT))); -- } -- -- OUT_VIDEO_REG(R300_VAP_VTE_CNTL, R300_VTX_XY_FMT | R300_VTX_Z_FMT); -- OUT_VIDEO_REG(R300_VAP_PSC_SGN_NORM_CNTL, 0); -- -- if (has_tcl) { -- OUT_VIDEO_REG(R300_VAP_PROG_STREAM_CNTL_0, -- ((R300_DATA_TYPE_FLOAT_2 << R300_DATA_TYPE_0_SHIFT) | -- (0 << R300_SKIP_DWORDS_0_SHIFT) | -- (0 << R300_DST_VEC_LOC_0_SHIFT) | -- R300_SIGNED_0 | -- (R300_DATA_TYPE_FLOAT_2 << R300_DATA_TYPE_1_SHIFT) | -- (0 << R300_SKIP_DWORDS_1_SHIFT) | -- (10 << R300_DST_VEC_LOC_1_SHIFT) | -- R300_LAST_VEC_1 | -- R300_SIGNED_1)); -- OUT_VIDEO_REG(R300_VAP_PROG_STREAM_CNTL_EXT_0, -- ((R300_SWIZZLE_SELECT_X << R300_SWIZZLE_SELECT_X_0_SHIFT) | -- (R300_SWIZZLE_SELECT_Y << R300_SWIZZLE_SELECT_Y_0_SHIFT) | -- (R300_SWIZZLE_SELECT_Z << R300_SWIZZLE_SELECT_Z_0_SHIFT) | -- (R300_SWIZZLE_SELECT_W << R300_SWIZZLE_SELECT_W_0_SHIFT) | -- ((R300_WRITE_ENA_X | R300_WRITE_ENA_Y | R300_WRITE_ENA_Z | R300_WRITE_ENA_W) -- << R300_WRITE_ENA_0_SHIFT) | -- (R300_SWIZZLE_SELECT_X << R300_SWIZZLE_SELECT_X_1_SHIFT) | -- (R300_SWIZZLE_SELECT_Y << R300_SWIZZLE_SELECT_Y_1_SHIFT) | -- (R300_SWIZZLE_SELECT_Z << R300_SWIZZLE_SELECT_Z_1_SHIFT) | -- (R300_SWIZZLE_SELECT_W << R300_SWIZZLE_SELECT_W_1_SHIFT) | -- ((R300_WRITE_ENA_X | R300_WRITE_ENA_Y | R300_WRITE_ENA_Z | R300_WRITE_ENA_W) -- << R300_WRITE_ENA_1_SHIFT))); -- } else { -- OUT_VIDEO_REG(R300_VAP_PROG_STREAM_CNTL_0, -- ((R300_DATA_TYPE_FLOAT_2 << R300_DATA_TYPE_0_SHIFT) | -- (0 << R300_SKIP_DWORDS_0_SHIFT) | -- (0 << R300_DST_VEC_LOC_0_SHIFT) | -- R300_SIGNED_0 | -- (R300_DATA_TYPE_FLOAT_2 << R300_DATA_TYPE_1_SHIFT) | -- (0 << R300_SKIP_DWORDS_1_SHIFT) | -- (6 << R300_DST_VEC_LOC_1_SHIFT) | -- R300_LAST_VEC_1 | -- R300_SIGNED_1)); -- OUT_VIDEO_REG(R300_VAP_PROG_STREAM_CNTL_EXT_0, -- ((R300_SWIZZLE_SELECT_X << R300_SWIZZLE_SELECT_X_0_SHIFT) | -- (R300_SWIZZLE_SELECT_Y << R300_SWIZZLE_SELECT_Y_0_SHIFT) | -- (R300_SWIZZLE_SELECT_FP_ZERO << R300_SWIZZLE_SELECT_Z_0_SHIFT) | -- (R300_SWIZZLE_SELECT_FP_ONE << R300_SWIZZLE_SELECT_W_0_SHIFT) | -- ((R300_WRITE_ENA_X | R300_WRITE_ENA_Y) -- << R300_WRITE_ENA_0_SHIFT) | -- (R300_SWIZZLE_SELECT_X << R300_SWIZZLE_SELECT_X_1_SHIFT) | -- (R300_SWIZZLE_SELECT_Y << R300_SWIZZLE_SELECT_Y_1_SHIFT) | -- (R300_SWIZZLE_SELECT_FP_ZERO << R300_SWIZZLE_SELECT_Z_1_SHIFT) | -- (R300_SWIZZLE_SELECT_FP_ONE << R300_SWIZZLE_SELECT_W_1_SHIFT) | -- ((R300_WRITE_ENA_X | R300_WRITE_ENA_Y) -- << R300_WRITE_ENA_1_SHIFT))); -- } -- -- /* setup vertex shader */ -- if (has_tcl) { -+ if (info->has_tcl) -+ BEGIN_VIDEO(6); -+ else -+ BEGIN_VIDEO(4); -+ -+ /* These registers define the number, type, and location of data submitted -+ * to the PVS unit of GA input (when PVS is disabled) -+ * DST_VEC_LOC is the slot in the PVS input vector memory when PVS/TCL is -+ * enabled. This memory provides the imputs to the vertex shader program -+ * and ordering is not important. When PVS/TCL is disabled, this field maps -+ * directly to the GA input memory and the order is signifigant. In -+ * PVS_BYPASS mode the order is as follows: -+ * Position -+ * Point Size -+ * Color 0-3 -+ * Textures 0-7 -+ * Fog -+ */ -+ OUT_VIDEO_REG(R300_VAP_PROG_STREAM_CNTL_0, -+ ((R300_DATA_TYPE_FLOAT_2 << R300_DATA_TYPE_0_SHIFT) | -+ (0 << R300_SKIP_DWORDS_0_SHIFT) | -+ (0 << R300_DST_VEC_LOC_0_SHIFT) | -+ R300_SIGNED_0 | -+ (R300_DATA_TYPE_FLOAT_2 << R300_DATA_TYPE_1_SHIFT) | -+ (0 << R300_SKIP_DWORDS_1_SHIFT) | -+ (6 << R300_DST_VEC_LOC_1_SHIFT) | -+ R300_LAST_VEC_1 | -+ R300_SIGNED_1)); -+ -+ /* load the vertex shader -+ * We pre-load vertex programs in RADEONInit3DEngine(): -+ * - exa no mask -+ * - exa mask -+ * - Xv -+ * Here we select the offset of the vertex program we want to use -+ */ -+ if (info->has_tcl) { - OUT_VIDEO_REG(R300_VAP_PVS_CODE_CNTL_0, -- ((0 << R300_PVS_FIRST_INST_SHIFT) | -- (1 << R300_PVS_XYZW_VALID_INST_SHIFT) | -- (1 << R300_PVS_LAST_INST_SHIFT))); -+ ((5 << R300_PVS_FIRST_INST_SHIFT) | -+ (6 << R300_PVS_XYZW_VALID_INST_SHIFT) | -+ (6 << R300_PVS_LAST_INST_SHIFT))); - OUT_VIDEO_REG(R300_VAP_PVS_CODE_CNTL_1, -- (1 << R300_PVS_LAST_VTX_SRC_INST_SHIFT)); -- OUT_VIDEO_REG(R300_VAP_PVS_VECTOR_INDX_REG, 0); -- OUT_VIDEO_REG(R300_VAP_PVS_VECTOR_DATA_REG,0x00f00203); -- OUT_VIDEO_REG(R300_VAP_PVS_VECTOR_DATA_REG,0x00d10001); -- OUT_VIDEO_REG(R300_VAP_PVS_VECTOR_DATA_REG,0x01248001); -- OUT_VIDEO_REG(R300_VAP_PVS_VECTOR_DATA_REG,0x01248001); -- OUT_VIDEO_REG(R300_VAP_PVS_VECTOR_DATA_REG,0x00f02203); -- OUT_VIDEO_REG(R300_VAP_PVS_VECTOR_DATA_REG,0x00d10141); -- OUT_VIDEO_REG(R300_VAP_PVS_VECTOR_DATA_REG,0x01248141); -- OUT_VIDEO_REG(R300_VAP_PVS_VECTOR_DATA_REG,0x01248141); -- OUT_VIDEO_REG(R300_VAP_PVS_FLOW_CNTL_OPC, 0); -- -- -- OUT_VIDEO_REG(R300_VAP_GB_VERT_CLIP_ADJ, 0x3f800000); -- OUT_VIDEO_REG(R300_VAP_GB_VERT_DISC_ADJ, 0x3f800000); -- OUT_VIDEO_REG(R300_VAP_GB_HORZ_CLIP_ADJ, 0x3f800000); -- OUT_VIDEO_REG(R300_VAP_GB_HORZ_DISC_ADJ, 0x3f800000); -- OUT_VIDEO_REG(R300_VAP_CLIP_CNTL, R300_CLIP_DISABLE); -+ (6 << R300_PVS_LAST_VTX_SRC_INST_SHIFT)); - } - -+ /* Position and one set of 2 texture coordinates */ - OUT_VIDEO_REG(R300_VAP_OUT_VTX_FMT_0, R300_VTX_POS_PRESENT); - OUT_VIDEO_REG(R300_VAP_OUT_VTX_FMT_1, (2 << R300_TEX_0_COMP_CNT_SHIFT)); -+ OUT_VIDEO_REG(R300_US_OUT_FMT_0, output_fmt); - FINISH_VIDEO(); - - /* setup pixel shader */ -- if (IS_R300_VARIANT || info->ChipFamily == CHIP_FAMILY_RS690) { -- BEGIN_VIDEO(16); -+ if (IS_R300_3D) { -+ BEGIN_VIDEO(8); -+ /* 2 components: 2 for tex0 */ - OUT_VIDEO_REG(R300_RS_COUNT, - ((2 << R300_RS_COUNT_IT_COUNT_SHIFT) | - R300_RS_COUNT_HIRES_EN)); -- OUT_VIDEO_REG(R300_RS_IP_0, -- (R300_RS_TEX_PTR(0) | -- R300_RS_COL_PTR(0) | -- R300_RS_COL_FMT(R300_RS_COL_FMT_RGBA) | -- R300_RS_SEL_S(R300_RS_SEL_C0) | -- R300_RS_SEL_T(R300_RS_SEL_C1) | -- R300_RS_SEL_R(R300_RS_SEL_K0) | -- R300_RS_SEL_Q(R300_RS_SEL_K1))); -- OUT_VIDEO_REG(R300_RS_INST_COUNT, R300_TX_OFFSET_RS(6)); -- OUT_VIDEO_REG(R300_RS_INST_0, R300_RS_INST_TEX_CN_WRITE); -- OUT_VIDEO_REG(R300_US_CONFIG, (0 << R300_NLEVEL_SHIFT) | R300_FIRST_TEX); -- OUT_VIDEO_REG(R300_US_PIXSIZE, 0); -+ /* R300_INST_COUNT_RS - highest RS instruction used */ -+ OUT_VIDEO_REG(R300_RS_INST_COUNT, R300_INST_COUNT_RS(0) | R300_TX_OFFSET_RS(6)); -+ - OUT_VIDEO_REG(R300_US_CODE_OFFSET, - (R300_ALU_CODE_OFFSET(0) | - R300_ALU_CODE_SIZE(1) | - R300_TEX_CODE_OFFSET(0) | - R300_TEX_CODE_SIZE(1))); -- OUT_VIDEO_REG(R300_US_CODE_ADDR_0, 0); -- OUT_VIDEO_REG(R300_US_CODE_ADDR_1, 0); -- OUT_VIDEO_REG(R300_US_CODE_ADDR_2, 0); -- OUT_VIDEO_REG(R300_US_CODE_ADDR_3, 0x400000); -- OUT_VIDEO_REG(R300_US_TEX_INST_0, 0x8000); -- OUT_VIDEO_REG(R300_US_ALU_RGB_ADDR_0, 0x1f800000); -- OUT_VIDEO_REG(R300_US_ALU_RGB_INST_0, 0x50a80); -- OUT_VIDEO_REG(R300_US_ALU_ALPHA_ADDR_0, 0x1800000); -- OUT_VIDEO_REG(R300_US_ALU_ALPHA_INST_0, 0x00040889); -+ -+ OUT_VIDEO_REG(R300_US_CODE_ADDR_3, -+ (R300_ALU_START(0) | -+ R300_ALU_SIZE(0) | -+ R300_TEX_START(0) | -+ R300_TEX_SIZE(0) | -+ R300_RGBA_OUT)); -+ -+ /* tex inst is preloaded in RADEONInit3DEngine() */ -+ -+ /* ALU inst */ -+ /* RGB */ -+ OUT_VIDEO_REG(R300_US_ALU_RGB_ADDR_0, -+ (R300_ALU_RGB_ADDR0(0) | -+ R300_ALU_RGB_ADDR1(0) | -+ R300_ALU_RGB_ADDR2(0) | -+ R300_ALU_RGB_ADDRD(0) | -+ R300_ALU_RGB_OMASK((R300_ALU_RGB_MASK_R | -+ R300_ALU_RGB_MASK_G | -+ R300_ALU_RGB_MASK_B)) | -+ R300_ALU_RGB_TARGET_A)); -+ OUT_VIDEO_REG(R300_US_ALU_RGB_INST_0, -+ (R300_ALU_RGB_SEL_A(R300_ALU_RGB_SRC0_RGB) | -+ R300_ALU_RGB_MOD_A(R300_ALU_RGB_MOD_NOP) | -+ R300_ALU_RGB_SEL_B(R300_ALU_RGB_1_0) | -+ R300_ALU_RGB_MOD_B(R300_ALU_RGB_MOD_NOP) | -+ R300_ALU_RGB_SEL_C(R300_ALU_RGB_0_0) | -+ R300_ALU_RGB_MOD_C(R300_ALU_RGB_MOD_NOP) | -+ R300_ALU_RGB_OP(R300_ALU_RGB_OP_MAD) | -+ R300_ALU_RGB_OMOD(R300_ALU_RGB_OMOD_NONE) | -+ R300_ALU_RGB_CLAMP)); -+ /* Alpha */ -+ OUT_VIDEO_REG(R300_US_ALU_ALPHA_ADDR_0, -+ (R300_ALU_ALPHA_ADDR0(0) | -+ R300_ALU_ALPHA_ADDR1(0) | -+ R300_ALU_ALPHA_ADDR2(0) | -+ R300_ALU_ALPHA_ADDRD(0) | -+ R300_ALU_ALPHA_OMASK(R300_ALU_ALPHA_MASK_A) | -+ R300_ALU_ALPHA_TARGET_A | -+ R300_ALU_ALPHA_OMASK_W(R300_ALU_ALPHA_MASK_NONE))); -+ OUT_VIDEO_REG(R300_US_ALU_ALPHA_INST_0, -+ (R300_ALU_ALPHA_SEL_A(R300_ALU_ALPHA_SRC0_A) | -+ R300_ALU_ALPHA_MOD_A(R300_ALU_ALPHA_MOD_NOP) | -+ R300_ALU_ALPHA_SEL_B(R300_ALU_ALPHA_1_0) | -+ R300_ALU_ALPHA_MOD_B(R300_ALU_ALPHA_MOD_NOP) | -+ R300_ALU_ALPHA_SEL_C(R300_ALU_ALPHA_0_0) | -+ R300_ALU_ALPHA_MOD_C(R300_ALU_ALPHA_MOD_NOP) | -+ R300_ALU_ALPHA_OP(R300_ALU_ALPHA_OP_MAD) | -+ R300_ALU_ALPHA_OMOD(R300_ALU_ALPHA_OMOD_NONE) | -+ R300_ALU_ALPHA_CLAMP)); - FINISH_VIDEO(); - } else { -- BEGIN_VIDEO(22); -+ BEGIN_VIDEO(18); -+ /* 2 components: 2 for tex0 */ - OUT_VIDEO_REG(R300_RS_COUNT, - ((2 << R300_RS_COUNT_IT_COUNT_SHIFT) | - R300_RS_COUNT_HIRES_EN)); -- OUT_VIDEO_REG(R500_RS_IP_0, (0 << R500_RS_IP_TEX_PTR_S_SHIFT) | (1 << R500_RS_IP_TEX_PTR_T_SHIFT) | -- (R500_RS_IP_PTR_K0 << R500_RS_IP_TEX_PTR_R_SHIFT) | (R500_RS_IP_PTR_K1 << R500_RS_IP_TEX_PTR_Q_SHIFT)); -- -- OUT_VIDEO_REG(R300_RS_INST_COUNT, 0); -- OUT_VIDEO_REG(R500_RS_INST_0, R500_RS_INST_TEX_CN_WRITE); -- OUT_VIDEO_REG(R300_US_CONFIG, R500_ZERO_TIMES_ANYTHING_EQUALS_ZERO); -- OUT_VIDEO_REG(R300_US_PIXSIZE, 0); -- OUT_VIDEO_REG(R500_US_FC_CTRL, 0); -- OUT_VIDEO_REG(R500_US_CODE_ADDR, R500_US_CODE_START_ADDR(0) | R500_US_CODE_END_ADDR(1)); -- OUT_VIDEO_REG(R500_US_CODE_RANGE, R500_US_CODE_RANGE_ADDR(0) | R500_US_CODE_RANGE_SIZE(1)); -+ -+ /* R300_INST_COUNT_RS - highest RS instruction used */ -+ OUT_VIDEO_REG(R300_RS_INST_COUNT, R300_INST_COUNT_RS(0) | R300_TX_OFFSET_RS(6)); -+ -+ OUT_VIDEO_REG(R500_US_CODE_ADDR, (R500_US_CODE_START_ADDR(0) | -+ R500_US_CODE_END_ADDR(1))); -+ OUT_VIDEO_REG(R500_US_CODE_RANGE, (R500_US_CODE_RANGE_ADDR(0) | -+ R500_US_CODE_RANGE_SIZE(1))); - OUT_VIDEO_REG(R500_US_CODE_OFFSET, 0); - OUT_VIDEO_REG(R500_GA_US_VECTOR_INDEX, 0); -- OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, 0x00007807); -- OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, 0x06400000); -- OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, 0xe4000400); -- OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, 0x00000000); -+ -+ /* tex inst */ -+ OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_INST_TYPE_TEX | -+ R500_INST_TEX_SEM_WAIT | -+ R500_INST_RGB_WMASK_R | -+ R500_INST_RGB_WMASK_G | -+ R500_INST_RGB_WMASK_B | -+ R500_INST_ALPHA_WMASK | -+ R500_INST_RGB_CLAMP | -+ R500_INST_ALPHA_CLAMP)); -+ -+ OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_TEX_ID(0) | -+ R500_TEX_INST_LD | -+ R500_TEX_SEM_ACQUIRE | -+ R500_TEX_IGNORE_UNCOVERED)); -+ -+ OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_TEX_SRC_ADDR(0) | -+ R500_TEX_SRC_S_SWIZ_R | -+ R500_TEX_SRC_T_SWIZ_G | -+ R500_TEX_DST_ADDR(0) | -+ R500_TEX_DST_R_SWIZ_R | -+ R500_TEX_DST_G_SWIZ_G | -+ R500_TEX_DST_B_SWIZ_B | -+ R500_TEX_DST_A_SWIZ_A)); -+ OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_DX_ADDR(0) | -+ R500_DX_S_SWIZ_R | -+ R500_DX_T_SWIZ_R | -+ R500_DX_R_SWIZ_R | -+ R500_DX_Q_SWIZ_R | -+ R500_DY_ADDR(0) | -+ R500_DY_S_SWIZ_R | -+ R500_DY_T_SWIZ_R | -+ R500_DY_R_SWIZ_R | -+ R500_DY_Q_SWIZ_R)); - OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, 0x00000000); - OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, 0x00000000); -- OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, 0x00078105); -- OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, 0x10040000); -- OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, 0x10040000); -- OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, 0x00db0220); -- OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, 0x00c0c000); -- OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, 0x20490000); -+ -+ /* ALU inst */ -+ OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_INST_TYPE_OUT | -+ R500_INST_TEX_SEM_WAIT | -+ R500_INST_LAST | -+ R500_INST_RGB_OMASK_R | -+ R500_INST_RGB_OMASK_G | -+ R500_INST_RGB_OMASK_B | -+ R500_INST_ALPHA_OMASK | -+ R500_INST_RGB_CLAMP | -+ R500_INST_ALPHA_CLAMP)); -+ -+ OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_RGB_ADDR0(0) | -+ R500_RGB_ADDR1(0) | -+ R500_RGB_ADDR1_CONST | -+ R500_RGB_ADDR2(0) | -+ R500_RGB_ADDR2_CONST)); -+ OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_ALPHA_ADDR0(0) | -+ R500_ALPHA_ADDR1(0) | -+ R500_ALPHA_ADDR1_CONST | -+ R500_ALPHA_ADDR2(0) | -+ R500_ALPHA_ADDR2_CONST)); -+ -+ OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_ALU_RGB_SEL_A_SRC0 | -+ R500_ALU_RGB_R_SWIZ_A_R | -+ R500_ALU_RGB_G_SWIZ_A_G | -+ R500_ALU_RGB_B_SWIZ_A_B | -+ R500_ALU_RGB_SEL_B_SRC0 | -+ R500_ALU_RGB_R_SWIZ_B_1 | -+ R500_ALU_RGB_B_SWIZ_B_1 | -+ R500_ALU_RGB_G_SWIZ_B_1)); -+ -+ OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_ALPHA_OP_MAD | -+ R500_ALPHA_SWIZ_A_A | -+ R500_ALPHA_SWIZ_B_1)); -+ -+ OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_ALU_RGBA_OP_MAD | -+ R500_ALU_RGBA_R_SWIZ_0 | -+ R500_ALU_RGBA_G_SWIZ_0 | -+ R500_ALU_RGBA_B_SWIZ_0 | -+ R500_ALU_RGBA_A_SWIZ_0)); - FINISH_VIDEO(); - } - -- BEGIN_VIDEO(6); -+ BEGIN_VIDEO(5); - OUT_VIDEO_REG(R300_TX_INVALTAGS, 0); - OUT_VIDEO_REG(R300_TX_ENABLE, txenable); - -@@ -361,8 +416,8 @@ FUNC_NAME(RADEONDisplayTexturedVideo)(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv - OUT_VIDEO_REG(R300_RB3D_COLORPITCH0, colorpitch); - - blendcntl = RADEON_SRC_BLEND_GL_ONE | RADEON_DST_BLEND_GL_ZERO; -+ /* no need to enable blending */ - OUT_VIDEO_REG(R300_RB3D_BLENDCNTL, blendcntl); -- OUT_VIDEO_REG(R300_RB3D_ABLENDCNTL, 0); - FINISH_VIDEO(); - - BEGIN_VIDEO(1); -@@ -431,6 +486,8 @@ FUNC_NAME(RADEONDisplayTexturedVideo)(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv - OUT_VIDEO_REG(R200_PP_TXFILTER_0, - R200_MAG_FILTER_LINEAR | - R200_MIN_FILTER_LINEAR | -+ R200_CLAMP_S_CLAMP_LAST | -+ R200_CLAMP_T_CLAMP_LAST | - R200_YUV_TO_RGB); - OUT_VIDEO_REG(R200_PP_TXFORMAT_0, txformat); - OUT_VIDEO_REG(R200_PP_TXFORMAT_X_0, 0); -@@ -466,8 +523,11 @@ FUNC_NAME(RADEONDisplayTexturedVideo)(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv - OUT_VIDEO_REG(RADEON_SE_VTX_FMT, RADEON_SE_VTX_FMT_XY | - RADEON_SE_VTX_FMT_ST0); - -- OUT_VIDEO_REG(RADEON_PP_TXFILTER_0, RADEON_MAG_FILTER_LINEAR | -+ OUT_VIDEO_REG(RADEON_PP_TXFILTER_0, -+ RADEON_MAG_FILTER_LINEAR | - RADEON_MIN_FILTER_LINEAR | -+ RADEON_CLAMP_S_CLAMP_LAST | -+ RADEON_CLAMP_T_CLAMP_LAST | - RADEON_YUV_TO_RGB); - OUT_VIDEO_REG(RADEON_PP_TXFORMAT_0, txformat); - OUT_VIDEO_REG(RADEON_PP_TXOFFSET_0, pPriv->src_offset); -@@ -527,47 +587,50 @@ FUNC_NAME(RADEONDisplayTexturedVideo)(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv - - #ifdef ACCEL_CP - if (info->ChipFamily < CHIP_FAMILY_R200) { -- BEGIN_RING(4 * VTX_DWORD_COUNT + 3); -+ BEGIN_RING(3 * VTX_DWORD_COUNT + 3); - OUT_RING(CP_PACKET3(RADEON_CP_PACKET3_3D_DRAW_IMMD, -- 4 * VTX_DWORD_COUNT + 1)); -+ 3 * VTX_DWORD_COUNT + 1)); - OUT_RING(RADEON_CP_VC_FRMT_XY | - RADEON_CP_VC_FRMT_ST0); -- OUT_RING(RADEON_CP_VC_CNTL_PRIM_TYPE_TRI_FAN | -+ OUT_RING(RADEON_CP_VC_CNTL_PRIM_TYPE_RECT_LIST | - RADEON_CP_VC_CNTL_PRIM_WALK_RING | - RADEON_CP_VC_CNTL_MAOS_ENABLE | - RADEON_CP_VC_CNTL_VTX_FMT_RADEON_MODE | -- (4 << RADEON_CP_VC_CNTL_NUM_SHIFT)); -+ (3 << RADEON_CP_VC_CNTL_NUM_SHIFT)); - } else { -- if (IS_R300_VARIANT || IS_AVIVO_VARIANT) -- BEGIN_RING(4 * VTX_DWORD_COUNT + 6); -+ if (IS_R300_3D || IS_R500_3D) -+ BEGIN_RING(4 * VTX_DWORD_COUNT + 4); - else - BEGIN_RING(4 * VTX_DWORD_COUNT + 2); - OUT_RING(CP_PACKET3(R200_CP_PACKET3_3D_DRAW_IMMD_2, - 4 * VTX_DWORD_COUNT)); -- OUT_RING(RADEON_CP_VC_CNTL_PRIM_TYPE_TRI_FAN | -+ OUT_RING(RADEON_CP_VC_CNTL_PRIM_TYPE_QUAD_LIST | - RADEON_CP_VC_CNTL_PRIM_WALK_RING | - (4 << RADEON_CP_VC_CNTL_NUM_SHIFT)); - } - #else /* ACCEL_CP */ -- if (IS_R300_VARIANT || IS_AVIVO_VARIANT) -- BEGIN_VIDEO(3 + VTX_DWORD_COUNT * 4); -+ if (IS_R300_3D || IS_R500_3D) -+ BEGIN_VIDEO(2 + VTX_DWORD_COUNT * 4); -+ else if (info->ChipFamily < CHIP_FAMILY_R200) -+ BEGIN_VIDEO(1 + VTX_DWORD_COUNT * 3); - else - BEGIN_VIDEO(1 + VTX_DWORD_COUNT * 4); - - if (info->ChipFamily < CHIP_FAMILY_R200) { -- OUT_VIDEO_REG(RADEON_SE_VF_CNTL, (RADEON_VF_PRIM_TYPE_TRIANGLE_FAN | -+ OUT_VIDEO_REG(RADEON_SE_VF_CNTL, (RADEON_VF_PRIM_TYPE_RECTANGLE_LIST | - RADEON_VF_PRIM_WALK_DATA | - RADEON_VF_RADEON_MODE | -- 4 << RADEON_VF_NUM_VERTICES_SHIFT)); -+ (3 << RADEON_VF_NUM_VERTICES_SHIFT))); - } else { - OUT_VIDEO_REG(RADEON_SE_VF_CNTL, (RADEON_VF_PRIM_TYPE_QUAD_LIST | - RADEON_VF_PRIM_WALK_DATA | -- 4 << RADEON_VF_NUM_VERTICES_SHIFT)); -+ (4 << RADEON_VF_NUM_VERTICES_SHIFT))); - } - #endif -- -- VTX_OUT((float)dstX, (float)dstY, -- xFixedToFloat(srcTopLeft.x) / info->texW[0], xFixedToFloat(srcTopLeft.y) / info->texH[0]); -+ if (info->ChipFamily >= CHIP_FAMILY_R200) { -+ VTX_OUT((float)dstX, (float)dstY, -+ xFixedToFloat(srcTopLeft.x) / info->texW[0], xFixedToFloat(srcTopLeft.y) / info->texH[0]); -+ } - VTX_OUT((float)dstX, (float)(dstY + dsth), - xFixedToFloat(srcBottomLeft.x) / info->texW[0], xFixedToFloat(srcBottomLeft.y) / info->texH[0]); - VTX_OUT((float)(dstX + dstw), (float)(dstY + dsth), -@@ -575,10 +638,9 @@ FUNC_NAME(RADEONDisplayTexturedVideo)(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv - VTX_OUT((float)(dstX + dstw), (float)dstY, - xFixedToFloat(srcTopRight.x) / info->texW[0], xFixedToFloat(srcTopRight.y) / info->texH[0]); - -- if (IS_R300_VARIANT || IS_AVIVO_VARIANT) { -- OUT_VIDEO_REG(R300_RB3D_DSTCACHE_CTLSTAT, R300_DC_FLUSH_3D | R300_DC_FREE_3D); -- OUT_VIDEO_REG(RADEON_WAIT_UNTIL, RADEON_WAIT_3D_IDLECLEAN); -- } -+ if (IS_R300_3D || IS_R500_3D) -+ /* flushing is pipelined, free/finish is not */ -+ OUT_VIDEO_REG(R300_RB3D_DSTCACHE_CTLSTAT, R300_DC_FLUSH_3D); - - #ifdef ACCEL_CP - ADVANCE_RING(); -@@ -589,6 +651,14 @@ FUNC_NAME(RADEONDisplayTexturedVideo)(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv - pBox++; - } - -+ if (IS_R300_3D || IS_R500_3D) { -+ BEGIN_VIDEO(2); -+ OUT_VIDEO_REG(R300_RB3D_DSTCACHE_CTLSTAT, R300_RB3D_DC_FLUSH_ALL); -+ } else -+ BEGIN_VIDEO(1); -+ OUT_VIDEO_REG(RADEON_WAIT_UNTIL, RADEON_WAIT_3D_IDLECLEAN); -+ FINISH_VIDEO(); -+ - DamageDamageRegion(pPriv->pDraw, &pPriv->clip); - } - -diff --git a/src/radeon_tv.c b/src/radeon_tv.c -index d5d1e9e..90020b3 100644 ---- a/src/radeon_tv.c -+++ b/src/radeon_tv.c -@@ -34,22 +34,22 @@ - - typedef struct - { -- CARD16 horResolution; -- CARD16 verResolution; -+ uint16_t horResolution; -+ uint16_t verResolution; - TVStd standard; -- CARD16 horTotal; -- CARD16 verTotal; -- CARD16 horStart; -- CARD16 horSyncStart; -- CARD16 verSyncStart; -+ uint16_t horTotal; -+ uint16_t verTotal; -+ uint16_t horStart; -+ uint16_t horSyncStart; -+ uint16_t verSyncStart; - unsigned defRestart; -- CARD16 crtcPLL_N; -- CARD8 crtcPLL_M; -- CARD8 crtcPLL_postDiv; -+ uint16_t crtcPLL_N; -+ uint8_t crtcPLL_M; -+ uint8_t crtcPLL_postDiv; - unsigned pixToTV; - } TVModeConstants; - --static const CARD16 hor_timing_NTSC[] = -+static const uint16_t hor_timing_NTSC[] = - { - 0x0007, - 0x003f, -@@ -71,7 +71,7 @@ static const CARD16 hor_timing_NTSC[] = - 0 - }; - --static const CARD16 vert_timing_NTSC[] = -+static const uint16_t vert_timing_NTSC[] = - { - 0x2001, - 0x200d, -@@ -89,7 +89,7 @@ static const CARD16 vert_timing_NTSC[] = - 0 - }; - --static const CARD16 hor_timing_PAL[] = -+static const uint16_t hor_timing_PAL[] = - { - 0x0007, - 0x0058, -@@ -111,7 +111,7 @@ static const CARD16 hor_timing_PAL[] = - 0 - }; - --static const CARD16 vert_timing_PAL[] = -+static const uint16_t vert_timing_PAL[] = - { - 0x2001, - 0x200c, -@@ -186,7 +186,7 @@ RADEONWaitPLLLock(ScrnInfoPtr pScrn, unsigned nTests, - { - RADEONInfoPtr info = RADEONPTR(pScrn); - unsigned char *RADEONMMIO = info->MMIO; -- CARD32 savePLLTest; -+ uint32_t savePLLTest; - unsigned i; - unsigned j; - -@@ -215,12 +215,12 @@ RADEONWaitPLLLock(ScrnInfoPtr pScrn, unsigned nTests, - - /* Write to TV FIFO RAM */ - static void --RADEONWriteTVFIFO(ScrnInfoPtr pScrn, CARD16 addr, -- CARD32 value) -+RADEONWriteTVFIFO(ScrnInfoPtr pScrn, uint16_t addr, -+ uint32_t value) - { - RADEONInfoPtr info = RADEONPTR(pScrn); - unsigned char *RADEONMMIO = info->MMIO; -- CARD32 tmp; -+ uint32_t tmp; - int i = 0; - - OUTREG(RADEON_TV_HOST_WRITE_DATA, value); -@@ -241,12 +241,12 @@ RADEONWriteTVFIFO(ScrnInfoPtr pScrn, CARD16 addr, - } - - /* Read from TV FIFO RAM */ --static CARD32 --RADEONReadTVFIFO(ScrnInfoPtr pScrn, CARD16 addr) -+static uint32_t -+RADEONReadTVFIFO(ScrnInfoPtr pScrn, uint16_t addr) - { - RADEONInfoPtr info = RADEONPTR(pScrn); - unsigned char *RADEONMMIO = info->MMIO; -- CARD32 tmp; -+ uint32_t tmp; - int i = 0; - - OUTREG(RADEON_TV_HOST_RD_WT_CNTL, addr); -@@ -269,10 +269,10 @@ RADEONReadTVFIFO(ScrnInfoPtr pScrn, CARD16 addr) - /* Get FIFO addresses of horizontal & vertical code timing tables from - * settings of uv_adr register. - */ --static CARD16 --RADEONGetHTimingTablesAddr(CARD32 tv_uv_adr) -+static uint16_t -+RADEONGetHTimingTablesAddr(uint32_t tv_uv_adr) - { -- CARD16 hTable; -+ uint16_t hTable; - - switch ((tv_uv_adr & RADEON_HCODE_TABLE_SEL_MASK) >> RADEON_HCODE_TABLE_SEL_SHIFT) { - case 0: -@@ -292,10 +292,10 @@ RADEONGetHTimingTablesAddr(CARD32 tv_uv_adr) - return hTable; - } - --static CARD16 --RADEONGetVTimingTablesAddr(CARD32 tv_uv_adr) -+static uint16_t -+RADEONGetVTimingTablesAddr(uint32_t tv_uv_adr) - { -- CARD16 vTable; -+ uint16_t vTable; - - switch ((tv_uv_adr & RADEON_VCODE_TABLE_SEL_MASK) >> RADEON_VCODE_TABLE_SEL_SHIFT) { - case 0: -@@ -321,9 +321,9 @@ RADEONRestoreTVTimingTables(ScrnInfoPtr pScrn, RADEONSavePtr restore) - { - RADEONInfoPtr info = RADEONPTR(pScrn); - unsigned char *RADEONMMIO = info->MMIO; -- CARD16 hTable; -- CARD16 vTable; -- CARD32 tmp; -+ uint16_t hTable; -+ uint16_t vTable; -+ uint32_t tmp; - unsigned i; - - OUTREG(RADEON_TV_UV_ADR, restore->tv_uv_adr); -@@ -331,14 +331,14 @@ RADEONRestoreTVTimingTables(ScrnInfoPtr pScrn, RADEONSavePtr restore) - vTable = RADEONGetVTimingTablesAddr(restore->tv_uv_adr); - - for (i = 0; i < MAX_H_CODE_TIMING_LEN; i += 2, hTable--) { -- tmp = ((CARD32)restore->h_code_timing[ i ] << 14) | ((CARD32)restore->h_code_timing[ i + 1 ]); -+ tmp = ((uint32_t)restore->h_code_timing[ i ] << 14) | ((uint32_t)restore->h_code_timing[ i + 1 ]); - RADEONWriteTVFIFO(pScrn, hTable, tmp); - if (restore->h_code_timing[ i ] == 0 || restore->h_code_timing[ i + 1 ] == 0) - break; - } - - for (i = 0; i < MAX_V_CODE_TIMING_LEN; i += 2, vTable++) { -- tmp = ((CARD32)restore->v_code_timing[ i + 1 ] << 14) | ((CARD32)restore->v_code_timing[ i ]); -+ tmp = ((uint32_t)restore->v_code_timing[ i + 1 ] << 14) | ((uint32_t)restore->v_code_timing[ i ]); - RADEONWriteTVFIFO(pScrn, vTable, tmp); - if (restore->v_code_timing[ i ] == 0 || restore->v_code_timing[ i + 1 ] == 0) - break; -@@ -485,9 +485,9 @@ RADEONSaveTVTimingTables(ScrnInfoPtr pScrn, RADEONSavePtr save) - { - RADEONInfoPtr info = RADEONPTR(pScrn); - unsigned char *RADEONMMIO = info->MMIO; -- CARD16 hTable; -- CARD16 vTable; -- CARD32 tmp; -+ uint16_t hTable; -+ uint16_t vTable; -+ uint32_t tmp; - unsigned i; - - save->tv_uv_adr = INREG(RADEON_TV_UV_ADR); -@@ -511,8 +511,8 @@ RADEONSaveTVTimingTables(ScrnInfoPtr pScrn, RADEONSavePtr save) - - for (i = 0; i < MAX_H_CODE_TIMING_LEN; i += 2) { - tmp = RADEONReadTVFIFO(pScrn, hTable--); -- save->h_code_timing[ i ] = (CARD16)((tmp >> 14) & 0x3fff); -- save->h_code_timing[ i + 1 ] = (CARD16)(tmp & 0x3fff); -+ save->h_code_timing[ i ] = (uint16_t)((tmp >> 14) & 0x3fff); -+ save->h_code_timing[ i + 1 ] = (uint16_t)(tmp & 0x3fff); - - if (save->h_code_timing[ i ] == 0 || save->h_code_timing[ i + 1 ] == 0) - break; -@@ -520,8 +520,8 @@ RADEONSaveTVTimingTables(ScrnInfoPtr pScrn, RADEONSavePtr save) - - for (i = 0; i < MAX_V_CODE_TIMING_LEN; i += 2) { - tmp = RADEONReadTVFIFO(pScrn, vTable++); -- save->v_code_timing[ i ] = (CARD16)(tmp & 0x3fff); -- save->v_code_timing[ i + 1 ] = (CARD16)((tmp >> 14) & 0x3fff); -+ save->v_code_timing[ i ] = (uint16_t)(tmp & 0x3fff); -+ save->v_code_timing[ i + 1 ] = (uint16_t)((tmp >> 14) & 0x3fff); - - if (save->v_code_timing[ i ] == 0 || save->v_code_timing[ i + 1 ] == 0) - break; -@@ -588,10 +588,10 @@ static Bool RADEONInitTVRestarts(xf86OutputPtr output, RADEONSavePtr save, - unsigned fTotal; - int vOffset; - int hOffset; -- CARD16 p1; -- CARD16 p2; -+ uint16_t p1; -+ uint16_t p2; - Bool hChanged; -- CARD16 hInc; -+ uint16_t hInc; - const TVModeConstants *constPtr; - - /* FIXME: need to revisit this when we add more modes */ -@@ -629,8 +629,8 @@ static Bool RADEONInitTVRestarts(xf86OutputPtr output, RADEONSavePtr save, - } - - -- p1 = (CARD16)((int)p1 + hOffset); -- p2 = (CARD16)((int)p2 - hOffset); -+ p1 = (uint16_t)((int)p1 + hOffset); -+ p2 = (uint16_t)((int)p2 - hOffset); - - hChanged = (p1 != save->h_code_timing[ H_TABLE_POS1 ] || - p2 != save->h_code_timing[ H_TABLE_POS2 ]); -@@ -675,14 +675,14 @@ static Bool RADEONInitTVRestarts(xf86OutputPtr output, RADEONSavePtr save, - if (radeon_output->tvStd == TV_STD_NTSC || - radeon_output->tvStd == TV_STD_NTSC_J || - radeon_output->tvStd == TV_STD_PAL_M) -- hInc = (CARD16)((int)(constPtr->horResolution * 4096 * NTSC_TV_CLOCK_T) / -+ hInc = (uint16_t)((int)(constPtr->horResolution * 4096 * NTSC_TV_CLOCK_T) / - (radeon_output->hSize * (int)(NTSC_TV_H_SIZE_UNIT) + (int)(NTSC_TV_ZERO_H_SIZE))); - else -- hInc = (CARD16)((int)(constPtr->horResolution * 4096 * PAL_TV_CLOCK_T) / -+ hInc = (uint16_t)((int)(constPtr->horResolution * 4096 * PAL_TV_CLOCK_T) / - (radeon_output->hSize * (int)(PAL_TV_H_SIZE_UNIT) + (int)(PAL_TV_ZERO_H_SIZE))); - - save->tv_timing_cntl = (save->tv_timing_cntl & ~RADEON_H_INC_MASK) | -- ((CARD32)hInc << RADEON_H_INC_SHIFT); -+ ((uint32_t)hInc << RADEON_H_INC_SHIFT); - - ErrorF("computeRestarts: hSize=%d,hInc=%u\n" , radeon_output->hSize , hInc); - -@@ -698,10 +698,10 @@ void RADEONInitTVRegisters(xf86OutputPtr output, RADEONSavePtr save, - RADEONInfoPtr info = RADEONPTR(pScrn); - unsigned i; - unsigned long vert_space, flicker_removal; -- CARD32 tmp; -+ uint32_t tmp; - const TVModeConstants *constPtr; -- const CARD16 *hor_timing; -- const CARD16 *vert_timing; -+ const uint16_t *hor_timing; -+ const uint16_t *vert_timing; - - - /* FIXME: need to revisit this when we add more modes */ -diff --git a/src/radeon_version.h b/src/radeon_version.h -index ccc1367..5717ead 100644 ---- a/src/radeon_version.h -+++ b/src/radeon_version.h -@@ -39,10 +39,9 @@ - #define R200_DRIVER_NAME "r200" - #define R300_DRIVER_NAME "r300" - --#define RADEON_VERSION_MAJOR 4 --#define RADEON_VERSION_MAJOR_TILED 5 --#define RADEON_VERSION_MINOR 3 --#define RADEON_VERSION_PATCH 0 -+#define RADEON_VERSION_MAJOR PACKAGE_VERSION_MAJOR -+#define RADEON_VERSION_MINOR PACKAGE_VERSION_MINOR -+#define RADEON_VERSION_PATCH PACKAGE_VERSION_PATCHLEVEL - - #ifndef RADEON_VERSION_EXTRA - #define RADEON_VERSION_EXTRA "" -diff --git a/src/radeon_video.c b/src/radeon_video.c -index 7502e1e..ac60166 100644 ---- a/src/radeon_video.c -+++ b/src/radeon_video.c -@@ -285,14 +285,22 @@ void RADEONInitVideo(ScreenPtr pScreen) - RADEONInitOffscreenImages(pScreen); - } - -- if (info->ChipFamily != CHIP_FAMILY_RS400) { -- texturedAdaptor = RADEONSetupImageTexturedVideo(pScreen); -- if (texturedAdaptor != NULL) { -- adaptors[num_adaptors++] = texturedAdaptor; -- xf86DrvMsg(pScrn->scrnIndex, X_INFO, "Set up textured video\n"); -+ if (info->ChipFamily != CHIP_FAMILY_RV250) { -+ if ((info->ChipFamily < CHIP_FAMILY_RS400) -+#ifdef XF86DRI -+ || (info->directRenderingEnabled) -+#endif -+ ) { -+ texturedAdaptor = RADEONSetupImageTexturedVideo(pScreen); -+ if (texturedAdaptor != NULL) { -+ adaptors[num_adaptors++] = texturedAdaptor; -+ xf86DrvMsg(pScrn->scrnIndex, X_INFO, "Set up textured video\n"); -+ } else -+ xf86DrvMsg(pScrn->scrnIndex, X_ERROR, "Failed to set up textured video\n"); - } else -- xf86DrvMsg(pScrn->scrnIndex, X_ERROR, "Failed to set up textured video\n"); -- } -+ xf86DrvMsg(pScrn->scrnIndex, X_INFO, "Textured video requires CP on R5xx/IGP\n"); -+ } else -+ xf86DrvMsg(pScrn->scrnIndex, X_INFO, "Textured video disabled on RV250 due to HW bug\n"); - - if(num_adaptors) - xf86XVScreenInit(pScreen, adaptors, num_adaptors); -@@ -550,59 +558,59 @@ static REF_TRANSFORM trans[2] = - /* Gamma curve definition for preset gammas */ - typedef struct tagGAMMA_CURVE_R100 - { -- CARD32 GAMMA_0_F_SLOPE; -- CARD32 GAMMA_0_F_OFFSET; -- CARD32 GAMMA_10_1F_SLOPE; -- CARD32 GAMMA_10_1F_OFFSET; -- CARD32 GAMMA_20_3F_SLOPE; -- CARD32 GAMMA_20_3F_OFFSET; -- CARD32 GAMMA_40_7F_SLOPE; -- CARD32 GAMMA_40_7F_OFFSET; -- CARD32 GAMMA_380_3BF_SLOPE; -- CARD32 GAMMA_380_3BF_OFFSET; -- CARD32 GAMMA_3C0_3FF_SLOPE; -- CARD32 GAMMA_3C0_3FF_OFFSET; -+ uint32_t GAMMA_0_F_SLOPE; -+ uint32_t GAMMA_0_F_OFFSET; -+ uint32_t GAMMA_10_1F_SLOPE; -+ uint32_t GAMMA_10_1F_OFFSET; -+ uint32_t GAMMA_20_3F_SLOPE; -+ uint32_t GAMMA_20_3F_OFFSET; -+ uint32_t GAMMA_40_7F_SLOPE; -+ uint32_t GAMMA_40_7F_OFFSET; -+ uint32_t GAMMA_380_3BF_SLOPE; -+ uint32_t GAMMA_380_3BF_OFFSET; -+ uint32_t GAMMA_3C0_3FF_SLOPE; -+ uint32_t GAMMA_3C0_3FF_OFFSET; - float OvGammaCont; - } GAMMA_CURVE_R100; - - typedef struct tagGAMMA_CURVE_R200 - { -- CARD32 GAMMA_0_F_SLOPE; -- CARD32 GAMMA_0_F_OFFSET; -- CARD32 GAMMA_10_1F_SLOPE; -- CARD32 GAMMA_10_1F_OFFSET; -- CARD32 GAMMA_20_3F_SLOPE; -- CARD32 GAMMA_20_3F_OFFSET; -- CARD32 GAMMA_40_7F_SLOPE; -- CARD32 GAMMA_40_7F_OFFSET; -- CARD32 GAMMA_80_BF_SLOPE; -- CARD32 GAMMA_80_BF_OFFSET; -- CARD32 GAMMA_C0_FF_SLOPE; -- CARD32 GAMMA_C0_FF_OFFSET; -- CARD32 GAMMA_100_13F_SLOPE; -- CARD32 GAMMA_100_13F_OFFSET; -- CARD32 GAMMA_140_17F_SLOPE; -- CARD32 GAMMA_140_17F_OFFSET; -- CARD32 GAMMA_180_1BF_SLOPE; -- CARD32 GAMMA_180_1BF_OFFSET; -- CARD32 GAMMA_1C0_1FF_SLOPE; -- CARD32 GAMMA_1C0_1FF_OFFSET; -- CARD32 GAMMA_200_23F_SLOPE; -- CARD32 GAMMA_200_23F_OFFSET; -- CARD32 GAMMA_240_27F_SLOPE; -- CARD32 GAMMA_240_27F_OFFSET; -- CARD32 GAMMA_280_2BF_SLOPE; -- CARD32 GAMMA_280_2BF_OFFSET; -- CARD32 GAMMA_2C0_2FF_SLOPE; -- CARD32 GAMMA_2C0_2FF_OFFSET; -- CARD32 GAMMA_300_33F_SLOPE; -- CARD32 GAMMA_300_33F_OFFSET; -- CARD32 GAMMA_340_37F_SLOPE; -- CARD32 GAMMA_340_37F_OFFSET; -- CARD32 GAMMA_380_3BF_SLOPE; -- CARD32 GAMMA_380_3BF_OFFSET; -- CARD32 GAMMA_3C0_3FF_SLOPE; -- CARD32 GAMMA_3C0_3FF_OFFSET; -+ uint32_t GAMMA_0_F_SLOPE; -+ uint32_t GAMMA_0_F_OFFSET; -+ uint32_t GAMMA_10_1F_SLOPE; -+ uint32_t GAMMA_10_1F_OFFSET; -+ uint32_t GAMMA_20_3F_SLOPE; -+ uint32_t GAMMA_20_3F_OFFSET; -+ uint32_t GAMMA_40_7F_SLOPE; -+ uint32_t GAMMA_40_7F_OFFSET; -+ uint32_t GAMMA_80_BF_SLOPE; -+ uint32_t GAMMA_80_BF_OFFSET; -+ uint32_t GAMMA_C0_FF_SLOPE; -+ uint32_t GAMMA_C0_FF_OFFSET; -+ uint32_t GAMMA_100_13F_SLOPE; -+ uint32_t GAMMA_100_13F_OFFSET; -+ uint32_t GAMMA_140_17F_SLOPE; -+ uint32_t GAMMA_140_17F_OFFSET; -+ uint32_t GAMMA_180_1BF_SLOPE; -+ uint32_t GAMMA_180_1BF_OFFSET; -+ uint32_t GAMMA_1C0_1FF_SLOPE; -+ uint32_t GAMMA_1C0_1FF_OFFSET; -+ uint32_t GAMMA_200_23F_SLOPE; -+ uint32_t GAMMA_200_23F_OFFSET; -+ uint32_t GAMMA_240_27F_SLOPE; -+ uint32_t GAMMA_240_27F_OFFSET; -+ uint32_t GAMMA_280_2BF_SLOPE; -+ uint32_t GAMMA_280_2BF_OFFSET; -+ uint32_t GAMMA_2C0_2FF_SLOPE; -+ uint32_t GAMMA_2C0_2FF_OFFSET; -+ uint32_t GAMMA_300_33F_SLOPE; -+ uint32_t GAMMA_300_33F_OFFSET; -+ uint32_t GAMMA_340_37F_SLOPE; -+ uint32_t GAMMA_340_37F_OFFSET; -+ uint32_t GAMMA_380_3BF_SLOPE; -+ uint32_t GAMMA_380_3BF_OFFSET; -+ uint32_t GAMMA_3C0_3FF_SLOPE; -+ uint32_t GAMMA_3C0_3FF_OFFSET; - float OvGammaCont; - } GAMMA_CURVE_R200; - -@@ -679,9 +687,9 @@ static GAMMA_CURVE_R100 gamma_curve_r100[8] = - static GAMMA_CURVE_R200 gamma_curve_r200[8] = - { - /* Gamma 1.0 */ -- {0x00000040, 0x00000000, -- 0x00000040, 0x00000020, -- 0x00000080, 0x00000040, -+ {0x00000100, 0x00000000, -+ 0x00000100, 0x00000020, -+ 0x00000100, 0x00000040, - 0x00000100, 0x00000080, - 0x00000100, 0x00000100, - 0x00000100, 0x00000100, -@@ -841,16 +849,18 @@ static GAMMA_CURVE_R200 gamma_curve_r200[8] = - }; - - static void --RADEONSetOverlayGamma(ScrnInfoPtr pScrn, CARD32 gamma) -+RADEONSetOverlayGamma(ScrnInfoPtr pScrn, uint32_t gamma) - { - RADEONInfoPtr info = RADEONPTR(pScrn); - unsigned char *RADEONMMIO = info->MMIO; -- CARD32 ov0_scale_cntl; - - /* Set gamma */ - RADEONWaitForIdleMMIO(pScrn); -- ov0_scale_cntl = INREG(RADEON_OV0_SCALE_CNTL) & ~RADEON_SCALER_GAMMA_SEL_MASK; -- OUTREG(RADEON_OV0_SCALE_CNTL, ov0_scale_cntl | (gamma << 0x00000005)); -+ -+ if (info->ChipFamily < CHIP_FAMILY_R200) { -+ uint32_t ov0_scale_cntl = INREG(RADEON_OV0_SCALE_CNTL) & ~RADEON_SCALER_GAMMA_SEL_MASK; -+ OUTREG(RADEON_OV0_SCALE_CNTL, ov0_scale_cntl | (gamma << 5)); -+ } - - /* Load gamma curve adjustments */ - if (info->ChipFamily >= CHIP_FAMILY_R200) { -@@ -931,6 +941,30 @@ RADEONSetOverlayGamma(ScrnInfoPtr pScrn, CARD32 gamma) - - } - -+static uint32_t -+RADEONTranslateUserGamma(uint32_t user_gamma) -+{ -+ /* translate from user_gamma (gamma x 1000) to radeon gamma table index value */ -+ if (user_gamma <= 925) /* 0.85 */ -+ return 1; -+ else if (user_gamma <= 1050) /* 1.0 */ -+ return 0; -+ else if (user_gamma <= 1150) /* 1.1 */ -+ return 2; -+ else if (user_gamma <= 1325) /* 1.2 */ -+ return 3; -+ else if (user_gamma <= 1575) /* 1.45 */ -+ return 4; -+ else if (user_gamma <= 1950) /* 1.7 */ -+ return 5; -+ else if (user_gamma <= 2350) /* 2.2 */ -+ return 6; -+ else if (user_gamma > 2350) /* 2.5 */ -+ return 7; -+ else -+ return 0; -+} -+ - - /**************************************************************************** - * SetTransform * -@@ -957,8 +991,8 @@ static void RADEONSetTransform (ScrnInfoPtr pScrn, - float red_intensity, - float green_intensity, - float blue_intensity, -- CARD32 ref, -- CARD32 user_gamma) -+ uint32_t ref, -+ uint32_t user_gamma) - { - RADEONInfoPtr info = RADEONPTR(pScrn); - unsigned char *RADEONMMIO = info->MMIO; -@@ -975,32 +1009,17 @@ static void RADEONSetTransform (ScrnInfoPtr pScrn, - float Loff = 64.0; - float Coff = 512.0f; - -- CARD32 dwOvLuma, dwOvROff, dwOvGOff, dwOvBOff; -- CARD32 dwOvRCb, dwOvRCr; -- CARD32 dwOvGCb, dwOvGCr; -- CARD32 dwOvBCb, dwOvBCr; -- CARD32 gamma = 0; -+ uint32_t dwOvLuma, dwOvROff, dwOvGOff, dwOvBOff; -+ uint32_t dwOvRCb, dwOvRCr; -+ uint32_t dwOvGCb, dwOvGCr; -+ uint32_t dwOvBCb, dwOvBCr; -+ uint32_t gamma = 0; - - if (ref >= 2) - return; - - /* translate from user_gamma (gamma x 1000) to radeon gamma table index value */ -- if (user_gamma <= 925) /* 0.85 */ -- gamma = 1; -- else if (user_gamma <= 1050) /* 1.0 */ -- gamma = 0; -- else if (user_gamma <= 1150) /* 1.1 */ -- gamma = 2; -- else if (user_gamma <= 1325) /* 1.2 */ -- gamma = 3; -- else if (user_gamma <= 1575) /* 1.45 */ -- gamma = 4; -- else if (user_gamma <= 1950) /* 1.7 */ -- gamma = 5; -- else if (user_gamma <= 2350) /* 2.2 */ -- gamma = 6; -- else if (user_gamma > 2350) /* 2.5 */ -- gamma = 7; -+ gamma = RADEONTranslateUserGamma(user_gamma); - - if (gamma >= 8) - return; -@@ -1143,16 +1162,16 @@ static void RADEONSetOverlayAlpha(ScrnInfoPtr pScrn, int ov_alpha, int gr_alpha, - /* not yet supported */ - } - --static void RADEONSetColorKey(ScrnInfoPtr pScrn, CARD32 colorKey) -+static void RADEONSetColorKey(ScrnInfoPtr pScrn, uint32_t colorKey) - { - RADEONInfoPtr info = RADEONPTR(pScrn); - unsigned char *RADEONMMIO = info->MMIO; -- CARD32 min, max; -- CARD8 r, g, b; -+ uint32_t min, max; -+ uint8_t r, g, b; - - if (info->CurrentLayout.depth > 8) - { -- CARD32 rbits, gbits, bbits; -+ uint32_t rbits, gbits, bbits; - - rbits = (colorKey & pScrn->mask.red) >> pScrn->offset.red; - gbits = (colorKey & pScrn->mask.green) >> pScrn->offset.green; -@@ -1164,7 +1183,7 @@ static void RADEONSetColorKey(ScrnInfoPtr pScrn, CARD32 colorKey) - } - else - { -- CARD32 bits; -+ uint32_t bits; - - bits = colorKey & ((1 << info->CurrentLayout.depth) - 1); - r = bits; -@@ -1307,7 +1326,7 @@ static void RADEONSetupTheatre(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv) - RADEONPLLPtr pll = &(info->pll); - TheatrePtr t; - -- CARD8 a; -+ uint8_t a; - int i; - - pPriv->theatre = NULL; -@@ -1401,7 +1420,7 @@ RADEONAllocAdaptor(ScrnInfoPtr pScrn) - XF86VideoAdaptorPtr adapt; - RADEONInfoPtr info = RADEONPTR(pScrn); - RADEONPortPrivPtr pPriv; -- CARD32 dot_clock; -+ uint32_t dot_clock; - int ecp; - - if(!(adapt = xf86XVAllocateVideoAdaptorRec(pScrn))) -@@ -2159,22 +2178,22 @@ RADEONCopyData( - unsigned int bpp - ){ - RADEONInfoPtr info = RADEONPTR(pScrn); -+ -+ /* Get the byte-swapping right for big endian systems */ -+ if ( bpp == 2 ) { -+ w *= 2; -+ bpp = 1; -+ } -+ - #ifdef XF86DRI - - if ( info->directRenderingEnabled && info->DMAForXv ) - { -- CARD8 *buf; -- CARD32 bufPitch, dstPitchOff; -+ uint8_t *buf; -+ uint32_t bufPitch, dstPitchOff; - int x, y; - unsigned int hpass; - -- /* Get the byte-swapping right for big endian systems */ -- if ( bpp == 2 ) -- { -- w *= 2; -- bpp = 1; -- } -- - RADEONHostDataParams( pScrn, dst, dstPitch, bpp, &dstPitchOff, &x, &y ); - - while ( (buf = RADEONHostDataBlit( pScrn, bpp, w, dstPitchOff, &bufPitch, -@@ -2235,21 +2254,21 @@ RADEONCopyRGB24Data( - unsigned int h, - unsigned int w - ){ -- CARD32 *dptr; -- CARD8 *sptr; -+ uint32_t *dptr; -+ uint8_t *sptr; - int i,j; - RADEONInfoPtr info = RADEONPTR(pScrn); - #ifdef XF86DRI - - if ( info->directRenderingEnabled && info->DMAForXv ) - { -- CARD32 bufPitch, dstPitchOff; -+ uint32_t bufPitch, dstPitchOff; - int x, y; - unsigned int hpass; - - RADEONHostDataParams( pScrn, dst, dstPitch, 4, &dstPitchOff, &x, &y ); - -- while ( (dptr = ( CARD32* )RADEONHostDataBlit( pScrn, 4, w, dstPitchOff, -+ while ( (dptr = ( uint32_t* )RADEONHostDataBlit( pScrn, 4, w, dstPitchOff, - &bufPitch, x, &y, &h, - &hpass )) ) - { -@@ -2282,7 +2301,7 @@ RADEONCopyRGB24Data( - #endif - - for (j = 0; j < h; j++) { -- dptr = (CARD32 *)(dst + j * dstPitch); -+ dptr = (uint32_t *)(dst + j * dstPitch); - sptr = src + j * srcPitch; - - for (i = 0; i < w; i++, sptr += 3) { -@@ -2333,8 +2352,8 @@ RADEONCopyMungedData( - - if ( info->directRenderingEnabled && info->DMAForXv ) - { -- CARD8 *buf; -- CARD32 y = 0, bufPitch, dstPitchOff; -+ uint8_t *buf; -+ uint32_t y = 0, bufPitch, dstPitchOff; - int blitX, blitY; - unsigned int hpass; - -@@ -2365,8 +2384,8 @@ RADEONCopyMungedData( - else - #endif /* XF86DRI */ - { -- CARD32 *dst; -- CARD8 *s1, *s2, *s3; -+ uint32_t *dst; -+ uint8_t *s1, *s2, *s3; - int i, j; - - #if X_BYTE_ORDER == X_BIG_ENDIAN -@@ -2420,7 +2439,7 @@ RADEONCopyMungedData( - * is measured in bytes, and the offset from the beginning of card space is - * returned. - */ --CARD32 -+uint32_t - RADEONAllocateMemory( - ScrnInfoPtr pScrn, - void **mem_struct, -@@ -2542,7 +2561,7 @@ RADEONDisplayVideo( - RADEONInfoPtr info = RADEONPTR(pScrn); - xf86CrtcConfigPtr xf86_config = XF86_CRTC_CONFIG_PTR(pScrn); - unsigned char *RADEONMMIO = info->MMIO; -- CARD32 v_inc, h_inc, h_inc_uv, step_by_y, step_by_uv, tmp; -+ uint32_t v_inc, h_inc, h_inc_uv, step_by_y, step_by_uv, tmp; - double h_inc_d; - int p1_h_accum_init, p23_h_accum_init; - int p1_v_accum_init, p23_v_accum_init; -@@ -2552,12 +2571,12 @@ RADEONDisplayVideo( - int y_mult; - int x_off; - int y_off; -- CARD32 scaler_src; -- CARD32 dot_clock; -+ uint32_t scaler_src; -+ uint32_t dot_clock; - int is_rgb; - int is_planar; - int i; -- CARD32 scale_cntl; -+ uint32_t scale_cntl; - double dsr; - int tap_set; - int predownscale=0; -@@ -2867,13 +2886,18 @@ RADEONDisplayVideo( - break; - } - -+ if (info->ChipFamily < CHIP_FAMILY_R200) { -+ scale_cntl &= ~RADEON_SCALER_GAMMA_SEL_MASK; -+ scale_cntl |= ((RADEONTranslateUserGamma(pPriv->gamma)) << 5); -+ } -+ - OUTREG(RADEON_OV0_SCALE_CNTL, scale_cntl); - OUTREG(RADEON_OV0_REG_LOAD_CNTL, 0); - } - - - static void --RADEONFillKeyHelper(DrawablePtr pDraw, CARD32 colorKey, RegionPtr clipBoxes) -+RADEONFillKeyHelper(DrawablePtr pDraw, uint32_t colorKey, RegionPtr clipBoxes) - { - #if HAVE_XV_DRAWABLE_HELPER - xf86XVFillKeyHelperDrawable(pDraw, colorKey, clipBoxes); -@@ -2906,7 +2930,7 @@ RADEONPutImage( - int top, left, npixels, nlines, bpp; - int idconv = id; - BoxRec dstBox; -- CARD32 tmp; -+ uint32_t tmp; - xf86CrtcPtr crtc; - - /* -@@ -2979,7 +3003,8 @@ RADEONPutImage( - case FOURCC_I420: - /* it seems rs4xx chips (all of them???) either can't handle planar - yuv at all or would need some unknown different setup. */ -- if (info->ChipFamily != CHIP_FAMILY_RS400) { -+ if ((info->ChipFamily != CHIP_FAMILY_RS400) && -+ (info->ChipFamily != CHIP_FAMILY_RS480)) { - /* need 16bytes alignment for u,v plane, so 2 times that for width - but blitter needs 64bytes alignment. 128byte is a waste but dstpitch - for uv planes needs to be dstpitch yplane >> 1 for now. */ -@@ -3462,7 +3487,7 @@ RADEONPutVideo( - int srcPitch, srcPitch2, dstPitch; - int bpp; - BoxRec dstBox; -- CARD32 id, display_base; -+ uint32_t id, display_base; - int width, height; - int mult; - int vbi_line_width, vbi_start, vbi_end; -diff --git a/src/radeon_video.h b/src/radeon_video.h -index f897e07..096de37 100644 ---- a/src/radeon_video.h -+++ b/src/radeon_video.h -@@ -15,8 +15,8 @@ - - /* Xvideo port struct */ - typedef struct { -- CARD32 transform_index; -- CARD32 gamma; /* gamma value x 1000 */ -+ uint32_t transform_index; -+ uint32_t gamma; /* gamma value x 1000 */ - int brightness; - int saturation; - int hue; -@@ -32,17 +32,17 @@ typedef struct { - - /* i2c bus and devices */ - I2CBusPtr i2c; -- CARD32 radeon_i2c_timing; -- CARD32 radeon_M; -- CARD32 radeon_N; -- CARD32 i2c_status; -- CARD32 i2c_cntl; -+ uint32_t radeon_i2c_timing; -+ uint32_t radeon_M; -+ uint32_t radeon_N; -+ uint32_t i2c_status; -+ uint32_t i2c_cntl; - - FI1236Ptr fi1236; -- CARD8 tuner_type; -+ uint8_t tuner_type; - MSP3430Ptr msp3430; - TDA9885Ptr tda9885; -- UDA1380Ptr uda1380; -+ UDA1380Ptr uda1380; - - /* VIP bus and devices */ - GENERIC_BUS_Ptr VIP; -@@ -50,12 +50,12 @@ typedef struct { - - Bool video_stream_active; - int encoding; -- CARD32 frequency; -+ uint32_t frequency; - int volume; - Bool mute; - int sap_channel; - int v; -- CARD32 adjustment; /* general purpose variable */ -+ uint32_t adjustment; /* general purpose variable */ - - #define METHOD_BOB 0 - #define METHOD_SINGLE 1 -@@ -74,14 +74,14 @@ typedef struct { - Bool doubleBuffer; - unsigned char currentBuffer; - RegionRec clip; -- CARD32 colorKey; -- CARD32 videoStatus; -+ uint32_t colorKey; -+ uint32_t videoStatus; - Time offTime; - Time freeTime; - Bool autopaint_colorkey; - xf86CrtcPtr desired_crtc; - -- int size; -+ int size; - #ifdef USE_EXA - ExaOffscreenArea *off_screen; - #endif -@@ -96,9 +96,9 @@ typedef struct { - DrawablePtr pDraw; - PixmapPtr pPixmap; - -- CARD32 src_offset; -- CARD32 src_pitch; -- CARD8 *src_addr; -+ uint32_t src_offset; -+ uint32_t src_pitch; -+ uint8_t *src_addr; - - int id; - int src_w, src_h, dst_w, dst_h; -@@ -113,7 +113,7 @@ void RADEONResetI2C(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv); - void RADEONVIP_init(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv); - void RADEONVIP_reset(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv); - --CARD32 -+uint32_t - RADEONAllocateMemory(ScrnInfoPtr pScrn, void **mem_struct, int size); - void - RADEONFreeMemory(ScrnInfoPtr pScrn, void *mem_struct); -diff --git a/src/radeon_vip.c b/src/radeon_vip.c -index 7ee4ab5..05b90f1 100644 ---- a/src/radeon_vip.c -+++ b/src/radeon_vip.c -@@ -46,13 +46,13 @@ static Bool RADEONVIP_ioctl(GENERIC_BUS_Ptr b, long ioctl, long arg1, char *arg2 - } - } - --static CARD32 RADEONVIP_idle(GENERIC_BUS_Ptr b) -+static uint32_t RADEONVIP_idle(GENERIC_BUS_Ptr b) - { - ScrnInfoPtr pScrn = xf86Screens[b->scrnIndex]; - RADEONInfoPtr info = RADEONPTR(pScrn); - unsigned char *RADEONMMIO = info->MMIO; - -- CARD32 timeout; -+ uint32_t timeout; - - RADEONWaitForIdleMMIO(pScrn); - timeout = INREG(RADEON_VIPH_TIMEOUT_STAT); -@@ -67,13 +67,13 @@ static CARD32 RADEONVIP_idle(GENERIC_BUS_Ptr b) - return (INREG(RADEON_VIPH_CONTROL) & 0x2000) ? VIP_BUSY : VIP_IDLE ; - } - --static CARD32 RADEONVIP_fifo_idle(GENERIC_BUS_Ptr b, CARD8 channel) -+static uint32_t RADEONVIP_fifo_idle(GENERIC_BUS_Ptr b, uint8_t channel) - { - ScrnInfoPtr pScrn = xf86Screens[b->scrnIndex]; - RADEONInfoPtr info = RADEONPTR(pScrn); - unsigned char *RADEONMMIO = info->MMIO; - -- CARD32 timeout; -+ uint32_t timeout; - - RADEONWaitForIdleMMIO(pScrn); - timeout = INREG(VIPH_TIMEOUT_STAT); -@@ -105,12 +105,12 @@ static CARD32 RADEONVIP_fifo_idle(GENERIC_BUS_Ptr b, CARD8 channel) - } \ - } - --static Bool RADEONVIP_read(GENERIC_BUS_Ptr b, CARD32 address, CARD32 count, CARD8 *buffer) -+static Bool RADEONVIP_read(GENERIC_BUS_Ptr b, uint32_t address, uint32_t count, uint8_t *buffer) - { - ScrnInfoPtr pScrn = xf86Screens[b->scrnIndex]; - RADEONInfoPtr info = RADEONPTR(pScrn); - unsigned char *RADEONMMIO = info->MMIO; -- CARD32 status,tmp; -+ uint32_t status,tmp; - - if((count!=1) && (count!=2) && (count!=4)) - { -@@ -152,13 +152,13 @@ static Bool RADEONVIP_read(GENERIC_BUS_Ptr b, CARD32 address, CARD32 count, CARD - RADEONWaitForIdleMMIO(pScrn); - switch(count){ - case 1: -- *buffer=(CARD8)(INREG(RADEON_VIPH_REG_DATA) & 0xff); -+ *buffer=(uint8_t)(INREG(RADEON_VIPH_REG_DATA) & 0xff); - break; - case 2: -- *(CARD16 *)buffer=(CARD16) (INREG(RADEON_VIPH_REG_DATA) & 0xffff); -+ *(uint16_t *)buffer=(uint16_t) (INREG(RADEON_VIPH_REG_DATA) & 0xffff); - break; - case 4: -- *(CARD32 *)buffer=(CARD32) ( INREG(RADEON_VIPH_REG_DATA) & 0xffffffff); -+ *(uint32_t *)buffer=(uint32_t) ( INREG(RADEON_VIPH_REG_DATA) & 0xffffffff); - break; - } - VIP_WAIT_FOR_IDLE(); -@@ -171,12 +171,12 @@ static Bool RADEONVIP_read(GENERIC_BUS_Ptr b, CARD32 address, CARD32 count, CARD - return TRUE; - } - --static Bool RADEONVIP_fifo_read(GENERIC_BUS_Ptr b, CARD32 address, CARD32 count, CARD8 *buffer) -+static Bool RADEONVIP_fifo_read(GENERIC_BUS_Ptr b, uint32_t address, uint32_t count, uint8_t *buffer) - { - ScrnInfoPtr pScrn = xf86Screens[b->scrnIndex]; - RADEONInfoPtr info = RADEONPTR(pScrn); - unsigned char *RADEONMMIO = info->MMIO; -- CARD32 status,tmp; -+ uint32_t status,tmp; - - if(count!=1) - { -@@ -222,13 +222,13 @@ static Bool RADEONVIP_fifo_read(GENERIC_BUS_Ptr b, CARD32 address, CARD32 count, - RADEONWaitForIdleMMIO(pScrn); - switch(count){ - case 1: -- *buffer=(CARD8)(INREG(VIPH_REG_DATA) & 0xff); -+ *buffer=(uint8_t)(INREG(VIPH_REG_DATA) & 0xff); - break; - case 2: -- *(CARD16 *)buffer=(CARD16) (INREG(VIPH_REG_DATA) & 0xffff); -+ *(uint16_t *)buffer=(uint16_t) (INREG(VIPH_REG_DATA) & 0xffff); - break; - case 4: -- *(CARD32 *)buffer=(CARD32) ( INREG(VIPH_REG_DATA) & 0xffffffff); -+ *(uint32_t *)buffer=(uint32_t) ( INREG(VIPH_REG_DATA) & 0xffffffff); - break; - } - while(VIP_BUSY == (status = RADEONVIP_fifo_idle(b, 0xff))); -@@ -245,13 +245,13 @@ static Bool RADEONVIP_fifo_read(GENERIC_BUS_Ptr b, CARD32 address, CARD32 count, - } - - --static Bool RADEONVIP_write(GENERIC_BUS_Ptr b, CARD32 address, CARD32 count, CARD8 *buffer) -+static Bool RADEONVIP_write(GENERIC_BUS_Ptr b, uint32_t address, uint32_t count, uint8_t *buffer) - { - ScrnInfoPtr pScrn = xf86Screens[b->scrnIndex]; - RADEONInfoPtr info = RADEONPTR(pScrn); - unsigned char *RADEONMMIO = info->MMIO; - -- CARD32 status; -+ uint32_t status; - - - if((count!=4)) -@@ -269,7 +269,7 @@ static Bool RADEONVIP_write(GENERIC_BUS_Ptr b, CARD32 address, CARD32 count, CAR - RADEONWaitForFifo(pScrn, 2); - switch(count){ - case 4: -- OUTREG(RADEON_VIPH_REG_DATA, *(CARD32 *)buffer); -+ OUTREG(RADEON_VIPH_REG_DATA, *(uint32_t *)buffer); - break; - } - write_mem_barrier(); -@@ -278,14 +278,14 @@ static Bool RADEONVIP_write(GENERIC_BUS_Ptr b, CARD32 address, CARD32 count, CAR - return TRUE; - } - --static Bool RADEONVIP_fifo_write(GENERIC_BUS_Ptr b, CARD32 address, CARD32 count, CARD8 *buffer) -+static Bool RADEONVIP_fifo_write(GENERIC_BUS_Ptr b, uint32_t address, uint32_t count, uint8_t *buffer) - { - ScrnInfoPtr pScrn = xf86Screens[b->scrnIndex]; - RADEONInfoPtr info = RADEONPTR(pScrn); - unsigned char *RADEONMMIO = info->MMIO; - -- CARD32 status; -- CARD32 i; -+ uint32_t status; -+ uint32_t i; - - RADEONWaitForFifo(pScrn, 2); - OUTREG(VIPH_REG_ADDR, (address & (~0x2000)) | 0x1000); -@@ -300,7 +300,7 @@ static Bool RADEONVIP_fifo_write(GENERIC_BUS_Ptr b, CARD32 address, CARD32 count - RADEONWaitForFifo(pScrn, 2); - for (i = 0; i < count; i+=4) - { -- OUTREG(VIPH_REG_DATA, *(CARD32*)(buffer + i)); -+ OUTREG(VIPH_REG_DATA, *(uint32_t*)(buffer + i)); - write_mem_barrier(); - while(VIP_BUSY == (status = RADEONVIP_fifo_idle(b, 0x0f))); - if(VIP_IDLE != status) -diff --git a/src/theatre.c b/src/theatre.c -index a5aadfb..ad055c5 100644 ---- a/src/theatre.c -+++ b/src/theatre.c -@@ -12,29 +12,31 @@ - #undef write - #undef ioctl - --static Bool theatre_read(TheatrePtr t,CARD32 reg, CARD32 *data) -+static Bool theatre_read(TheatrePtr t,uint32_t reg, uint32_t *data) - { - if(t->theatre_num<0)return FALSE; -- return t->VIP->read(t->VIP, ((t->theatre_num & 0x3)<<14) | reg,4, (CARD8 *) data); -+ return t->VIP->read(t->VIP, ((t->theatre_num & 0x3)<<14) | reg,4, (uint8_t *) data); - } - --static Bool theatre_write(TheatrePtr t,CARD32 reg, CARD32 data) -+static Bool theatre_write(TheatrePtr t,uint32_t reg, uint32_t data) - { - if(t->theatre_num<0)return FALSE; -- return t->VIP->write(t->VIP,((t->theatre_num & 0x03)<<14) | reg,4, (CARD8 *) &data); -+ return t->VIP->write(t->VIP,((t->theatre_num & 0x03)<<14) | reg,4, (uint8_t *) &data); - } - - #define RT_regr(reg,data) theatre_read(t,(reg),(data)) - #define RT_regw(reg,data) theatre_write(t,(reg),(data)) - #define VIP_TYPE "ATI VIP BUS" - -+static void CalculateCrCbGain (TheatrePtr t, double *CrGain, double *CbGain, uint16_t wStandard); -+static void RT_SetCombFilter (TheatrePtr t, uint16_t wStandard, uint16_t wConnector); - - #if 0 - TheatrePtr DetectTheatre(GENERIC_BUS_Ptr b) - { - TheatrePtr t; -- CARD32 i; -- CARD32 val; -+ uint32_t i; -+ uint32_t val; - char s[20]; - - b->ioctl(b,GB_IOCTL_GET_TYPE,20,s); -@@ -49,10 +51,10 @@ TheatrePtr DetectTheatre(GENERIC_BUS_Ptr b) - t->theatre_num = -1; - t->mode=MODE_UNINITIALIZED; - -- b->read(b, VIP_VIP_VENDOR_DEVICE_ID, 4, (CARD8 *)&val); -+ b->read(b, VIP_VIP_VENDOR_DEVICE_ID, 4, (uint8_t *)&val); - for(i=0;i<4;i++) - { -- if(b->read(b, ((i & 0x03)<<14) | VIP_VIP_VENDOR_DEVICE_ID, 4, (CARD8 *)&val)) -+ if(b->read(b, ((i & 0x03)<<14) | VIP_VIP_VENDOR_DEVICE_ID, 4, (uint8_t *)&val)) - { - if(val)xf86DrvMsg(b->scrnIndex, X_INFO, "Device %d on VIP bus ids as 0x%08x\n",i,val); - if(t->theatre_num>=0)continue; /* already found one instance */ -@@ -171,7 +173,7 @@ fld_V_INT_LENGTH, - fld_CRDR_ACTIVE_GAIN, - fld_CBDB_ACTIVE_GAIN, - fld_DVS_DIRECTION, --fld_DVS_VBI_CARD8_SWAP, -+fld_DVS_VBI_UINT8_SWAP, - fld_DVS_CLK_SELECT, - fld_CONTINUOUS_STREAM, - fld_DVSOUT_CLK_DRV, -@@ -253,17 +255,17 @@ regRT_MAX_REGS - - - typedef struct { -- CARD8 size; -- CARD32 fld_id; -- CARD32 dwRegAddrLSBs; -- CARD32 dwFldOffsetLSBs; -- CARD32 dwMaskLSBs; -- CARD32 addr2; -- CARD32 offs2; -- CARD32 mask2; -- CARD32 dwCurrValue; -- CARD32 rw; -- } RTREGMAP; -+ uint8_t size; -+ uint32_t fld_id; -+ uint32_t dwRegAddrLSBs; -+ uint32_t dwFldOffsetLSBs; -+ uint32_t dwMaskLSBs; -+ uint32_t addr2; -+ uint32_t offs2; -+ uint32_t mask2; -+ uint32_t dwCurrValue; -+ uint32_t rw; -+} RTREGMAP; - - #define READONLY 1 - #define WRITEONLY 2 -@@ -350,7 +352,7 @@ RTREGMAP RT_RegMap[regRT_MAX_REGS]={ - {10 ,fld_CRDR_ACTIVE_GAIN ,VIP_CP_ACTIVE_GAIN , 0, 0xFFFFFC00, 0, 0,0, fld_CRDR_ACTIVE_GAIN_def ,READWRITE }, - {10 ,fld_CBDB_ACTIVE_GAIN ,VIP_CP_ACTIVE_GAIN , 16, 0xFC00FFFF, 0, 0,0, fld_CBDB_ACTIVE_GAIN_def ,READWRITE }, - {1 ,fld_DVS_DIRECTION ,VIP_DVS_PORT_CTRL , 0, 0xFFFFFFFE, 0, 0,0, fld_DVS_DIRECTION_def ,READWRITE }, --{1 ,fld_DVS_VBI_CARD8_SWAP ,VIP_DVS_PORT_CTRL , 1, 0xFFFFFFFD, 0, 0,0, fld_DVS_VBI_CARD8_SWAP_def ,READWRITE }, -+{1 ,fld_DVS_VBI_UINT8_SWAP ,VIP_DVS_PORT_CTRL , 1, 0xFFFFFFFD, 0, 0,0, fld_DVS_VBI_UINT8_SWAP_def ,READWRITE }, - {1 ,fld_DVS_CLK_SELECT ,VIP_DVS_PORT_CTRL , 2, 0xFFFFFFFB, 0, 0,0, fld_DVS_CLK_SELECT_def ,READWRITE }, - {1 ,fld_CONTINUOUS_STREAM ,VIP_DVS_PORT_CTRL , 3, 0xFFFFFFF7, 0, 0,0, fld_CONTINUOUS_STREAM_def ,READWRITE }, - {1 ,fld_DVSOUT_CLK_DRV ,VIP_DVS_PORT_CTRL , 4, 0xFFFFFFEF, 0, 0,0, fld_DVSOUT_CLK_DRV_def ,READWRITE }, -@@ -429,7 +431,7 @@ RTREGMAP RT_RegMap[regRT_MAX_REGS]={ - }; - - /* Rage Theatre's register fields default values: */ --CARD32 RT_RegDef[regRT_MAX_REGS]= -+uint32_t RT_RegDef[regRT_MAX_REGS]= - { - fld_tmpReg1_def, - fld_tmpReg2_def, -@@ -507,7 +509,7 @@ fld_V_INT_LENGTH_def, - fld_CRDR_ACTIVE_GAIN_def, - fld_CBDB_ACTIVE_GAIN_def, - fld_DVS_DIRECTION_def, --fld_DVS_VBI_CARD8_SWAP_def, -+fld_DVS_VBI_UINT8_SWAP_def, - fld_DVS_CLK_SELECT_def, - fld_CONTINUOUS_STREAM_def, - fld_DVSOUT_CLK_DRV_def, -@@ -586,16 +588,16 @@ fld_GPIO_6_OUT_def, - }; - - /**************************************************************************** -- * WriteRT_fld (CARD32 dwReg, CARD32 dwData) * -+ * WriteRT_fld (uint32_t dwReg, uint32_t dwData) * - * Function: Writes a register field within Rage Theatre * -- * Inputs: CARD32 dwReg = register field to be written * -- * CARD32 dwData = data that will be written to the reg field * -+ * Inputs: uint32_t dwReg = register field to be written * -+ * uint32_t dwData = data that will be written to the reg field * - * Outputs: NONE * - ****************************************************************************/ --static void WriteRT_fld1 (TheatrePtr t, CARD32 dwReg, CARD32 dwData) -+static void WriteRT_fld1 (TheatrePtr t, uint32_t dwReg, uint32_t dwData) - { -- CARD32 dwResult=0; -- CARD32 dwValue=0; -+ uint32_t dwResult=0; -+ uint32_t dwValue=0; - - if (RT_regr (RT_RegMap[dwReg].dwRegAddrLSBs, &dwResult) == TRUE) - { -@@ -615,14 +617,14 @@ static void WriteRT_fld1 (TheatrePtr t, CARD32 dwReg, CARD32 dwData) - } /* WriteRT_fld ()... */ - - /**************************************************************************** -- * ReadRT_fld (CARD32 dwReg) * -+ * ReadRT_fld (uint32_t dwReg) * - * Function: Reads a register field within Rage Theatre * -- * Inputs: CARD32 dwReg = register field to be read * -- * Outputs: CARD32 - value read from register field * -+ * Inputs: uint32_t dwReg = register field to be read * -+ * Outputs: uint32_t - value read from register field * - ****************************************************************************/ --static CARD32 ReadRT_fld1 (TheatrePtr t,CARD32 dwReg) -+static uint32_t ReadRT_fld1 (TheatrePtr t,uint32_t dwReg) - { -- CARD32 dwResult=0; -+ uint32_t dwResult=0; - - if (RT_regr (RT_RegMap[dwReg].dwRegAddrLSBs, &dwResult) == TRUE) - { -@@ -641,15 +643,15 @@ static CARD32 ReadRT_fld1 (TheatrePtr t,CARD32 dwReg) - #define ReadRT_fld(a) ReadRT_fld1(t,(a)) - - /**************************************************************************** -- * RT_SetVINClock (CARD16 wStandard) * -+ * RT_SetVINClock (uint16_t wStandard) * - * Function: to set the VIN clock for the selected standard * -- * Inputs: CARD16 wStandard - input standard (NTSC, PAL, SECAM) * -+ * Inputs: uint16_t wStandard - input standard (NTSC, PAL, SECAM) * - * Outputs: NONE * - ****************************************************************************/ --static void RT_SetVINClock(TheatrePtr t, CARD16 wStandard) -+static void RT_SetVINClock(TheatrePtr t, uint16_t wStandard) - { -- CARD32 dwM0=0, dwN0=0, dwP=0; -- CARD8 ref_freq; -+ uint32_t dwM0=0, dwN0=0, dwP=0; -+ uint8_t ref_freq; - - /* Determine the reference frequency first. This can be obtained - from the MMTABLE.video_decoder_type field (bits 4:7) -@@ -657,9 +659,9 @@ static void RT_SetVINClock(TheatrePtr t, CARD16 wStandard) - 27 or 29.49 MHz. */ - /* - R128ReadBIOS(0x48, -- (CARD8 *)&bios_header, sizeof(bios_header)); -+ (uint8_t *)&bios_header, sizeof(bios_header)); - R128ReadBIOS(bios_header + 0x30, -- (CARD8 *)&pll_info_block, sizeof(pll_info_block)); -+ (uint8_t *)&pll_info_block, sizeof(pll_info_block)); - - R128ReadBIOS(pll_info_block+0x07, &video_decoder_type, sizeof(video_decoder_type)); - */ -@@ -793,9 +795,9 @@ static void RT_SetVINClock(TheatrePtr t, CARD16 wStandard) - * Inputs: int hue - the hue value to be set. * - * Outputs: NONE * - ****************************************************************************/ --void RT_SetTint (TheatrePtr t, int hue) -+_X_EXPORT void RT_SetTint (TheatrePtr t, int hue) - { -- CARD32 nhue = 0; -+ uint32_t nhue = 0; - - t->iHue=hue; - /* Scale hue value from -1000<->1000 to -180<->180 */ -@@ -822,11 +824,11 @@ void RT_SetTint (TheatrePtr t, int hue) - case (DEC_SECAM): - if (hue >= 0) - { -- nhue = (CARD32) (256 * hue)/360; -+ nhue = (uint32_t) (256 * hue)/360; - } - else - { -- nhue = (CARD32) (256 * (hue + 360))/360; -+ nhue = (uint32_t) (256 * (hue + 360))/360; - } - break; - -@@ -846,9 +848,9 @@ void RT_SetTint (TheatrePtr t, int hue) - * Inputs: int Saturation - the saturation value to be set. * - * Outputs: NONE * - ****************************************************************************/ --void RT_SetSaturation (TheatrePtr t, int Saturation) -+_X_EXPORT void RT_SetSaturation (TheatrePtr t, int Saturation) - { -- CARD16 wSaturation_V, wSaturation_U; -+ uint16_t wSaturation_V, wSaturation_U; - double dbSaturation = 0, dbCrGain = 0, dbCbGain = 0; - - /* VALIDATE SATURATION LEVEL */ -@@ -873,8 +875,8 @@ void RT_SetSaturation (TheatrePtr t, int Saturation) - - CalculateCrCbGain (t, &dbCrGain, &dbCbGain, t->wStandard); - -- wSaturation_U = (CARD16) ((dbCrGain * dbSaturation * 128.0) + 0.5); -- wSaturation_V = (CARD16) ((dbCbGain * dbSaturation * 128.0) + 0.5); -+ wSaturation_U = (uint16_t) ((dbCrGain * dbSaturation * 128.0) + 0.5); -+ wSaturation_V = (uint16_t) ((dbCbGain * dbSaturation * 128.0) + 0.5); - - /* SET SATURATION LEVEL */ - WriteRT_fld (fld_CRDR_ACTIVE_GAIN, wSaturation_U); -@@ -893,14 +895,14 @@ void RT_SetSaturation (TheatrePtr t, int Saturation) - * Inputs: int Brightness - the brightness value to be set. * - * Outputs: NONE * - ****************************************************************************/ --void RT_SetBrightness (TheatrePtr t, int Brightness) -+_X_EXPORT void RT_SetBrightness (TheatrePtr t, int Brightness) - { - double dbSynctipRef0=0, dbContrast=1; - - double dbYgain=0; - double dbBrightness=0; - double dbSetup=0; -- CARD16 wBrightness=0; -+ uint16_t wBrightness=0; - - /* VALIDATE BRIGHTNESS LEVEL */ - if (Brightness < -1000) -@@ -950,7 +952,7 @@ void RT_SetBrightness (TheatrePtr t, int Brightness) - break; - } - -- wBrightness = (CARD16) (16.0 * ((dbBrightness-dbSetup) + (16.0 / (dbContrast * dbYgain)))); -+ wBrightness = (uint16_t) (16.0 * ((dbBrightness-dbSetup) + (16.0 / (dbContrast * dbYgain)))); - - WriteRT_fld (fld_LP_BRIGHTNESS, wBrightness); - -@@ -962,12 +964,12 @@ void RT_SetBrightness (TheatrePtr t, int Brightness) - - - /**************************************************************************** -- * RT_SetSharpness (CARD16 wSharpness) * -+ * RT_SetSharpness (uint16_t wSharpness) * - * Function: sets the sharpness level for the Rage Theatre video in * -- * Inputs: CARD16 wSharpness - the sharpness value to be set. * -+ * Inputs: uint16_t wSharpness - the sharpness value to be set. * - * Outputs: NONE * - ****************************************************************************/ --void RT_SetSharpness (TheatrePtr t, CARD16 wSharpness) -+_X_EXPORT void RT_SetSharpness (TheatrePtr t, uint16_t wSharpness) - { - switch (wSharpness) - { -@@ -993,11 +995,11 @@ void RT_SetSharpness (TheatrePtr t, CARD16 wSharpness) - * Inputs: int Contrast - the contrast value to be set. * - * Outputs: NONE * - ****************************************************************************/ --void RT_SetContrast (TheatrePtr t, int Contrast) -+_X_EXPORT void RT_SetContrast (TheatrePtr t, int Contrast) - { - double dbSynctipRef0=0, dbContrast=0; - double dbYgain=0; -- CARD8 bTempContrast=0; -+ uint8_t bTempContrast=0; - - /* VALIDATE CONTRAST LEVEL */ - if (Contrast < -1000) -@@ -1035,9 +1037,9 @@ void RT_SetContrast (TheatrePtr t, int Contrast) - break; - } - -- bTempContrast = (CARD8) ((dbContrast * dbYgain * 64) + 0.5); -+ bTempContrast = (uint8_t) ((dbContrast * dbYgain * 64) + 0.5); - -- WriteRT_fld (fld_LP_CONTRAST, (CARD32)bTempContrast); -+ WriteRT_fld (fld_LP_CONTRAST, (uint32_t)bTempContrast); - - /* Save value for future modification */ - t->dbContrast = dbContrast; -@@ -1047,23 +1049,23 @@ void RT_SetContrast (TheatrePtr t, int Contrast) - } /* RT_SetContrast ()... */ - - /**************************************************************************** -- * RT_SetInterlace (CARD8 bInterlace) * -+ * RT_SetInterlace (uint8_t bInterlace) * - * Function: to set the interlacing pattern for the Rage Theatre video in * -- * Inputs: CARD8 bInterlace * -+ * Inputs: uint8_t bInterlace * - * Outputs: NONE * - ****************************************************************************/ --void RT_SetInterlace (TheatrePtr t, CARD8 bInterlace) -+_X_EXPORT void RT_SetInterlace (TheatrePtr t, uint8_t bInterlace) - { - - switch(bInterlace) - { - case (TRUE): /*DEC_INTERLACE */ - WriteRT_fld (fld_V_DEINTERLACE_ON, 0x1); -- t->wInterlaced = (CARD16) RT_DECINTERLACED; -+ t->wInterlaced = (uint16_t) RT_DECINTERLACED; - break; - case (FALSE): /*DEC_NONINTERLACE */ - WriteRT_fld (fld_V_DEINTERLACE_ON, RT_DECNONINTERLACED); -- t->wInterlaced = (CARD16) RT_DECNONINTERLACED; -+ t->wInterlaced = (uint16_t) RT_DECNONINTERLACED; - break; - default: - break; -@@ -1075,16 +1077,16 @@ void RT_SetInterlace (TheatrePtr t, CARD8 bInterlace) - - /**************************************************************************** - * GetStandardConstants (double *LPeriod, double *FPeriod, * -- * double *Fsamp, CARD16 wStandard) * -+ * double *Fsamp, uint16_t wStandard) * - * Function: return timing values for a given standard * - * Inputs: double *LPeriod - - * double *FPeriod - - * double *Fsamp - sampling frequency used for a given standard * -- * CARD16 wStandard - input standard (NTSC, PAL, SECAM) * -+ * uint16_t wStandard - input standard (NTSC, PAL, SECAM) * - * Outputs: NONE * - ****************************************************************************/ - static void GetStandardConstants (double *LPeriod, double *FPeriod, -- double *Fsamp, CARD16 wStandard) -+ double *Fsamp, uint16_t wStandard) - { - *LPeriod = 0.0; - *FPeriod = 0.0; -@@ -1137,15 +1139,15 @@ static void GetStandardConstants (double *LPeriod, double *FPeriod, - - - /**************************************************************************** -- * RT_SetStandard (CARD16 wStandard) * -+ * RT_SetStandard (uint16_t wStandard) * - * Function: to set the input standard for the Rage Theatre video in * -- * Inputs: CARD16 wStandard - input standard (NTSC, PAL, SECAM) * -+ * Inputs: uint16_t wStandard - input standard (NTSC, PAL, SECAM) * - * Outputs: NONE * - ****************************************************************************/ --void RT_SetStandard (TheatrePtr t, CARD16 wStandard) -+_X_EXPORT void RT_SetStandard (TheatrePtr t, uint16_t wStandard) - { - double dbFsamp=0, dbLPeriod=0, dbFPeriod=0; -- CARD16 wFrameTotal = 0; -+ uint16_t wFrameTotal = 0; - double dbSPPeriod = 4.70; - - xf86DrvMsg(t->VIP->scrnIndex,X_INFO,"Rage Theatre setting standard 0x%04x\n", -@@ -1155,7 +1157,7 @@ void RT_SetStandard (TheatrePtr t, CARD16 wStandard) - /* Get the constants for the given standard. */ - GetStandardConstants (&dbLPeriod, &dbFPeriod, &dbFsamp, wStandard); - -- wFrameTotal = (CARD16) (((2.0 * dbFPeriod) * 1000 / dbLPeriod) + 0.5); -+ wFrameTotal = (uint16_t) (((2.0 * dbFPeriod) * 1000 / dbLPeriod) + 0.5); - - /* Procedures before setting the standards: */ - WriteRT_fld (fld_VIN_CLK_SEL, RT_REF_CLK); -@@ -1207,10 +1209,10 @@ void RT_SetStandard (TheatrePtr t, CARD16 wStandard) - WriteRT_fld (fld_V_VBI_WIND_START, RT_NTSCM_V_VBI_WIND_START); - WriteRT_fld (fld_V_VBI_WIND_END, RT_NTSCM_V_VBI_WIND_END); - -- WriteRT_fld (fld_UV_INT_START, (CARD8)((0.10 * dbLPeriod * dbFsamp / 2.0) + 0.5 - 32)); -+ WriteRT_fld (fld_UV_INT_START, (uint8_t)((0.10 * dbLPeriod * dbFsamp / 2.0) + 0.5 - 32)); - -- WriteRT_fld (fld_VSYNC_INT_TRIGGER , (CARD16) RT_NTSCM_VSYNC_INT_TRIGGER); -- WriteRT_fld (fld_VSYNC_INT_HOLD, (CARD16) RT_NTSCM_VSYNC_INT_HOLD); -+ WriteRT_fld (fld_VSYNC_INT_TRIGGER , (uint16_t) RT_NTSCM_VSYNC_INT_TRIGGER); -+ WriteRT_fld (fld_VSYNC_INT_HOLD, (uint16_t) RT_NTSCM_VSYNC_INT_HOLD); - - switch (wStandard & 0xFF00) - { -@@ -1283,7 +1285,7 @@ void RT_SetStandard (TheatrePtr t, CARD16 wStandard) - - WriteRT_fld (fld_VERT_LOCKOUT_START, RT_PAL_VERT_LOCKOUT_START); - WriteRT_fld (fld_VERT_LOCKOUT_END, RT_PAL_VERT_LOCKOUT_END); -- WriteRT_fld (fld_VS_FIELD_BLANK_START, (CARD16)RT_PALSEM_VS_FIELD_BLANK_START); -+ WriteRT_fld (fld_VS_FIELD_BLANK_START, (uint16_t)RT_PALSEM_VS_FIELD_BLANK_START); - - WriteRT_fld (fld_VS_FIELD_BLANK_END, RT_PAL_VS_FIELD_BLANK_END); - -@@ -1300,11 +1302,11 @@ void RT_SetStandard (TheatrePtr t, CARD16 wStandard) - WriteRT_fld (fld_V_VBI_WIND_END, RT_PAL_V_VBI_WIND_END); - - /* Magic 0.10 is correct - according to Ivo. Also see SECAM code below */ --/* WriteRT_fld (fld_UV_INT_START, (CARD8)( (0.12 * dbLPeriod * dbFsamp / 2.0) + 0.5 - 32 )); */ -- WriteRT_fld (fld_UV_INT_START, (CARD8)( (0.10 * dbLPeriod * dbFsamp / 2.0) + 0.5 - 32 )); -+/* WriteRT_fld (fld_UV_INT_START, (uint8_t)( (0.12 * dbLPeriod * dbFsamp / 2.0) + 0.5 - 32 )); */ -+ WriteRT_fld (fld_UV_INT_START, (uint8_t)( (0.10 * dbLPeriod * dbFsamp / 2.0) + 0.5 - 32 )); - -- WriteRT_fld (fld_VSYNC_INT_TRIGGER , (CARD16) RT_PALSEM_VSYNC_INT_TRIGGER); -- WriteRT_fld (fld_VSYNC_INT_HOLD, (CARD16) RT_PALSEM_VSYNC_INT_HOLD); -+ WriteRT_fld (fld_VSYNC_INT_TRIGGER , (uint16_t) RT_PALSEM_VSYNC_INT_TRIGGER); -+ WriteRT_fld (fld_VSYNC_INT_HOLD, (uint16_t) RT_PALSEM_VSYNC_INT_HOLD); - - break; - case (DEC_SECAM): /*PAL GROUP*/ -@@ -1343,7 +1345,7 @@ void RT_SetStandard (TheatrePtr t, CARD16 wStandard) - WriteRT_fld (fld_VERT_LOCKOUT_START, RT_SECAM_VERT_LOCKOUT_START); /*Might not need */ - WriteRT_fld (fld_VERT_LOCKOUT_END, RT_SECAM_VERT_LOCKOUT_END); /* Might not need */ - -- WriteRT_fld (fld_VS_FIELD_BLANK_START, (CARD16)RT_PALSEM_VS_FIELD_BLANK_START); -+ WriteRT_fld (fld_VS_FIELD_BLANK_START, (uint16_t)RT_PALSEM_VS_FIELD_BLANK_START); - WriteRT_fld (fld_VS_FIELD_BLANK_END, RT_PAL_VS_FIELD_BLANK_END); - - WriteRT_fld (fld_H_ACTIVE_START, RT_PAL_H_ACTIVE_START); -@@ -1358,11 +1360,11 @@ void RT_SetStandard (TheatrePtr t, CARD16 wStandard) - WriteRT_fld (fld_V_VBI_WIND_START, RT_PAL_V_VBI_WIND_START); - WriteRT_fld (fld_V_VBI_WIND_END, RT_PAL_V_VBI_WIND_END); - -- WriteRT_fld (fld_VSYNC_INT_TRIGGER , (CARD16) RT_PALSEM_VSYNC_INT_TRIGGER); -- WriteRT_fld (fld_VSYNC_INT_HOLD, (CARD16) RT_PALSEM_VSYNC_INT_HOLD); -+ WriteRT_fld (fld_VSYNC_INT_TRIGGER , (uint16_t) RT_PALSEM_VSYNC_INT_TRIGGER); -+ WriteRT_fld (fld_VSYNC_INT_HOLD, (uint16_t) RT_PALSEM_VSYNC_INT_HOLD); - --/* WriteRT_fld (fld_UV_INT_START, (CARD8)( (0.12 * dbLPeriod * dbFsamp / 2.0) + 0.5 - 32 )); */ -- WriteRT_fld (fld_UV_INT_START, (CARD8)( (0.10 * dbLPeriod * dbFsamp / 2.0) + 0.5 - 32 )); -+/* WriteRT_fld (fld_UV_INT_START, (uint8_t)( (0.12 * dbLPeriod * dbFsamp / 2.0) + 0.5 - 32 )); */ -+ WriteRT_fld (fld_UV_INT_START, (uint8_t)( (0.10 * dbLPeriod * dbFsamp / 2.0) + 0.5 - 32 )); - - break; - default: -@@ -1381,37 +1383,37 @@ void RT_SetStandard (TheatrePtr t, CARD16 wStandard) - } - - /* Set the following values according to the formulas */ -- WriteRT_fld (fld_HS_LINE_TOTAL, (CARD16)((dbLPeriod * dbFsamp / 2.0) +0.5)); -+ WriteRT_fld (fld_HS_LINE_TOTAL, (uint16_t)((dbLPeriod * dbFsamp / 2.0) +0.5)); - /* According to Ivo PAL/SECAM needs different treatment */ - switch(wStandard & 0x00FF) - { - case DEC_PAL: - case DEC_SECAM: -- WriteRT_fld (fld_MIN_PULSE_WIDTH, (CARD8)(0.5 * dbSPPeriod * dbFsamp/2.0)); -- WriteRT_fld (fld_MAX_PULSE_WIDTH, (CARD8)(1.5 * dbSPPeriod * dbFsamp/2.0)); -- WriteRT_fld (fld_WIN_OPEN_LIMIT, (CARD16)(((dbLPeriod * dbFsamp / 4.0) + 0.5) - 16)); -- WriteRT_fld (fld_WIN_CLOSE_LIMIT, (CARD16)(2.39 * dbSPPeriod * dbFsamp / 2.0)); -- /* WriteRT_fld (fld_VS_FIELD_IDLOCATION, (CARD16)RT_PAL_FIELD_IDLOCATION); */ -+ WriteRT_fld (fld_MIN_PULSE_WIDTH, (uint8_t)(0.5 * dbSPPeriod * dbFsamp/2.0)); -+ WriteRT_fld (fld_MAX_PULSE_WIDTH, (uint8_t)(1.5 * dbSPPeriod * dbFsamp/2.0)); -+ WriteRT_fld (fld_WIN_OPEN_LIMIT, (uint16_t)(((dbLPeriod * dbFsamp / 4.0) + 0.5) - 16)); -+ WriteRT_fld (fld_WIN_CLOSE_LIMIT, (uint16_t)(2.39 * dbSPPeriod * dbFsamp / 2.0)); -+ /* WriteRT_fld (fld_VS_FIELD_IDLOCATION, (uint16_t)RT_PAL_FIELD_IDLOCATION); */ - /* According to docs the following value will work right, though the resulting stream deviates - slightly from CCIR..., in particular the value that was before will do nuts to VCRs in - pause/rewind state. */ -- WriteRT_fld (fld_VS_FIELD_IDLOCATION, (CARD16)0x01); -+ WriteRT_fld (fld_VS_FIELD_IDLOCATION, (uint16_t)0x01); - WriteRT_fld (fld_HS_PLL_SGAIN, 2); - break; - case DEC_NTSC: -- WriteRT_fld (fld_MIN_PULSE_WIDTH, (CARD8)(0.75 * dbSPPeriod * dbFsamp/2.0)); -- WriteRT_fld (fld_MAX_PULSE_WIDTH, (CARD8)(1.25 * dbSPPeriod * dbFsamp/2.0)); -- WriteRT_fld (fld_WIN_OPEN_LIMIT, (CARD16)(((dbLPeriod * dbFsamp / 4.0) + 0.5) - 16)); -- WriteRT_fld (fld_WIN_CLOSE_LIMIT, (CARD16)(1.15 * dbSPPeriod * dbFsamp / 2.0)); -- /* WriteRT_fld (fld_VS_FIELD_IDLOCATION, (CARD16)fld_VS_FIELD_IDLOCATION_def);*/ -+ WriteRT_fld (fld_MIN_PULSE_WIDTH, (uint8_t)(0.75 * dbSPPeriod * dbFsamp/2.0)); -+ WriteRT_fld (fld_MAX_PULSE_WIDTH, (uint8_t)(1.25 * dbSPPeriod * dbFsamp/2.0)); -+ WriteRT_fld (fld_WIN_OPEN_LIMIT, (uint16_t)(((dbLPeriod * dbFsamp / 4.0) + 0.5) - 16)); -+ WriteRT_fld (fld_WIN_CLOSE_LIMIT, (uint16_t)(1.15 * dbSPPeriod * dbFsamp / 2.0)); -+ /* WriteRT_fld (fld_VS_FIELD_IDLOCATION, (uint16_t)fld_VS_FIELD_IDLOCATION_def);*/ - /* I think the default value was the same as the one here.. does not hurt to hardcode it */ -- WriteRT_fld (fld_VS_FIELD_IDLOCATION, (CARD16)0x01); -+ WriteRT_fld (fld_VS_FIELD_IDLOCATION, (uint16_t)0x01); - - } - -- WriteRT_fld (fld_VS_FRAME_TOTAL, (CARD16)(wFrameTotal) + 10); -- WriteRT_fld (fld_BLACK_INT_START, (CARD8)((0.09 * dbLPeriod * dbFsamp / 2.0) - 32 )); -- WriteRT_fld (fld_SYNC_TIP_START, (CARD16)((dbLPeriod * dbFsamp / 2.0 + 0.5) - 28 )); -+ WriteRT_fld (fld_VS_FRAME_TOTAL, (uint16_t)(wFrameTotal) + 10); -+ WriteRT_fld (fld_BLACK_INT_START, (uint8_t)((0.09 * dbLPeriod * dbFsamp / 2.0) - 32 )); -+ WriteRT_fld (fld_SYNC_TIP_START, (uint16_t)((dbLPeriod * dbFsamp / 2.0 + 0.5) - 28 )); - - return; - -@@ -1420,19 +1422,19 @@ void RT_SetStandard (TheatrePtr t, CARD16 wStandard) - - - /**************************************************************************** -- * RT_SetCombFilter (CARD16 wStandard, CARD16 wConnector) * -+ * RT_SetCombFilter (uint16_t wStandard, uint16_t wConnector) * - * Function: sets the input comb filter based on the standard and * - * connector being used (composite vs. svideo) * -- * Inputs: CARD16 wStandard - input standard (NTSC, PAL, SECAM) * -- * CARD16 wConnector - COMPOSITE, SVIDEO * -+ * Inputs: uint16_t wStandard - input standard (NTSC, PAL, SECAM) * -+ * uint16_t wConnector - COMPOSITE, SVIDEO * - * Outputs: NONE * - ****************************************************************************/ --void RT_SetCombFilter (TheatrePtr t, CARD16 wStandard, CARD16 wConnector) -+static void RT_SetCombFilter (TheatrePtr t, uint16_t wStandard, uint16_t wConnector) - { -- CARD32 dwComb_Cntl0=0; -- CARD32 dwComb_Cntl1=0; -- CARD32 dwComb_Cntl2=0; -- CARD32 dwComb_Line_Length=0; -+ uint32_t dwComb_Cntl0=0; -+ uint32_t dwComb_Cntl1=0; -+ uint32_t dwComb_Cntl2=0; -+ uint32_t dwComb_Line_Length=0; - - switch (wConnector) - { -@@ -1558,28 +1560,28 @@ void RT_SetCombFilter (TheatrePtr t, CARD16 wStandard, CARD16 wConnector) - - - /**************************************************************************** -- * RT_SetOutputVideoSize (CARD16 wHorzSize, CARD16 wVertSize, * -- * CARD8 fCC_On, CARD8 fVBICap_On) * -+ * RT_SetOutputVideoSize (uint16_t wHorzSize, uint16_t wVertSize, * -+ * uint8_t fCC_On, uint8_t fVBICap_On) * - * Function: sets the output video size for the Rage Theatre video in * -- * Inputs: CARD16 wHorzSize - width of output in pixels * -- * CARD16 wVertSize - height of output in pixels (lines) * -- * CARD8 fCC_On - enable CC output * -- * CARD8 fVBI_Cap_On - enable VBI capture * -+ * Inputs: uint16_t wHorzSize - width of output in pixels * -+ * uint16_t wVertSize - height of output in pixels (lines) * -+ * uint8_t fCC_On - enable CC output * -+ * uint8_t fVBI_Cap_On - enable VBI capture * - * Outputs: NONE * - ****************************************************************************/ --void RT_SetOutputVideoSize (TheatrePtr t, CARD16 wHorzSize, CARD16 wVertSize, CARD8 fCC_On, CARD8 fVBICap_On) -+_X_EXPORT void RT_SetOutputVideoSize (TheatrePtr t, uint16_t wHorzSize, uint16_t wVertSize, uint8_t fCC_On, uint8_t fVBICap_On) - { -- CARD32 dwHwinStart=0; -- CARD32 dwHScaleRatio=0; -- CARD32 dwHActiveLength=0; -- CARD32 dwVwinStart=0; -- CARD32 dwVScaleRatio=0; -- CARD32 dwVActiveLength=0; -- CARD32 dwTempRatio=0; -- CARD32 dwEvenFieldOffset=0; -- CARD32 dwOddFieldOffset=0; -- CARD32 dwXin=0; -- CARD32 dwYin=0; -+ uint32_t dwHwinStart=0; -+ uint32_t dwHScaleRatio=0; -+ uint32_t dwHActiveLength=0; -+ uint32_t dwVwinStart=0; -+ uint32_t dwVScaleRatio=0; -+ uint32_t dwVActiveLength=0; -+ uint32_t dwTempRatio=0; -+ uint32_t dwEvenFieldOffset=0; -+ uint32_t dwOddFieldOffset=0; -+ uint32_t dwXin=0; -+ uint32_t dwYin=0; - - if (fVBICap_On) - { -@@ -1626,21 +1628,21 @@ void RT_SetOutputVideoSize (TheatrePtr t, CARD16 wHorzSize, CARD16 wVertSize, CA - dwHwinStart = RT_NTSCM_H_IN_START; - dwXin = (ReadRT_fld (fld_H_ACTIVE_END) - ReadRT_fld (fld_H_ACTIVE_START)); /*tempscaler*/ - dwXin = RT_NTSC_H_ACTIVE_SIZE; -- dwHScaleRatio = (CARD32) ((long) dwXin * 65536L / wHorzSize); -+ dwHScaleRatio = (uint32_t) ((long) dwXin * 65536L / wHorzSize); - dwHScaleRatio = dwHScaleRatio & 0x001FFFFF; /*21 bit number;*/ - dwHActiveLength = wHorzSize; - break; - case (DEC_PAL): - dwHwinStart = RT_PAL_H_IN_START; - dwXin = RT_PAL_H_ACTIVE_SIZE; -- dwHScaleRatio = (CARD32) ((long) dwXin * 65536L / wHorzSize); -+ dwHScaleRatio = (uint32_t) ((long) dwXin * 65536L / wHorzSize); - dwHScaleRatio = dwHScaleRatio & 0x001FFFFF; /*21 bit number;*/ - dwHActiveLength = wHorzSize; - break; - case (DEC_SECAM): - dwHwinStart = RT_SECAM_H_IN_START; - dwXin = RT_SECAM_H_ACTIVE_SIZE; -- dwHScaleRatio = (CARD32) ((long) dwXin * 65536L / wHorzSize); -+ dwHScaleRatio = (uint32_t) ((long) dwXin * 65536L / wHorzSize); - dwHScaleRatio = dwHScaleRatio & 0x001FFFFF; /*21 bit number;*/ - dwHActiveLength = wHorzSize; - break; -@@ -1655,24 +1657,24 @@ void RT_SetOutputVideoSize (TheatrePtr t, CARD16 wHorzSize, CARD16 wVertSize, CA - dwVwinStart = RT_NTSCM_V_IN_START; - /* dwYin = (ReadRT_fld (fld_V_ACTIVE_END) - ReadRT_fld (fld_V_ACTIVE_START)); */ /*tempscaler*/ - dwYin = RT_NTSCM_V_ACTIVE_SIZE; -- dwTempRatio = (CARD32)((long) wVertSize / dwYin); -- dwVScaleRatio = (CARD32)((long)wVertSize * 2048L / dwYin); -+ dwTempRatio = (uint32_t)((long) wVertSize / dwYin); -+ dwVScaleRatio = (uint32_t)((long)wVertSize * 2048L / dwYin); - dwVScaleRatio = dwVScaleRatio & 0x00000FFF; - dwVActiveLength = wVertSize/2; - break; - case (DEC_PAL): - dwVwinStart = RT_PAL_V_IN_START; - dwYin = RT_PAL_V_ACTIVE_SIZE; -- dwTempRatio = (CARD32)(wVertSize/dwYin); -- dwVScaleRatio = (CARD32)((long)wVertSize * 2048L / dwYin); -+ dwTempRatio = (uint32_t)(wVertSize/dwYin); -+ dwVScaleRatio = (uint32_t)((long)wVertSize * 2048L / dwYin); - dwVScaleRatio = dwVScaleRatio & 0x00000FFF; - dwVActiveLength = wVertSize/2; - break; - case (DEC_SECAM): - dwVwinStart = RT_SECAM_V_IN_START; - dwYin = RT_SECAM_V_ACTIVE_SIZE; -- dwTempRatio = (CARD32) (wVertSize / dwYin); -- dwVScaleRatio = (CARD32) ((long) wVertSize * 2048L / dwYin); -+ dwTempRatio = (uint32_t) (wVertSize / dwYin); -+ dwVScaleRatio = (uint32_t) ((long) wVertSize * 2048L / dwYin); - dwVScaleRatio = dwVScaleRatio & 0x00000FFF; - dwVActiveLength = wVertSize/2; - break; -@@ -1683,14 +1685,14 @@ void RT_SetOutputVideoSize (TheatrePtr t, CARD16 wHorzSize, CARD16 wVertSize, CA - /*4. Set up offset based on if interlaced or not:*/ - if (t->wInterlaced == RT_DECINTERLACED) - { -- dwEvenFieldOffset = (CARD32) ((1.0 - ((double) wVertSize / (double) dwYin)) * 512.0); -+ dwEvenFieldOffset = (uint32_t) ((1.0 - ((double) wVertSize / (double) dwYin)) * 512.0); - dwOddFieldOffset = dwEvenFieldOffset; - WriteRT_fld (fld_V_DEINTERLACE_ON, 0x1); - } - else - { -- dwEvenFieldOffset = (CARD32)(dwTempRatio * 512.0); -- dwOddFieldOffset = (CARD32)(2048 - dwEvenFieldOffset); -+ dwEvenFieldOffset = (uint32_t)(dwTempRatio * 512.0); -+ dwOddFieldOffset = (uint32_t)(2048 - dwEvenFieldOffset); - WriteRT_fld (fld_V_DEINTERLACE_ON, 0x0); - } - -@@ -1716,14 +1718,14 @@ void RT_SetOutputVideoSize (TheatrePtr t, CARD16 wHorzSize, CARD16 wVertSize, CA - - - /**************************************************************************** -- * CalculateCrCbGain (double *CrGain, double *CbGain, CARD16 wStandard) * -+ * CalculateCrCbGain (double *CrGain, double *CbGain, uint16_t wStandard) * - * Function: * - * Inputs: double *CrGain - - * double *CbGain - -- * CARD16 wStandard - input standard (NTSC, PAL, SECAM) * -+ * uint16_t wStandard - input standard (NTSC, PAL, SECAM) * - * Outputs: NONE * - ****************************************************************************/ --void CalculateCrCbGain (TheatrePtr t, double *CrGain, double *CbGain, CARD16 wStandard) -+static void CalculateCrCbGain (TheatrePtr t, double *CrGain, double *CbGain, uint16_t wStandard) - { - #define UVFLTGAIN 1.5 - #define FRMAX 280000.0 -@@ -1773,15 +1775,15 @@ void CalculateCrCbGain (TheatrePtr t, double *CrGain, double *CbGain, CARD16 wSt - - - /**************************************************************************** -- * RT_SetConnector (CARD16 wStandard, int tunerFlag) * -+ * RT_SetConnector (uint16_t wStandard, int tunerFlag) * - * Function: -- * Inputs: CARD16 wStandard - input standard (NTSC, PAL, SECAM) * -+ * Inputs: uint16_t wStandard - input standard (NTSC, PAL, SECAM) * - * int tunerFlag - * Outputs: NONE * - ****************************************************************************/ --void RT_SetConnector (TheatrePtr t, CARD16 wConnector, int tunerFlag) -+void RT_SetConnector (TheatrePtr t, uint16_t wConnector, int tunerFlag) - { -- CARD32 dwTempContrast=0; -+ uint32_t dwTempContrast=0; - int i; - long counter; - -@@ -1864,9 +1866,9 @@ void RT_SetConnector (TheatrePtr t, CARD16 wConnector, int tunerFlag) - } /* RT_SetConnector ()...*/ - - --void InitTheatre(TheatrePtr t) -+_X_EXPORT void InitTheatre(TheatrePtr t) - { -- CARD32 data; -+ uint32_t data; - - - /* 0 reset Rage Theatre */ -@@ -1929,7 +1931,7 @@ void InitTheatre(TheatrePtr t) - } - - --void ShutdownTheatre(TheatrePtr t) -+_X_EXPORT void ShutdownTheatre(TheatrePtr t) - { - WriteRT_fld (fld_VIN_ASYNC_RST, RT_ASYNC_DISABLE); - WriteRT_fld (fld_VINRST , RT_VINRST_RESET); -@@ -1938,10 +1940,10 @@ void ShutdownTheatre(TheatrePtr t) - t->mode=MODE_UNINITIALIZED; - } - --void DumpRageTheatreRegs(TheatrePtr t) -+_X_EXPORT void DumpRageTheatreRegs(TheatrePtr t) - { - int i; -- CARD32 data; -+ uint32_t data; - - for(i=0;i<0x900;i+=4) - { -@@ -1955,7 +1957,7 @@ void DumpRageTheatreRegs(TheatrePtr t) - void DumpRageTheatreRegsByName(TheatrePtr t) - { - int i; -- CARD32 data; -+ uint32_t data; - struct { char *name; long addr; } rt_reg_list[]={ - { "ADC_CNTL ", 0x0400 }, - { "ADC_DEBUG ", 0x0404 }, -@@ -2159,7 +2161,7 @@ void DumpRageTheatreRegsByName(TheatrePtr t) - - } - --void ResetTheatreRegsForNoTVout(TheatrePtr t) -+_X_EXPORT void ResetTheatreRegsForNoTVout(TheatrePtr t) - { - RT_regw(VIP_CLKOUT_CNTL, 0x0); - RT_regw(VIP_HCOUNT, 0x0); -@@ -2173,7 +2175,7 @@ void ResetTheatreRegsForNoTVout(TheatrePtr t) - } - - --void ResetTheatreRegsForTVout(TheatrePtr t) -+_X_EXPORT void ResetTheatreRegsForTVout(TheatrePtr t) - { - /* RT_regw(VIP_HW_DEBUG, 0x200); */ - /* RT_regw(VIP_INT_CNTL, 0x0); -diff --git a/src/theatre.h b/src/theatre.h -index 958b443..c70a0e0 100644 ---- a/src/theatre.h -+++ b/src/theatre.h -@@ -8,72 +8,64 @@ - typedef struct { - GENERIC_BUS_Ptr VIP; - -- int theatre_num; -- CARD32 theatre_id; -- int mode; -- char* microc_path; -- char* microc_type; -+ int theatre_num; -+ uint32_t theatre_id; -+ int mode; -+ char* microc_path; -+ char* microc_type; - -- CARD16 video_decoder_type; -- CARD32 wStandard; -- CARD32 wConnector; -- int iHue; -- int iSaturation; -- CARD32 wSaturation_U; -- CARD32 wSaturation_V; -- int iBrightness; -- int dbBrightnessRatio; -- CARD32 wSharpness; -- int iContrast; -- int dbContrast; -- CARD32 wInterlaced; -- CARD32 wTunerConnector; -- CARD32 wComp0Connector; -- CARD32 wSVideo0Connector; -- CARD32 dwHorzScalingRatio; -- CARD32 dwVertScalingRatio; -+ uint16_t video_decoder_type; -+ uint32_t wStandard; -+ uint32_t wConnector; -+ int iHue; -+ int iSaturation; -+ uint32_t wSaturation_U; -+ uint32_t wSaturation_V; -+ int iBrightness; -+ int dbBrightnessRatio; -+ uint32_t wSharpness; -+ int iContrast; -+ int dbContrast; -+ uint32_t wInterlaced; -+ uint32_t wTunerConnector; -+ uint32_t wComp0Connector; -+ uint32_t wSVideo0Connector; -+ uint32_t dwHorzScalingRatio; -+ uint32_t dwVertScalingRatio; - - } TheatreRec, * TheatrePtr; - --/* DO NOT FORGET to setup constants before calling InitTheatre */ --void InitTheatre(TheatrePtr t); -- --void RT_SetTint (TheatrePtr t, int hue); --void RT_SetSaturation (TheatrePtr t, int Saturation); --void RT_SetBrightness (TheatrePtr t, int Brightness); --void RT_SetSharpness (TheatrePtr t, CARD16 wSharpness); --void RT_SetContrast (TheatrePtr t, int Contrast); --void RT_SetInterlace (TheatrePtr t, CARD8 bInterlace); --void RT_SetStandard (TheatrePtr t, CARD16 wStandard); --void RT_SetCombFilter (TheatrePtr t, CARD16 wStandard, CARD16 wConnector); --void RT_SetOutputVideoSize (TheatrePtr t, CARD16 wHorzSize, CARD16 wVertSize, CARD8 fCC_On, CARD8 fVBICap_On); --void CalculateCrCbGain (TheatrePtr t, double *CrGain, double *CbGain, CARD16 wStandard); --void RT_SetConnector (TheatrePtr t, CARD16 wConnector, int tunerFlag); -- --void RageTheatreDebugGain(TheatrePtr t, Bool on, CARD32 gain); --void ShutdownTheatre(TheatrePtr t); --void DumpRageTheatreRegs(TheatrePtr t); --void ResetTheatreRegsForTVout(TheatrePtr t); --void ResetTheatreRegsForNoTVout(TheatrePtr t); -- - --#define xf86_InitTheatre ((void (*)(TheatrePtr t))LoaderSymbol("InitTheatre")) -- --#define xf86_RT_SetTint ((void (*)(TheatrePtr, int))LoaderSymbol("RT_SetTint")) --#define xf86_RT_SetSaturation ((void (*)(TheatrePtr, int))LoaderSymbol("RT_SetSaturation")) --#define xf86_RT_SetBrightness ((void (*)(TheatrePtr, int))LoaderSymbol("RT_SetBrightness")) --#define xf86_RT_SetSharpness ((void (*)(TheatrePtr, CARD16))LoaderSymbol("RT_SetSharpness")) --#define xf86_RT_SetContrast ((void (*)(TheatrePtr, int))LoaderSymbol("RT_SetContrast")) --#define xf86_RT_SetInterlace ((void (*)(TheatrePtr, CARD8))LoaderSymbol("RT_SetInterlace")) --#define xf86_RT_SetStandard ((void (*)(TheatrePtr, CARD16))LoaderSymbol("RT_SetStandard")) --#define xf86_RT_SetOutputVideoSize ((void (*)(TheatrePtr, CARD16, CARD16, CARD8, CARD8))LoaderSymbol("RT_SetOutputVideoSize")) --#define xf86_RT_SetConnector ((void (*)(TheatrePtr, CARD16, int))LoaderSymbol("RT_SetConnector")) -- --#define xf86_RageTheatreDebugGain ((void (*)(TheatrePtr, Bool, CARD32))LoaderSymbol("RageTheatreDebugGain")) --#define xf86_ShutdownTheatre ((void (*)(TheatrePtr))LoaderSymbol("ShutdownTheatre")) --#define xf86_DumpRageTheatreRegs ((void (*)(TheatrePtr))LoaderSymbol("DumpRageTheatreRegs")) --#define xf86_ResetTheatreRegsForTVout ((void (*)(TheatrePtr))LoaderSymbol("ResetTheatreRegsForTVout")) --#define xf86_ResetTheatreRegsForNoTVout ((void (*)(TheatrePtr))LoaderSymbol("ResetTheatreRegsForNoTVout")) --#define xf86_RT_GetSignalStatus ((void (*)(TheatrePtr))LoaderSymbol("xf86_RT_GetSignalStatus")) -+/* DO NOT FORGET to setup constants before calling InitTheatre */ -+#define xf86_InitTheatre InitTheatre -+_X_EXPORT void InitTheatre(TheatrePtr t); -+#define xf86_RT_SetTint RT_SetTint -+_X_EXPORT void RT_SetTint (TheatrePtr t, int hue); -+#define xf86_RT_SetSaturation RT_SetSaturation -+_X_EXPORT void RT_SetSaturation (TheatrePtr t, int Saturation); -+#define xf86_RT_SetBrightness RT_SetBrightness -+_X_EXPORT void RT_SetBrightness (TheatrePtr t, int Brightness); -+#define xf86_RT_SetSharpness RT_SetSharpness -+_X_EXPORT void RT_SetSharpness (TheatrePtr t, uint16_t wSharpness); -+#define xf86_RT_SetContrast RT_SetContrast -+_X_EXPORT void RT_SetContrast (TheatrePtr t, int Contrast); -+#define xf86_RT_SetInterlace RT_SetInterlace -+_X_EXPORT void RT_SetInterlace (TheatrePtr t, uint8_t bInterlace); -+#define xf86_RT_SetStandard RT_SetStandard -+_X_EXPORT void RT_SetStandard (TheatrePtr t, uint16_t wStandard); -+#define xf86_RT_SetOutputVideoSize RT_SetOutputVideoSize -+_X_EXPORT void RT_SetOutputVideoSize (TheatrePtr t, uint16_t wHorzSize, uint16_t wVertSize, uint8_t fCC_On, uint8_t fVBICap_On); -+#define xf86_RT_SetConnector RT_SetConnector -+_X_EXPORT void RT_SetConnector (TheatrePtr t, uint16_t wConnector, int tunerFlag); -+#define xf86_ResetTheatreRegsForNoTVout ResetTheatreRegsForNoTVout -+_X_EXPORT void ResetTheatreRegsForNoTVout(TheatrePtr t); -+#define xf86_ResetTheatreRegsForTVout ResetTheatreRegsForTVout -+_X_EXPORT void ResetTheatreRegsForTVout(TheatrePtr t); -+#define xf86_DumpRageTheatreRegs DumpRageTheatreRegs -+_X_EXPORT void DumpRageTheatreRegs(TheatrePtr t); -+#define xf86_DumpRageTheatreRegsByName DumpRageTheatreRegsByName -+_X_EXPORT void DumpRageTheatreRegsByName(TheatrePtr t); -+#define xf86_ShutdownTheatre ShutdownTheatre -+_X_EXPORT void ShutdownTheatre(TheatrePtr t); - - #endif -diff --git a/src/theatre200.c b/src/theatre200.c -index 672f01e..c150ed4 100644 ---- a/src/theatre200.c -+++ b/src/theatre200.c -@@ -71,51 +71,51 @@ static void microc_clean(struct rt200_microc_data* microc_datap, int screen); - static int dsp_init(TheatrePtr t, struct rt200_microc_data* microc_datap); - static int dsp_load(TheatrePtr t, struct rt200_microc_data* microc_datap); - --static CARD32 dsp_send_command(TheatrePtr t, CARD32 fb_scratch1, CARD32 fb_scratch0); --static CARD32 dsp_set_video_input_connector(TheatrePtr t, CARD32 connector); --//static CARD32 dsp_reset(TheatrePtr t); --static CARD32 dsp_set_lowpowerstate(TheatrePtr t, CARD32 pstate); --static CARD32 dsp_set_video_standard(TheatrePtr t, CARD32 standard); --static CARD32 dsp_set_videostreamformat(TheatrePtr t, CARD32 format); --static CARD32 dsp_video_standard_detection(TheatrePtr t); --//static CARD32 dsp_get_signallockstatus(TheatrePtr t); --//static CARD32 dsp_get_signallinenumber(TheatrePtr t); -- --static CARD32 dsp_set_brightness(TheatrePtr t, CARD8 brightness); --static CARD32 dsp_set_contrast(TheatrePtr t, CARD8 contrast); --//static CARD32 dsp_set_sharpness(TheatrePtr t, int sharpness); --static CARD32 dsp_set_tint(TheatrePtr t, CARD8 tint); --static CARD32 dsp_set_saturation(TheatrePtr t, CARD8 saturation); --static CARD32 dsp_set_video_scaler_horizontal(TheatrePtr t, CARD16 output_width, CARD16 horz_start, CARD16 horz_end); --static CARD32 dsp_set_video_scaler_vertical(TheatrePtr t, CARD16 output_height, CARD16 vert_start, CARD16 vert_end); --static CARD32 dsp_audio_mute(TheatrePtr t, CARD8 left, CARD8 right); --static CARD32 dsp_set_audio_volume(TheatrePtr t, CARD8 left, CARD8 right, CARD8 auto_mute); --//static CARD32 dsp_audio_detection(TheatrePtr t, CARD8 option); --static CARD32 dsp_configure_i2s_port(TheatrePtr t, CARD8 tx_mode, CARD8 rx_mode, CARD8 clk_mode); --static CARD32 dsp_configure_spdif_port(TheatrePtr t, CARD8 state); -- --static Bool theatre_read(TheatrePtr t,CARD32 reg, CARD32 *data) -+static uint32_t dsp_send_command(TheatrePtr t, uint32_t fb_scratch1, uint32_t fb_scratch0); -+static uint32_t dsp_set_video_input_connector(TheatrePtr t, uint32_t connector); -+//static uint32_t dsp_reset(TheatrePtr t); -+static uint32_t dsp_set_lowpowerstate(TheatrePtr t, uint32_t pstate); -+static uint32_t dsp_set_video_standard(TheatrePtr t, uint32_t standard); -+static uint32_t dsp_set_videostreamformat(TheatrePtr t, uint32_t format); -+static uint32_t dsp_video_standard_detection(TheatrePtr t); -+//static uint32_t dsp_get_signallockstatus(TheatrePtr t); -+//static uint32_t dsp_get_signallinenumber(TheatrePtr t); -+ -+static uint32_t dsp_set_brightness(TheatrePtr t, uint8_t brightness); -+static uint32_t dsp_set_contrast(TheatrePtr t, uint8_t contrast); -+//static uint32_t dsp_set_sharpness(TheatrePtr t, int sharpness); -+static uint32_t dsp_set_tint(TheatrePtr t, uint8_t tint); -+static uint32_t dsp_set_saturation(TheatrePtr t, uint8_t saturation); -+static uint32_t dsp_set_video_scaler_horizontal(TheatrePtr t, uint16_t output_width, uint16_t horz_start, uint16_t horz_end); -+static uint32_t dsp_set_video_scaler_vertical(TheatrePtr t, uint16_t output_height, uint16_t vert_start, uint16_t vert_end); -+static uint32_t dsp_audio_mute(TheatrePtr t, uint8_t left, uint8_t right); -+static uint32_t dsp_set_audio_volume(TheatrePtr t, uint8_t left, uint8_t right, uint8_t auto_mute); -+//static uint32_t dsp_audio_detection(TheatrePtr t, uint8_t option); -+static uint32_t dsp_configure_i2s_port(TheatrePtr t, uint8_t tx_mode, uint8_t rx_mode, uint8_t clk_mode); -+static uint32_t dsp_configure_spdif_port(TheatrePtr t, uint8_t state); -+ -+static Bool theatre_read(TheatrePtr t,uint32_t reg, uint32_t *data) - { - if(t->theatre_num<0)return FALSE; -- return t->VIP->read(t->VIP, ((t->theatre_num & 0x3)<<14) | reg,4, (CARD8 *) data); -+ return t->VIP->read(t->VIP, ((t->theatre_num & 0x3)<<14) | reg,4, (uint8_t *) data); - } - --static Bool theatre_write(TheatrePtr t,CARD32 reg, CARD32 data) -+static Bool theatre_write(TheatrePtr t,uint32_t reg, uint32_t data) - { - if(t->theatre_num<0)return FALSE; -- return t->VIP->write(t->VIP,((t->theatre_num & 0x03)<<14) | reg,4, (CARD8 *) &data); -+ return t->VIP->write(t->VIP,((t->theatre_num & 0x03)<<14) | reg,4, (uint8_t *) &data); - } - --static Bool theatre_fifo_read(TheatrePtr t,CARD32 fifo, CARD8 *data) -+static Bool theatre_fifo_read(TheatrePtr t,uint32_t fifo, uint8_t *data) - { - if(t->theatre_num<0)return FALSE; -- return t->VIP->fifo_read(t->VIP, ((t->theatre_num & 0x3)<<14) | fifo,1, (CARD8 *) data); -+ return t->VIP->fifo_read(t->VIP, ((t->theatre_num & 0x3)<<14) | fifo,1, (uint8_t *) data); - } - --static Bool theatre_fifo_write(TheatrePtr t,CARD32 fifo, CARD32 count, CARD8* buffer) -+static Bool theatre_fifo_write(TheatrePtr t,uint32_t fifo, uint32_t count, uint8_t* buffer) - { - if(t->theatre_num<0)return FALSE; -- return t->VIP->fifo_write(t->VIP,((t->theatre_num & 0x03)<<14) | fifo,count, (CARD8 *)buffer); -+ return t->VIP->fifo_write(t->VIP,((t->theatre_num & 0x03)<<14) | fifo,count, (uint8_t *)buffer); - } - - #define RT_regr(reg,data) theatre_read(t,(reg),(data)) -@@ -344,7 +344,7 @@ static void microc_clean(struct rt200_microc_data* microc_datap, int screen) - - static int dsp_init(TheatrePtr t, struct rt200_microc_data* microc_datap) - { -- CARD32 data; -+ uint32_t data; - int i = 0; - int screen = t->VIP->scrnIndex; - -@@ -369,12 +369,12 @@ static int dsp_init(TheatrePtr t, struct rt200_microc_data* microc_datap) - static int dsp_load(TheatrePtr t, struct rt200_microc_data* microc_datap) - { - struct rt200_microc_seg* seg_list = microc_datap->microc_seg_list; -- CARD8 data8; -- CARD32 data, fb_scratch0, fb_scratch1; -- CARD32 i; -- CARD32 tries = 0; -- CARD32 result = 0; -- CARD32 seg_id = 0; -+ uint8_t data8; -+ uint32_t data, fb_scratch0, fb_scratch1; -+ uint32_t i; -+ uint32_t tries = 0; -+ uint32_t result = 0; -+ uint32_t seg_id = 0; - int screen = t->VIP->scrnIndex; - - DEBUG("Microcode: before everything: %x\n", data8); -@@ -564,9 +564,9 @@ static int dsp_load(TheatrePtr t, struct rt200_microc_data* microc_datap) - return 0; - } - --static CARD32 dsp_send_command(TheatrePtr t, CARD32 fb_scratch1, CARD32 fb_scratch0) -+static uint32_t dsp_send_command(TheatrePtr t, uint32_t fb_scratch1, uint32_t fb_scratch0) - { -- CARD32 data; -+ uint32_t data; - int i; - - /* -@@ -611,10 +611,10 @@ static CARD32 dsp_send_command(TheatrePtr t, CARD32 fb_scratch1, CARD32 fb_scrat - return fb_scratch0; - } - --static CARD32 dsp_set_video_input_connector(TheatrePtr t, CARD32 connector) -+static uint32_t dsp_set_video_input_connector(TheatrePtr t, uint32_t connector) - { -- CARD32 fb_scratch0 = 0; -- CARD32 result; -+ uint32_t fb_scratch0 = 0; -+ uint32_t result; - int screen = t->VIP->scrnIndex; - - fb_scratch0 = ((connector << 8) & 0xff00) | (55 & 0xff); -@@ -627,10 +627,10 @@ static CARD32 dsp_set_video_input_connector(TheatrePtr t, CARD32 connector) - } - - #if 0 --static CARD32 dsp_reset(TheatrePtr t) -+static uint32_t dsp_reset(TheatrePtr t) - { -- CARD32 fb_scratch0 = 0; -- CARD32 result; -+ uint32_t fb_scratch0 = 0; -+ uint32_t result; - int screen = t->VIP->scrnIndex; - - fb_scratch0 = ((2 << 8) & 0xff00) | (8 & 0xff); -@@ -643,10 +643,10 @@ static CARD32 dsp_reset(TheatrePtr t) - } - #endif - --static CARD32 dsp_set_lowpowerstate(TheatrePtr t, CARD32 pstate) -+static uint32_t dsp_set_lowpowerstate(TheatrePtr t, uint32_t pstate) - { -- CARD32 fb_scratch0 = 0; -- CARD32 result; -+ uint32_t fb_scratch0 = 0; -+ uint32_t result; - int screen = t->VIP->scrnIndex; - - fb_scratch0 = ((pstate << 8) & 0xff00) | (82 & 0xff); -@@ -657,10 +657,10 @@ static CARD32 dsp_set_lowpowerstate(TheatrePtr t, CARD32 pstate) - - return result; - } --static CARD32 dsp_set_video_standard(TheatrePtr t, CARD32 standard) -+static uint32_t dsp_set_video_standard(TheatrePtr t, uint32_t standard) - { -- CARD32 fb_scratch0 = 0; -- CARD32 result; -+ uint32_t fb_scratch0 = 0; -+ uint32_t result; - int screen = t->VIP->scrnIndex; - - fb_scratch0 = ((standard << 8) & 0xff00) | (52 & 0xff); -@@ -672,10 +672,10 @@ static CARD32 dsp_set_video_standard(TheatrePtr t, CARD32 standard) - return result; - } - --static CARD32 dsp_set_videostreamformat(TheatrePtr t, CARD32 format) -+static uint32_t dsp_set_videostreamformat(TheatrePtr t, uint32_t format) - { -- CARD32 fb_scratch0 = 0; -- CARD32 result; -+ uint32_t fb_scratch0 = 0; -+ uint32_t result; - int screen = t->VIP->scrnIndex; - - fb_scratch0 = ((format << 8) & 0xff00) | (65 & 0xff); -@@ -687,10 +687,10 @@ static CARD32 dsp_set_videostreamformat(TheatrePtr t, CARD32 format) - return result; - } - --static CARD32 dsp_video_standard_detection(TheatrePtr t) -+static uint32_t dsp_video_standard_detection(TheatrePtr t) - { -- CARD32 fb_scratch0 = 0; -- CARD32 result; -+ uint32_t fb_scratch0 = 0; -+ uint32_t result; - int screen = t->VIP->scrnIndex; - - fb_scratch0 = 0 | (54 & 0xff); -@@ -703,11 +703,11 @@ static CARD32 dsp_video_standard_detection(TheatrePtr t) - } - - #if 0 --static CARD32 dsp_get_signallockstatus(TheatrePtr t) -+static uint32_t dsp_get_signallockstatus(TheatrePtr t) - { -- CARD32 fb_scratch1 = 0; -- CARD32 fb_scratch0 = 0; -- CARD32 result; -+ uint32_t fb_scratch1 = 0; -+ uint32_t fb_scratch0 = 0; -+ uint32_t result; - int screen = t->VIP->scrnIndex; - - fb_scratch0 = 0 | (77 & 0xff); -@@ -720,11 +720,11 @@ static CARD32 dsp_get_signallockstatus(TheatrePtr t) - return result; - } - --static CARD32 dsp_get_signallinenumber(TheatrePtr t) -+static uint32_t dsp_get_signallinenumber(TheatrePtr t) - { -- CARD32 fb_scratch1 = 0; -- CARD32 fb_scratch0 = 0; -- CARD32 result; -+ uint32_t fb_scratch1 = 0; -+ uint32_t fb_scratch0 = 0; -+ uint32_t result; - int screen = t->VIP->scrnIndex; - - fb_scratch0 = 0 | (78 & 0xff); -@@ -738,11 +738,11 @@ static CARD32 dsp_get_signallinenumber(TheatrePtr t) - } - #endif - --static CARD32 dsp_set_brightness(TheatrePtr t, CARD8 brightness) -+static uint32_t dsp_set_brightness(TheatrePtr t, uint8_t brightness) - { -- CARD32 fb_scratch1 = 0; -- CARD32 fb_scratch0 = 0; -- CARD32 result; -+ uint32_t fb_scratch1 = 0; -+ uint32_t fb_scratch0 = 0; -+ uint32_t result; - int screen = t->VIP->scrnIndex; - - fb_scratch0 = ((brightness << 8) & 0xff00) | (67 & 0xff); -@@ -754,11 +754,11 @@ static CARD32 dsp_set_brightness(TheatrePtr t, CARD8 brightness) - return result; - } - --static CARD32 dsp_set_contrast(TheatrePtr t, CARD8 contrast) -+static uint32_t dsp_set_contrast(TheatrePtr t, uint8_t contrast) - { -- CARD32 fb_scratch1 = 0; -- CARD32 fb_scratch0 = 0; -- CARD32 result; -+ uint32_t fb_scratch1 = 0; -+ uint32_t fb_scratch0 = 0; -+ uint32_t result; - int screen = t->VIP->scrnIndex; - - fb_scratch0 = ((contrast << 8) & 0xff00) | (71 & 0xff); -@@ -771,11 +771,11 @@ static CARD32 dsp_set_contrast(TheatrePtr t, CARD8 contrast) - } - - #if 0 --static CARD32 dsp_set_sharpness(TheatrePtr t, int sharpness) -+static uint32_t dsp_set_sharpness(TheatrePtr t, int sharpness) - { -- CARD32 fb_scratch1 = 0; -- CARD32 fb_scratch0 = 0; -- CARD32 result; -+ uint32_t fb_scratch1 = 0; -+ uint32_t fb_scratch0 = 0; -+ uint32_t result; - int screen = t->VIP->scrnIndex; - - fb_scratch0 = 0 | (73 & 0xff); -@@ -788,11 +788,11 @@ static CARD32 dsp_set_sharpness(TheatrePtr t, int sharpness) - } - #endif - --static CARD32 dsp_set_tint(TheatrePtr t, CARD8 tint) -+static uint32_t dsp_set_tint(TheatrePtr t, uint8_t tint) - { -- CARD32 fb_scratch1 = 0; -- CARD32 fb_scratch0 = 0; -- CARD32 result; -+ uint32_t fb_scratch1 = 0; -+ uint32_t fb_scratch0 = 0; -+ uint32_t result; - int screen = t->VIP->scrnIndex; - - fb_scratch0 = ((tint << 8) & 0xff00) | (75 & 0xff); -@@ -804,11 +804,11 @@ static CARD32 dsp_set_tint(TheatrePtr t, CARD8 tint) - return result; - } - --static CARD32 dsp_set_saturation(TheatrePtr t, CARD8 saturation) -+static uint32_t dsp_set_saturation(TheatrePtr t, uint8_t saturation) - { -- CARD32 fb_scratch1 = 0; -- CARD32 fb_scratch0 = 0; -- CARD32 result; -+ uint32_t fb_scratch1 = 0; -+ uint32_t fb_scratch0 = 0; -+ uint32_t result; - int screen = t->VIP->scrnIndex; - - fb_scratch0 = ((saturation << 8) & 0xff00) | (69 & 0xff); -@@ -820,11 +820,11 @@ static CARD32 dsp_set_saturation(TheatrePtr t, CARD8 saturation) - return result; - } - --static CARD32 dsp_set_video_scaler_horizontal(TheatrePtr t, CARD16 output_width, CARD16 horz_start, CARD16 horz_end) -+static uint32_t dsp_set_video_scaler_horizontal(TheatrePtr t, uint16_t output_width, uint16_t horz_start, uint16_t horz_end) - { -- CARD32 fb_scratch1 = 0; -- CARD32 fb_scratch0 = 0; -- CARD32 result; -+ uint32_t fb_scratch1 = 0; -+ uint32_t fb_scratch0 = 0; -+ uint32_t result; - int screen = t->VIP->scrnIndex; - - fb_scratch0 = ((output_width << 8) & 0x00ffff00) | (195 & 0xff); -@@ -837,11 +837,11 @@ static CARD32 dsp_set_video_scaler_horizontal(TheatrePtr t, CARD16 output_width, - return result; - } - --static CARD32 dsp_set_video_scaler_vertical(TheatrePtr t, CARD16 output_height, CARD16 vert_start, CARD16 vert_end) -+static uint32_t dsp_set_video_scaler_vertical(TheatrePtr t, uint16_t output_height, uint16_t vert_start, uint16_t vert_end) - { -- CARD32 fb_scratch1 = 0; -- CARD32 fb_scratch0 = 0; -- CARD32 result; -+ uint32_t fb_scratch1 = 0; -+ uint32_t fb_scratch0 = 0; -+ uint32_t result; - int screen = t->VIP->scrnIndex; - - fb_scratch0 = ((output_height << 8) & 0x00ffff00) | (196 & 0xff); -@@ -854,11 +854,11 @@ static CARD32 dsp_set_video_scaler_vertical(TheatrePtr t, CARD16 output_height, - return result; - } - --static CARD32 dsp_audio_mute(TheatrePtr t, CARD8 left, CARD8 right) -+static uint32_t dsp_audio_mute(TheatrePtr t, uint8_t left, uint8_t right) - { -- CARD32 fb_scratch1 = 0; -- CARD32 fb_scratch0 = 0; -- CARD32 result; -+ uint32_t fb_scratch1 = 0; -+ uint32_t fb_scratch0 = 0; -+ uint32_t result; - int screen = t->VIP->scrnIndex; - - fb_scratch0 = ((right << 16) & 0xff0000) | ((left << 8) & 0xff00) | (21 & 0xff); -@@ -870,11 +870,11 @@ static CARD32 dsp_audio_mute(TheatrePtr t, CARD8 left, CARD8 right) - return result; - } - --static CARD32 dsp_set_audio_volume(TheatrePtr t, CARD8 left, CARD8 right, CARD8 auto_mute) -+static uint32_t dsp_set_audio_volume(TheatrePtr t, uint8_t left, uint8_t right, uint8_t auto_mute) - { -- CARD32 fb_scratch1 = 0; -- CARD32 fb_scratch0 = 0; -- CARD32 result; -+ uint32_t fb_scratch1 = 0; -+ uint32_t fb_scratch0 = 0; -+ uint32_t result; - int screen = t->VIP->scrnIndex; - - fb_scratch0 = ((auto_mute << 24) & 0xff000000) | ((right << 16) & 0xff0000) | ((left << 8) & 0xff00) | (22 & 0xff); -@@ -887,11 +887,11 @@ static CARD32 dsp_set_audio_volume(TheatrePtr t, CARD8 left, CARD8 right, CARD8 - } - - #if 0 --static CARD32 dsp_audio_detection(TheatrePtr t, CARD8 option) -+static uint32_t dsp_audio_detection(TheatrePtr t, uint8_t option) - { -- CARD32 fb_scratch1 = 0; -- CARD32 fb_scratch0 = 0; -- CARD32 result; -+ uint32_t fb_scratch1 = 0; -+ uint32_t fb_scratch0 = 0; -+ uint32_t result; - int screen = t->VIP->scrnIndex; - - fb_scratch0 = ((option << 8) & 0xff00) | (16 & 0xff); -@@ -904,11 +904,11 @@ static CARD32 dsp_audio_detection(TheatrePtr t, CARD8 option) - } - #endif - --static CARD32 dsp_configure_i2s_port(TheatrePtr t, CARD8 tx_mode, CARD8 rx_mode, CARD8 clk_mode) -+static uint32_t dsp_configure_i2s_port(TheatrePtr t, uint8_t tx_mode, uint8_t rx_mode, uint8_t clk_mode) - { -- CARD32 fb_scratch1 = 0; -- CARD32 fb_scratch0 = 0; -- CARD32 result; -+ uint32_t fb_scratch1 = 0; -+ uint32_t fb_scratch0 = 0; -+ uint32_t result; - int screen = t->VIP->scrnIndex; - - fb_scratch0 = ((clk_mode << 24) & 0xff000000) | ((rx_mode << 16) & 0xff0000) | ((tx_mode << 8) & 0xff00) | (40 & 0xff); -@@ -920,11 +920,11 @@ static CARD32 dsp_configure_i2s_port(TheatrePtr t, CARD8 tx_mode, CARD8 rx_mode, - return result; - } - --static CARD32 dsp_configure_spdif_port(TheatrePtr t, CARD8 state) -+static uint32_t dsp_configure_spdif_port(TheatrePtr t, uint8_t state) - { -- CARD32 fb_scratch1 = 0; -- CARD32 fb_scratch0 = 0; -- CARD32 result; -+ uint32_t fb_scratch1 = 0; -+ uint32_t fb_scratch0 = 0; -+ uint32_t result; - int screen = t->VIP->scrnIndex; - - fb_scratch0 = ((state << 8) & 0xff00) | (41 & 0xff); -@@ -1014,7 +1014,7 @@ fld_V_INT_LENGTH, - fld_CRDR_ACTIVE_GAIN, - fld_CBDB_ACTIVE_GAIN, - fld_DVS_DIRECTION, --fld_DVS_VBI_CARD8_SWAP, -+fld_DVS_VBI_UINT8_SWAP, - fld_DVS_CLK_SELECT, - fld_CONTINUOUS_STREAM, - fld_DVSOUT_CLK_DRV, -@@ -1096,16 +1096,16 @@ regRT_MAX_REGS - - - typedef struct { -- CARD8 size; -- CARD32 fld_id; -- CARD32 dwRegAddrLSBs; -- CARD32 dwFldOffsetLSBs; -- CARD32 dwMaskLSBs; -- CARD32 addr2; -- CARD32 offs2; -- CARD32 mask2; -- CARD32 dwCurrValue; -- CARD32 rw; -+ uint8_t size; -+ uint32_t fld_id; -+ uint32_t dwRegAddrLSBs; -+ uint32_t dwFldOffsetLSBs; -+ uint32_t dwMaskLSBs; -+ uint32_t addr2; -+ uint32_t offs2; -+ uint32_t mask2; -+ uint32_t dwCurrValue; -+ uint32_t rw; - } RTREGMAP; - - #define READONLY 1 -@@ -1193,7 +1193,7 @@ RTREGMAP RT_RegMap[regRT_MAX_REGS]={ - {10 ,fld_CRDR_ACTIVE_GAIN ,VIP_CP_ACTIVE_GAIN , 0, 0xFFFFFC00, 0, 0,0, fld_CRDR_ACTIVE_GAIN_def ,READWRITE }, - {10 ,fld_CBDB_ACTIVE_GAIN ,VIP_CP_ACTIVE_GAIN , 16, 0xFC00FFFF, 0, 0,0, fld_CBDB_ACTIVE_GAIN_def ,READWRITE }, - {1 ,fld_DVS_DIRECTION ,VIP_DVS_PORT_CTRL , 0, 0xFFFFFFFE, 0, 0,0, fld_DVS_DIRECTION_def ,READWRITE }, --{1 ,fld_DVS_VBI_CARD8_SWAP ,VIP_DVS_PORT_CTRL , 1, 0xFFFFFFFD, 0, 0,0, fld_DVS_VBI_CARD8_SWAP_def ,READWRITE }, -+{1 ,fld_DVS_VBI_UINT8_SWAP ,VIP_DVS_PORT_CTRL , 1, 0xFFFFFFFD, 0, 0,0, fld_DVS_VBI_UINT8_SWAP_def ,READWRITE }, - {1 ,fld_DVS_CLK_SELECT ,VIP_DVS_PORT_CTRL , 2, 0xFFFFFFFB, 0, 0,0, fld_DVS_CLK_SELECT_def ,READWRITE }, - {1 ,fld_CONTINUOUS_STREAM ,VIP_DVS_PORT_CTRL , 3, 0xFFFFFFF7, 0, 0,0, fld_CONTINUOUS_STREAM_def ,READWRITE }, - {1 ,fld_DVSOUT_CLK_DRV ,VIP_DVS_PORT_CTRL , 4, 0xFFFFFFEF, 0, 0,0, fld_DVSOUT_CLK_DRV_def ,READWRITE }, -@@ -1272,7 +1272,7 @@ RTREGMAP RT_RegMap[regRT_MAX_REGS]={ - }; - - /* Rage Theatre's register fields default values: */ --CARD32 RT_RegDef[regRT_MAX_REGS]= -+uint32_t RT_RegDef[regRT_MAX_REGS]= - { - fld_tmpReg1_def, - fld_tmpReg2_def, -@@ -1350,7 +1350,7 @@ fld_V_INT_LENGTH_def, - fld_CRDR_ACTIVE_GAIN_def, - fld_CBDB_ACTIVE_GAIN_def, - fld_DVS_DIRECTION_def, --fld_DVS_VBI_CARD8_SWAP_def, -+fld_DVS_VBI_UINT8_SWAP_def, - fld_DVS_CLK_SELECT_def, - fld_CONTINUOUS_STREAM_def, - fld_DVSOUT_CLK_DRV_def, -@@ -1429,16 +1429,16 @@ fld_GPIO_6_OUT_def, - }; - - /**************************************************************************** -- * WriteRT_fld (CARD32 dwReg, CARD32 dwData) * -+ * WriteRT_fld (uint32_t dwReg, uint32_t dwData) * - * Function: Writes a register field within Rage Theatre * -- * Inputs: CARD32 dwReg = register field to be written * -- * CARD32 dwData = data that will be written to the reg field * -+ * Inputs: uint32_t dwReg = register field to be written * -+ * uint32_t dwData = data that will be written to the reg field * - * Outputs: NONE * - ****************************************************************************/ --static void WriteRT_fld1 (TheatrePtr t, CARD32 dwReg, CARD32 dwData) -+static void WriteRT_fld1 (TheatrePtr t, uint32_t dwReg, uint32_t dwData) - { -- CARD32 dwResult=0; -- CARD32 dwValue=0; -+ uint32_t dwResult=0; -+ uint32_t dwValue=0; - - if (RT_regr (RT_RegMap[dwReg].dwRegAddrLSBs, &dwResult) == TRUE) - { -@@ -1458,14 +1458,14 @@ static void WriteRT_fld1 (TheatrePtr t, CARD32 dwReg, CARD32 dwData) - - #if 0 - /**************************************************************************** -- * ReadRT_fld (CARD32 dwReg) * -+ * ReadRT_fld (uint32_t dwReg) * - * Function: Reads a register field within Rage Theatre * -- * Inputs: CARD32 dwReg = register field to be read * -- * Outputs: CARD32 - value read from register field * -+ * Inputs: uint32_t dwReg = register field to be read * -+ * Outputs: uint32_t - value read from register field * - ****************************************************************************/ --static CARD32 ReadRT_fld1 (TheatrePtr t,CARD32 dwReg) -+static uint32_t ReadRT_fld1 (TheatrePtr t,uint32_t dwReg) - { -- CARD32 dwResult=0; -+ uint32_t dwResult=0; - - if (RT_regr (RT_RegMap[dwReg].dwRegAddrLSBs, &dwResult) == TRUE) - { -@@ -1492,7 +1492,7 @@ static CARD32 ReadRT_fld1 (TheatrePtr t,CARD32 dwReg) - * Inputs: int hue - the hue value to be set. * - * Outputs: NONE * - ****************************************************************************/ --void RT_SetTint (TheatrePtr t, int hue) -+_X_EXPORT void RT_SetTint (TheatrePtr t, int hue) - { - /* Validate Hue level */ - if (hue < -1000) -@@ -1506,7 +1506,7 @@ void RT_SetTint (TheatrePtr t, int hue) - - t->iHue=hue; - -- dsp_set_tint(t, (CARD8)((hue*255)/2000 + 128)); -+ dsp_set_tint(t, (uint8_t)((hue*255)/2000 + 128)); - - } /* RT_SetTint ()... */ - -@@ -1517,7 +1517,7 @@ void RT_SetTint (TheatrePtr t, int hue) - * Inputs: int Saturation - the saturation value to be set. * - * Outputs: NONE * - ****************************************************************************/ --void RT_SetSaturation (TheatrePtr t, int Saturation) -+_X_EXPORT void RT_SetSaturation (TheatrePtr t, int Saturation) - { - /* VALIDATE SATURATION LEVEL */ - if (Saturation < -1000L) -@@ -1532,7 +1532,7 @@ void RT_SetSaturation (TheatrePtr t, int Saturation) - t->iSaturation = Saturation; - - /* RT200 has saturation in range 0 to 255 with nominal value 128 */ -- dsp_set_saturation(t, (CARD8)((Saturation*255)/2000 + 128)); -+ dsp_set_saturation(t, (uint8_t)((Saturation*255)/2000 + 128)); - - return; - } /* RT_SetSaturation ()...*/ -@@ -1543,7 +1543,7 @@ void RT_SetSaturation (TheatrePtr t, int Saturation) - * Inputs: int Brightness - the brightness value to be set. * - * Outputs: NONE * - ****************************************************************************/ --void RT_SetBrightness (TheatrePtr t, int Brightness) -+_X_EXPORT void RT_SetBrightness (TheatrePtr t, int Brightness) - { - /* VALIDATE BRIGHTNESS LEVEL */ - if (Brightness < -1000) -@@ -1560,19 +1560,19 @@ void RT_SetBrightness (TheatrePtr t, int Brightness) - t->dbBrightnessRatio = (double) (Brightness+1000.0) / 10.0; - - /* RT200 is having brightness level from 0 to 255 with 128 nominal value */ -- dsp_set_brightness(t, (CARD8)((Brightness*255)/2000 + 128)); -+ dsp_set_brightness(t, (uint8_t)((Brightness*255)/2000 + 128)); - - return; - } /* RT_SetBrightness ()... */ - - - /**************************************************************************** -- * RT_SetSharpness (CARD16 wSharpness) * -+ * RT_SetSharpness (uint16_t wSharpness) * - * Function: sets the sharpness level for the Rage Theatre video in * -- * Inputs: CARD16 wSharpness - the sharpness value to be set. * -+ * Inputs: uint16_t wSharpness - the sharpness value to be set. * - * Outputs: NONE * - ****************************************************************************/ --void RT_SetSharpness (TheatrePtr t, CARD16 wSharpness) -+_X_EXPORT void RT_SetSharpness (TheatrePtr t, uint16_t wSharpness) - { - switch (wSharpness) - { -@@ -1598,7 +1598,7 @@ void RT_SetSharpness (TheatrePtr t, CARD16 wSharpness) - * Inputs: int Contrast - the contrast value to be set. * - * Outputs: NONE * - ****************************************************************************/ --void RT_SetContrast (TheatrePtr t, int Contrast) -+_X_EXPORT void RT_SetContrast (TheatrePtr t, int Contrast) - { - /* VALIDATE CONTRAST LEVEL */ - if (Contrast < -1000) -@@ -1615,28 +1615,28 @@ void RT_SetContrast (TheatrePtr t, int Contrast) - t->dbContrast = (double) (Contrast+1000.0) / 1000.0; - - /* RT200 has contrast values between 0 to 255 with nominal value at 128 */ -- dsp_set_contrast(t, (CARD8)((Contrast*255)/2000 + 128)); -+ dsp_set_contrast(t, (uint8_t)((Contrast*255)/2000 + 128)); - return; - - } /* RT_SetContrast ()... */ - - /**************************************************************************** -- * RT_SetInterlace (CARD8 bInterlace) * -+ * RT_SetInterlace (uint8_t bInterlace) * - * Function: to set the interlacing pattern for the Rage Theatre video in * -- * Inputs: CARD8 bInterlace * -+ * Inputs: uint8_t bInterlace * - * Outputs: NONE * - ****************************************************************************/ --void RT_SetInterlace (TheatrePtr t, CARD8 bInterlace) -+_X_EXPORT void RT_SetInterlace (TheatrePtr t, uint8_t bInterlace) - { - switch(bInterlace) - { - case (TRUE): /*DEC_INTERLACE */ - WriteRT_fld (fld_V_DEINTERLACE_ON, 0x1); -- t->wInterlaced = (CARD16) RT_DECINTERLACED; -+ t->wInterlaced = (uint16_t) RT_DECINTERLACED; - break; - case (FALSE): /*DEC_NONINTERLACE */ - WriteRT_fld (fld_V_DEINTERLACE_ON, RT_DECNONINTERLACED); -- t->wInterlaced = (CARD16) RT_DECNONINTERLACED; -+ t->wInterlaced = (uint16_t) RT_DECNONINTERLACED; - break; - default: - break; -@@ -1648,12 +1648,12 @@ void RT_SetInterlace (TheatrePtr t, CARD8 bInterlace) - - - /**************************************************************************** -- * RT_SetStandard (CARD16 wStandard) * -+ * RT_SetStandard (uint16_t wStandard) * - * Function: to set the input standard for the Rage Theatre video in * -- * Inputs: CARD16 wStandard - input standard (NTSC, PAL, SECAM) * -+ * Inputs: uint16_t wStandard - input standard (NTSC, PAL, SECAM) * - * Outputs: NONE * - ****************************************************************************/ --void RT_SetStandard (TheatrePtr t, CARD16 wStandard) -+_X_EXPORT void RT_SetStandard (TheatrePtr t, uint16_t wStandard) - { - xf86DrvMsg(t->VIP->scrnIndex,X_INFO,"Rage Theatre setting standard 0x%04x\n", - wStandard); -@@ -1763,16 +1763,16 @@ void RT_SetStandard (TheatrePtr t, CARD16 wStandard) - - - /**************************************************************************** -- * RT_SetOutputVideoSize (CARD16 wHorzSize, CARD16 wVertSize, * -- * CARD8 fCC_On, CARD8 fVBICap_On) * -+ * RT_SetOutputVideoSize (uint16_t wHorzSize, uint16_t wVertSize, * -+ * uint8_t fCC_On, uint8_t fVBICap_On) * - * Function: sets the output video size for the Rage Theatre video in * -- * Inputs: CARD16 wHorzSize - width of output in pixels * -- * CARD16 wVertSize - height of output in pixels (lines) * -- * CARD8 fCC_On - enable CC output * -- * CARD8 fVBI_Cap_On - enable VBI capture * -+ * Inputs: uint16_t wHorzSize - width of output in pixels * -+ * uint16_t wVertSize - height of output in pixels (lines) * -+ * uint8_t fCC_On - enable CC output * -+ * uint8_t fVBI_Cap_On - enable VBI capture * - * Outputs: NONE * - ****************************************************************************/ --void RT_SetOutputVideoSize (TheatrePtr t, CARD16 wHorzSize, CARD16 wVertSize, CARD8 fCC_On, CARD8 fVBICap_On) -+_X_EXPORT void RT_SetOutputVideoSize (TheatrePtr t, uint16_t wHorzSize, uint16_t wVertSize, uint8_t fCC_On, uint8_t fVBICap_On) - { - /* VBI is ignored now */ - -@@ -1786,15 +1786,15 @@ void RT_SetOutputVideoSize (TheatrePtr t, CARD16 wHorzSize, CARD16 wVertSize, CA - - - /**************************************************************************** -- * RT_SetConnector (CARD16 wStandard, int tunerFlag) * -+ * RT_SetConnector (uint16_t wStandard, int tunerFlag) * - * Function: -- * Inputs: CARD16 wStandard - input standard (NTSC, PAL, SECAM) * -+ * Inputs: uint16_t wStandard - input standard (NTSC, PAL, SECAM) * - * int tunerFlag - * Outputs: NONE * - ****************************************************************************/ --void RT_SetConnector (TheatrePtr t, CARD16 wConnector, int tunerFlag) -+_X_EXPORT void RT_SetConnector (TheatrePtr t, uint16_t wConnector, int tunerFlag) - { -- CARD32 data; -+ uint32_t data; - - t->wConnector = wConnector; - -@@ -1871,10 +1871,10 @@ void RT_SetConnector (TheatrePtr t, CARD16 wConnector, int tunerFlag) - } /* RT_SetConnector ()...*/ - - --void InitTheatre(TheatrePtr t) -+_X_EXPORT void InitTheatre(TheatrePtr t) - { -- CARD32 data; -- CARD32 M, N, P; -+ uint32_t data; -+ uint32_t M, N, P; - - /* this will give 108Mhz at 27Mhz reference */ - M = 28; -@@ -1992,7 +1992,7 @@ err_exit: - } - - --void ShutdownTheatre(TheatrePtr t) -+_X_EXPORT void ShutdownTheatre(TheatrePtr t) - { - #if 0 - WriteRT_fld (fld_VIN_ASYNC_RST, RT_ASYNC_DISABLE); -@@ -2003,10 +2003,10 @@ void ShutdownTheatre(TheatrePtr t) - t->mode=MODE_UNINITIALIZED; - } - --void DumpRageTheatreRegs(TheatrePtr t) -+_X_EXPORT void DumpRageTheatreRegs(TheatrePtr t) - { - int i; -- CARD32 data; -+ uint32_t data; - - for(i=0;i<0x900;i+=4) - { -@@ -2020,7 +2020,7 @@ void DumpRageTheatreRegs(TheatrePtr t) - void DumpRageTheatreRegsByName(TheatrePtr t) - { - int i; -- CARD32 data; -+ uint32_t data; - struct { char *name; long addr; } rt_reg_list[]={ - { "ADC_CNTL ", 0x0400 }, - { "ADC_DEBUG ", 0x0404 }, -@@ -2224,7 +2224,7 @@ void DumpRageTheatreRegsByName(TheatrePtr t) - - } - --void ResetTheatreRegsForNoTVout(TheatrePtr t) -+_X_EXPORT void ResetTheatreRegsForNoTVout(TheatrePtr t) - { - RT_regw(VIP_CLKOUT_CNTL, 0x0); - RT_regw(VIP_HCOUNT, 0x0); -@@ -2238,7 +2238,7 @@ void ResetTheatreRegsForNoTVout(TheatrePtr t) - } - - --void ResetTheatreRegsForTVout(TheatrePtr t) -+_X_EXPORT void ResetTheatreRegsForTVout(TheatrePtr t) - { - /* RT_regw(VIP_HW_DEBUG, 0x200); */ - /* RT_regw(VIP_INT_CNTL, 0x0); -diff --git a/src/theatre_detect.c b/src/theatre_detect.c -index 8770911..7e7f813 100644 ---- a/src/theatre_detect.c -+++ b/src/theatre_detect.c -@@ -43,19 +43,20 @@ - #include "generic_bus.h" - #include "theatre.h" - #include "theatre_reg.h" -+#include "theatre_detect.h" - --static Bool theatre_read(TheatrePtr t,CARD32 reg, CARD32 *data) -+static Bool theatre_read(TheatrePtr t,uint32_t reg, uint32_t *data) - { - if(t->theatre_num<0)return FALSE; -- return t->VIP->read(t->VIP, ((t->theatre_num & 0x3)<<14) | reg,4, (CARD8 *) data); -+ return t->VIP->read(t->VIP, ((t->theatre_num & 0x3)<<14) | reg,4, (uint8_t *) data); - } - - /* Unused code - reference */ - #if 0 --static Bool theatre_write(TheatrePtr t,CARD32 reg, CARD32 data) -+static Bool theatre_write(TheatrePtr t,uint32_t reg, uint32_t data) - { - if(t->theatre_num<0)return FALSE; -- return t->VIP->write(t->VIP,((t->theatre_num & 0x03)<<14) | reg,4, (CARD8 *) &data); -+ return t->VIP->write(t->VIP,((t->theatre_num & 0x03)<<14) | reg,4, (uint8_t *) &data); - } - #define RT_regw(reg,data) theatre_write(t,(reg),(data)) - #endif -@@ -64,11 +65,11 @@ static Bool theatre_write(TheatrePtr t,CARD32 reg, CARD32 data) - #define VIP_TYPE "ATI VIP BUS" - - --TheatrePtr DetectTheatre(GENERIC_BUS_Ptr b) -+_X_EXPORT TheatrePtr DetectTheatre(GENERIC_BUS_Ptr b) - { - TheatrePtr t; - int i; -- CARD32 val; -+ uint32_t val; - char s[20]; - - b->ioctl(b,GB_IOCTL_GET_TYPE,20,s); -@@ -83,10 +84,10 @@ TheatrePtr DetectTheatre(GENERIC_BUS_Ptr b) - t->theatre_num = -1; - t->mode=MODE_UNINITIALIZED; - -- b->read(b, VIP_VIP_VENDOR_DEVICE_ID, 4, (CARD8 *)&val); -+ b->read(b, VIP_VIP_VENDOR_DEVICE_ID, 4, (uint8_t *)&val); - for(i=0;i<4;i++) - { -- if(b->read(b, ((i & 0x03)<<14) | VIP_VIP_VENDOR_DEVICE_ID, 4, (CARD8 *)&val)) -+ if(b->read(b, ((i & 0x03)<<14) | VIP_VIP_VENDOR_DEVICE_ID, 4, (uint8_t *)&val)) - { - if(val)xf86DrvMsg(b->scrnIndex, X_INFO, - "Device %d on VIP bus ids as 0x%08x\n", i, -diff --git a/src/theatre_detect.h b/src/theatre_detect.h -index 5fed160..53d8d11 100644 ---- a/src/theatre_detect.h -+++ b/src/theatre_detect.h -@@ -38,9 +38,9 @@ - */ - - --TheatrePtr DetectTheatre(GENERIC_BUS_Ptr b); -+#define xf86_DetectTheatre DetectTheatre -+_X_EXPORT TheatrePtr DetectTheatre(GENERIC_BUS_Ptr b); - - --#define xf86_DetectTheatre ((TheatrePtr (*)(GENERIC_BUS_Ptr))LoaderSymbol("DetectTheatre")) - - #endif -diff --git a/src/theatre_reg.h b/src/theatre_reg.h -index c681001..30fafe7 100644 ---- a/src/theatre_reg.h -+++ b/src/theatre_reg.h -@@ -661,215 +661,215 @@ - #define DEC_SHARP 1 - - /* RT Register Field Defaults: */ --#define fld_tmpReg1_def (CARD32) 0x00000000 --#define fld_tmpReg2_def (CARD32) 0x00000001 --#define fld_tmpReg3_def (CARD32) 0x00000002 -+#define fld_tmpReg1_def (uint32_t) 0x00000000 -+#define fld_tmpReg2_def (uint32_t) 0x00000001 -+#define fld_tmpReg3_def (uint32_t) 0x00000002 - --#define fld_LP_CONTRAST_def (CARD32) 0x0000006e --#define fld_LP_BRIGHTNESS_def (CARD32) 0x00003ff0 --#define fld_CP_HUE_CNTL_def (CARD32) 0x00000000 --#define fld_LUMA_FILTER_def (CARD32) 0x00000001 --#define fld_H_SCALE_RATIO_def (CARD32) 0x00010000 --#define fld_H_SHARPNESS_def (CARD32) 0x00000000 -+#define fld_LP_CONTRAST_def (uint32_t) 0x0000006e -+#define fld_LP_BRIGHTNESS_def (uint32_t) 0x00003ff0 -+#define fld_CP_HUE_CNTL_def (uint32_t) 0x00000000 -+#define fld_LUMA_FILTER_def (uint32_t) 0x00000001 -+#define fld_H_SCALE_RATIO_def (uint32_t) 0x00010000 -+#define fld_H_SHARPNESS_def (uint32_t) 0x00000000 - --#define fld_V_SCALE_RATIO_def (CARD32) 0x00000800 --#define fld_V_DEINTERLACE_ON_def (CARD32) 0x00000001 --#define fld_V_BYPSS_def (CARD32) 0x00000000 --#define fld_V_DITHER_ON_def (CARD32) 0x00000001 --#define fld_EVENF_OFFSET_def (CARD32) 0x00000000 --#define fld_ODDF_OFFSET_def (CARD32) 0x00000000 -+#define fld_V_SCALE_RATIO_def (uint32_t) 0x00000800 -+#define fld_V_DEINTERLACE_ON_def (uint32_t) 0x00000001 -+#define fld_V_BYPSS_def (uint32_t) 0x00000000 -+#define fld_V_DITHER_ON_def (uint32_t) 0x00000001 -+#define fld_EVENF_OFFSET_def (uint32_t) 0x00000000 -+#define fld_ODDF_OFFSET_def (uint32_t) 0x00000000 - --#define fld_INTERLACE_DETECTED_def (CARD32) 0x00000000 -+#define fld_INTERLACE_DETECTED_def (uint32_t) 0x00000000 - --#define fld_VS_LINE_COUNT_def (CARD32) 0x00000000 --#define fld_VS_DETECTED_LINES_def (CARD32) 0x00000000 --#define fld_VS_ITU656_VB_def (CARD32) 0x00000000 -+#define fld_VS_LINE_COUNT_def (uint32_t) 0x00000000 -+#define fld_VS_DETECTED_LINES_def (uint32_t) 0x00000000 -+#define fld_VS_ITU656_VB_def (uint32_t) 0x00000000 - --#define fld_VBI_CC_DATA_def (CARD32) 0x00000000 --#define fld_VBI_CC_WT_def (CARD32) 0x00000000 --#define fld_VBI_CC_WT_ACK_def (CARD32) 0x00000000 --#define fld_VBI_CC_HOLD_def (CARD32) 0x00000000 --#define fld_VBI_DECODE_EN_def (CARD32) 0x00000000 -+#define fld_VBI_CC_DATA_def (uint32_t) 0x00000000 -+#define fld_VBI_CC_WT_def (uint32_t) 0x00000000 -+#define fld_VBI_CC_WT_ACK_def (uint32_t) 0x00000000 -+#define fld_VBI_CC_HOLD_def (uint32_t) 0x00000000 -+#define fld_VBI_DECODE_EN_def (uint32_t) 0x00000000 - --#define fld_VBI_CC_DTO_P_def (CARD32) 0x00001802 --#define fld_VBI_20BIT_DTO_P_def (CARD32) 0x0000155c -+#define fld_VBI_CC_DTO_P_def (uint32_t) 0x00001802 -+#define fld_VBI_20BIT_DTO_P_def (uint32_t) 0x0000155c - --#define fld_VBI_CC_LEVEL_def (CARD32) 0x0000003f --#define fld_VBI_20BIT_LEVEL_def (CARD32) 0x00000059 --#define fld_VBI_CLK_RUNIN_GAIN_def (CARD32) 0x0000010f -+#define fld_VBI_CC_LEVEL_def (uint32_t) 0x0000003f -+#define fld_VBI_20BIT_LEVEL_def (uint32_t) 0x00000059 -+#define fld_VBI_CLK_RUNIN_GAIN_def (uint32_t) 0x0000010f - --#define fld_H_VBI_WIND_START_def (CARD32) 0x00000041 --#define fld_H_VBI_WIND_END_def (CARD32) 0x00000366 -+#define fld_H_VBI_WIND_START_def (uint32_t) 0x00000041 -+#define fld_H_VBI_WIND_END_def (uint32_t) 0x00000366 - --#define fld_V_VBI_WIND_START_def (CARD32) 0x0B /* instead of 0x0D - V.D. */ --#define fld_V_VBI_WIND_END_def (CARD32) 0x24 -+#define fld_V_VBI_WIND_START_def (uint32_t) 0x0B /* instead of 0x0D - V.D. */ -+#define fld_V_VBI_WIND_END_def (uint32_t) 0x24 - --#define fld_VBI_20BIT_DATA0_def (CARD32) 0x00000000 --#define fld_VBI_20BIT_DATA1_def (CARD32) 0x00000000 --#define fld_VBI_20BIT_WT_def (CARD32) 0x00000000 --#define fld_VBI_20BIT_WT_ACK_def (CARD32) 0x00000000 --#define fld_VBI_20BIT_HOLD_def (CARD32) 0x00000000 -+#define fld_VBI_20BIT_DATA0_def (uint32_t) 0x00000000 -+#define fld_VBI_20BIT_DATA1_def (uint32_t) 0x00000000 -+#define fld_VBI_20BIT_WT_def (uint32_t) 0x00000000 -+#define fld_VBI_20BIT_WT_ACK_def (uint32_t) 0x00000000 -+#define fld_VBI_20BIT_HOLD_def (uint32_t) 0x00000000 - --#define fld_VBI_CAPTURE_ENABLE_def (CARD32) 0x00000000 -+#define fld_VBI_CAPTURE_ENABLE_def (uint32_t) 0x00000000 - --#define fld_VBI_EDS_DATA_def (CARD32) 0x00000000 --#define fld_VBI_EDS_WT_def (CARD32) 0x00000000 --#define fld_VBI_EDS_WT_ACK_def (CARD32) 0x00000000 --#define fld_VBI_EDS_HOLD_def (CARD32) 0x00000000 -+#define fld_VBI_EDS_DATA_def (uint32_t) 0x00000000 -+#define fld_VBI_EDS_WT_def (uint32_t) 0x00000000 -+#define fld_VBI_EDS_WT_ACK_def (uint32_t) 0x00000000 -+#define fld_VBI_EDS_HOLD_def (uint32_t) 0x00000000 - --#define fld_VBI_SCALING_RATIO_def (CARD32) 0x00010000 --#define fld_VBI_ALIGNER_ENABLE_def (CARD32) 0x00000000 -+#define fld_VBI_SCALING_RATIO_def (uint32_t) 0x00010000 -+#define fld_VBI_ALIGNER_ENABLE_def (uint32_t) 0x00000000 - --#define fld_H_ACTIVE_START_def (CARD32) 0x00000070 --#define fld_H_ACTIVE_END_def (CARD32) 0x000002f0 -+#define fld_H_ACTIVE_START_def (uint32_t) 0x00000070 -+#define fld_H_ACTIVE_END_def (uint32_t) 0x000002f0 - --#define fld_V_ACTIVE_START_def (CARD32) ((22-4)*2+1) --#define fld_V_ACTIVE_END_def (CARD32) ((22+240-4)*2+2) -+#define fld_V_ACTIVE_START_def (uint32_t) ((22-4)*2+1) -+#define fld_V_ACTIVE_END_def (uint32_t) ((22+240-4)*2+2) - --#define fld_CH_HEIGHT_def (CARD32) 0x000000CD --#define fld_CH_KILL_LEVEL_def (CARD32) 0x000000C0 --#define fld_CH_AGC_ERROR_LIM_def (CARD32) 0x00000002 --#define fld_CH_AGC_FILTER_EN_def (CARD32) 0x00000000 --#define fld_CH_AGC_LOOP_SPEED_def (CARD32) 0x00000000 -+#define fld_CH_HEIGHT_def (uint32_t) 0x000000CD -+#define fld_CH_KILL_LEVEL_def (uint32_t) 0x000000C0 -+#define fld_CH_AGC_ERROR_LIM_def (uint32_t) 0x00000002 -+#define fld_CH_AGC_FILTER_EN_def (uint32_t) 0x00000000 -+#define fld_CH_AGC_LOOP_SPEED_def (uint32_t) 0x00000000 - --#define fld_HUE_ADJ_def (CARD32) 0x00000000 -+#define fld_HUE_ADJ_def (uint32_t) 0x00000000 - --#define fld_STANDARD_SEL_def (CARD32) 0x00000000 --#define fld_STANDARD_YC_def (CARD32) 0x00000000 -+#define fld_STANDARD_SEL_def (uint32_t) 0x00000000 -+#define fld_STANDARD_YC_def (uint32_t) 0x00000000 - --#define fld_ADC_PDWN_def (CARD32) 0x00000001 --#define fld_INPUT_SELECT_def (CARD32) 0x00000000 -+#define fld_ADC_PDWN_def (uint32_t) 0x00000001 -+#define fld_INPUT_SELECT_def (uint32_t) 0x00000000 - --#define fld_ADC_PREFLO_def (CARD32) 0x00000003 --#define fld_H_SYNC_PULSE_WIDTH_def (CARD32) 0x00000000 --#define fld_HS_GENLOCKED_def (CARD32) 0x00000000 --#define fld_HS_SYNC_IN_WIN_def (CARD32) 0x00000000 -+#define fld_ADC_PREFLO_def (uint32_t) 0x00000003 -+#define fld_H_SYNC_PULSE_WIDTH_def (uint32_t) 0x00000000 -+#define fld_HS_GENLOCKED_def (uint32_t) 0x00000000 -+#define fld_HS_SYNC_IN_WIN_def (uint32_t) 0x00000000 - --#define fld_VIN_ASYNC_RST_def (CARD32) 0x00000001 --#define fld_DVS_ASYNC_RST_def (CARD32) 0x00000001 -+#define fld_VIN_ASYNC_RST_def (uint32_t) 0x00000001 -+#define fld_DVS_ASYNC_RST_def (uint32_t) 0x00000001 - - /* Vendor IDs: */ --#define fld_VIP_VENDOR_ID_def (CARD32) 0x00001002 --#define fld_VIP_DEVICE_ID_def (CARD32) 0x00004d54 --#define fld_VIP_REVISION_ID_def (CARD32) 0x00000001 -+#define fld_VIP_VENDOR_ID_def (uint32_t) 0x00001002 -+#define fld_VIP_DEVICE_ID_def (uint32_t) 0x00004d54 -+#define fld_VIP_REVISION_ID_def (uint32_t) 0x00000001 - - /* AGC Delay Register */ --#define fld_BLACK_INT_START_def (CARD32) 0x00000031 --#define fld_BLACK_INT_LENGTH_def (CARD32) 0x0000000f -+#define fld_BLACK_INT_START_def (uint32_t) 0x00000031 -+#define fld_BLACK_INT_LENGTH_def (uint32_t) 0x0000000f - --#define fld_UV_INT_START_def (CARD32) 0x0000003b --#define fld_U_INT_LENGTH_def (CARD32) 0x0000000f --#define fld_V_INT_LENGTH_def (CARD32) 0x0000000f --#define fld_CRDR_ACTIVE_GAIN_def (CARD32) 0x0000007a --#define fld_CBDB_ACTIVE_GAIN_def (CARD32) 0x000000ac -+#define fld_UV_INT_START_def (uint32_t) 0x0000003b -+#define fld_U_INT_LENGTH_def (uint32_t) 0x0000000f -+#define fld_V_INT_LENGTH_def (uint32_t) 0x0000000f -+#define fld_CRDR_ACTIVE_GAIN_def (uint32_t) 0x0000007a -+#define fld_CBDB_ACTIVE_GAIN_def (uint32_t) 0x000000ac - --#define fld_DVS_DIRECTION_def (CARD32) 0x00000000 --#define fld_DVS_VBI_CARD8_SWAP_def (CARD32) 0x00000000 --#define fld_DVS_CLK_SELECT_def (CARD32) 0x00000000 --#define fld_CONTINUOUS_STREAM_def (CARD32) 0x00000000 --#define fld_DVSOUT_CLK_DRV_def (CARD32) 0x00000001 --#define fld_DVSOUT_DATA_DRV_def (CARD32) 0x00000001 -+#define fld_DVS_DIRECTION_def (uint32_t) 0x00000000 -+#define fld_DVS_VBI_UINT8_SWAP_def (uint32_t) 0x00000000 -+#define fld_DVS_CLK_SELECT_def (uint32_t) 0x00000000 -+#define fld_CONTINUOUS_STREAM_def (uint32_t) 0x00000000 -+#define fld_DVSOUT_CLK_DRV_def (uint32_t) 0x00000001 -+#define fld_DVSOUT_DATA_DRV_def (uint32_t) 0x00000001 - --#define fld_COMB_CNTL0_def (CARD32) 0x09438090 --#define fld_COMB_CNTL1_def (CARD32) 0x00000010 -+#define fld_COMB_CNTL0_def (uint32_t) 0x09438090 -+#define fld_COMB_CNTL1_def (uint32_t) 0x00000010 - --#define fld_COMB_CNTL2_def (CARD32) 0x16161010 --#define fld_COMB_LENGTH_def (CARD32) 0x0718038A -+#define fld_COMB_CNTL2_def (uint32_t) 0x16161010 -+#define fld_COMB_LENGTH_def (uint32_t) 0x0718038A - --#define fld_SYNCTIP_REF0_def (CARD32) 0x00000037 --#define fld_SYNCTIP_REF1_def (CARD32) 0x00000029 --#define fld_CLAMP_REF_def (CARD32) 0x0000003B --#define fld_AGC_PEAKWHITE_def (CARD32) 0x000000FF --#define fld_VBI_PEAKWHITE_def (CARD32) 0x000000D2 -+#define fld_SYNCTIP_REF0_def (uint32_t) 0x00000037 -+#define fld_SYNCTIP_REF1_def (uint32_t) 0x00000029 -+#define fld_CLAMP_REF_def (uint32_t) 0x0000003B -+#define fld_AGC_PEAKWHITE_def (uint32_t) 0x000000FF -+#define fld_VBI_PEAKWHITE_def (uint32_t) 0x000000D2 - --#define fld_WPA_THRESHOLD_def (CARD32) 0x000003B0 -+#define fld_WPA_THRESHOLD_def (uint32_t) 0x000003B0 - --#define fld_WPA_TRIGGER_LO_def (CARD32) 0x000000B4 --#define fld_WPA_TRIGGER_HIGH_def (CARD32) 0x0000021C -+#define fld_WPA_TRIGGER_LO_def (uint32_t) 0x000000B4 -+#define fld_WPA_TRIGGER_HIGH_def (uint32_t) 0x0000021C - --#define fld_LOCKOUT_START_def (CARD32) 0x00000206 --#define fld_LOCKOUT_END_def (CARD32) 0x00000021 -+#define fld_LOCKOUT_START_def (uint32_t) 0x00000206 -+#define fld_LOCKOUT_END_def (uint32_t) 0x00000021 - --#define fld_CH_DTO_INC_def (CARD32) 0x00400000 --#define fld_PLL_SGAIN_def (CARD32) 0x00000001 --#define fld_PLL_FGAIN_def (CARD32) 0x00000002 -+#define fld_CH_DTO_INC_def (uint32_t) 0x00400000 -+#define fld_PLL_SGAIN_def (uint32_t) 0x00000001 -+#define fld_PLL_FGAIN_def (uint32_t) 0x00000002 - --#define fld_CR_BURST_GAIN_def (CARD32) 0x0000007a --#define fld_CB_BURST_GAIN_def (CARD32) 0x000000ac -+#define fld_CR_BURST_GAIN_def (uint32_t) 0x0000007a -+#define fld_CB_BURST_GAIN_def (uint32_t) 0x000000ac - --#define fld_VERT_LOCKOUT_START_def (CARD32) 0x00000207 --#define fld_VERT_LOCKOUT_END_def (CARD32) 0x0000000E -+#define fld_VERT_LOCKOUT_START_def (uint32_t) 0x00000207 -+#define fld_VERT_LOCKOUT_END_def (uint32_t) 0x0000000E - --#define fld_H_IN_WIND_START_def (CARD32) 0x00000070 --#define fld_V_IN_WIND_START_def (CARD32) 0x00000027 -+#define fld_H_IN_WIND_START_def (uint32_t) 0x00000070 -+#define fld_V_IN_WIND_START_def (uint32_t) 0x00000027 - --#define fld_H_OUT_WIND_WIDTH_def (CARD32) 0x000002f4 -+#define fld_H_OUT_WIND_WIDTH_def (uint32_t) 0x000002f4 - --#define fld_V_OUT_WIND_WIDTH_def (CARD32) 0x000000f0 -+#define fld_V_OUT_WIND_WIDTH_def (uint32_t) 0x000000f0 - --#define fld_HS_LINE_TOTAL_def (CARD32) 0x0000038E -+#define fld_HS_LINE_TOTAL_def (uint32_t) 0x0000038E - --#define fld_MIN_PULSE_WIDTH_def (CARD32) 0x0000002F --#define fld_MAX_PULSE_WIDTH_def (CARD32) 0x00000046 -+#define fld_MIN_PULSE_WIDTH_def (uint32_t) 0x0000002F -+#define fld_MAX_PULSE_WIDTH_def (uint32_t) 0x00000046 - --#define fld_WIN_CLOSE_LIMIT_def (CARD32) 0x0000004D --#define fld_WIN_OPEN_LIMIT_def (CARD32) 0x000001B7 -+#define fld_WIN_CLOSE_LIMIT_def (uint32_t) 0x0000004D -+#define fld_WIN_OPEN_LIMIT_def (uint32_t) 0x000001B7 - --#define fld_VSYNC_INT_TRIGGER_def (CARD32) 0x000002AA -+#define fld_VSYNC_INT_TRIGGER_def (uint32_t) 0x000002AA - --#define fld_VSYNC_INT_HOLD_def (CARD32) 0x0000001D -+#define fld_VSYNC_INT_HOLD_def (uint32_t) 0x0000001D - --#define fld_VIN_M0_def (CARD32) 0x00000039 --#define fld_VIN_N0_def (CARD32) 0x0000014c --#define fld_MNFLIP_EN_def (CARD32) 0x00000000 --#define fld_VIN_P_def (CARD32) 0x00000006 --#define fld_REG_CLK_SEL_def (CARD32) 0x00000000 -+#define fld_VIN_M0_def (uint32_t) 0x00000039 -+#define fld_VIN_N0_def (uint32_t) 0x0000014c -+#define fld_MNFLIP_EN_def (uint32_t) 0x00000000 -+#define fld_VIN_P_def (uint32_t) 0x00000006 -+#define fld_REG_CLK_SEL_def (uint32_t) 0x00000000 - --#define fld_VIN_M1_def (CARD32) 0x00000000 --#define fld_VIN_N1_def (CARD32) 0x00000000 --#define fld_VIN_DRIVER_SEL_def (CARD32) 0x00000000 --#define fld_VIN_MNFLIP_REQ_def (CARD32) 0x00000000 --#define fld_VIN_MNFLIP_DONE_def (CARD32) 0x00000000 --#define fld_TV_LOCK_TO_VIN_def (CARD32) 0x00000000 --#define fld_TV_P_FOR_WINCLK_def (CARD32) 0x00000004 -+#define fld_VIN_M1_def (uint32_t) 0x00000000 -+#define fld_VIN_N1_def (uint32_t) 0x00000000 -+#define fld_VIN_DRIVER_SEL_def (uint32_t) 0x00000000 -+#define fld_VIN_MNFLIP_REQ_def (uint32_t) 0x00000000 -+#define fld_VIN_MNFLIP_DONE_def (uint32_t) 0x00000000 -+#define fld_TV_LOCK_TO_VIN_def (uint32_t) 0x00000000 -+#define fld_TV_P_FOR_WINCLK_def (uint32_t) 0x00000004 - --#define fld_VINRST_def (CARD32) 0x00000001 --#define fld_VIN_CLK_SEL_def (CARD32) 0x00000000 -+#define fld_VINRST_def (uint32_t) 0x00000001 -+#define fld_VIN_CLK_SEL_def (uint32_t) 0x00000000 - --#define fld_VS_FIELD_BLANK_START_def (CARD32) 0x00000206 -+#define fld_VS_FIELD_BLANK_START_def (uint32_t) 0x00000206 - --#define fld_VS_FIELD_BLANK_END_def (CARD32) 0x0000000A -+#define fld_VS_FIELD_BLANK_END_def (uint32_t) 0x0000000A - --/*#define fld_VS_FIELD_IDLOCATION_def (CARD32) 0x00000105 */ --#define fld_VS_FIELD_IDLOCATION_def (CARD32) 0x00000001 --#define fld_VS_FRAME_TOTAL_def (CARD32) 0x00000217 -+/*#define fld_VS_FIELD_IDLOCATION_def (uint32_t) 0x00000105 */ -+#define fld_VS_FIELD_IDLOCATION_def (uint32_t) 0x00000001 -+#define fld_VS_FRAME_TOTAL_def (uint32_t) 0x00000217 - --#define fld_SYNC_TIP_START_def (CARD32) 0x00000372 --#define fld_SYNC_TIP_LENGTH_def (CARD32) 0x0000000F -+#define fld_SYNC_TIP_START_def (uint32_t) 0x00000372 -+#define fld_SYNC_TIP_LENGTH_def (uint32_t) 0x0000000F - --#define fld_GAIN_FORCE_DATA_def (CARD32) 0x00000000 --#define fld_GAIN_FORCE_EN_def (CARD32) 0x00000000 --#define fld_I_CLAMP_SEL_def (CARD32) 0x00000003 --#define fld_I_AGC_SEL_def (CARD32) 0x00000001 --#define fld_EXT_CLAMP_CAP_def (CARD32) 0x00000001 --#define fld_EXT_AGC_CAP_def (CARD32) 0x00000001 --#define fld_DECI_DITHER_EN_def (CARD32) 0x00000001 --#define fld_ADC_PREFHI_def (CARD32) 0x00000000 --#define fld_ADC_CH_GAIN_SEL_def (CARD32) 0x00000001 -+#define fld_GAIN_FORCE_DATA_def (uint32_t) 0x00000000 -+#define fld_GAIN_FORCE_EN_def (uint32_t) 0x00000000 -+#define fld_I_CLAMP_SEL_def (uint32_t) 0x00000003 -+#define fld_I_AGC_SEL_def (uint32_t) 0x00000001 -+#define fld_EXT_CLAMP_CAP_def (uint32_t) 0x00000001 -+#define fld_EXT_AGC_CAP_def (uint32_t) 0x00000001 -+#define fld_DECI_DITHER_EN_def (uint32_t) 0x00000001 -+#define fld_ADC_PREFHI_def (uint32_t) 0x00000000 -+#define fld_ADC_CH_GAIN_SEL_def (uint32_t) 0x00000001 - --#define fld_HS_PLL_SGAIN_def (CARD32) 0x00000003 -+#define fld_HS_PLL_SGAIN_def (uint32_t) 0x00000003 - --#define fld_NREn_def (CARD32) 0x00000000 --#define fld_NRGainCntl_def (CARD32) 0x00000000 --#define fld_NRBWTresh_def (CARD32) 0x00000000 --#define fld_NRGCTresh_def (CARD32) 0x00000000 --#define fld_NRCoefDespeclMode_def (CARD32) 0x00000000 -+#define fld_NREn_def (uint32_t) 0x00000000 -+#define fld_NRGainCntl_def (uint32_t) 0x00000000 -+#define fld_NRBWTresh_def (uint32_t) 0x00000000 -+#define fld_NRGCTresh_def (uint32_t) 0x00000000 -+#define fld_NRCoefDespeclMode_def (uint32_t) 0x00000000 - --#define fld_GPIO_5_OE_def (CARD32) 0x00000000 --#define fld_GPIO_6_OE_def (CARD32) 0x00000000 -+#define fld_GPIO_5_OE_def (uint32_t) 0x00000000 -+#define fld_GPIO_6_OE_def (uint32_t) 0x00000000 - --#define fld_GPIO_5_OUT_def (CARD32) 0x00000000 --#define fld_GPIO_6_OUT_def (CARD32) 0x00000000 -+#define fld_GPIO_5_OUT_def (uint32_t) 0x00000000 -+#define fld_GPIO_6_OUT_def (uint32_t) 0x00000000 - - /* End of field default values. */ - diff --git a/radeon-modeset.patch b/radeon-modeset.patch index 1c3764a..9da719e 100644 --- a/radeon-modeset.patch +++ b/radeon-modeset.patch @@ -807,7 +807,7 @@ index 0000000..59e6307 +#endif +#endif diff --git a/src/radeon.h b/src/radeon.h -index 8f25fdf..c766d79 100644 +index 63655b8..bcca356 100644 --- a/src/radeon.h +++ b/src/radeon.h @@ -46,6 +46,8 @@ @@ -923,7 +923,7 @@ index 8f25fdf..c766d79 100644 } RADEONInfoRec, *RADEONInfoPtr; #define RADEONWaitForFifo(pScrn, entries) \ -@@ -1033,6 +1095,21 @@ extern void RADEONUpdateHVPosition(xf86OutputPtr output, DisplayModePtr mode); +@@ -1036,6 +1098,21 @@ extern void RADEONUpdateHVPosition(xf86OutputPtr output, DisplayModePtr mode); extern void RADEONInitVideo(ScreenPtr pScreen); extern void RADEONResetVideo(ScrnInfoPtr pScrn); @@ -945,7 +945,7 @@ index 8f25fdf..c766d79 100644 #ifdef XF86DRI # ifdef USE_XAA /* radeon_accelfuncs.c */ -@@ -1051,7 +1128,9 @@ do { \ +@@ -1054,7 +1131,9 @@ do { \ #define RADEONCP_RELEASE(pScrn, info) \ do { \ @@ -956,7 +956,7 @@ index 8f25fdf..c766d79 100644 RADEON_PURGE_CACHE(); \ RADEON_WAIT_UNTIL_IDLE(); \ RADEONCPReleaseIndirect(pScrn); \ -@@ -1085,7 +1164,7 @@ do { \ +@@ -1088,7 +1167,7 @@ do { \ #define RADEONCP_REFRESH(pScrn, info) \ do { \ @@ -965,7 +965,7 @@ index 8f25fdf..c766d79 100644 if (info->needCacheFlush) { \ RADEON_PURGE_CACHE(); \ RADEON_PURGE_ZCACHE(); \ -@@ -1124,6 +1203,13 @@ do { \ +@@ -1127,6 +1206,13 @@ do { \ #define RING_LOCALS uint32_t *__head = NULL; int __expected; int __count = 0 #define BEGIN_RING(n) do { \ @@ -979,7 +979,7 @@ index 8f25fdf..c766d79 100644 if (RADEON_VERBOSE) { \ xf86DrvMsg(pScrn->scrnIndex, X_INFO, \ "BEGIN_RING(%d) in %s\n", (unsigned int)n, __FUNCTION__);\ -@@ -1136,13 +1222,6 @@ do { \ +@@ -1139,13 +1225,6 @@ do { \ } \ info->dma_debug_func = __FILE__; \ info->dma_debug_lineno = __LINE__; \ @@ -993,7 +993,7 @@ index 8f25fdf..c766d79 100644 __expected = n; \ __head = (pointer)((char *)info->indirectBuffer->address + \ info->indirectBuffer->used); \ -@@ -1185,6 +1264,17 @@ do { \ +@@ -1188,6 +1267,17 @@ do { \ OUT_RING(val); \ } while (0) @@ -2248,7 +2248,7 @@ index a192811..c834280 100644 + +} diff --git a/src/radeon_driver.c b/src/radeon_driver.c -index 010f1b9..fa0befa 100644 +index 45d2c2f..bfb3c54 100644 --- a/src/radeon_driver.c +++ b/src/radeon_driver.c @@ -1621,7 +1621,10 @@ static Bool RADEONPreInitVRAM(ScrnInfoPtr pScrn) @@ -2804,8 +2804,7 @@ index 010f1b9..fa0befa 100644 - goto fail; - } + info->drmmode.create_new_fb = radeon_create_new_fb; - -- ErrorF("after xf86InitialConfiguration\n"); ++ + info->drmFD = info->drmmode.fd; + xfree(bus_id); + @@ -2824,7 +2823,8 @@ index 010f1b9..fa0befa 100644 + { + drmRadeonGetParam gp; + int value; -+ + +- ErrorF("after xf86InitialConfiguration\n"); + memset(&gp, 0, sizeof(gp)); + gp.param = RADEON_PARAM_FB_LOCATION; + gp.value = &value; @@ -3109,51 +3109,18 @@ index 010f1b9..fa0befa 100644 } xf86DrvMsg(pScrn->scrnIndex, X_INFO, "Direct rendering enabled\n"); -@@ -5392,73 +5538,83 @@ Bool RADEONEnterVT(int scrnIndex, int flags) +@@ -5390,7 +5536,8 @@ Bool RADEONEnterVT(int scrnIndex, int flags) xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG, "RADEONEnterVT\n"); -- if (info->ChipFamily >= CHIP_FAMILY_R600) -- mem_size = INREG(R600_CONFIG_MEMSIZE); -- else -- mem_size = INREG(RADEON_CONFIG_MEMSIZE); -- -- if (mem_size == 0) { /* Softboot V_BIOS */ -- if (info->IsAtomBios) { -- rhdAtomASICInit(info->atomBIOS); -+ if (!info->drm_mode_setting) { -+ if (info->ChipFamily >= CHIP_FAMILY_R600) -+ mem_size = INREG(R600_CONFIG_MEMSIZE); -+ else -+ mem_size = INREG(RADEON_CONFIG_MEMSIZE); -+ -+ if (mem_size == 0) { /* Softboot V_BIOS */ -+ if (info->IsAtomBios) { -+ rhdAtomASICInit(info->atomBIOS); +- if (!radeon_card_posted(pScrn)) { /* Softboot V_BIOS */ ++ /* Softboot V_BIOS */ ++ if (!info->drm_mode_setting && !radeon_card_posted(pScrn)) { + if (info->IsAtomBios) { + rhdAtomASICInit(info->atomBIOS); } else { -- xf86Int10InfoPtr pInt; -- xf86DrvMsg(pScrn->scrnIndex, X_WARNING, -- "zero MEMSIZE, probably at D3cold. Re-POSTing via int10.\n"); -- pInt = xf86InitInt10 (info->pEnt->index); -- if (pInt) { -- pInt->num = 0xe6; -- xf86ExecX86int10 (pInt); -- xf86FreeInt10 (pInt); -- } else { -- RADEONGetBIOSInitTableOffsets(pScrn); -- RADEONPostCardFromBIOSTables(pScrn); -+ xf86Int10InfoPtr pInt; -+ xf86DrvMsg(pScrn->scrnIndex, X_WARNING, -+ "zero MEMSIZE, probably at D3cold. Re-POSTing via int10.\n"); -+ pInt = xf86InitInt10 (info->pEnt->index); -+ if (pInt) { -+ pInt->num = 0xe6; -+ xf86ExecX86int10 (pInt); -+ xf86FreeInt10 (pInt); -+ } else { -+ RADEONGetBIOSInitTableOffsets(pScrn); -+ RADEONPostCardFromBIOSTables(pScrn); -+ } +@@ -5406,51 +5553,59 @@ Bool RADEONEnterVT(int scrnIndex, int flags) + RADEONPostCardFromBIOSTables(pScrn); } } - } @@ -3245,7 +3212,7 @@ index 010f1b9..fa0befa 100644 } #endif /* this will get XVideo going again, but only if XVideo was initialised -@@ -5470,7 +5626,7 @@ Bool RADEONEnterVT(int scrnIndex, int flags) +@@ -5462,7 +5617,7 @@ Bool RADEONEnterVT(int scrnIndex, int flags) RADEONEngineRestore(pScrn); #ifdef XF86DRI @@ -3254,7 +3221,7 @@ index 010f1b9..fa0befa 100644 RADEONCP_START(pScrn, info); DRIUnlock(pScrn->pScreen); } -@@ -5493,24 +5649,26 @@ void RADEONLeaveVT(int scrnIndex, int flags) +@@ -5485,24 +5640,26 @@ void RADEONLeaveVT(int scrnIndex, int flags) "RADEONLeaveVT\n"); #ifdef XF86DRI if (RADEONPTR(pScrn)->directRenderingInited) { @@ -3294,7 +3261,7 @@ index 010f1b9..fa0befa 100644 i = 0; -@@ -5539,10 +5697,15 @@ void RADEONLeaveVT(int scrnIndex, int flags) +@@ -5531,10 +5688,15 @@ void RADEONLeaveVT(int scrnIndex, int flags) xf86_hide_cursors (pScrn); @@ -3313,7 +3280,7 @@ index 010f1b9..fa0befa 100644 xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG, "Ok, leaving now...\n"); -@@ -5587,7 +5750,8 @@ static Bool RADEONCloseScreen(int scrnIndex, ScreenPtr pScreen) +@@ -5579,7 +5741,8 @@ static Bool RADEONCloseScreen(int scrnIndex, ScreenPtr pScreen) #endif /* USE_XAA */ if (pScrn->vtSema) { @@ -3323,7 +3290,7 @@ index 010f1b9..fa0befa 100644 } xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG, -@@ -5622,6 +5786,12 @@ static Bool RADEONCloseScreen(int scrnIndex, ScreenPtr pScreen) +@@ -5614,6 +5777,12 @@ static Bool RADEONCloseScreen(int scrnIndex, ScreenPtr pScreen) info->DGAModes = NULL; xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG, "Unmapping memory\n"); @@ -3925,7 +3892,7 @@ index 56de23e..75c8f46 100644 ) { xf86DrvMsg(pScrn->scrnIndex, X_INFO, "Render acceleration " diff --git a/src/radeon_exa_render.c b/src/radeon_exa_render.c -index 4736e4f..fe9d1a9 100644 +index 5d28d80..1c4b92c 100644 --- a/src/radeon_exa_render.c +++ b/src/radeon_exa_render.c @@ -410,19 +410,22 @@ static Bool FUNC_NAME(R100TextureSetup)(PicturePtr pPict, PixmapPtr pPix, @@ -4456,11 +4423,11 @@ index 0000000..b30a68d + + diff --git a/src/radeon_probe.h b/src/radeon_probe.h -index 944ab9f..59f7f95 100644 +index 3770abf..e14c280 100644 --- a/src/radeon_probe.h +++ b/src/radeon_probe.h -@@ -178,6 +178,26 @@ typedef struct - uint32_t get_data_mask; +@@ -182,6 +182,26 @@ typedef struct + uint32_t a_data_mask; } RADEONI2CBusRec, *RADEONI2CBusPtr; +struct radeon_memory { @@ -4486,7 +4453,7 @@ index 944ab9f..59f7f95 100644 typedef struct _RADEONCrtcPrivateRec { #ifdef USE_XAA FBLinearPtr rotate_mem_xaa; -@@ -194,6 +214,8 @@ typedef struct _RADEONCrtcPrivateRec { +@@ -198,6 +218,8 @@ typedef struct _RADEONCrtcPrivateRec { uint32_t crtc_offset; int can_tile; Bool enabled; @@ -4577,7 +4544,7 @@ index cfa349d..2ec4cc1 100644 else #endif diff --git a/src/radeon_textured_videofuncs.c b/src/radeon_textured_videofuncs.c -index 98dc9a4..ad8136d 100644 +index d39f74d..aaf54a0 100644 --- a/src/radeon_textured_videofuncs.c +++ b/src/radeon_textured_videofuncs.c @@ -82,19 +82,19 @@ FUNC_NAME(RADEONDisplayTexturedVideo)(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv diff --git a/sources b/sources index 02646cb..c96c796 100644 --- a/sources +++ b/sources @@ -1 +1 @@ -3c97c7925ebf4162eeb3463e23adc0e3 xf86-video-ati-6.8.0.tar.bz2 +afa4873f58ae6fa31fedeb9ed31531db xf86-video-ati-6.9.0.tar.bz2 diff --git a/xorg-x11-drv-ati.spec b/xorg-x11-drv-ati.spec index 192d27f..cc2da74 100644 --- a/xorg-x11-drv-ati.spec +++ b/xorg-x11-drv-ati.spec @@ -4,31 +4,18 @@ Summary: Xorg X11 ati video driver Name: xorg-x11-drv-ati -Version: 6.8.0 -Release: 21%{?dist} +Version: 6.9.0 +Release: 1%{?dist} URL: http://www.x.org License: MIT Group: User Interface/X Hardware Support BuildRoot: %{_tmppath}/%{name}-%{version}-%{release}-root-%(%{__id_u} -n) -Source0: ftp://ftp.x.org/pub/individual/driver/%{tarball}-%{version}.tar.bz2 -Source1: ati.xinf -Source2: r128.xinf +Source0: http://www.x.org/pub/individual/driver/%{tarball}-%{version}.tar.bz2 Source3: radeon.xinf -# Radeon patches (0-99) -Patch1: radeon-git-upstream-fixes.patch -Patch2: radeon-git-upstream-fixes2.patch +Patch0: radeon-6.9.0-to-git.patch Patch3: radeon-modeset.patch -Patch4: radeon-6.7.196-faster-ddc.patch - -# Rage 128 patches (100-199) -Patch100: r128-bios-size.patch - -# mach64 patches (200-299) -Patch200: mach64-ia64-pagesize.patch - -# ati wrapperloader patches (300-399) ExcludeArch: s390 s390x @@ -47,14 +34,8 @@ X.Org X11 ati video driver. %prep %setup -q -n %{tarball}-%{version} - -%patch1 -p1 -b .git -%patch2 -p1 -b .git2 +%patch0 -p1 -b .git %patch3 -p1 -b .modeset -#patch4 -p1 -b .ddc - -%patch100 -p1 -b .r128-bios -%patch200 -p1 -b .mach64-ia64 %build autoreconf @@ -78,22 +59,20 @@ rm -rf $RPM_BUILD_ROOT %files %defattr(-,root,root,-) -%doc README.ati README.r128 %{driverdir}/ati_drv.so -%{driverdir}/mach64_drv.so -%{driverdir}/r128_drv.so %{driverdir}/radeon_drv.so -%{_datadir}/hwdata/videoaliases/ati.xinf -%{_datadir}/hwdata/videoaliases/r128.xinf %{_datadir}/hwdata/videoaliases/radeon.xinf %{moduledir}/multimedia/theatre200_drv.so %{moduledir}/multimedia/theatre_detect_drv.so %{moduledir}/multimedia/theatre_drv.so -%{_mandir}/man4/ati.4* -%{_mandir}/man4/r128.4* %{_mandir}/man4/radeon.4* %changelog +* Sun Aug 10 2008 Adam Jackson 6.9.0-1 +- Move to 6.9.0, now that the r128 and mach64 drivers are split out. +- Add git fixes since 6.9.0. +- Rebase the modesetting patch onto git master. + * Wed Aug 06 2008 Dave Airlie 6.8.0-21 - bunch of fixes to modesetting code + remove debugging.